Callisto4Bootloader: SysTick Functions

Callisto4Bootloader

Modules | Variables
SysTick Functions
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions » | Functions and Instructions Reference » NVIC Functions » FPU Functions » SAU Functions Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions » | Functions and Instructions Reference » NVIC Functions » FPU Functions » | Cache Functions

Functions that configure the System. More...

## Modules

| ITM Functions
| Functions that access the ITM debug interface.

## Variables

uint32_t APSR_Type::_reserved0:28
uint32_t APSR_Type::V:1
uint32_t APSR_Type::C:1
uint32_t APSR_Type::Z:1
uint32_t APSR_Type::N:1
struct {
uint32_t APSR_Type::_reserved0:28
uint32_t APSR_Type::V:1
uint32_t APSR_Type::C:1
uint32_t APSR_Type::Z:1
uint32_t APSR_Type::N:1
} | APSR_Type::b
uint32_t IPSR_Type::ISR:9
uint32_t IPSR_Type::_reserved0:23
struct {
uint32_t IPSR_Type::ISR:9
uint32_t IPSR_Type::_reserved0:23
} | IPSR_Type::b
uint32_t xPSR_Type::ISR:9
uint32_t xPSR_Type::_reserved0:15
uint32_t xPSR_Type::T:1
uint32_t xPSR_Type::_reserved1:3
uint32_t xPSR_Type::V:1
uint32_t xPSR_Type::C:1
uint32_t xPSR_Type::Z:1
uint32_t xPSR_Type::N:1
struct {
uint32_t xPSR_Type::ISR:9
uint32_t xPSR_Type::_reserved0:15
uint32_t xPSR_Type::T:1
uint32_t xPSR_Type::_reserved1:3
uint32_t xPSR_Type::V:1
uint32_t xPSR_Type::C:1
uint32_t xPSR_Type::Z:1
uint32_t xPSR_Type::N:1
} | xPSR_Type::b
uint32_t CONTROL_Type::nPRIV:1
uint32_t CONTROL_Type::SPSEL:1
uint32_t CONTROL_Type::_reserved1:30
struct {
uint32_t CONTROL_Type::nPRIV:1
uint32_t CONTROL_Type::SPSEL:1
uint32_t CONTROL_Type::_reserved1:30
} | CONTROL_Type::b
__IOM uint32_t | NVIC_Type::IPR [124U]
uint32_t | SCB_Type::RESERVED0
uint32_t | SCB_Type::RESERVED1
__IOM uint32_t | SCB_Type::SHPR [2U]
uint32_t | DWT_Type::RESERVED0 [6U]
__IOM uint32_t | TPI_Type::PSCR
__OM uint32_t | TPI_Type::LAR
__IM uint32_t | TPI_Type::LSR
__IM uint32_t | TPI_Type::TYPE

## Detailed Description

Functions that configure the System.

## Variable Documentation

## ◆ _reserved0 [1/3]

uint32_t { ... } ::_reserved0

bit: 0..27 Reserved

Definition at line 235 of file core_armv8mbl.h.

## ◆ _reserved0 [2/3]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 266 of file core_armv8mbl.h.

## ◆ _reserved0 [3/3]

uint32_t { ... } ::_reserved0

bit: 9..23 Reserved

Definition at line 284 of file core_armv8mbl.h.

## ◆ _reserved1 [1/2]

uint32_t { ... } ::_reserved1

bit: 25..27 Reserved

Definition at line 286 of file core_armv8mbl.h.

## ◆ _reserved1 [2/2]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 324 of file core_armv8mbl.h.

## ◆ b [1/4]

struct { ... } APSR_Type::b

Structure used for bit access

## ◆ b [2/4]

struct { ... } IPSR_Type::b

Structure used for bit access

## ◆ b [3/4]

struct { ... } xPSR_Type::b

Structure used for bit access

## ◆ b [4/4]

struct { ... } CONTROL_Type::b

Structure used for bit access

## ◆ C [1/2]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 237 of file core_armv8mbl.h.

## ◆ C [2/2]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 288 of file core_armv8mbl.h.

## ◆ IPR

__IOM uint32_t NVIC_Type::IPR[124U]

Offset: 0x300 (R/W) Interrupt Priority Register

Definition at line 363 of file core_armv8mbl.h.

## ◆ ISR [1/2]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 265 of file core_armv8mbl.h.

## ◆ ISR [2/2]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 283 of file core_armv8mbl.h.

## ◆ LAR

__OM uint32_t TPI_Type::LAR

Offset: 0xFB0 ( /W) Software Lock Access Register

Definition at line 736 of file core_armv8mbl.h.

## ◆ LSR

__IM uint32_t TPI_Type::LSR

Offset: 0xFB4 (R/ ) Software Lock Status Register

Definition at line 737 of file core_armv8mbl.h.

## ◆ N [1/2]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 239 of file core_armv8mbl.h.

## ◆ N [2/2]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 290 of file core_armv8mbl.h.

## ◆ nPRIV

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 322 of file core_armv8mbl.h.

## ◆ PSCR

__IOM uint32_t TPI_Type::PSCR

Offset: 0x308 (R/W) Periodic Synchronization Control Register

Definition at line 734 of file core_armv8mbl.h.

## ◆ RESERVED0 [1/2]

uint32_t DWT_Type::RESERVED0

Definition at line 611 of file core_armv8mbl.h.

## ◆ RESERVED0 [2/2]

uint32_t SCB_Type::RESERVED0

Definition at line 386 of file core_armv8mbl.h.

## ◆ RESERVED1

uint32_t SCB_Type::RESERVED1

Definition at line 391 of file core_armv8mbl.h.

## ◆ SHPR

__IOM uint32_t SCB_Type::SHPR[2U]

Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED

Definition at line 392 of file core_armv8mbl.h.

## ◆ SPSEL

uint32_t { ... } ::SPSEL

bit: 1 Stack-pointer select

Definition at line 323 of file core_armv8mbl.h.

## ◆ T

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 285 of file core_armv8mbl.h.

## ◆ TYPE

__IM uint32_t TPI_Type::TYPE

Offset: 0xFC8 (R/ ) Device Identifier Register

Definition at line 739 of file core_armv8mbl.h.

## ◆ V [1/2]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 236 of file core_armv8mbl.h.

## ◆ V [2/2]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 287 of file core_armv8mbl.h.

## ◆ Z [1/2]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 238 of file core_armv8mbl.h.

## ◆ Z [2/2]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 289 of file core_armv8mbl.h.