Callisto4Bootloader: Globals

Callisto4Bootloader

### - l -

- LCDIF : MIMXRT1062.h
- LCDIF_BASE : MIMXRT1062.h
- LCDIF_BASE_ADDRS : MIMXRT1062.h
- LCDIF_BASE_PTRS : MIMXRT1062.h
- LCDIF_BM_ERROR_STAT_ADDR : MIMXRT1062.h
- LCDIF_BM_ERROR_STAT_ADDR_MASK : MIMXRT1062.h
- LCDIF_BM_ERROR_STAT_ADDR_SHIFT : MIMXRT1062.h
- LCDIF_CRC_STAT_CRC_VALUE : MIMXRT1062.h
- LCDIF_CRC_STAT_CRC_VALUE_MASK : MIMXRT1062.h
- LCDIF_CRC_STAT_CRC_VALUE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_BM_ERROR_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_BM_ERROR_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_BM_ERROR_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_BYTE_PACKING_FORMAT : MIMXRT1062.h
- LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BM_ERROR_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CS_OUT_SELECT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_FIFO_CLEAR : MIMXRT1062.h
- LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_INTERLACE_FIELDS : MIMXRT1062.h
- LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS : MIMXRT1062.h
- LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_OVERFLOW_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW : MIMXRT1062.h
- LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL1_CLR_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD : MIMXRT1062.h
- LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_UNDERFLOW_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CS_OUT_SELECT : MIMXRT1062.h
- LCDIF_CTRL1_CS_OUT_SELECT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CS_OUT_SELECT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CUR_FRAME_DONE_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_FIFO_CLEAR : MIMXRT1062.h
- LCDIF_CTRL1_FIFO_CLEAR_MASK : MIMXRT1062.h
- LCDIF_CTRL1_FIFO_CLEAR_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_IMAGE_DATA_SELECT : MIMXRT1062.h
- LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_INTERLACE_FIELDS : MIMXRT1062.h
- LCDIF_CTRL1_INTERLACE_FIELDS_MASK : MIMXRT1062.h
- LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS : MIMXRT1062.h
- LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK : MIMXRT1062.h
- LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_OVERFLOW_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_OVERFLOW_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_OVERFLOW_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_RECOVER_ON_UNDERFLOW : MIMXRT1062.h
- LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK : MIMXRT1062.h
- LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL1_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL1_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_BM_ERROR_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT : MIMXRT1062.h
- LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_CS_OUT_SELECT : MIMXRT1062.h
- LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_FIFO_CLEAR : MIMXRT1062.h
- LCDIF_CTRL1_SET_FIFO_CLEAR_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_IMAGE_DATA_SELECT : MIMXRT1062.h
- LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_INTERLACE_FIELDS : MIMXRT1062.h
- LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS : MIMXRT1062.h
- LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_OVERFLOW_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW : MIMXRT1062.h
- LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL1_SET_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD : MIMXRT1062.h
- LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_UNDERFLOW_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD : MIMXRT1062.h
- LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK : MIMXRT1062.h
- LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BM_ERROR_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CS_OUT_SELECT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_FIFO_CLEAR : MIMXRT1062.h
- LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_INTERLACE_FIELDS : MIMXRT1062.h
- LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS : MIMXRT1062.h
- LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_OVERFLOW_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW : MIMXRT1062.h
- LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL1_TOG_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD : MIMXRT1062.h
- LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_UNDERFLOW_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_UNDERFLOW_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_UNDERFLOW_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_UNDERFLOW_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_VSYNC_EDGE_IRQ : MIMXRT1062.h
- LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN : MIMXRT1062.h
- LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK : MIMXRT1062.h
- LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK : MIMXRT1062.h
- LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_BURST_LEN_8 : MIMXRT1062.h
- LCDIF_CTRL2_BURST_LEN_8_MASK : MIMXRT1062.h
- LCDIF_CTRL2_BURST_LEN_8_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_CLR_BURST_LEN_8 : MIMXRT1062.h
- LCDIF_CTRL2_CLR_BURST_LEN_8_MASK : MIMXRT1062.h
- LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN : MIMXRT1062.h
- LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK : MIMXRT1062.h
- LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_CLR_ODD_LINE_PATTERN : MIMXRT1062.h
- LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK : MIMXRT1062.h
- LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_CLR_OUTSTANDING_REQS : MIMXRT1062.h
- LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK : MIMXRT1062.h
- LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD3 : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD3_MASK : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD3_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD4 : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD4_MASK : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD4_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD5 : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD5_MASK : MIMXRT1062.h
- LCDIF_CTRL2_CLR_RSRVD5_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_EVEN_LINE_PATTERN : MIMXRT1062.h
- LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK : MIMXRT1062.h
- LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_ODD_LINE_PATTERN : MIMXRT1062.h
- LCDIF_CTRL2_ODD_LINE_PATTERN_MASK : MIMXRT1062.h
- LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_OUTSTANDING_REQS : MIMXRT1062.h
- LCDIF_CTRL2_OUTSTANDING_REQS_MASK : MIMXRT1062.h
- LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD3 : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD3_MASK : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD3_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD4 : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD4_MASK : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD4_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD5 : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD5_MASK : MIMXRT1062.h
- LCDIF_CTRL2_RSRVD5_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_SET_BURST_LEN_8 : MIMXRT1062.h
- LCDIF_CTRL2_SET_BURST_LEN_8_MASK : MIMXRT1062.h
- LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_SET_EVEN_LINE_PATTERN : MIMXRT1062.h
- LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK : MIMXRT1062.h
- LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_SET_ODD_LINE_PATTERN : MIMXRT1062.h
- LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK : MIMXRT1062.h
- LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_SET_OUTSTANDING_REQS : MIMXRT1062.h
- LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK : MIMXRT1062.h
- LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD3 : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD3_MASK : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD3_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD4 : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD4_MASK : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD4_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD5 : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD5_MASK : MIMXRT1062.h
- LCDIF_CTRL2_SET_RSRVD5_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_TOG_BURST_LEN_8 : MIMXRT1062.h
- LCDIF_CTRL2_TOG_BURST_LEN_8_MASK : MIMXRT1062.h
- LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN : MIMXRT1062.h
- LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK : MIMXRT1062.h
- LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_TOG_ODD_LINE_PATTERN : MIMXRT1062.h
- LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK : MIMXRT1062.h
- LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_TOG_OUTSTANDING_REQS : MIMXRT1062.h
- LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK : MIMXRT1062.h
- LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD3 : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD3_MASK : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD3_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD4 : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD4_MASK : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD4_SHIFT : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD5 : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD5_MASK : MIMXRT1062.h
- LCDIF_CTRL2_TOG_RSRVD5_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_BYPASS_COUNT : MIMXRT1062.h
- LCDIF_CTRL_BYPASS_COUNT_MASK : MIMXRT1062.h
- LCDIF_CTRL_BYPASS_COUNT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLKGATE : MIMXRT1062.h
- LCDIF_CTRL_CLKGATE_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLKGATE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_BYPASS_COUNT : MIMXRT1062.h
- LCDIF_CTRL_CLR_BYPASS_COUNT_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_CLKGATE : MIMXRT1062.h
- LCDIF_CTRL_CLR_CLKGATE_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_CLKGATE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE : MIMXRT1062.h
- LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_SHIFT_DIR : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_DOTCLK_MODE : MIMXRT1062.h
- LCDIF_CTRL_CLR_DOTCLK_MODE_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE : MIMXRT1062.h
- LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE : MIMXRT1062.h
- LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH : MIMXRT1062.h
- LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_MASTER : MIMXRT1062.h
- LCDIF_CTRL_CLR_MASTER_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_MASTER_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL_CLR_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_RUN : MIMXRT1062.h
- LCDIF_CTRL_CLR_RUN_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_RUN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_SFTRST : MIMXRT1062.h
- LCDIF_CTRL_CLR_SFTRST_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_SFTRST_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_SHIFT_NUM_BITS : MIMXRT1062.h
- LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CLR_WORD_LENGTH : MIMXRT1062.h
- LCDIF_CTRL_CLR_WORD_LENGTH_MASK : MIMXRT1062.h
- LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_CSC_DATA_SWIZZLE : MIMXRT1062.h
- LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK : MIMXRT1062.h
- LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_16_BIT : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_18_BIT : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_24_BIT : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_DATA_SHIFT_DIR : MIMXRT1062.h
- LCDIF_CTRL_DATA_SHIFT_DIR_MASK : MIMXRT1062.h
- LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_DOTCLK_MODE : MIMXRT1062.h
- LCDIF_CTRL_DOTCLK_MODE_MASK : MIMXRT1062.h
- LCDIF_CTRL_DOTCLK_MODE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_ENABLE_PXP_HANDSHAKE : MIMXRT1062.h
- LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK : MIMXRT1062.h
- LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_INPUT_DATA_SWIZZLE : MIMXRT1062.h
- LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK : MIMXRT1062.h
- LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_LCD_DATABUS_WIDTH : MIMXRT1062.h
- LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK : MIMXRT1062.h
- LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_MASTER : MIMXRT1062.h
- LCDIF_CTRL_MASTER_MASK : MIMXRT1062.h
- LCDIF_CTRL_MASTER_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_RUN : MIMXRT1062.h
- LCDIF_CTRL_RUN_MASK : MIMXRT1062.h
- LCDIF_CTRL_RUN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_BYPASS_COUNT : MIMXRT1062.h
- LCDIF_CTRL_SET_BYPASS_COUNT_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_CLKGATE : MIMXRT1062.h
- LCDIF_CTRL_SET_CLKGATE_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_CLKGATE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_CSC_DATA_SWIZZLE : MIMXRT1062.h
- LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_16_BIT : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_18_BIT : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_24_BIT : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_SHIFT_DIR : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_DOTCLK_MODE : MIMXRT1062.h
- LCDIF_CTRL_SET_DOTCLK_MODE_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE : MIMXRT1062.h
- LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE : MIMXRT1062.h
- LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_LCD_DATABUS_WIDTH : MIMXRT1062.h
- LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_MASTER : MIMXRT1062.h
- LCDIF_CTRL_SET_MASTER_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_MASTER_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL_SET_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_RUN : MIMXRT1062.h
- LCDIF_CTRL_SET_RUN_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_RUN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_SFTRST : MIMXRT1062.h
- LCDIF_CTRL_SET_SFTRST_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_SFTRST_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_SHIFT_NUM_BITS : MIMXRT1062.h
- LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SET_WORD_LENGTH : MIMXRT1062.h
- LCDIF_CTRL_SET_WORD_LENGTH_MASK : MIMXRT1062.h
- LCDIF_CTRL_SET_WORD_LENGTH_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SFTRST : MIMXRT1062.h
- LCDIF_CTRL_SFTRST_MASK : MIMXRT1062.h
- LCDIF_CTRL_SFTRST_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_SHIFT_NUM_BITS : MIMXRT1062.h
- LCDIF_CTRL_SHIFT_NUM_BITS_MASK : MIMXRT1062.h
- LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_BYPASS_COUNT : MIMXRT1062.h
- LCDIF_CTRL_TOG_BYPASS_COUNT_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_CLKGATE : MIMXRT1062.h
- LCDIF_CTRL_TOG_CLKGATE_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_CLKGATE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE : MIMXRT1062.h
- LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_SHIFT_DIR : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_DOTCLK_MODE : MIMXRT1062.h
- LCDIF_CTRL_TOG_DOTCLK_MODE_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE : MIMXRT1062.h
- LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE : MIMXRT1062.h
- LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH : MIMXRT1062.h
- LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_MASTER : MIMXRT1062.h
- LCDIF_CTRL_TOG_MASTER_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_MASTER_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_RSRVD0 : MIMXRT1062.h
- LCDIF_CTRL_TOG_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_RUN : MIMXRT1062.h
- LCDIF_CTRL_TOG_RUN_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_RUN_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_SFTRST : MIMXRT1062.h
- LCDIF_CTRL_TOG_SFTRST_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_SFTRST_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_SHIFT_NUM_BITS : MIMXRT1062.h
- LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_TOG_WORD_LENGTH : MIMXRT1062.h
- LCDIF_CTRL_TOG_WORD_LENGTH_MASK : MIMXRT1062.h
- LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT : MIMXRT1062.h
- LCDIF_CTRL_WORD_LENGTH : MIMXRT1062.h
- LCDIF_CTRL_WORD_LENGTH_MASK : MIMXRT1062.h
- LCDIF_CTRL_WORD_LENGTH_SHIFT : MIMXRT1062.h
- LCDIF_CUR_BUF_ADDR : MIMXRT1062.h
- LCDIF_CUR_BUF_ADDR_MASK : MIMXRT1062.h
- LCDIF_CUR_BUF_ADDR_SHIFT : MIMXRT1062.h
- LCDIF_IRQ0_IRQS : MIMXRT1062.h
- LCDIF_LUT0_ADDR_ADDR : MIMXRT1062.h
- LCDIF_LUT0_ADDR_ADDR_MASK : MIMXRT1062.h
- LCDIF_LUT0_ADDR_ADDR_SHIFT : MIMXRT1062.h
- LCDIF_LUT0_DATA_DATA : MIMXRT1062.h
- LCDIF_LUT0_DATA_DATA_MASK : MIMXRT1062.h
- LCDIF_LUT0_DATA_DATA_SHIFT : MIMXRT1062.h
- LCDIF_LUT1_ADDR_ADDR : MIMXRT1062.h
- LCDIF_LUT1_ADDR_ADDR_MASK : MIMXRT1062.h
- LCDIF_LUT1_ADDR_ADDR_SHIFT : MIMXRT1062.h
- LCDIF_LUT1_DATA_DATA : MIMXRT1062.h
- LCDIF_LUT1_DATA_DATA_MASK : MIMXRT1062.h
- LCDIF_LUT1_DATA_DATA_SHIFT : MIMXRT1062.h
- LCDIF_LUT_CTRL_LUT_BYPASS : MIMXRT1062.h
- LCDIF_LUT_CTRL_LUT_BYPASS_MASK : MIMXRT1062.h
- LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT : MIMXRT1062.h
- LCDIF_NEXT_BUF_ADDR : MIMXRT1062.h
- LCDIF_NEXT_BUF_ADDR_MASK : MIMXRT1062.h
- LCDIF_NEXT_BUF_ADDR_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_0_COUNT : MIMXRT1062.h
- LCDIF_PIGEON_0_EN : MIMXRT1062.h
- LCDIF_PIGEON_0_EN_MASK : MIMXRT1062.h
- LCDIF_PIGEON_0_EN_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_0_INC_SEL : MIMXRT1062.h
- LCDIF_PIGEON_0_INC_SEL_MASK : MIMXRT1062.h
- LCDIF_PIGEON_0_INC_SEL_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_0_MASK_CNT : MIMXRT1062.h
- LCDIF_PIGEON_0_MASK_CNT_MASK : MIMXRT1062.h
- LCDIF_PIGEON_0_MASK_CNT_SEL : MIMXRT1062.h
- LCDIF_PIGEON_0_MASK_CNT_SEL_MASK : MIMXRT1062.h
- LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_0_MASK_CNT_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_0_OFFSET : MIMXRT1062.h
- LCDIF_PIGEON_0_OFFSET_MASK : MIMXRT1062.h
- LCDIF_PIGEON_0_OFFSET_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_0_POL : MIMXRT1062.h
- LCDIF_PIGEON_0_POL_MASK : MIMXRT1062.h
- LCDIF_PIGEON_0_POL_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_0_STATE_MASK : MIMXRT1062.h
- LCDIF_PIGEON_0_STATE_MASK_MASK : MIMXRT1062.h
- LCDIF_PIGEON_0_STATE_MASK_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_1_CLR_CNT : MIMXRT1062.h
- LCDIF_PIGEON_1_CLR_CNT_MASK : MIMXRT1062.h
- LCDIF_PIGEON_1_CLR_CNT_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_1_COUNT : MIMXRT1062.h
- LCDIF_PIGEON_1_SET_CNT : MIMXRT1062.h
- LCDIF_PIGEON_1_SET_CNT_MASK : MIMXRT1062.h
- LCDIF_PIGEON_1_SET_CNT_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_2_COUNT : MIMXRT1062.h
- LCDIF_PIGEON_2_RSVD : MIMXRT1062.h
- LCDIF_PIGEON_2_RSVD_MASK : MIMXRT1062.h
- LCDIF_PIGEON_2_RSVD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_2_SIG_ANOTHER : MIMXRT1062.h
- LCDIF_PIGEON_2_SIG_ANOTHER_MASK : MIMXRT1062.h
- LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT : MIMXRT1062.h
- LCDIF_PIGEON_2_SIG_LOGIC : MIMXRT1062.h
- LCDIF_PIGEON_2_SIG_LOGIC_MASK : MIMXRT1062.h
- LCDIF_PIGEON_2_SIG_LOGIC_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_CLR_FD_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_CLR_LD_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_FD_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_FD_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_LD_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_LD_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_SET_FD_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_SET_LD_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_TOG_FD_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_TOG_LD_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_PIGEON_DATA_EN : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK : MIMXRT1062.h
- LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT : MIMXRT1062.h
- LCDIF_STAT_DMA_REQ : MIMXRT1062.h
- LCDIF_STAT_DMA_REQ_MASK : MIMXRT1062.h
- LCDIF_STAT_DMA_REQ_SHIFT : MIMXRT1062.h
- LCDIF_STAT_LFIFO_COUNT : MIMXRT1062.h
- LCDIF_STAT_LFIFO_COUNT_MASK : MIMXRT1062.h
- LCDIF_STAT_LFIFO_COUNT_SHIFT : MIMXRT1062.h
- LCDIF_STAT_LFIFO_EMPTY : MIMXRT1062.h
- LCDIF_STAT_LFIFO_EMPTY_MASK : MIMXRT1062.h
- LCDIF_STAT_LFIFO_EMPTY_SHIFT : MIMXRT1062.h
- LCDIF_STAT_LFIFO_FULL : MIMXRT1062.h
- LCDIF_STAT_LFIFO_FULL_MASK : MIMXRT1062.h
- LCDIF_STAT_LFIFO_FULL_SHIFT : MIMXRT1062.h
- LCDIF_STAT_PRESENT : MIMXRT1062.h
- LCDIF_STAT_PRESENT_MASK : MIMXRT1062.h
- LCDIF_STAT_PRESENT_SHIFT : MIMXRT1062.h
- LCDIF_STAT_RSRVD0 : MIMXRT1062.h
- LCDIF_STAT_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_STAT_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_STAT_TXFIFO_EMPTY : MIMXRT1062.h
- LCDIF_STAT_TXFIFO_EMPTY_MASK : MIMXRT1062.h
- LCDIF_STAT_TXFIFO_EMPTY_SHIFT : MIMXRT1062.h
- LCDIF_STAT_TXFIFO_FULL : MIMXRT1062.h
- LCDIF_STAT_TXFIFO_FULL_MASK : MIMXRT1062.h
- LCDIF_STAT_TXFIFO_FULL_SHIFT : MIMXRT1062.h
- LCDIF_TRANSFER_COUNT_H_COUNT : MIMXRT1062.h
- LCDIF_TRANSFER_COUNT_H_COUNT_MASK : MIMXRT1062.h
- LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT : MIMXRT1062.h
- LCDIF_TRANSFER_COUNT_V_COUNT : MIMXRT1062.h
- LCDIF_TRANSFER_COUNT_V_COUNT_MASK : MIMXRT1062.h
- LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_DOTCLK_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_ENABLE_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_ENABLE_PRESENT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HALF_LINE : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HALF_LINE_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HALF_LINE_MODE : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HSYNC_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_RSRVD1 : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_RSRVD1_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_RSRVD2 : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_RSRVD2_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_DOTCLK_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_DOTCLK_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_DOTCLK_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_ENABLE_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_ENABLE_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_ENABLE_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_ENABLE_PRESENT : MIMXRT1062.h
- LCDIF_VDCTRL0_ENABLE_PRESENT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_HALF_LINE : MIMXRT1062.h
- LCDIF_VDCTRL0_HALF_LINE_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_HALF_LINE_MODE : MIMXRT1062.h
- LCDIF_VDCTRL0_HALF_LINE_MODE_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_HALF_LINE_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_HSYNC_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_HSYNC_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_HSYNC_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_RSRVD1 : MIMXRT1062.h
- LCDIF_VDCTRL0_RSRVD1_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_RSRVD1_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_RSRVD2 : MIMXRT1062.h
- LCDIF_VDCTRL0_RSRVD2_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_RSRVD2_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_DOTCLK_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_ENABLE_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_ENABLE_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_ENABLE_PRESENT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HALF_LINE : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HALF_LINE_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HALF_LINE_MODE : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HSYNC_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HSYNC_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_RSRVD1 : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_RSRVD1_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_RSRVD1_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_RSRVD2 : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_RSRVD2_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_RSRVD2_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_DOTCLK_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_ENABLE_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_ENABLE_PRESENT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HALF_LINE : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HALF_LINE_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HALF_LINE_MODE : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HSYNC_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_RSRVD1 : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_RSRVD1_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_RSRVD2 : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_RSRVD2_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_POL : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_POL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_POL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL1_VSYNC_PERIOD : MIMXRT1062.h
- LCDIF_VDCTRL1_VSYNC_PERIOD_MASK : MIMXRT1062.h
- LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL2_HSYNC_PERIOD : MIMXRT1062.h
- LCDIF_VDCTRL2_HSYNC_PERIOD_MASK : MIMXRT1062.h
- LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH : MIMXRT1062.h
- LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK : MIMXRT1062.h
- LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT : MIMXRT1062.h
- LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL3_MUX_SYNC_SIGNALS : MIMXRT1062.h
- LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK : MIMXRT1062.h
- LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL3_RSRVD0 : MIMXRT1062.h
- LCDIF_VDCTRL3_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_VDCTRL3_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL3_VERTICAL_WAIT_CNT : MIMXRT1062.h
- LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL3_VSYNC_ONLY : MIMXRT1062.h
- LCDIF_VDCTRL3_VSYNC_ONLY_MASK : MIMXRT1062.h
- LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL4_DOTCLK_DLY_SEL : MIMXRT1062.h
- LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK : MIMXRT1062.h
- LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT : MIMXRT1062.h
- LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK : MIMXRT1062.h
- LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL4_RSRVD0 : MIMXRT1062.h
- LCDIF_VDCTRL4_RSRVD0_MASK : MIMXRT1062.h
- LCDIF_VDCTRL4_RSRVD0_SHIFT : MIMXRT1062.h
- LCDIF_VDCTRL4_SYNC_SIGNALS_ON : MIMXRT1062.h
- LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK : MIMXRT1062.h
- LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT : MIMXRT1062.h
- LEARN_DDR : fsl_flexspi.h
- LEARN_SDR : fsl_flexspi.h
- LEDS_GPIO : c4_colours.c
- LOGIC_LED_OFF : board.h
- LOGIC_LED_ON : board.h
- LPI2C1 : MIMXRT1062.h
- LPI2C1_BASE : MIMXRT1062.h
- LPI2C2 : MIMXRT1062.h
- LPI2C2_BASE : MIMXRT1062.h
- LPI2C2_BAUDRATE : platform_eeprom.c
- LPI2C2_MASTER : platform_eeprom.c
- LPI2C3 : MIMXRT1062.h
- LPI2C3_BASE : MIMXRT1062.h
- LPI2C4 : MIMXRT1062.h
- LPI2C4_BASE : MIMXRT1062.h
- LPI2C_BASE_ADDRS : MIMXRT1062.h
- LPI2C_BASE_PTRS : MIMXRT1062.h
- LPI2C_CLOCK_SOURCE_DIVIDER : platform_eeprom.c
- LPI2C_CLOCK_SOURCE_SELECT : platform_eeprom.c
- LPI2C_IRQS : MIMXRT1062.h
- LPI2C_MASTER_CLOCK_FREQUENCY : platform_eeprom.c
- LPI2C_MCCR0_CLKHI : MIMXRT1062.h
- LPI2C_MCCR0_CLKHI_MASK : MIMXRT1062.h
- LPI2C_MCCR0_CLKHI_SHIFT : MIMXRT1062.h
- LPI2C_MCCR0_CLKLO : MIMXRT1062.h
- LPI2C_MCCR0_CLKLO_MASK : MIMXRT1062.h
- LPI2C_MCCR0_CLKLO_SHIFT : MIMXRT1062.h
- LPI2C_MCCR0_DATAVD : MIMXRT1062.h
- LPI2C_MCCR0_DATAVD_MASK : MIMXRT1062.h
- LPI2C_MCCR0_DATAVD_SHIFT : MIMXRT1062.h
- LPI2C_MCCR0_SETHOLD : MIMXRT1062.h
- LPI2C_MCCR0_SETHOLD_MASK : MIMXRT1062.h
- LPI2C_MCCR0_SETHOLD_SHIFT : MIMXRT1062.h
- LPI2C_MCCR1_CLKHI : MIMXRT1062.h
- LPI2C_MCCR1_CLKHI_MASK : MIMXRT1062.h
- LPI2C_MCCR1_CLKHI_SHIFT : MIMXRT1062.h
- LPI2C_MCCR1_CLKLO : MIMXRT1062.h
- LPI2C_MCCR1_CLKLO_MASK : MIMXRT1062.h
- LPI2C_MCCR1_CLKLO_SHIFT : MIMXRT1062.h
- LPI2C_MCCR1_DATAVD : MIMXRT1062.h
- LPI2C_MCCR1_DATAVD_MASK : MIMXRT1062.h
- LPI2C_MCCR1_DATAVD_SHIFT : MIMXRT1062.h
- LPI2C_MCCR1_SETHOLD : MIMXRT1062.h
- LPI2C_MCCR1_SETHOLD_MASK : MIMXRT1062.h
- LPI2C_MCCR1_SETHOLD_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR0_CIRFIFO : MIMXRT1062.h
- LPI2C_MCFGR0_CIRFIFO_MASK : MIMXRT1062.h
- LPI2C_MCFGR0_CIRFIFO_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR0_HREN : MIMXRT1062.h
- LPI2C_MCFGR0_HREN_MASK : MIMXRT1062.h
- LPI2C_MCFGR0_HREN_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR0_HRPOL : MIMXRT1062.h
- LPI2C_MCFGR0_HRPOL_MASK : MIMXRT1062.h
- LPI2C_MCFGR0_HRPOL_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR0_HRSEL : MIMXRT1062.h
- LPI2C_MCFGR0_HRSEL_MASK : MIMXRT1062.h
- LPI2C_MCFGR0_HRSEL_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR0_RDMO : MIMXRT1062.h
- LPI2C_MCFGR0_RDMO_MASK : MIMXRT1062.h
- LPI2C_MCFGR0_RDMO_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR1_AUTOSTOP : MIMXRT1062.h
- LPI2C_MCFGR1_AUTOSTOP_MASK : MIMXRT1062.h
- LPI2C_MCFGR1_AUTOSTOP_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR1_IGNACK : MIMXRT1062.h
- LPI2C_MCFGR1_IGNACK_MASK : MIMXRT1062.h
- LPI2C_MCFGR1_IGNACK_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR1_MATCFG : MIMXRT1062.h
- LPI2C_MCFGR1_MATCFG_MASK : MIMXRT1062.h
- LPI2C_MCFGR1_MATCFG_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR1_PINCFG : MIMXRT1062.h
- LPI2C_MCFGR1_PINCFG_MASK : MIMXRT1062.h
- LPI2C_MCFGR1_PINCFG_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR1_PRESCALE : MIMXRT1062.h
- LPI2C_MCFGR1_PRESCALE_MASK : MIMXRT1062.h
- LPI2C_MCFGR1_PRESCALE_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR1_TIMECFG : MIMXRT1062.h
- LPI2C_MCFGR1_TIMECFG_MASK : MIMXRT1062.h
- LPI2C_MCFGR1_TIMECFG_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR2_BUSIDLE : MIMXRT1062.h
- LPI2C_MCFGR2_BUSIDLE_MASK : MIMXRT1062.h
- LPI2C_MCFGR2_BUSIDLE_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR2_FILTSCL : MIMXRT1062.h
- LPI2C_MCFGR2_FILTSCL_MASK : MIMXRT1062.h
- LPI2C_MCFGR2_FILTSCL_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR2_FILTSDA : MIMXRT1062.h
- LPI2C_MCFGR2_FILTSDA_MASK : MIMXRT1062.h
- LPI2C_MCFGR2_FILTSDA_SHIFT : MIMXRT1062.h
- LPI2C_MCFGR3_PINLOW : MIMXRT1062.h
- LPI2C_MCFGR3_PINLOW_MASK : MIMXRT1062.h
- LPI2C_MCFGR3_PINLOW_SHIFT : MIMXRT1062.h
- LPI2C_MCR_DBGEN : MIMXRT1062.h
- LPI2C_MCR_DBGEN_MASK : MIMXRT1062.h
- LPI2C_MCR_DBGEN_SHIFT : MIMXRT1062.h
- LPI2C_MCR_DOZEN : MIMXRT1062.h
- LPI2C_MCR_DOZEN_MASK : MIMXRT1062.h
- LPI2C_MCR_DOZEN_SHIFT : MIMXRT1062.h
- LPI2C_MCR_MEN : MIMXRT1062.h
- LPI2C_MCR_MEN_MASK : MIMXRT1062.h
- LPI2C_MCR_MEN_SHIFT : MIMXRT1062.h
- LPI2C_MCR_RRF : MIMXRT1062.h
- LPI2C_MCR_RRF_MASK : MIMXRT1062.h
- LPI2C_MCR_RRF_SHIFT : MIMXRT1062.h
- LPI2C_MCR_RST : MIMXRT1062.h
- LPI2C_MCR_RST_MASK : MIMXRT1062.h
- LPI2C_MCR_RST_SHIFT : MIMXRT1062.h
- LPI2C_MCR_RTF : MIMXRT1062.h
- LPI2C_MCR_RTF_MASK : MIMXRT1062.h
- LPI2C_MCR_RTF_SHIFT : MIMXRT1062.h
- LPI2C_MDER_RDDE : MIMXRT1062.h
- LPI2C_MDER_RDDE_MASK : MIMXRT1062.h
- LPI2C_MDER_RDDE_SHIFT : MIMXRT1062.h
- LPI2C_MDER_TDDE : MIMXRT1062.h
- LPI2C_MDER_TDDE_MASK : MIMXRT1062.h
- LPI2C_MDER_TDDE_SHIFT : MIMXRT1062.h
- LPI2C_MDMR_MATCH0 : MIMXRT1062.h
- LPI2C_MDMR_MATCH0_MASK : MIMXRT1062.h
- LPI2C_MDMR_MATCH0_SHIFT : MIMXRT1062.h
- LPI2C_MDMR_MATCH1 : MIMXRT1062.h
- LPI2C_MDMR_MATCH1_MASK : MIMXRT1062.h
- LPI2C_MDMR_MATCH1_SHIFT : MIMXRT1062.h
- LPI2C_MFCR_RXWATER : MIMXRT1062.h
- LPI2C_MFCR_RXWATER_MASK : MIMXRT1062.h
- LPI2C_MFCR_RXWATER_SHIFT : MIMXRT1062.h
- LPI2C_MFCR_TXWATER : MIMXRT1062.h
- LPI2C_MFCR_TXWATER_MASK : MIMXRT1062.h
- LPI2C_MFCR_TXWATER_SHIFT : MIMXRT1062.h
- LPI2C_MFSR_RXCOUNT : MIMXRT1062.h
- LPI2C_MFSR_RXCOUNT_MASK : MIMXRT1062.h
- LPI2C_MFSR_RXCOUNT_SHIFT : MIMXRT1062.h
- LPI2C_MFSR_TXCOUNT : MIMXRT1062.h
- LPI2C_MFSR_TXCOUNT_MASK : MIMXRT1062.h
- LPI2C_MFSR_TXCOUNT_SHIFT : MIMXRT1062.h
- LPI2C_MIER_ALIE : MIMXRT1062.h
- LPI2C_MIER_ALIE_MASK : MIMXRT1062.h
- LPI2C_MIER_ALIE_SHIFT : MIMXRT1062.h
- LPI2C_MIER_DMIE : MIMXRT1062.h
- LPI2C_MIER_DMIE_MASK : MIMXRT1062.h
- LPI2C_MIER_DMIE_SHIFT : MIMXRT1062.h
- LPI2C_MIER_EPIE : MIMXRT1062.h
- LPI2C_MIER_EPIE_MASK : MIMXRT1062.h
- LPI2C_MIER_EPIE_SHIFT : MIMXRT1062.h
- LPI2C_MIER_FEIE : MIMXRT1062.h
- LPI2C_MIER_FEIE_MASK : MIMXRT1062.h
- LPI2C_MIER_FEIE_SHIFT : MIMXRT1062.h
- LPI2C_MIER_NDIE : MIMXRT1062.h
- LPI2C_MIER_NDIE_MASK : MIMXRT1062.h
- LPI2C_MIER_NDIE_SHIFT : MIMXRT1062.h
- LPI2C_MIER_PLTIE : MIMXRT1062.h
- LPI2C_MIER_PLTIE_MASK : MIMXRT1062.h
- LPI2C_MIER_PLTIE_SHIFT : MIMXRT1062.h
- LPI2C_MIER_RDIE : MIMXRT1062.h
- LPI2C_MIER_RDIE_MASK : MIMXRT1062.h
- LPI2C_MIER_RDIE_SHIFT : MIMXRT1062.h
- LPI2C_MIER_SDIE : MIMXRT1062.h
- LPI2C_MIER_SDIE_MASK : MIMXRT1062.h
- LPI2C_MIER_SDIE_SHIFT : MIMXRT1062.h
- LPI2C_MIER_TDIE : MIMXRT1062.h
- LPI2C_MIER_TDIE_MASK : MIMXRT1062.h
- LPI2C_MIER_TDIE_SHIFT : MIMXRT1062.h
- LPI2C_MRDR_DATA : MIMXRT1062.h
- LPI2C_MRDR_DATA_MASK : MIMXRT1062.h
- LPI2C_MRDR_DATA_SHIFT : MIMXRT1062.h
- LPI2C_MRDR_RXEMPTY : MIMXRT1062.h
- LPI2C_MRDR_RXEMPTY_MASK : MIMXRT1062.h
- LPI2C_MRDR_RXEMPTY_SHIFT : MIMXRT1062.h
- LPI2C_MSR_ALF : MIMXRT1062.h
- LPI2C_MSR_ALF_MASK : MIMXRT1062.h
- LPI2C_MSR_ALF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_BBF : MIMXRT1062.h
- LPI2C_MSR_BBF_MASK : MIMXRT1062.h
- LPI2C_MSR_BBF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_DMF : MIMXRT1062.h
- LPI2C_MSR_DMF_MASK : MIMXRT1062.h
- LPI2C_MSR_DMF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_EPF : MIMXRT1062.h
- LPI2C_MSR_EPF_MASK : MIMXRT1062.h
- LPI2C_MSR_EPF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_FEF : MIMXRT1062.h
- LPI2C_MSR_FEF_MASK : MIMXRT1062.h
- LPI2C_MSR_FEF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_MBF : MIMXRT1062.h
- LPI2C_MSR_MBF_MASK : MIMXRT1062.h
- LPI2C_MSR_MBF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_NDF : MIMXRT1062.h
- LPI2C_MSR_NDF_MASK : MIMXRT1062.h
- LPI2C_MSR_NDF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_PLTF : MIMXRT1062.h
- LPI2C_MSR_PLTF_MASK : MIMXRT1062.h
- LPI2C_MSR_PLTF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_RDF : MIMXRT1062.h
- LPI2C_MSR_RDF_MASK : MIMXRT1062.h
- LPI2C_MSR_RDF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_SDF : MIMXRT1062.h
- LPI2C_MSR_SDF_MASK : MIMXRT1062.h
- LPI2C_MSR_SDF_SHIFT : MIMXRT1062.h
- LPI2C_MSR_TDF : MIMXRT1062.h
- LPI2C_MSR_TDF_MASK : MIMXRT1062.h
- LPI2C_MSR_TDF_SHIFT : MIMXRT1062.h
- LPI2C_MTDR_CMD : MIMXRT1062.h
- LPI2C_MTDR_CMD_MASK : MIMXRT1062.h
- LPI2C_MTDR_CMD_SHIFT : MIMXRT1062.h
- LPI2C_MTDR_DATA : MIMXRT1062.h
- LPI2C_MTDR_DATA_MASK : MIMXRT1062.h
- LPI2C_MTDR_DATA_SHIFT : MIMXRT1062.h
- LPI2C_PARAM_MRXFIFO : MIMXRT1062.h
- LPI2C_PARAM_MRXFIFO_MASK : MIMXRT1062.h
- LPI2C_PARAM_MRXFIFO_SHIFT : MIMXRT1062.h
- LPI2C_PARAM_MTXFIFO : MIMXRT1062.h
- LPI2C_PARAM_MTXFIFO_MASK : MIMXRT1062.h
- LPI2C_PARAM_MTXFIFO_SHIFT : MIMXRT1062.h
- LPI2C_SAMR_ADDR0 : MIMXRT1062.h
- LPI2C_SAMR_ADDR0_MASK : MIMXRT1062.h
- LPI2C_SAMR_ADDR0_SHIFT : MIMXRT1062.h
- LPI2C_SAMR_ADDR1 : MIMXRT1062.h
- LPI2C_SAMR_ADDR1_MASK : MIMXRT1062.h
- LPI2C_SAMR_ADDR1_SHIFT : MIMXRT1062.h
- LPI2C_SASR_ANV : MIMXRT1062.h
- LPI2C_SASR_ANV_MASK : MIMXRT1062.h
- LPI2C_SASR_ANV_SHIFT : MIMXRT1062.h
- LPI2C_SASR_RADDR : MIMXRT1062.h
- LPI2C_SASR_RADDR_MASK : MIMXRT1062.h
- LPI2C_SASR_RADDR_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_ACKSTALL : MIMXRT1062.h
- LPI2C_SCFGR1_ACKSTALL_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_ACKSTALL_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_ADDRCFG : MIMXRT1062.h
- LPI2C_SCFGR1_ADDRCFG_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_ADDRCFG_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_ADRSTALL : MIMXRT1062.h
- LPI2C_SCFGR1_ADRSTALL_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_ADRSTALL_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_GCEN : MIMXRT1062.h
- LPI2C_SCFGR1_GCEN_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_GCEN_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_HSMEN : MIMXRT1062.h
- LPI2C_SCFGR1_HSMEN_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_HSMEN_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_IGNACK : MIMXRT1062.h
- LPI2C_SCFGR1_IGNACK_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_IGNACK_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_RXCFG : MIMXRT1062.h
- LPI2C_SCFGR1_RXCFG_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_RXCFG_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_RXSTALL : MIMXRT1062.h
- LPI2C_SCFGR1_RXSTALL_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_RXSTALL_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_SAEN : MIMXRT1062.h
- LPI2C_SCFGR1_SAEN_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_SAEN_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_TXCFG : MIMXRT1062.h
- LPI2C_SCFGR1_TXCFG_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_TXCFG_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR1_TXDSTALL : MIMXRT1062.h
- LPI2C_SCFGR1_TXDSTALL_MASK : MIMXRT1062.h
- LPI2C_SCFGR1_TXDSTALL_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR2_CLKHOLD : MIMXRT1062.h
- LPI2C_SCFGR2_CLKHOLD_MASK : MIMXRT1062.h
- LPI2C_SCFGR2_CLKHOLD_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR2_DATAVD : MIMXRT1062.h
- LPI2C_SCFGR2_DATAVD_MASK : MIMXRT1062.h
- LPI2C_SCFGR2_DATAVD_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR2_FILTSCL : MIMXRT1062.h
- LPI2C_SCFGR2_FILTSCL_MASK : MIMXRT1062.h
- LPI2C_SCFGR2_FILTSCL_SHIFT : MIMXRT1062.h
- LPI2C_SCFGR2_FILTSDA : MIMXRT1062.h
- LPI2C_SCFGR2_FILTSDA_MASK : MIMXRT1062.h
- LPI2C_SCFGR2_FILTSDA_SHIFT : MIMXRT1062.h
- LPI2C_SCR_FILTDZ : MIMXRT1062.h
- LPI2C_SCR_FILTDZ_MASK : MIMXRT1062.h
- LPI2C_SCR_FILTDZ_SHIFT : MIMXRT1062.h
- LPI2C_SCR_FILTEN : MIMXRT1062.h
- LPI2C_SCR_FILTEN_MASK : MIMXRT1062.h
- LPI2C_SCR_FILTEN_SHIFT : MIMXRT1062.h
- LPI2C_SCR_RRF : MIMXRT1062.h
- LPI2C_SCR_RRF_MASK : MIMXRT1062.h
- LPI2C_SCR_RRF_SHIFT : MIMXRT1062.h
- LPI2C_SCR_RST : MIMXRT1062.h
- LPI2C_SCR_RST_MASK : MIMXRT1062.h
- LPI2C_SCR_RST_SHIFT : MIMXRT1062.h
- LPI2C_SCR_RTF : MIMXRT1062.h
- LPI2C_SCR_RTF_MASK : MIMXRT1062.h
- LPI2C_SCR_RTF_SHIFT : MIMXRT1062.h
- LPI2C_SCR_SEN : MIMXRT1062.h
- LPI2C_SCR_SEN_MASK : MIMXRT1062.h
- LPI2C_SCR_SEN_SHIFT : MIMXRT1062.h
- LPI2C_SDER_AVDE : MIMXRT1062.h
- LPI2C_SDER_AVDE_MASK : MIMXRT1062.h
- LPI2C_SDER_AVDE_SHIFT : MIMXRT1062.h
- LPI2C_SDER_RDDE : MIMXRT1062.h
- LPI2C_SDER_RDDE_MASK : MIMXRT1062.h
- LPI2C_SDER_RDDE_SHIFT : MIMXRT1062.h
- LPI2C_SDER_TDDE : MIMXRT1062.h
- LPI2C_SDER_TDDE_MASK : MIMXRT1062.h
- LPI2C_SDER_TDDE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_AM0IE : MIMXRT1062.h
- LPI2C_SIER_AM0IE_MASK : MIMXRT1062.h
- LPI2C_SIER_AM0IE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_AM1F : MIMXRT1062.h
- LPI2C_SIER_AM1F_MASK : MIMXRT1062.h
- LPI2C_SIER_AM1F_SHIFT : MIMXRT1062.h
- LPI2C_SIER_AVIE : MIMXRT1062.h
- LPI2C_SIER_AVIE_MASK : MIMXRT1062.h
- LPI2C_SIER_AVIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_BEIE : MIMXRT1062.h
- LPI2C_SIER_BEIE_MASK : MIMXRT1062.h
- LPI2C_SIER_BEIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_FEIE : MIMXRT1062.h
- LPI2C_SIER_FEIE_MASK : MIMXRT1062.h
- LPI2C_SIER_FEIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_GCIE : MIMXRT1062.h
- LPI2C_SIER_GCIE_MASK : MIMXRT1062.h
- LPI2C_SIER_GCIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_RDIE : MIMXRT1062.h
- LPI2C_SIER_RDIE_MASK : MIMXRT1062.h
- LPI2C_SIER_RDIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_RSIE : MIMXRT1062.h
- LPI2C_SIER_RSIE_MASK : MIMXRT1062.h
- LPI2C_SIER_RSIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_SARIE : MIMXRT1062.h
- LPI2C_SIER_SARIE_MASK : MIMXRT1062.h
- LPI2C_SIER_SARIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_SDIE : MIMXRT1062.h
- LPI2C_SIER_SDIE_MASK : MIMXRT1062.h
- LPI2C_SIER_SDIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_TAIE : MIMXRT1062.h
- LPI2C_SIER_TAIE_MASK : MIMXRT1062.h
- LPI2C_SIER_TAIE_SHIFT : MIMXRT1062.h
- LPI2C_SIER_TDIE : MIMXRT1062.h
- LPI2C_SIER_TDIE_MASK : MIMXRT1062.h
- LPI2C_SIER_TDIE_SHIFT : MIMXRT1062.h
- LPI2C_SRDR_DATA : MIMXRT1062.h
- LPI2C_SRDR_DATA_MASK : MIMXRT1062.h
- LPI2C_SRDR_DATA_SHIFT : MIMXRT1062.h
- LPI2C_SRDR_RXEMPTY : MIMXRT1062.h
- LPI2C_SRDR_RXEMPTY_MASK : MIMXRT1062.h
- LPI2C_SRDR_RXEMPTY_SHIFT : MIMXRT1062.h
- LPI2C_SRDR_SOF : MIMXRT1062.h
- LPI2C_SRDR_SOF_MASK : MIMXRT1062.h
- LPI2C_SRDR_SOF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_AM0F : MIMXRT1062.h
- LPI2C_SSR_AM0F_MASK : MIMXRT1062.h
- LPI2C_SSR_AM0F_SHIFT : MIMXRT1062.h
- LPI2C_SSR_AM1F : MIMXRT1062.h
- LPI2C_SSR_AM1F_MASK : MIMXRT1062.h
- LPI2C_SSR_AM1F_SHIFT : MIMXRT1062.h
- LPI2C_SSR_AVF : MIMXRT1062.h
- LPI2C_SSR_AVF_MASK : MIMXRT1062.h
- LPI2C_SSR_AVF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_BBF : MIMXRT1062.h
- LPI2C_SSR_BBF_MASK : MIMXRT1062.h
- LPI2C_SSR_BBF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_BEF : MIMXRT1062.h
- LPI2C_SSR_BEF_MASK : MIMXRT1062.h
- LPI2C_SSR_BEF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_FEF : MIMXRT1062.h
- LPI2C_SSR_FEF_MASK : MIMXRT1062.h
- LPI2C_SSR_FEF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_GCF : MIMXRT1062.h
- LPI2C_SSR_GCF_MASK : MIMXRT1062.h
- LPI2C_SSR_GCF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_RDF : MIMXRT1062.h
- LPI2C_SSR_RDF_MASK : MIMXRT1062.h
- LPI2C_SSR_RDF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_RSF : MIMXRT1062.h
- LPI2C_SSR_RSF_MASK : MIMXRT1062.h
- LPI2C_SSR_RSF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_SARF : MIMXRT1062.h
- LPI2C_SSR_SARF_MASK : MIMXRT1062.h
- LPI2C_SSR_SARF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_SBF : MIMXRT1062.h
- LPI2C_SSR_SBF_MASK : MIMXRT1062.h
- LPI2C_SSR_SBF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_SDF : MIMXRT1062.h
- LPI2C_SSR_SDF_MASK : MIMXRT1062.h
- LPI2C_SSR_SDF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_TAF : MIMXRT1062.h
- LPI2C_SSR_TAF_MASK : MIMXRT1062.h
- LPI2C_SSR_TAF_SHIFT : MIMXRT1062.h
- LPI2C_SSR_TDF : MIMXRT1062.h
- LPI2C_SSR_TDF_MASK : MIMXRT1062.h
- LPI2C_SSR_TDF_SHIFT : MIMXRT1062.h
- LPI2C_STAR_TXNACK : MIMXRT1062.h
- LPI2C_STAR_TXNACK_MASK : MIMXRT1062.h
- LPI2C_STAR_TXNACK_SHIFT : MIMXRT1062.h
- LPI2C_STDR_DATA : MIMXRT1062.h
- LPI2C_STDR_DATA_MASK : MIMXRT1062.h
- LPI2C_STDR_DATA_SHIFT : MIMXRT1062.h
- LPI2C_VERID_FEATURE : MIMXRT1062.h
- LPI2C_VERID_FEATURE_MASK : MIMXRT1062.h
- LPI2C_VERID_FEATURE_SHIFT : MIMXRT1062.h
- LPI2C_VERID_MAJOR : MIMXRT1062.h
- LPI2C_VERID_MAJOR_MASK : MIMXRT1062.h
- LPI2C_VERID_MAJOR_SHIFT : MIMXRT1062.h
- LPI2C_VERID_MINOR : MIMXRT1062.h
- LPI2C_VERID_MINOR_MASK : MIMXRT1062.h
- LPI2C_VERID_MINOR_SHIFT : MIMXRT1062.h
- LPSPI1 : MIMXRT1062.h
- LPSPI1_BASE : MIMXRT1062.h
- LPSPI2 : MIMXRT1062.h
- LPSPI2_BASE : MIMXRT1062.h
- LPSPI3 : MIMXRT1062.h
- LPSPI3_BASE : MIMXRT1062.h
- LPSPI4 : MIMXRT1062.h
- LPSPI4_BASE : MIMXRT1062.h
- LPSPI_BASE_ADDRS : MIMXRT1062.h
- LPSPI_BASE_PTRS : MIMXRT1062.h
- LPSPI_CCR_DBT : MIMXRT1062.h
- LPSPI_CCR_DBT_MASK : MIMXRT1062.h
- LPSPI_CCR_DBT_SHIFT : MIMXRT1062.h
- LPSPI_CCR_PCSSCK : MIMXRT1062.h
- LPSPI_CCR_PCSSCK_MASK : MIMXRT1062.h
- LPSPI_CCR_PCSSCK_SHIFT : MIMXRT1062.h
- LPSPI_CCR_SCKDIV : MIMXRT1062.h
- LPSPI_CCR_SCKDIV_MASK : MIMXRT1062.h
- LPSPI_CCR_SCKDIV_SHIFT : MIMXRT1062.h
- LPSPI_CCR_SCKPCS : MIMXRT1062.h
- LPSPI_CCR_SCKPCS_MASK : MIMXRT1062.h
- LPSPI_CCR_SCKPCS_SHIFT : MIMXRT1062.h
- LPSPI_CFGR0_CIRFIFO : MIMXRT1062.h
- LPSPI_CFGR0_CIRFIFO_MASK : MIMXRT1062.h
- LPSPI_CFGR0_CIRFIFO_SHIFT : MIMXRT1062.h
- LPSPI_CFGR0_HREN : MIMXRT1062.h
- LPSPI_CFGR0_HREN_MASK : MIMXRT1062.h
- LPSPI_CFGR0_HREN_SHIFT : MIMXRT1062.h
- LPSPI_CFGR0_HRPOL : MIMXRT1062.h
- LPSPI_CFGR0_HRPOL_MASK : MIMXRT1062.h
- LPSPI_CFGR0_HRPOL_SHIFT : MIMXRT1062.h
- LPSPI_CFGR0_HRSEL : MIMXRT1062.h
- LPSPI_CFGR0_HRSEL_MASK : MIMXRT1062.h
- LPSPI_CFGR0_HRSEL_SHIFT : MIMXRT1062.h
- LPSPI_CFGR0_RDMO : MIMXRT1062.h
- LPSPI_CFGR0_RDMO_MASK : MIMXRT1062.h
- LPSPI_CFGR0_RDMO_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_AUTOPCS : MIMXRT1062.h
- LPSPI_CFGR1_AUTOPCS_MASK : MIMXRT1062.h
- LPSPI_CFGR1_AUTOPCS_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_MASTER : MIMXRT1062.h
- LPSPI_CFGR1_MASTER_MASK : MIMXRT1062.h
- LPSPI_CFGR1_MASTER_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_MATCFG : MIMXRT1062.h
- LPSPI_CFGR1_MATCFG_MASK : MIMXRT1062.h
- LPSPI_CFGR1_MATCFG_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_NOSTALL : MIMXRT1062.h
- LPSPI_CFGR1_NOSTALL_MASK : MIMXRT1062.h
- LPSPI_CFGR1_NOSTALL_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_OUTCFG : MIMXRT1062.h
- LPSPI_CFGR1_OUTCFG_MASK : MIMXRT1062.h
- LPSPI_CFGR1_OUTCFG_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_PCSCFG : MIMXRT1062.h
- LPSPI_CFGR1_PCSCFG_MASK : MIMXRT1062.h
- LPSPI_CFGR1_PCSCFG_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_PCSPOL : MIMXRT1062.h
- LPSPI_CFGR1_PCSPOL_MASK : MIMXRT1062.h
- LPSPI_CFGR1_PCSPOL_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_PINCFG : MIMXRT1062.h
- LPSPI_CFGR1_PINCFG_MASK : MIMXRT1062.h
- LPSPI_CFGR1_PINCFG_SHIFT : MIMXRT1062.h
- LPSPI_CFGR1_SAMPLE : MIMXRT1062.h
- LPSPI_CFGR1_SAMPLE_MASK : MIMXRT1062.h
- LPSPI_CFGR1_SAMPLE_SHIFT : MIMXRT1062.h
- LPSPI_CR_DBGEN : MIMXRT1062.h
- LPSPI_CR_DBGEN_MASK : MIMXRT1062.h
- LPSPI_CR_DBGEN_SHIFT : MIMXRT1062.h
- LPSPI_CR_DOZEN : MIMXRT1062.h
- LPSPI_CR_DOZEN_MASK : MIMXRT1062.h
- LPSPI_CR_DOZEN_SHIFT : MIMXRT1062.h
- LPSPI_CR_MEN : MIMXRT1062.h
- LPSPI_CR_MEN_MASK : MIMXRT1062.h
- LPSPI_CR_MEN_SHIFT : MIMXRT1062.h
- LPSPI_CR_RRF : MIMXRT1062.h
- LPSPI_CR_RRF_MASK : MIMXRT1062.h
- LPSPI_CR_RRF_SHIFT : MIMXRT1062.h
- LPSPI_CR_RST : MIMXRT1062.h
- LPSPI_CR_RST_MASK : MIMXRT1062.h
- LPSPI_CR_RST_SHIFT : MIMXRT1062.h
- LPSPI_CR_RTF : MIMXRT1062.h
- LPSPI_CR_RTF_MASK : MIMXRT1062.h
- LPSPI_CR_RTF_SHIFT : MIMXRT1062.h
- LPSPI_DER_RDDE : MIMXRT1062.h
- LPSPI_DER_RDDE_MASK : MIMXRT1062.h
- LPSPI_DER_RDDE_SHIFT : MIMXRT1062.h
- LPSPI_DER_TDDE : MIMXRT1062.h
- LPSPI_DER_TDDE_MASK : MIMXRT1062.h
- LPSPI_DER_TDDE_SHIFT : MIMXRT1062.h
- LPSPI_DMR0_MATCH0 : MIMXRT1062.h
- LPSPI_DMR0_MATCH0_MASK : MIMXRT1062.h
- LPSPI_DMR0_MATCH0_SHIFT : MIMXRT1062.h
- LPSPI_DMR1_MATCH1 : MIMXRT1062.h
- LPSPI_DMR1_MATCH1_MASK : MIMXRT1062.h
- LPSPI_DMR1_MATCH1_SHIFT : MIMXRT1062.h
- LPSPI_FCR_RXWATER : MIMXRT1062.h
- LPSPI_FCR_RXWATER_MASK : MIMXRT1062.h
- LPSPI_FCR_RXWATER_SHIFT : MIMXRT1062.h
- LPSPI_FCR_TXWATER : MIMXRT1062.h
- LPSPI_FCR_TXWATER_MASK : MIMXRT1062.h
- LPSPI_FCR_TXWATER_SHIFT : MIMXRT1062.h
- LPSPI_FSR_RXCOUNT : MIMXRT1062.h
- LPSPI_FSR_RXCOUNT_MASK : MIMXRT1062.h
- LPSPI_FSR_RXCOUNT_SHIFT : MIMXRT1062.h
- LPSPI_FSR_TXCOUNT : MIMXRT1062.h
- LPSPI_FSR_TXCOUNT_MASK : MIMXRT1062.h
- LPSPI_FSR_TXCOUNT_SHIFT : MIMXRT1062.h
- LPSPI_IER_DMIE : MIMXRT1062.h
- LPSPI_IER_DMIE_MASK : MIMXRT1062.h
- LPSPI_IER_DMIE_SHIFT : MIMXRT1062.h
- LPSPI_IER_FCIE : MIMXRT1062.h
- LPSPI_IER_FCIE_MASK : MIMXRT1062.h
- LPSPI_IER_FCIE_SHIFT : MIMXRT1062.h
- LPSPI_IER_RDIE : MIMXRT1062.h
- LPSPI_IER_RDIE_MASK : MIMXRT1062.h
- LPSPI_IER_RDIE_SHIFT : MIMXRT1062.h
- LPSPI_IER_REIE : MIMXRT1062.h
- LPSPI_IER_REIE_MASK : MIMXRT1062.h
- LPSPI_IER_REIE_SHIFT : MIMXRT1062.h
- LPSPI_IER_TCIE : MIMXRT1062.h
- LPSPI_IER_TCIE_MASK : MIMXRT1062.h
- LPSPI_IER_TCIE_SHIFT : MIMXRT1062.h
- LPSPI_IER_TDIE : MIMXRT1062.h
- LPSPI_IER_TDIE_MASK : MIMXRT1062.h
- LPSPI_IER_TDIE_SHIFT : MIMXRT1062.h
- LPSPI_IER_TEIE : MIMXRT1062.h
- LPSPI_IER_TEIE_MASK : MIMXRT1062.h
- LPSPI_IER_TEIE_SHIFT : MIMXRT1062.h
- LPSPI_IER_WCIE : MIMXRT1062.h
- LPSPI_IER_WCIE_MASK : MIMXRT1062.h
- LPSPI_IER_WCIE_SHIFT : MIMXRT1062.h
- LPSPI_IRQS : MIMXRT1062.h
- LPSPI_PARAM_PCSNUM : MIMXRT1062.h
- LPSPI_PARAM_PCSNUM_MASK : MIMXRT1062.h
- LPSPI_PARAM_PCSNUM_SHIFT : MIMXRT1062.h
- LPSPI_PARAM_RXFIFO : MIMXRT1062.h
- LPSPI_PARAM_RXFIFO_MASK : MIMXRT1062.h
- LPSPI_PARAM_RXFIFO_SHIFT : MIMXRT1062.h
- LPSPI_PARAM_TXFIFO : MIMXRT1062.h
- LPSPI_PARAM_TXFIFO_MASK : MIMXRT1062.h
- LPSPI_PARAM_TXFIFO_SHIFT : MIMXRT1062.h
- LPSPI_RDR_DATA : MIMXRT1062.h
- LPSPI_RDR_DATA_MASK : MIMXRT1062.h
- LPSPI_RDR_DATA_SHIFT : MIMXRT1062.h
- LPSPI_RSR_RXEMPTY : MIMXRT1062.h
- LPSPI_RSR_RXEMPTY_MASK : MIMXRT1062.h
- LPSPI_RSR_RXEMPTY_SHIFT : MIMXRT1062.h
- LPSPI_RSR_SOF : MIMXRT1062.h
- LPSPI_RSR_SOF_MASK : MIMXRT1062.h
- LPSPI_RSR_SOF_SHIFT : MIMXRT1062.h
- LPSPI_SR_DMF : MIMXRT1062.h
- LPSPI_SR_DMF_MASK : MIMXRT1062.h
- LPSPI_SR_DMF_SHIFT : MIMXRT1062.h
- LPSPI_SR_FCF : MIMXRT1062.h
- LPSPI_SR_FCF_MASK : MIMXRT1062.h
- LPSPI_SR_FCF_SHIFT : MIMXRT1062.h
- LPSPI_SR_MBF : MIMXRT1062.h
- LPSPI_SR_MBF_MASK : MIMXRT1062.h
- LPSPI_SR_MBF_SHIFT : MIMXRT1062.h
- LPSPI_SR_RDF : MIMXRT1062.h
- LPSPI_SR_RDF_MASK : MIMXRT1062.h
- LPSPI_SR_RDF_SHIFT : MIMXRT1062.h
- LPSPI_SR_REF : MIMXRT1062.h
- LPSPI_SR_REF_MASK : MIMXRT1062.h
- LPSPI_SR_REF_SHIFT : MIMXRT1062.h
- LPSPI_SR_TCF : MIMXRT1062.h
- LPSPI_SR_TCF_MASK : MIMXRT1062.h
- LPSPI_SR_TCF_SHIFT : MIMXRT1062.h
- LPSPI_SR_TDF : MIMXRT1062.h
- LPSPI_SR_TDF_MASK : MIMXRT1062.h
- LPSPI_SR_TDF_SHIFT : MIMXRT1062.h
- LPSPI_SR_TEF : MIMXRT1062.h
- LPSPI_SR_TEF_MASK : MIMXRT1062.h
- LPSPI_SR_TEF_SHIFT : MIMXRT1062.h
- LPSPI_SR_WCF : MIMXRT1062.h
- LPSPI_SR_WCF_MASK : MIMXRT1062.h
- LPSPI_SR_WCF_SHIFT : MIMXRT1062.h
- LPSPI_TCR_BYSW : MIMXRT1062.h
- LPSPI_TCR_BYSW_MASK : MIMXRT1062.h
- LPSPI_TCR_BYSW_SHIFT : MIMXRT1062.h
- LPSPI_TCR_CONT : MIMXRT1062.h
- LPSPI_TCR_CONT_MASK : MIMXRT1062.h
- LPSPI_TCR_CONT_SHIFT : MIMXRT1062.h
- LPSPI_TCR_CONTC : MIMXRT1062.h
- LPSPI_TCR_CONTC_MASK : MIMXRT1062.h
- LPSPI_TCR_CONTC_SHIFT : MIMXRT1062.h
- LPSPI_TCR_CPHA : MIMXRT1062.h
- LPSPI_TCR_CPHA_MASK : MIMXRT1062.h
- LPSPI_TCR_CPHA_SHIFT : MIMXRT1062.h
- LPSPI_TCR_CPOL : MIMXRT1062.h
- LPSPI_TCR_CPOL_MASK : MIMXRT1062.h
- LPSPI_TCR_CPOL_SHIFT : MIMXRT1062.h
- LPSPI_TCR_FRAMESZ : MIMXRT1062.h
- LPSPI_TCR_FRAMESZ_MASK : MIMXRT1062.h
- LPSPI_TCR_FRAMESZ_SHIFT : MIMXRT1062.h
- LPSPI_TCR_LSBF : MIMXRT1062.h
- LPSPI_TCR_LSBF_MASK : MIMXRT1062.h
- LPSPI_TCR_LSBF_SHIFT : MIMXRT1062.h
- LPSPI_TCR_PCS : MIMXRT1062.h
- LPSPI_TCR_PCS_MASK : MIMXRT1062.h
- LPSPI_TCR_PCS_SHIFT : MIMXRT1062.h
- LPSPI_TCR_PRESCALE : MIMXRT1062.h
- LPSPI_TCR_PRESCALE_MASK : MIMXRT1062.h
- LPSPI_TCR_PRESCALE_SHIFT : MIMXRT1062.h
- LPSPI_TCR_RXMSK : MIMXRT1062.h
- LPSPI_TCR_RXMSK_MASK : MIMXRT1062.h
- LPSPI_TCR_RXMSK_SHIFT : MIMXRT1062.h
- LPSPI_TCR_TXMSK : MIMXRT1062.h
- LPSPI_TCR_TXMSK_MASK : MIMXRT1062.h
- LPSPI_TCR_TXMSK_SHIFT : MIMXRT1062.h
- LPSPI_TCR_WIDTH : MIMXRT1062.h
- LPSPI_TCR_WIDTH_MASK : MIMXRT1062.h
- LPSPI_TCR_WIDTH_SHIFT : MIMXRT1062.h
- LPSPI_TDR_DATA : MIMXRT1062.h
- LPSPI_TDR_DATA_MASK : MIMXRT1062.h
- LPSPI_TDR_DATA_SHIFT : MIMXRT1062.h
- LPSPI_VERID_FEATURE : MIMXRT1062.h
- LPSPI_VERID_FEATURE_MASK : MIMXRT1062.h
- LPSPI_VERID_FEATURE_SHIFT : MIMXRT1062.h
- LPSPI_VERID_MAJOR : MIMXRT1062.h
- LPSPI_VERID_MAJOR_MASK : MIMXRT1062.h
- LPSPI_VERID_MAJOR_SHIFT : MIMXRT1062.h
- LPSPI_VERID_MINOR : MIMXRT1062.h
- LPSPI_VERID_MINOR_MASK : MIMXRT1062.h
- LPSPI_VERID_MINOR_SHIFT : MIMXRT1062.h
- LPUART1 : MIMXRT1062.h
- LPUART1_BASE : MIMXRT1062.h
- LPUART2 : MIMXRT1062.h
- LPUART2_BASE : MIMXRT1062.h
- LPUART3 : MIMXRT1062.h
- LPUART3_BASE : MIMXRT1062.h
- LPUART4 : MIMXRT1062.h
- LPUART4_BASE : MIMXRT1062.h
- LPUART5 : MIMXRT1062.h
- LPUART5_BASE : MIMXRT1062.h
- LPUART6 : MIMXRT1062.h
- LPUART6_BASE : MIMXRT1062.h
- LPUART7 : MIMXRT1062.h
- LPUART7_BASE : MIMXRT1062.h
- LPUART8 : MIMXRT1062.h
- LPUART8_BASE : MIMXRT1062.h
- LPUART_BASE_ADDRS : MIMXRT1062.h
- LPUART_BASE_PTRS : MIMXRT1062.h
- LPUART_BAUD_BOTHEDGE : MIMXRT1062.h
- LPUART_BAUD_BOTHEDGE_MASK : MIMXRT1062.h
- LPUART_BAUD_BOTHEDGE_SHIFT : MIMXRT1062.h
- LPUART_BAUD_LBKDIE : MIMXRT1062.h
- LPUART_BAUD_LBKDIE_MASK : MIMXRT1062.h
- LPUART_BAUD_LBKDIE_SHIFT : MIMXRT1062.h
- LPUART_BAUD_M10 : MIMXRT1062.h
- LPUART_BAUD_M10_MASK : MIMXRT1062.h
- LPUART_BAUD_M10_SHIFT : MIMXRT1062.h
- LPUART_BAUD_MAEN1 : MIMXRT1062.h
- LPUART_BAUD_MAEN1_MASK : MIMXRT1062.h
- LPUART_BAUD_MAEN1_SHIFT : MIMXRT1062.h
- LPUART_BAUD_MAEN2 : MIMXRT1062.h
- LPUART_BAUD_MAEN2_MASK : MIMXRT1062.h
- LPUART_BAUD_MAEN2_SHIFT : MIMXRT1062.h
- LPUART_BAUD_MATCFG : MIMXRT1062.h
- LPUART_BAUD_MATCFG_MASK : MIMXRT1062.h
- LPUART_BAUD_MATCFG_SHIFT : MIMXRT1062.h
- LPUART_BAUD_OSR : MIMXRT1062.h
- LPUART_BAUD_OSR_MASK : MIMXRT1062.h
- LPUART_BAUD_OSR_SHIFT : MIMXRT1062.h
- LPUART_BAUD_RDMAE : MIMXRT1062.h
- LPUART_BAUD_RDMAE_MASK : MIMXRT1062.h
- LPUART_BAUD_RDMAE_SHIFT : MIMXRT1062.h
- LPUART_BAUD_RESYNCDIS : MIMXRT1062.h
- LPUART_BAUD_RESYNCDIS_MASK : MIMXRT1062.h
- LPUART_BAUD_RESYNCDIS_SHIFT : MIMXRT1062.h
- LPUART_BAUD_RIDMAE : MIMXRT1062.h
- LPUART_BAUD_RIDMAE_MASK : MIMXRT1062.h
- LPUART_BAUD_RIDMAE_SHIFT : MIMXRT1062.h
- LPUART_BAUD_RXEDGIE : MIMXRT1062.h
- LPUART_BAUD_RXEDGIE_MASK : MIMXRT1062.h
- LPUART_BAUD_RXEDGIE_SHIFT : MIMXRT1062.h
- LPUART_BAUD_SBNS : MIMXRT1062.h
- LPUART_BAUD_SBNS_MASK : MIMXRT1062.h
- LPUART_BAUD_SBNS_SHIFT : MIMXRT1062.h
- LPUART_BAUD_SBR : MIMXRT1062.h
- LPUART_BAUD_SBR_MASK : MIMXRT1062.h
- LPUART_BAUD_SBR_SHIFT : MIMXRT1062.h
- LPUART_BAUD_TDMAE : MIMXRT1062.h
- LPUART_BAUD_TDMAE_MASK : MIMXRT1062.h
- LPUART_BAUD_TDMAE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_DOZEEN : MIMXRT1062.h
- LPUART_CTRL_DOZEEN_MASK : MIMXRT1062.h
- LPUART_CTRL_DOZEEN_SHIFT : MIMXRT1062.h
- LPUART_CTRL_FEIE : MIMXRT1062.h
- LPUART_CTRL_FEIE_MASK : MIMXRT1062.h
- LPUART_CTRL_FEIE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_IDLECFG : MIMXRT1062.h
- LPUART_CTRL_IDLECFG_MASK : MIMXRT1062.h
- LPUART_CTRL_IDLECFG_SHIFT : MIMXRT1062.h
- LPUART_CTRL_ILIE : MIMXRT1062.h
- LPUART_CTRL_ILIE_MASK : MIMXRT1062.h
- LPUART_CTRL_ILIE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_ILT : MIMXRT1062.h
- LPUART_CTRL_ILT_MASK : MIMXRT1062.h
- LPUART_CTRL_ILT_SHIFT : MIMXRT1062.h
- LPUART_CTRL_LOOPS : MIMXRT1062.h
- LPUART_CTRL_LOOPS_MASK : MIMXRT1062.h
- LPUART_CTRL_LOOPS_SHIFT : MIMXRT1062.h
- LPUART_CTRL_M : MIMXRT1062.h
- LPUART_CTRL_M7 : MIMXRT1062.h
- LPUART_CTRL_M7_MASK : MIMXRT1062.h
- LPUART_CTRL_M7_SHIFT : MIMXRT1062.h
- LPUART_CTRL_M_MASK : MIMXRT1062.h
- LPUART_CTRL_M_SHIFT : MIMXRT1062.h
- LPUART_CTRL_MA1IE : MIMXRT1062.h
- LPUART_CTRL_MA1IE_MASK : MIMXRT1062.h
- LPUART_CTRL_MA1IE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_MA2IE : MIMXRT1062.h
- LPUART_CTRL_MA2IE_MASK : MIMXRT1062.h
- LPUART_CTRL_MA2IE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_NEIE : MIMXRT1062.h
- LPUART_CTRL_NEIE_MASK : MIMXRT1062.h
- LPUART_CTRL_NEIE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_ORIE : MIMXRT1062.h
- LPUART_CTRL_ORIE_MASK : MIMXRT1062.h
- LPUART_CTRL_ORIE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_PE : MIMXRT1062.h
- LPUART_CTRL_PE_MASK : MIMXRT1062.h
- LPUART_CTRL_PE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_PEIE : MIMXRT1062.h
- LPUART_CTRL_PEIE_MASK : MIMXRT1062.h
- LPUART_CTRL_PEIE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_PT : MIMXRT1062.h
- LPUART_CTRL_PT_MASK : MIMXRT1062.h
- LPUART_CTRL_PT_SHIFT : MIMXRT1062.h
- LPUART_CTRL_R8T9 : MIMXRT1062.h
- LPUART_CTRL_R8T9_MASK : MIMXRT1062.h
- LPUART_CTRL_R8T9_SHIFT : MIMXRT1062.h
- LPUART_CTRL_R9T8 : MIMXRT1062.h
- LPUART_CTRL_R9T8_MASK : MIMXRT1062.h
- LPUART_CTRL_R9T8_SHIFT : MIMXRT1062.h
- LPUART_CTRL_RE : MIMXRT1062.h
- LPUART_CTRL_RE_MASK : MIMXRT1062.h
- LPUART_CTRL_RE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_RIE : MIMXRT1062.h
- LPUART_CTRL_RIE_MASK : MIMXRT1062.h
- LPUART_CTRL_RIE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_RSRC : MIMXRT1062.h
- LPUART_CTRL_RSRC_MASK : MIMXRT1062.h
- LPUART_CTRL_RSRC_SHIFT : MIMXRT1062.h
- LPUART_CTRL_RWU : MIMXRT1062.h
- LPUART_CTRL_RWU_MASK : MIMXRT1062.h
- LPUART_CTRL_RWU_SHIFT : MIMXRT1062.h
- LPUART_CTRL_SBK : MIMXRT1062.h
- LPUART_CTRL_SBK_MASK : MIMXRT1062.h
- LPUART_CTRL_SBK_SHIFT : MIMXRT1062.h
- LPUART_CTRL_TCIE : MIMXRT1062.h
- LPUART_CTRL_TCIE_MASK : MIMXRT1062.h
- LPUART_CTRL_TCIE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_TE : MIMXRT1062.h
- LPUART_CTRL_TE_MASK : MIMXRT1062.h
- LPUART_CTRL_TE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_TIE : MIMXRT1062.h
- LPUART_CTRL_TIE_MASK : MIMXRT1062.h
- LPUART_CTRL_TIE_SHIFT : MIMXRT1062.h
- LPUART_CTRL_TXDIR : MIMXRT1062.h
- LPUART_CTRL_TXDIR_MASK : MIMXRT1062.h
- LPUART_CTRL_TXDIR_SHIFT : MIMXRT1062.h
- LPUART_CTRL_TXINV : MIMXRT1062.h
- LPUART_CTRL_TXINV_MASK : MIMXRT1062.h
- LPUART_CTRL_TXINV_SHIFT : MIMXRT1062.h
- LPUART_CTRL_WAKE : MIMXRT1062.h
- LPUART_CTRL_WAKE_MASK : MIMXRT1062.h
- LPUART_CTRL_WAKE_SHIFT : MIMXRT1062.h
- LPUART_DATA_FRETSC : MIMXRT1062.h
- LPUART_DATA_FRETSC_MASK : MIMXRT1062.h
- LPUART_DATA_FRETSC_SHIFT : MIMXRT1062.h
- LPUART_DATA_IDLINE : MIMXRT1062.h
- LPUART_DATA_IDLINE_MASK : MIMXRT1062.h
- LPUART_DATA_IDLINE_SHIFT : MIMXRT1062.h
- LPUART_DATA_NOISY : MIMXRT1062.h
- LPUART_DATA_NOISY_MASK : MIMXRT1062.h
- LPUART_DATA_NOISY_SHIFT : MIMXRT1062.h
- LPUART_DATA_PARITYE : MIMXRT1062.h
- LPUART_DATA_PARITYE_MASK : MIMXRT1062.h
- LPUART_DATA_PARITYE_SHIFT : MIMXRT1062.h
- LPUART_DATA_R0T0 : MIMXRT1062.h
- LPUART_DATA_R0T0_MASK : MIMXRT1062.h
- LPUART_DATA_R0T0_SHIFT : MIMXRT1062.h
- LPUART_DATA_R1T1 : MIMXRT1062.h
- LPUART_DATA_R1T1_MASK : MIMXRT1062.h
- LPUART_DATA_R1T1_SHIFT : MIMXRT1062.h
- LPUART_DATA_R2T2 : MIMXRT1062.h
- LPUART_DATA_R2T2_MASK : MIMXRT1062.h
- LPUART_DATA_R2T2_SHIFT : MIMXRT1062.h
- LPUART_DATA_R3T3 : MIMXRT1062.h
- LPUART_DATA_R3T3_MASK : MIMXRT1062.h
- LPUART_DATA_R3T3_SHIFT : MIMXRT1062.h
- LPUART_DATA_R4T4 : MIMXRT1062.h
- LPUART_DATA_R4T4_MASK : MIMXRT1062.h
- LPUART_DATA_R4T4_SHIFT : MIMXRT1062.h
- LPUART_DATA_R5T5 : MIMXRT1062.h
- LPUART_DATA_R5T5_MASK : MIMXRT1062.h
- LPUART_DATA_R5T5_SHIFT : MIMXRT1062.h
- LPUART_DATA_R6T6 : MIMXRT1062.h
- LPUART_DATA_R6T6_MASK : MIMXRT1062.h
- LPUART_DATA_R6T6_SHIFT : MIMXRT1062.h
- LPUART_DATA_R7T7 : MIMXRT1062.h
- LPUART_DATA_R7T7_MASK : MIMXRT1062.h
- LPUART_DATA_R7T7_SHIFT : MIMXRT1062.h
- LPUART_DATA_R8T8 : MIMXRT1062.h
- LPUART_DATA_R8T8_MASK : MIMXRT1062.h
- LPUART_DATA_R8T8_SHIFT : MIMXRT1062.h
- LPUART_DATA_R9T9 : MIMXRT1062.h
- LPUART_DATA_R9T9_MASK : MIMXRT1062.h
- LPUART_DATA_R9T9_SHIFT : MIMXRT1062.h
- LPUART_DATA_RXEMPT : MIMXRT1062.h
- LPUART_DATA_RXEMPT_MASK : MIMXRT1062.h
- LPUART_DATA_RXEMPT_SHIFT : MIMXRT1062.h
- LPUART_FIFO_RXEMPT : MIMXRT1062.h
- LPUART_FIFO_RXEMPT_MASK : MIMXRT1062.h
- LPUART_FIFO_RXEMPT_SHIFT : MIMXRT1062.h
- LPUART_FIFO_RXFE : MIMXRT1062.h
- LPUART_FIFO_RXFE_MASK : MIMXRT1062.h
- LPUART_FIFO_RXFE_SHIFT : MIMXRT1062.h
- LPUART_FIFO_RXFIFOSIZE : MIMXRT1062.h
- LPUART_FIFO_RXFIFOSIZE_MASK : MIMXRT1062.h
- LPUART_FIFO_RXFIFOSIZE_SHIFT : MIMXRT1062.h
- LPUART_FIFO_RXFLUSH : MIMXRT1062.h
- LPUART_FIFO_RXFLUSH_MASK : MIMXRT1062.h
- LPUART_FIFO_RXFLUSH_SHIFT : MIMXRT1062.h
- LPUART_FIFO_RXIDEN : MIMXRT1062.h
- LPUART_FIFO_RXIDEN_MASK : MIMXRT1062.h
- LPUART_FIFO_RXIDEN_SHIFT : MIMXRT1062.h
- LPUART_FIFO_RXUF : MIMXRT1062.h
- LPUART_FIFO_RXUF_MASK : MIMXRT1062.h
- LPUART_FIFO_RXUF_SHIFT : MIMXRT1062.h
- LPUART_FIFO_RXUFE : MIMXRT1062.h
- LPUART_FIFO_RXUFE_MASK : MIMXRT1062.h
- LPUART_FIFO_RXUFE_SHIFT : MIMXRT1062.h
- LPUART_FIFO_TXEMPT : MIMXRT1062.h
- LPUART_FIFO_TXEMPT_MASK : MIMXRT1062.h
- LPUART_FIFO_TXEMPT_SHIFT : MIMXRT1062.h
- LPUART_FIFO_TXFE : MIMXRT1062.h
- LPUART_FIFO_TXFE_MASK : MIMXRT1062.h
- LPUART_FIFO_TXFE_SHIFT : MIMXRT1062.h
- LPUART_FIFO_TXFIFOSIZE : MIMXRT1062.h
- LPUART_FIFO_TXFIFOSIZE_MASK : MIMXRT1062.h
- LPUART_FIFO_TXFIFOSIZE_SHIFT : MIMXRT1062.h
- LPUART_FIFO_TXFLUSH : MIMXRT1062.h
- LPUART_FIFO_TXFLUSH_MASK : MIMXRT1062.h
- LPUART_FIFO_TXFLUSH_SHIFT : MIMXRT1062.h
- LPUART_FIFO_TXOF : MIMXRT1062.h
- LPUART_FIFO_TXOF_MASK : MIMXRT1062.h
- LPUART_FIFO_TXOF_SHIFT : MIMXRT1062.h
- LPUART_FIFO_TXOFE : MIMXRT1062.h
- LPUART_FIFO_TXOFE_MASK : MIMXRT1062.h
- LPUART_FIFO_TXOFE_SHIFT : MIMXRT1062.h
- LPUART_GLOBAL_RST : MIMXRT1062.h
- LPUART_GLOBAL_RST_MASK : MIMXRT1062.h
- LPUART_GLOBAL_RST_SHIFT : MIMXRT1062.h
- LPUART_MATCH_MA1 : MIMXRT1062.h
- LPUART_MATCH_MA1_MASK : MIMXRT1062.h
- LPUART_MATCH_MA1_SHIFT : MIMXRT1062.h
- LPUART_MATCH_MA2 : MIMXRT1062.h
- LPUART_MATCH_MA2_MASK : MIMXRT1062.h
- LPUART_MATCH_MA2_SHIFT : MIMXRT1062.h
- LPUART_MODIR_IREN : MIMXRT1062.h
- LPUART_MODIR_IREN_MASK : MIMXRT1062.h
- LPUART_MODIR_IREN_SHIFT : MIMXRT1062.h
- LPUART_MODIR_RTSWATER : MIMXRT1062.h
- LPUART_MODIR_RTSWATER_MASK : MIMXRT1062.h
- LPUART_MODIR_RTSWATER_SHIFT : MIMXRT1062.h
- LPUART_MODIR_RXRTSE : MIMXRT1062.h
- LPUART_MODIR_RXRTSE_MASK : MIMXRT1062.h
- LPUART_MODIR_RXRTSE_SHIFT : MIMXRT1062.h
- LPUART_MODIR_TNP : MIMXRT1062.h
- LPUART_MODIR_TNP_MASK : MIMXRT1062.h
- LPUART_MODIR_TNP_SHIFT : MIMXRT1062.h
- LPUART_MODIR_TXCTSC : MIMXRT1062.h
- LPUART_MODIR_TXCTSC_MASK : MIMXRT1062.h
- LPUART_MODIR_TXCTSC_SHIFT : MIMXRT1062.h
- LPUART_MODIR_TXCTSE : MIMXRT1062.h
- LPUART_MODIR_TXCTSE_MASK : MIMXRT1062.h
- LPUART_MODIR_TXCTSE_SHIFT : MIMXRT1062.h
- LPUART_MODIR_TXCTSSRC : MIMXRT1062.h
- LPUART_MODIR_TXCTSSRC_MASK : MIMXRT1062.h
- LPUART_MODIR_TXCTSSRC_SHIFT : MIMXRT1062.h
- LPUART_MODIR_TXRTSE : MIMXRT1062.h
- LPUART_MODIR_TXRTSE_MASK : MIMXRT1062.h
- LPUART_MODIR_TXRTSE_SHIFT : MIMXRT1062.h
- LPUART_MODIR_TXRTSPOL : MIMXRT1062.h
- LPUART_MODIR_TXRTSPOL_MASK : MIMXRT1062.h
- LPUART_MODIR_TXRTSPOL_SHIFT : MIMXRT1062.h
- LPUART_PARAM_RXFIFO : MIMXRT1062.h
- LPUART_PARAM_RXFIFO_MASK : MIMXRT1062.h
- LPUART_PARAM_RXFIFO_SHIFT : MIMXRT1062.h
- LPUART_PARAM_TXFIFO : MIMXRT1062.h
- LPUART_PARAM_TXFIFO_MASK : MIMXRT1062.h
- LPUART_PARAM_TXFIFO_SHIFT : MIMXRT1062.h
- LPUART_PINCFG_TRGSEL : MIMXRT1062.h
- LPUART_PINCFG_TRGSEL_MASK : MIMXRT1062.h
- LPUART_PINCFG_TRGSEL_SHIFT : MIMXRT1062.h
- LPUART_RX_TX_IRQS : MIMXRT1062.h
- LPUART_STAT_BRK13 : MIMXRT1062.h
- LPUART_STAT_BRK13_MASK : MIMXRT1062.h
- LPUART_STAT_BRK13_SHIFT : MIMXRT1062.h
- LPUART_STAT_FE : MIMXRT1062.h
- LPUART_STAT_FE_MASK : MIMXRT1062.h
- LPUART_STAT_FE_SHIFT : MIMXRT1062.h
- LPUART_STAT_IDLE : MIMXRT1062.h
- LPUART_STAT_IDLE_MASK : MIMXRT1062.h
- LPUART_STAT_IDLE_SHIFT : MIMXRT1062.h
- LPUART_STAT_LBKDE : MIMXRT1062.h
- LPUART_STAT_LBKDE_MASK : MIMXRT1062.h
- LPUART_STAT_LBKDE_SHIFT : MIMXRT1062.h
- LPUART_STAT_LBKDIF : MIMXRT1062.h
- LPUART_STAT_LBKDIF_MASK : MIMXRT1062.h
- LPUART_STAT_LBKDIF_SHIFT : MIMXRT1062.h
- LPUART_STAT_MA1F : MIMXRT1062.h
- LPUART_STAT_MA1F_MASK : MIMXRT1062.h
- LPUART_STAT_MA1F_SHIFT : MIMXRT1062.h
- LPUART_STAT_MA2F : MIMXRT1062.h
- LPUART_STAT_MA2F_MASK : MIMXRT1062.h
- LPUART_STAT_MA2F_SHIFT : MIMXRT1062.h
- LPUART_STAT_MSBF : MIMXRT1062.h
- LPUART_STAT_MSBF_MASK : MIMXRT1062.h
- LPUART_STAT_MSBF_SHIFT : MIMXRT1062.h
- LPUART_STAT_NF : MIMXRT1062.h
- LPUART_STAT_NF_MASK : MIMXRT1062.h
- LPUART_STAT_NF_SHIFT : MIMXRT1062.h
- LPUART_STAT_OR : MIMXRT1062.h
- LPUART_STAT_OR_MASK : MIMXRT1062.h
- LPUART_STAT_OR_SHIFT : MIMXRT1062.h
- LPUART_STAT_PF : MIMXRT1062.h
- LPUART_STAT_PF_MASK : MIMXRT1062.h
- LPUART_STAT_PF_SHIFT : MIMXRT1062.h
- LPUART_STAT_RAF : MIMXRT1062.h
- LPUART_STAT_RAF_MASK : MIMXRT1062.h
- LPUART_STAT_RAF_SHIFT : MIMXRT1062.h
- LPUART_STAT_RDRF : MIMXRT1062.h
- LPUART_STAT_RDRF_MASK : MIMXRT1062.h
- LPUART_STAT_RDRF_SHIFT : MIMXRT1062.h
- LPUART_STAT_RWUID : MIMXRT1062.h
- LPUART_STAT_RWUID_MASK : MIMXRT1062.h
- LPUART_STAT_RWUID_SHIFT : MIMXRT1062.h
- LPUART_STAT_RXEDGIF : MIMXRT1062.h
- LPUART_STAT_RXEDGIF_MASK : MIMXRT1062.h
- LPUART_STAT_RXEDGIF_SHIFT : MIMXRT1062.h
- LPUART_STAT_RXINV : MIMXRT1062.h
- LPUART_STAT_RXINV_MASK : MIMXRT1062.h
- LPUART_STAT_RXINV_SHIFT : MIMXRT1062.h
- LPUART_STAT_TC : MIMXRT1062.h
- LPUART_STAT_TC_MASK : MIMXRT1062.h
- LPUART_STAT_TC_SHIFT : MIMXRT1062.h
- LPUART_STAT_TDRE : MIMXRT1062.h
- LPUART_STAT_TDRE_MASK : MIMXRT1062.h
- LPUART_STAT_TDRE_SHIFT : MIMXRT1062.h
- LPUART_VERID_FEATURE : MIMXRT1062.h
- LPUART_VERID_FEATURE_MASK : MIMXRT1062.h
- LPUART_VERID_FEATURE_SHIFT : MIMXRT1062.h
- LPUART_VERID_MAJOR : MIMXRT1062.h
- LPUART_VERID_MAJOR_MASK : MIMXRT1062.h
- LPUART_VERID_MAJOR_SHIFT : MIMXRT1062.h
- LPUART_VERID_MINOR : MIMXRT1062.h
- LPUART_VERID_MINOR_MASK : MIMXRT1062.h
- LPUART_VERID_MINOR_SHIFT : MIMXRT1062.h
- LPUART_WATER_RXCOUNT : MIMXRT1062.h
- LPUART_WATER_RXCOUNT_MASK : MIMXRT1062.h
- LPUART_WATER_RXCOUNT_SHIFT : MIMXRT1062.h
- LPUART_WATER_RXWATER : MIMXRT1062.h
- LPUART_WATER_RXWATER_MASK : MIMXRT1062.h
- LPUART_WATER_RXWATER_SHIFT : MIMXRT1062.h
- LPUART_WATER_TXCOUNT : MIMXRT1062.h
- LPUART_WATER_TXCOUNT_MASK : MIMXRT1062.h
- LPUART_WATER_TXCOUNT_SHIFT : MIMXRT1062.h
- LPUART_WATER_TXWATER : MIMXRT1062.h
- LPUART_WATER_TXWATER_MASK : MIMXRT1062.h
- LPUART_WATER_TXWATER_SHIFT : MIMXRT1062.h