Callisto4Bootloader: Cortex M7 Core Configuration

Callisto4Bootloader

Macros
Cortex M7 Core Configuration

## Macros

#define | __MPU_PRESENT 1
#define | __ICACHE_PRESENT 1
#define | __DCACHE_PRESENT 1
#define | __DTCM_PRESENT 1
#define | __NVIC_PRIO_BITS 4
#define | __Vendor_SysTickConfig 0
#define | __FPU_PRESENT 1

## Detailed Description

## Macro Definition Documentation

## ◆ __DCACHE_PRESENT

#define __DCACHE_PRESENT 1

Defines if an DCACHE is present or not

Definition at line 266 of file MIMXRT1062.h.

## ◆ __DTCM_PRESENT

#define __DTCM_PRESENT 1

Defines if an DTCM is present or not

Definition at line 267 of file MIMXRT1062.h.

## ◆ __FPU_PRESENT

#define __FPU_PRESENT 1

Defines if an FPU is present or not

Definition at line 270 of file MIMXRT1062.h.

## ◆ __ICACHE_PRESENT

#define __ICACHE_PRESENT 1

Defines if an ICACHE is present or not

Definition at line 265 of file MIMXRT1062.h.

## ◆ __MPU_PRESENT

#define __MPU_PRESENT 1

Defines if an MPU is present or not

Definition at line 264 of file MIMXRT1062.h.

## ◆ __NVIC_PRIO_BITS

#define __NVIC_PRIO_BITS 4

Number of priority bits implemented in the NVIC

Definition at line 268 of file MIMXRT1062.h.

## ◆ __Vendor_SysTickConfig

#define __Vendor_SysTickConfig 0

Vendor specific implementation of SysTickConfig is defined

Definition at line 269 of file MIMXRT1062.h.