Callisto4Bootloader: CSI Register Masks

Callisto4Bootloader

CSI Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » CSI Peripheral Access Layer

## CSICR1 - CSI Control Register 1

#define | CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
#define | CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
#define | CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
#define | CSI_CSICR1_REDGE_MASK (0x2U)
#define | CSI_CSICR1_REDGE_SHIFT (1U)
#define | CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
#define | CSI_CSICR1_INV_PCLK_MASK (0x4U)
#define | CSI_CSICR1_INV_PCLK_SHIFT (2U)
#define | CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
#define | CSI_CSICR1_INV_DATA_MASK (0x8U)
#define | CSI_CSICR1_INV_DATA_SHIFT (3U)
#define | CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
#define | CSI_CSICR1_GCLK_MODE_MASK (0x10U)
#define | CSI_CSICR1_GCLK_MODE_SHIFT (4U)
#define | CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
#define | CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
#define | CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
#define | CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
#define | CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
#define | CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
#define | CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
#define | CSI_CSICR1_PACK_DIR_MASK (0x80U)
#define | CSI_CSICR1_PACK_DIR_SHIFT (7U)
#define | CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
#define | CSI_CSICR1_FCC_MASK (0x100U)
#define | CSI_CSICR1_FCC_SHIFT (8U)
#define | CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
#define | CSI_CSICR1_CCIR_EN_MASK (0x400U)
#define | CSI_CSICR1_CCIR_EN_SHIFT (10U)
#define | CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
#define | CSI_CSICR1_HSYNC_POL_MASK (0x800U)
#define | CSI_CSICR1_HSYNC_POL_SHIFT (11U)
#define | CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
#define | CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
#define | CSI_CSICR1_SOF_INTEN_SHIFT (16U)
#define | CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
#define | CSI_CSICR1_SOF_POL_MASK (0x20000U)
#define | CSI_CSICR1_SOF_POL_SHIFT (17U)
#define | CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
#define | CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
#define | CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
#define | CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
#define | CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
#define | CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
#define | CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
#define | CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
#define | CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
#define | CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
#define | CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
#define | CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
#define | CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
#define | CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
#define | CSI_CSICR1_COF_INT_EN_SHIFT (26U)
#define | CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
#define | CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)
#define | CSI_CSICR1_CCIR_MODE_SHIFT (27U)
#define | CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
#define | CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
#define | CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
#define | CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
#define | CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
#define | CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
#define | CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
#define | CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
#define | CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
#define | CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
#define | CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
#define | CSI_CSICR1_SWAP16_EN_SHIFT (31U)
#define | CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)

## CSICR2 - CSI Control Register 2

#define | CSI_CSICR2_HSC_MASK (0xFFU)
#define | CSI_CSICR2_HSC_SHIFT (0U)
#define | CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
#define | CSI_CSICR2_VSC_MASK (0xFF00U)
#define | CSI_CSICR2_VSC_SHIFT (8U)
#define | CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
#define | CSI_CSICR2_LVRM_MASK (0x70000U)
#define | CSI_CSICR2_LVRM_SHIFT (16U)
#define | CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
#define | CSI_CSICR2_BTS_MASK (0x180000U)
#define | CSI_CSICR2_BTS_SHIFT (19U)
#define | CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
#define | CSI_CSICR2_SCE_MASK (0x800000U)
#define | CSI_CSICR2_SCE_SHIFT (23U)
#define | CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
#define | CSI_CSICR2_AFS_MASK (0x3000000U)
#define | CSI_CSICR2_AFS_SHIFT (24U)
#define | CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
#define | CSI_CSICR2_DRM_MASK (0x4000000U)
#define | CSI_CSICR2_DRM_SHIFT (26U)
#define | CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)

## CSICR3 - CSI Control Register 3

#define | CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
#define | CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
#define | CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
#define | CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
#define | CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
#define | CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
#define | CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
#define | CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
#define | CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
#define | CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
#define | CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
#define | CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
#define | CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
#define | CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
#define | CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
#define | CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
#define | CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
#define | CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
#define | CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
#define | CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
#define | CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
#define | CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
#define | CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
#define | CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
#define | CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
#define | CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
#define | CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
#define | CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
#define | CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
#define | CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
#define | CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
#define | CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
#define | CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
#define | CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
#define | CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
#define | CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
#define | CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
#define | CSI_CSICR3_FRMCNT_SHIFT (16U)
#define | CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)

## CSISTATFIFO - CSI Statistic FIFO Register

#define | CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
#define | CSI_CSISTATFIFO_STAT_SHIFT (0U)
#define | CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)

## CSIRFIFO - CSI RX FIFO Register

#define | CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
#define | CSI_CSIRFIFO_IMAGE_SHIFT (0U)
#define | CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)

## CSIRXCNT - CSI RX Count Register

#define | CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
#define | CSI_CSIRXCNT_RXCNT_SHIFT (0U)
#define | CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)

## CSISR - CSI Status Register

#define | CSI_CSISR_DRDY_MASK (0x1U)
#define | CSI_CSISR_DRDY_SHIFT (0U)
#define | CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
#define | CSI_CSISR_ECC_INT_MASK (0x2U)
#define | CSI_CSISR_ECC_INT_SHIFT (1U)
#define | CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
#define | CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
#define | CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
#define | CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
#define | CSI_CSISR_COF_INT_MASK (0x2000U)
#define | CSI_CSISR_COF_INT_SHIFT (13U)
#define | CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
#define | CSI_CSISR_F1_INT_MASK (0x4000U)
#define | CSI_CSISR_F1_INT_SHIFT (14U)
#define | CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
#define | CSI_CSISR_F2_INT_MASK (0x8000U)
#define | CSI_CSISR_F2_INT_SHIFT (15U)
#define | CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
#define | CSI_CSISR_SOF_INT_MASK (0x10000U)
#define | CSI_CSISR_SOF_INT_SHIFT (16U)
#define | CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
#define | CSI_CSISR_EOF_INT_MASK (0x20000U)
#define | CSI_CSISR_EOF_INT_SHIFT (17U)
#define | CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
#define | CSI_CSISR_RxFF_INT_MASK (0x40000U)
#define | CSI_CSISR_RxFF_INT_SHIFT (18U)
#define | CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
#define | CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
#define | CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
#define | CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
#define | CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
#define | CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
#define | CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
#define | CSI_CSISR_STATFF_INT_MASK (0x200000U)
#define | CSI_CSISR_STATFF_INT_SHIFT (21U)
#define | CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
#define | CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
#define | CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
#define | CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
#define | CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
#define | CSI_CSISR_RF_OR_INT_SHIFT (24U)
#define | CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
#define | CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
#define | CSI_CSISR_SF_OR_INT_SHIFT (25U)
#define | CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
#define | CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
#define | CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
#define | CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
#define | CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
#define | CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
#define | CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)

## CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO

#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)

## CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO

#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)

## CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1

#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)

## CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2

#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)

## CSIFBUF_PARA - CSI Frame Buffer Parameter Register

#define | CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
#define | CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
#define | CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)

## CSIIMAG_PARA - CSI Image Parameter Register

#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)

## CSICR18 - CSI Control Register 18

#define | CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
#define | CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
#define | CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
#define | CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
#define | CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
#define | CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
#define | CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
#define | CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
#define | CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
#define | CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
#define | CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
#define | CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
#define | CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
#define | CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
#define | CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
#define | CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
#define | CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
#define | CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
#define | CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
#define | CSI_CSICR18_AHB_HPROT_SHIFT (12U)
#define | CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
#define | CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
#define | CSI_CSICR18_MASK_OPTION_SHIFT (18U)
#define | CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
#define | CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
#define | CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
#define | CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)

## CSICR19 - CSI Control Register 19

#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ CSI_CSICR18_AHB_HPROT

#define CSI_CSICR18_AHB_HPROT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)

Definition at line 10598 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_AHB_HPROT_MASK

#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U)

Definition at line 10596 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_AHB_HPROT_SHIFT

#define CSI_CSICR18_AHB_HPROT_SHIFT (12U)

Definition at line 10597 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE

#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)

Definition at line 10588 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK

#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)

Definition at line 10586 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT

#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)

Definition at line 10587 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_SWITCH_EN

#define CSI_CSICR18_BASEADDR_SWITCH_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)

Definition at line 10557 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_SWITCH_EN_MASK

#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)

Definition at line 10555 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT

#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)

Definition at line 10556 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_SWITCH_SEL

#define CSI_CSICR18_BASEADDR_SWITCH_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)

BASEADDR_SWITCH_SEL 0b0..Switching base address at the edge of the vsync 0b1..Switching base address at the edge of the first data of each frame

Definition at line 10564 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK

#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)

Definition at line 10558 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT

#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)

Definition at line 10559 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_CSI_ENABLE

#define CSI_CSICR18_CSI_ENABLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)

Definition at line 10610 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_CSI_ENABLE_MASK

#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)

Definition at line 10608 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_CSI_ENABLE_SHIFT

#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U)

Definition at line 10609 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_DEINTERLACE_EN

#define CSI_CSICR18_DEINTERLACE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)

DEINTERLACE_EN 0b0..Deinterlace disabled 0b1..Deinterlace enabled

Definition at line 10551 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_DEINTERLACE_EN_MASK

#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)

Definition at line 10545 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_DEINTERLACE_EN_SHIFT

#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)

Definition at line 10546 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_DMA_FIELD1_DONE_IE

#define CSI_CSICR18_DMA_FIELD1_DONE_IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)

DMA_FIELD1_DONE_IE 0b0..Interrupt disabled 0b1..Interrupt enabled

Definition at line 10578 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK

#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)

Definition at line 10572 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT

#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)

Definition at line 10573 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_FIELD0_DONE_IE

#define CSI_CSICR18_FIELD0_DONE_IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)

FIELD0_DONE_IE 0b0..Interrupt disabled 0b1..Interrupt enabled

Definition at line 10571 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_FIELD0_DONE_IE_MASK

#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)

Definition at line 10565 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_FIELD0_DONE_IE_SHIFT

#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)

Definition at line 10566 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_LAST_DMA_REQ_SEL

#define CSI_CSICR18_LAST_DMA_REQ_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)

LAST_DMA_REQ_SEL 0b0..fifo_full_level 0b1..hburst_length

Definition at line 10585 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_LAST_DMA_REQ_SEL_MASK

#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)

Definition at line 10579 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT

#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)

Definition at line 10580 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_MASK_OPTION

#define CSI_CSICR18_MASK_OPTION | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)

MASK_OPTION 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. 0b01..Writing to memory when CSI_ENABLE is 1. 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.

Definition at line 10607 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_MASK_OPTION_MASK

#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)

Definition at line 10599 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_MASK_OPTION_SHIFT

#define CSI_CSICR18_MASK_OPTION_SHIFT (18U)

Definition at line 10600 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_PARALLEL24_EN

#define CSI_CSICR18_PARALLEL24_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)

Definition at line 10554 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_PARALLEL24_EN_MASK

#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)

Definition at line 10552 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_PARALLEL24_EN_SHIFT

#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)

Definition at line 10553 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_RGB888A_FORMAT_SEL

#define CSI_CSICR18_RGB888A_FORMAT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)

RGB888A_FORMAT_SEL 0b0..{8'h0, data[23:0]} 0b1..{data[23:0], 8'h0}

Definition at line 10595 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_RGB888A_FORMAT_SEL_MASK

#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)

Definition at line 10589 of file MIMXRT1062.h.

## ◆ CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT

#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)

Definition at line 10590 of file MIMXRT1062.h.

## ◆ CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL

#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)

Definition at line 10617 of file MIMXRT1062.h.

## ◆ CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK

#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)

Definition at line 10615 of file MIMXRT1062.h.

## ◆ CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT

#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)

Definition at line 10616 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CCIR_EN

#define CSI_CSICR1_CCIR_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)

CCIR_EN 0b0..Traditional interface is selected. Timing interface logic is used to latch data. 0b1..CCIR656 interface is selected.

Definition at line 10069 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CCIR_EN_MASK

#define CSI_CSICR1_CCIR_EN_MASK (0x400U)

Definition at line 10063 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CCIR_EN_SHIFT

#define CSI_CSICR1_CCIR_EN_SHIFT (10U)

Definition at line 10064 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CCIR_MODE

#define CSI_CSICR1_CCIR_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)

CCIR_MODE 0b0..Progressive mode is selected 0b1..Interlace mode is selected

Definition at line 10153 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CCIR_MODE_MASK

#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)

Definition at line 10147 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CCIR_MODE_SHIFT

#define CSI_CSICR1_CCIR_MODE_SHIFT (27U)

Definition at line 10148 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CLR_RXFIFO

#define CSI_CSICR1_CLR_RXFIFO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)

Definition at line 10043 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CLR_RXFIFO_MASK

#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)

Definition at line 10041 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CLR_RXFIFO_SHIFT

#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)

Definition at line 10042 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CLR_STATFIFO

#define CSI_CSICR1_CLR_STATFIFO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)

Definition at line 10046 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CLR_STATFIFO_MASK

#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)

Definition at line 10044 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_CLR_STATFIFO_SHIFT

#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)

Definition at line 10045 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_COF_INT_EN

#define CSI_CSICR1_COF_INT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)

COF_INT_EN 0b0..COF interrupt is disabled 0b1..COF interrupt is enabled

Definition at line 10146 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_COF_INT_EN_MASK

#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)

Definition at line 10140 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_COF_INT_EN_SHIFT

#define CSI_CSICR1_COF_INT_EN_SHIFT (26U)

Definition at line 10141 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_EOF_INT_EN

#define CSI_CSICR1_EOF_INT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)

EOF_INT_EN 0b0..EOF interrupt is disabled. 0b1..EOF interrupt is generated when RX count value is reached.

Definition at line 10167 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_EOF_INT_EN_MASK

#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)

Definition at line 10161 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_EOF_INT_EN_SHIFT

#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U)

Definition at line 10162 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_EXT_VSYNC

#define CSI_CSICR1_EXT_VSYNC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)

EXT_VSYNC 0b0..Internal VSYNC mode 0b1..External VSYNC mode

Definition at line 10174 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_EXT_VSYNC_MASK

#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)

Definition at line 10168 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_EXT_VSYNC_SHIFT

#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U)

Definition at line 10169 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FB1_DMA_DONE_INTEN

#define CSI_CSICR1_FB1_DMA_DONE_INTEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)

FB1_DMA_DONE_INTEN 0b0..Frame Buffer1 DMA Transfer Done interrupt disable 0b1..Frame Buffer1 DMA Transfer Done interrupt enable

Definition at line 10104 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK

#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)

Definition at line 10098 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT

#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)

Definition at line 10099 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FB2_DMA_DONE_INTEN

#define CSI_CSICR1_FB2_DMA_DONE_INTEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)

FB2_DMA_DONE_INTEN 0b0..Frame Buffer2 DMA Transfer Done interrupt disable 0b1..Frame Buffer2 DMA Transfer Done interrupt enable

Definition at line 10111 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK

#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)

Definition at line 10105 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT

#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)

Definition at line 10106 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FCC

#define CSI_CSICR1_FCC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)

FCC 0b0..Asynchronous FIFO clear is selected. 0b1..Synchronous FIFO clear is selected.

Definition at line 10062 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FCC_MASK

#define CSI_CSICR1_FCC_MASK (0x100U)

Definition at line 10056 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_FCC_SHIFT

#define CSI_CSICR1_FCC_SHIFT (8U)

Definition at line 10057 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_GCLK_MODE

#define CSI_CSICR1_GCLK_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)

GCLK_MODE 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.

Definition at line 10040 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_GCLK_MODE_MASK

#define CSI_CSICR1_GCLK_MODE_MASK (0x10U)

Definition at line 10034 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_GCLK_MODE_SHIFT

#define CSI_CSICR1_GCLK_MODE_SHIFT (4U)

Definition at line 10035 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_HSYNC_POL

#define CSI_CSICR1_HSYNC_POL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)

HSYNC_POL 0b0..HSYNC is active low 0b1..HSYNC is active high

Definition at line 10076 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_HSYNC_POL_MASK

#define CSI_CSICR1_HSYNC_POL_MASK (0x800U)

Definition at line 10070 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_HSYNC_POL_SHIFT

#define CSI_CSICR1_HSYNC_POL_SHIFT (11U)

Definition at line 10071 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_INV_DATA

#define CSI_CSICR1_INV_DATA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)

INV_DATA 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry

Definition at line 10033 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_INV_DATA_MASK

#define CSI_CSICR1_INV_DATA_MASK (0x8U)

Definition at line 10027 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_INV_DATA_SHIFT

#define CSI_CSICR1_INV_DATA_SHIFT (3U)

Definition at line 10028 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_INV_PCLK

#define CSI_CSICR1_INV_PCLK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)

INV_PCLK 0b0..CSI_PIXCLK is directly applied to internal circuitry 0b1..CSI_PIXCLK is inverted before applied to internal circuitry

Definition at line 10026 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_INV_PCLK_MASK

#define CSI_CSICR1_INV_PCLK_MASK (0x4U)

Definition at line 10020 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_INV_PCLK_SHIFT

#define CSI_CSICR1_INV_PCLK_SHIFT (2U)

Definition at line 10021 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PACK_DIR

#define CSI_CSICR1_PACK_DIR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)

PACK_DIR 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.

Definition at line 10055 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PACK_DIR_MASK

#define CSI_CSICR1_PACK_DIR_MASK (0x80U)

Definition at line 10047 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PACK_DIR_SHIFT

#define CSI_CSICR1_PACK_DIR_SHIFT (7U)

Definition at line 10048 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PIXEL_BIT

#define CSI_CSICR1_PIXEL_BIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)

PIXEL_BIT 0b0..8-bit data for each pixel 0b1..10-bit data for each pixel

Definition at line 10012 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PIXEL_BIT_MASK

#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U)

Definition at line 10006 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PIXEL_BIT_SHIFT

#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U)

Definition at line 10007 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PrP_IF_EN

#define CSI_CSICR1_PrP_IF_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)

PrP_IF_EN 0b0..CSI to PrP bus is disabled 0b1..CSI to PrP bus is enabled

Definition at line 10160 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PrP_IF_EN_MASK

#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)

Definition at line 10154 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_PrP_IF_EN_SHIFT

#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U)

Definition at line 10155 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_REDGE

#define CSI_CSICR1_REDGE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)

REDGE 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK

Definition at line 10019 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_REDGE_MASK

#define CSI_CSICR1_REDGE_MASK (0x2U)

Definition at line 10013 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_REDGE_SHIFT

#define CSI_CSICR1_REDGE_SHIFT (1U)

Definition at line 10014 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_RF_OR_INTEN

#define CSI_CSICR1_RF_OR_INTEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)

RF_OR_INTEN 0b0..RxFIFO overrun interrupt is disabled 0b1..RxFIFO overrun interrupt is enabled

Definition at line 10132 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_RF_OR_INTEN_MASK

#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)

Definition at line 10126 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_RF_OR_INTEN_SHIFT

#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)

Definition at line 10127 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_RXFF_INTEN

#define CSI_CSICR1_RXFF_INTEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)

RXFF_INTEN 0b0..RxFIFO full interrupt disable 0b1..RxFIFO full interrupt enable

Definition at line 10097 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_RXFF_INTEN_MASK

#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)

Definition at line 10091 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_RXFF_INTEN_SHIFT

#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U)

Definition at line 10092 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SF_OR_INTEN

#define CSI_CSICR1_SF_OR_INTEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)

SF_OR_INTEN 0b0..STATFIFO overrun interrupt is disabled 0b1..STATFIFO overrun interrupt is enabled

Definition at line 10139 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SF_OR_INTEN_MASK

#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)

Definition at line 10133 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SF_OR_INTEN_SHIFT

#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)

Definition at line 10134 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SFF_DMA_DONE_INTEN

#define CSI_CSICR1_SFF_DMA_DONE_INTEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)

SFF_DMA_DONE_INTEN 0b0..STATFIFO DMA Transfer Done interrupt disable 0b1..STATFIFO DMA Transfer Done interrupt enable

Definition at line 10125 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK

#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)

Definition at line 10119 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT

#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)

Definition at line 10120 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SOF_INTEN

#define CSI_CSICR1_SOF_INTEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)

SOF_INTEN 0b0..SOF interrupt disable 0b1..SOF interrupt enable

Definition at line 10083 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SOF_INTEN_MASK

#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U)

Definition at line 10077 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SOF_INTEN_SHIFT

#define CSI_CSICR1_SOF_INTEN_SHIFT (16U)

Definition at line 10078 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SOF_POL

#define CSI_CSICR1_SOF_POL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)

SOF_POL 0b0..SOF interrupt is generated on SOF falling edge 0b1..SOF interrupt is generated on SOF rising edge

Definition at line 10090 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SOF_POL_MASK

#define CSI_CSICR1_SOF_POL_MASK (0x20000U)

Definition at line 10084 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SOF_POL_SHIFT

#define CSI_CSICR1_SOF_POL_SHIFT (17U)

Definition at line 10085 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_STATFF_INTEN

#define CSI_CSICR1_STATFF_INTEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)

STATFF_INTEN 0b0..STATFIFO full interrupt disable 0b1..STATFIFO full interrupt enable

Definition at line 10118 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_STATFF_INTEN_MASK

#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)

Definition at line 10112 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_STATFF_INTEN_SHIFT

#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U)

Definition at line 10113 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SWAP16_EN

#define CSI_CSICR1_SWAP16_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)

SWAP16_EN 0b0..Disable swapping 0b1..Enable swapping

Definition at line 10181 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SWAP16_EN_MASK

#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)

Definition at line 10175 of file MIMXRT1062.h.

## ◆ CSI_CSICR1_SWAP16_EN_SHIFT

#define CSI_CSICR1_SWAP16_EN_SHIFT (31U)

Definition at line 10176 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_AFS

#define CSI_CSICR2_AFS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)

AFS 0b00..Abs Diff on consecutive green pixels 0b01..Abs Diff on every third green pixels 0b1x..Abs Diff on every four green pixels

Definition at line 10227 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_AFS_MASK

#define CSI_CSICR2_AFS_MASK (0x3000000U)

Definition at line 10220 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_AFS_SHIFT

#define CSI_CSICR2_AFS_SHIFT (24U)

Definition at line 10221 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_BTS

#define CSI_CSICR2_BTS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)

BTS 0b00..GR 0b01..RG 0b10..BG 0b11..GB

Definition at line 10212 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_BTS_MASK

#define CSI_CSICR2_BTS_MASK (0x180000U)

Definition at line 10204 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_BTS_SHIFT

#define CSI_CSICR2_BTS_SHIFT (19U)

Definition at line 10205 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DMA_BURST_TYPE_RFF

#define CSI_CSICR2_DMA_BURST_TYPE_RFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)

DMA_BURST_TYPE_RFF 0bx0..INCR8 0b01..INCR4 0b11..INCR16

Definition at line 10250 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK

#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)

Definition at line 10243 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT

#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)

Definition at line 10244 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DMA_BURST_TYPE_SFF

#define CSI_CSICR2_DMA_BURST_TYPE_SFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)

DMA_BURST_TYPE_SFF 0bx0..INCR8 0b01..INCR4 0b11..INCR16

Definition at line 10242 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK

#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)

Definition at line 10235 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT

#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)

Definition at line 10236 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DRM

#define CSI_CSICR2_DRM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)

DRM 0b0..Stats grid of 8 x 6 0b1..Stats grid of 8 x 12

Definition at line 10234 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DRM_MASK

#define CSI_CSICR2_DRM_MASK (0x4000000U)

Definition at line 10228 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_DRM_SHIFT

#define CSI_CSICR2_DRM_SHIFT (26U)

Definition at line 10229 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_HSC

#define CSI_CSICR2_HSC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)

Definition at line 10188 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_HSC_MASK

#define CSI_CSICR2_HSC_MASK (0xFFU)

Definition at line 10186 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_HSC_SHIFT

#define CSI_CSICR2_HSC_SHIFT (0U)

Definition at line 10187 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_LVRM

#define CSI_CSICR2_LVRM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)

LVRM 0b000..512 x 384 0b001..448 x 336 0b010..384 x 288 0b011..384 x 256 0b100..320 x 240 0b101..288 x 216 0b110..400 x 300

Definition at line 10203 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_LVRM_MASK

#define CSI_CSICR2_LVRM_MASK (0x70000U)

Definition at line 10192 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_LVRM_SHIFT

#define CSI_CSICR2_LVRM_SHIFT (16U)

Definition at line 10193 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_SCE

#define CSI_CSICR2_SCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)

SCE 0b0..Skip count disable 0b1..Skip count enable

Definition at line 10219 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_SCE_MASK

#define CSI_CSICR2_SCE_MASK (0x800000U)

Definition at line 10213 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_SCE_SHIFT

#define CSI_CSICR2_SCE_SHIFT (23U)

Definition at line 10214 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_VSC

#define CSI_CSICR2_VSC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)

Definition at line 10191 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_VSC_MASK

#define CSI_CSICR2_VSC_MASK (0xFF00U)

Definition at line 10189 of file MIMXRT1062.h.

## ◆ CSI_CSICR2_VSC_SHIFT

#define CSI_CSICR2_VSC_SHIFT (8U)

Definition at line 10190 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REFLASH_RFF

#define CSI_CSICR3_DMA_REFLASH_RFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)

DMA_REFLASH_RFF 0b0..No reflashing 0b1..Reflash the embedded DMA controller

Definition at line 10343 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REFLASH_RFF_MASK

#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)

Definition at line 10337 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REFLASH_RFF_SHIFT

#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)

Definition at line 10338 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REFLASH_SFF

#define CSI_CSICR3_DMA_REFLASH_SFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)

DMA_REFLASH_SFF 0b0..No reflashing 0b1..Reflash the embedded DMA controller

Definition at line 10336 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REFLASH_SFF_MASK

#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)

Definition at line 10330 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REFLASH_SFF_SHIFT

#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)

Definition at line 10331 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REQ_EN_RFF

#define CSI_CSICR3_DMA_REQ_EN_RFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)

DMA_REQ_EN_RFF 0b0..Disable the dma request 0b1..Enable the dma request

Definition at line 10329 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REQ_EN_RFF_MASK

#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)

Definition at line 10323 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT

#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)

Definition at line 10324 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REQ_EN_SFF

#define CSI_CSICR3_DMA_REQ_EN_SFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)

DMA_REQ_EN_SFF 0b0..Disable the dma request 0b1..Enable the dma request

Definition at line 10322 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REQ_EN_SFF_MASK

#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)

Definition at line 10316 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT

#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)

Definition at line 10317 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ECC_AUTO_EN

#define CSI_CSICR3_ECC_AUTO_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)

ECC_AUTO_EN 0b0..Auto Error correction is disabled. 0b1..Auto Error correction is enabled.

Definition at line 10261 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ECC_AUTO_EN_MASK

#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)

Definition at line 10255 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ECC_AUTO_EN_SHIFT

#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)

Definition at line 10256 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ECC_INT_EN

#define CSI_CSICR3_ECC_INT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)

ECC_INT_EN 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. 0b1..Interrupt is generated when error is detected.

Definition at line 10268 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ECC_INT_EN_MASK

#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U)

Definition at line 10262 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ECC_INT_EN_SHIFT

#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U)

Definition at line 10263 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_FRMCNT

#define CSI_CSICR3_FRMCNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)

Definition at line 10353 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_FRMCNT_MASK

#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)

Definition at line 10351 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_FRMCNT_RST

#define CSI_CSICR3_FRMCNT_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)

FRMCNT_RST 0b0..Do not reset 0b1..Reset frame counter immediately

Definition at line 10350 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_FRMCNT_RST_MASK

#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)

Definition at line 10344 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_FRMCNT_RST_SHIFT

#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U)

Definition at line 10345 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_FRMCNT_SHIFT

#define CSI_CSICR3_FRMCNT_SHIFT (16U)

Definition at line 10352 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_HRESP_ERR_EN

#define CSI_CSICR3_HRESP_ERR_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)

HRESP_ERR_EN 0b0..Disable hresponse error interrupt 0b1..Enable hresponse error interrupt

Definition at line 10302 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_HRESP_ERR_EN_MASK

#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)

Definition at line 10296 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_HRESP_ERR_EN_SHIFT

#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)

Definition at line 10297 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_RxFF_LEVEL

#define CSI_CSICR3_RxFF_LEVEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)

RxFF_LEVEL 0b000..4 Double words 0b001..8 Double words 0b010..16 Double words 0b011..24 Double words 0b100..32 Double words 0b101..48 Double words 0b110..64 Double words 0b111..96 Double words

Definition at line 10295 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_RxFF_LEVEL_MASK

#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)

Definition at line 10283 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_RxFF_LEVEL_SHIFT

#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)

Definition at line 10284 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_STATFF_LEVEL

#define CSI_CSICR3_STATFF_LEVEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)

STATFF_LEVEL 0b000..4 Double words 0b001..8 Double words 0b010..12 Double words 0b011..16 Double words 0b100..24 Double words 0b101..32 Double words 0b110..48 Double words 0b111..64 Double words

Definition at line 10315 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_STATFF_LEVEL_MASK

#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)

Definition at line 10303 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_STATFF_LEVEL_SHIFT

#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)

Definition at line 10304 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_TWO_8BIT_SENSOR

#define CSI_CSICR3_TWO_8BIT_SENSOR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)

TWO_8BIT_SENSOR 0b0..Only one sensor is connected. 0b1..Two 8-bit sensors are connected or one 16-bit sensor is connected.

Definition at line 10282 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_TWO_8BIT_SENSOR_MASK

#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)

Definition at line 10276 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT

#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)

Definition at line 10277 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ZERO_PACK_EN

#define CSI_CSICR3_ZERO_PACK_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)

ZERO_PACK_EN 0b0..Zero packing disabled 0b1..Zero packing enabled

Definition at line 10275 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ZERO_PACK_EN_MASK

#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)

Definition at line 10269 of file MIMXRT1062.h.

## ◆ CSI_CSICR3_ZERO_PACK_EN_SHIFT

#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)

Definition at line 10270 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1

#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)

Definition at line 10513 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK

#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)

Definition at line 10511 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT

#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)

Definition at line 10512 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2

#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)

Definition at line 10520 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK

#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)

Definition at line 10518 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT

#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)

Definition at line 10519 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF

#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)

Definition at line 10499 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK

#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)

Definition at line 10497 of file MIMXRT1062.h.

## ◆ CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT

#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)

Definition at line 10498 of file MIMXRT1062.h.

## ◆ CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF

#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)

Definition at line 10506 of file MIMXRT1062.h.

## ◆ CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK

#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)

Definition at line 10504 of file MIMXRT1062.h.

## ◆ CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT

#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)

Definition at line 10505 of file MIMXRT1062.h.

## ◆ CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE

#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)

Definition at line 10530 of file MIMXRT1062.h.

## ◆ CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK

#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)

Definition at line 10528 of file MIMXRT1062.h.

## ◆ CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT

#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)

Definition at line 10529 of file MIMXRT1062.h.

## ◆ CSI_CSIFBUF_PARA_FBUF_STRIDE

#define CSI_CSIFBUF_PARA_FBUF_STRIDE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)

Definition at line 10527 of file MIMXRT1062.h.

## ◆ CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK

#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)

Definition at line 10525 of file MIMXRT1062.h.

## ◆ CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT

#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)

Definition at line 10526 of file MIMXRT1062.h.

## ◆ CSI_CSIIMAG_PARA_IMAGE_HEIGHT

#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)

Definition at line 10537 of file MIMXRT1062.h.

## ◆ CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK

#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)

Definition at line 10535 of file MIMXRT1062.h.

## ◆ CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT

#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)

Definition at line 10536 of file MIMXRT1062.h.

## ◆ CSI_CSIIMAG_PARA_IMAGE_WIDTH

#define CSI_CSIIMAG_PARA_IMAGE_WIDTH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)

Definition at line 10540 of file MIMXRT1062.h.

## ◆ CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK

#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)

Definition at line 10538 of file MIMXRT1062.h.

## ◆ CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT

#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)

Definition at line 10539 of file MIMXRT1062.h.

## ◆ CSI_CSIRFIFO_IMAGE

#define CSI_CSIRFIFO_IMAGE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)

Definition at line 10367 of file MIMXRT1062.h.

## ◆ CSI_CSIRFIFO_IMAGE_MASK

#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)

Definition at line 10365 of file MIMXRT1062.h.

## ◆ CSI_CSIRFIFO_IMAGE_SHIFT

#define CSI_CSIRFIFO_IMAGE_SHIFT (0U)

Definition at line 10366 of file MIMXRT1062.h.

## ◆ CSI_CSIRXCNT_RXCNT

#define CSI_CSIRXCNT_RXCNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)

Definition at line 10374 of file MIMXRT1062.h.

## ◆ CSI_CSIRXCNT_RXCNT_MASK

#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)

Definition at line 10372 of file MIMXRT1062.h.

## ◆ CSI_CSIRXCNT_RXCNT_SHIFT

#define CSI_CSIRXCNT_RXCNT_SHIFT (0U)

Definition at line 10373 of file MIMXRT1062.h.

## ◆ CSI_CSISR_BASEADDR_CHHANGE_ERROR

#define CSI_CSISR_BASEADDR_CHHANGE_ERROR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)

Definition at line 10492 of file MIMXRT1062.h.

## ◆ CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK

#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)

Definition at line 10490 of file MIMXRT1062.h.

## ◆ CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT

#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)

Definition at line 10491 of file MIMXRT1062.h.

## ◆ CSI_CSISR_COF_INT

#define CSI_CSISR_COF_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)

COF_INT 0b0..Video field has no change. 0b1..Change of video field is detected.

Definition at line 10406 of file MIMXRT1062.h.

## ◆ CSI_CSISR_COF_INT_MASK

#define CSI_CSISR_COF_INT_MASK (0x2000U)

Definition at line 10400 of file MIMXRT1062.h.

## ◆ CSI_CSISR_COF_INT_SHIFT

#define CSI_CSISR_COF_INT_SHIFT (13U)

Definition at line 10401 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_FIELD0_DONE

#define CSI_CSISR_DMA_FIELD0_DONE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)

Definition at line 10489 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_FIELD0_DONE_MASK

#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)

Definition at line 10487 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_FIELD0_DONE_SHIFT

#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)

Definition at line 10488 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_FIELD1_DONE

#define CSI_CSISR_DMA_FIELD1_DONE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)

Definition at line 10486 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_FIELD1_DONE_MASK

#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)

Definition at line 10484 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_FIELD1_DONE_SHIFT

#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)

Definition at line 10485 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_FB1

#define CSI_CSISR_DMA_TSF_DONE_FB1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)

DMA_TSF_DONE_FB1 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.

Definition at line 10448 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_FB1_MASK

#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)

Definition at line 10442 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT

#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)

Definition at line 10443 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_FB2

#define CSI_CSISR_DMA_TSF_DONE_FB2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)

DMA_TSF_DONE_FB2 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.

Definition at line 10455 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_FB2_MASK

#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)

Definition at line 10449 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT

#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)

Definition at line 10450 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_SFF

#define CSI_CSISR_DMA_TSF_DONE_SFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)

DMA_TSF_DONE_SFF 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.

Definition at line 10469 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_SFF_MASK

#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)

Definition at line 10463 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT

#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)

Definition at line 10464 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DRDY

#define CSI_CSISR_DRDY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)

DRDY 0b0..No data (word) is ready 0b1..At least 1 datum (word) is ready in RXFIFO.

Definition at line 10385 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DRDY_MASK

#define CSI_CSISR_DRDY_MASK (0x1U)

Definition at line 10379 of file MIMXRT1062.h.

## ◆ CSI_CSISR_DRDY_SHIFT

#define CSI_CSISR_DRDY_SHIFT (0U)

Definition at line 10380 of file MIMXRT1062.h.

## ◆ CSI_CSISR_ECC_INT

#define CSI_CSISR_ECC_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)

ECC_INT 0b0..No error detected 0b1..Error is detected in CCIR coding

Definition at line 10392 of file MIMXRT1062.h.

## ◆ CSI_CSISR_ECC_INT_MASK

#define CSI_CSISR_ECC_INT_MASK (0x2U)

Definition at line 10386 of file MIMXRT1062.h.

## ◆ CSI_CSISR_ECC_INT_SHIFT

#define CSI_CSISR_ECC_INT_SHIFT (1U)

Definition at line 10387 of file MIMXRT1062.h.

## ◆ CSI_CSISR_EOF_INT

#define CSI_CSISR_EOF_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)

EOF_INT 0b0..EOF is not detected. 0b1..EOF is detected.

Definition at line 10434 of file MIMXRT1062.h.

## ◆ CSI_CSISR_EOF_INT_MASK

#define CSI_CSISR_EOF_INT_MASK (0x20000U)

Definition at line 10428 of file MIMXRT1062.h.

## ◆ CSI_CSISR_EOF_INT_SHIFT

#define CSI_CSISR_EOF_INT_SHIFT (17U)

Definition at line 10429 of file MIMXRT1062.h.

## ◆ CSI_CSISR_F1_INT

#define CSI_CSISR_F1_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)

F1_INT 0b0..Field 1 of video is not detected. 0b1..Field 1 of video is about to start.

Definition at line 10413 of file MIMXRT1062.h.

## ◆ CSI_CSISR_F1_INT_MASK

#define CSI_CSISR_F1_INT_MASK (0x4000U)

Definition at line 10407 of file MIMXRT1062.h.

## ◆ CSI_CSISR_F1_INT_SHIFT

#define CSI_CSISR_F1_INT_SHIFT (14U)

Definition at line 10408 of file MIMXRT1062.h.

## ◆ CSI_CSISR_F2_INT

#define CSI_CSISR_F2_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)

F2_INT 0b0..Field 2 of video is not detected 0b1..Field 2 of video is about to start

Definition at line 10420 of file MIMXRT1062.h.

## ◆ CSI_CSISR_F2_INT_MASK

#define CSI_CSISR_F2_INT_MASK (0x8000U)

Definition at line 10414 of file MIMXRT1062.h.

## ◆ CSI_CSISR_F2_INT_SHIFT

#define CSI_CSISR_F2_INT_SHIFT (15U)

Definition at line 10415 of file MIMXRT1062.h.

## ◆ CSI_CSISR_HRESP_ERR_INT

#define CSI_CSISR_HRESP_ERR_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)

HRESP_ERR_INT 0b0..No hresponse error. 0b1..Hresponse error is detected.

Definition at line 10399 of file MIMXRT1062.h.

## ◆ CSI_CSISR_HRESP_ERR_INT_MASK

#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)

Definition at line 10393 of file MIMXRT1062.h.

## ◆ CSI_CSISR_HRESP_ERR_INT_SHIFT

#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)

Definition at line 10394 of file MIMXRT1062.h.

## ◆ CSI_CSISR_RF_OR_INT

#define CSI_CSISR_RF_OR_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)

RF_OR_INT 0b0..RXFIFO has not overflowed. 0b1..RXFIFO has overflowed.

Definition at line 10476 of file MIMXRT1062.h.

## ◆ CSI_CSISR_RF_OR_INT_MASK

#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U)

Definition at line 10470 of file MIMXRT1062.h.

## ◆ CSI_CSISR_RF_OR_INT_SHIFT

#define CSI_CSISR_RF_OR_INT_SHIFT (24U)

Definition at line 10471 of file MIMXRT1062.h.

## ◆ CSI_CSISR_RxFF_INT

#define CSI_CSISR_RxFF_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)

RxFF_INT 0b0..RxFIFO is not full. 0b1..RxFIFO is full.

Definition at line 10441 of file MIMXRT1062.h.

## ◆ CSI_CSISR_RxFF_INT_MASK

#define CSI_CSISR_RxFF_INT_MASK (0x40000U)

Definition at line 10435 of file MIMXRT1062.h.

## ◆ CSI_CSISR_RxFF_INT_SHIFT

#define CSI_CSISR_RxFF_INT_SHIFT (18U)

Definition at line 10436 of file MIMXRT1062.h.

## ◆ CSI_CSISR_SF_OR_INT

#define CSI_CSISR_SF_OR_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)

SF_OR_INT 0b0..STATFIFO has not overflowed. 0b1..STATFIFO has overflowed.

Definition at line 10483 of file MIMXRT1062.h.

## ◆ CSI_CSISR_SF_OR_INT_MASK

#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U)

Definition at line 10477 of file MIMXRT1062.h.

## ◆ CSI_CSISR_SF_OR_INT_SHIFT

#define CSI_CSISR_SF_OR_INT_SHIFT (25U)

Definition at line 10478 of file MIMXRT1062.h.

## ◆ CSI_CSISR_SOF_INT

#define CSI_CSISR_SOF_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)

SOF_INT 0b0..SOF is not detected. 0b1..SOF is detected.

Definition at line 10427 of file MIMXRT1062.h.

## ◆ CSI_CSISR_SOF_INT_MASK

#define CSI_CSISR_SOF_INT_MASK (0x10000U)

Definition at line 10421 of file MIMXRT1062.h.

## ◆ CSI_CSISR_SOF_INT_SHIFT

#define CSI_CSISR_SOF_INT_SHIFT (16U)

Definition at line 10422 of file MIMXRT1062.h.

## ◆ CSI_CSISR_STATFF_INT

#define CSI_CSISR_STATFF_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)

STATFF_INT 0b0..STATFIFO is not full. 0b1..STATFIFO is full.

Definition at line 10462 of file MIMXRT1062.h.

## ◆ CSI_CSISR_STATFF_INT_MASK

#define CSI_CSISR_STATFF_INT_MASK (0x200000U)

Definition at line 10456 of file MIMXRT1062.h.

## ◆ CSI_CSISR_STATFF_INT_SHIFT

#define CSI_CSISR_STATFF_INT_SHIFT (21U)

Definition at line 10457 of file MIMXRT1062.h.

## ◆ CSI_CSISTATFIFO_STAT

#define CSI_CSISTATFIFO_STAT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)

Definition at line 10360 of file MIMXRT1062.h.

## ◆ CSI_CSISTATFIFO_STAT_MASK

#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)

Definition at line 10358 of file MIMXRT1062.h.

## ◆ CSI_CSISTATFIFO_STAT_SHIFT

#define CSI_CSISTATFIFO_STAT_SHIFT (0U)

Definition at line 10359 of file MIMXRT1062.h.