Callisto4Bootloader: Modules

Callisto4Bootloader

Modules
Here is a list of all modules:
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Basic Math Functions |
▼ Fast Math Functions | This set of functions provides a fast approximation to sine, cosine, and square root. As compared to most of the other functions in the CMSIS math library, the fast math functions operate on individual values and not arrays. There are separate functions for Q15, Q31, and floating-point data
Square Root | Computes the square root of a number. There are separate functions for Q15, Q31, and floating-point data types. The square root function is computed using the Newton-Raphson algorithm. This is an iterative algorithm of the form:
Complex Math Functions | This set of functions operates on complex data vectors. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). In the API functions, the number of samples in a complex array refers to the number of complex values; the array contains twice this number of real values
Filtering Functions |
Matrix Functions | This set of functions provides basic matrix math operations. The functions operate on matrix data structures. For example, the type definition for the floating-point matrix structure is shown below:
Transform Functions |
▼ Controller Functions |
PID Motor Control | A Proportional Integral Derivative (PID) controller is a generic feedback control loop mechanism widely used in industrial control systems. A PID controller is the most commonly used type of feedback controller
Vector Clarke Transform | Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. Generally the Clarke transform uses three-phase currents `Ia, Ib and Ic` to calculate currents in the two-phase orthogonal stator axis `Ialpha` and `Ibeta`. When `Ialpha` is superposed with `Ia` as shown in the figure below
Vector Inverse Clarke Transform | Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases
Vector Park Transform | Forward Park transform converts the input two-coordinate vector to flux and torque components. The Park transform can be used to realize the transformation of the `Ialpha` and the `Ibeta` currents from the stationary to the moving reference frame and control the spatial relationship between the stator vector current and rotor flux vector. If we consider the d axis aligned with the rotor flux, the diagram below shows the current vector and the relationship from the two reference frames:
Vector Inverse Park transform | Inverse Park transform converts the input flux and torque components to two-coordinate vector
Statistics Functions |
Support Functions |
▼ Interpolation Functions | These functions perform 1- and 2-dimensional interpolation of data. Linear interpolation is used for 1-dimensional data and bilinear interpolation is used for 2-dimensional data
Linear Interpolation | Linear interpolation is a method of curve fitting using linear polynomials. Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
Bilinear Interpolation | Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. The underlying function `f(x, y)` is sampled on a regular grid and the interpolation process determines values between the grid points. Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. Bilinear interpolation is often used in image processing to rescale images. The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types
Examples |
CMSIS Global Defines | IO Type Qualifiers are used
▼ Defines and Type Definitions | Type definitions and defines for Cortex-M processor based devices
▼ Status and Control Registers | Core Register type definitions
▼ Nested Vectored Interrupt Controller (NVIC) | Type definitions for the NVIC Registers
▼ System Control Block (SCB) | Type definitions for the System Control Block Registers
► System Controls not in SCB (SCnSCB) | Type definitions for the System Control and ID Register not in the SCB
► System Tick Timer (SysTick) | Type definitions for the System Timer Registers
► Instrumentation Trace Macrocell (ITM) | Type definitions for the Instrumentation Trace Macrocell (ITM)
► Data Watchpoint and Trace (DWT) | Type definitions for the Data Watchpoint and Trace (DWT)
► Trace Port Interface (TPI) | Type definitions for the Trace Port Interface (TPI)
► Floating Point Unit (FPU) | Type definitions for the Floating Point Unit (FPU)
► Core Debug Registers (CoreDebug) | Type definitions for the Core Debug Registers
► Core register bit field macros | Macros for use with bit field definitions (xxx_Pos, xxx_Msk)
► Core Definitions | Definitions for base addresses, unions, and structures
► Functions and Instructions Reference |
► CMSIS Core Register Access Functions |
► CMSIS Core Instruction Interface | Access to dedicated instructions
CMSIS SIMD Intrinsics | Access to dedicated SIMD instructions
► NVIC Functions | Functions that manage interrupts and exceptions via the NVIC
► FPU Functions | Function that provides FPU type
► SAU Functions | Functions that configure the SAU
► SysTick Functions | Functions that configure the System
ITM Functions | Functions that access the ITM debug interface
► Cache Functions | Functions that configure Instruction and Data cache
► SysTick Functions | Functions that configure the System
ITM Functions | Functions that access the ITM debug interface
► NVIC Functions | Functions that manage interrupts and exceptions via the NVIC
► FPU Functions | Function that provides FPU type
► SAU Functions | Functions that configure the SAU
► SysTick Functions | Functions that configure the System
ITM Functions | Functions that access the ITM debug interface
► Cache Functions | Functions that configure Instruction and Data cache
► SysTick Functions | Functions that configure the System
ITM Functions | Functions that access the ITM debug interface
LED connections onto the processor GPIO pins. |
Pin_mux |
Interrupt vector numbers |
Cortex M7 Core Configuration |
▼ Mapping Information |
▼ Edma_request |
▼ Iomuxc_pads |
▼ Device Peripheral Access Layer |
► ADC Peripheral Access Layer |
ADC Register Masks |
► ADC_ETC Peripheral Access Layer |
ADC_ETC Register Masks |
► AIPSTZ Peripheral Access Layer |
AIPSTZ Register Masks |
► AOI Peripheral Access Layer |
AOI Register Masks |
► BEE Peripheral Access Layer |
BEE Register Masks |
► CAN Peripheral Access Layer |
CAN Register Masks |
► CCM Peripheral Access Layer |
CCM Register Masks |
► CCM_ANALOG Peripheral Access Layer |
CCM_ANALOG Register Masks |
► CMP Peripheral Access Layer |
CMP Register Masks |
► CSI Peripheral Access Layer |
CSI Register Masks |
► CSU Peripheral Access Layer |
CSU Register Masks |
► DCDC Peripheral Access Layer |
DCDC Register Masks |
► DCP Peripheral Access Layer |
DCP Register Masks |
► DMA Peripheral Access Layer |
DMA Register Masks |
► DMAMUX Peripheral Access Layer |
DMAMUX Register Masks |
► ENC Peripheral Access Layer |
ENC Register Masks |
► ENET Peripheral Access Layer |
ENET Register Masks |
► EWM Peripheral Access Layer |
EWM Register Masks |
► FLEXIO Peripheral Access Layer |
FLEXIO Register Masks |
► FLEXRAM Peripheral Access Layer |
FLEXRAM Register Masks |
► FLEXSPI Peripheral Access Layer |
FLEXSPI Register Masks |
► GPC Peripheral Access Layer |
GPC Register Masks |
► GPIO Peripheral Access Layer |
GPIO Register Masks |
► GPT Peripheral Access Layer |
GPT Register Masks |
► I2S Peripheral Access Layer |
I2S Register Masks |
► IOMUXC Peripheral Access Layer |
IOMUXC Register Masks |
► IOMUXC_GPR Peripheral Access Layer |
IOMUXC_GPR Register Masks |
► IOMUXC_SNVS Peripheral Access Layer |
IOMUXC_SNVS Register Masks |
► IOMUXC_SNVS_GPR Peripheral Access Layer |
IOMUXC_SNVS_GPR Register Masks |
► KPP Peripheral Access Layer |
KPP Register Masks |
► LCDIF Peripheral Access Layer |
LCDIF Register Masks |
► LPI2C Peripheral Access Layer |
LPI2C Register Masks |
► LPSPI Peripheral Access Layer |
LPSPI Register Masks |
► LPUART Peripheral Access Layer |
LPUART Register Masks |
► OCOTP Peripheral Access Layer |
OCOTP Register Masks |
► PGC Peripheral Access Layer |
PGC Register Masks |
► PIT Peripheral Access Layer |
PIT Register Masks |
► PMU Peripheral Access Layer |
PMU Register Masks |
► PWM Peripheral Access Layer |
PWM Register Masks |
► PXP Peripheral Access Layer |
PXP Register Masks |
► ROMC Peripheral Access Layer |
ROMC Register Masks |
► RTWDOG Peripheral Access Layer |
RTWDOG Register Masks |
► SEMC Peripheral Access Layer |
SEMC Register Masks |
► SNVS Peripheral Access Layer |
SNVS Register Masks |
► SPDIF Peripheral Access Layer |
SPDIF Register Masks |
► SRC Peripheral Access Layer |
SRC Register Masks |
► TEMPMON Peripheral Access Layer |
TEMPMON Register Masks |
► TMR Peripheral Access Layer |
TMR Register Masks |
► TRNG Peripheral Access Layer |
TRNG Register Masks |
► TSC Peripheral Access Layer |
TSC Register Masks |
► USB Peripheral Access Layer |
USB Register Masks |
► USBNC Peripheral Access Layer |
USBNC Register Masks |
► USBPHY Peripheral Access Layer |
USBPHY Register Masks |
► USB_ANALOG Peripheral Access Layer |
USB_ANALOG Register Masks |
► USDHC Peripheral Access Layer |
USDHC Register Masks |
► WDOG Peripheral Access Layer |
WDOG Register Masks |
► XBARA Peripheral Access Layer |
XBARA Register Masks |
► XBARB Peripheral Access Layer |
XBARB Register Masks |
► XTALOSC24M Peripheral Access Layer |
XTALOSC24M Register Masks |
Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). |
SDK Compatibility |
Bl_hw |
Rtwdog |
Wdog |