Callisto4Bootloader: ITM Functions

Callisto4Bootloader

Variables
ITM Functions
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions » | Functions and Instructions Reference » NVIC Functions » FPU Functions » SAU Functions Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions » | Functions and Instructions Reference » NVIC Functions » FPU Functions » | Cache Functions » SysTick Functions

Functions that access the ITM debug interface. More...

## Variables

uint32_t APSR_Type::_reserved0:16
uint32_t APSR_Type::GE:4
uint32_t APSR_Type::_reserved1:7
uint32_t APSR_Type::Q:1
uint32_t APSR_Type::V:1
uint32_t APSR_Type::C:1
uint32_t APSR_Type::Z:1
uint32_t APSR_Type::N:1
struct {
uint32_t APSR_Type::_reserved0:16
uint32_t APSR_Type::GE:4
uint32_t APSR_Type::_reserved1:7
uint32_t APSR_Type::Q:1
uint32_t APSR_Type::V:1
uint32_t APSR_Type::C:1
uint32_t APSR_Type::Z:1
uint32_t APSR_Type::N:1
} | APSR_Type::b
uint32_t | APSR_Type::w
uint32_t IPSR_Type::ISR:9
uint32_t IPSR_Type::_reserved0:23
struct {
uint32_t IPSR_Type::ISR:9
uint32_t IPSR_Type::_reserved0:23
} | IPSR_Type::b
uint32_t | IPSR_Type::w
uint32_t xPSR_Type::ISR:9
uint32_t xPSR_Type::_reserved0:7
uint32_t xPSR_Type::GE:4
uint32_t xPSR_Type::_reserved1:4
uint32_t xPSR_Type::T:1
uint32_t xPSR_Type::IT:2
uint32_t xPSR_Type::Q:1
uint32_t xPSR_Type::V:1
uint32_t xPSR_Type::C:1
uint32_t xPSR_Type::Z:1
uint32_t xPSR_Type::N:1
struct {
uint32_t xPSR_Type::ISR:9
uint32_t xPSR_Type::_reserved0:7
uint32_t xPSR_Type::GE:4
uint32_t xPSR_Type::_reserved1:4
uint32_t xPSR_Type::T:1
uint32_t xPSR_Type::IT:2
uint32_t xPSR_Type::Q:1
uint32_t xPSR_Type::V:1
uint32_t xPSR_Type::C:1
uint32_t xPSR_Type::Z:1
uint32_t xPSR_Type::N:1
} | xPSR_Type::b
uint32_t | xPSR_Type::w
uint32_t CONTROL_Type::nPRIV:1
uint32_t CONTROL_Type::SPSEL:1
uint32_t CONTROL_Type::FPCA:1
uint32_t CONTROL_Type::SFPA:1
uint32_t CONTROL_Type::_reserved1:28
struct {
uint32_t CONTROL_Type::nPRIV:1
uint32_t CONTROL_Type::SPSEL:1
uint32_t CONTROL_Type::FPCA:1
uint32_t CONTROL_Type::SFPA:1
uint32_t CONTROL_Type::_reserved1:28
} | CONTROL_Type::b
uint32_t | CONTROL_Type::w
__IOM uint32_t | NVIC_Type::ISER [16U]
uint32_t | NVIC_Type::RESERVED0 [16U]
__IOM uint32_t | NVIC_Type::ICER [16U]
uint32_t | NVIC_Type::RSERVED1 [16U]
__IOM uint32_t | NVIC_Type::ISPR [16U]
uint32_t | NVIC_Type::RESERVED2 [16U]
__IOM uint32_t | NVIC_Type::ICPR [16U]
uint32_t | NVIC_Type::RESERVED3 [16U]
__IOM uint32_t | NVIC_Type::IABR [16U]
uint32_t | NVIC_Type::RESERVED4 [16U]
__IOM uint32_t | NVIC_Type::ITNS [16U]
uint32_t | NVIC_Type::RESERVED5 [16U]
__IOM uint8_t | NVIC_Type::IPR [496U]
uint32_t | NVIC_Type::RESERVED6 [580U]
__OM uint32_t | NVIC_Type::STIR
__IM uint32_t | SCB_Type::CPUID
__IOM uint32_t | SCB_Type::ICSR
__IOM uint32_t | SCB_Type::VTOR
__IOM uint32_t | SCB_Type::AIRCR
__IOM uint32_t | SCB_Type::SCR
__IOM uint32_t | SCB_Type::CCR
__IOM uint8_t | SCB_Type::SHPR [12U]
__IOM uint32_t | SCB_Type::SHCSR
__IOM uint32_t | SCB_Type::CFSR
__IOM uint32_t | SCB_Type::HFSR
__IOM uint32_t | SCB_Type::DFSR
__IOM uint32_t | SCB_Type::MMFAR
__IOM uint32_t | SCB_Type::BFAR
__IOM uint32_t | SCB_Type::AFSR
__IM uint32_t | SCB_Type::ID_PFR [2U]
__IM uint32_t | SCB_Type::ID_DFR
__IM uint32_t | SCB_Type::ID_ADR
__IM uint32_t | SCB_Type::ID_MMFR [4U]
__IM uint32_t | SCB_Type::ID_ISAR [6U]
__IM uint32_t | SCB_Type::CLIDR
__IM uint32_t | SCB_Type::CTR
__IM uint32_t | SCB_Type::CCSIDR
__IOM uint32_t | SCB_Type::CSSELR
__IOM uint32_t | SCB_Type::CPACR
__IOM uint32_t | SCB_Type::NSACR
uint32_t | SCB_Type::RESERVED3 [92U]
__OM uint32_t | SCB_Type::STIR
uint32_t | SCB_Type::RESERVED4 [15U]
__IM uint32_t | SCB_Type::MVFR0
__IM uint32_t | SCB_Type::MVFR1
__IM uint32_t | SCB_Type::MVFR2
uint32_t | SCB_Type::RESERVED5 [1U]
__OM uint32_t | SCB_Type::ICIALLU
uint32_t | SCB_Type::RESERVED6 [1U]
__OM uint32_t | SCB_Type::ICIMVAU
__OM uint32_t | SCB_Type::DCIMVAC
__OM uint32_t | SCB_Type::DCISW
__OM uint32_t | SCB_Type::DCCMVAU
__OM uint32_t | SCB_Type::DCCMVAC
__OM uint32_t | SCB_Type::DCCSW
__OM uint32_t | SCB_Type::DCCIMVAC
__OM uint32_t | SCB_Type::DCCISW
uint32_t | SCB_Type::RESERVED7 [6U]
__IOM uint32_t | SCB_Type::ITCMCR
__IOM uint32_t | SCB_Type::DTCMCR
__IOM uint32_t | SCB_Type::AHBPCR
__IOM uint32_t | SCB_Type::CACR
__IOM uint32_t | SCB_Type::AHBSCR
uint32_t | SCB_Type::RESERVED8 [1U]
__IOM uint32_t | SCB_Type::ABFSR
uint32_t | SCnSCB_Type::RESERVED0 [1U]
__IM uint32_t | SCnSCB_Type::ICTR
__IOM uint32_t | SCnSCB_Type::ACTLR
__IOM uint32_t | SCnSCB_Type::CPPWR
__IOM uint32_t | SysTick_Type::CTRL
__IOM uint32_t | SysTick_Type::LOAD
__IOM uint32_t | SysTick_Type::VAL
__IM uint32_t | SysTick_Type::CALIB
__OM uint8_t ITM_Type::u8
__OM uint16_t ITM_Type::u16
__OM uint32_t ITM_Type::u32
union {
__OM uint8_t ITM_Type::u8
__OM uint16_t ITM_Type::u16
__OM uint32_t ITM_Type::u32
} | ITM_Type::PORT [32U]
uint32_t | ITM_Type::RESERVED0 [864U]
__IOM uint32_t | ITM_Type::TER
uint32_t | ITM_Type::RESERVED1 [15U]
__IOM uint32_t | ITM_Type::TPR
uint32_t | ITM_Type::RESERVED2 [15U]
__IOM uint32_t | ITM_Type::TCR
uint32_t | ITM_Type::RESERVED3 [29U]
__OM uint32_t | ITM_Type::IWR
__IM uint32_t | ITM_Type::IRR
__IOM uint32_t | ITM_Type::IMCR
uint32_t | ITM_Type::RESERVED4 [43U]
__OM uint32_t | ITM_Type::LAR
__IM uint32_t | ITM_Type::LSR
uint32_t | ITM_Type::RESERVED5 [1U]
__IM uint32_t | ITM_Type::DEVARCH
uint32_t | ITM_Type::RESERVED6 [4U]
__IM uint32_t | ITM_Type::PID4
__IM uint32_t | ITM_Type::PID5
__IM uint32_t | ITM_Type::PID6
__IM uint32_t | ITM_Type::PID7
__IM uint32_t | ITM_Type::PID0
__IM uint32_t | ITM_Type::PID1
__IM uint32_t | ITM_Type::PID2
__IM uint32_t | ITM_Type::PID3
__IM uint32_t | ITM_Type::CID0
__IM uint32_t | ITM_Type::CID1
__IM uint32_t | ITM_Type::CID2
__IM uint32_t | ITM_Type::CID3
__IOM uint32_t | DWT_Type::CTRL
__IOM uint32_t | DWT_Type::CYCCNT
__IOM uint32_t | DWT_Type::CPICNT
__IOM uint32_t | DWT_Type::EXCCNT
__IOM uint32_t | DWT_Type::SLEEPCNT
__IOM uint32_t | DWT_Type::LSUCNT
__IOM uint32_t | DWT_Type::FOLDCNT
__IM uint32_t | DWT_Type::PCSR
__IOM uint32_t | DWT_Type::COMP0
uint32_t | DWT_Type::RESERVED1 [1U]
__IOM uint32_t | DWT_Type::FUNCTION0
uint32_t | DWT_Type::RESERVED2 [1U]
__IOM uint32_t | DWT_Type::COMP1
uint32_t | DWT_Type::RESERVED3 [1U]
__IOM uint32_t | DWT_Type::FUNCTION1
uint32_t | DWT_Type::RESERVED4 [1U]
__IOM uint32_t | DWT_Type::COMP2
uint32_t | DWT_Type::RESERVED5 [1U]
__IOM uint32_t | DWT_Type::FUNCTION2
uint32_t | DWT_Type::RESERVED6 [1U]
__IOM uint32_t | DWT_Type::COMP3
uint32_t | DWT_Type::RESERVED7 [1U]
__IOM uint32_t | DWT_Type::FUNCTION3
uint32_t | DWT_Type::RESERVED8 [1U]
__IOM uint32_t | DWT_Type::COMP4
uint32_t | DWT_Type::RESERVED9 [1U]
__IOM uint32_t | DWT_Type::FUNCTION4
uint32_t | DWT_Type::RESERVED10 [1U]
__IOM uint32_t | DWT_Type::COMP5
uint32_t | DWT_Type::RESERVED11 [1U]
__IOM uint32_t | DWT_Type::FUNCTION5
uint32_t | DWT_Type::RESERVED12 [1U]
__IOM uint32_t | DWT_Type::COMP6
uint32_t | DWT_Type::RESERVED13 [1U]
__IOM uint32_t | DWT_Type::FUNCTION6
uint32_t | DWT_Type::RESERVED14 [1U]
__IOM uint32_t | DWT_Type::COMP7
uint32_t | DWT_Type::RESERVED15 [1U]
__IOM uint32_t | DWT_Type::FUNCTION7
uint32_t | DWT_Type::RESERVED16 [1U]
__IOM uint32_t | DWT_Type::COMP8
uint32_t | DWT_Type::RESERVED17 [1U]
__IOM uint32_t | DWT_Type::FUNCTION8
uint32_t | DWT_Type::RESERVED18 [1U]
__IOM uint32_t | DWT_Type::COMP9
uint32_t | DWT_Type::RESERVED19 [1U]
__IOM uint32_t | DWT_Type::FUNCTION9
uint32_t | DWT_Type::RESERVED20 [1U]
__IOM uint32_t | DWT_Type::COMP10
uint32_t | DWT_Type::RESERVED21 [1U]
__IOM uint32_t | DWT_Type::FUNCTION10
uint32_t | DWT_Type::RESERVED22 [1U]
__IOM uint32_t | DWT_Type::COMP11
uint32_t | DWT_Type::RESERVED23 [1U]
__IOM uint32_t | DWT_Type::FUNCTION11
uint32_t | DWT_Type::RESERVED24 [1U]
__IOM uint32_t | DWT_Type::COMP12
uint32_t | DWT_Type::RESERVED25 [1U]
__IOM uint32_t | DWT_Type::FUNCTION12
uint32_t | DWT_Type::RESERVED26 [1U]
__IOM uint32_t | DWT_Type::COMP13
uint32_t | DWT_Type::RESERVED27 [1U]
__IOM uint32_t | DWT_Type::FUNCTION13
uint32_t | DWT_Type::RESERVED28 [1U]
__IOM uint32_t | DWT_Type::COMP14
uint32_t | DWT_Type::RESERVED29 [1U]
__IOM uint32_t | DWT_Type::FUNCTION14
uint32_t | DWT_Type::RESERVED30 [1U]
__IOM uint32_t | DWT_Type::COMP15
uint32_t | DWT_Type::RESERVED31 [1U]
__IOM uint32_t | DWT_Type::FUNCTION15
uint32_t | DWT_Type::RESERVED32 [934U]
__IM uint32_t | DWT_Type::LSR
uint32_t | DWT_Type::RESERVED33 [1U]
__IM uint32_t | DWT_Type::DEVARCH
__IM uint32_t | TPI_Type::SSPSR
__IOM uint32_t | TPI_Type::CSPSR
uint32_t | TPI_Type::RESERVED0 [2U]
__IOM uint32_t | TPI_Type::ACPR
uint32_t | TPI_Type::RESERVED1 [55U]
__IOM uint32_t | TPI_Type::SPPR
uint32_t | TPI_Type::RESERVED2 [131U]
__IM uint32_t | TPI_Type::FFSR
__IOM uint32_t | TPI_Type::FFCR
__IM uint32_t | TPI_Type::FSCR
uint32_t | TPI_Type::RESERVED3 [759U]
__IM uint32_t | TPI_Type::TRIGGER
__IM uint32_t | TPI_Type::FIFO0
__IM uint32_t | TPI_Type::ITATBCTR2
uint32_t | TPI_Type::RESERVED4 [1U]
__IM uint32_t | TPI_Type::ITATBCTR0
__IM uint32_t | TPI_Type::FIFO1
__IOM uint32_t | TPI_Type::ITCTRL
uint32_t | TPI_Type::RESERVED5 [39U]
__IOM uint32_t | TPI_Type::CLAIMSET
__IOM uint32_t | TPI_Type::CLAIMCLR
uint32_t | TPI_Type::RESERVED7 [8U]
__IM uint32_t | TPI_Type::DEVID
__IM uint32_t | TPI_Type::DEVTYPE
uint32_t | FPU_Type::RESERVED0 [1U]
__IOM uint32_t | FPU_Type::FPCCR
__IOM uint32_t | FPU_Type::FPCAR
__IOM uint32_t | FPU_Type::FPDSCR
__IM uint32_t | FPU_Type::MVFR0
__IM uint32_t | FPU_Type::MVFR1
__IOM uint32_t | CoreDebug_Type::DHCSR
__OM uint32_t | CoreDebug_Type::DCRSR
__IOM uint32_t | CoreDebug_Type::DCRDR
__IOM uint32_t | CoreDebug_Type::DEMCR
uint32_t | CoreDebug_Type::RESERVED4 [1U]
__IOM uint32_t | CoreDebug_Type::DAUTHCTRL
__IOM uint32_t | CoreDebug_Type::DSCSR
uint32_t APSR_Type::_reserved0:16
uint32_t APSR_Type::GE:4
uint32_t APSR_Type::_reserved1:7
uint32_t APSR_Type::Q:1
uint32_t APSR_Type::V:1
uint32_t APSR_Type::C:1
uint32_t APSR_Type::Z:1
uint32_t APSR_Type::N:1
struct {
uint32_t APSR_Type::_reserved0:16
uint32_t APSR_Type::GE:4
uint32_t APSR_Type::_reserved1:7
uint32_t APSR_Type::Q:1
uint32_t APSR_Type::V:1
uint32_t APSR_Type::C:1
uint32_t APSR_Type::Z:1
uint32_t APSR_Type::N:1
} | APSR_Type::b
uint32_t IPSR_Type::ISR:9
uint32_t IPSR_Type::_reserved0:23
struct {
uint32_t IPSR_Type::ISR:9
uint32_t IPSR_Type::_reserved0:23
} | IPSR_Type::b
uint32_t xPSR_Type::ISR:9
uint32_t xPSR_Type::_reserved0:7
uint32_t xPSR_Type::GE:4
uint32_t xPSR_Type::_reserved1:4
uint32_t xPSR_Type::T:1
uint32_t xPSR_Type::IT:2
uint32_t xPSR_Type::Q:1
uint32_t xPSR_Type::V:1
uint32_t xPSR_Type::C:1
uint32_t xPSR_Type::Z:1
uint32_t xPSR_Type::N:1
struct {
uint32_t xPSR_Type::ISR:9
uint32_t xPSR_Type::_reserved0:7
uint32_t xPSR_Type::GE:4
uint32_t xPSR_Type::_reserved1:4
uint32_t xPSR_Type::T:1
uint32_t xPSR_Type::IT:2
uint32_t xPSR_Type::Q:1
uint32_t xPSR_Type::V:1
uint32_t xPSR_Type::C:1
uint32_t xPSR_Type::Z:1
uint32_t xPSR_Type::N:1
} | xPSR_Type::b
uint32_t CONTROL_Type::nPRIV:1
uint32_t CONTROL_Type::SPSEL:1
uint32_t CONTROL_Type::FPCA:1
uint32_t CONTROL_Type::SFPA:1
uint32_t CONTROL_Type::_reserved1:28
struct {
uint32_t CONTROL_Type::nPRIV:1
uint32_t CONTROL_Type::SPSEL:1
uint32_t CONTROL_Type::FPCA:1
uint32_t CONTROL_Type::SFPA:1
uint32_t CONTROL_Type::_reserved1:28
} | CONTROL_Type::b
__OM uint8_t ITM_Type::u8
__OM uint16_t ITM_Type::u16
__OM uint32_t ITM_Type::u32
union {
__OM uint8_t ITM_Type::u8
__OM uint16_t ITM_Type::u16
__OM uint32_t ITM_Type::u32
} | ITM_Type::PORT [32U]
uint32_t APSR_Type::_reserved0:16
uint32_t APSR_Type::GE:4
uint32_t APSR_Type::_reserved1:7
uint32_t APSR_Type::Q:1
uint32_t APSR_Type::V:1
uint32_t APSR_Type::C:1
uint32_t APSR_Type::Z:1
uint32_t APSR_Type::N:1
struct {
uint32_t APSR_Type::_reserved0:16
uint32_t APSR_Type::GE:4
uint32_t APSR_Type::_reserved1:7
uint32_t APSR_Type::Q:1
uint32_t APSR_Type::V:1
uint32_t APSR_Type::C:1
uint32_t APSR_Type::Z:1
uint32_t APSR_Type::N:1
} | APSR_Type::b
uint32_t IPSR_Type::ISR:9
uint32_t IPSR_Type::_reserved0:23
struct {
uint32_t IPSR_Type::ISR:9
uint32_t IPSR_Type::_reserved0:23
} | IPSR_Type::b
uint32_t xPSR_Type::ISR:9
uint32_t xPSR_Type::_reserved0:1
uint32_t xPSR_Type::ICI_IT_1:6
uint32_t xPSR_Type::GE:4
uint32_t xPSR_Type::_reserved1:4
uint32_t xPSR_Type::T:1
uint32_t xPSR_Type::ICI_IT_2:2
uint32_t xPSR_Type::Q:1
uint32_t xPSR_Type::V:1
uint32_t xPSR_Type::C:1
uint32_t xPSR_Type::Z:1
uint32_t xPSR_Type::N:1
struct {
uint32_t xPSR_Type::ISR:9
uint32_t xPSR_Type::_reserved0:1
uint32_t xPSR_Type::ICI_IT_1:6
uint32_t xPSR_Type::GE:4
uint32_t xPSR_Type::_reserved1:4
uint32_t xPSR_Type::T:1
uint32_t xPSR_Type::ICI_IT_2:2
uint32_t xPSR_Type::Q:1
uint32_t xPSR_Type::V:1
uint32_t xPSR_Type::C:1
uint32_t xPSR_Type::Z:1
uint32_t xPSR_Type::N:1
} | xPSR_Type::b
uint32_t CONTROL_Type::nPRIV:1
uint32_t CONTROL_Type::SPSEL:1
uint32_t CONTROL_Type::FPCA:1
uint32_t CONTROL_Type::_reserved0:29
struct {
uint32_t CONTROL_Type::nPRIV:1
uint32_t CONTROL_Type::SPSEL:1
uint32_t CONTROL_Type::FPCA:1
uint32_t CONTROL_Type::_reserved0:29
} | CONTROL_Type::b
uint32_t | NVIC_Type::RESERVED1 [24U]
__IOM uint8_t | NVIC_Type::IP [240U]
__IM uint32_t | SCB_Type::ID_AFR
__IM uint32_t | SCB_Type::ID_MFR [4U]
__OM uint8_t ITM_Type::u8
__OM uint16_t ITM_Type::u16
__OM uint32_t ITM_Type::u32
union {
__OM uint8_t ITM_Type::u8
__OM uint16_t ITM_Type::u16
__OM uint32_t ITM_Type::u32
} | ITM_Type::PORT [32U]
__IOM uint32_t | DWT_Type::MASK0
__IOM uint32_t | DWT_Type::MASK1
__IOM uint32_t | DWT_Type::MASK2
__IOM uint32_t | DWT_Type::MASK3
__OM uint32_t | DWT_Type::LAR
__IM uint32_t | FPU_Type::MVFR2
volatile int32_t | ITM_RxBuffer
__STATIC_INLINE uint32_t | ITM_SendChar (uint32_t ch)
| ITM Send Character. More...
__STATIC_INLINE int32_t | ITM_ReceiveChar (void)
| ITM Receive Character. More...
__STATIC_INLINE int32_t | ITM_CheckChar (void)
| ITM Check Character. More...
#define | ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
volatile int32_t | ITM_RxBuffer
#define | ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
volatile int32_t | ITM_RxBuffer
#define | ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

## Detailed Description

Functions that access the ITM debug interface.

## Macro Definition Documentation

## ◆ ITM_RXBUFFER_EMPTY [1/3]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2612 of file core_cm7.h.

## ◆ ITM_RXBUFFER_EMPTY [2/3]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2753 of file core_armv8mml.h.

## ◆ ITM_RXBUFFER_EMPTY [3/3]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2889 of file core_armv81mml.h.

## Function Documentation

## ◆ ITM_CheckChar()

__STATIC_INLINE int32_t ITM_CheckChar | ( | void |  | ) |

ITM Check Character.

Checks whether a character is pending for reading in the variable ITM_RxBuffer.

Returns
  0 No character available.
  1 Character available.

Definition at line 2941 of file core_armv81mml.h.

## ◆ ITM_ReceiveChar()

__STATIC_INLINE int32_t ITM_ReceiveChar | ( | void |  | ) |

ITM Receive Character.

Inputs a character via the external variable ITM_RxBuffer.

Returns
  Received character.
  -1 No character pending.

Definition at line 2921 of file core_armv81mml.h.

## ◆ ITM_SendChar()

__STATIC_INLINE uint32_t ITM_SendChar | ( | uint32_t | ch | ) |

ITM Send Character.

Transmits a character via the ITM channel 0, and

- Just returns when no debugger is connected that has booked the output.
- Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
  Parameters

    [in] | ch | Character to transmit.

  Returns
    Character to transmit.

Definition at line 2900 of file core_armv81mml.h.

## Variable Documentation

## ◆ _reserved0 [1/14]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 276 of file core_cm7.h.

## ◆ _reserved0 [2/14]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 316 of file core_armv8mml.h.

## ◆ _reserved0 [3/14]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 316 of file core_cm7.h.

## ◆ _reserved0 [4/14]

uint32_t APSR_Type::_reserved0

bit: 0..15 Reserved

bit: 0..27 Reserved

Definition at line 318 of file core_armv81mml.h.

## ◆ _reserved0 [5/14]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 318 of file core_armv81mml.h.

## ◆ _reserved0 [6/14]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 334 of file core_cm7.h.

## ◆ _reserved0 [7/14]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 356 of file core_armv8mml.h.

## ◆ _reserved0 [8/14]

uint32_t IPSR_Type::_reserved0

bit: 9..31 Reserved

Definition at line 358 of file core_armv81mml.h.

## ◆ _reserved0 [9/14]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 358 of file core_armv81mml.h.

## ◆ _reserved0 [10/14]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 374 of file core_armv8mml.h.

## ◆ _reserved0 [11/14]

uint32_t xPSR_Type::_reserved0

bit: 9..15 Reserved

bit: 9..23 Reserved

bit: 9 Reserved

Definition at line 376 of file core_armv81mml.h.

## ◆ _reserved0 [12/14]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 376 of file core_armv81mml.h.

## ◆ _reserved0 [13/14]

uint32_t CONTROL_Type::_reserved0

bit: 3..31 Reserved

Definition at line 391 of file core_cm7.h.

## ◆ _reserved0 [14/14]

uint32_t { ... } ::_reserved0

bit: 3..31 Reserved

Definition at line 391 of file core_cm7.h.

## ◆ _reserved1 [1/11]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 278 of file core_cm7.h.

## ◆ _reserved1 [2/11]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 318 of file core_armv8mml.h.

## ◆ _reserved1 [3/11]

uint32_t APSR_Type::_reserved1

bit: 20..26 Reserved

Definition at line 320 of file core_armv81mml.h.

## ◆ _reserved1 [4/11]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 320 of file core_armv81mml.h.

## ◆ _reserved1 [5/11]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 337 of file core_cm7.h.

## ◆ _reserved1 [6/11]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 376 of file core_armv8mml.h.

## ◆ _reserved1 [7/11]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 378 of file core_armv81mml.h.

## ◆ _reserved1 [8/11]

uint32_t xPSR_Type::_reserved1

bit: 20..23 Reserved

bit: 25..27 Reserved

Definition at line 378 of file core_armv81mml.h.

## ◆ _reserved1 [9/11]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 428 of file core_armv8mml.h.

## ◆ _reserved1 [10/11]

uint32_t CONTROL_Type::_reserved1

bit: 4..31 Reserved

bit: 2..31 Reserved

Definition at line 430 of file core_armv81mml.h.

## ◆ _reserved1 [11/11]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 430 of file core_armv81mml.h.

## ◆ ABFSR

__IOM uint32_t SCB_Type::ABFSR

Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register

Definition at line 548 of file core_armv81mml.h.

## ◆ ACPR

__IOM uint32_t TPI_Type::ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

Definition at line 1392 of file core_armv81mml.h.

## ◆ ACTLR

__IOM uint32_t SCnSCB_Type::ACTLR

Offset: 0x008 (R/W) Auxiliary Control Register

Definition at line 1013 of file core_armv81mml.h.

## ◆ AFSR

__IOM uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register

Definition at line 512 of file core_armv81mml.h.

## ◆ AHBPCR

__IOM uint32_t SCB_Type::AHBPCR

Offset: 0x298 (R/W) AHBP Control Register

Definition at line 544 of file core_armv81mml.h.

## ◆ AHBSCR

__IOM uint32_t SCB_Type::AHBSCR

Offset: 0x2A0 (R/W) AHB Slave Control Register

Definition at line 546 of file core_armv81mml.h.

## ◆ AIRCR

__IOM uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

Definition at line 502 of file core_armv81mml.h.

## ◆ b [1/12]

struct { ... } APSR_Type::b

Structure used for bit access

## ◆ b [2/12]

struct { ... } IPSR_Type::b

Structure used for bit access

## ◆ b [3/12]

struct { ... } APSR_Type::b

Structure used for bit access

## ◆ b [4/12]

struct { ... } APSR_Type::b

Structure used for bit access

## ◆ b [5/12]

struct { ... } xPSR_Type::b

Structure used for bit access

## ◆ b [6/12]

struct { ... } IPSR_Type::b

Structure used for bit access

## ◆ b [7/12]

struct { ... } IPSR_Type::b

Structure used for bit access

## ◆ b [8/12]

struct { ... } xPSR_Type::b

Structure used for bit access

## ◆ b [9/12]

struct { ... } xPSR_Type::b

Structure used for bit access

## ◆ b [10/12]

struct { ... } CONTROL_Type::b

Structure used for bit access

## ◆ b [11/12]

struct { ... } CONTROL_Type::b

Structure used for bit access

## ◆ b [12/12]

struct { ... } CONTROL_Type::b

Structure used for bit access

Referenced by C4_enterUnprivileged().

## ◆ BFAR

__IOM uint32_t SCB_Type::BFAR

Offset: 0x038 (R/W) BusFault Address Register

Definition at line 511 of file core_armv81mml.h.

## ◆ C [1/8]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 281 of file core_cm7.h.

## ◆ C [2/8]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 321 of file core_armv8mml.h.

## ◆ C [3/8]

uint32_t APSR_Type::C

bit: 29 Carry condition code flag

Definition at line 323 of file core_armv81mml.h.

## ◆ C [4/8]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 323 of file core_armv81mml.h.

## ◆ C [5/8]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 342 of file core_cm7.h.

## ◆ C [6/8]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 381 of file core_armv8mml.h.

## ◆ C [7/8]

uint32_t xPSR_Type::C

bit: 29 Carry condition code flag

Definition at line 383 of file core_armv81mml.h.

## ◆ C [8/8]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 383 of file core_armv81mml.h.

## ◆ CACR

__IOM uint32_t SCB_Type::CACR

Offset: 0x29C (R/W) L1 Cache Control Register

Definition at line 545 of file core_armv81mml.h.

## ◆ CALIB

__IM uint32_t SysTick_Type::CALIB

Offset: 0x00C (R/ ) SysTick Calibration Register

Definition at line 1039 of file core_armv81mml.h.

## ◆ CCR

__IOM uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register

Definition at line 504 of file core_armv81mml.h.

## ◆ CCSIDR

__IM uint32_t SCB_Type::CCSIDR

Offset: 0x080 (R/ ) Cache Size ID Register

Definition at line 520 of file core_armv81mml.h.

## ◆ CFSR

__IOM uint32_t SCB_Type::CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register

Definition at line 507 of file core_armv81mml.h.

## ◆ CID0

__IM uint32_t ITM_Type::CID0

Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

Definition at line 1118 of file core_armv81mml.h.

## ◆ CID1

__IM uint32_t ITM_Type::CID1

Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

Definition at line 1119 of file core_armv81mml.h.

## ◆ CID2

__IM uint32_t ITM_Type::CID2

Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

Definition at line 1120 of file core_armv81mml.h.

## ◆ CID3

__IM uint32_t ITM_Type::CID3

Offset: 0xFFC (R/ ) ITM Component Identification Register #3

Definition at line 1121 of file core_armv81mml.h.

## ◆ CLAIMCLR

__IOM uint32_t TPI_Type::CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear

Definition at line 1409 of file core_armv81mml.h.

## ◆ CLAIMSET

__IOM uint32_t TPI_Type::CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set

Definition at line 1408 of file core_armv81mml.h.

## ◆ CLIDR

__IM uint32_t SCB_Type::CLIDR

Offset: 0x078 (R/ ) Cache Level ID register

Definition at line 518 of file core_armv81mml.h.

## ◆ COMP0

__IOM uint32_t DWT_Type::COMP0

Offset: 0x020 (R/W) Comparator Register 0

Definition at line 1211 of file core_armv81mml.h.

## ◆ COMP1

__IOM uint32_t DWT_Type::COMP1

Offset: 0x030 (R/W) Comparator Register 1

Definition at line 1215 of file core_armv81mml.h.

## ◆ COMP10

__IOM uint32_t DWT_Type::COMP10

Offset: 0x0C0 (R/W) Comparator Register 10

Definition at line 1251 of file core_armv81mml.h.

## ◆ COMP11

__IOM uint32_t DWT_Type::COMP11

Offset: 0x0D0 (R/W) Comparator Register 11

Definition at line 1255 of file core_armv81mml.h.

## ◆ COMP12

__IOM uint32_t DWT_Type::COMP12

Offset: 0x0E0 (R/W) Comparator Register 12

Definition at line 1259 of file core_armv81mml.h.

## ◆ COMP13

__IOM uint32_t DWT_Type::COMP13

Offset: 0x0F0 (R/W) Comparator Register 13

Definition at line 1263 of file core_armv81mml.h.

## ◆ COMP14

__IOM uint32_t DWT_Type::COMP14

Offset: 0x100 (R/W) Comparator Register 14

Definition at line 1267 of file core_armv81mml.h.

## ◆ COMP15

__IOM uint32_t DWT_Type::COMP15

Offset: 0x110 (R/W) Comparator Register 15

Definition at line 1271 of file core_armv81mml.h.

## ◆ COMP2

__IOM uint32_t DWT_Type::COMP2

Offset: 0x040 (R/W) Comparator Register 2

Definition at line 1219 of file core_armv81mml.h.

## ◆ COMP3

__IOM uint32_t DWT_Type::COMP3

Offset: 0x050 (R/W) Comparator Register 3

Definition at line 1223 of file core_armv81mml.h.

## ◆ COMP4

__IOM uint32_t DWT_Type::COMP4

Offset: 0x060 (R/W) Comparator Register 4

Definition at line 1227 of file core_armv81mml.h.

## ◆ COMP5

__IOM uint32_t DWT_Type::COMP5

Offset: 0x070 (R/W) Comparator Register 5

Definition at line 1231 of file core_armv81mml.h.

## ◆ COMP6

__IOM uint32_t DWT_Type::COMP6

Offset: 0x080 (R/W) Comparator Register 6

Definition at line 1235 of file core_armv81mml.h.

## ◆ COMP7

__IOM uint32_t DWT_Type::COMP7

Offset: 0x090 (R/W) Comparator Register 7

Definition at line 1239 of file core_armv81mml.h.

## ◆ COMP8

__IOM uint32_t DWT_Type::COMP8

Offset: 0x0A0 (R/W) Comparator Register 8

Definition at line 1243 of file core_armv81mml.h.

## ◆ COMP9

__IOM uint32_t DWT_Type::COMP9

Offset: 0x0B0 (R/W) Comparator Register 9

Definition at line 1247 of file core_armv81mml.h.

## ◆ CPACR

__IOM uint32_t SCB_Type::CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register

Definition at line 522 of file core_armv81mml.h.

## ◆ CPICNT

__IOM uint32_t DWT_Type::CPICNT

Offset: 0x008 (R/W) CPI Count Register

Definition at line 1205 of file core_armv81mml.h.

## ◆ CPPWR

__IOM uint32_t SCnSCB_Type::CPPWR

Offset: 0x00C (R/W) Coprocessor Power Control Register

Definition at line 1014 of file core_armv81mml.h.

## ◆ CPUID

__IM uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register

Definition at line 499 of file core_armv81mml.h.

## ◆ CSPSR

__IOM uint32_t TPI_Type::CSPSR

Offset: 0x004 (R/W) Current Parallel Port Sizes Register

Offset: 0x004 (R/W) Current Parallel Port Size Register

Definition at line 1390 of file core_armv81mml.h.

## ◆ CSSELR

__IOM uint32_t SCB_Type::CSSELR

Offset: 0x084 (R/W) Cache Size Selection Register

Definition at line 521 of file core_armv81mml.h.

## ◆ CTR

__IM uint32_t SCB_Type::CTR

Offset: 0x07C (R/ ) Cache Type register

Definition at line 519 of file core_armv81mml.h.

## ◆ CTRL [1/2]

__IOM uint32_t SysTick_Type::CTRL

Offset: 0x000 (R/W) SysTick Control and Status Register

Definition at line 1036 of file core_armv81mml.h.

## ◆ CTRL [2/2]

__IOM uint32_t DWT_Type::CTRL

Offset: 0x000 (R/W) Control Register

Definition at line 1203 of file core_armv81mml.h.

## ◆ CYCCNT

__IOM uint32_t DWT_Type::CYCCNT

Offset: 0x004 (R/W) Cycle Count Register

Definition at line 1204 of file core_armv81mml.h.

## ◆ DAUTHCTRL

__IOM uint32_t CoreDebug_Type::DAUTHCTRL

Offset: 0x014 (R/W) Debug Authentication Control Register

Definition at line 1882 of file core_armv81mml.h.

## ◆ DCCIMVAC

__OM uint32_t SCB_Type::DCCIMVAC

Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC

Definition at line 539 of file core_armv81mml.h.

## ◆ DCCISW

__OM uint32_t SCB_Type::DCCISW

Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way

Definition at line 540 of file core_armv81mml.h.

## ◆ DCCMVAC

__OM uint32_t SCB_Type::DCCMVAC

Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC

Definition at line 537 of file core_armv81mml.h.

## ◆ DCCMVAU

__OM uint32_t SCB_Type::DCCMVAU

Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU

Definition at line 536 of file core_armv81mml.h.

## ◆ DCCSW

__OM uint32_t SCB_Type::DCCSW

Offset: 0x26C ( /W) D-Cache Clean by Set-way

Definition at line 538 of file core_armv81mml.h.

## ◆ DCIMVAC

__OM uint32_t SCB_Type::DCIMVAC

Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC

Definition at line 534 of file core_armv81mml.h.

## ◆ DCISW

__OM uint32_t SCB_Type::DCISW

Offset: 0x260 ( /W) D-Cache Invalidate by Set-way

Definition at line 535 of file core_armv81mml.h.

## ◆ DCRDR

__IOM uint32_t CoreDebug_Type::DCRDR

Offset: 0x008 (R/W) Debug Core Register Data Register

Definition at line 1879 of file core_armv81mml.h.

## ◆ DCRSR

__OM uint32_t CoreDebug_Type::DCRSR

Offset: 0x004 ( /W) Debug Core Register Selector Register

Definition at line 1878 of file core_armv81mml.h.

## ◆ DEMCR

__IOM uint32_t CoreDebug_Type::DEMCR

Offset: 0x00C (R/W) Debug Exception and Monitor Control Register

Definition at line 1880 of file core_armv81mml.h.

## ◆ DEVARCH [1/2]

__IM uint32_t ITM_Type::DEVARCH

Offset: 0xFBC (R/ ) ITM Device Architecture Register

Definition at line 1108 of file core_armv81mml.h.

## ◆ DEVARCH [2/2]

__IM uint32_t DWT_Type::DEVARCH

Offset: 0xFBC (R/ ) Device Architecture Register

Definition at line 1277 of file core_armv81mml.h.

## ◆ DEVID

__IM uint32_t TPI_Type::DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID

Definition at line 1411 of file core_armv81mml.h.

## ◆ DEVTYPE

__IM uint32_t TPI_Type::DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

Offset: 0xFCC (R/ ) Device Type Register

Definition at line 1412 of file core_armv81mml.h.

## ◆ DFSR

__IOM uint32_t SCB_Type::DFSR

Offset: 0x030 (R/W) Debug Fault Status Register

Definition at line 509 of file core_armv81mml.h.

## ◆ DHCSR

__IOM uint32_t CoreDebug_Type::DHCSR

Offset: 0x000 (R/W) Debug Halting Control and Status Register

Definition at line 1877 of file core_armv81mml.h.

## ◆ DSCSR

__IOM uint32_t CoreDebug_Type::DSCSR

Offset: 0x018 (R/W) Debug Security Control and Status Register

Definition at line 1883 of file core_armv81mml.h.

## ◆ DTCMCR

__IOM uint32_t SCB_Type::DTCMCR

Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers

Definition at line 543 of file core_armv81mml.h.

## ◆ EXCCNT

__IOM uint32_t DWT_Type::EXCCNT

Offset: 0x00C (R/W) Exception Overhead Count Register

Definition at line 1206 of file core_armv81mml.h.

## ◆ FFCR

__IOM uint32_t TPI_Type::FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register

Definition at line 1397 of file core_armv81mml.h.

## ◆ FFSR

__IM uint32_t TPI_Type::FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register

Definition at line 1396 of file core_armv81mml.h.

## ◆ FIFO0

__IM uint32_t TPI_Type::FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data

Definition at line 1401 of file core_armv81mml.h.

## ◆ FIFO1

__IM uint32_t TPI_Type::FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data

Definition at line 1405 of file core_armv81mml.h.

## ◆ FOLDCNT

__IOM uint32_t DWT_Type::FOLDCNT

Offset: 0x018 (R/W) Folded-instruction Count Register

Definition at line 1209 of file core_armv81mml.h.

## ◆ FPCA [1/4]

uint32_t { ... } ::FPCA

bit: 2 FP extension active flag

Definition at line 390 of file core_cm7.h.

## ◆ FPCA [2/4]

uint32_t { ... } ::FPCA

bit: 2 Floating-point context active

Definition at line 426 of file core_armv8mml.h.

## ◆ FPCA [3/4]

uint32_t CONTROL_Type::FPCA

bit: 2 Floating-point context active

bit: 2 FP extension active flag

Definition at line 428 of file core_armv81mml.h.

## ◆ FPCA [4/4]

uint32_t { ... } ::FPCA

bit: 2 Floating-point context active

Definition at line 428 of file core_armv81mml.h.

## ◆ FPCAR

__IOM uint32_t FPU_Type::FPCAR

Offset: 0x008 (R/W) Floating-Point Context Address Register

Definition at line 1749 of file core_armv81mml.h.

## ◆ FPCCR

__IOM uint32_t FPU_Type::FPCCR

Offset: 0x004 (R/W) Floating-Point Context Control Register

Definition at line 1748 of file core_armv81mml.h.

## ◆ FPDSCR

__IOM uint32_t FPU_Type::FPDSCR

Offset: 0x00C (R/W) Floating-Point Default Status Control Register

Definition at line 1750 of file core_armv81mml.h.

## ◆ FSCR

__IM uint32_t TPI_Type::FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

Definition at line 1398 of file core_armv81mml.h.

## ◆ FUNCTION0

__IOM uint32_t DWT_Type::FUNCTION0

Offset: 0x028 (R/W) Function Register 0

Definition at line 1213 of file core_armv81mml.h.

## ◆ FUNCTION1

__IOM uint32_t DWT_Type::FUNCTION1

Offset: 0x038 (R/W) Function Register 1

Definition at line 1217 of file core_armv81mml.h.

## ◆ FUNCTION10

__IOM uint32_t DWT_Type::FUNCTION10

Offset: 0x0C8 (R/W) Function Register 10

Definition at line 1253 of file core_armv81mml.h.

## ◆ FUNCTION11

__IOM uint32_t DWT_Type::FUNCTION11

Offset: 0x0D8 (R/W) Function Register 11

Definition at line 1257 of file core_armv81mml.h.

## ◆ FUNCTION12

__IOM uint32_t DWT_Type::FUNCTION12

Offset: 0x0E8 (R/W) Function Register 12

Definition at line 1261 of file core_armv81mml.h.

## ◆ FUNCTION13

__IOM uint32_t DWT_Type::FUNCTION13

Offset: 0x0F8 (R/W) Function Register 13

Definition at line 1265 of file core_armv81mml.h.

## ◆ FUNCTION14

__IOM uint32_t DWT_Type::FUNCTION14

Offset: 0x108 (R/W) Function Register 14

Definition at line 1269 of file core_armv81mml.h.

## ◆ FUNCTION15

__IOM uint32_t DWT_Type::FUNCTION15

Offset: 0x118 (R/W) Function Register 15

Definition at line 1273 of file core_armv81mml.h.

## ◆ FUNCTION2

__IOM uint32_t DWT_Type::FUNCTION2

Offset: 0x048 (R/W) Function Register 2

Definition at line 1221 of file core_armv81mml.h.

## ◆ FUNCTION3

__IOM uint32_t DWT_Type::FUNCTION3

Offset: 0x058 (R/W) Function Register 3

Definition at line 1225 of file core_armv81mml.h.

## ◆ FUNCTION4

__IOM uint32_t DWT_Type::FUNCTION4

Offset: 0x068 (R/W) Function Register 4

Definition at line 1229 of file core_armv81mml.h.

## ◆ FUNCTION5

__IOM uint32_t DWT_Type::FUNCTION5

Offset: 0x078 (R/W) Function Register 5

Definition at line 1233 of file core_armv81mml.h.

## ◆ FUNCTION6

__IOM uint32_t DWT_Type::FUNCTION6

Offset: 0x088 (R/W) Function Register 6

Definition at line 1237 of file core_armv81mml.h.

## ◆ FUNCTION7

__IOM uint32_t DWT_Type::FUNCTION7

Offset: 0x098 (R/W) Function Register 7

Definition at line 1241 of file core_armv81mml.h.

## ◆ FUNCTION8

__IOM uint32_t DWT_Type::FUNCTION8

Offset: 0x0A8 (R/W) Function Register 8

Definition at line 1245 of file core_armv81mml.h.

## ◆ FUNCTION9

__IOM uint32_t DWT_Type::FUNCTION9

Offset: 0x0B8 (R/W) Function Register 9

Definition at line 1249 of file core_armv81mml.h.

## ◆ GE [1/8]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 277 of file core_cm7.h.

## ◆ GE [2/8]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 317 of file core_armv8mml.h.

## ◆ GE [3/8]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 319 of file core_armv81mml.h.

## ◆ GE [4/8]

uint32_t APSR_Type::GE

bit: 16..19 Greater than or Equal flags

Definition at line 319 of file core_armv81mml.h.

## ◆ GE [5/8]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 336 of file core_cm7.h.

## ◆ GE [6/8]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 375 of file core_armv8mml.h.

## ◆ GE [7/8]

uint32_t xPSR_Type::GE

bit: 16..19 Greater than or Equal flags

Definition at line 377 of file core_armv81mml.h.

## ◆ GE [8/8]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 377 of file core_armv81mml.h.

## ◆ HFSR

__IOM uint32_t SCB_Type::HFSR

Offset: 0x02C (R/W) HardFault Status Register

Definition at line 508 of file core_armv81mml.h.

## ◆ IABR

__IOM uint32_t NVIC_Type::IABR

Offset: 0x200 (R/W) Interrupt Active bit Register

Definition at line 471 of file core_armv81mml.h.

## ◆ ICER

__IOM uint32_t NVIC_Type::ICER

Offset: 0x080 (R/W) Interrupt Clear Enable Register

Definition at line 465 of file core_armv81mml.h.

## ◆ ICI_IT_1 [1/2]

uint32_t xPSR_Type::ICI_IT_1

bit: 10..15 ICI/IT part 1

Definition at line 335 of file core_cm7.h.

## ◆ ICI_IT_1 [2/2]

uint32_t { ... } ::ICI_IT_1

bit: 10..15 ICI/IT part 1

Definition at line 335 of file core_cm7.h.

## ◆ ICI_IT_2 [1/2]

uint32_t { ... } ::ICI_IT_2

bit: 25..26 ICI/IT part 2

Definition at line 339 of file core_cm7.h.

## ◆ ICI_IT_2 [2/2]

uint32_t xPSR_Type::ICI_IT_2

bit: 25..26 ICI/IT part 2

Definition at line 339 of file core_cm7.h.

## ◆ ICIALLU

__OM uint32_t SCB_Type::ICIALLU

Offset: 0x250 ( /W) I-Cache Invalidate All to PoU

Definition at line 531 of file core_armv81mml.h.

## ◆ ICIMVAU

__OM uint32_t SCB_Type::ICIMVAU

Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU

Definition at line 533 of file core_armv81mml.h.

## ◆ ICPR

__IOM uint32_t NVIC_Type::ICPR

Offset: 0x180 (R/W) Interrupt Clear Pending Register

Definition at line 469 of file core_armv81mml.h.

## ◆ ICSR

__IOM uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

Definition at line 500 of file core_armv81mml.h.

## ◆ ICTR

__IM uint32_t SCnSCB_Type::ICTR

Offset: 0x004 (R/ ) Interrupt Controller Type Register

Definition at line 1012 of file core_armv81mml.h.

## ◆ ID_ADR

__IM uint32_t SCB_Type::ID_ADR

Offset: 0x04C (R/ ) Auxiliary Feature Register

Definition at line 515 of file core_armv81mml.h.

## ◆ ID_AFR

__IM uint32_t SCB_Type::ID_AFR

Offset: 0x04C (R/ ) Auxiliary Feature Register

Definition at line 471 of file core_cm7.h.

## ◆ ID_DFR

__IM uint32_t SCB_Type::ID_DFR

Offset: 0x048 (R/ ) Debug Feature Register

Definition at line 514 of file core_armv81mml.h.

## ◆ ID_ISAR

__IM uint32_t SCB_Type::ID_ISAR

Offset: 0x060 (R/ ) Instruction Set Attributes Register

Definition at line 517 of file core_armv81mml.h.

## ◆ ID_MFR

__IM uint32_t SCB_Type::ID_MFR[4U]

Offset: 0x050 (R/ ) Memory Model Feature Register

Definition at line 472 of file core_cm7.h.

## ◆ ID_MMFR

__IM uint32_t SCB_Type::ID_MMFR

Offset: 0x050 (R/ ) Memory Model Feature Register

Definition at line 516 of file core_armv81mml.h.

## ◆ ID_PFR

__IM uint32_t SCB_Type::ID_PFR

Offset: 0x040 (R/ ) Processor Feature Register

Definition at line 513 of file core_armv81mml.h.

## ◆ IMCR

__IOM uint32_t ITM_Type::IMCR

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

Definition at line 1103 of file core_armv81mml.h.

## ◆ IP

__IOM uint8_t NVIC_Type::IP[240U]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 431 of file core_cm7.h.

## ◆ IPR

__IOM uint8_t NVIC_Type::IPR

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 475 of file core_armv81mml.h.

## ◆ IRR

__IM uint32_t ITM_Type::IRR

Offset: 0xEFC (R/ ) ITM Integration Read Register

Definition at line 1102 of file core_armv81mml.h.

## ◆ ISER

__IOM uint32_t NVIC_Type::ISER

Offset: 0x000 (R/W) Interrupt Set Enable Register

Definition at line 463 of file core_armv81mml.h.

## ◆ ISPR

__IOM uint32_t NVIC_Type::ISPR

Offset: 0x100 (R/W) Interrupt Set Pending Register

Definition at line 467 of file core_armv81mml.h.

## ◆ ISR [1/8]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 315 of file core_cm7.h.

## ◆ ISR [2/8]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 333 of file core_cm7.h.

## ◆ ISR [3/8]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 355 of file core_armv8mml.h.

## ◆ ISR [4/8]

uint32_t IPSR_Type::ISR

bit: 0.. 8 Exception number

Definition at line 357 of file core_armv81mml.h.

## ◆ ISR [5/8]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 357 of file core_armv81mml.h.

## ◆ ISR [6/8]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 373 of file core_armv8mml.h.

## ◆ ISR [7/8]

uint32_t xPSR_Type::ISR

bit: 0.. 8 Exception number

Definition at line 375 of file core_armv81mml.h.

## ◆ ISR [8/8]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 375 of file core_armv81mml.h.

## ◆ IT [1/3]

uint32_t { ... } ::IT

bit: 25..26 saved IT state (read 0)

Definition at line 378 of file core_armv8mml.h.

## ◆ IT [2/3]

uint32_t xPSR_Type::IT

bit: 25..26 saved IT state (read 0)

Definition at line 380 of file core_armv81mml.h.

## ◆ IT [3/3]

uint32_t { ... } ::IT

bit: 25..26 saved IT state (read 0)

Definition at line 380 of file core_armv81mml.h.

## ◆ ITATBCTR0

__IM uint32_t TPI_Type::ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0

Definition at line 1404 of file core_armv81mml.h.

## ◆ ITATBCTR2

__IM uint32_t TPI_Type::ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2

Definition at line 1402 of file core_armv81mml.h.

## ◆ ITCMCR

__IOM uint32_t SCB_Type::ITCMCR

Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register

Definition at line 542 of file core_armv81mml.h.

## ◆ ITCTRL

__IOM uint32_t TPI_Type::ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control

Definition at line 1406 of file core_armv81mml.h.

## ◆ ITM_RxBuffer [1/3]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

## ◆ ITM_RxBuffer [2/3]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

## ◆ ITM_RxBuffer [3/3]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

## ◆ ITNS

__IOM uint32_t NVIC_Type::ITNS

Offset: 0x280 (R/W) Interrupt Non-Secure State Register

Definition at line 473 of file core_armv81mml.h.

## ◆ IWR

__OM uint32_t ITM_Type::IWR

Offset: 0xEF8 ( /W) ITM Integration Write Register

Definition at line 1101 of file core_armv81mml.h.

## ◆ LAR [1/2]

__OM uint32_t ITM_Type::LAR

Offset: 0xFB0 ( /W) ITM Lock Access Register

Definition at line 1105 of file core_armv81mml.h.

## ◆ LAR [2/2]

__OM uint32_t DWT_Type::LAR

Offset: 0xFB0 ( W) Lock Access Register

Definition at line 1143 of file core_cm7.h.

## ◆ LOAD

__IOM uint32_t SysTick_Type::LOAD

Offset: 0x004 (R/W) SysTick Reload Value Register

Definition at line 1037 of file core_armv81mml.h.

## ◆ LSR [1/2]

__IM uint32_t ITM_Type::LSR

Offset: 0xFB4 (R/ ) ITM Lock Status Register

Definition at line 1106 of file core_armv81mml.h.

## ◆ LSR [2/2]

__IM uint32_t DWT_Type::LSR

Offset: 0xFB4 (R ) Lock Status Register

Definition at line 1275 of file core_armv81mml.h.

## ◆ LSUCNT

__IOM uint32_t DWT_Type::LSUCNT

Offset: 0x014 (R/W) LSU Count Register

Definition at line 1208 of file core_armv81mml.h.

## ◆ MASK0

__IOM uint32_t DWT_Type::MASK0

Offset: 0x024 (R/W) Mask Register 0

Definition at line 1128 of file core_cm7.h.

## ◆ MASK1

__IOM uint32_t DWT_Type::MASK1

Offset: 0x034 (R/W) Mask Register 1

Definition at line 1132 of file core_cm7.h.

## ◆ MASK2

__IOM uint32_t DWT_Type::MASK2

Offset: 0x044 (R/W) Mask Register 2

Definition at line 1136 of file core_cm7.h.

## ◆ MASK3

__IOM uint32_t DWT_Type::MASK3

Offset: 0x054 (R/W) Mask Register 3

Definition at line 1140 of file core_cm7.h.

## ◆ MMFAR

__IOM uint32_t SCB_Type::MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register

Definition at line 510 of file core_armv81mml.h.

## ◆ MVFR0 [1/2]

__IM uint32_t SCB_Type::MVFR0

Offset: 0x240 (R/ ) Media and VFP Feature Register 0

Definition at line 527 of file core_armv81mml.h.

## ◆ MVFR0 [2/2]

__IM uint32_t FPU_Type::MVFR0

Offset: 0x010 (R/ ) Media and FP Feature Register 0

Definition at line 1751 of file core_armv81mml.h.

## ◆ MVFR1 [1/2]

__IM uint32_t SCB_Type::MVFR1

Offset: 0x244 (R/ ) Media and VFP Feature Register 1

Definition at line 528 of file core_armv81mml.h.

## ◆ MVFR1 [2/2]

__IM uint32_t FPU_Type::MVFR1

Offset: 0x014 (R/ ) Media and FP Feature Register 1

Definition at line 1752 of file core_armv81mml.h.

## ◆ MVFR2 [1/2]

__IM uint32_t SCB_Type::MVFR2

Offset: 0x248 (R/ ) Media and VFP Feature Register 2

Definition at line 529 of file core_armv81mml.h.

## ◆ MVFR2 [2/2]

__IM uint32_t FPU_Type::MVFR2

Offset: 0x018 (R/ ) Media and FP Feature Register 2

Definition at line 1533 of file core_cm7.h.

## ◆ N [1/8]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 283 of file core_cm7.h.

## ◆ N [2/8]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 323 of file core_armv8mml.h.

## ◆ N [3/8]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 325 of file core_armv81mml.h.

## ◆ N [4/8]

uint32_t APSR_Type::N

bit: 31 Negative condition code flag

Definition at line 325 of file core_armv81mml.h.

## ◆ N [5/8]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 344 of file core_cm7.h.

## ◆ N [6/8]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 383 of file core_armv8mml.h.

## ◆ N [7/8]

uint32_t xPSR_Type::N

bit: 31 Negative condition code flag

Definition at line 385 of file core_armv81mml.h.

## ◆ N [8/8]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 385 of file core_armv81mml.h.

## ◆ nPRIV [1/4]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 388 of file core_cm7.h.

## ◆ nPRIV [2/4]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 424 of file core_armv8mml.h.

## ◆ nPRIV [3/4]

uint32_t CONTROL_Type::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 426 of file core_armv81mml.h.

Referenced by C4_enterUnprivileged().

## ◆ nPRIV [4/4]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 426 of file core_armv81mml.h.

## ◆ NSACR

__IOM uint32_t SCB_Type::NSACR

Offset: 0x08C (R/W) Non-Secure Access Control Register

Definition at line 523 of file core_armv81mml.h.

## ◆ PCSR

__IM uint32_t DWT_Type::PCSR

Offset: 0x01C (R/ ) Program Counter Sample Register

Definition at line 1210 of file core_armv81mml.h.

## ◆ PID0

__IM uint32_t ITM_Type::PID0

Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

Definition at line 1114 of file core_armv81mml.h.

## ◆ PID1

__IM uint32_t ITM_Type::PID1

Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

Definition at line 1115 of file core_armv81mml.h.

## ◆ PID2

__IM uint32_t ITM_Type::PID2

Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

Definition at line 1116 of file core_armv81mml.h.

## ◆ PID3

__IM uint32_t ITM_Type::PID3

Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

Definition at line 1117 of file core_armv81mml.h.

## ◆ PID4

__IM uint32_t ITM_Type::PID4

Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

Definition at line 1110 of file core_armv81mml.h.

## ◆ PID5

__IM uint32_t ITM_Type::PID5

Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

Definition at line 1111 of file core_armv81mml.h.

## ◆ PID6

__IM uint32_t ITM_Type::PID6

Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

Definition at line 1112 of file core_armv81mml.h.

## ◆ PID7

__IM uint32_t ITM_Type::PID7

Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

Definition at line 1113 of file core_armv81mml.h.

## ◆ PORT [1/3]

__OM { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

## ◆ PORT [2/3]

__OM { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

## ◆ PORT [3/3]

__OM { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

## ◆ Q [1/8]

uint32_t { ... } ::Q

bit: 27 Saturation condition flag

Definition at line 279 of file core_cm7.h.

## ◆ Q [2/8]

uint32_t { ... } ::Q

bit: 27 Saturation condition flag

Definition at line 319 of file core_armv8mml.h.

## ◆ Q [3/8]

uint32_t { ... } ::Q

bit: 27 Saturation condition flag

Definition at line 321 of file core_armv81mml.h.

## ◆ Q [4/8]

uint32_t APSR_Type::Q

bit: 27 Saturation condition flag

Definition at line 321 of file core_armv81mml.h.

## ◆ Q [5/8]

uint32_t { ... } ::Q

bit: 27 Saturation condition flag

Definition at line 340 of file core_cm7.h.

## ◆ Q [6/8]

uint32_t { ... } ::Q

bit: 27 Saturation condition flag

Definition at line 379 of file core_armv8mml.h.

## ◆ Q [7/8]

uint32_t { ... } ::Q

bit: 27 Saturation condition flag

Definition at line 381 of file core_armv81mml.h.

## ◆ Q [8/8]

uint32_t xPSR_Type::Q

bit: 27 Saturation condition flag

Definition at line 381 of file core_armv81mml.h.

## ◆ RESERVED0 [1/5]

uint32_t NVIC_Type::RESERVED0

Definition at line 464 of file core_armv81mml.h.

## ◆ RESERVED0 [2/5]

uint32_t SCnSCB_Type::RESERVED0

Definition at line 1011 of file core_armv81mml.h.

## ◆ RESERVED0 [3/5]

uint32_t FPU_Type::RESERVED0

Definition at line 1747 of file core_armv81mml.h.

## ◆ RESERVED0 [4/5]

uint32_t TPI_Type::RESERVED0

Definition at line 1391 of file core_armv81mml.h.

## ◆ RESERVED0 [5/5]

uint32_t ITM_Type::RESERVED0

Definition at line 1094 of file core_armv81mml.h.

## ◆ RESERVED1 [1/4]

uint32_t ITM_Type::RESERVED1

Definition at line 1096 of file core_armv81mml.h.

## ◆ RESERVED1 [2/4]

uint32_t DWT_Type::RESERVED1

Definition at line 1212 of file core_armv81mml.h.

## ◆ RESERVED1 [3/4]

uint32_t NVIC_Type::RESERVED1[24U]

Definition at line 424 of file core_cm7.h.

## ◆ RESERVED1 [4/4]

uint32_t TPI_Type::RESERVED1

Definition at line 1393 of file core_armv81mml.h.

## ◆ RESERVED10

uint32_t DWT_Type::RESERVED10

Definition at line 1230 of file core_armv81mml.h.

## ◆ RESERVED11

uint32_t DWT_Type::RESERVED11

Definition at line 1232 of file core_armv81mml.h.

## ◆ RESERVED12

uint32_t DWT_Type::RESERVED12

Definition at line 1234 of file core_armv81mml.h.

## ◆ RESERVED13

uint32_t DWT_Type::RESERVED13

Definition at line 1236 of file core_armv81mml.h.

## ◆ RESERVED14

uint32_t DWT_Type::RESERVED14

Definition at line 1238 of file core_armv81mml.h.

## ◆ RESERVED15

uint32_t DWT_Type::RESERVED15

Definition at line 1240 of file core_armv81mml.h.

## ◆ RESERVED16

uint32_t DWT_Type::RESERVED16

Definition at line 1242 of file core_armv81mml.h.

## ◆ RESERVED17

uint32_t DWT_Type::RESERVED17

Definition at line 1244 of file core_armv81mml.h.

## ◆ RESERVED18

uint32_t DWT_Type::RESERVED18

Definition at line 1246 of file core_armv81mml.h.

## ◆ RESERVED19

uint32_t DWT_Type::RESERVED19

Definition at line 1248 of file core_armv81mml.h.

## ◆ RESERVED2 [1/4]

uint32_t TPI_Type::RESERVED2

Definition at line 1395 of file core_armv81mml.h.

## ◆ RESERVED2 [2/4]

uint32_t ITM_Type::RESERVED2

Definition at line 1098 of file core_armv81mml.h.

## ◆ RESERVED2 [3/4]

uint32_t NVIC_Type::RESERVED2

Definition at line 468 of file core_armv81mml.h.

## ◆ RESERVED2 [4/4]

uint32_t DWT_Type::RESERVED2

Definition at line 1214 of file core_armv81mml.h.

## ◆ RESERVED20

uint32_t DWT_Type::RESERVED20

Definition at line 1250 of file core_armv81mml.h.

## ◆ RESERVED21

uint32_t DWT_Type::RESERVED21

Definition at line 1252 of file core_armv81mml.h.

## ◆ RESERVED22

uint32_t DWT_Type::RESERVED22

Definition at line 1254 of file core_armv81mml.h.

## ◆ RESERVED23

uint32_t DWT_Type::RESERVED23

Definition at line 1256 of file core_armv81mml.h.

## ◆ RESERVED24

uint32_t DWT_Type::RESERVED24

Definition at line 1258 of file core_armv81mml.h.

## ◆ RESERVED25

uint32_t DWT_Type::RESERVED25

Definition at line 1260 of file core_armv81mml.h.

## ◆ RESERVED26

uint32_t DWT_Type::RESERVED26

Definition at line 1262 of file core_armv81mml.h.

## ◆ RESERVED27

uint32_t DWT_Type::RESERVED27

Definition at line 1264 of file core_armv81mml.h.

## ◆ RESERVED28

uint32_t DWT_Type::RESERVED28

Definition at line 1266 of file core_armv81mml.h.

## ◆ RESERVED29

uint32_t DWT_Type::RESERVED29

Definition at line 1268 of file core_armv81mml.h.

## ◆ RESERVED3 [1/5]

uint32_t NVIC_Type::RESERVED3

Definition at line 470 of file core_armv81mml.h.

## ◆ RESERVED3 [2/5]

uint32_t DWT_Type::RESERVED3

Definition at line 1216 of file core_armv81mml.h.

## ◆ RESERVED3 [3/5]

uint32_t ITM_Type::RESERVED3

Definition at line 1100 of file core_armv81mml.h.

## ◆ RESERVED3 [4/5]

uint32_t TPI_Type::RESERVED3

Definition at line 1399 of file core_armv81mml.h.

## ◆ RESERVED3 [5/5]

uint32_t SCB_Type::RESERVED3

Definition at line 524 of file core_armv81mml.h.

## ◆ RESERVED30

uint32_t DWT_Type::RESERVED30

Definition at line 1270 of file core_armv81mml.h.

## ◆ RESERVED31

uint32_t DWT_Type::RESERVED31

Definition at line 1272 of file core_armv81mml.h.

## ◆ RESERVED32

uint32_t DWT_Type::RESERVED32

Definition at line 1274 of file core_armv81mml.h.

## ◆ RESERVED33

uint32_t DWT_Type::RESERVED33

Definition at line 1276 of file core_armv81mml.h.

## ◆ RESERVED4 [1/6]

uint32_t SCB_Type::RESERVED4

Definition at line 526 of file core_armv81mml.h.

## ◆ RESERVED4 [2/6]

uint32_t NVIC_Type::RESERVED4

Definition at line 472 of file core_armv81mml.h.

## ◆ RESERVED4 [3/6]

uint32_t DWT_Type::RESERVED4

Definition at line 1218 of file core_armv81mml.h.

## ◆ RESERVED4 [4/6]

uint32_t TPI_Type::RESERVED4

Definition at line 1403 of file core_armv81mml.h.

## ◆ RESERVED4 [5/6]

uint32_t CoreDebug_Type::RESERVED4

Definition at line 1881 of file core_armv81mml.h.

## ◆ RESERVED4 [6/6]

uint32_t ITM_Type::RESERVED4

Definition at line 1104 of file core_armv81mml.h.

## ◆ RESERVED5 [1/5]

uint32_t NVIC_Type::RESERVED5

Definition at line 474 of file core_armv81mml.h.

## ◆ RESERVED5 [2/5]

uint32_t SCB_Type::RESERVED5

Definition at line 530 of file core_armv81mml.h.

## ◆ RESERVED5 [3/5]

uint32_t ITM_Type::RESERVED5

Definition at line 1107 of file core_armv81mml.h.

## ◆ RESERVED5 [4/5]

uint32_t DWT_Type::RESERVED5

Definition at line 1220 of file core_armv81mml.h.

## ◆ RESERVED5 [5/5]

uint32_t TPI_Type::RESERVED5

Definition at line 1407 of file core_armv81mml.h.

## ◆ RESERVED6 [1/4]

uint32_t SCB_Type::RESERVED6

Definition at line 532 of file core_armv81mml.h.

## ◆ RESERVED6 [2/4]

uint32_t DWT_Type::RESERVED6

Definition at line 1222 of file core_armv81mml.h.

## ◆ RESERVED6 [3/4]

uint32_t ITM_Type::RESERVED6

Definition at line 1109 of file core_armv81mml.h.

## ◆ RESERVED6 [4/4]

uint32_t NVIC_Type::RESERVED6

Definition at line 476 of file core_armv81mml.h.

## ◆ RESERVED7 [1/3]

uint32_t DWT_Type::RESERVED7

Definition at line 1224 of file core_armv81mml.h.

## ◆ RESERVED7 [2/3]

uint32_t SCB_Type::RESERVED7

Definition at line 541 of file core_armv81mml.h.

## ◆ RESERVED7 [3/3]

uint32_t TPI_Type::RESERVED7

Definition at line 1410 of file core_armv81mml.h.

## ◆ RESERVED8 [1/2]

uint32_t SCB_Type::RESERVED8

Definition at line 547 of file core_armv81mml.h.

## ◆ RESERVED8 [2/2]

uint32_t DWT_Type::RESERVED8

Definition at line 1226 of file core_armv81mml.h.

## ◆ RESERVED9

uint32_t DWT_Type::RESERVED9

Definition at line 1228 of file core_armv81mml.h.

## ◆ RSERVED1

uint32_t NVIC_Type::RSERVED1

Definition at line 466 of file core_armv81mml.h.

## ◆ SCR

__IOM uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register

Definition at line 503 of file core_armv81mml.h.

## ◆ SFPA [1/3]

uint32_t { ... } ::SFPA

bit: 3 Secure floating-point active

Definition at line 427 of file core_armv8mml.h.

## ◆ SFPA [2/3]

uint32_t CONTROL_Type::SFPA

bit: 3 Secure floating-point active

Definition at line 429 of file core_armv81mml.h.

## ◆ SFPA [3/3]

uint32_t { ... } ::SFPA

bit: 3 Secure floating-point active

Definition at line 429 of file core_armv81mml.h.

## ◆ SHCSR

__IOM uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

Definition at line 506 of file core_armv81mml.h.

## ◆ SHPR

__IOM uint8_t SCB_Type::SHPR

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

Definition at line 505 of file core_armv81mml.h.

## ◆ SLEEPCNT

__IOM uint32_t DWT_Type::SLEEPCNT

Offset: 0x010 (R/W) Sleep Count Register

Definition at line 1207 of file core_armv81mml.h.

## ◆ SPPR

__IOM uint32_t TPI_Type::SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

Definition at line 1394 of file core_armv81mml.h.

## ◆ SPSEL [1/4]

uint32_t { ... } ::SPSEL

bit: 1 Stack to be used

Definition at line 389 of file core_cm7.h.

## ◆ SPSEL [2/4]

uint32_t { ... } ::SPSEL

bit: 1 Stack-pointer select

Definition at line 425 of file core_armv8mml.h.

## ◆ SPSEL [3/4]

uint32_t { ... } ::SPSEL

bit: 1 Stack-pointer select

Definition at line 427 of file core_armv81mml.h.

## ◆ SPSEL [4/4]

uint32_t CONTROL_Type::SPSEL

bit: 1 Stack-pointer select

bit: 1 Stack to be used

Definition at line 427 of file core_armv81mml.h.

## ◆ SSPSR

__IM uint32_t TPI_Type::SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

Definition at line 1389 of file core_armv81mml.h.

## ◆ STIR [1/2]

__OM uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

Definition at line 477 of file core_armv81mml.h.

## ◆ STIR [2/2]

__OM uint32_t SCB_Type::STIR

Offset: 0x200 ( /W) Software Triggered Interrupt Register

Definition at line 525 of file core_armv81mml.h.

## ◆ T [1/4]

uint32_t { ... } ::T

bit: 24 Thumb bit

Definition at line 338 of file core_cm7.h.

## ◆ T [2/4]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 377 of file core_armv8mml.h.

## ◆ T [3/4]

uint32_t xPSR_Type::T

bit: 24 Thumb bit (read 0)

bit: 24 Thumb bit

Definition at line 379 of file core_armv81mml.h.

## ◆ T [4/4]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 379 of file core_armv81mml.h.

## ◆ TCR

__IOM uint32_t ITM_Type::TCR

Offset: 0xE80 (R/W) ITM Trace Control Register

Definition at line 1099 of file core_armv81mml.h.

## ◆ TER

__IOM uint32_t ITM_Type::TER

Offset: 0xE00 (R/W) ITM Trace Enable Register

Definition at line 1095 of file core_armv81mml.h.

## ◆ TPR

__IOM uint32_t ITM_Type::TPR

Offset: 0xE40 (R/W) ITM Trace Privilege Register

Definition at line 1097 of file core_armv81mml.h.

## ◆ TRIGGER

__IM uint32_t TPI_Type::TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER Register

Definition at line 1400 of file core_armv81mml.h.

## ◆ u16 [1/4]

__OM { ... } ::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

Definition at line 1009 of file core_armv8mml.h.

## ◆ u16 [2/4]

__OM { ... } ::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

Definition at line 1034 of file core_cm7.h.

## ◆ u16 [3/4]

__OM { ... } ::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

Definition at line 1091 of file core_armv81mml.h.

## ◆ u16 [4/4]

__OM uint16_t ITM_Type::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

Definition at line 1091 of file core_armv81mml.h.

## ◆ u32 [1/4]

__OM { ... } ::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

Definition at line 1010 of file core_armv8mml.h.

## ◆ u32 [2/4]

__OM { ... } ::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

Definition at line 1035 of file core_cm7.h.

## ◆ u32 [3/4]

__OM uint32_t ITM_Type::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

Definition at line 1092 of file core_armv81mml.h.

## ◆ u32 [4/4]

__OM { ... } ::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

Definition at line 1092 of file core_armv81mml.h.

## ◆ u8 [1/4]

__OM { ... } ::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

Definition at line 1008 of file core_armv8mml.h.

## ◆ u8 [2/4]

__OM { ... } ::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

Definition at line 1033 of file core_cm7.h.

## ◆ u8 [3/4]

__OM uint8_t ITM_Type::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

Definition at line 1090 of file core_armv81mml.h.

## ◆ u8 [4/4]

__OM { ... } ::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

Definition at line 1090 of file core_armv81mml.h.

## ◆ V [1/8]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 280 of file core_cm7.h.

## ◆ V [2/8]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 320 of file core_armv8mml.h.

## ◆ V [3/8]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 322 of file core_armv81mml.h.

## ◆ V [4/8]

uint32_t APSR_Type::V

bit: 28 Overflow condition code flag

Definition at line 322 of file core_armv81mml.h.

## ◆ V [5/8]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 341 of file core_cm7.h.

## ◆ V [6/8]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 380 of file core_armv8mml.h.

## ◆ V [7/8]

uint32_t xPSR_Type::V

bit: 28 Overflow condition code flag

Definition at line 382 of file core_armv81mml.h.

## ◆ V [8/8]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 382 of file core_armv81mml.h.

## ◆ VAL

__IOM uint32_t SysTick_Type::VAL

Offset: 0x008 (R/W) SysTick Current Value Register

Definition at line 1038 of file core_armv81mml.h.

## ◆ VTOR

__IOM uint32_t SCB_Type::VTOR

Offset: 0x008 (R/W) Vector Table Offset Register

Definition at line 501 of file core_armv81mml.h.

## ◆ w [1/4]

uint32_t APSR_Type::w

Type used for word access

Definition at line 327 of file core_armv81mml.h.

## ◆ w [2/4]

uint32_t IPSR_Type::w

Type used for word access

Definition at line 360 of file core_armv81mml.h.

## ◆ w [3/4]

uint32_t xPSR_Type::w

Type used for word access

Definition at line 387 of file core_armv81mml.h.

## ◆ w [4/4]

uint32_t CONTROL_Type::w

Type used for word access

Definition at line 432 of file core_armv81mml.h.

Referenced by TestUnprivileged().

## ◆ Z [1/8]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 282 of file core_cm7.h.

## ◆ Z [2/8]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 322 of file core_armv8mml.h.

## ◆ Z [3/8]

uint32_t APSR_Type::Z

bit: 30 Zero condition code flag

Definition at line 324 of file core_armv81mml.h.

## ◆ Z [4/8]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 324 of file core_armv81mml.h.

## ◆ Z [5/8]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 343 of file core_cm7.h.

## ◆ Z [6/8]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 382 of file core_armv8mml.h.

## ◆ Z [7/8]

uint32_t xPSR_Type::Z

bit: 30 Zero condition code flag

Definition at line 384 of file core_armv81mml.h.

## ◆ Z [8/8]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 384 of file core_armv81mml.h.