Callisto4Bootloader: TMR Register Masks

Callisto4Bootloader

Macros
TMR Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » TMR Peripheral Access Layer

## Macros

#define | TMR_COMP1_COUNT (4U)
#define | TMR_COMP2_COUNT (4U)
#define | TMR_CAPT_COUNT (4U)
#define | TMR_LOAD_COUNT (4U)
#define | TMR_HOLD_COUNT (4U)
#define | TMR_CNTR_COUNT (4U)
#define | TMR_CTRL_COUNT (4U)
#define | TMR_SCTRL_COUNT (4U)
#define | TMR_CMPLD1_COUNT (4U)
#define | TMR_CMPLD2_COUNT (4U)
#define | TMR_CSCTRL_COUNT (4U)
#define | TMR_FILT_COUNT (4U)
#define | TMR_DMA_COUNT (4U)
#define | TMR_ENBL_COUNT (4U)

## COMP1 - Timer Channel Compare Register 1

#define | TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
#define | TMR_COMP1_COMPARISON_1_SHIFT (0U)
#define | TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)

## COMP2 - Timer Channel Compare Register 2

#define | TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
#define | TMR_COMP2_COMPARISON_2_SHIFT (0U)
#define | TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)

## CAPT - Timer Channel Capture Register

#define | TMR_CAPT_CAPTURE_MASK (0xFFFFU)
#define | TMR_CAPT_CAPTURE_SHIFT (0U)
#define | TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)

## LOAD - Timer Channel Load Register

#define | TMR_LOAD_LOAD_MASK (0xFFFFU)
#define | TMR_LOAD_LOAD_SHIFT (0U)
#define | TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)

## HOLD - Timer Channel Hold Register

#define | TMR_HOLD_HOLD_MASK (0xFFFFU)
#define | TMR_HOLD_HOLD_SHIFT (0U)
#define | TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)

## CNTR - Timer Channel Counter Register

#define | TMR_CNTR_COUNTER_MASK (0xFFFFU)
#define | TMR_CNTR_COUNTER_SHIFT (0U)
#define | TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)

## CTRL - Timer Channel Control Register

#define | TMR_CTRL_OUTMODE_MASK (0x7U)
#define | TMR_CTRL_OUTMODE_SHIFT (0U)
#define | TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
#define | TMR_CTRL_COINIT_MASK (0x8U)
#define | TMR_CTRL_COINIT_SHIFT (3U)
#define | TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
#define | TMR_CTRL_DIR_MASK (0x10U)
#define | TMR_CTRL_DIR_SHIFT (4U)
#define | TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
#define | TMR_CTRL_LENGTH_MASK (0x20U)
#define | TMR_CTRL_LENGTH_SHIFT (5U)
#define | TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
#define | TMR_CTRL_ONCE_MASK (0x40U)
#define | TMR_CTRL_ONCE_SHIFT (6U)
#define | TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
#define | TMR_CTRL_SCS_MASK (0x180U)
#define | TMR_CTRL_SCS_SHIFT (7U)
#define | TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
#define | TMR_CTRL_PCS_MASK (0x1E00U)
#define | TMR_CTRL_PCS_SHIFT (9U)
#define | TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
#define | TMR_CTRL_CM_MASK (0xE000U)
#define | TMR_CTRL_CM_SHIFT (13U)
#define | TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)

## SCTRL - Timer Channel Status and Control Register

#define | TMR_SCTRL_OEN_MASK (0x1U)
#define | TMR_SCTRL_OEN_SHIFT (0U)
#define | TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
#define | TMR_SCTRL_OPS_MASK (0x2U)
#define | TMR_SCTRL_OPS_SHIFT (1U)
#define | TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
#define | TMR_SCTRL_FORCE_MASK (0x4U)
#define | TMR_SCTRL_FORCE_SHIFT (2U)
#define | TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
#define | TMR_SCTRL_VAL_MASK (0x8U)
#define | TMR_SCTRL_VAL_SHIFT (3U)
#define | TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
#define | TMR_SCTRL_EEOF_MASK (0x10U)
#define | TMR_SCTRL_EEOF_SHIFT (4U)
#define | TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
#define | TMR_SCTRL_MSTR_MASK (0x20U)
#define | TMR_SCTRL_MSTR_SHIFT (5U)
#define | TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
#define | TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
#define | TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
#define | TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
#define | TMR_SCTRL_INPUT_MASK (0x100U)
#define | TMR_SCTRL_INPUT_SHIFT (8U)
#define | TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
#define | TMR_SCTRL_IPS_MASK (0x200U)
#define | TMR_SCTRL_IPS_SHIFT (9U)
#define | TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
#define | TMR_SCTRL_IEFIE_MASK (0x400U)
#define | TMR_SCTRL_IEFIE_SHIFT (10U)
#define | TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
#define | TMR_SCTRL_IEF_MASK (0x800U)
#define | TMR_SCTRL_IEF_SHIFT (11U)
#define | TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
#define | TMR_SCTRL_TOFIE_MASK (0x1000U)
#define | TMR_SCTRL_TOFIE_SHIFT (12U)
#define | TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
#define | TMR_SCTRL_TOF_MASK (0x2000U)
#define | TMR_SCTRL_TOF_SHIFT (13U)
#define | TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
#define | TMR_SCTRL_TCFIE_MASK (0x4000U)
#define | TMR_SCTRL_TCFIE_SHIFT (14U)
#define | TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
#define | TMR_SCTRL_TCF_MASK (0x8000U)
#define | TMR_SCTRL_TCF_SHIFT (15U)
#define | TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)

## CMPLD1 - Timer Channel Comparator Load Register 1

#define | TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
#define | TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
#define | TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)

## CMPLD2 - Timer Channel Comparator Load Register 2

#define | TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
#define | TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
#define | TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)

## CSCTRL - Timer Channel Comparator Status and Control Register

#define | TMR_CSCTRL_CL1_MASK (0x3U)
#define | TMR_CSCTRL_CL1_SHIFT (0U)
#define | TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
#define | TMR_CSCTRL_CL2_MASK (0xCU)
#define | TMR_CSCTRL_CL2_SHIFT (2U)
#define | TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
#define | TMR_CSCTRL_TCF1_MASK (0x10U)
#define | TMR_CSCTRL_TCF1_SHIFT (4U)
#define | TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
#define | TMR_CSCTRL_TCF2_MASK (0x20U)
#define | TMR_CSCTRL_TCF2_SHIFT (5U)
#define | TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
#define | TMR_CSCTRL_TCF1EN_MASK (0x40U)
#define | TMR_CSCTRL_TCF1EN_SHIFT (6U)
#define | TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
#define | TMR_CSCTRL_TCF2EN_MASK (0x80U)
#define | TMR_CSCTRL_TCF2EN_SHIFT (7U)
#define | TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
#define | TMR_CSCTRL_UP_MASK (0x200U)
#define | TMR_CSCTRL_UP_SHIFT (9U)
#define | TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
#define | TMR_CSCTRL_TCI_MASK (0x400U)
#define | TMR_CSCTRL_TCI_SHIFT (10U)
#define | TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
#define | TMR_CSCTRL_ROC_MASK (0x800U)
#define | TMR_CSCTRL_ROC_SHIFT (11U)
#define | TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
#define | TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
#define | TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
#define | TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
#define | TMR_CSCTRL_FAULT_MASK (0x2000U)
#define | TMR_CSCTRL_FAULT_SHIFT (13U)
#define | TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
#define | TMR_CSCTRL_DBG_EN_MASK (0xC000U)
#define | TMR_CSCTRL_DBG_EN_SHIFT (14U)
#define | TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)

## FILT - Timer Channel Input Filter Register

#define | TMR_FILT_FILT_PER_MASK (0xFFU)
#define | TMR_FILT_FILT_PER_SHIFT (0U)
#define | TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
#define | TMR_FILT_FILT_CNT_MASK (0x700U)
#define | TMR_FILT_FILT_CNT_SHIFT (8U)
#define | TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)

## DMA - Timer Channel DMA Enable Register

#define | TMR_DMA_IEFDE_MASK (0x1U)
#define | TMR_DMA_IEFDE_SHIFT (0U)
#define | TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
#define | TMR_DMA_CMPLD1DE_MASK (0x2U)
#define | TMR_DMA_CMPLD1DE_SHIFT (1U)
#define | TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
#define | TMR_DMA_CMPLD2DE_MASK (0x4U)
#define | TMR_DMA_CMPLD2DE_SHIFT (2U)
#define | TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)

## ENBL - Timer Channel Enable Register

#define | TMR_ENBL_ENBL_MASK (0xFU)
#define | TMR_ENBL_ENBL_SHIFT (0U)
#define | TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ TMR_CAPT_CAPTURE

#define TMR_CAPT_CAPTURE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)

CAPTURE - Capture Value

Definition at line 39822 of file MIMXRT1062.h.

## ◆ TMR_CAPT_CAPTURE_MASK

#define TMR_CAPT_CAPTURE_MASK (0xFFFFU)

Definition at line 39818 of file MIMXRT1062.h.

## ◆ TMR_CAPT_CAPTURE_SHIFT

#define TMR_CAPT_CAPTURE_SHIFT (0U)

Definition at line 39819 of file MIMXRT1062.h.

## ◆ TMR_CAPT_COUNT

#define TMR_CAPT_COUNT (4U)

Definition at line 39826 of file MIMXRT1062.h.

## ◆ TMR_CMPLD1_COMPARATOR_LOAD_1

#define TMR_CMPLD1_COMPARATOR_LOAD_1 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)

Definition at line 40056 of file MIMXRT1062.h.

## ◆ TMR_CMPLD1_COMPARATOR_LOAD_1_MASK

#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)

Definition at line 40054 of file MIMXRT1062.h.

## ◆ TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT

#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)

Definition at line 40055 of file MIMXRT1062.h.

## ◆ TMR_CMPLD1_COUNT

#define TMR_CMPLD1_COUNT (4U)

Definition at line 40060 of file MIMXRT1062.h.

## ◆ TMR_CMPLD2_COMPARATOR_LOAD_2

#define TMR_CMPLD2_COMPARATOR_LOAD_2 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)

Definition at line 40066 of file MIMXRT1062.h.

## ◆ TMR_CMPLD2_COMPARATOR_LOAD_2_MASK

#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)

Definition at line 40064 of file MIMXRT1062.h.

## ◆ TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT

#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)

Definition at line 40065 of file MIMXRT1062.h.

## ◆ TMR_CMPLD2_COUNT

#define TMR_CMPLD2_COUNT (4U)

Definition at line 40070 of file MIMXRT1062.h.

## ◆ TMR_CNTR_COUNT

#define TMR_CNTR_COUNT (4U)

Definition at line 39858 of file MIMXRT1062.h.

## ◆ TMR_CNTR_COUNTER

#define TMR_CNTR_COUNTER | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)

Definition at line 39854 of file MIMXRT1062.h.

## ◆ TMR_CNTR_COUNTER_MASK

#define TMR_CNTR_COUNTER_MASK (0xFFFFU)

Definition at line 39852 of file MIMXRT1062.h.

## ◆ TMR_CNTR_COUNTER_SHIFT

#define TMR_CNTR_COUNTER_SHIFT (0U)

Definition at line 39853 of file MIMXRT1062.h.

## ◆ TMR_COMP1_COMPARISON_1

#define TMR_COMP1_COMPARISON_1 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)

COMPARISON_1 - Comparison Value 1

Definition at line 39798 of file MIMXRT1062.h.

## ◆ TMR_COMP1_COMPARISON_1_MASK

#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)

Definition at line 39794 of file MIMXRT1062.h.

## ◆ TMR_COMP1_COMPARISON_1_SHIFT

#define TMR_COMP1_COMPARISON_1_SHIFT (0U)

Definition at line 39795 of file MIMXRT1062.h.

## ◆ TMR_COMP1_COUNT

#define TMR_COMP1_COUNT (4U)

Definition at line 39802 of file MIMXRT1062.h.

## ◆ TMR_COMP2_COMPARISON_2

#define TMR_COMP2_COMPARISON_2 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)

COMPARISON_2 - Comparison Value 2

Definition at line 39810 of file MIMXRT1062.h.

## ◆ TMR_COMP2_COMPARISON_2_MASK

#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)

Definition at line 39806 of file MIMXRT1062.h.

## ◆ TMR_COMP2_COMPARISON_2_SHIFT

#define TMR_COMP2_COMPARISON_2_SHIFT (0U)

Definition at line 39807 of file MIMXRT1062.h.

## ◆ TMR_COMP2_COUNT

#define TMR_COMP2_COUNT (4U)

Definition at line 39814 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_ALT_LOAD

#define TMR_CSCTRL_ALT_LOAD | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)

ALT_LOAD - Alternative Load Enable 0b0..Counter can be re-initialized only with the LOAD register. 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.

Definition at line 40139 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_ALT_LOAD_MASK

#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)

Definition at line 40133 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_ALT_LOAD_SHIFT

#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)

Definition at line 40134 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_CL1

#define TMR_CSCTRL_CL1 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)

CL1 - Compare Load Control 1 0b00..Never preload 0b01..Load upon successful compare with the value in COMP1 0b10..Load upon successful compare with the value in COMP2 0b11..Reserved

Definition at line 40082 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_CL1_MASK

#define TMR_CSCTRL_CL1_MASK (0x3U)

Definition at line 40074 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_CL1_SHIFT

#define TMR_CSCTRL_CL1_SHIFT (0U)

Definition at line 40075 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_CL2

#define TMR_CSCTRL_CL2 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)

CL2 - Compare Load Control 2 0b00..Never preload 0b01..Load upon successful compare with the value in COMP1 0b10..Load upon successful compare with the value in COMP2 0b11..Reserved

Definition at line 40091 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_CL2_MASK

#define TMR_CSCTRL_CL2_MASK (0xCU)

Definition at line 40083 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_CL2_SHIFT

#define TMR_CSCTRL_CL2_SHIFT (2U)

Definition at line 40084 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_COUNT

#define TMR_CSCTRL_COUNT (4U)

Definition at line 40159 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_DBG_EN

#define TMR_CSCTRL_DBG_EN | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)

DBG_EN - Debug Actions Enable 0b00..Continue with normal operation during debug mode. (default) 0b01..Halt TMR counter during debug mode. 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 0b11..Both halt counter and force output to 0 during debug mode.

Definition at line 40155 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_DBG_EN_MASK

#define TMR_CSCTRL_DBG_EN_MASK (0xC000U)

Definition at line 40147 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_DBG_EN_SHIFT

#define TMR_CSCTRL_DBG_EN_SHIFT (14U)

Definition at line 40148 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_FAULT

#define TMR_CSCTRL_FAULT | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)

FAULT - Fault Enable 0b0..Fault function disabled. 0b1..Fault function enabled.

Definition at line 40146 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_FAULT_MASK

#define TMR_CSCTRL_FAULT_MASK (0x2000U)

Definition at line 40140 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_FAULT_SHIFT

#define TMR_CSCTRL_FAULT_SHIFT (13U)

Definition at line 40141 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_ROC

#define TMR_CSCTRL_ROC | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)

ROC - Reload on Capture 0b0..Do not reload the counter on a capture event. 0b1..Reload the counter on a capture event.

Definition at line 40132 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_ROC_MASK

#define TMR_CSCTRL_ROC_MASK (0x800U)

Definition at line 40126 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_ROC_SHIFT

#define TMR_CSCTRL_ROC_SHIFT (11U)

Definition at line 40127 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF1

#define TMR_CSCTRL_TCF1 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)

TCF1 - Timer Compare 1 Interrupt Flag

Definition at line 40096 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF1_MASK

#define TMR_CSCTRL_TCF1_MASK (0x10U)

Definition at line 40092 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF1_SHIFT

#define TMR_CSCTRL_TCF1_SHIFT (4U)

Definition at line 40093 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF1EN

#define TMR_CSCTRL_TCF1EN | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)

TCF1EN - Timer Compare 1 Interrupt Enable

Definition at line 40106 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF1EN_MASK

#define TMR_CSCTRL_TCF1EN_MASK (0x40U)

Definition at line 40102 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF1EN_SHIFT

#define TMR_CSCTRL_TCF1EN_SHIFT (6U)

Definition at line 40103 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF2

#define TMR_CSCTRL_TCF2 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)

TCF2 - Timer Compare 2 Interrupt Flag

Definition at line 40101 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF2_MASK

#define TMR_CSCTRL_TCF2_MASK (0x20U)

Definition at line 40097 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF2_SHIFT

#define TMR_CSCTRL_TCF2_SHIFT (5U)

Definition at line 40098 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF2EN

#define TMR_CSCTRL_TCF2EN | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)

TCF2EN - Timer Compare 2 Interrupt Enable

Definition at line 40111 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF2EN_MASK

#define TMR_CSCTRL_TCF2EN_MASK (0x80U)

Definition at line 40107 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCF2EN_SHIFT

#define TMR_CSCTRL_TCF2EN_SHIFT (7U)

Definition at line 40108 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCI

#define TMR_CSCTRL_TCI | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)

TCI - Triggered Count Initialization Control 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.

Definition at line 40125 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCI_MASK

#define TMR_CSCTRL_TCI_MASK (0x400U)

Definition at line 40119 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_TCI_SHIFT

#define TMR_CSCTRL_TCI_SHIFT (10U)

Definition at line 40120 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_UP

#define TMR_CSCTRL_UP | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)

UP - Counting Direction Indicator 0b0..The last count was in the DOWN direction. 0b1..The last count was in the UP direction.

Definition at line 40118 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_UP_MASK

#define TMR_CSCTRL_UP_MASK (0x200U)

Definition at line 40112 of file MIMXRT1062.h.

## ◆ TMR_CSCTRL_UP_SHIFT

#define TMR_CSCTRL_UP_SHIFT (9U)

Definition at line 40113 of file MIMXRT1062.h.

## ◆ TMR_CTRL_CM

#define TMR_CTRL_CM | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)

CM - Count Mode 0b000..No operation 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 0b011..Count rising edges of primary source while secondary input high active 0b100..Quadrature count mode, uses primary and secondary sources 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 0b110..Edge of secondary source triggers primary count until compare 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.

Definition at line 39955 of file MIMXRT1062.h.

## ◆ TMR_CTRL_CM_MASK

#define TMR_CTRL_CM_MASK (0xE000U)

Definition at line 39940 of file MIMXRT1062.h.

## ◆ TMR_CTRL_CM_SHIFT

#define TMR_CTRL_CM_SHIFT (13U)

Definition at line 39941 of file MIMXRT1062.h.

## ◆ TMR_CTRL_COINIT

#define TMR_CTRL_COINIT | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)

COINIT - Co-Channel Initialization 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer

Definition at line 39881 of file MIMXRT1062.h.

## ◆ TMR_CTRL_COINIT_MASK

#define TMR_CTRL_COINIT_MASK (0x8U)

Definition at line 39875 of file MIMXRT1062.h.

## ◆ TMR_CTRL_COINIT_SHIFT

#define TMR_CTRL_COINIT_SHIFT (3U)

Definition at line 39876 of file MIMXRT1062.h.

## ◆ TMR_CTRL_COUNT

#define TMR_CTRL_COUNT (4U)

Definition at line 39959 of file MIMXRT1062.h.

## ◆ TMR_CTRL_DIR

#define TMR_CTRL_DIR | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)

DIR - Count Direction 0b0..Count up. 0b1..Count down.

Definition at line 39888 of file MIMXRT1062.h.

## ◆ TMR_CTRL_DIR_MASK

#define TMR_CTRL_DIR_MASK (0x10U)

Definition at line 39882 of file MIMXRT1062.h.

## ◆ TMR_CTRL_DIR_SHIFT

#define TMR_CTRL_DIR_SHIFT (4U)

Definition at line 39883 of file MIMXRT1062.h.

## ◆ TMR_CTRL_LENGTH

#define TMR_CTRL_LENGTH | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)

LENGTH - Count Length 0b0..Count until roll over at $FFFF and continue from $0000. 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.

Definition at line 39899 of file MIMXRT1062.h.

## ◆ TMR_CTRL_LENGTH_MASK

#define TMR_CTRL_LENGTH_MASK (0x20U)

Definition at line 39889 of file MIMXRT1062.h.

## ◆ TMR_CTRL_LENGTH_SHIFT

#define TMR_CTRL_LENGTH_SHIFT (5U)

Definition at line 39890 of file MIMXRT1062.h.

## ◆ TMR_CTRL_ONCE

#define TMR_CTRL_ONCE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)

ONCE - Count Once 0b0..Count repeatedly. 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.

Definition at line 39909 of file MIMXRT1062.h.

## ◆ TMR_CTRL_ONCE_MASK

#define TMR_CTRL_ONCE_MASK (0x40U)

Definition at line 39900 of file MIMXRT1062.h.

## ◆ TMR_CTRL_ONCE_SHIFT

#define TMR_CTRL_ONCE_SHIFT (6U)

Definition at line 39901 of file MIMXRT1062.h.

## ◆ TMR_CTRL_OUTMODE

#define TMR_CTRL_OUTMODE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)

OUTMODE - Output Mode 0b000..Asserted while counter is active 0b001..Clear OFLAG output on successful compare 0b010..Set OFLAG output on successful compare 0b011..Toggle OFLAG output on successful compare 0b100..Toggle OFLAG output using alternating compare registers 0b101..Set on compare, cleared on secondary source input edge 0b110..Set on compare, cleared on counter rollover 0b111..Enable gated clock output while counter is active

Definition at line 39874 of file MIMXRT1062.h.

## ◆ TMR_CTRL_OUTMODE_MASK

#define TMR_CTRL_OUTMODE_MASK (0x7U)

Definition at line 39862 of file MIMXRT1062.h.

## ◆ TMR_CTRL_OUTMODE_SHIFT

#define TMR_CTRL_OUTMODE_SHIFT (0U)

Definition at line 39863 of file MIMXRT1062.h.

## ◆ TMR_CTRL_PCS

#define TMR_CTRL_PCS | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)

PCS - Primary Count Source 0b0000..Counter 0 input pin 0b0001..Counter 1 input pin 0b0010..Counter 2 input pin 0b0011..Counter 3 input pin 0b0100..Counter 0 output 0b0101..Counter 1 output 0b0110..Counter 2 output 0b0111..Counter 3 output 0b1000..IP bus clock divide by 1 prescaler 0b1001..IP bus clock divide by 2 prescaler 0b1010..IP bus clock divide by 4 prescaler 0b1011..IP bus clock divide by 8 prescaler 0b1100..IP bus clock divide by 16 prescaler 0b1101..IP bus clock divide by 32 prescaler 0b1110..IP bus clock divide by 64 prescaler 0b1111..IP bus clock divide by 128 prescaler

Definition at line 39939 of file MIMXRT1062.h.

## ◆ TMR_CTRL_PCS_MASK

#define TMR_CTRL_PCS_MASK (0x1E00U)

Definition at line 39919 of file MIMXRT1062.h.

## ◆ TMR_CTRL_PCS_SHIFT

#define TMR_CTRL_PCS_SHIFT (9U)

Definition at line 39920 of file MIMXRT1062.h.

## ◆ TMR_CTRL_SCS

#define TMR_CTRL_SCS | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)

SCS - Secondary Count Source 0b00..Counter 0 input pin 0b01..Counter 1 input pin 0b10..Counter 2 input pin 0b11..Counter 3 input pin

Definition at line 39918 of file MIMXRT1062.h.

## ◆ TMR_CTRL_SCS_MASK

#define TMR_CTRL_SCS_MASK (0x180U)

Definition at line 39910 of file MIMXRT1062.h.

## ◆ TMR_CTRL_SCS_SHIFT

#define TMR_CTRL_SCS_SHIFT (7U)

Definition at line 39911 of file MIMXRT1062.h.

## ◆ TMR_DMA_CMPLD1DE

#define TMR_DMA_CMPLD1DE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)

CMPLD1DE - Comparator Preload Register 1 DMA Enable

Definition at line 40189 of file MIMXRT1062.h.

## ◆ TMR_DMA_CMPLD1DE_MASK

#define TMR_DMA_CMPLD1DE_MASK (0x2U)

Definition at line 40185 of file MIMXRT1062.h.

## ◆ TMR_DMA_CMPLD1DE_SHIFT

#define TMR_DMA_CMPLD1DE_SHIFT (1U)

Definition at line 40186 of file MIMXRT1062.h.

## ◆ TMR_DMA_CMPLD2DE

#define TMR_DMA_CMPLD2DE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)

CMPLD2DE - Comparator Preload Register 2 DMA Enable

Definition at line 40194 of file MIMXRT1062.h.

## ◆ TMR_DMA_CMPLD2DE_MASK

#define TMR_DMA_CMPLD2DE_MASK (0x4U)

Definition at line 40190 of file MIMXRT1062.h.

## ◆ TMR_DMA_CMPLD2DE_SHIFT

#define TMR_DMA_CMPLD2DE_SHIFT (2U)

Definition at line 40191 of file MIMXRT1062.h.

## ◆ TMR_DMA_COUNT

#define TMR_DMA_COUNT (4U)

Definition at line 40198 of file MIMXRT1062.h.

## ◆ TMR_DMA_IEFDE

#define TMR_DMA_IEFDE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)

IEFDE - Input Edge Flag DMA Enable

Definition at line 40184 of file MIMXRT1062.h.

## ◆ TMR_DMA_IEFDE_MASK

#define TMR_DMA_IEFDE_MASK (0x1U)

Definition at line 40180 of file MIMXRT1062.h.

## ◆ TMR_DMA_IEFDE_SHIFT

#define TMR_DMA_IEFDE_SHIFT (0U)

Definition at line 40181 of file MIMXRT1062.h.

## ◆ TMR_ENBL_COUNT

#define TMR_ENBL_COUNT (4U)

Definition at line 40212 of file MIMXRT1062.h.

## ◆ TMR_ENBL_ENBL

#define TMR_ENBL_ENBL | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)

ENBL - Timer Channel Enable 0b0000..Timer channel is disabled. 0b0001..Timer channel is enabled. (default)

Definition at line 40208 of file MIMXRT1062.h.

## ◆ TMR_ENBL_ENBL_MASK

#define TMR_ENBL_ENBL_MASK (0xFU)

Definition at line 40202 of file MIMXRT1062.h.

## ◆ TMR_ENBL_ENBL_SHIFT

#define TMR_ENBL_ENBL_SHIFT (0U)

Definition at line 40203 of file MIMXRT1062.h.

## ◆ TMR_FILT_COUNT

#define TMR_FILT_COUNT (4U)

Definition at line 40176 of file MIMXRT1062.h.

## ◆ TMR_FILT_FILT_CNT

#define TMR_FILT_FILT_CNT | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)

FILT_CNT - Input Filter Sample Count

Definition at line 40172 of file MIMXRT1062.h.

## ◆ TMR_FILT_FILT_CNT_MASK

#define TMR_FILT_FILT_CNT_MASK (0x700U)

Definition at line 40168 of file MIMXRT1062.h.

## ◆ TMR_FILT_FILT_CNT_SHIFT

#define TMR_FILT_FILT_CNT_SHIFT (8U)

Definition at line 40169 of file MIMXRT1062.h.

## ◆ TMR_FILT_FILT_PER

#define TMR_FILT_FILT_PER | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)

FILT_PER - Input Filter Sample Period

Definition at line 40167 of file MIMXRT1062.h.

## ◆ TMR_FILT_FILT_PER_MASK

#define TMR_FILT_FILT_PER_MASK (0xFFU)

Definition at line 40163 of file MIMXRT1062.h.

## ◆ TMR_FILT_FILT_PER_SHIFT

#define TMR_FILT_FILT_PER_SHIFT (0U)

Definition at line 40164 of file MIMXRT1062.h.

## ◆ TMR_HOLD_COUNT

#define TMR_HOLD_COUNT (4U)

Definition at line 39848 of file MIMXRT1062.h.

## ◆ TMR_HOLD_HOLD

#define TMR_HOLD_HOLD | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)

Definition at line 39844 of file MIMXRT1062.h.

## ◆ TMR_HOLD_HOLD_MASK

#define TMR_HOLD_HOLD_MASK (0xFFFFU)

Definition at line 39842 of file MIMXRT1062.h.

## ◆ TMR_HOLD_HOLD_SHIFT

#define TMR_HOLD_HOLD_SHIFT (0U)

Definition at line 39843 of file MIMXRT1062.h.

## ◆ TMR_LOAD_COUNT

#define TMR_LOAD_COUNT (4U)

Definition at line 39838 of file MIMXRT1062.h.

## ◆ TMR_LOAD_LOAD

#define TMR_LOAD_LOAD | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)

LOAD - Timer Load Register

Definition at line 39834 of file MIMXRT1062.h.

## ◆ TMR_LOAD_LOAD_MASK

#define TMR_LOAD_LOAD_MASK (0xFFFFU)

Definition at line 39830 of file MIMXRT1062.h.

## ◆ TMR_LOAD_LOAD_SHIFT

#define TMR_LOAD_LOAD_SHIFT (0U)

Definition at line 39831 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_CAPTURE_MODE

#define TMR_SCTRL_CAPTURE_MODE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)

CAPTURE_MODE - Input Capture Mode 0b00..Capture function is disabled 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 0b11..Load capture register on both edges of input

Definition at line 40006 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_CAPTURE_MODE_MASK

#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)

Definition at line 39998 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_CAPTURE_MODE_SHIFT

#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)

Definition at line 39999 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_COUNT

#define TMR_SCTRL_COUNT (4U)

Definition at line 40050 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_EEOF

#define TMR_SCTRL_EEOF | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)

EEOF - Enable External OFLAG Force

Definition at line 39992 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_EEOF_MASK

#define TMR_SCTRL_EEOF_MASK (0x10U)

Definition at line 39988 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_EEOF_SHIFT

#define TMR_SCTRL_EEOF_SHIFT (4U)

Definition at line 39989 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_FORCE

#define TMR_SCTRL_FORCE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)

FORCE - Force OFLAG Output

Definition at line 39982 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_FORCE_MASK

#define TMR_SCTRL_FORCE_MASK (0x4U)

Definition at line 39978 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_FORCE_SHIFT

#define TMR_SCTRL_FORCE_SHIFT (2U)

Definition at line 39979 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IEF

#define TMR_SCTRL_IEF | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)

IEF - Input Edge Flag

Definition at line 40026 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IEF_MASK

#define TMR_SCTRL_IEF_MASK (0x800U)

Definition at line 40022 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IEF_SHIFT

#define TMR_SCTRL_IEF_SHIFT (11U)

Definition at line 40023 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IEFIE

#define TMR_SCTRL_IEFIE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)

IEFIE - Input Edge Flag Interrupt Enable

Definition at line 40021 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IEFIE_MASK

#define TMR_SCTRL_IEFIE_MASK (0x400U)

Definition at line 40017 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IEFIE_SHIFT

#define TMR_SCTRL_IEFIE_SHIFT (10U)

Definition at line 40018 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_INPUT

#define TMR_SCTRL_INPUT | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)

INPUT - External Input Signal

Definition at line 40011 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_INPUT_MASK

#define TMR_SCTRL_INPUT_MASK (0x100U)

Definition at line 40007 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_INPUT_SHIFT

#define TMR_SCTRL_INPUT_SHIFT (8U)

Definition at line 40008 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IPS

#define TMR_SCTRL_IPS | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)

IPS - Input Polarity Select

Definition at line 40016 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IPS_MASK

#define TMR_SCTRL_IPS_MASK (0x200U)

Definition at line 40012 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_IPS_SHIFT

#define TMR_SCTRL_IPS_SHIFT (9U)

Definition at line 40013 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_MSTR

#define TMR_SCTRL_MSTR | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)

MSTR - Master Mode

Definition at line 39997 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_MSTR_MASK

#define TMR_SCTRL_MSTR_MASK (0x20U)

Definition at line 39993 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_MSTR_SHIFT

#define TMR_SCTRL_MSTR_SHIFT (5U)

Definition at line 39994 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_OEN

#define TMR_SCTRL_OEN | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)

OEN - Output Enable 0b0..The external pin is configured as an input. 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.

Definition at line 39970 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_OEN_MASK

#define TMR_SCTRL_OEN_MASK (0x1U)

Definition at line 39963 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_OEN_SHIFT

#define TMR_SCTRL_OEN_SHIFT (0U)

Definition at line 39964 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_OPS

#define TMR_SCTRL_OPS | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)

OPS - Output Polarity Select 0b0..True polarity. 0b1..Inverted polarity.

Definition at line 39977 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_OPS_MASK

#define TMR_SCTRL_OPS_MASK (0x2U)

Definition at line 39971 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_OPS_SHIFT

#define TMR_SCTRL_OPS_SHIFT (1U)

Definition at line 39972 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TCF

#define TMR_SCTRL_TCF | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)

TCF - Timer Compare Flag

Definition at line 40046 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TCF_MASK

#define TMR_SCTRL_TCF_MASK (0x8000U)

Definition at line 40042 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TCF_SHIFT

#define TMR_SCTRL_TCF_SHIFT (15U)

Definition at line 40043 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TCFIE

#define TMR_SCTRL_TCFIE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)

TCFIE - Timer Compare Flag Interrupt Enable

Definition at line 40041 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TCFIE_MASK

#define TMR_SCTRL_TCFIE_MASK (0x4000U)

Definition at line 40037 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TCFIE_SHIFT

#define TMR_SCTRL_TCFIE_SHIFT (14U)

Definition at line 40038 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TOF

#define TMR_SCTRL_TOF | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)

TOF - Timer Overflow Flag

Definition at line 40036 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TOF_MASK

#define TMR_SCTRL_TOF_MASK (0x2000U)

Definition at line 40032 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TOF_SHIFT

#define TMR_SCTRL_TOF_SHIFT (13U)

Definition at line 40033 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TOFIE

#define TMR_SCTRL_TOFIE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)

TOFIE - Timer Overflow Flag Interrupt Enable

Definition at line 40031 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TOFIE_MASK

#define TMR_SCTRL_TOFIE_MASK (0x1000U)

Definition at line 40027 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_TOFIE_SHIFT

#define TMR_SCTRL_TOFIE_SHIFT (12U)

Definition at line 40028 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_VAL

#define TMR_SCTRL_VAL | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)

VAL - Forced OFLAG Value

Definition at line 39987 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_VAL_MASK

#define TMR_SCTRL_VAL_MASK (0x8U)

Definition at line 39983 of file MIMXRT1062.h.

## ◆ TMR_SCTRL_VAL_SHIFT

#define TMR_SCTRL_VAL_SHIFT (3U)

Definition at line 39984 of file MIMXRT1062.h.