Callisto4Bootloader: CMSIS/cmsis_armcc.h Source File

Callisto4Bootloader

cmsis_armcc.h
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1 /**************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_ARMCC_H
26 #define __CMSIS_ARMCC_H
27
28
29 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
30 #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
31 #endif
32
33 /* CMSIS compiler control architecture macros */
34 #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
35 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
36 #define __ARM_ARCH_6M__ 1
37 #endif
38
39 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
40 #define __ARM_ARCH_7M__ 1
41 #endif
42
43 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
44 #define __ARM_ARCH_7EM__ 1
45 #endif
46
47 /* __ARM_ARCH_8M_BASE__ not applicable */
48 /* __ARM_ARCH_8M_MAIN__ not applicable */
49
50 /* CMSIS compiler control DSP macros */
51 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
52 #define __ARM_FEATURE_DSP 1
53 #endif
54
55 /* CMSIS compiler specific defines */
56 #ifndef __ASM
57 #define __ASM __asm
58 #endif
59 #ifndef __INLINE
60 #define __INLINE __inline
61 #endif
62 #ifndef __STATIC_INLINE
63 #define __STATIC_INLINE static __inline
64 #endif
65 #ifndef __STATIC_FORCEINLINE
66 #define __STATIC_FORCEINLINE static __forceinline
67 #endif
68 #ifndef __NO_RETURN
69 #define __NO_RETURN __declspec(noreturn)
70 #endif
71 #ifndef __USED
72 #define __USED __attribute__((used))
73 #endif
74 #ifndef __WEAK
75 #define __WEAK __attribute__((weak))
76 #endif
77 #ifndef __PACKED
78 #define __PACKED __attribute__((packed))
79 #endif
80 #ifndef __PACKED_STRUCT
81 #define __PACKED_STRUCT __packed struct
82 #endif
83 #ifndef __PACKED_UNION
84 #define __PACKED_UNION __packed union
85 #endif
86 #ifndef __UNALIGNED_UINT32 /* deprecated */
87 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
88 #endif
89 #ifndef __UNALIGNED_UINT16_WRITE
90 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
91 #endif
92 #ifndef __UNALIGNED_UINT16_READ
93 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
94 #endif
95 #ifndef __UNALIGNED_UINT32_WRITE
96 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
97 #endif
98 #ifndef __UNALIGNED_UINT32_READ
99 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
100 #endif
101 #ifndef __ALIGNED
102 #define __ALIGNED(x) __attribute__((aligned(x)))
103 #endif
104 #ifndef __RESTRICT
105 #define __RESTRICT __restrict
106 #endif
107
108 /* ########################### Core Function Access ########################### */
119 /* intrinsic void __enable_irq(); */
120
121
127 /* intrinsic void __disable_irq(); */
128
134 __STATIC_INLINE uint32_t __get_CONTROL(void)
135 {
136 register uint32_t __regControl __ASM("control");
137 return(__regControl);
138 }
139
140
146 __STATIC_INLINE void __set_CONTROL(uint32_t control)
147 {
148 register uint32_t __regControl __ASM("control");
149 __regControl = control;
150 }
151
152
158 __STATIC_INLINE uint32_t __get_IPSR(void)
159 {
160 register uint32_t __regIPSR __ASM("ipsr");
161 return(__regIPSR);
162 }
163
164
170 __STATIC_INLINE uint32_t __get_APSR(void)
171 {
172 register uint32_t __regAPSR __ASM("apsr");
173 return(__regAPSR);
174 }
175
176
182 __STATIC_INLINE uint32_t __get_xPSR(void)
183 {
184 register uint32_t __regXPSR __ASM("xpsr");
185 return(__regXPSR);
186 }
187
188
194 __STATIC_INLINE uint32_t __get_PSP(void)
195 {
196 register uint32_t __regProcessStackPointer __ASM("psp");
197 return(__regProcessStackPointer);
198 }
199
200
206 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
207 {
208 register uint32_t __regProcessStackPointer __ASM("psp");
209 __regProcessStackPointer = topOfProcStack;
210 }
211
212
218 __STATIC_INLINE uint32_t __get_MSP(void)
219 {
220 register uint32_t __regMainStackPointer __ASM("msp");
221 return(__regMainStackPointer);
222 }
223
224
230 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
231 {
232 register uint32_t __regMainStackPointer __ASM("msp");
233 __regMainStackPointer = topOfMainStack;
234 }
235
236
242 __STATIC_INLINE uint32_t __get_PRIMASK(void)
243 {
244 register uint32_t __regPriMask __ASM("primask");
245 return(__regPriMask);
246 }
247
248
254 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
255 {
256 register uint32_t __regPriMask __ASM("primask");
257 __regPriMask = (priMask);
258 }
259
260
261 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
262 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
263
269 #define __enable_fault_irq __enable_fiq
270
271
277 #define __disable_fault_irq __disable_fiq
278
279
285 __STATIC_INLINE uint32_t __get_BASEPRI(void)
286 {
287 register uint32_t __regBasePri __ASM("basepri");
288 return(__regBasePri);
289 }
290
291
297 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
298 {
299 register uint32_t __regBasePri __ASM("basepri");
300 __regBasePri = (basePri & 0xFFU);
301 }
302
303
310 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
311 {
312 register uint32_t __regBasePriMax __ASM("basepri_max");
313 __regBasePriMax = (basePri & 0xFFU);
314 }
315
316
322 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
323 {
324 register uint32_t __regFaultMask __ASM("faultmask");
325 return(__regFaultMask);
326 }
327
328
334 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
335 {
336 register uint32_t __regFaultMask __ASM("faultmask");
337 __regFaultMask = (faultMask & (uint32_t)1U);
338 }
339
340 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
341 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
342
343
349 __STATIC_INLINE uint32_t __get_FPSCR(void)
350 {
351 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
352 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
353 register uint32_t __regfpscr __ASM("fpscr");
354 return(__regfpscr);
355 #else
356 return(0U);
357 #endif
358 }
359
360
366 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
367 {
368 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
369 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
370 register uint32_t __regfpscr __ASM("fpscr");
371 __regfpscr = (fpscr);
372 #else
373 (void)fpscr;
374 #endif
375 }
376
377
381 /* ########################## Core Instruction Access ######################### */
391 #define __NOP __nop
392
393
398 #define __WFI __wfi
399
400
406 #define __WFE __wfe
407
408
413 #define __SEV __sev
414
415
422 #define __ISB() do {\
423 __schedule_barrier();\
424 __isb(0xF);\
425 __schedule_barrier();\
426 } while (0U)
427
433 #define __DSB() do {\
434 __schedule_barrier();\
435 __dsb(0xF);\
436 __schedule_barrier();\
437 } while (0U)
438
444 #define __DMB() do {\
445 __schedule_barrier();\
446 __dmb(0xF);\
447 __schedule_barrier();\
448 } while (0U)
449
450
457 #define __REV __rev
458
459
466 #ifndef __NO_EMBEDDED_ASM
467 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
468 {
469 rev16 r0, r0
470 bx lr
471 }
472 #endif
473
474
481 #ifndef __NO_EMBEDDED_ASM
482 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
483 {
484 revsh r0, r0
485 bx lr
486 }
487 #endif
488
489
497 #define __ROR __ror
498
499
507 #define __BKPT(value) __breakpoint(value)
508
509
516 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
517 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
518 #define __RBIT __rbit
519 #else
520 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
521 {
522 uint32_t result;
523 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
524
525 result = value; /* r will be reversed bits of v; first get LSB of v */
526 for (value >>= 1U; value != 0U; value >>= 1U)
527 {
528 result <<= 1U;
529 result |= value & 1U;
530 s--;
531 }
532 result <<= s; /* shift when v's highest bits are zero */
533 return result;
534 }
535 #endif
536
537
544 #define __CLZ __clz
545
546
547 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
548 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
549
556 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
557 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
558 #else
559 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
560 #endif
561
562
569 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
570 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
571 #else
572 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
573 #endif
574
575
582 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
583 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
584 #else
585 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
586 #endif
587
588
597 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
598 #define __STREXB(value, ptr) __strex(value, ptr)
599 #else
600 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
601 #endif
602
603
612 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
613 #define __STREXH(value, ptr) __strex(value, ptr)
614 #else
615 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
616 #endif
617
618
627 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
628 #define __STREXW(value, ptr) __strex(value, ptr)
629 #else
630 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
631 #endif
632
633
638 #define __CLREX __clrex
639
640
648 #define __SSAT __ssat
649
650
658 #define __USAT __usat
659
660
668 #ifndef __NO_EMBEDDED_ASM
669 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
670 {
671 rrx r0, r0
672 bx lr
673 }
674 #endif
675
676
683 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
684
685
692 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
693
694
701 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
702
703
710 #define __STRBT(value, ptr) __strt(value, ptr)
711
712
719 #define __STRHT(value, ptr) __strt(value, ptr)
720
721
728 #define __STRT(value, ptr) __strt(value, ptr)
729
730 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
731 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
732
740 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
741 {
742 if ((sat >= 1U) && (sat <= 32U))
743 {
744 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
745 const int32_t min = -1 - max ;
746 if (val > max)
747 {
748 return max;
749 }
750 else if (val < min)
751 {
752 return min;
753 }
754 }
755 return val;
756 }
757
765 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
766 {
767 if (sat <= 31U)
768 {
769 const uint32_t max = ((1U << sat) - 1U);
770 if (val > (int32_t)max)
771 {
772 return max;
773 }
774 else if (val < 0)
775 {
776 return 0U;
777 }
778 }
779 return (uint32_t)val;
780 }
781
782 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
783 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
784 /* end of group CMSIS_Core_InstructionInterface */
786
787
788 /* ################### Compiler specific Intrinsics ########################### */
794 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
795
796 #define __SADD8 __sadd8
797 #define __QADD8 __qadd8
798 #define __SHADD8 __shadd8
799 #define __UADD8 __uadd8
800 #define __UQADD8 __uqadd8
801 #define __UHADD8 __uhadd8
802 #define __SSUB8 __ssub8
803 #define __QSUB8 __qsub8
804 #define __SHSUB8 __shsub8
805 #define __USUB8 __usub8
806 #define __UQSUB8 __uqsub8
807 #define __UHSUB8 __uhsub8
808 #define __SADD16 __sadd16
809 #define __QADD16 __qadd16
810 #define __SHADD16 __shadd16
811 #define __UADD16 __uadd16
812 #define __UQADD16 __uqadd16
813 #define __UHADD16 __uhadd16
814 #define __SSUB16 __ssub16
815 #define __QSUB16 __qsub16
816 #define __SHSUB16 __shsub16
817 #define __USUB16 __usub16
818 #define __UQSUB16 __uqsub16
819 #define __UHSUB16 __uhsub16
820 #define __SASX __sasx
821 #define __QASX __qasx
822 #define __SHASX __shasx
823 #define __UASX __uasx
824 #define __UQASX __uqasx
825 #define __UHASX __uhasx
826 #define __SSAX __ssax
827 #define __QSAX __qsax
828 #define __SHSAX __shsax
829 #define __USAX __usax
830 #define __UQSAX __uqsax
831 #define __UHSAX __uhsax
832 #define __USAD8 __usad8
833 #define __USADA8 __usada8
834 #define __SSAT16 __ssat16
835 #define __USAT16 __usat16
836 #define __UXTB16 __uxtb16
837 #define __UXTAB16 __uxtab16
838 #define __SXTB16 __sxtb16
839 #define __SXTAB16 __sxtab16
840 #define __SMUAD __smuad
841 #define __SMUADX __smuadx
842 #define __SMLAD __smlad
843 #define __SMLADX __smladx
844 #define __SMLALD __smlald
845 #define __SMLALDX __smlaldx
846 #define __SMUSD __smusd
847 #define __SMUSDX __smusdx
848 #define __SMLSD __smlsd
849 #define __SMLSDX __smlsdx
850 #define __SMLSLD __smlsld
851 #define __SMLSLDX __smlsldx
852 #define __SEL __sel
853 #define __QADD __qadd
854 #define __QSUB __qsub
855
856 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
857 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
858
859 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
860 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
861
862 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
863 ((int64_t)(ARG3) << 32U) ) >> 32U))
864
865 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
866
869 #endif /* __CMSIS_ARMCC_H */
__set_FPSCR
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Set FPSCR.
Definition: cmsis_armcc.h:366
__ASM
#define __ASM
Definition: cmsis_armcc.h:57
__REVSH
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
Reverse byte order (16 bit)
Definition: cmsis_gcc.h:934
__attribute__
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
Reverse byte order (16 bit)
Definition: cmsis_armcc.h:467
__get_APSR
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition: cmsis_armcc.h:170
__get_CONTROL
__STATIC_INLINE uint32_t __get_CONTROL(void)
Enable IRQ Interrupts.
Definition: cmsis_armcc.h:134
__set_PSP
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
Definition: cmsis_armcc.h:206
__USAT
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition: cmsis_armclang.h:1164
__get_IPSR
__STATIC_INLINE uint32_t __get_IPSR(void)
Get IPSR Register.
Definition: cmsis_armcc.h:158
__set_MSP
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
Definition: cmsis_armcc.h:230
__REV16
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
Reverse byte order (16 bit)
Definition: cmsis_gcc.h:919
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:63
sat
uint32_t sat
Definition: cmsis_armcc.h:741
__SSAT
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition: cmsis_armclang.h:1139
__get_xPSR
__STATIC_INLINE uint32_t __get_xPSR(void)
Get xPSR Register.
Definition: cmsis_armcc.h:182
__get_PRIMASK
__STATIC_INLINE uint32_t __get_PRIMASK(void)
Get Priority Mask.
Definition: cmsis_armcc.h:242
__set_CONTROL
__STATIC_INLINE void __set_CONTROL(uint32_t control)
Set Control Register.
Definition: cmsis_armcc.h:146
__set_PRIMASK
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
Definition: cmsis_armcc.h:254
__RBIT
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
Reverse bit order of value.
Definition: cmsis_gcc.h:981
min
#define min(a, b)
Minimum.
Definition: c4_qspi.h:41
__get_FPSCR
__STATIC_INLINE uint32_t __get_FPSCR(void)
Get FPSCR.
Definition: cmsis_armcc.h:349
__get_MSP
__STATIC_INLINE uint32_t __get_MSP(void)
Get Main Stack Pointer.
Definition: cmsis_armcc.h:218
max
#define max(a, b)
Maximum.
Definition: c4_qspi.h:26
__get_PSP
__STATIC_INLINE uint32_t __get_PSP(void)
Get Process Stack Pointer.
Definition: cmsis_armcc.h:194