Callisto4Bootloader: drivers/fsl_flexspi.h Source File

Callisto4Bootloader

fsl_flexspi.h
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1 /*
2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 *
8 */
9
10 #ifndef __FSL_FLEXSPI_H__
11 #define __FSL_FLEXSPI_H__
12
13 #include "fsl_common.h"
14
15 /**********************************************************************************************************************
16 * Definitions
17 *********************************************************************************************************************/
18 /* The count of FlexSPI_LUT */
19 #define FlexSPI_LUT_COUNT (64)
20 /* The count of FlexSPI AHB Buffer */
21 #define FlexSPI_AHB_RX_BUF_COUNT (4U)
22 /* AHB RX_BUF depth, in longwords */
23 #define FlexSPI_AHB_RX_BUF_DEPTH (512U)
24 /* AHB TX BUF depth, in longwords */
25 #define FlexSPI_AHB_TX_BUF_DEPTH (32U)
26 /* IP_RX_BUF depth, in longwords */
27 #define FlexSPI_IP_RX_BUF_DEPTH (256U)
28 /* IP TX BUF depth, in longwords */
29 #define FlexSPI_IP_TX_BUF_DEPTH (256U)
30
31 /* FLEXSPI memory config block related defintions */
32 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
33 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
34 #define FLEXSPI_CFG_BLK_SIZE (512)
35
36 /* FLEXSPI Feature related definitions */
37 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
38
39 /* Lookup table related defintions */
40 #define CMD_INDEX_READ 0
41 #define CMD_INDEX_READSTATUS 1
42 #define CMD_INDEX_WRITEENABLE 2
43 #define CMD_INDEX_WRITE 4
44
45 #define CMD_LUT_SEQ_IDX_READ 0
46 #define CMD_LUT_SEQ_IDX_READSTATUS 1
47 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3
48 #define CMD_LUT_SEQ_IDX_WRITE 9
49
50 #define CMD_SDR 0x01
51 #define CMD_DDR 0x21
52 #define RADDR_SDR 0x02
53 #define RADDR_DDR 0x22
54 #define CADDR_SDR 0x03
55 #define CADDR_DDR 0x23
56 #define MODE1_SDR 0x04
57 #define MODE1_DDR 0x24
58 #define MODE2_SDR 0x05
59 #define MODE2_DDR 0x25
60 #define MODE4_SDR 0x06
61 #define MODE4_DDR 0x26
62 #define MODE8_SDR 0x07
63 #define MODE8_DDR 0x27
64 #define WRITE_SDR 0x08
65 #define WRITE_DDR 0x28
66 #define READ_SDR 0x09
67 #define READ_DDR 0x29
68 #define LEARN_SDR 0x0A
69 #define LEARN_DDR 0x2A
70 #define DATSZ_SDR 0x0B
71 #define DATSZ_DDR 0x2B
72 #define DUMMY_SDR 0x0C
73 #define DUMMY_DDR 0x2C
74 #define DUMMY_RWDS_SDR 0x0D
75 #define DUMMY_RWDS_DDR 0x2D
76 #define JMP_ON_CS 0x1F
77 #define STOP 0
78
79 #define FLEXSPI_1PAD 0
80 #define FLEXSPI_2PAD 1
81 #define FLEXSPI_4PAD 2
82 #define FLEXSPI_8PAD 3
83
84 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
85 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
86 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
87
89 enum
90 {
91 kFlexSpiSerialClk_SafeFreq = 1,
92 };
93
95 enum
96 {
97 kFlexSpiClk_SDR,
98 kFlexSpiClk_DDR,
99 };
100
102 typedef enum _FlashReadSampleClkSource
103 {
104 kFlexSPIReadSampleClk_LoopbackInternally = 0,
105 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
106 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
107 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
108 } flexspi_read_sample_clk_t;
109
111 typedef enum _FlexSpiIpCmdError
112 {
113 kFlexSpiIpCmdError_NoError = 0,
114 kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode = 1,
115 kFlexSpiIpCmdError_JumpOnCsInIpCmd = 2,
116 kFlexSpiIpCmdError_UnknownOpCode = 3,
117 kFlexSpiIpCmdError_SdrDummyInDdrSequence = 4,
118 kFlexSpiIpCmdError_DDRDummyInSdrSequence = 5,
119 kFlexSpiIpCmdError_InvalidAddress = 6,
120 kFlexSpiIpCmdError_SequenceExecutionTimeout = 0x0E,
121 kFlexSpiIpCmdError_FlashBoundaryAcrosss = 0x0F
122 } flexspi_ipcmd_error_t;
123
124 /* status code for flexspi */
125 enum _flexspi_status
126 {
127 kStatus_FLEXSPI_SequenceExecutionTimeout =
128 MAKE_STATUS(kStatusGroup_FLEXSPI, 0),
129 kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusGroup_FLEXSPI, 1),
130 kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 2),
131 };
132
134 enum
135 {
136 kFlexSpiMiscOffset_DiffClkEnable = 0,
137 kFlexSpiMiscOffset_Ck2Enable = 1,
138 kFlexSpiMiscOffset_ParallelEnable = 2,
139 kFlexSpiMiscOffset_WordAddressableEnable = 3,
140 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
141 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
142 kFlexSpiMiscOffset_DdrModeEnable = 6,
143 kFlexSpiMiscOffset_UseValidTimeForAllFreq = 7,
144 kFlexSpiMiscOffset_SecondPinMux = 8,
145 };
146
148 enum
149 {
150 kFlexSpiDeviceType_SerialNOR = 1,
151 kFlexSpiDeviceType_SerialNAND = 2,
152 kFlexSpiDeviceType_SerialRAM = 3,
153 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12,
154 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,
155 };
156
158 enum
159 {
160 kSerialFlash_1Pad = 1,
161 kSerialFlash_2Pads = 2,
162 kSerialFlash_4Pads = 4,
163 kSerialFlash_8Pads = 8,
164 };
165
167 typedef struct _lut_sequence
168 {
169 uint8_t seqNum;
170 uint8_t seqId;
171 uint16_t reserved;
172 } flexspi_lut_seq_t;
173
175 enum
176 {
177 kDeviceConfigCmdType_Generic,
178 kDeviceConfigCmdType_QuadEnable,
179 kDeviceConfigCmdType_Spi2Xpi,
180 kDeviceConfigCmdType_Xpi2Spi,
181 kDeviceConfigCmdType_Spi2NoCmd,
182 kDeviceConfigCmdType_Reset,
183 };
184
185 typedef struct
186 {
187 uint8_t time_100ps; // Data valid time, in terms of 100ps
188 uint8_t delay_cells; // Data valid time, in terms of delay cells
189 } flexspi_dll_time_t;
190
192 typedef struct _FlexSPIConfig
193 {
194 uint32_t tag;
195 uint32_t version;
196 uint32_t reserved0;
197 uint8_t readSampleClkSrc;
198 uint8_t csHoldTime;
199 uint8_t csSetupTime;
200 uint8_t columnAddressWidth;
201 uint8_t deviceModeCfgEnable;
203 uint8_t deviceModeType;
204 uint16_t waitTimeCfgCommands;
206 flexspi_lut_seq_t deviceModeSeq;
208 uint32_t deviceModeArg;
210 uint8_t configCmdEnable;
211 uint8_t configModeType[3];
212 flexspi_lut_seq_t
213 configCmdSeqs[3];
214 uint32_t reserved1;
215 uint32_t configCmdArgs[3];
216 uint32_t reserved2;
217 uint32_t controllerMiscOption;
218 uint8_t deviceType;
220 uint8_t sflashPadType;
221 uint8_t serialClkFreq;
222 uint8_t lutCustomSeqEnable;
224 uint32_t reserved3[2];
226 uint32_t sflashA1Size;
227 uint32_t sflashA2Size;
228 uint32_t sflashB1Size;
229 uint32_t sflashB2Size;
230 uint32_t csPadSettingOverride;
231 uint32_t sclkPadSettingOverride;
232 uint32_t dataPadSettingOverride;
233 uint32_t dqsPadSettingOverride;
234 uint32_t timeoutInMs;
235 uint32_t commandInterval;
236 flexspi_dll_time_t dataValidTime[2];
237 uint16_t busyOffset;
238 uint16_t busyBitPolarity;
239 uint32_t lookupTable[64];
241 flexspi_lut_seq_t lutCustomSeq[12];
242 uint32_t reserved4[4];
243 } flexspi_mem_config_t;
244
245 typedef enum _FlexSPIOperationType
246 {
247 kFlexSpiOperation_Command,
248 kFlexSpiOperation_Config,
250 kFlexSpiOperation_Write,
252 kFlexSpiOperation_Read,
254 kFlexSpiOperation_End = kFlexSpiOperation_Read,
256 } flexspi_operation_t;
257
259 typedef struct _FlexSpiXfer
260 {
261 flexspi_operation_t operation;
262 uint32_t baseAddress;
263 uint32_t seqId;
264 uint32_t seqNum;
265 bool isParallelModeEnable;
266 uint32_t *txBuffer;
267 uint32_t txSize;
268 uint32_t *rxBuffer;
269 uint32_t rxSize;
270 } flexspi_xfer_t;
271
273 typedef enum
274 {
275 kFlexSpiClock_CoreClock,
276 kFlexSpiClock_AhbClock,
277 kFlexSpiClock_SerialRootClock,
278 kFlexSpiClock_IpgClock,
279 } flexspi_clock_type_t;
280
282 #define FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset))
283
284 /**********************************************************************************************************************
285 * API
286 *********************************************************************************************************************/
287
288 #ifdef __cplusplus
289 extern "C" {
290 #endif
291
293 status_t flexspi_init(uint32_t instance, flexspi_mem_config_t *config);
294
296 status_t flexspi_device_write_enable(uint32_t instance,
297 flexspi_mem_config_t *config,
298 bool isParallelMode,
299 uint32_t baseAddr);
300
302 status_t flexspi_device_wait_busy(uint32_t instance,
303 flexspi_mem_config_t *config,
304 bool isParallelMode,
305 uint32_t baseAddr);
306
308 status_t flexspi_update_lut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq);
309
311 status_t flexspi_command_xfer(uint32_t instance, flexspi_xfer_t *xfer);
312
314 extern status_t flexspi_get_clock(uint32_t instance, flexspi_clock_type_t type, uint32_t *freq);
315
317 void flexspi_wait_idle(uint32_t instance);
318
320 void flexspi_clear_cache(uint32_t instance);
321
323 void flexspi_clear_sequence_pointer(uint32_t instance);
324
326 extern void flexspi_clock_gate_enable(uint32_t instance);
327
329 extern void flexspi_clock_gate_disable(uint32_t instance);
330
332 extern void flexspi_iomux_config(uint32_t instance, flexspi_mem_config_t *config);
333
335 extern void flexspi_clock_config(uint32_t instance, uint32_t freq, uint32_t sampleClkMode);
336
338 bool flexspi_is_padsetting_override_enable(flexspi_mem_config_t *config);
339
341 bool flexspi_is_differential_clock_enable(flexspi_mem_config_t *config);
342
344 bool flexspi_is_ddr_mode_enable(flexspi_mem_config_t *config);
345
347 bool flexspi_is_ck2_enabled(flexspi_mem_config_t *config);
348
350 bool flexspi_is_parallel_mode(flexspi_mem_config_t *config);
351
353 bool flexspi_is_word_addressable(flexspi_mem_config_t *config);
354
356 status_t flexspi_configure_dll(uint32_t instance, flexspi_mem_config_t *config);
357
359 void flexspi_half_clock_control(uint32_t instance, uint32_t option);
360
362 extern status_t flexspi_set_failsafe_setting(flexspi_mem_config_t *config);
363
365 extern status_t flexspi_get_max_supported_freq(uint32_t instance, uint32_t *freq, uint32_t clkMode);
366
367 extern void flexspi_sw_delay_us(uint64_t us);
368
369 extern void flexspi_update_padsetting(flexspi_mem_config_t *config, uint32_t driveStrength);
370
371 #ifdef __cplusplus
372 }
373 #endif
374
375 #endif
kDeviceConfigCmdType_Xpi2Spi
Switch from DPI/QPI/OPI to SPI mode.
Definition: fsl_flexspi.h:179
flexspi_is_padsetting_override_enable
bool flexspi_is_padsetting_override_enable(flexspi_mem_config_t *config)
Check whether Pad Setting Override feature is enabled.
Definition: fsl_flexspi.c:107
_lut_sequence::seqNum
uint8_t seqNum
Sequence Number, valid number: 1-16.
Definition: fsl_flexspi.h:168
kFlexSpiIpCmdError_FlashBoundaryAcrosss
Definition: fsl_flexspi.h:120
kDeviceConfigCmdType_Generic
Generic command, for example: configure dummy cycles, drive strength, etc.
Definition: fsl_flexspi.h:176
kSerialFlash_2Pads
Definition: fsl_flexspi.h:160
kFlexSpiMiscOffset_UseValidTimeForAllFreq
Bit for DLLCR settings under all modes.
Definition: fsl_flexspi.h:142
flexspi_set_failsafe_setting
status_t flexspi_set_failsafe_setting(flexspi_mem_config_t *config)
Set Failfase setting info.
kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode
Definition: fsl_flexspi.h:113
kFlexSpiClk_SDR
Clock configure for SDR mode.
Definition: fsl_flexspi.h:96
kFlexSpiMiscOffset_WordAddressableEnable
Bit for Word Addressable enable.
Definition: fsl_flexspi.h:138
flexspi_is_ddr_mode_enable
bool flexspi_is_ddr_mode_enable(flexspi_mem_config_t *config)
Check whether DDR mode feature is enabled.
Definition: fsl_flexspi.c:155
_FlexSPIConfig::reserved4
uint32_t reserved4[4]
[0x1b0-0x1bf] Reserved for future use
Definition: fsl_flexspi.h:241
flexspi_lut_seq_t
struct _lut_sequence flexspi_lut_seq_t
FlexSPI LUT Sequence structure.
_FlexSPIConfig::deviceModeArg
uint32_t deviceModeArg
sequence number, [31:16] Reserved
Definition: fsl_flexspi.h:208
_FlexSPIConfig::timeoutInMs
uint32_t timeoutInMs
[0x070-0x073] Timeout threshold for read status command
Definition: fsl_flexspi.h:233
kFlexSpiOperation_Write
TX FIFO size is fixed in LUT.
Definition: fsl_flexspi.h:250
_FlexSPIConfig::configModeType
uint8_t configModeType[3]
[0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
Definition: fsl_flexspi.h:210
_FlexSPIConfig::tag
uint32_t tag
[0x000-0x003] Tag, fixed value 0x42464346UL
Definition: fsl_flexspi.h:193
flexspi_clock_type_t
flexspi_clock_type_t
FlexSPI Clock Type.
Definition: fsl_flexspi.h:272
kFlexSPIReadSampleClk_LoopbackFromDqsPad
Definition: fsl_flexspi.h:104
flexspi_device_write_enable
status_t flexspi_device_write_enable(uint32_t instance, flexspi_mem_config_t *config, bool isParallelMode, uint32_t baseAddr)
Send Write enable command to Serial Memory device.
Definition: fsl_flexspi.c:543
_FlexSpiIpCmdError
_FlexSpiIpCmdError
FlexSPI IP Error codes.
Definition: fsl_flexspi.h:110
_FlexSPIConfig::csSetupTime
uint8_t csSetupTime
[0x00e-0x00e] CS setup time, default value: 3
Definition: fsl_flexspi.h:198
_lut_sequence::seqId
uint8_t seqId
Sequence Index, valid number: 0-15.
Definition: fsl_flexspi.h:169
_FlexSPIConfig::dataValidTime
flexspi_dll_time_t dataValidTime[2]
[0x078-0x07b] CLK edge to data valid time for PORT A and PORT B
Definition: fsl_flexspi.h:235
_FlexSPIConfig::lookupTable
uint32_t lookupTable[64]
busy flag is 0 when flash device is busy
Definition: fsl_flexspi.h:239
kFlexSpiClock_AhbClock
AHB clock.
Definition: fsl_flexspi.h:275
kFlexSpiDeviceType_SerialNOR
Flash devices are Serial NOR.
Definition: fsl_flexspi.h:149
_FlexSPIConfig::reserved2
uint32_t reserved2
[0x03c-0x03f] Reserved for future use
Definition: fsl_flexspi.h:215
flexspi_ipcmd_error_t
enum _FlexSpiIpCmdError flexspi_ipcmd_error_t
FlexSPI IP Error codes.
kFlexSpiClock_CoreClock
ARM Core Clock.
Definition: fsl_flexspi.h:274
kFlexSpiOperation_Config
RX buffer are ignored.
Definition: fsl_flexspi.h:248
kSerialFlash_8Pads
Definition: fsl_flexspi.h:162
_FlexSPIConfig::reserved3
uint32_t reserved3[2]
be done using 1 LUT sequence, currently, only applicable to HyperFLASH
Definition: fsl_flexspi.h:224
_FlexSpiXfer::baseAddress
uint32_t baseAddress
FlexSPI operation base address.
Definition: fsl_flexspi.h:261
kFlexSpiIpCmdError_UnknownOpCode
Definition: fsl_flexspi.h:115
kFlexSpiIpCmdError_InvalidAddress
Definition: fsl_flexspi.h:118
kFlexSpiSerialClk_SafeFreq
Definition: fsl_flexspi.h:90
_FlexSPIConfig::sflashA2Size
uint32_t sflashA2Size
[0x054-0x057] Size of Flash connected to A2
Definition: fsl_flexspi.h:226
_FlexSpiXfer::seqId
uint32_t seqId
Sequence Id.
Definition: fsl_flexspi.h:262
flexspi_mem_config_t
struct _FlexSPIConfig flexspi_mem_config_t
FlexSPI Memory Configuration Block.
_FlexSpiXfer
FlexSPI Transfer Context.
Definition: fsl_flexspi.h:258
kFlexSpiMiscOffset_PadSettingOverrideEnable
Bit for Pad setting override enable.
Definition: fsl_flexspi.h:140
_FlashReadSampleClkSource
_FlashReadSampleClkSource
FlexSPI Read Sample Clock Source definition.
Definition: fsl_flexspi.h:101
flexspi_update_lut
status_t flexspi_update_lut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq)
Configure FlexSPI Lookup table.
Definition: fsl_flexspi.c:924
flexspi_update_padsetting
void flexspi_update_padsetting(flexspi_mem_config_t *config, uint32_t driveStrength)
kDeviceConfigCmdType_Reset
Reset device command.
Definition: fsl_flexspi.h:181
_FlexSpiXfer::operation
flexspi_operation_t operation
FlexSPI operation.
Definition: fsl_flexspi.h:260
flexspi_init
status_t flexspi_init(uint32_t instance, flexspi_mem_config_t *config)
Initialize FlexSPI.
Definition: fsl_flexspi.c:769
flexspi_clock_config
void flexspi_clock_config(uint32_t instance, uint32_t freq, uint32_t sampleClkMode)
Configure Clock for FlexSPI.
kFlexSPIReadSampleClk_LoopbackInternally
Definition: fsl_flexspi.h:103
kFlexSpiOperation_Read
effective
Definition: fsl_flexspi.h:252
_FlexSPIConfig::csHoldTime
uint8_t csHoldTime
[0x00d-0x00d] CS hold time, default value: 3
Definition: fsl_flexspi.h:197
kFlexSpiIpCmdError_JumpOnCsInIpCmd
Definition: fsl_flexspi.h:114
_FlexSPIConfig::configCmdEnable
uint8_t configCmdEnable
[0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
Definition: fsl_flexspi.h:209
kFlexSpiMiscOffset_DiffClkEnable
Bit for Differential clock enable.
Definition: fsl_flexspi.h:135
_FlexSPIConfig::readSampleClkSrc
uint8_t readSampleClkSrc
[0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
Definition: fsl_flexspi.h:196
flexspi_half_clock_control
void flexspi_half_clock_control(uint32_t instance, uint32_t option)
Half FlexSPI Clock.
Definition: fsl_flexspi.c:1360
flexspi_iomux_config
void flexspi_iomux_config(uint32_t instance, flexspi_mem_config_t *config)
Configure IOMUX for FlexSPI.
kFlexSpiMiscOffset_Ck2Enable
Bit for CK2 enable.
Definition: fsl_flexspi.h:136
_FlexSpiXfer::isParallelModeEnable
bool isParallelModeEnable
Is a parallel transfer.
Definition: fsl_flexspi.h:264
_FlexSPIConfig::busyOffset
uint16_t busyOffset
[0x07c-0x07d] Busy offset, valid value: 0-31
Definition: fsl_flexspi.h:236
_FlexSPIConfig::busyBitPolarity
uint16_t busyBitPolarity
Definition: fsl_flexspi.h:237
_FlexSPIConfig::deviceType
uint8_t deviceType
details
Definition: fsl_flexspi.h:218
_FlexSPIConfig::configCmdArgs
uint32_t configCmdArgs[3]
[0x030-0x03b] Arguments/Parameters for device Configuration commands
Definition: fsl_flexspi.h:214
_FlexSPIConfig::deviceModeType
uint8_t deviceModeType
Definition: fsl_flexspi.h:202
_FlexSPIConfig::csPadSettingOverride
uint32_t csPadSettingOverride
[0x060-0x063] CS pad setting override value
Definition: fsl_flexspi.h:229
_FlexSPIConfig::sflashPadType
uint8_t sflashPadType
[0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
Definition: fsl_flexspi.h:219
flexspi_read_sample_clk_t
enum _FlashReadSampleClkSource flexspi_read_sample_clk_t
FlexSPI Read Sample Clock Source definition.
flexspi_wait_idle
void flexspi_wait_idle(uint32_t instance)
Wait until FlexSPI controller becomes idle.
Definition: fsl_flexspi.c:1171
kStatus_FLEXSPI_InvalidSequence
Status for Invalid Sequence.
Definition: fsl_flexspi.h:128
flexspi_clock_gate_disable
void flexspi_clock_gate_disable(uint32_t instance)
Disable clock gate of FlexSPI.
kDeviceConfigCmdType_QuadEnable
Quad Enable command.
Definition: fsl_flexspi.h:177
kFlexSPIReadSampleClk_LoopbackFromSckPad
Definition: fsl_flexspi.h:105
_FlexSPIConfig::deviceModeCfgEnable
uint8_t deviceModeCfgEnable
Serial NAND, need to refer to datasheet.
Definition: fsl_flexspi.h:201
kDeviceConfigCmdType_Spi2Xpi
Switch from SPI to DPI/QPI/OPI mode.
Definition: fsl_flexspi.h:178
_FlexSPIConfig::reserved0
uint32_t reserved0
[0x008-0x00b] Reserved for future use
Definition: fsl_flexspi.h:195
kFlexSpiDeviceType_SerialNAND
Flash devices are Serial NAND.
Definition: fsl_flexspi.h:150
_flexspi_status
_flexspi_status
Definition: fsl_flexspi.h:124
_FlexSPIConfig::sflashB1Size
uint32_t sflashB1Size
[0x058-0x05b] Size of Flash connected to B1
Definition: fsl_flexspi.h:227
_FlexSPIConfig::version
uint32_t version
[0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
Definition: fsl_flexspi.h:194
_FlexSPIConfig::reserved1
uint32_t reserved1
[0x02c-0x02f] Reserved for future use
Definition: fsl_flexspi.h:213
kFlexSpiOperation_Command
Definition: fsl_flexspi.h:246
_FlexSpiXfer::txSize
uint32_t txSize
Tx size in bytes.
Definition: fsl_flexspi.h:266
kFlexSpiClk_DDR
Clock configurat for DDR mode.
Definition: fsl_flexspi.h:97
_FlexSPIConfig::controllerMiscOption
uint32_t controllerMiscOption
Definition: fsl_flexspi.h:216
_FlexSPIOperationType
_FlexSPIOperationType
Definition: fsl_flexspi.h:244
_FlexSpiXfer::rxSize
uint32_t rxSize
Rx size in bytes.
Definition: fsl_flexspi.h:268
kFlexSpiMiscOffset_SecondPinMux
Bit for Second Pinmux group.
Definition: fsl_flexspi.h:143
kFlexSpiClock_SerialRootClock
Serial Root Clock.
Definition: fsl_flexspi.h:276
kFlexSpiMiscOffset_SafeConfigFreqEnable
Bit for Safe Configuration Frequency enable.
Definition: fsl_flexspi.h:139
flexspi_is_word_addressable
bool flexspi_is_word_addressable(flexspi_mem_config_t *config)
Check whether device works under word addressable mode.
Definition: fsl_flexspi.c:131
kFlexSpiMiscOffset_ParallelEnable
Bit for Parallel mode enable.
Definition: fsl_flexspi.h:137
kFlexSpiDeviceType_MCP_NOR_NAND
Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND.
Definition: fsl_flexspi.h:152
_FlexSPIConfig::dataPadSettingOverride
uint32_t dataPadSettingOverride
[0x068-0x06b] data pad setting override value
Definition: fsl_flexspi.h:231
flexspi_configure_dll
status_t flexspi_configure_dll(uint32_t instance, flexspi_mem_config_t *config)
Configure FlexSPI DLL register.
Definition: fsl_flexspi.c:168
kFlexSpiDeviceType_MCP_NOR_RAM
Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs.
Definition: fsl_flexspi.h:153
flexspi_clear_cache
void flexspi_clear_cache(uint32_t instance)
Clear FlexSPI cache.
Definition: fsl_flexspi.c:1189
kFlexSpiOperation_End
effective.
Definition: fsl_flexspi.h:254
kFlexSpiIpCmdError_SequenceExecutionTimeout
Definition: fsl_flexspi.h:119
_FlexSPIConfig::waitTimeCfgCommands
uint16_t waitTimeCfgCommands
Generic configuration, etc.
Definition: fsl_flexspi.h:204
_FlexSPIConfig::dqsPadSettingOverride
uint32_t dqsPadSettingOverride
[0x06c-0x06f] DQS pad setting override value
Definition: fsl_flexspi.h:232
_FlexSPIConfig::columnAddressWidth
uint8_t columnAddressWidth
Definition: fsl_flexspi.h:199
_FlexSpiXfer::txBuffer
uint32_t * txBuffer
Tx buffer.
Definition: fsl_flexspi.h:265
_FlexSpiXfer::rxBuffer
uint32_t * rxBuffer
Rx buffer.
Definition: fsl_flexspi.h:267
kFlexSPIReadSampleClk_ExternalInputFromDqsPad
Definition: fsl_flexspi.h:106
flexspi_clock_gate_enable
void flexspi_clock_gate_enable(uint32_t instance)
Enable clock gate of FlexSPI.
flexspi_sw_delay_us
void flexspi_sw_delay_us(uint64_t us)
_FlexSpiXfer::seqNum
uint32_t seqNum
Sequence Number.
Definition: fsl_flexspi.h:263
_FlexSPIConfig::lutCustomSeq
flexspi_lut_seq_t lutCustomSeq[12]
[0x180-0x1af] Customizable LUT Sequences
Definition: fsl_flexspi.h:240
_FlexSPIConfig::sflashA1Size
uint32_t sflashA1Size
[0x050-0x053] Size of Flash connected to A1
Definition: fsl_flexspi.h:225
flexspi_get_max_supported_freq
status_t flexspi_get_max_supported_freq(uint32_t instance, uint32_t *freq, uint32_t clkMode)
Get Maximumn clock frequency.
kFlexSpiIpCmdError_NoError
Definition: fsl_flexspi.h:112
_FlexSPIConfig::deviceModeSeq
flexspi_lut_seq_t deviceModeSeq
DPI/QPI/OPI switch or reset command.
Definition: fsl_flexspi.h:206
flexspi_is_parallel_mode
bool flexspi_is_parallel_mode(flexspi_mem_config_t *config)
Check whether Parallel mode feature is enabled.
Definition: fsl_flexspi.c:95
kSerialFlash_4Pads
Definition: fsl_flexspi.h:161
kDeviceConfigCmdType_Spi2NoCmd
Switch to 0-4-4/0-8-8 mode.
Definition: fsl_flexspi.h:180
kFlexSpiDeviceType_SerialRAM
Flash devices are Serial RAM/HyperFLASH.
Definition: fsl_flexspi.h:151
_FlexSPIConfig::configCmdSeqs
flexspi_lut_seq_t configCmdSeqs[3]
[0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
Definition: fsl_flexspi.h:212
flexspi_clear_sequence_pointer
void flexspi_clear_sequence_pointer(uint32_t instance)
Clear FlexSPI sequence pointer.
Definition: fsl_flexspi.c:1340
kStatus_FLEXSPI_DeviceTimeout
Status for Device timeout.
Definition: fsl_flexspi.h:129
_FlexSPIConfig::lutCustomSeqEnable
uint8_t lutCustomSeqEnable
Chapter for more details.
Definition: fsl_flexspi.h:222
kStatus_FLEXSPI_SequenceExecutionTimeout
Status for Sequence Execution timeout.
Definition: fsl_flexspi.h:126
kFlexSpiClock_IpgClock
IPG clock.
Definition: fsl_flexspi.h:277
kFlexSpiIpCmdError_SdrDummyInDdrSequence
Definition: fsl_flexspi.h:116
flexspi_xfer_t
struct _FlexSpiXfer flexspi_xfer_t
FlexSPI Transfer Context.
flexspi_command_xfer
status_t flexspi_command_xfer(uint32_t instance, flexspi_xfer_t *xfer)
Perform FlexSPI command.
Definition: fsl_flexspi.c:965
flexspi_get_clock
status_t flexspi_get_clock(uint32_t instance, flexspi_clock_type_t type, uint32_t *freq)
Get FlexSPI Clock frequency.
flexspi_is_differential_clock_enable
bool flexspi_is_differential_clock_enable(flexspi_mem_config_t *config)
Check whether Differential clock feature is enabled.
Definition: fsl_flexspi.c:119
flexspi_is_ck2_enabled
bool flexspi_is_ck2_enabled(flexspi_mem_config_t *config)
Check whether CK2 feature is enabled.
Definition: fsl_flexspi.c:143
flexspi_dll_time_t
Definition: fsl_flexspi.h:184
kSerialFlash_1Pad
Definition: fsl_flexspi.h:159
_FlexSPIConfig
FlexSPI Memory Configuration Block.
Definition: fsl_flexspi.h:191
_FlexSPIConfig::serialClkFreq
uint8_t serialClkFreq
Definition: fsl_flexspi.h:220
_FlexSPIConfig::sflashB2Size
uint32_t sflashB2Size
[0x05c-0x05f] Size of Flash connected to B2
Definition: fsl_flexspi.h:228
_lut_sequence
FlexSPI LUT Sequence structure.
Definition: fsl_flexspi.h:166
flexspi_operation_t
enum _FlexSPIOperationType flexspi_operation_t
kFlexSpiMiscOffset_DdrModeEnable
Bit for DDR clock confiuration indication.
Definition: fsl_flexspi.h:141
_FlexSPIConfig::sclkPadSettingOverride
uint32_t sclkPadSettingOverride
[0x064-0x067] SCK pad setting override value
Definition: fsl_flexspi.h:230
flexspi_device_wait_busy
status_t flexspi_device_wait_busy(uint32_t instance, flexspi_mem_config_t *config, bool isParallelMode, uint32_t baseAddr)
Wait until device is idle.
Definition: fsl_flexspi.c:1233
_lut_sequence::reserved
uint16_t reserved
Definition: fsl_flexspi.h:170
_FlexSPIConfig::commandInterval
uint32_t commandInterval
[0x074-0x077] CS deselect interval between two commands
Definition: fsl_flexspi.h:234
kFlexSpiIpCmdError_DDRDummyInSdrSequence
Definition: fsl_flexspi.h:117