Callisto4Bootloader: CMSIS/core_cm7.h Source File

Callisto4Bootloader

core_cm7.h
Go to the documentation of this file.
1 /**************************************************************************/
7 /*
8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM7_H_GENERIC
32 #define __CORE_CM7_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
63 #include "cmsis_version.h"
64
65 /* CMSIS CM7 definitions */
66 #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB)
68 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
69 __CM7_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (7U)
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89 #if defined __ARM_FP
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91 #define __FPU_USED 1U
92 #else
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #define __FPU_USED 0U
95 #endif
96 #else
97 #define __FPU_USED 0U
98 #endif
99
100 #elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
104 #else
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
107 #endif
108 #else
109 #define __FPU_USED 0U
110 #endif
111
112 #elif defined ( __ICCARM__ )
113 #if defined __ARMVFP__
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
116 #else
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
119 #endif
120 #else
121 #define __FPU_USED 0U
122 #endif
123
124 #elif defined ( __TI_ARM__ )
125 #if defined __TI_VFP_SUPPORT__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136 #elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
140 #else
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
143 #endif
144 #else
145 #define __FPU_USED 0U
146 #endif
147
148 #elif defined ( __CSMC__ )
149 #if ( __CSMC__ & 0x400U)
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
152 #else
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
155 #endif
156 #else
157 #define __FPU_USED 0U
158 #endif
159
160 #endif
161
162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
163
164
165 #ifdef __cplusplus
166 }
167 #endif
168
169 #endif /* __CORE_CM7_H_GENERIC */
170
171 #ifndef __CMSIS_GENERIC
172
173 #ifndef __CORE_CM7_H_DEPENDANT
174 #define __CORE_CM7_H_DEPENDANT
175
176 #ifdef __cplusplus
177 extern "C" {
178 #endif
179
180 /* check device defines and use defaults */
181 #if defined __CHECK_DEVICE_DEFINES
182 #ifndef __CM7_REV
183 #define __CM7_REV 0x0000U
184 #warning "__CM7_REV not defined in device header file; using default!"
185 #endif
186
187 #ifndef __FPU_PRESENT
188 #define __FPU_PRESENT 0U
189 #warning "__FPU_PRESENT not defined in device header file; using default!"
190 #endif
191
192 #ifndef __MPU_PRESENT
193 #define __MPU_PRESENT 0U
194 #warning "__MPU_PRESENT not defined in device header file; using default!"
195 #endif
196
197 #ifndef __ICACHE_PRESENT
198 #define __ICACHE_PRESENT 0U
199 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
200 #endif
201
202 #ifndef __DCACHE_PRESENT
203 #define __DCACHE_PRESENT 0U
204 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
205 #endif
206
207 #ifndef __DTCM_PRESENT
208 #define __DTCM_PRESENT 0U
209 #warning "__DTCM_PRESENT not defined in device header file; using default!"
210 #endif
211
212 #ifndef __NVIC_PRIO_BITS
213 #define __NVIC_PRIO_BITS 3U
214 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
215 #endif
216
217 #ifndef __Vendor_SysTickConfig
218 #define __Vendor_SysTickConfig 0U
219 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
220 #endif
221 #endif
222
223 /* IO definitions (access restrictions to peripheral registers) */
231 #ifdef __cplusplus
232 #define __I volatile
233 #else
234 #define __I volatile const
235 #endif
236 #define __O volatile
237 #define __IO volatile
239 /* following defines should be used for structure members */
240 #define __IM volatile const
241 #define __OM volatile
242 #define __IOM volatile
244
248 /*******************************************************************************
249 * Register Abstraction
250 Core Register contain:
251 - Core Register
252 - Core NVIC Register
253 - Core SCB Register
254 - Core SysTick Register
255 - Core Debug Register
256 - Core MPU Register
257 - Core FPU Register
258 ******************************************************************************/
259
274 typedef union
275 {
276 struct
277 {
278 uint32_t _reserved0:16;
279 uint32_t GE:4;
280 uint32_t _reserved1:7;
281 uint32_t Q:1;
282 uint32_t V:1;
283 uint32_t C:1;
284 uint32_t Z:1;
285 uint32_t N:1;
286 } b;
287 uint32_t w;
288 } APSR_Type;
289
290 /* APSR Register Definitions */
291 #define APSR_N_Pos 31U
292 #define APSR_N_Msk (1UL << APSR_N_Pos)
294 #define APSR_Z_Pos 30U
295 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
297 #define APSR_C_Pos 29U
298 #define APSR_C_Msk (1UL << APSR_C_Pos)
300 #define APSR_V_Pos 28U
301 #define APSR_V_Msk (1UL << APSR_V_Pos)
303 #define APSR_Q_Pos 27U
304 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
306 #define APSR_GE_Pos 16U
307 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
313 typedef union
314 {
315 struct
316 {
317 uint32_t ISR:9;
318 uint32_t _reserved0:23;
319 } b;
320 uint32_t w;
321 } IPSR_Type;
322
323 /* IPSR Register Definitions */
324 #define IPSR_ISR_Pos 0U
325 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
331 typedef union
332 {
333 struct
334 {
335 uint32_t ISR:9;
336 uint32_t _reserved0:1;
337 uint32_t ICI_IT_1:6;
338 uint32_t GE:4;
339 uint32_t _reserved1:4;
340 uint32_t T:1;
341 uint32_t ICI_IT_2:2;
342 uint32_t Q:1;
343 uint32_t V:1;
344 uint32_t C:1;
345 uint32_t Z:1;
346 uint32_t N:1;
347 } b;
348 uint32_t w;
349 } xPSR_Type;
350
351 /* xPSR Register Definitions */
352 #define xPSR_N_Pos 31U
353 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
355 #define xPSR_Z_Pos 30U
356 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
358 #define xPSR_C_Pos 29U
359 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
361 #define xPSR_V_Pos 28U
362 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
364 #define xPSR_Q_Pos 27U
365 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
367 #define xPSR_ICI_IT_2_Pos 25U
368 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
370 #define xPSR_T_Pos 24U
371 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
373 #define xPSR_GE_Pos 16U
374 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
376 #define xPSR_ICI_IT_1_Pos 10U
377 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
379 #define xPSR_ISR_Pos 0U
380 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
386 typedef union
387 {
388 struct
389 {
390 uint32_t nPRIV:1;
391 uint32_t SPSEL:1;
392 uint32_t FPCA:1;
393 uint32_t _reserved0:29;
394 } b;
395 uint32_t w;
396 } CONTROL_Type;
397
398 /* CONTROL Register Definitions */
399 #define CONTROL_FPCA_Pos 2U
400 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
402 #define CONTROL_SPSEL_Pos 1U
403 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
405 #define CONTROL_nPRIV_Pos 0U
406 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
408
421 typedef struct
422 {
423 __IOM uint32_t ISER[8U];
424 uint32_t RESERVED0[24U];
425 __IOM uint32_t ICER[8U];
426 uint32_t RESERVED1[24U];
427 __IOM uint32_t ISPR[8U];
428 uint32_t RESERVED2[24U];
429 __IOM uint32_t ICPR[8U];
430 uint32_t RESERVED3[24U];
431 __IOM uint32_t IABR[8U];
432 uint32_t RESERVED4[56U];
433 __IOM uint8_t IP[240U];
434 uint32_t RESERVED5[644U];
435 __OM uint32_t STIR;
436 } NVIC_Type;
437
438 /* Software Triggered Interrupt Register Definitions */
439 #define NVIC_STIR_INTID_Pos 0U
440 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
442
455 typedef struct
456 {
457 __IM uint32_t CPUID;
458 __IOM uint32_t ICSR;
459 __IOM uint32_t VTOR;
460 __IOM uint32_t AIRCR;
461 __IOM uint32_t SCR;
462 __IOM uint32_t CCR;
463 __IOM uint8_t SHPR[12U];
464 __IOM uint32_t SHCSR;
465 __IOM uint32_t CFSR;
466 __IOM uint32_t HFSR;
467 __IOM uint32_t DFSR;
468 __IOM uint32_t MMFAR;
469 __IOM uint32_t BFAR;
470 __IOM uint32_t AFSR;
471 __IM uint32_t ID_PFR[2U];
472 __IM uint32_t ID_DFR;
473 __IM uint32_t ID_AFR;
474 __IM uint32_t ID_MFR[4U];
475 __IM uint32_t ID_ISAR[5U];
476 uint32_t RESERVED0[1U];
477 __IM uint32_t CLIDR;
478 __IM uint32_t CTR;
479 __IM uint32_t CCSIDR;
480 __IOM uint32_t CSSELR;
481 __IOM uint32_t CPACR;
482 uint32_t RESERVED3[93U];
483 __OM uint32_t STIR;
484 uint32_t RESERVED4[15U];
485 __IM uint32_t MVFR0;
486 __IM uint32_t MVFR1;
487 __IM uint32_t MVFR2;
488 uint32_t RESERVED5[1U];
489 __OM uint32_t ICIALLU;
490 uint32_t RESERVED6[1U];
491 __OM uint32_t ICIMVAU;
492 __OM uint32_t DCIMVAC;
493 __OM uint32_t DCISW;
494 __OM uint32_t DCCMVAU;
495 __OM uint32_t DCCMVAC;
496 __OM uint32_t DCCSW;
497 __OM uint32_t DCCIMVAC;
498 __OM uint32_t DCCISW;
499 uint32_t RESERVED7[6U];
500 __IOM uint32_t ITCMCR;
501 __IOM uint32_t DTCMCR;
502 __IOM uint32_t AHBPCR;
503 __IOM uint32_t CACR;
504 __IOM uint32_t AHBSCR;
505 uint32_t RESERVED8[1U];
506 __IOM uint32_t ABFSR;
507 } SCB_Type;
508
509 /* SCB CPUID Register Definitions */
510 #define SCB_CPUID_IMPLEMENTER_Pos 24U
511 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
513 #define SCB_CPUID_VARIANT_Pos 20U
514 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
516 #define SCB_CPUID_ARCHITECTURE_Pos 16U
517 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
519 #define SCB_CPUID_PARTNO_Pos 4U
520 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
522 #define SCB_CPUID_REVISION_Pos 0U
523 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
525 /* SCB Interrupt Control State Register Definitions */
526 #define SCB_ICSR_NMIPENDSET_Pos 31U
527 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
529 #define SCB_ICSR_PENDSVSET_Pos 28U
530 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
532 #define SCB_ICSR_PENDSVCLR_Pos 27U
533 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
535 #define SCB_ICSR_PENDSTSET_Pos 26U
536 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
538 #define SCB_ICSR_PENDSTCLR_Pos 25U
539 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
541 #define SCB_ICSR_ISRPREEMPT_Pos 23U
542 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
544 #define SCB_ICSR_ISRPENDING_Pos 22U
545 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
547 #define SCB_ICSR_VECTPENDING_Pos 12U
548 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
550 #define SCB_ICSR_RETTOBASE_Pos 11U
551 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
553 #define SCB_ICSR_VECTACTIVE_Pos 0U
554 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
556 /* SCB Vector Table Offset Register Definitions */
557 #define SCB_VTOR_TBLOFF_Pos 7U
558 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
560 /* SCB Application Interrupt and Reset Control Register Definitions */
561 #define SCB_AIRCR_VECTKEY_Pos 16U
562 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
564 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
565 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
567 #define SCB_AIRCR_ENDIANESS_Pos 15U
568 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
570 #define SCB_AIRCR_PRIGROUP_Pos 8U
571 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
573 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
574 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
576 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
577 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
579 #define SCB_AIRCR_VECTRESET_Pos 0U
580 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
582 /* SCB System Control Register Definitions */
583 #define SCB_SCR_SEVONPEND_Pos 4U
584 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
586 #define SCB_SCR_SLEEPDEEP_Pos 2U
587 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
589 #define SCB_SCR_SLEEPONEXIT_Pos 1U
590 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
592 /* SCB Configuration Control Register Definitions */
593 #define SCB_CCR_BP_Pos 18U
594 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
596 #define SCB_CCR_IC_Pos 17U
597 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
599 #define SCB_CCR_DC_Pos 16U
600 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
602 #define SCB_CCR_STKALIGN_Pos 9U
603 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
605 #define SCB_CCR_BFHFNMIGN_Pos 8U
606 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
608 #define SCB_CCR_DIV_0_TRP_Pos 4U
609 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
611 #define SCB_CCR_UNALIGN_TRP_Pos 3U
612 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
614 #define SCB_CCR_USERSETMPEND_Pos 1U
615 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
617 #define SCB_CCR_NONBASETHRDENA_Pos 0U
618 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
620 /* SCB System Handler Control and State Register Definitions */
621 #define SCB_SHCSR_USGFAULTENA_Pos 18U
622 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
624 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
625 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
627 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
628 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
630 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
631 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
633 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
634 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
636 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
637 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
639 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
640 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
642 #define SCB_SHCSR_SYSTICKACT_Pos 11U
643 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
645 #define SCB_SHCSR_PENDSVACT_Pos 10U
646 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
648 #define SCB_SHCSR_MONITORACT_Pos 8U
649 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
651 #define SCB_SHCSR_SVCALLACT_Pos 7U
652 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
654 #define SCB_SHCSR_USGFAULTACT_Pos 3U
655 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
657 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
658 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
660 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
661 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
663 /* SCB Configurable Fault Status Register Definitions */
664 #define SCB_CFSR_USGFAULTSR_Pos 16U
665 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
667 #define SCB_CFSR_BUSFAULTSR_Pos 8U
668 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
670 #define SCB_CFSR_MEMFAULTSR_Pos 0U
671 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
673 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
674 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
675 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
677 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
678 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
680 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
681 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
683 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
684 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
686 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
687 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
689 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
690 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
692 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
693 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
694 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
696 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
697 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
699 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
700 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
702 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
703 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
705 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
706 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
708 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
709 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
711 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
712 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
714 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
715 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
716 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
718 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
719 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
721 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
722 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
724 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
725 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
727 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
728 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
730 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
731 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
733 /* SCB Hard Fault Status Register Definitions */
734 #define SCB_HFSR_DEBUGEVT_Pos 31U
735 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
737 #define SCB_HFSR_FORCED_Pos 30U
738 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
740 #define SCB_HFSR_VECTTBL_Pos 1U
741 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
743 /* SCB Debug Fault Status Register Definitions */
744 #define SCB_DFSR_EXTERNAL_Pos 4U
745 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
747 #define SCB_DFSR_VCATCH_Pos 3U
748 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
750 #define SCB_DFSR_DWTTRAP_Pos 2U
751 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
753 #define SCB_DFSR_BKPT_Pos 1U
754 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
756 #define SCB_DFSR_HALTED_Pos 0U
757 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
759 /* SCB Cache Level ID Register Definitions */
760 #define SCB_CLIDR_LOUU_Pos 27U
761 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
763 #define SCB_CLIDR_LOC_Pos 24U
764 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
766 /* SCB Cache Type Register Definitions */
767 #define SCB_CTR_FORMAT_Pos 29U
768 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
770 #define SCB_CTR_CWG_Pos 24U
771 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
773 #define SCB_CTR_ERG_Pos 20U
774 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
776 #define SCB_CTR_DMINLINE_Pos 16U
777 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
779 #define SCB_CTR_IMINLINE_Pos 0U
780 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
782 /* SCB Cache Size ID Register Definitions */
783 #define SCB_CCSIDR_WT_Pos 31U
784 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
786 #define SCB_CCSIDR_WB_Pos 30U
787 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
789 #define SCB_CCSIDR_RA_Pos 29U
790 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
792 #define SCB_CCSIDR_WA_Pos 28U
793 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
795 #define SCB_CCSIDR_NUMSETS_Pos 13U
796 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
798 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
799 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
801 #define SCB_CCSIDR_LINESIZE_Pos 0U
802 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
804 /* SCB Cache Size Selection Register Definitions */
805 #define SCB_CSSELR_LEVEL_Pos 1U
806 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
808 #define SCB_CSSELR_IND_Pos 0U
809 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
811 /* SCB Software Triggered Interrupt Register Definitions */
812 #define SCB_STIR_INTID_Pos 0U
813 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
815 /* SCB D-Cache Invalidate by Set-way Register Definitions */
816 #define SCB_DCISW_WAY_Pos 30U
817 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
819 #define SCB_DCISW_SET_Pos 5U
820 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
822 /* SCB D-Cache Clean by Set-way Register Definitions */
823 #define SCB_DCCSW_WAY_Pos 30U
824 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
826 #define SCB_DCCSW_SET_Pos 5U
827 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
829 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
830 #define SCB_DCCISW_WAY_Pos 30U
831 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
833 #define SCB_DCCISW_SET_Pos 5U
834 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
836 /* Instruction Tightly-Coupled Memory Control Register Definitions */
837 #define SCB_ITCMCR_SZ_Pos 3U
838 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
840 #define SCB_ITCMCR_RETEN_Pos 2U
841 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
843 #define SCB_ITCMCR_RMW_Pos 1U
844 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
846 #define SCB_ITCMCR_EN_Pos 0U
847 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
849 /* Data Tightly-Coupled Memory Control Register Definitions */
850 #define SCB_DTCMCR_SZ_Pos 3U
851 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
853 #define SCB_DTCMCR_RETEN_Pos 2U
854 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
856 #define SCB_DTCMCR_RMW_Pos 1U
857 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
859 #define SCB_DTCMCR_EN_Pos 0U
860 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
862 /* AHBP Control Register Definitions */
863 #define SCB_AHBPCR_SZ_Pos 1U
864 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
866 #define SCB_AHBPCR_EN_Pos 0U
867 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
869 /* L1 Cache Control Register Definitions */
870 #define SCB_CACR_FORCEWT_Pos 2U
871 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
873 #define SCB_CACR_ECCEN_Pos 1U
874 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
876 #define SCB_CACR_SIWT_Pos 0U
877 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
879 /* AHBS Control Register Definitions */
880 #define SCB_AHBSCR_INITCOUNT_Pos 11U
881 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
883 #define SCB_AHBSCR_TPRI_Pos 2U
884 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
886 #define SCB_AHBSCR_CTL_Pos 0U
887 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
889 /* Auxiliary Bus Fault Status Register Definitions */
890 #define SCB_ABFSR_AXIMTYPE_Pos 8U
891 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
893 #define SCB_ABFSR_EPPB_Pos 4U
894 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
896 #define SCB_ABFSR_AXIM_Pos 3U
897 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
899 #define SCB_ABFSR_AHBP_Pos 2U
900 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
902 #define SCB_ABFSR_DTCM_Pos 1U
903 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
905 #define SCB_ABFSR_ITCM_Pos 0U
906 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
908
921 typedef struct
922 {
923 uint32_t RESERVED0[1U];
924 __IM uint32_t ICTR;
925 __IOM uint32_t ACTLR;
926 } SCnSCB_Type;
927
928 /* Interrupt Controller Type Register Definitions */
929 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
930 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
932 /* Auxiliary Control Register Definitions */
933 #define SCnSCB_ACTLR_DISDYNADD_Pos 26U
934 #define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)
936 #define SCnSCB_ACTLR_DISISSCH1_Pos 21U
937 #define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)
939 #define SCnSCB_ACTLR_DISDI_Pos 16U
940 #define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)
942 #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U
943 #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)
945 #define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U
946 #define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)
948 #define SCnSCB_ACTLR_DISBTACREAD_Pos 13U
949 #define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)
951 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U
952 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)
954 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U
955 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)
957 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U
958 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)
960 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
961 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
963 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
964 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
966
979 typedef struct
980 {
981 __IOM uint32_t CTRL;
982 __IOM uint32_t LOAD;
983 __IOM uint32_t VAL;
984 __IM uint32_t CALIB;
985 } SysTick_Type;
986
987 /* SysTick Control / Status Register Definitions */
988 #define SysTick_CTRL_COUNTFLAG_Pos 16U
989 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
991 #define SysTick_CTRL_CLKSOURCE_Pos 2U
992 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
994 #define SysTick_CTRL_TICKINT_Pos 1U
995 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
997 #define SysTick_CTRL_ENABLE_Pos 0U
998 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1000 /* SysTick Reload Register Definitions */
1001 #define SysTick_LOAD_RELOAD_Pos 0U
1002 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1004 /* SysTick Current Register Definitions */
1005 #define SysTick_VAL_CURRENT_Pos 0U
1006 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1008 /* SysTick Calibration Register Definitions */
1009 #define SysTick_CALIB_NOREF_Pos 31U
1010 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1012 #define SysTick_CALIB_SKEW_Pos 30U
1013 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1015 #define SysTick_CALIB_TENMS_Pos 0U
1016 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1018
1031 typedef struct
1032 {
1033 __OM union
1034 {
1035 __OM uint8_t u8;
1036 __OM uint16_t u16;
1037 __OM uint32_t u32;
1038 } PORT [32U];
1039 uint32_t RESERVED0[864U];
1040 __IOM uint32_t TER;
1041 uint32_t RESERVED1[15U];
1042 __IOM uint32_t TPR;
1043 uint32_t RESERVED2[15U];
1044 __IOM uint32_t TCR;
1045 uint32_t RESERVED3[32U];
1046 uint32_t RESERVED4[43U];
1047 __OM uint32_t LAR;
1048 __IM uint32_t LSR;
1049 uint32_t RESERVED5[6U];
1050 __IM uint32_t PID4;
1051 __IM uint32_t PID5;
1052 __IM uint32_t PID6;
1053 __IM uint32_t PID7;
1054 __IM uint32_t PID0;
1055 __IM uint32_t PID1;
1056 __IM uint32_t PID2;
1057 __IM uint32_t PID3;
1058 __IM uint32_t CID0;
1059 __IM uint32_t CID1;
1060 __IM uint32_t CID2;
1061 __IM uint32_t CID3;
1062 } ITM_Type;
1063
1064 /* ITM Trace Privilege Register Definitions */
1065 #define ITM_TPR_PRIVMASK_Pos 0U
1066 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1068 /* ITM Trace Control Register Definitions */
1069 #define ITM_TCR_BUSY_Pos 23U
1070 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1072 #define ITM_TCR_TraceBusID_Pos 16U
1073 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
1075 #define ITM_TCR_GTSFREQ_Pos 10U
1076 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1078 #define ITM_TCR_TSPrescale_Pos 8U
1079 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
1081 #define ITM_TCR_SWOENA_Pos 4U
1082 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1084 #define ITM_TCR_DWTENA_Pos 3U
1085 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1087 #define ITM_TCR_SYNCENA_Pos 2U
1088 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1090 #define ITM_TCR_TSENA_Pos 1U
1091 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1093 #define ITM_TCR_ITMENA_Pos 0U
1094 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1096 /* ITM Lock Status Register Definitions */
1097 #define ITM_LSR_ByteAcc_Pos 2U
1098 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1100 #define ITM_LSR_Access_Pos 1U
1101 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1103 #define ITM_LSR_Present_Pos 0U
1104 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1106 /* end of group CMSIS_ITM */
1107
1108
1119 typedef struct
1120 {
1121 __IOM uint32_t CTRL;
1122 __IOM uint32_t CYCCNT;
1123 __IOM uint32_t CPICNT;
1124 __IOM uint32_t EXCCNT;
1125 __IOM uint32_t SLEEPCNT;
1126 __IOM uint32_t LSUCNT;
1127 __IOM uint32_t FOLDCNT;
1128 __IM uint32_t PCSR;
1129 __IOM uint32_t COMP0;
1130 __IOM uint32_t MASK0;
1131 __IOM uint32_t FUNCTION0;
1132 uint32_t RESERVED0[1U];
1133 __IOM uint32_t COMP1;
1134 __IOM uint32_t MASK1;
1135 __IOM uint32_t FUNCTION1;
1136 uint32_t RESERVED1[1U];
1137 __IOM uint32_t COMP2;
1138 __IOM uint32_t MASK2;
1139 __IOM uint32_t FUNCTION2;
1140 uint32_t RESERVED2[1U];
1141 __IOM uint32_t COMP3;
1142 __IOM uint32_t MASK3;
1143 __IOM uint32_t FUNCTION3;
1144 uint32_t RESERVED3[981U];
1145 __OM uint32_t LAR;
1146 __IM uint32_t LSR;
1147 } DWT_Type;
1148
1149 /* DWT Control Register Definitions */
1150 #define DWT_CTRL_NUMCOMP_Pos 28U
1151 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1153 #define DWT_CTRL_NOTRCPKT_Pos 27U
1154 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1156 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1157 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1159 #define DWT_CTRL_NOCYCCNT_Pos 25U
1160 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1162 #define DWT_CTRL_NOPRFCNT_Pos 24U
1163 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1165 #define DWT_CTRL_CYCEVTENA_Pos 22U
1166 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1168 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1169 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1171 #define DWT_CTRL_LSUEVTENA_Pos 20U
1172 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1174 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1175 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1177 #define DWT_CTRL_EXCEVTENA_Pos 18U
1178 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1180 #define DWT_CTRL_CPIEVTENA_Pos 17U
1181 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1183 #define DWT_CTRL_EXCTRCENA_Pos 16U
1184 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1186 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1187 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1189 #define DWT_CTRL_SYNCTAP_Pos 10U
1190 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1192 #define DWT_CTRL_CYCTAP_Pos 9U
1193 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1195 #define DWT_CTRL_POSTINIT_Pos 5U
1196 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1198 #define DWT_CTRL_POSTPRESET_Pos 1U
1199 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1201 #define DWT_CTRL_CYCCNTENA_Pos 0U
1202 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1204 /* DWT CPI Count Register Definitions */
1205 #define DWT_CPICNT_CPICNT_Pos 0U
1206 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1208 /* DWT Exception Overhead Count Register Definitions */
1209 #define DWT_EXCCNT_EXCCNT_Pos 0U
1210 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1212 /* DWT Sleep Count Register Definitions */
1213 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1214 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1216 /* DWT LSU Count Register Definitions */
1217 #define DWT_LSUCNT_LSUCNT_Pos 0U
1218 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1220 /* DWT Folded-instruction Count Register Definitions */
1221 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1222 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1224 /* DWT Comparator Mask Register Definitions */
1225 #define DWT_MASK_MASK_Pos 0U
1226 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
1228 /* DWT Comparator Function Register Definitions */
1229 #define DWT_FUNCTION_MATCHED_Pos 24U
1230 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1232 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
1233 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1235 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
1236 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1238 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1239 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1241 #define DWT_FUNCTION_LNK1ENA_Pos 9U
1242 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1244 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
1245 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1247 #define DWT_FUNCTION_CYCMATCH_Pos 7U
1248 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1250 #define DWT_FUNCTION_EMITRANGE_Pos 5U
1251 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1253 #define DWT_FUNCTION_FUNCTION_Pos 0U
1254 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
1256 /* end of group CMSIS_DWT */
1257
1258
1269 typedef struct
1270 {
1271 __IM uint32_t SSPSR;
1272 __IOM uint32_t CSPSR;
1273 uint32_t RESERVED0[2U];
1274 __IOM uint32_t ACPR;
1275 uint32_t RESERVED1[55U];
1276 __IOM uint32_t SPPR;
1277 uint32_t RESERVED2[131U];
1278 __IM uint32_t FFSR;
1279 __IOM uint32_t FFCR;
1280 __IM uint32_t FSCR;
1281 uint32_t RESERVED3[759U];
1282 __IM uint32_t TRIGGER;
1283 __IM uint32_t FIFO0;
1284 __IM uint32_t ITATBCTR2;
1285 uint32_t RESERVED4[1U];
1286 __IM uint32_t ITATBCTR0;
1287 __IM uint32_t FIFO1;
1288 __IOM uint32_t ITCTRL;
1289 uint32_t RESERVED5[39U];
1290 __IOM uint32_t CLAIMSET;
1291 __IOM uint32_t CLAIMCLR;
1292 uint32_t RESERVED7[8U];
1293 __IM uint32_t DEVID;
1294 __IM uint32_t DEVTYPE;
1295 } TPI_Type;
1296
1297 /* TPI Asynchronous Clock Prescaler Register Definitions */
1298 #define TPI_ACPR_PRESCALER_Pos 0U
1299 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1301 /* TPI Selected Pin Protocol Register Definitions */
1302 #define TPI_SPPR_TXMODE_Pos 0U
1303 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1305 /* TPI Formatter and Flush Status Register Definitions */
1306 #define TPI_FFSR_FtNonStop_Pos 3U
1307 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1309 #define TPI_FFSR_TCPresent_Pos 2U
1310 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1312 #define TPI_FFSR_FtStopped_Pos 1U
1313 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1315 #define TPI_FFSR_FlInProg_Pos 0U
1316 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1318 /* TPI Formatter and Flush Control Register Definitions */
1319 #define TPI_FFCR_TrigIn_Pos 8U
1320 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1322 #define TPI_FFCR_EnFCont_Pos 1U
1323 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1325 /* TPI TRIGGER Register Definitions */
1326 #define TPI_TRIGGER_TRIGGER_Pos 0U
1327 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1329 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1330 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1331 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
1333 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1334 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1336 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1337 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
1339 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1340 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1342 #define TPI_FIFO0_ETM2_Pos 16U
1343 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1345 #define TPI_FIFO0_ETM1_Pos 8U
1346 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1348 #define TPI_FIFO0_ETM0_Pos 0U
1349 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1351 /* TPI ITATBCTR2 Register Definitions */
1352 #define TPI_ITATBCTR2_ATREADY2_Pos 0U
1353 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
1355 #define TPI_ITATBCTR2_ATREADY1_Pos 0U
1356 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
1358 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1359 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1360 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
1362 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1363 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1365 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1366 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
1368 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1369 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1371 #define TPI_FIFO1_ITM2_Pos 16U
1372 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1374 #define TPI_FIFO1_ITM1_Pos 8U
1375 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1377 #define TPI_FIFO1_ITM0_Pos 0U
1378 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1380 /* TPI ITATBCTR0 Register Definitions */
1381 #define TPI_ITATBCTR0_ATREADY2_Pos 0U
1382 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
1384 #define TPI_ITATBCTR0_ATREADY1_Pos 0U
1385 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
1387 /* TPI Integration Mode Control Register Definitions */
1388 #define TPI_ITCTRL_Mode_Pos 0U
1389 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1391 /* TPI DEVID Register Definitions */
1392 #define TPI_DEVID_NRZVALID_Pos 11U
1393 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1395 #define TPI_DEVID_MANCVALID_Pos 10U
1396 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1398 #define TPI_DEVID_PTINVALID_Pos 9U
1399 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1401 #define TPI_DEVID_MinBufSz_Pos 6U
1402 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1404 #define TPI_DEVID_AsynClkIn_Pos 5U
1405 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1407 #define TPI_DEVID_NrTraceInput_Pos 0U
1408 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1410 /* TPI DEVTYPE Register Definitions */
1411 #define TPI_DEVTYPE_SubType_Pos 4U
1412 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1414 #define TPI_DEVTYPE_MajorType_Pos 0U
1415 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1417 /* end of group CMSIS_TPI */
1418
1419
1420 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1421
1431 typedef struct
1432 {
1433 __IM uint32_t TYPE;
1434 __IOM uint32_t CTRL;
1435 __IOM uint32_t RNR;
1436 __IOM uint32_t RBAR;
1437 __IOM uint32_t RASR;
1438 __IOM uint32_t RBAR_A1;
1439 __IOM uint32_t RASR_A1;
1440 __IOM uint32_t RBAR_A2;
1441 __IOM uint32_t RASR_A2;
1442 __IOM uint32_t RBAR_A3;
1443 __IOM uint32_t RASR_A3;
1444 } MPU_Type;
1445
1446 #define MPU_TYPE_RALIASES 4U
1447
1448 /* MPU Type Register Definitions */
1449 #define MPU_TYPE_IREGION_Pos 16U
1450 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1452 #define MPU_TYPE_DREGION_Pos 8U
1453 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1455 #define MPU_TYPE_SEPARATE_Pos 0U
1456 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1458 /* MPU Control Register Definitions */
1459 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1460 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1462 #define MPU_CTRL_HFNMIENA_Pos 1U
1463 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1465 #define MPU_CTRL_ENABLE_Pos 0U
1466 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1468 /* MPU Region Number Register Definitions */
1469 #define MPU_RNR_REGION_Pos 0U
1470 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1472 /* MPU Region Base Address Register Definitions */
1473 #define MPU_RBAR_ADDR_Pos 5U
1474 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1476 #define MPU_RBAR_VALID_Pos 4U
1477 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1479 #define MPU_RBAR_REGION_Pos 0U
1480 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1482 /* MPU Region Attribute and Size Register Definitions */
1483 #define MPU_RASR_ATTRS_Pos 16U
1484 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1486 #define MPU_RASR_XN_Pos 28U
1487 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1489 #define MPU_RASR_AP_Pos 24U
1490 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1492 #define MPU_RASR_TEX_Pos 19U
1493 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1495 #define MPU_RASR_S_Pos 18U
1496 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1498 #define MPU_RASR_C_Pos 17U
1499 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1501 #define MPU_RASR_B_Pos 16U
1502 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1504 #define MPU_RASR_SRD_Pos 8U
1505 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1507 #define MPU_RASR_SIZE_Pos 1U
1508 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1510 #define MPU_RASR_ENABLE_Pos 0U
1511 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1513
1514 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1515
1516
1527 typedef struct
1528 {
1529 uint32_t RESERVED0[1U];
1530 __IOM uint32_t FPCCR;
1531 __IOM uint32_t FPCAR;
1532 __IOM uint32_t FPDSCR;
1533 __IM uint32_t MVFR0;
1534 __IM uint32_t MVFR1;
1535 __IM uint32_t MVFR2;
1536 } FPU_Type;
1537
1538 /* Floating-Point Context Control Register Definitions */
1539 #define FPU_FPCCR_ASPEN_Pos 31U
1540 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1542 #define FPU_FPCCR_LSPEN_Pos 30U
1543 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1545 #define FPU_FPCCR_MONRDY_Pos 8U
1546 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1548 #define FPU_FPCCR_BFRDY_Pos 6U
1549 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1551 #define FPU_FPCCR_MMRDY_Pos 5U
1552 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1554 #define FPU_FPCCR_HFRDY_Pos 4U
1555 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1557 #define FPU_FPCCR_THREAD_Pos 3U
1558 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1560 #define FPU_FPCCR_USER_Pos 1U
1561 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1563 #define FPU_FPCCR_LSPACT_Pos 0U
1564 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1566 /* Floating-Point Context Address Register Definitions */
1567 #define FPU_FPCAR_ADDRESS_Pos 3U
1568 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1570 /* Floating-Point Default Status Control Register Definitions */
1571 #define FPU_FPDSCR_AHP_Pos 26U
1572 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1574 #define FPU_FPDSCR_DN_Pos 25U
1575 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1577 #define FPU_FPDSCR_FZ_Pos 24U
1578 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1580 #define FPU_FPDSCR_RMode_Pos 22U
1581 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1583 /* Media and FP Feature Register 0 Definitions */
1584 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1585 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1587 #define FPU_MVFR0_Short_vectors_Pos 24U
1588 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1590 #define FPU_MVFR0_Square_root_Pos 20U
1591 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1593 #define FPU_MVFR0_Divide_Pos 16U
1594 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1596 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1597 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1599 #define FPU_MVFR0_Double_precision_Pos 8U
1600 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1602 #define FPU_MVFR0_Single_precision_Pos 4U
1603 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1605 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1606 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1608 /* Media and FP Feature Register 1 Definitions */
1609 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1610 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1612 #define FPU_MVFR1_FP_HPFP_Pos 24U
1613 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1615 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1616 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1618 #define FPU_MVFR1_FtZ_mode_Pos 0U
1619 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1621 /* Media and FP Feature Register 2 Definitions */
1622
1623 #define FPU_MVFR2_VFP_Misc_Pos 4U
1624 #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
1626
1639 typedef struct
1640 {
1641 __IOM uint32_t DHCSR;
1642 __OM uint32_t DCRSR;
1643 __IOM uint32_t DCRDR;
1644 __IOM uint32_t DEMCR;
1645 } CoreDebug_Type;
1646
1647 /* Debug Halting Control and Status Register Definitions */
1648 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1649 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1651 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1652 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1654 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1655 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1657 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1658 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1660 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1661 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1663 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1664 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1666 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1667 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1669 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1670 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1672 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1673 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1675 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1676 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1678 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1679 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1681 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1682 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1684 /* Debug Core Register Selector Register Definitions */
1685 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1686 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1688 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1689 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1691 /* Debug Exception and Monitor Control Register Definitions */
1692 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1693 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1695 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1696 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1698 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1699 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1701 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1702 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1704 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1705 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1707 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1708 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1710 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1711 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1713 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1714 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1716 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1717 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1719 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1720 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1722 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1723 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1725 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1726 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1728 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1729 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1731
1747 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1748
1755 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1756
1767 /* Memory mapping of Core Hardware */
1768 #define SCS_BASE (0xE000E000UL)
1769 #define ITM_BASE (0xE0000000UL)
1770 #define DWT_BASE (0xE0001000UL)
1771 #define TPI_BASE (0xE0040000UL)
1772 #define CoreDebug_BASE (0xE000EDF0UL)
1773 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1774 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1775 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1777 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1778 #define SCB ((SCB_Type *) SCB_BASE )
1779 #define SysTick ((SysTick_Type *) SysTick_BASE )
1780 #define NVIC ((NVIC_Type *) NVIC_BASE )
1781 #define ITM ((ITM_Type *) ITM_BASE )
1782 #define DWT ((DWT_Type *) DWT_BASE )
1783 #define TPI ((TPI_Type *) TPI_BASE )
1784 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1786 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1787 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1788 #define MPU ((MPU_Type *) MPU_BASE )
1789 #endif
1790
1791 #define FPU_BASE (SCS_BASE + 0x0F30UL)
1792 #define FPU ((FPU_Type *) FPU_BASE )
1794
1798 /*******************************************************************************
1799 * Hardware Abstraction Layer
1800 Core Function Interface contains:
1801 - Core NVIC Functions
1802 - Core SysTick Functions
1803 - Core Debug Functions
1804 - Core Register Access Functions
1805 ******************************************************************************/
1806
1812 /* ########################## NVIC functions #################################### */
1820 #ifdef CMSIS_NVIC_VIRTUAL
1821 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1822 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1823 #endif
1824 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1825 #else
1826 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1827 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1828 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1829 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1830 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1831 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1832 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1833 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1834 #define NVIC_GetActive __NVIC_GetActive
1835 #define NVIC_SetPriority __NVIC_SetPriority
1836 #define NVIC_GetPriority __NVIC_GetPriority
1837 #define NVIC_SystemReset __NVIC_SystemReset
1838 #endif /* CMSIS_NVIC_VIRTUAL */
1839
1840 #ifdef CMSIS_VECTAB_VIRTUAL
1841 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1842 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1843 #endif
1844 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1845 #else
1846 #define NVIC_SetVector __NVIC_SetVector
1847 #define NVIC_GetVector __NVIC_GetVector
1848 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1849
1850 #define NVIC_USER_IRQ_OFFSET 16
1851
1852
1853 /* The following EXC_RETURN values are saved the LR on exception entry */
1854 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1855 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1856 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1857 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1858 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1859 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1860
1861
1871 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1872 {
1873 uint32_t reg_value;
1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1875
1876 reg_value = SCB->AIRCR; /* read old register configuration */
1877 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1878 reg_value = (reg_value |
1879 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1880 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1881 SCB->AIRCR = reg_value;
1882 }
1883
1884
1890 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1891 {
1892 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1893 }
1894
1895
1902 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1903 {
1904 if ((int32_t)(IRQn) >= 0)
1905 {
1906 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1907 }
1908 }
1909
1910
1919 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1920 {
1921 if ((int32_t)(IRQn) >= 0)
1922 {
1923 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1924 }
1925 else
1926 {
1927 return(0U);
1928 }
1929 }
1930
1931
1938 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1939 {
1940 if ((int32_t)(IRQn) >= 0)
1941 {
1942 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1943 __DSB();
1944 __ISB();
1945 }
1946 }
1947
1948
1957 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1958 {
1959 if ((int32_t)(IRQn) >= 0)
1960 {
1961 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1962 }
1963 else
1964 {
1965 return(0U);
1966 }
1967 }
1968
1969
1976 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1977 {
1978 if ((int32_t)(IRQn) >= 0)
1979 {
1980 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1981 }
1982 }
1983
1984
1991 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1992 {
1993 if ((int32_t)(IRQn) >= 0)
1994 {
1995 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1996 }
1997 }
1998
1999
2008 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2009 {
2010 if ((int32_t)(IRQn) >= 0)
2011 {
2012 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2013 }
2014 else
2015 {
2016 return(0U);
2017 }
2018 }
2019
2020
2030 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2031 {
2032 if ((int32_t)(IRQn) >= 0)
2033 {
2034 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2035 }
2036 else
2037 {
2038 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2039 }
2040 }
2041
2042
2052 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2053 {
2054
2055 if ((int32_t)(IRQn) >= 0)
2056 {
2057 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2058 }
2059 else
2060 {
2061 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2062 }
2063 }
2064
2065
2077 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2078 {
2079 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2080 uint32_t PreemptPriorityBits;
2081 uint32_t SubPriorityBits;
2082
2083 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2084 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2085
2086 return (
2087 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2088 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2089 );
2090 }
2091
2092
2104 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2105 {
2106 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2107 uint32_t PreemptPriorityBits;
2108 uint32_t SubPriorityBits;
2109
2110 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2111 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2112
2113 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2114 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2115 }
2116
2117
2127 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2128 {
2129 uint32_t vectors = (uint32_t )SCB->VTOR;
2130 (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
2131 }
2132
2133
2142 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2143 {
2144 uint32_t vectors = (uint32_t )SCB->VTOR;
2145 return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
2146 }
2147
2148
2153 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2154 {
2155 __DSB(); /* Ensure all outstanding memory accesses included
2156 buffered write are completed before reset */
2157 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2158 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2159 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2160 __DSB(); /* Ensure completion of memory access */
2161
2162 for(;;) /* wait until reset */
2163 {
2164 __NOP();
2165 }
2166 }
2167
2171 /* ########################## MPU functions #################################### */
2172
2173 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2174
2175 #include "mpu_armv7.h"
2176
2177 #endif
2178
2179
2180 /* ########################## FPU functions #################################### */
2196 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2197 {
2198 uint32_t mvfr0;
2199
2200 mvfr0 = SCB->MVFR0;
2201 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2202 {
2203 return 2U; /* Double + Single precision FPU */
2204 }
2205 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2206 {
2207 return 1U; /* Single precision FPU */
2208 }
2209 else
2210 {
2211 return 0U; /* No FPU */
2212 }
2213 }
2214
2219 /* ########################## Cache functions #################################### */
2227 /* Cache Size ID Register Macros */
2228 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
2229 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
2230
2231 #define __SCB_DCACHE_LINE_SIZE 32U
2237 __STATIC_FORCEINLINE void SCB_EnableICache (void)
2238 {
2239 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
2240 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
2241
2242 __DSB();
2243 __ISB();
2244 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
2245 __DSB();
2246 __ISB();
2247 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
2248 __DSB();
2249 __ISB();
2250 #endif
2251 }
2252
2253
2258 __STATIC_FORCEINLINE void SCB_DisableICache (void)
2259 {
2260 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
2261 __DSB();
2262 __ISB();
2263 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
2264 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
2265 __DSB();
2266 __ISB();
2267 #endif
2268 }
2269
2270
2275 __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
2276 {
2277 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
2278 __DSB();
2279 __ISB();
2280 SCB->ICIALLU = 0UL;
2281 __DSB();
2282 __ISB();
2283 #endif
2284 }
2285
2286
2291 __STATIC_FORCEINLINE void SCB_EnableDCache (void)
2292 {
2293 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2294 uint32_t ccsidr;
2295 uint32_t sets;
2296 uint32_t ways;
2297
2298 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
2299
2300 SCB->CSSELR = 0U; /* select Level 1 data cache */
2301 __DSB();
2302
2303 ccsidr = SCB->CCSIDR;
2304
2305 /* invalidate D-Cache */
2306 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2307 do {
2308 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2309 do {
2310 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
2311 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
2312 #if defined ( __CC_ARM )
2313 __schedule_barrier();
2314 #endif
2315 } while (ways-- != 0U);
2316 } while(sets-- != 0U);
2317 __DSB();
2318
2319 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
2320
2321 __DSB();
2322 __ISB();
2323 #endif
2324 }
2325
2326
2331 __STATIC_FORCEINLINE void SCB_DisableDCache (void)
2332 {
2333 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2334 register uint32_t ccsidr;
2335 register uint32_t sets;
2336 register uint32_t ways;
2337
2338 SCB->CSSELR = 0U; /* select Level 1 data cache */
2339 __DSB();
2340
2341 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
2342 __DSB();
2343
2344 ccsidr = SCB->CCSIDR;
2345
2346 /* clean & invalidate D-Cache */
2347 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2348 do {
2349 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2350 do {
2351 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
2352 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
2353 #if defined ( __CC_ARM )
2354 __schedule_barrier();
2355 #endif
2356 } while (ways-- != 0U);
2357 } while(sets-- != 0U);
2358
2359 __DSB();
2360 __ISB();
2361 #endif
2362 }
2363
2364
2369 __STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
2370 {
2371 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2372 uint32_t ccsidr;
2373 uint32_t sets;
2374 uint32_t ways;
2375
2376 SCB->CSSELR = 0U; /* select Level 1 data cache */
2377 __DSB();
2378
2379 ccsidr = SCB->CCSIDR;
2380
2381 /* invalidate D-Cache */
2382 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2383 do {
2384 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2385 do {
2386 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
2387 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
2388 #if defined ( __CC_ARM )
2389 __schedule_barrier();
2390 #endif
2391 } while (ways-- != 0U);
2392 } while(sets-- != 0U);
2393
2394 __DSB();
2395 __ISB();
2396 #endif
2397 }
2398
2399
2404 __STATIC_FORCEINLINE void SCB_CleanDCache (void)
2405 {
2406 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2407 uint32_t ccsidr;
2408 uint32_t sets;
2409 uint32_t ways;
2410
2411 SCB->CSSELR = 0U; /* select Level 1 data cache */
2412 __DSB();
2413
2414 ccsidr = SCB->CCSIDR;
2415
2416 /* clean D-Cache */
2417 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2418 do {
2419 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2420 do {
2421 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
2422 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
2423 #if defined ( __CC_ARM )
2424 __schedule_barrier();
2425 #endif
2426 } while (ways-- != 0U);
2427 } while(sets-- != 0U);
2428
2429 __DSB();
2430 __ISB();
2431 #endif
2432 }
2433
2434
2439 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
2440 {
2441 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2442 uint32_t ccsidr;
2443 uint32_t sets;
2444 uint32_t ways;
2445
2446 SCB->CSSELR = 0U; /* select Level 1 data cache */
2447 __DSB();
2448
2449 ccsidr = SCB->CCSIDR;
2450
2451 /* clean & invalidate D-Cache */
2452 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2453 do {
2454 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2455 do {
2456 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
2457 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
2458 #if defined ( __CC_ARM )
2459 __schedule_barrier();
2460 #endif
2461 } while (ways-- != 0U);
2462 } while(sets-- != 0U);
2463
2464 __DSB();
2465 __ISB();
2466 #endif
2467 }
2468
2469
2478 __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
2479 {
2480 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2481 if ( dsize > 0 ) {
2482 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
2483 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2484
2485 __DSB();
2486
2487 do {
2488 SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
2489 op_addr += __SCB_DCACHE_LINE_SIZE;
2490 op_size -= __SCB_DCACHE_LINE_SIZE;
2491 } while ( op_size > 0 );
2492
2493 __DSB();
2494 __ISB();
2495 }
2496 #endif
2497 }
2498
2499
2508 __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
2509 {
2510 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2511 if ( dsize > 0 ) {
2512 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
2513 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2514
2515 __DSB();
2516
2517 do {
2518 SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
2519 op_addr += __SCB_DCACHE_LINE_SIZE;
2520 op_size -= __SCB_DCACHE_LINE_SIZE;
2521 } while ( op_size > 0 );
2522
2523 __DSB();
2524 __ISB();
2525 }
2526 #endif
2527 }
2528
2529
2538 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2539 {
2540 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2541 if ( dsize > 0 ) {
2542 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
2543 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2544
2545 __DSB();
2546
2547 do {
2548 SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
2549 op_addr += __SCB_DCACHE_LINE_SIZE;
2550 op_size -= __SCB_DCACHE_LINE_SIZE;
2551 } while ( op_size > 0 );
2552
2553 __DSB();
2554 __ISB();
2555 }
2556 #endif
2557 }
2558
2563 /* ################################## SysTick function ############################################ */
2571 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2572
2584 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2585 {
2586 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2587 {
2588 return (1UL); /* Reload value impossible */
2589 }
2590
2591 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2592 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2593 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2594 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2595 SysTick_CTRL_TICKINT_Msk |
2596 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2597 return (0UL); /* Function successful */
2598 }
2599
2600 #endif
2601
2606 /* ##################################### Debug In/Output function ########################################### */
2614 extern volatile int32_t ITM_RxBuffer;
2615 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2626 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2627 {
2628 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2629 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2630 {
2631 while (ITM->PORT[0U].u32 == 0UL)
2632 {
2633 __NOP();
2634 }
2635 ITM->PORT[0U].u8 = (uint8_t)ch;
2636 }
2637 return (ch);
2638 }
2639
2640
2647 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2648 {
2649 int32_t ch = -1; /* no character available */
2650
2651 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2652 {
2653 ch = ITM_RxBuffer;
2654 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2655 }
2656
2657 return (ch);
2658 }
2659
2660
2667 __STATIC_INLINE int32_t ITM_CheckChar (void)
2668 {
2669
2670 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2671 {
2672 return (0); /* no character available */
2673 }
2674 else
2675 {
2676 return (1); /* character available */
2677 }
2678 }
2679
2685 #ifdef __cplusplus
2686 }
2687 #endif
2688
2689 #endif /* __CORE_CM7_H_DEPENDANT */
2690
2691 #endif /* __CMSIS_GENERIC */
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1034
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1062.h:268
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv81mml.h:2173
NVIC
#define NVIC
Definition: core_cm7.h:1778
SCB_DisableDCache
__STATIC_FORCEINLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: core_cm7.h:2328
SCB_DCISW_SET_Msk
#define SCB_DCISW_SET_Msk
Definition: core_cm7.h:818
SCB_DCISW_SET_Pos
#define SCB_DCISW_SET_Pos
Definition: core_cm7.h:817
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:2259
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv81mml.h:2154
SCB_EnableDCache
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: core_cm7.h:2288
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:2380
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:2274
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:2746
SCB_DCCISW_WAY_Pos
#define SCB_DCCISW_WAY_Pos
Definition: core_cm7.h:828
mpu_armv7.h
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:371
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm7.h:2612
SCB_DCCISW_SET_Msk
#define SCB_DCCISW_SET_Msk
Definition: core_cm7.h:832
SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition: core_cm7.h:598
SCB_InvalidateICache
__STATIC_FORCEINLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: core_cm7.h:2272
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866
SysTick_IRQn
Definition: MIMXRT1062.h:87
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_cm7.h:1832
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:2185
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1387
SCB_DisableICache
__STATIC_FORCEINLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: core_cm7.h:2255
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv81mml.h:1086
SCB_DCISW_WAY_Pos
#define SCB_DCISW_WAY_Pos
Definition: core_cm7.h:814
SysTick
#define SysTick
Definition: core_cm7.h:1777
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_armv81mml.h:1745
CCSIDR_WAYS
#define CCSIDR_WAYS(x)
Definition: core_cm7.h:2225
SCB_DCCSW_SET_Pos
#define SCB_DCCSW_SET_Pos
Definition: core_cm7.h:824
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:497
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm7.h:993
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:2291
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv81mml.h:2941
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:2477
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm7.h:569
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:2427
SCB_DCCSW_WAY_Pos
#define SCB_DCCSW_WAY_Pos
Definition: core_cm7.h:821
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv81mml.h:1009
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:391
IRQn
IRQn
Definition: MIMXRT1062.h:74
__IOM
#define __IOM
Definition: core_cm7.h:241
IRQn_Type
enum IRQn IRQn_Type
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:353
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm7.h:1000
cmsis_version.h
CMSIS Core(M) Version definitions.
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv81mml.h:2921
SCB_DCCSW_WAY_Msk
#define SCB_DCCSW_WAY_Msk
Definition: core_cm7.h:822
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:2221
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm7.h:1092
SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition: core_cm7.h:595
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:2503
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: core_cm7.h:1601
SCB_DCISW_WAY_Msk
#define SCB_DCISW_WAY_Msk
Definition: core_cm7.h:815
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:2492
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm7.h:568
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:422
SCB_CleanDCache_by_Addr
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean by address.
Definition: core_cm7.h:2505
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:63
SCB_InvalidateDCache
__STATIC_FORCEINLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: core_cm7.h:2366
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:2240
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm7.h:572
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:2402
CCSIDR_SETS
#define CCSIDR_SETS(x)
Definition: core_cm7.h:2226
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm7.h:560
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm7.h:996
__IM
#define __IM
Definition: core_cm7.h:239
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_armv81mml.h:1875
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:461
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:2202
SCB_CleanInvalidateDCache_by_Addr
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition: core_cm7.h:2535
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_armcc.h:69
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: core_cm7.h:1598
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:314
SCB_CleanDCache
__STATIC_FORCEINLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: core_cm7.h:2401
SCB_DCCISW_WAY_Msk
#define SCB_DCCISW_WAY_Msk
Definition: core_cm7.h:829
cmsis_compiler.h
CMSIS compiler generic header file.
SCB_CleanInvalidateDCache
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: core_cm7.h:2436
__SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE
Definition: core_cm7.h:2228
SCB_InvalidateDCache_by_Addr
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr(void *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition: core_cm7.h:2475
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm7.h:990
SCB_DCCISW_SET_Pos
#define SCB_DCCISW_SET_Pos
Definition: core_cm7.h:831
__STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE
Definition: cmsis_armcc.h:66
SCB_DCCSW_SET_Msk
#define SCB_DCCSW_SET_Msk
Definition: core_cm7.h:825
ITM
#define ITM
Definition: core_cm7.h:1779
SCB
#define SCB
Definition: core_cm7.h:1776
__OM
#define __OM
Definition: core_cm7.h:240
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:2454
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_cm7.h:1847
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm7.h:559
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1201