Callisto4Bootloader: board/board.c Source File

Callisto4Bootloader

board.c
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1 /*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12 #include "fsl_lpi2c.h"
13 #endif /* SDK_I2C_BASED_COMPONENT_USED */
14 #include "fsl_iomuxc.h"
15
16 /*******************************************************************************
17 * Variables
18 ******************************************************************************/
19 /*******************************************************************************
20 * Code
21 ******************************************************************************/
22
23 /* Get debug console frequency. */
24 uint32_t BOARD_DebugConsoleSrcFreq(void)
25 {
26 uint32_t freq;
27
28 /* To make it simple, we assume default PLL and divider settings, and the only variable
29 from application is use PLL3 source or OSC source */
30 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
31 {
32 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
33 }
34 else
35 {
36 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
37 }
38
39 return freq;
40 }
41
42 /* Initialize debug console. */
43 void BOARD_InitDebugConsole(void)
44 {
45 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
46
47 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
48 }
49
50 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
51 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
52 {
53 lpi2c_master_config_t lpi2cConfig = {0};
54
55 /*
56 * lpi2cConfig.debugEnable = false;
57 * lpi2cConfig.ignoreAck = false;
58 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
59 * lpi2cConfig.baudRate_Hz = 100000U;
60 * lpi2cConfig.busIdleTimeout_ns = 0;
61 * lpi2cConfig.pinLowTimeout_ns = 0;
62 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
63 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
64 */
65 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
66 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
67 }
68
69 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
70 uint8_t deviceAddress,
71 uint32_t subAddress,
72 uint8_t subAddressSize,
73 uint8_t *txBuff,
74 uint8_t txBuffSize)
75 {
76 lpi2c_master_transfer_t xfer;
77
78 xfer.flags = kLPI2C_TransferDefaultFlag;
79 xfer.slaveAddress = deviceAddress;
80 xfer.direction = kLPI2C_Write;
81 xfer.subaddress = subAddress;
82 xfer.subaddressSize = subAddressSize;
83 xfer.data = txBuff;
84 xfer.dataSize = txBuffSize;
85
86 return LPI2C_MasterTransferBlocking(base, &xfer);
87 }
88
89 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
90 uint8_t deviceAddress,
91 uint32_t subAddress,
92 uint8_t subAddressSize,
93 uint8_t *rxBuff,
94 uint8_t rxBuffSize)
95 {
96 lpi2c_master_transfer_t xfer;
97
98 xfer.flags = kLPI2C_TransferDefaultFlag;
99 xfer.slaveAddress = deviceAddress;
100 xfer.direction = kLPI2C_Read;
101 xfer.subaddress = subAddress;
102 xfer.subaddressSize = subAddressSize;
103 xfer.data = rxBuff;
104 xfer.dataSize = rxBuffSize;
105
106 return LPI2C_MasterTransferBlocking(base, &xfer);
107 }
108
109 status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
110 uint8_t deviceAddress,
111 uint32_t subAddress,
112 uint8_t subAddressSize,
113 uint8_t *txBuff,
114 uint8_t txBuffSize)
115 {
116 lpi2c_master_transfer_t xfer;
117
118 xfer.flags = kLPI2C_TransferDefaultFlag;
119 xfer.slaveAddress = deviceAddress;
120 xfer.direction = kLPI2C_Write;
121 xfer.subaddress = subAddress;
122 xfer.subaddressSize = subAddressSize;
123 xfer.data = txBuff;
124 xfer.dataSize = txBuffSize;
125
126 return LPI2C_MasterTransferBlocking(base, &xfer);
127 }
128
129 status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
130 uint8_t deviceAddress,
131 uint32_t subAddress,
132 uint8_t subAddressSize,
133 uint8_t *rxBuff,
134 uint8_t rxBuffSize)
135 {
136 status_t status;
137 lpi2c_master_transfer_t xfer;
138
139 xfer.flags = kLPI2C_TransferDefaultFlag;
140 xfer.slaveAddress = deviceAddress;
141 xfer.direction = kLPI2C_Write;
142 xfer.subaddress = subAddress;
143 xfer.subaddressSize = subAddressSize;
144 xfer.data = NULL;
145 xfer.dataSize = 0;
146
147 status = LPI2C_MasterTransferBlocking(base, &xfer);
148
149 if (kStatus_Success == status)
150 {
151 xfer.subaddressSize = 0;
152 xfer.direction = kLPI2C_Read;
153 xfer.data = rxBuff;
154 xfer.dataSize = rxBuffSize;
155
156 status = LPI2C_MasterTransferBlocking(base, &xfer);
157 }
158
159 return status;
160 }
161
162 void BOARD_Accel_I2C_Init(void)
163 {
164 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
165 }
166
167 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
168 {
169 uint8_t data = (uint8_t)txBuff;
170
171 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
172 }
173
174 status_t BOARD_Accel_I2C_Receive(
175 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
176 {
177 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
178 }
179
180 void BOARD_Codec_I2C_Init(void)
181 {
182 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
183 }
184
185 status_t BOARD_Codec_I2C_Send(
186 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
187 {
188 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
189 txBuffSize);
190 }
191
192 status_t BOARD_Codec_I2C_Receive(
193 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
194 {
195 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
196 }
197
198 void BOARD_Camera_I2C_Init(void)
199 {
200 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
201 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
202 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
203 }
204
205 status_t BOARD_Camera_I2C_Send(
206 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
207 {
208 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
209 txBuffSize);
210 }
211
212 status_t BOARD_Camera_I2C_Receive(
213 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
214 {
215 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
216 rxBuffSize);
217 }
218
219 status_t BOARD_Camera_I2C_SendSCCB(
220 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
221 {
222 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
223 txBuffSize);
224 }
225
226 status_t BOARD_Camera_I2C_ReceiveSCCB(
227 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
228 {
229 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
230 rxBuffSize);
231 }
232 #endif /* SDK_I2C_BASED_COMPONENT_USED */
233
234 /* MPU configuration. */
235 void BOARD_ConfigMPU(void)
236 {
237 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
238 extern uint32_t Image$$RW_m_ncache$$Base[];
239 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
240 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
241 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
242 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
243 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
244 0 :
245 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
246 #elif defined(__MCUXPRESSO)
247 extern uint32_t __base_NCACHE_REGION;
248 extern uint32_t __top_NCACHE_REGION;
249 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
250 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
251 #elif defined(__ICCARM__) || defined(__GNUC__)
252 extern uint32_t __NCACHE_REGION_START[];
253 extern uint32_t __NCACHE_REGION_SIZE[];
254 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
255 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
256 #endif
257 uint32_t i = 0;
258
259 /* Disable I cache and D cache */
260 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
261 {
262 SCB_DisableICache();
263 }
264 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
265 {
266 SCB_DisableDCache();
267 }
268
269 /* Disable MPU */
270 ARM_MPU_Disable();
271
272 /* MPU configure:
273 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
274 * SubRegionDisable, Size)
275 * API in mpu_armv7.h.
276 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
277 * disabled.
278 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
279 * Privileged mode.
280 * Use MACROS defined in mpu_armv7.h:
281 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
282 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
283 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
284 * 0 x 0 0 Strongly Ordered shareable
285 * 0 x 0 1 Device shareable
286 * 0 0 1 0 Normal not shareable Outer and inner write
287 * through no write allocate
288 * 0 0 1 1 Normal not shareable Outer and inner write
289 * back no write allocate
290 * 0 1 1 0 Normal shareable Outer and inner write
291 * through no write allocate
292 * 0 1 1 1 Normal shareable Outer and inner write
293 * back no write allocate
294 * 1 0 0 0 Normal not shareable outer and inner
295 * noncache
296 * 1 1 0 0 Normal shareable outer and inner
297 * noncache
298 * 1 0 1 1 Normal not shareable outer and inner write
299 * back write/read acllocate
300 * 1 1 1 1 Normal shareable outer and inner write
301 * back write/read acllocate
302 * 2 x 0 0 Device not shareable
303 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
304 * policy.
305 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
306 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
307 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
308 * mpu_armv7.h.
309 */
310
311 /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
312 MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
313 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
314
315 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
316 MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
317 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
318
319 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
320 /* Region 2 setting: Memory with Normal type, not shareable, outer/inner write back. */
321 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
322 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
323 #endif
324
325 /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
326 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
327 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
328
329 /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
330 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
331 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
332
333 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
334 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
335 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
336
337 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
338 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
339 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
340
341 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
342 MPU->RBAR = ARM_MPU_RBAR(7, 0x20280000U);
343 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
344
345 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
346 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
347 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
348
349 while ((size >> i) > 0x1U)
350 {
351 i++;
352 }
353
354 if (i != 0)
355 {
356 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
357 assert(!(nonCacheStart % size));
358 assert(size == (uint32_t)(1 << i));
359 assert(i >= 5);
360
361 /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
362 MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
363 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
364 }
365
366 /* Enable MPU */
367 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
368
369 /* Enable I cache and D cache */
370 SCB_EnableDCache();
371 SCB_EnableICache();
372 }
373
374 void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
375 {
376 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
377 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
378 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
379 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
380 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
381 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
382 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
383 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
384 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
385 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
386 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
387 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
388 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
389 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
390 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
391 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
392 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
393 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
394 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
395 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
396 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
397 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
398 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
399 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
400 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
401 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
402 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
403 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
404 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
405 }
406
407 void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
408 {
409 }
NULL
#define NULL
Definition: bootloader_common.h:26
ARM_MPU_REGION_SIZE_256KB
#define ARM_MPU_REGION_SIZE_256KB
Definition: mpu_armv7.h:46
BOARD_InitDebugConsole
void BOARD_InitDebugConsole(void)
Definition: board.c:41
SCB_DisableDCache
__STATIC_FORCEINLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: core_cm7.h:2328
IOMUXC_SW_PAD_CTL_PAD_SPEED
#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x)
Definition: MIMXRT1062.h:21992
LPI2C_Type
Definition: MIMXRT1062.h:26674
ARM_MPU_REGION_SIZE_128KB
#define ARM_MPU_REGION_SIZE_128KB
Definition: mpu_armv7.h:45
SCB_EnableDCache
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: core_cm7.h:2288
BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER
Definition: board.h:211
SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition: core_armv81mml.h:660
SCB_DisableICache
__STATIC_FORCEINLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: core_cm7.h:2255
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK
#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK
Definition: MIMXRT1062.h:22007
i
volatile int i
Definition: excep_test.c:17
ARM_MPU_Enable
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Definition: mpu_armv7.h:190
BOARD_ACCEL_I2C_CLOCK_FREQ
#define BOARD_ACCEL_I2C_CLOCK_FREQ
Definition: board.h:201
ARM_MPU_Disable
__STATIC_INLINE void ARM_MPU_Disable(void)
Definition: mpu_armv7.h:202
BOARD_MMC_Pin_Config
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
Definition: board.c:405
BOARD_CODEC_I2C_CLOCK_FREQ
#define BOARD_CODEC_I2C_CLOCK_FREQ
Definition: board.h:207
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK
#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK
Definition: MIMXRT1062.h:22000
ARM_MPU_AP_FULL
#define ARM_MPU_AP_FULL
Definition: mpu_armv7.h:65
BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT
Definition: board.h:212
IOMUXC_SW_PAD_CTL_PAD_PUS
#define IOMUXC_SW_PAD_CTL_PAD_PUS(x)
Definition: MIMXRT1062.h:22022
ARM_MPU_RBAR
#define ARM_MPU_RBAR(Region, BaseAddress)
Definition: mpu_armv7.h:74
BOARD_ACCEL_I2C_BASEADDR
#define BOARD_ACCEL_I2C_BASEADDR
Definition: board.h:196
BOARD_CAMERA_I2C_BASEADDR
#define BOARD_CAMERA_I2C_BASEADDR
Definition: board.h:210
SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition: core_armv81mml.h:657
BOARD_SD_Pin_Config
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
Definition: board.c:372
BOARD_DEBUG_UART_INSTANCE
#define BOARD_DEBUG_UART_INSTANCE
Definition: board.h:24
BOARD_CODEC_I2C_BASEADDR
#define BOARD_CODEC_I2C_BASEADDR
Definition: board.h:203
ARM_MPU_REGION_SIZE_32MB
#define ARM_MPU_REGION_SIZE_32MB
Definition: mpu_armv7.h:53
ARM_MPU_REGION_SIZE_1GB
#define ARM_MPU_REGION_SIZE_1GB
Definition: mpu_armv7.h:58
BOARD_CAMERA_I2C_CLOCK_FREQ
#define BOARD_CAMERA_I2C_CLOCK_FREQ
Definition: board.h:213
ARM_MPU_REGION_SIZE_512MB
#define ARM_MPU_REGION_SIZE_512MB
Definition: mpu_armv7.h:57
BOARD_DEBUG_UART_TYPE
#define BOARD_DEBUG_UART_TYPE
Definition: board.h:22
IOMUXC_SW_PAD_CTL_PAD_DSE
#define IOMUXC_SW_PAD_CTL_PAD_DSE(x)
Definition: MIMXRT1062.h:21983
ARM_MPU_REGION_SIZE_8MB
#define ARM_MPU_REGION_SIZE_8MB
Definition: mpu_armv7.h:51
BOARD_ConfigMPU
void BOARD_ConfigMPU(void)
Definition: board.c:233
board.h
ARM_MPU_AP_RO
#define ARM_MPU_AP_RO
Definition: mpu_armv7.h:67
BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE
Definition: board.h:32
ARM_MPU_REGION_SIZE_512KB
#define ARM_MPU_REGION_SIZE_512KB
Definition: mpu_armv7.h:47
SCB
#define SCB
Definition: core_armv81mml.h:2043
BOARD_DebugConsoleSrcFreq
uint32_t BOARD_DebugConsoleSrcFreq(void)
Definition: board.c:22
SCB_EnableICache
__STATIC_FORCEINLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: core_cm7.h:2234
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK
#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK
Definition: MIMXRT1062.h:22023
IOMUXC_SW_PAD_CTL_PAD_SRE_MASK
#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK
Definition: MIMXRT1062.h:21964
ARM_MPU_RASR
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
Definition: mpu_armv7.h:122