Callisto4Bootloader: PMU Register Masks

Callisto4Bootloader

PMU Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » PMU Peripheral Access Layer

## MISC0 - Miscellaneous Register 0

#define | PMU_MISC0_REFTOP_PWD_MASK (0x1U)
#define | PMU_MISC0_REFTOP_PWD_SHIFT (0U)
#define | PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
#define | PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
#define | PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
#define | PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
#define | PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
#define | PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
#define | PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
#define | PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
#define | PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
#define | PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
#define | PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
#define | PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
#define | PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
#define | PMU_MISC0_OSC_I_MASK (0x6000U)
#define | PMU_MISC0_OSC_I_SHIFT (13U)
#define | PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
#define | PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
#define | PMU_MISC0_OSC_XTALOK_SHIFT (15U)
#define | PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
#define | PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
#define | PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
#define | PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
#define | PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
#define | PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
#define | PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
#define | PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
#define | PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
#define | PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
#define | PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
#define | PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
#define | PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
#define | PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
#define | PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
#define | PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)
#define | PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)

## MISC0_SET - Miscellaneous Register 0

#define | PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
#define | PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
#define | PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
#define | PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
#define | PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
#define | PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
#define | PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
#define | PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
#define | PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
#define | PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
#define | PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
#define | PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
#define | PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
#define | PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
#define | PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
#define | PMU_MISC0_SET_OSC_I_MASK (0x6000U)
#define | PMU_MISC0_SET_OSC_I_SHIFT (13U)
#define | PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
#define | PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
#define | PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
#define | PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
#define | PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
#define | PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
#define | PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
#define | PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
#define | PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
#define | PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
#define | PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
#define | PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
#define | PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
#define | PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
#define | PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
#define | PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
#define | PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
#define | PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
#define | PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
#define | PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)

## MISC0_CLR - Miscellaneous Register 0

#define | PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
#define | PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
#define | PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
#define | PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
#define | PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
#define | PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
#define | PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
#define | PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
#define | PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
#define | PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
#define | PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
#define | PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
#define | PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
#define | PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
#define | PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
#define | PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
#define | PMU_MISC0_CLR_OSC_I_SHIFT (13U)
#define | PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
#define | PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
#define | PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
#define | PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
#define | PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
#define | PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
#define | PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
#define | PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
#define | PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
#define | PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
#define | PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
#define | PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
#define | PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
#define | PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
#define | PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
#define | PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
#define | PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
#define | PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
#define | PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
#define | PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)

## MISC0_TOG - Miscellaneous Register 0

#define | PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
#define | PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
#define | PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
#define | PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
#define | PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
#define | PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
#define | PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
#define | PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
#define | PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
#define | PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
#define | PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
#define | PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
#define | PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
#define | PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
#define | PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
#define | PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
#define | PMU_MISC0_TOG_OSC_I_SHIFT (13U)
#define | PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
#define | PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
#define | PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
#define | PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
#define | PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
#define | PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
#define | PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
#define | PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
#define | PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
#define | PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
#define | PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
#define | PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
#define | PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
#define | PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
#define | PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
#define | PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
#define | PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
#define | PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
#define | PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
#define | PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)

## MISC1 - Miscellaneous Register 1

#define | PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
#define | PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
#define | PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
#define | PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)
#define | PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)
#define | PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
#define | PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
#define | PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
#define | PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
#define | PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)
#define | PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)
#define | PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
#define | PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
#define | PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
#define | PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
#define | PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)
#define | PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)
#define | PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
#define | PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
#define | PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
#define | PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
#define | PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
#define | PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
#define | PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
#define | PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
#define | PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
#define | PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
#define | PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
#define | PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
#define | PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
#define | PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
#define | PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
#define | PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)

## MISC1_SET - Miscellaneous Register 1

#define | PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
#define | PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
#define | PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
#define | PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)
#define | PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)
#define | PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
#define | PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
#define | PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
#define | PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
#define | PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)
#define | PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)
#define | PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
#define | PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
#define | PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
#define | PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
#define | PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)
#define | PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)
#define | PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
#define | PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
#define | PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
#define | PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
#define | PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
#define | PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
#define | PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
#define | PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
#define | PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
#define | PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
#define | PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
#define | PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
#define | PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
#define | PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
#define | PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
#define | PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)

## MISC1_CLR - Miscellaneous Register 1

#define | PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
#define | PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
#define | PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
#define | PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)
#define | PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)
#define | PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
#define | PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
#define | PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
#define | PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
#define | PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)
#define | PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)
#define | PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
#define | PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
#define | PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
#define | PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
#define | PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)
#define | PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)
#define | PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
#define | PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
#define | PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
#define | PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
#define | PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
#define | PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
#define | PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
#define | PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
#define | PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
#define | PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
#define | PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
#define | PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
#define | PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
#define | PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
#define | PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
#define | PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)

## MISC1_TOG - Miscellaneous Register 1

#define | PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
#define | PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
#define | PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
#define | PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)
#define | PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)
#define | PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
#define | PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
#define | PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
#define | PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
#define | PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)
#define | PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)
#define | PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
#define | PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
#define | PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
#define | PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
#define | PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)
#define | PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)
#define | PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
#define | PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
#define | PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
#define | PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
#define | PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
#define | PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
#define | PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
#define | PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
#define | PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
#define | PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
#define | PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
#define | PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
#define | PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
#define | PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
#define | PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
#define | PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)

## REG_1P1 - Regulator 1P1 Register

#define | PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
#define | PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
#define | PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
#define | PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
#define | PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
#define | PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
#define | PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
#define | PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
#define | PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
#define | PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
#define | PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
#define | PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
#define | PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
#define | PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
#define | PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)

## REG_1P1_SET - Regulator 1P1 Register

#define | PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
#define | PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
#define | PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
#define | PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
#define | PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
#define | PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
#define | PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
#define | PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
#define | PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
#define | PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
#define | PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
#define | PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
#define | PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
#define | PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
#define | PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)

## REG_1P1_CLR - Regulator 1P1 Register

#define | PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
#define | PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
#define | PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
#define | PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
#define | PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
#define | PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
#define | PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
#define | PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
#define | PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
#define | PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
#define | PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
#define | PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
#define | PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
#define | PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
#define | PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)

## REG_1P1_TOG - Regulator 1P1 Register

#define | PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
#define | PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
#define | PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
#define | PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
#define | PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
#define | PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
#define | PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
#define | PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
#define | PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
#define | PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
#define | PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
#define | PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
#define | PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
#define | PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
#define | PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)

## REG_3P0 - Regulator 3P0 Register

#define | PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
#define | PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
#define | PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
#define | PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
#define | PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
#define | PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
#define | PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
#define | PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
#define | PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
#define | PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
#define | PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
#define | PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
#define | PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
#define | PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)

## REG_3P0_SET - Regulator 3P0 Register

#define | PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
#define | PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
#define | PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
#define | PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
#define | PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
#define | PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
#define | PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
#define | PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
#define | PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
#define | PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
#define | PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
#define | PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
#define | PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
#define | PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)

## REG_3P0_CLR - Regulator 3P0 Register

#define | PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
#define | PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
#define | PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
#define | PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
#define | PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
#define | PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
#define | PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
#define | PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
#define | PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
#define | PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
#define | PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
#define | PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
#define | PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
#define | PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)

## REG_3P0_TOG - Regulator 3P0 Register

#define | PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
#define | PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
#define | PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
#define | PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
#define | PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
#define | PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
#define | PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
#define | PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
#define | PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
#define | PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
#define | PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
#define | PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
#define | PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
#define | PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)

## REG_2P5 - Regulator 2P5 Register

#define | PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
#define | PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
#define | PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
#define | PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
#define | PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
#define | PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
#define | PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
#define | PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
#define | PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
#define | PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
#define | PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
#define | PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)

## REG_2P5_SET - Regulator 2P5 Register

#define | PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
#define | PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
#define | PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
#define | PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
#define | PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
#define | PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
#define | PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
#define | PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
#define | PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
#define | PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
#define | PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
#define | PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)

## REG_2P5_CLR - Regulator 2P5 Register

#define | PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
#define | PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
#define | PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
#define | PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
#define | PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
#define | PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
#define | PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
#define | PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
#define | PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
#define | PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
#define | PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
#define | PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)

## REG_2P5_TOG - Regulator 2P5 Register

#define | PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
#define | PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
#define | PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
#define | PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
#define | PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
#define | PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
#define | PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
#define | PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
#define | PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
#define | PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
#define | PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
#define | PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)

## REG_CORE - Digital Regulator Core Register

#define | PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
#define | PMU_REG_CORE_REG0_TARG_SHIFT (0U)
#define | PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
#define | PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
#define | PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
#define | PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
#define | PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
#define | PMU_REG_CORE_REG1_TARG_SHIFT (9U)
#define | PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
#define | PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
#define | PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
#define | PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
#define | PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
#define | PMU_REG_CORE_REG2_TARG_SHIFT (18U)
#define | PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
#define | PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
#define | PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
#define | PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
#define | PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
#define | PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
#define | PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
#define | PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
#define | PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
#define | PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)

## REG_CORE_SET - Digital Regulator Core Register

#define | PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
#define | PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
#define | PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
#define | PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
#define | PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
#define | PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
#define | PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
#define | PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
#define | PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
#define | PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
#define | PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
#define | PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
#define | PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
#define | PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
#define | PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
#define | PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
#define | PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
#define | PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
#define | PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
#define | PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
#define | PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
#define | PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
#define | PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
#define | PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)

## REG_CORE_CLR - Digital Regulator Core Register

#define | PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
#define | PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
#define | PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
#define | PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
#define | PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
#define | PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
#define | PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
#define | PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
#define | PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
#define | PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
#define | PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
#define | PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
#define | PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
#define | PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
#define | PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
#define | PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
#define | PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
#define | PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
#define | PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
#define | PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
#define | PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
#define | PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
#define | PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
#define | PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)

## REG_CORE_TOG - Digital Regulator Core Register

#define | PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
#define | PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
#define | PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
#define | PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
#define | PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
#define | PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
#define | PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
#define | PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
#define | PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
#define | PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
#define | PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
#define | PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
#define | PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
#define | PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
#define | PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
#define | PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
#define | PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
#define | PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
#define | PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
#define | PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
#define | PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
#define | PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
#define | PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
#define | PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)

## MISC2 - Miscellaneous Control Register

#define | PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
#define | PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
#define | PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
#define | PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
#define | PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
#define | PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
#define | PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
#define | PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
#define | PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
#define | PMU_MISC2_PLL3_disable_MASK (0x80U)
#define | PMU_MISC2_PLL3_disable_SHIFT (7U)
#define | PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
#define | PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
#define | PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
#define | PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
#define | PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
#define | PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
#define | PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
#define | PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
#define | PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
#define | PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
#define | PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
#define | PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
#define | PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
#define | PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
#define | PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
#define | PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
#define | PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
#define | PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
#define | PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
#define | PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
#define | PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
#define | PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
#define | PMU_MISC2_REG2_OK_MASK (0x400000U)
#define | PMU_MISC2_REG2_OK_SHIFT (22U)
#define | PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
#define | PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
#define | PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
#define | PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
#define | PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
#define | PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
#define | PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
#define | PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
#define | PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
#define | PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
#define | PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
#define | PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
#define | PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
#define | PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)
#define | PMU_MISC2_VIDEO_DIV_SHIFT (30U)
#define | PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)

## MISC2_SET - Miscellaneous Control Register

#define | PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
#define | PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
#define | PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
#define | PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
#define | PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
#define | PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
#define | PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
#define | PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
#define | PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
#define | PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
#define | PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
#define | PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
#define | PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
#define | PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
#define | PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
#define | PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
#define | PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
#define | PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
#define | PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
#define | PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
#define | PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
#define | PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
#define | PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
#define | PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
#define | PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
#define | PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
#define | PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
#define | PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
#define | PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
#define | PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
#define | PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
#define | PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
#define | PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
#define | PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
#define | PMU_MISC2_SET_REG2_OK_SHIFT (22U)
#define | PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
#define | PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
#define | PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
#define | PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
#define | PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
#define | PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
#define | PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
#define | PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
#define | PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
#define | PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
#define | PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
#define | PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
#define | PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
#define | PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
#define | PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)
#define | PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)

## MISC2_CLR - Miscellaneous Control Register

#define | PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
#define | PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
#define | PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
#define | PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
#define | PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
#define | PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
#define | PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
#define | PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
#define | PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
#define | PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
#define | PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
#define | PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
#define | PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
#define | PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
#define | PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
#define | PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
#define | PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
#define | PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
#define | PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
#define | PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
#define | PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
#define | PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
#define | PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
#define | PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
#define | PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
#define | PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
#define | PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
#define | PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
#define | PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
#define | PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
#define | PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
#define | PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
#define | PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
#define | PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
#define | PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
#define | PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
#define | PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
#define | PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
#define | PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
#define | PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
#define | PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
#define | PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
#define | PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
#define | PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
#define | PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
#define | PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
#define | PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
#define | PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
#define | PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
#define | PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
#define | PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)

## MISC2_TOG - Miscellaneous Control Register

#define | PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
#define | PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
#define | PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
#define | PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
#define | PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
#define | PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
#define | PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
#define | PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
#define | PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
#define | PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
#define | PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
#define | PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
#define | PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
#define | PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
#define | PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
#define | PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
#define | PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
#define | PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
#define | PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
#define | PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
#define | PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
#define | PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
#define | PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
#define | PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
#define | PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
#define | PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
#define | PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
#define | PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
#define | PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
#define | PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
#define | PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
#define | PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
#define | PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
#define | PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
#define | PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
#define | PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
#define | PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
#define | PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
#define | PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
#define | PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
#define | PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
#define | PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
#define | PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
#define | PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
#define | PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
#define | PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
#define | PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
#define | PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
#define | PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
#define | PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
#define | PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ PMU_MISC0_CLKGATE_CTRL

#define PMU_MISC0_CLKGATE_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

Definition at line 31946 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLKGATE_CTRL_MASK

#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)

Definition at line 31940 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLKGATE_CTRL_SHIFT

#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)

Definition at line 31941 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLKGATE_DELAY

#define PMU_MISC0_CLKGATE_DELAY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

Definition at line 31959 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLKGATE_DELAY_MASK

#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)

Definition at line 31947 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLKGATE_DELAY_SHIFT

#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)

Definition at line 31948 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_CLKGATE_CTRL

#define PMU_MISC0_CLR_CLKGATE_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

Definition at line 32142 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_CLKGATE_CTRL_MASK

#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)

Definition at line 32136 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT

#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)

Definition at line 32137 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_CLKGATE_DELAY

#define PMU_MISC0_CLR_CLKGATE_DELAY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

Definition at line 32155 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_CLKGATE_DELAY_MASK

#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)

Definition at line 32143 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT

#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)

Definition at line 32144 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS

#define PMU_MISC0_CLR_DISCON_HIGH_SNVS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

Definition at line 32120 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK

#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)

Definition at line 32114 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT

#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)

Definition at line 32115 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_I

#define PMU_MISC0_CLR_OSC_I | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

Definition at line 32129 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_I_MASK

#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)

Definition at line 32121 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_I_SHIFT

#define PMU_MISC0_CLR_OSC_I_SHIFT (13U)

Definition at line 32122 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_XTALOK

#define PMU_MISC0_CLR_OSC_XTALOK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)

Definition at line 32132 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_XTALOK_EN

#define PMU_MISC0_CLR_OSC_XTALOK_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)

Definition at line 32135 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_XTALOK_EN_MASK

#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)

Definition at line 32133 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT

#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)

Definition at line 32134 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_XTALOK_MASK

#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)

Definition at line 32130 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_OSC_XTALOK_SHIFT

#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)

Definition at line 32131 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_PWD

#define PMU_MISC0_CLR_REFTOP_PWD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)

Definition at line 32081 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_PWD_MASK

#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)

Definition at line 32079 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_PWD_SHIFT

#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)

Definition at line 32080 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF

#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

Definition at line 32088 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK

#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)

Definition at line 32082 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT

#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)

Definition at line 32083 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_VBGADJ

#define PMU_MISC0_CLR_REFTOP_VBGADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

Definition at line 32101 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_VBGADJ_MASK

#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)

Definition at line 32089 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT

#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)

Definition at line 32090 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_VBGUP

#define PMU_MISC0_CLR_REFTOP_VBGUP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)

Definition at line 32104 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_VBGUP_MASK

#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)

Definition at line 32102 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT

#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)

Definition at line 32103 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE

#define PMU_MISC0_CLR_RTC_XTAL_SOURCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

Definition at line 32162 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK

#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)

Definition at line 32156 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT

#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)

Definition at line 32157 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_STOP_MODE_CONFIG

#define PMU_MISC0_CLR_STOP_MODE_CONFIG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

Definition at line 32113 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK

#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)

Definition at line 32105 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT

#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)

Definition at line 32106 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_VID_PLL_PREDIV

#define PMU_MISC0_CLR_VID_PLL_PREDIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

Definition at line 32172 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_VID_PLL_PREDIV_MASK

#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)

Definition at line 32166 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT

#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)

Definition at line 32167 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_XTAL_24M_PWD

#define PMU_MISC0_CLR_XTAL_24M_PWD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)

Definition at line 32165 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_XTAL_24M_PWD_MASK

#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)

Definition at line 32163 of file MIMXRT1062.h.

## ◆ PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT

#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)

Definition at line 32164 of file MIMXRT1062.h.

## ◆ PMU_MISC0_DISCON_HIGH_SNVS

#define PMU_MISC0_DISCON_HIGH_SNVS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

Definition at line 31924 of file MIMXRT1062.h.

## ◆ PMU_MISC0_DISCON_HIGH_SNVS_MASK

#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)

Definition at line 31918 of file MIMXRT1062.h.

## ◆ PMU_MISC0_DISCON_HIGH_SNVS_SHIFT

#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)

Definition at line 31919 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_I

#define PMU_MISC0_OSC_I | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

Definition at line 31933 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_I_MASK

#define PMU_MISC0_OSC_I_MASK (0x6000U)

Definition at line 31925 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_I_SHIFT

#define PMU_MISC0_OSC_I_SHIFT (13U)

Definition at line 31926 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_XTALOK

#define PMU_MISC0_OSC_XTALOK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)

Definition at line 31936 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_XTALOK_EN

#define PMU_MISC0_OSC_XTALOK_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)

Definition at line 31939 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_XTALOK_EN_MASK

#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)

Definition at line 31937 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_XTALOK_EN_SHIFT

#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)

Definition at line 31938 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_XTALOK_MASK

#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)

Definition at line 31934 of file MIMXRT1062.h.

## ◆ PMU_MISC0_OSC_XTALOK_SHIFT

#define PMU_MISC0_OSC_XTALOK_SHIFT (15U)

Definition at line 31935 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_PWD

#define PMU_MISC0_REFTOP_PWD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)

Definition at line 31885 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_PWD_MASK

#define PMU_MISC0_REFTOP_PWD_MASK (0x1U)

Definition at line 31883 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_PWD_SHIFT

#define PMU_MISC0_REFTOP_PWD_SHIFT (0U)

Definition at line 31884 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_SELFBIASOFF

#define PMU_MISC0_REFTOP_SELFBIASOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

Definition at line 31892 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_SELFBIASOFF_MASK

#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)

Definition at line 31886 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT

#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)

Definition at line 31887 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_VBGADJ

#define PMU_MISC0_REFTOP_VBGADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

Definition at line 31905 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_VBGADJ_MASK

#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)

Definition at line 31893 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_VBGADJ_SHIFT

#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)

Definition at line 31894 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_VBGUP

#define PMU_MISC0_REFTOP_VBGUP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)

Definition at line 31908 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_VBGUP_MASK

#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)

Definition at line 31906 of file MIMXRT1062.h.

## ◆ PMU_MISC0_REFTOP_VBGUP_SHIFT

#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)

Definition at line 31907 of file MIMXRT1062.h.

## ◆ PMU_MISC0_RTC_XTAL_SOURCE

#define PMU_MISC0_RTC_XTAL_SOURCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

Definition at line 31966 of file MIMXRT1062.h.

## ◆ PMU_MISC0_RTC_XTAL_SOURCE_MASK

#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)

Definition at line 31960 of file MIMXRT1062.h.

## ◆ PMU_MISC0_RTC_XTAL_SOURCE_SHIFT

#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)

Definition at line 31961 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_CLKGATE_CTRL

#define PMU_MISC0_SET_CLKGATE_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

Definition at line 32044 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_CLKGATE_CTRL_MASK

#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)

Definition at line 32038 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_CLKGATE_CTRL_SHIFT

#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)

Definition at line 32039 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_CLKGATE_DELAY

#define PMU_MISC0_SET_CLKGATE_DELAY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

Definition at line 32057 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_CLKGATE_DELAY_MASK

#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)

Definition at line 32045 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_CLKGATE_DELAY_SHIFT

#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)

Definition at line 32046 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_DISCON_HIGH_SNVS

#define PMU_MISC0_SET_DISCON_HIGH_SNVS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

Definition at line 32022 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK

#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)

Definition at line 32016 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT

#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)

Definition at line 32017 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_I

#define PMU_MISC0_SET_OSC_I | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

Definition at line 32031 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_I_MASK

#define PMU_MISC0_SET_OSC_I_MASK (0x6000U)

Definition at line 32023 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_I_SHIFT

#define PMU_MISC0_SET_OSC_I_SHIFT (13U)

Definition at line 32024 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_XTALOK

#define PMU_MISC0_SET_OSC_XTALOK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)

Definition at line 32034 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_XTALOK_EN

#define PMU_MISC0_SET_OSC_XTALOK_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)

Definition at line 32037 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_XTALOK_EN_MASK

#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)

Definition at line 32035 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT

#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)

Definition at line 32036 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_XTALOK_MASK

#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)

Definition at line 32032 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_OSC_XTALOK_SHIFT

#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)

Definition at line 32033 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_PWD

#define PMU_MISC0_SET_REFTOP_PWD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)

Definition at line 31983 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_PWD_MASK

#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)

Definition at line 31981 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_PWD_SHIFT

#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)

Definition at line 31982 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_SELFBIASOFF

#define PMU_MISC0_SET_REFTOP_SELFBIASOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

Definition at line 31990 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK

#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)

Definition at line 31984 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT

#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)

Definition at line 31985 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_VBGADJ

#define PMU_MISC0_SET_REFTOP_VBGADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

Definition at line 32003 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_VBGADJ_MASK

#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)

Definition at line 31991 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT

#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)

Definition at line 31992 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_VBGUP

#define PMU_MISC0_SET_REFTOP_VBGUP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)

Definition at line 32006 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_VBGUP_MASK

#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)

Definition at line 32004 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_REFTOP_VBGUP_SHIFT

#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)

Definition at line 32005 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_RTC_XTAL_SOURCE

#define PMU_MISC0_SET_RTC_XTAL_SOURCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

Definition at line 32064 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK

#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)

Definition at line 32058 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT

#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)

Definition at line 32059 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_STOP_MODE_CONFIG

#define PMU_MISC0_SET_STOP_MODE_CONFIG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

Definition at line 32015 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_STOP_MODE_CONFIG_MASK

#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)

Definition at line 32007 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT

#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)

Definition at line 32008 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_VID_PLL_PREDIV

#define PMU_MISC0_SET_VID_PLL_PREDIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

Definition at line 32074 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_VID_PLL_PREDIV_MASK

#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)

Definition at line 32068 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT

#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)

Definition at line 32069 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_XTAL_24M_PWD

#define PMU_MISC0_SET_XTAL_24M_PWD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)

Definition at line 32067 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_XTAL_24M_PWD_MASK

#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)

Definition at line 32065 of file MIMXRT1062.h.

## ◆ PMU_MISC0_SET_XTAL_24M_PWD_SHIFT

#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)

Definition at line 32066 of file MIMXRT1062.h.

## ◆ PMU_MISC0_STOP_MODE_CONFIG

#define PMU_MISC0_STOP_MODE_CONFIG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

Definition at line 31917 of file MIMXRT1062.h.

## ◆ PMU_MISC0_STOP_MODE_CONFIG_MASK

#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)

Definition at line 31909 of file MIMXRT1062.h.

## ◆ PMU_MISC0_STOP_MODE_CONFIG_SHIFT

#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)

Definition at line 31910 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_CLKGATE_CTRL

#define PMU_MISC0_TOG_CLKGATE_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

Definition at line 32240 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_CLKGATE_CTRL_MASK

#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)

Definition at line 32234 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT

#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)

Definition at line 32235 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_CLKGATE_DELAY

#define PMU_MISC0_TOG_CLKGATE_DELAY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

Definition at line 32253 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_CLKGATE_DELAY_MASK

#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)

Definition at line 32241 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT

#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)

Definition at line 32242 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_DISCON_HIGH_SNVS

#define PMU_MISC0_TOG_DISCON_HIGH_SNVS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

Definition at line 32218 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK

#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)

Definition at line 32212 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT

#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)

Definition at line 32213 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_I

#define PMU_MISC0_TOG_OSC_I | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

Definition at line 32227 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_I_MASK

#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)

Definition at line 32219 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_I_SHIFT

#define PMU_MISC0_TOG_OSC_I_SHIFT (13U)

Definition at line 32220 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_XTALOK

#define PMU_MISC0_TOG_OSC_XTALOK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)

Definition at line 32230 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_XTALOK_EN

#define PMU_MISC0_TOG_OSC_XTALOK_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)

Definition at line 32233 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_XTALOK_EN_MASK

#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)

Definition at line 32231 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT

#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)

Definition at line 32232 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_XTALOK_MASK

#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)

Definition at line 32228 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_OSC_XTALOK_SHIFT

#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)

Definition at line 32229 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_PWD

#define PMU_MISC0_TOG_REFTOP_PWD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)

Definition at line 32179 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_PWD_MASK

#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)

Definition at line 32177 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_PWD_SHIFT

#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)

Definition at line 32178 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_SELFBIASOFF

#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

Definition at line 32186 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK

#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)

Definition at line 32180 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT

#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)

Definition at line 32181 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_VBGADJ

#define PMU_MISC0_TOG_REFTOP_VBGADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

Definition at line 32199 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_VBGADJ_MASK

#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)

Definition at line 32187 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT

#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)

Definition at line 32188 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_VBGUP

#define PMU_MISC0_TOG_REFTOP_VBGUP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)

Definition at line 32202 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_VBGUP_MASK

#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)

Definition at line 32200 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT

#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)

Definition at line 32201 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_RTC_XTAL_SOURCE

#define PMU_MISC0_TOG_RTC_XTAL_SOURCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

Definition at line 32260 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK

#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)

Definition at line 32254 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT

#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)

Definition at line 32255 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_STOP_MODE_CONFIG

#define PMU_MISC0_TOG_STOP_MODE_CONFIG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

Definition at line 32211 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK

#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)

Definition at line 32203 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT

#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)

Definition at line 32204 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_VID_PLL_PREDIV

#define PMU_MISC0_TOG_VID_PLL_PREDIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

Definition at line 32270 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_VID_PLL_PREDIV_MASK

#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)

Definition at line 32264 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT

#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)

Definition at line 32265 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_XTAL_24M_PWD

#define PMU_MISC0_TOG_XTAL_24M_PWD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)

Definition at line 32263 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_XTAL_24M_PWD_MASK

#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)

Definition at line 32261 of file MIMXRT1062.h.

## ◆ PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT

#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)

Definition at line 32262 of file MIMXRT1062.h.

## ◆ PMU_MISC0_VID_PLL_PREDIV

#define PMU_MISC0_VID_PLL_PREDIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

Definition at line 31976 of file MIMXRT1062.h.

## ◆ PMU_MISC0_VID_PLL_PREDIV_MASK

#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)

Definition at line 31970 of file MIMXRT1062.h.

## ◆ PMU_MISC0_VID_PLL_PREDIV_SHIFT

#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)

Definition at line 31971 of file MIMXRT1062.h.

## ◆ PMU_MISC0_XTAL_24M_PWD

#define PMU_MISC0_XTAL_24M_PWD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)

Definition at line 31969 of file MIMXRT1062.h.

## ◆ PMU_MISC0_XTAL_24M_PWD_MASK

#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)

Definition at line 31967 of file MIMXRT1062.h.

## ◆ PMU_MISC0_XTAL_24M_PWD_SHIFT

#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)

Definition at line 31968 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_ANA_BO

#define PMU_MISC1_CLR_IRQ_ANA_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)

Definition at line 32519 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_ANA_BO_MASK

#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)

Definition at line 32517 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT

#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)

Definition at line 32518 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_DIG_BO

#define PMU_MISC1_CLR_IRQ_DIG_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)

Definition at line 32522 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_DIG_BO_MASK

#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)

Definition at line 32520 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT

#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)

Definition at line 32521 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPHIGH

#define PMU_MISC1_CLR_IRQ_TEMPHIGH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)

Definition at line 32516 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK

#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)

Definition at line 32514 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT

#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)

Definition at line 32515 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPLOW

#define PMU_MISC1_CLR_IRQ_TEMPLOW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)

Definition at line 32513 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPLOW_MASK

#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)

Definition at line 32511 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT

#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)

Definition at line 32512 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPPANIC

#define PMU_MISC1_CLR_IRQ_TEMPPANIC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)

Definition at line 32510 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK

#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)

Definition at line 32508 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT

#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)

Definition at line 32509 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDS1_CLK_SEL

#define PMU_MISC1_CLR_LVDS1_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

Definition at line 32463 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK

#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)

Definition at line 32443 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT

#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)

Definition at line 32444 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDS2_CLK_SEL

#define PMU_MISC1_CLR_LVDS2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

Definition at line 32489 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK

#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)

Definition at line 32464 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT

#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)

Definition at line 32465 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK1_IBEN

#define PMU_MISC1_CLR_LVDSCLK1_IBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)

Definition at line 32498 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK

#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)

Definition at line 32496 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT

#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)

Definition at line 32497 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK1_OBEN

#define PMU_MISC1_CLR_LVDSCLK1_OBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)

Definition at line 32492 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK

#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)

Definition at line 32490 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT

#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)

Definition at line 32491 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK2_IBEN

#define PMU_MISC1_CLR_LVDSCLK2_IBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)

Definition at line 32501 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK

#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)

Definition at line 32499 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT

#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)

Definition at line 32500 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK2_OBEN

#define PMU_MISC1_CLR_LVDSCLK2_OBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)

Definition at line 32495 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK

#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)

Definition at line 32493 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT

#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)

Definition at line 32494 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_PFD_480_AUTOGATE_EN

#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)

Definition at line 32504 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK

#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)

Definition at line 32502 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT

#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)

Definition at line 32503 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_PFD_528_AUTOGATE_EN

#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)

Definition at line 32507 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK

#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)

Definition at line 32505 of file MIMXRT1062.h.

## ◆ PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT

#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)

Definition at line 32506 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_ANA_BO

#define PMU_MISC1_IRQ_ANA_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)

Definition at line 32351 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_ANA_BO_MASK

#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)

Definition at line 32349 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_ANA_BO_SHIFT

#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)

Definition at line 32350 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_DIG_BO

#define PMU_MISC1_IRQ_DIG_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)

Definition at line 32354 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_DIG_BO_MASK

#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)

Definition at line 32352 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_DIG_BO_SHIFT

#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)

Definition at line 32353 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPHIGH

#define PMU_MISC1_IRQ_TEMPHIGH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)

Definition at line 32348 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPHIGH_MASK

#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)

Definition at line 32346 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPHIGH_SHIFT

#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)

Definition at line 32347 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPLOW

#define PMU_MISC1_IRQ_TEMPLOW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)

Definition at line 32345 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPLOW_MASK

#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)

Definition at line 32343 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPLOW_SHIFT

#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)

Definition at line 32344 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPPANIC

#define PMU_MISC1_IRQ_TEMPPANIC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)

Definition at line 32342 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPPANIC_MASK

#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)

Definition at line 32340 of file MIMXRT1062.h.

## ◆ PMU_MISC1_IRQ_TEMPPANIC_SHIFT

#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)

Definition at line 32341 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDS1_CLK_SEL

#define PMU_MISC1_LVDS1_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

Definition at line 32295 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDS1_CLK_SEL_MASK

#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)

Definition at line 32275 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDS1_CLK_SEL_SHIFT

#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)

Definition at line 32276 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDS2_CLK_SEL

#define PMU_MISC1_LVDS2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

Definition at line 32321 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDS2_CLK_SEL_MASK

#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)

Definition at line 32296 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDS2_CLK_SEL_SHIFT

#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)

Definition at line 32297 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK1_IBEN

#define PMU_MISC1_LVDSCLK1_IBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)

Definition at line 32330 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK1_IBEN_MASK

#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)

Definition at line 32328 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK1_IBEN_SHIFT

#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)

Definition at line 32329 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK1_OBEN

#define PMU_MISC1_LVDSCLK1_OBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)

Definition at line 32324 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK1_OBEN_MASK

#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)

Definition at line 32322 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK1_OBEN_SHIFT

#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)

Definition at line 32323 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK2_IBEN

#define PMU_MISC1_LVDSCLK2_IBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)

Definition at line 32333 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK2_IBEN_MASK

#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)

Definition at line 32331 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK2_IBEN_SHIFT

#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)

Definition at line 32332 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK2_OBEN

#define PMU_MISC1_LVDSCLK2_OBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)

Definition at line 32327 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK2_OBEN_MASK

#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)

Definition at line 32325 of file MIMXRT1062.h.

## ◆ PMU_MISC1_LVDSCLK2_OBEN_SHIFT

#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)

Definition at line 32326 of file MIMXRT1062.h.

## ◆ PMU_MISC1_PFD_480_AUTOGATE_EN

#define PMU_MISC1_PFD_480_AUTOGATE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)

Definition at line 32336 of file MIMXRT1062.h.

## ◆ PMU_MISC1_PFD_480_AUTOGATE_EN_MASK

#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)

Definition at line 32334 of file MIMXRT1062.h.

## ◆ PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT

#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)

Definition at line 32335 of file MIMXRT1062.h.

## ◆ PMU_MISC1_PFD_528_AUTOGATE_EN

#define PMU_MISC1_PFD_528_AUTOGATE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)

Definition at line 32339 of file MIMXRT1062.h.

## ◆ PMU_MISC1_PFD_528_AUTOGATE_EN_MASK

#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)

Definition at line 32337 of file MIMXRT1062.h.

## ◆ PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT

#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)

Definition at line 32338 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_ANA_BO

#define PMU_MISC1_SET_IRQ_ANA_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)

Definition at line 32435 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_ANA_BO_MASK

#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)

Definition at line 32433 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_ANA_BO_SHIFT

#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)

Definition at line 32434 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_DIG_BO

#define PMU_MISC1_SET_IRQ_DIG_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)

Definition at line 32438 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_DIG_BO_MASK

#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)

Definition at line 32436 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_DIG_BO_SHIFT

#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)

Definition at line 32437 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPHIGH

#define PMU_MISC1_SET_IRQ_TEMPHIGH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)

Definition at line 32432 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPHIGH_MASK

#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)

Definition at line 32430 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT

#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)

Definition at line 32431 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPLOW

#define PMU_MISC1_SET_IRQ_TEMPLOW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)

Definition at line 32429 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPLOW_MASK

#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)

Definition at line 32427 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT

#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)

Definition at line 32428 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPPANIC

#define PMU_MISC1_SET_IRQ_TEMPPANIC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)

Definition at line 32426 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPPANIC_MASK

#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)

Definition at line 32424 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT

#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)

Definition at line 32425 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDS1_CLK_SEL

#define PMU_MISC1_SET_LVDS1_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

Definition at line 32379 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDS1_CLK_SEL_MASK

#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)

Definition at line 32359 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT

#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)

Definition at line 32360 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDS2_CLK_SEL

#define PMU_MISC1_SET_LVDS2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

Definition at line 32405 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDS2_CLK_SEL_MASK

#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)

Definition at line 32380 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT

#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)

Definition at line 32381 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK1_IBEN

#define PMU_MISC1_SET_LVDSCLK1_IBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)

Definition at line 32414 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK1_IBEN_MASK

#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)

Definition at line 32412 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT

#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)

Definition at line 32413 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK1_OBEN

#define PMU_MISC1_SET_LVDSCLK1_OBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)

Definition at line 32408 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK1_OBEN_MASK

#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)

Definition at line 32406 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT

#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)

Definition at line 32407 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK2_IBEN

#define PMU_MISC1_SET_LVDSCLK2_IBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)

Definition at line 32417 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK2_IBEN_MASK

#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)

Definition at line 32415 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT

#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)

Definition at line 32416 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK2_OBEN

#define PMU_MISC1_SET_LVDSCLK2_OBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)

Definition at line 32411 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK2_OBEN_MASK

#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)

Definition at line 32409 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT

#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)

Definition at line 32410 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_PFD_480_AUTOGATE_EN

#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)

Definition at line 32420 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK

#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)

Definition at line 32418 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT

#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)

Definition at line 32419 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_PFD_528_AUTOGATE_EN

#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)

Definition at line 32423 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK

#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)

Definition at line 32421 of file MIMXRT1062.h.

## ◆ PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT

#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)

Definition at line 32422 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_ANA_BO

#define PMU_MISC1_TOG_IRQ_ANA_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)

Definition at line 32603 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_ANA_BO_MASK

#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)

Definition at line 32601 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT

#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)

Definition at line 32602 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_DIG_BO

#define PMU_MISC1_TOG_IRQ_DIG_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)

Definition at line 32606 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_DIG_BO_MASK

#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)

Definition at line 32604 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT

#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)

Definition at line 32605 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPHIGH

#define PMU_MISC1_TOG_IRQ_TEMPHIGH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)

Definition at line 32600 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK

#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)

Definition at line 32598 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT

#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)

Definition at line 32599 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPLOW

#define PMU_MISC1_TOG_IRQ_TEMPLOW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)

Definition at line 32597 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPLOW_MASK

#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)

Definition at line 32595 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT

#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)

Definition at line 32596 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPPANIC

#define PMU_MISC1_TOG_IRQ_TEMPPANIC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)

Definition at line 32594 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK

#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)

Definition at line 32592 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT

#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)

Definition at line 32593 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDS1_CLK_SEL

#define PMU_MISC1_TOG_LVDS1_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

Definition at line 32547 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK

#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)

Definition at line 32527 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT

#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)

Definition at line 32528 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDS2_CLK_SEL

#define PMU_MISC1_TOG_LVDS2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

Definition at line 32573 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK

#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)

Definition at line 32548 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT

#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)

Definition at line 32549 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK1_IBEN

#define PMU_MISC1_TOG_LVDSCLK1_IBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)

Definition at line 32582 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK

#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)

Definition at line 32580 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT

#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)

Definition at line 32581 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK1_OBEN

#define PMU_MISC1_TOG_LVDSCLK1_OBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)

Definition at line 32576 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK

#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)

Definition at line 32574 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT

#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)

Definition at line 32575 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK2_IBEN

#define PMU_MISC1_TOG_LVDSCLK2_IBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)

Definition at line 32585 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK

#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)

Definition at line 32583 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT

#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)

Definition at line 32584 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK2_OBEN

#define PMU_MISC1_TOG_LVDSCLK2_OBEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)

Definition at line 32579 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK

#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)

Definition at line 32577 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT

#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)

Definition at line 32578 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_PFD_480_AUTOGATE_EN

#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)

Definition at line 32588 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK

#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)

Definition at line 32586 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT

#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)

Definition at line 32587 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_PFD_528_AUTOGATE_EN

#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)

Definition at line 32591 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK

#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)

Definition at line 32589 of file MIMXRT1062.h.

## ◆ PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT

#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)

Definition at line 32590 of file MIMXRT1062.h.

## ◆ PMU_MISC2_AUDIO_DIV_LSB

#define PMU_MISC2_AUDIO_DIV_LSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 32652 of file MIMXRT1062.h.

## ◆ PMU_MISC2_AUDIO_DIV_LSB_MASK

#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)

Definition at line 32646 of file MIMXRT1062.h.

## ◆ PMU_MISC2_AUDIO_DIV_LSB_SHIFT

#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)

Definition at line 32647 of file MIMXRT1062.h.

## ◆ PMU_MISC2_AUDIO_DIV_MSB

#define PMU_MISC2_AUDIO_DIV_MSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 32675 of file MIMXRT1062.h.

## ◆ PMU_MISC2_AUDIO_DIV_MSB_MASK

#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)

Definition at line 32669 of file MIMXRT1062.h.

## ◆ PMU_MISC2_AUDIO_DIV_MSB_SHIFT

#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)

Definition at line 32670 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_AUDIO_DIV_LSB

#define PMU_MISC2_CLR_AUDIO_DIV_LSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 32862 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK

#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)

Definition at line 32856 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT

#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)

Definition at line 32857 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_AUDIO_DIV_MSB

#define PMU_MISC2_CLR_AUDIO_DIV_MSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 32885 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK

#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)

Definition at line 32879 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT

#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)

Definition at line 32880 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_PLL3_disable

#define PMU_MISC2_CLR_PLL3_disable | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)

Definition at line 32839 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_PLL3_disable_MASK

#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)

Definition at line 32837 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_PLL3_disable_SHIFT

#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)

Definition at line 32838 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_BO_OFFSET

#define PMU_MISC2_CLR_REG0_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32827 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_BO_OFFSET_MASK

#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)

Definition at line 32821 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT

#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)

Definition at line 32822 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_BO_STATUS

#define PMU_MISC2_CLR_REG0_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 32833 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_BO_STATUS_MASK

#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)

Definition at line 32828 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT

#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)

Definition at line 32829 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_ENABLE_BO

#define PMU_MISC2_CLR_REG0_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)

Definition at line 32836 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_ENABLE_BO_MASK

#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)

Definition at line 32834 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT

#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)

Definition at line 32835 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_STEP_TIME

#define PMU_MISC2_CLR_REG0_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32894 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_STEP_TIME_MASK

#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)

Definition at line 32886 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT

#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)

Definition at line 32887 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_BO_OFFSET

#define PMU_MISC2_CLR_REG1_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32846 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_BO_OFFSET_MASK

#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)

Definition at line 32840 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT

#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)

Definition at line 32841 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_BO_STATUS

#define PMU_MISC2_CLR_REG1_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 32852 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_BO_STATUS_MASK

#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)

Definition at line 32847 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT

#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)

Definition at line 32848 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_ENABLE_BO

#define PMU_MISC2_CLR_REG1_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)

Definition at line 32855 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_ENABLE_BO_MASK

#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)

Definition at line 32853 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT

#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)

Definition at line 32854 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_STEP_TIME

#define PMU_MISC2_CLR_REG1_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32903 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_STEP_TIME_MASK

#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)

Definition at line 32895 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT

#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)

Definition at line 32896 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_BO_OFFSET

#define PMU_MISC2_CLR_REG2_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32869 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_BO_OFFSET_MASK

#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)

Definition at line 32863 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT

#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)

Definition at line 32864 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_BO_STATUS

#define PMU_MISC2_CLR_REG2_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)

Definition at line 32872 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_BO_STATUS_MASK

#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)

Definition at line 32870 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT

#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)

Definition at line 32871 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_ENABLE_BO

#define PMU_MISC2_CLR_REG2_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)

Definition at line 32875 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_ENABLE_BO_MASK

#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)

Definition at line 32873 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT

#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)

Definition at line 32874 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_OK

#define PMU_MISC2_CLR_REG2_OK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)

Definition at line 32878 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_OK_MASK

#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)

Definition at line 32876 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_OK_SHIFT

#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)

Definition at line 32877 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_STEP_TIME

#define PMU_MISC2_CLR_REG2_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32912 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_STEP_TIME_MASK

#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)

Definition at line 32904 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT

#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)

Definition at line 32905 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_VIDEO_DIV

#define PMU_MISC2_CLR_VIDEO_DIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

Definition at line 32921 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_VIDEO_DIV_MASK

#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)

Definition at line 32913 of file MIMXRT1062.h.

## ◆ PMU_MISC2_CLR_VIDEO_DIV_SHIFT

#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)

Definition at line 32914 of file MIMXRT1062.h.

## ◆ PMU_MISC2_PLL3_disable

#define PMU_MISC2_PLL3_disable | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)

Definition at line 32629 of file MIMXRT1062.h.

## ◆ PMU_MISC2_PLL3_disable_MASK

#define PMU_MISC2_PLL3_disable_MASK (0x80U)

Definition at line 32627 of file MIMXRT1062.h.

## ◆ PMU_MISC2_PLL3_disable_SHIFT

#define PMU_MISC2_PLL3_disable_SHIFT (7U)

Definition at line 32628 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_BO_OFFSET

#define PMU_MISC2_REG0_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32617 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_BO_OFFSET_MASK

#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)

Definition at line 32611 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_BO_OFFSET_SHIFT

#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)

Definition at line 32612 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_BO_STATUS

#define PMU_MISC2_REG0_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 32623 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_BO_STATUS_MASK

#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)

Definition at line 32618 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_BO_STATUS_SHIFT

#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)

Definition at line 32619 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_ENABLE_BO

#define PMU_MISC2_REG0_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)

Definition at line 32626 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_ENABLE_BO_MASK

#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)

Definition at line 32624 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_ENABLE_BO_SHIFT

#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)

Definition at line 32625 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_STEP_TIME

#define PMU_MISC2_REG0_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32684 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_STEP_TIME_MASK

#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)

Definition at line 32676 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG0_STEP_TIME_SHIFT

#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)

Definition at line 32677 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_BO_OFFSET

#define PMU_MISC2_REG1_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32636 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_BO_OFFSET_MASK

#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)

Definition at line 32630 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_BO_OFFSET_SHIFT

#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)

Definition at line 32631 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_BO_STATUS

#define PMU_MISC2_REG1_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 32642 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_BO_STATUS_MASK

#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)

Definition at line 32637 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_BO_STATUS_SHIFT

#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)

Definition at line 32638 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_ENABLE_BO

#define PMU_MISC2_REG1_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)

Definition at line 32645 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_ENABLE_BO_MASK

#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)

Definition at line 32643 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_ENABLE_BO_SHIFT

#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)

Definition at line 32644 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_STEP_TIME

#define PMU_MISC2_REG1_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32693 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_STEP_TIME_MASK

#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)

Definition at line 32685 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG1_STEP_TIME_SHIFT

#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)

Definition at line 32686 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_BO_OFFSET

#define PMU_MISC2_REG2_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32659 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_BO_OFFSET_MASK

#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)

Definition at line 32653 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_BO_OFFSET_SHIFT

#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)

Definition at line 32654 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_BO_STATUS

#define PMU_MISC2_REG2_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)

Definition at line 32662 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_BO_STATUS_MASK

#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)

Definition at line 32660 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_BO_STATUS_SHIFT

#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)

Definition at line 32661 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_ENABLE_BO

#define PMU_MISC2_REG2_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)

Definition at line 32665 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_ENABLE_BO_MASK

#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)

Definition at line 32663 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_ENABLE_BO_SHIFT

#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)

Definition at line 32664 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_OK

#define PMU_MISC2_REG2_OK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)

Definition at line 32668 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_OK_MASK

#define PMU_MISC2_REG2_OK_MASK (0x400000U)

Definition at line 32666 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_OK_SHIFT

#define PMU_MISC2_REG2_OK_SHIFT (22U)

Definition at line 32667 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_STEP_TIME

#define PMU_MISC2_REG2_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32702 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_STEP_TIME_MASK

#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)

Definition at line 32694 of file MIMXRT1062.h.

## ◆ PMU_MISC2_REG2_STEP_TIME_SHIFT

#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)

Definition at line 32695 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_AUDIO_DIV_LSB

#define PMU_MISC2_SET_AUDIO_DIV_LSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 32757 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_AUDIO_DIV_LSB_MASK

#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)

Definition at line 32751 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT

#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)

Definition at line 32752 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_AUDIO_DIV_MSB

#define PMU_MISC2_SET_AUDIO_DIV_MSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 32780 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_AUDIO_DIV_MSB_MASK

#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)

Definition at line 32774 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT

#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)

Definition at line 32775 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_PLL3_disable

#define PMU_MISC2_SET_PLL3_disable | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)

Definition at line 32734 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_PLL3_disable_MASK

#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)

Definition at line 32732 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_PLL3_disable_SHIFT

#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)

Definition at line 32733 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_BO_OFFSET

#define PMU_MISC2_SET_REG0_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32722 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_BO_OFFSET_MASK

#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)

Definition at line 32716 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT

#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)

Definition at line 32717 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_BO_STATUS

#define PMU_MISC2_SET_REG0_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 32728 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_BO_STATUS_MASK

#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)

Definition at line 32723 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_BO_STATUS_SHIFT

#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)

Definition at line 32724 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_ENABLE_BO

#define PMU_MISC2_SET_REG0_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)

Definition at line 32731 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_ENABLE_BO_MASK

#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)

Definition at line 32729 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT

#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)

Definition at line 32730 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_STEP_TIME

#define PMU_MISC2_SET_REG0_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32789 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_STEP_TIME_MASK

#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)

Definition at line 32781 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG0_STEP_TIME_SHIFT

#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)

Definition at line 32782 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_BO_OFFSET

#define PMU_MISC2_SET_REG1_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32741 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_BO_OFFSET_MASK

#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)

Definition at line 32735 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT

#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)

Definition at line 32736 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_BO_STATUS

#define PMU_MISC2_SET_REG1_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 32747 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_BO_STATUS_MASK

#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)

Definition at line 32742 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_BO_STATUS_SHIFT

#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)

Definition at line 32743 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_ENABLE_BO

#define PMU_MISC2_SET_REG1_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)

Definition at line 32750 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_ENABLE_BO_MASK

#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)

Definition at line 32748 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT

#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)

Definition at line 32749 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_STEP_TIME

#define PMU_MISC2_SET_REG1_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32798 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_STEP_TIME_MASK

#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)

Definition at line 32790 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG1_STEP_TIME_SHIFT

#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)

Definition at line 32791 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_BO_OFFSET

#define PMU_MISC2_SET_REG2_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32764 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_BO_OFFSET_MASK

#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)

Definition at line 32758 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT

#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)

Definition at line 32759 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_BO_STATUS

#define PMU_MISC2_SET_REG2_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)

Definition at line 32767 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_BO_STATUS_MASK

#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)

Definition at line 32765 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_BO_STATUS_SHIFT

#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)

Definition at line 32766 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_ENABLE_BO

#define PMU_MISC2_SET_REG2_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)

Definition at line 32770 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_ENABLE_BO_MASK

#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)

Definition at line 32768 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT

#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)

Definition at line 32769 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_OK

#define PMU_MISC2_SET_REG2_OK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)

Definition at line 32773 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_OK_MASK

#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)

Definition at line 32771 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_OK_SHIFT

#define PMU_MISC2_SET_REG2_OK_SHIFT (22U)

Definition at line 32772 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_STEP_TIME

#define PMU_MISC2_SET_REG2_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32807 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_STEP_TIME_MASK

#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)

Definition at line 32799 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_REG2_STEP_TIME_SHIFT

#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)

Definition at line 32800 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_VIDEO_DIV

#define PMU_MISC2_SET_VIDEO_DIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

Definition at line 32816 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_VIDEO_DIV_MASK

#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)

Definition at line 32808 of file MIMXRT1062.h.

## ◆ PMU_MISC2_SET_VIDEO_DIV_SHIFT

#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)

Definition at line 32809 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_AUDIO_DIV_LSB

#define PMU_MISC2_TOG_AUDIO_DIV_LSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 32967 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK

#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)

Definition at line 32961 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT

#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)

Definition at line 32962 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_AUDIO_DIV_MSB

#define PMU_MISC2_TOG_AUDIO_DIV_MSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

Definition at line 32990 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK

#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)

Definition at line 32984 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT

#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)

Definition at line 32985 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_PLL3_disable

#define PMU_MISC2_TOG_PLL3_disable | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)

Definition at line 32944 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_PLL3_disable_MASK

#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)

Definition at line 32942 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_PLL3_disable_SHIFT

#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)

Definition at line 32943 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_BO_OFFSET

#define PMU_MISC2_TOG_REG0_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32932 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_BO_OFFSET_MASK

#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)

Definition at line 32926 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT

#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)

Definition at line 32927 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_BO_STATUS

#define PMU_MISC2_TOG_REG0_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 32938 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_BO_STATUS_MASK

#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)

Definition at line 32933 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT

#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)

Definition at line 32934 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_ENABLE_BO

#define PMU_MISC2_TOG_REG0_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)

Definition at line 32941 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_ENABLE_BO_MASK

#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)

Definition at line 32939 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT

#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)

Definition at line 32940 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_STEP_TIME

#define PMU_MISC2_TOG_REG0_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 32999 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_STEP_TIME_MASK

#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)

Definition at line 32991 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT

#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)

Definition at line 32992 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_BO_OFFSET

#define PMU_MISC2_TOG_REG1_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32951 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_BO_OFFSET_MASK

#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)

Definition at line 32945 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT

#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)

Definition at line 32946 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_BO_STATUS

#define PMU_MISC2_TOG_REG1_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

Definition at line 32957 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_BO_STATUS_MASK

#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)

Definition at line 32952 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT

#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)

Definition at line 32953 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_ENABLE_BO

#define PMU_MISC2_TOG_REG1_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)

Definition at line 32960 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_ENABLE_BO_MASK

#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)

Definition at line 32958 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT

#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)

Definition at line 32959 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_STEP_TIME

#define PMU_MISC2_TOG_REG1_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 33008 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_STEP_TIME_MASK

#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)

Definition at line 33000 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT

#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)

Definition at line 33001 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_BO_OFFSET

#define PMU_MISC2_TOG_REG2_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

Definition at line 32974 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_BO_OFFSET_MASK

#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)

Definition at line 32968 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT

#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)

Definition at line 32969 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_BO_STATUS

#define PMU_MISC2_TOG_REG2_BO_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)

Definition at line 32977 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_BO_STATUS_MASK

#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)

Definition at line 32975 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT

#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)

Definition at line 32976 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_ENABLE_BO

#define PMU_MISC2_TOG_REG2_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)

Definition at line 32980 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_ENABLE_BO_MASK

#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)

Definition at line 32978 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT

#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)

Definition at line 32979 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_OK

#define PMU_MISC2_TOG_REG2_OK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)

Definition at line 32983 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_OK_MASK

#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)

Definition at line 32981 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_OK_SHIFT

#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)

Definition at line 32982 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_STEP_TIME

#define PMU_MISC2_TOG_REG2_STEP_TIME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

Definition at line 33017 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_STEP_TIME_MASK

#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)

Definition at line 33009 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT

#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)

Definition at line 33010 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_VIDEO_DIV

#define PMU_MISC2_TOG_VIDEO_DIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

Definition at line 33026 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_VIDEO_DIV_MASK

#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)

Definition at line 33018 of file MIMXRT1062.h.

## ◆ PMU_MISC2_TOG_VIDEO_DIV_SHIFT

#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)

Definition at line 33019 of file MIMXRT1062.h.

## ◆ PMU_MISC2_VIDEO_DIV

#define PMU_MISC2_VIDEO_DIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

Definition at line 32711 of file MIMXRT1062.h.

## ◆ PMU_MISC2_VIDEO_DIV_MASK

#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)

Definition at line 32703 of file MIMXRT1062.h.

## ◆ PMU_MISC2_VIDEO_DIV_SHIFT

#define PMU_MISC2_VIDEO_DIV_SHIFT (30U)

Definition at line 32704 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_BO_OFFSET

#define PMU_REG_1P1_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)

Definition at line 30941 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_BO_OFFSET_MASK

#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)

Definition at line 30939 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_BO_OFFSET_SHIFT

#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)

Definition at line 30940 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_BO_VDD1P1

#define PMU_REG_1P1_BO_VDD1P1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)

Definition at line 30952 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_BO_VDD1P1_MASK

#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)

Definition at line 30950 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_BO_VDD1P1_SHIFT

#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)

Definition at line 30951 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_BO_OFFSET

#define PMU_REG_1P1_CLR_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)

Definition at line 31027 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_BO_OFFSET_MASK

#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)

Definition at line 31025 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_BO_OFFSET_SHIFT

#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)

Definition at line 31026 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_BO_VDD1P1

#define PMU_REG_1P1_CLR_BO_VDD1P1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)

Definition at line 31038 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_BO_VDD1P1_MASK

#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)

Definition at line 31036 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT

#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)

Definition at line 31037 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_BO

#define PMU_REG_1P1_CLR_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)

Definition at line 31018 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_BO_MASK

#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)

Definition at line 31016 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_BO_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)

Definition at line 31017 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_ILIMIT

#define PMU_REG_1P1_CLR_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)

Definition at line 31021 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK

#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31019 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31020 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_LINREG

#define PMU_REG_1P1_CLR_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)

Definition at line 31015 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_LINREG_MASK

#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)

Definition at line 31013 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)

Definition at line 31014 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_PULLDOWN

#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)

Definition at line 31024 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK

#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 31022 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 31023 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG

#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)

Definition at line 31044 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 31042 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 31043 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_OK_VDD1P1

#define PMU_REG_1P1_CLR_OK_VDD1P1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)

Definition at line 31041 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_OK_VDD1P1_MASK

#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)

Definition at line 31039 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT

#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)

Definition at line 31040 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_OUTPUT_TRG

#define PMU_REG_1P1_CLR_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00100..0.8V 0b10000..1.1V 0b000x1..1.375V

Definition at line 31035 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_OUTPUT_TRG_MASK

#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31028 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT

#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)

Definition at line 31029 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_SELREF_WEAK_LINREG

#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)

SELREF_WEAK_LINREG 0b0..Weak-linreg output tracks low-power-bandgap voltage 0b1..Weak-linreg output tracks VDD_SOC_IN voltage

Definition at line 31051 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK

#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)

Definition at line 31045 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)

Definition at line 31046 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_BO

#define PMU_REG_1P1_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)

Definition at line 30932 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_BO_MASK

#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)

Definition at line 30930 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_BO_SHIFT

#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)

Definition at line 30931 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_ILIMIT

#define PMU_REG_1P1_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)

Definition at line 30935 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_ILIMIT_MASK

#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 30933 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_ILIMIT_SHIFT

#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 30934 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_LINREG

#define PMU_REG_1P1_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)

Definition at line 30929 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_LINREG_MASK

#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)

Definition at line 30927 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_LINREG_SHIFT

#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)

Definition at line 30928 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_PULLDOWN

#define PMU_REG_1P1_ENABLE_PULLDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)

Definition at line 30938 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_PULLDOWN_MASK

#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 30936 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 30937 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_WEAK_LINREG

#define PMU_REG_1P1_ENABLE_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)

Definition at line 30958 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 30956 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 30957 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_OK_VDD1P1

#define PMU_REG_1P1_OK_VDD1P1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)

Definition at line 30955 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_OK_VDD1P1_MASK

#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)

Definition at line 30953 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_OK_VDD1P1_SHIFT

#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)

Definition at line 30954 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_OUTPUT_TRG

#define PMU_REG_1P1_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00100..0.8V 0b10000..1.1V 0b000x1..1.375V

Definition at line 30949 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_OUTPUT_TRG_MASK

#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 30942 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_OUTPUT_TRG_SHIFT

#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)

Definition at line 30943 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SELREF_WEAK_LINREG

#define PMU_REG_1P1_SELREF_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)

SELREF_WEAK_LINREG 0b0..Weak-linreg output tracks low-power-bandgap voltage 0b1..Weak-linreg output tracks VDD_SOC_IN voltage

Definition at line 30965 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SELREF_WEAK_LINREG_MASK

#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)

Definition at line 30959 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)

Definition at line 30960 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_BO_OFFSET

#define PMU_REG_1P1_SET_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)

Definition at line 30984 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_BO_OFFSET_MASK

#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)

Definition at line 30982 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_BO_OFFSET_SHIFT

#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)

Definition at line 30983 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_BO_VDD1P1

#define PMU_REG_1P1_SET_BO_VDD1P1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)

Definition at line 30995 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_BO_VDD1P1_MASK

#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)

Definition at line 30993 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_BO_VDD1P1_SHIFT

#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)

Definition at line 30994 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_BO

#define PMU_REG_1P1_SET_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)

Definition at line 30975 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_BO_MASK

#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)

Definition at line 30973 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_BO_SHIFT

#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)

Definition at line 30974 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_ILIMIT

#define PMU_REG_1P1_SET_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)

Definition at line 30978 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK

#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 30976 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT

#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 30977 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_LINREG

#define PMU_REG_1P1_SET_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)

Definition at line 30972 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_LINREG_MASK

#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)

Definition at line 30970 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT

#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)

Definition at line 30971 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_PULLDOWN

#define PMU_REG_1P1_SET_ENABLE_PULLDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)

Definition at line 30981 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK

#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 30979 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 30980 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_WEAK_LINREG

#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)

Definition at line 31001 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 30999 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 31000 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_OK_VDD1P1

#define PMU_REG_1P1_SET_OK_VDD1P1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)

Definition at line 30998 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_OK_VDD1P1_MASK

#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)

Definition at line 30996 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_OK_VDD1P1_SHIFT

#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)

Definition at line 30997 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_OUTPUT_TRG

#define PMU_REG_1P1_SET_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00100..0.8V 0b10000..1.1V 0b000x1..1.375V

Definition at line 30992 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_OUTPUT_TRG_MASK

#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 30985 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT

#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)

Definition at line 30986 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_SELREF_WEAK_LINREG

#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)

SELREF_WEAK_LINREG 0b0..Weak-linreg output tracks low-power-bandgap voltage 0b1..Weak-linreg output tracks VDD_SOC_IN voltage

Definition at line 31008 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK

#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)

Definition at line 31002 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)

Definition at line 31003 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_BO_OFFSET

#define PMU_REG_1P1_TOG_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)

Definition at line 31070 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_BO_OFFSET_MASK

#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)

Definition at line 31068 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_BO_OFFSET_SHIFT

#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)

Definition at line 31069 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_BO_VDD1P1

#define PMU_REG_1P1_TOG_BO_VDD1P1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)

Definition at line 31081 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_BO_VDD1P1_MASK

#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)

Definition at line 31079 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT

#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)

Definition at line 31080 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_BO

#define PMU_REG_1P1_TOG_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)

Definition at line 31061 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_BO_MASK

#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)

Definition at line 31059 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_BO_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)

Definition at line 31060 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_ILIMIT

#define PMU_REG_1P1_TOG_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)

Definition at line 31064 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK

#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31062 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31063 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_LINREG

#define PMU_REG_1P1_TOG_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)

Definition at line 31058 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_LINREG_MASK

#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)

Definition at line 31056 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)

Definition at line 31057 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_PULLDOWN

#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)

Definition at line 31067 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK

#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 31065 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 31066 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG

#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)

Definition at line 31087 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 31085 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 31086 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_OK_VDD1P1

#define PMU_REG_1P1_TOG_OK_VDD1P1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)

Definition at line 31084 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_OK_VDD1P1_MASK

#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)

Definition at line 31082 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT

#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)

Definition at line 31083 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_OUTPUT_TRG

#define PMU_REG_1P1_TOG_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00100..0.8V 0b10000..1.1V 0b000x1..1.375V

Definition at line 31078 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_OUTPUT_TRG_MASK

#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31071 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT

#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)

Definition at line 31072 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_SELREF_WEAK_LINREG

#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)

SELREF_WEAK_LINREG 0b0..Weak-linreg output tracks low-power-bandgap voltage 0b1..Weak-linreg output tracks VDD_SOC_IN voltage

Definition at line 31094 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK

#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)

Definition at line 31088 of file MIMXRT1062.h.

## ◆ PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT

#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)

Definition at line 31089 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_BO_OFFSET

#define PMU_REG_2P5_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)

Definition at line 31261 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_BO_OFFSET_MASK

#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)

Definition at line 31259 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_BO_OFFSET_SHIFT

#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)

Definition at line 31260 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_BO_VDD2P5

#define PMU_REG_2P5_BO_VDD2P5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)

Definition at line 31272 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_BO_VDD2P5_MASK

#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)

Definition at line 31270 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_BO_VDD2P5_SHIFT

#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)

Definition at line 31271 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_BO_OFFSET

#define PMU_REG_2P5_CLR_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)

Definition at line 31333 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_BO_OFFSET_MASK

#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)

Definition at line 31331 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_BO_OFFSET_SHIFT

#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)

Definition at line 31332 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_BO_VDD2P5

#define PMU_REG_2P5_CLR_BO_VDD2P5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)

Definition at line 31344 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_BO_VDD2P5_MASK

#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)

Definition at line 31342 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT

#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)

Definition at line 31343 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_BO

#define PMU_REG_2P5_CLR_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)

Definition at line 31324 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_BO_MASK

#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)

Definition at line 31322 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_BO_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)

Definition at line 31323 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_ILIMIT

#define PMU_REG_2P5_CLR_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)

Definition at line 31327 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK

#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31325 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31326 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_LINREG

#define PMU_REG_2P5_CLR_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)

Definition at line 31321 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_LINREG_MASK

#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)

Definition at line 31319 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)

Definition at line 31320 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_PULLDOWN

#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)

Definition at line 31330 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK

#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 31328 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 31329 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG

#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)

Definition at line 31350 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 31348 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 31349 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_OK_VDD2P5

#define PMU_REG_2P5_CLR_OK_VDD2P5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)

Definition at line 31347 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_OK_VDD2P5_MASK

#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)

Definition at line 31345 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT

#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)

Definition at line 31346 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_OUTPUT_TRG

#define PMU_REG_2P5_CLR_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.10V 0b10000..2.50V 0b11111..2.875V

Definition at line 31341 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_OUTPUT_TRG_MASK

#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31334 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT

#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)

Definition at line 31335 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_BO

#define PMU_REG_2P5_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)

Definition at line 31252 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_BO_MASK

#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)

Definition at line 31250 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_BO_SHIFT

#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)

Definition at line 31251 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_ILIMIT

#define PMU_REG_2P5_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)

Definition at line 31255 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_ILIMIT_MASK

#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31253 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_ILIMIT_SHIFT

#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31254 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_LINREG

#define PMU_REG_2P5_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)

Definition at line 31249 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_LINREG_MASK

#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)

Definition at line 31247 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_LINREG_SHIFT

#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)

Definition at line 31248 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_PULLDOWN

#define PMU_REG_2P5_ENABLE_PULLDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)

Definition at line 31258 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_PULLDOWN_MASK

#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 31256 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 31257 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_WEAK_LINREG

#define PMU_REG_2P5_ENABLE_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)

Definition at line 31278 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 31276 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 31277 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_OK_VDD2P5

#define PMU_REG_2P5_OK_VDD2P5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)

Definition at line 31275 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_OK_VDD2P5_MASK

#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)

Definition at line 31273 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_OK_VDD2P5_SHIFT

#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)

Definition at line 31274 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_OUTPUT_TRG

#define PMU_REG_2P5_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.10V 0b10000..2.50V 0b11111..2.875V

Definition at line 31269 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_OUTPUT_TRG_MASK

#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31262 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_OUTPUT_TRG_SHIFT

#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)

Definition at line 31263 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_BO_OFFSET

#define PMU_REG_2P5_SET_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)

Definition at line 31297 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_BO_OFFSET_MASK

#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)

Definition at line 31295 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_BO_OFFSET_SHIFT

#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)

Definition at line 31296 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_BO_VDD2P5

#define PMU_REG_2P5_SET_BO_VDD2P5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)

Definition at line 31308 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_BO_VDD2P5_MASK

#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)

Definition at line 31306 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_BO_VDD2P5_SHIFT

#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)

Definition at line 31307 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_BO

#define PMU_REG_2P5_SET_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)

Definition at line 31288 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_BO_MASK

#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)

Definition at line 31286 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_BO_SHIFT

#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)

Definition at line 31287 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_ILIMIT

#define PMU_REG_2P5_SET_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)

Definition at line 31291 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK

#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31289 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT

#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31290 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_LINREG

#define PMU_REG_2P5_SET_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)

Definition at line 31285 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_LINREG_MASK

#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)

Definition at line 31283 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT

#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)

Definition at line 31284 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_PULLDOWN

#define PMU_REG_2P5_SET_ENABLE_PULLDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)

Definition at line 31294 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK

#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 31292 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 31293 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_WEAK_LINREG

#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)

Definition at line 31314 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 31312 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 31313 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_OK_VDD2P5

#define PMU_REG_2P5_SET_OK_VDD2P5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)

Definition at line 31311 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_OK_VDD2P5_MASK

#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)

Definition at line 31309 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_OK_VDD2P5_SHIFT

#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)

Definition at line 31310 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_OUTPUT_TRG

#define PMU_REG_2P5_SET_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.10V 0b10000..2.50V 0b11111..2.875V

Definition at line 31305 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_OUTPUT_TRG_MASK

#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31298 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT

#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)

Definition at line 31299 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_BO_OFFSET

#define PMU_REG_2P5_TOG_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)

Definition at line 31369 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_BO_OFFSET_MASK

#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)

Definition at line 31367 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_BO_OFFSET_SHIFT

#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)

Definition at line 31368 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_BO_VDD2P5

#define PMU_REG_2P5_TOG_BO_VDD2P5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)

Definition at line 31380 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_BO_VDD2P5_MASK

#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)

Definition at line 31378 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT

#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)

Definition at line 31379 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_BO

#define PMU_REG_2P5_TOG_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)

Definition at line 31360 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_BO_MASK

#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)

Definition at line 31358 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_BO_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)

Definition at line 31359 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_ILIMIT

#define PMU_REG_2P5_TOG_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)

Definition at line 31363 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK

#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31361 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31362 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_LINREG

#define PMU_REG_2P5_TOG_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)

Definition at line 31357 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_LINREG_MASK

#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)

Definition at line 31355 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)

Definition at line 31356 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_PULLDOWN

#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)

Definition at line 31366 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK

#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)

Definition at line 31364 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)

Definition at line 31365 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG

#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)

Definition at line 31386 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK

#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)

Definition at line 31384 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT

#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)

Definition at line 31385 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_OK_VDD2P5

#define PMU_REG_2P5_TOG_OK_VDD2P5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)

Definition at line 31383 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_OK_VDD2P5_MASK

#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)

Definition at line 31381 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT

#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)

Definition at line 31382 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_OUTPUT_TRG

#define PMU_REG_2P5_TOG_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.10V 0b10000..2.50V 0b11111..2.875V

Definition at line 31377 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_OUTPUT_TRG_MASK

#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31370 of file MIMXRT1062.h.

## ◆ PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT

#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)

Definition at line 31371 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_BO_OFFSET

#define PMU_REG_3P0_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)

Definition at line 31110 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_BO_OFFSET_MASK

#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)

Definition at line 31108 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_BO_OFFSET_SHIFT

#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)

Definition at line 31109 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_BO_VDD3P0

#define PMU_REG_3P0_BO_VDD3P0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)

Definition at line 31128 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_BO_VDD3P0_MASK

#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)

Definition at line 31126 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_BO_VDD3P0_SHIFT

#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)

Definition at line 31127 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_BO_OFFSET

#define PMU_REG_3P0_CLR_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)

Definition at line 31184 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_BO_OFFSET_MASK

#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)

Definition at line 31182 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_BO_OFFSET_SHIFT

#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)

Definition at line 31183 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_BO_VDD3P0

#define PMU_REG_3P0_CLR_BO_VDD3P0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)

Definition at line 31202 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_BO_VDD3P0_MASK

#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)

Definition at line 31200 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT

#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)

Definition at line 31201 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_BO

#define PMU_REG_3P0_CLR_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)

Definition at line 31178 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_BO_MASK

#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)

Definition at line 31176 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_BO_SHIFT

#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)

Definition at line 31177 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_ILIMIT

#define PMU_REG_3P0_CLR_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)

Definition at line 31181 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK

#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31179 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT

#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31180 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_LINREG

#define PMU_REG_3P0_CLR_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)

Definition at line 31175 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_LINREG_MASK

#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)

Definition at line 31173 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT

#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)

Definition at line 31174 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_OK_VDD3P0

#define PMU_REG_3P0_CLR_OK_VDD3P0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)

Definition at line 31205 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_OK_VDD3P0_MASK

#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)

Definition at line 31203 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT

#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)

Definition at line 31204 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_OUTPUT_TRG

#define PMU_REG_3P0_CLR_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.625V 0b01111..3.000V 0b11111..3.400V

Definition at line 31199 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_OUTPUT_TRG_MASK

#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31192 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT

#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)

Definition at line 31193 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_VBUS_SEL

#define PMU_REG_3P0_CLR_VBUS_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)

VBUS_SEL 0b1..Utilize VBUS OTG1 power 0b0..Utilize VBUS OTG2 power

Definition at line 31191 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_VBUS_SEL_MASK

#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)

Definition at line 31185 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_CLR_VBUS_SEL_SHIFT

#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)

Definition at line 31186 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_BO

#define PMU_REG_3P0_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)

Definition at line 31104 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_BO_MASK

#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)

Definition at line 31102 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_BO_SHIFT

#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)

Definition at line 31103 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_ILIMIT

#define PMU_REG_3P0_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)

Definition at line 31107 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_ILIMIT_MASK

#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31105 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_ILIMIT_SHIFT

#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31106 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_LINREG

#define PMU_REG_3P0_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)

Definition at line 31101 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_LINREG_MASK

#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)

Definition at line 31099 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_ENABLE_LINREG_SHIFT

#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)

Definition at line 31100 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_OK_VDD3P0

#define PMU_REG_3P0_OK_VDD3P0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)

Definition at line 31131 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_OK_VDD3P0_MASK

#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)

Definition at line 31129 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_OK_VDD3P0_SHIFT

#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)

Definition at line 31130 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_OUTPUT_TRG

#define PMU_REG_3P0_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.625V 0b01111..3.000V 0b11111..3.400V

Definition at line 31125 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_OUTPUT_TRG_MASK

#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31118 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_OUTPUT_TRG_SHIFT

#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)

Definition at line 31119 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_BO_OFFSET

#define PMU_REG_3P0_SET_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)

Definition at line 31147 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_BO_OFFSET_MASK

#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)

Definition at line 31145 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_BO_OFFSET_SHIFT

#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)

Definition at line 31146 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_BO_VDD3P0

#define PMU_REG_3P0_SET_BO_VDD3P0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)

Definition at line 31165 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_BO_VDD3P0_MASK

#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)

Definition at line 31163 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_BO_VDD3P0_SHIFT

#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)

Definition at line 31164 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_BO

#define PMU_REG_3P0_SET_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)

Definition at line 31141 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_BO_MASK

#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)

Definition at line 31139 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_BO_SHIFT

#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)

Definition at line 31140 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_ILIMIT

#define PMU_REG_3P0_SET_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)

Definition at line 31144 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK

#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31142 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT

#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31143 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_LINREG

#define PMU_REG_3P0_SET_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)

Definition at line 31138 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_LINREG_MASK

#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)

Definition at line 31136 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT

#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)

Definition at line 31137 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_OK_VDD3P0

#define PMU_REG_3P0_SET_OK_VDD3P0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)

Definition at line 31168 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_OK_VDD3P0_MASK

#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)

Definition at line 31166 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_OK_VDD3P0_SHIFT

#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)

Definition at line 31167 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_OUTPUT_TRG

#define PMU_REG_3P0_SET_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.625V 0b01111..3.000V 0b11111..3.400V

Definition at line 31162 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_OUTPUT_TRG_MASK

#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31155 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT

#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)

Definition at line 31156 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_VBUS_SEL

#define PMU_REG_3P0_SET_VBUS_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)

VBUS_SEL 0b1..Utilize VBUS OTG1 power 0b0..Utilize VBUS OTG2 power

Definition at line 31154 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_VBUS_SEL_MASK

#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)

Definition at line 31148 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_SET_VBUS_SEL_SHIFT

#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)

Definition at line 31149 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_BO_OFFSET

#define PMU_REG_3P0_TOG_BO_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)

Definition at line 31221 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_BO_OFFSET_MASK

#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)

Definition at line 31219 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_BO_OFFSET_SHIFT

#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)

Definition at line 31220 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_BO_VDD3P0

#define PMU_REG_3P0_TOG_BO_VDD3P0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)

Definition at line 31239 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_BO_VDD3P0_MASK

#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)

Definition at line 31237 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT

#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)

Definition at line 31238 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_BO

#define PMU_REG_3P0_TOG_ENABLE_BO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)

Definition at line 31215 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_BO_MASK

#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)

Definition at line 31213 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_BO_SHIFT

#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)

Definition at line 31214 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_ILIMIT

#define PMU_REG_3P0_TOG_ENABLE_ILIMIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)

Definition at line 31218 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK

#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)

Definition at line 31216 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT

#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)

Definition at line 31217 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_LINREG

#define PMU_REG_3P0_TOG_ENABLE_LINREG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)

Definition at line 31212 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_LINREG_MASK

#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)

Definition at line 31210 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT

#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)

Definition at line 31211 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_OK_VDD3P0

#define PMU_REG_3P0_TOG_OK_VDD3P0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)

Definition at line 31242 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_OK_VDD3P0_MASK

#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)

Definition at line 31240 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT

#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)

Definition at line 31241 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_OUTPUT_TRG

#define PMU_REG_3P0_TOG_OUTPUT_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)

OUTPUT_TRG 0b00000..2.625V 0b01111..3.000V 0b11111..3.400V

Definition at line 31236 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_OUTPUT_TRG_MASK

#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)

Definition at line 31229 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT

#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)

Definition at line 31230 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_VBUS_SEL

#define PMU_REG_3P0_TOG_VBUS_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)

VBUS_SEL 0b1..Utilize VBUS OTG1 power 0b0..Utilize VBUS OTG2 power

Definition at line 31228 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_VBUS_SEL_MASK

#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)

Definition at line 31222 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_TOG_VBUS_SEL_SHIFT

#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)

Definition at line 31223 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_VBUS_SEL

#define PMU_REG_3P0_VBUS_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)

VBUS_SEL 0b1..Utilize VBUS OTG1 power 0b0..Utilize VBUS OTG2 power

Definition at line 31117 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_VBUS_SEL_MASK

#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)

Definition at line 31111 of file MIMXRT1062.h.

## ◆ PMU_REG_3P0_VBUS_SEL_SHIFT

#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)

Definition at line 31112 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_FET_ODRIVE

#define PMU_REG_CORE_CLR_FET_ODRIVE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)

Definition at line 31755 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_FET_ODRIVE_MASK

#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)

Definition at line 31753 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT

#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)

Definition at line 31754 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_RAMP_RATE

#define PMU_REG_CORE_CLR_RAMP_RATE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)

RAMP_RATE 0b00..Fast 0b01..Medium Fast 0b10..Medium Slow 0b11..Slow

Definition at line 31752 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_RAMP_RATE_MASK

#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)

Definition at line 31744 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_RAMP_RATE_SHIFT

#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)

Definition at line 31745 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG0_ADJ

#define PMU_REG_CORE_CLR_REG0_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)

REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31671 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG0_ADJ_MASK

#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)

Definition at line 31649 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG0_ADJ_SHIFT

#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)

Definition at line 31650 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG0_TARG

#define PMU_REG_CORE_CLR_REG0_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)

REG0_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31648 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG0_TARG_MASK

#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)

Definition at line 31637 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG0_TARG_SHIFT

#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)

Definition at line 31638 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG1_ADJ

#define PMU_REG_CORE_CLR_REG1_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)

REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31708 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG1_ADJ_MASK

#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)

Definition at line 31686 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG1_ADJ_SHIFT

#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)

Definition at line 31687 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG1_TARG

#define PMU_REG_CORE_CLR_REG1_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)

REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31685 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG1_TARG_MASK

#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)

Definition at line 31672 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG1_TARG_SHIFT

#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)

Definition at line 31673 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG2_ADJ

#define PMU_REG_CORE_CLR_REG2_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)

REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31743 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG2_ADJ_MASK

#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)

Definition at line 31721 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG2_ADJ_SHIFT

#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)

Definition at line 31722 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG2_TARG

#define PMU_REG_CORE_CLR_REG2_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)

REG2_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31720 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG2_TARG_MASK

#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)

Definition at line 31709 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_CLR_REG2_TARG_SHIFT

#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)

Definition at line 31710 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_FET_ODRIVE

#define PMU_REG_CORE_FET_ODRIVE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)

Definition at line 31509 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_FET_ODRIVE_MASK

#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)

Definition at line 31507 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_FET_ODRIVE_SHIFT

#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)

Definition at line 31508 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_RAMP_RATE

#define PMU_REG_CORE_RAMP_RATE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)

RAMP_RATE 0b00..Fast 0b01..Medium Fast 0b10..Medium Slow 0b11..Slow

Definition at line 31506 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_RAMP_RATE_MASK

#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)

Definition at line 31498 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_RAMP_RATE_SHIFT

#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)

Definition at line 31499 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG0_ADJ

#define PMU_REG_CORE_REG0_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)

REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31425 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG0_ADJ_MASK

#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)

Definition at line 31403 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG0_ADJ_SHIFT

#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)

Definition at line 31404 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG0_TARG

#define PMU_REG_CORE_REG0_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)

REG0_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31402 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG0_TARG_MASK

#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)

Definition at line 31391 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG0_TARG_SHIFT

#define PMU_REG_CORE_REG0_TARG_SHIFT (0U)

Definition at line 31392 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG1_ADJ

#define PMU_REG_CORE_REG1_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)

REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31462 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG1_ADJ_MASK

#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)

Definition at line 31440 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG1_ADJ_SHIFT

#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)

Definition at line 31441 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG1_TARG

#define PMU_REG_CORE_REG1_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)

REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31439 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG1_TARG_MASK

#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)

Definition at line 31426 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG1_TARG_SHIFT

#define PMU_REG_CORE_REG1_TARG_SHIFT (9U)

Definition at line 31427 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG2_ADJ

#define PMU_REG_CORE_REG2_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)

REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31497 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG2_ADJ_MASK

#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)

Definition at line 31475 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG2_ADJ_SHIFT

#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)

Definition at line 31476 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG2_TARG

#define PMU_REG_CORE_REG2_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)

REG2_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31474 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG2_TARG_MASK

#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)

Definition at line 31463 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_REG2_TARG_SHIFT

#define PMU_REG_CORE_REG2_TARG_SHIFT (18U)

Definition at line 31464 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_FET_ODRIVE

#define PMU_REG_CORE_SET_FET_ODRIVE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)

Definition at line 31632 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_FET_ODRIVE_MASK

#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)

Definition at line 31630 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_FET_ODRIVE_SHIFT

#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)

Definition at line 31631 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_RAMP_RATE

#define PMU_REG_CORE_SET_RAMP_RATE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)

RAMP_RATE 0b00..Fast 0b01..Medium Fast 0b10..Medium Slow 0b11..Slow

Definition at line 31629 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_RAMP_RATE_MASK

#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)

Definition at line 31621 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_RAMP_RATE_SHIFT

#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)

Definition at line 31622 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG0_ADJ

#define PMU_REG_CORE_SET_REG0_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)

REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31548 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG0_ADJ_MASK

#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)

Definition at line 31526 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG0_ADJ_SHIFT

#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)

Definition at line 31527 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG0_TARG

#define PMU_REG_CORE_SET_REG0_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)

REG0_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31525 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG0_TARG_MASK

#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)

Definition at line 31514 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG0_TARG_SHIFT

#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)

Definition at line 31515 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG1_ADJ

#define PMU_REG_CORE_SET_REG1_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)

REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31585 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG1_ADJ_MASK

#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)

Definition at line 31563 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG1_ADJ_SHIFT

#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)

Definition at line 31564 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG1_TARG

#define PMU_REG_CORE_SET_REG1_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)

REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31562 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG1_TARG_MASK

#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)

Definition at line 31549 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG1_TARG_SHIFT

#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)

Definition at line 31550 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG2_ADJ

#define PMU_REG_CORE_SET_REG2_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)

REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31620 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG2_ADJ_MASK

#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)

Definition at line 31598 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG2_ADJ_SHIFT

#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)

Definition at line 31599 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG2_TARG

#define PMU_REG_CORE_SET_REG2_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)

REG2_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31597 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG2_TARG_MASK

#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)

Definition at line 31586 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_SET_REG2_TARG_SHIFT

#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)

Definition at line 31587 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_FET_ODRIVE

#define PMU_REG_CORE_TOG_FET_ODRIVE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)

Definition at line 31878 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_FET_ODRIVE_MASK

#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)

Definition at line 31876 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT

#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)

Definition at line 31877 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_RAMP_RATE

#define PMU_REG_CORE_TOG_RAMP_RATE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)

RAMP_RATE 0b00..Fast 0b01..Medium Fast 0b10..Medium Slow 0b11..Slow

Definition at line 31875 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_RAMP_RATE_MASK

#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)

Definition at line 31867 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_RAMP_RATE_SHIFT

#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)

Definition at line 31868 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG0_ADJ

#define PMU_REG_CORE_TOG_REG0_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)

REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31794 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG0_ADJ_MASK

#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)

Definition at line 31772 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG0_ADJ_SHIFT

#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)

Definition at line 31773 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG0_TARG

#define PMU_REG_CORE_TOG_REG0_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)

REG0_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31771 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG0_TARG_MASK

#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)

Definition at line 31760 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG0_TARG_SHIFT

#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)

Definition at line 31761 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG1_ADJ

#define PMU_REG_CORE_TOG_REG1_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)

REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31831 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG1_ADJ_MASK

#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)

Definition at line 31809 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG1_ADJ_SHIFT

#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)

Definition at line 31810 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG1_TARG

#define PMU_REG_CORE_TOG_REG1_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)

REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31808 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG1_TARG_MASK

#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)

Definition at line 31795 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG1_TARG_SHIFT

#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)

Definition at line 31796 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG2_ADJ

#define PMU_REG_CORE_TOG_REG2_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)

REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0b0000..No adjustment 0b0001..+ 0.25% 0b0010..+ 0.50% 0b0011..+ 0.75% 0b0100..+ 1.00% 0b0101..+ 1.25% 0b0110..+ 1.50% 0b0111..+ 1.75% 0b1000..- 0.25% 0b1001..- 0.50% 0b1010..- 0.75% 0b1011..- 1.00% 0b1100..- 1.25% 0b1101..- 1.50% 0b1110..- 1.75% 0b1111..- 2.00%

Definition at line 31866 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG2_ADJ_MASK

#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)

Definition at line 31844 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG2_ADJ_SHIFT

#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)

Definition at line 31845 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG2_TARG

#define PMU_REG_CORE_TOG_REG2_TARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)

REG2_TARG 0b00000..Power gated off 0b00001..Target core voltage = 0.725V 0b00010..Target core voltage = 0.750V 0b00011..Target core voltage = 0.775V 0b10000..Target core voltage = 1.100V 0b11110..Target core voltage = 1.450V 0b11111..Power FET switched full on. No regulation.

Definition at line 31843 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG2_TARG_MASK

#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)

Definition at line 31832 of file MIMXRT1062.h.

## ◆ PMU_REG_CORE_TOG_REG2_TARG_SHIFT

#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)

Definition at line 31833 of file MIMXRT1062.h.