Callisto4Bootloader: Edma_request

Callisto4Bootloader

Modules | Typedefs | Enumerations
Edma_request
Mapping Information

## Modules

| Iomuxc_pads

## Typedefs

typedef enum _dma_request_source | dma_request_source_t
| Structure for the DMA hardware request. More...

## Enumerations

enum

_dma_request_source {
kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, kDmaRequestMuxLPUART1Tx = 2|0x100U, kDmaRequestMuxLPUART1Rx = 3|0x100U,
kDmaRequestMuxLPUART3Tx = 4|0x100U, kDmaRequestMuxLPUART3Rx = 5|0x100U, kDmaRequestMuxLPUART5Tx = 6|0x100U, kDmaRequestMuxLPUART5Rx = 7|0x100U,
kDmaRequestMuxLPUART7Tx = 8|0x100U, kDmaRequestMuxLPUART7Rx = 9|0x100U, kDmaRequestMuxCAN3 = 11|0x100U, kDmaRequestMuxCSI = 12|0x100U,
kDmaRequestMuxLPSPI1Rx = 13|0x100U, kDmaRequestMuxLPSPI1Tx = 14|0x100U, kDmaRequestMuxLPSPI3Rx = 15|0x100U, kDmaRequestMuxLPSPI3Tx = 16|0x100U,
kDmaRequestMuxLPI2C1 = 17|0x100U, kDmaRequestMuxLPI2C3 = 18|0x100U, kDmaRequestMuxSai1Rx = 19|0x100U, kDmaRequestMuxSai1Tx = 20|0x100U,
kDmaRequestMuxSai2Rx = 21|0x100U, kDmaRequestMuxSai2Tx = 22|0x100U, kDmaRequestMuxADC_ETC = 23|0x100U, kDmaRequestMuxADC1 = 24|0x100U,
kDmaRequestMuxACMP1 = 25|0x100U, kDmaRequestMuxACMP3 = 26|0x100U, kDmaRequestMuxFlexSPIRx = 28|0x100U, kDmaRequestMuxFlexSPITx = 29|0x100U,
kDmaRequestMuxXBAR1Request0 = 30|0x100U, kDmaRequestMuxXBAR1Request1 = 31|0x100U, kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U,
kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U,
kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U,
kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U,
kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,
kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U,
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U,
kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, kDmaRequestMuxFlexSPI2Rx = 60|0x100U, kDmaRequestMuxFlexSPI2Tx = 61|0x100U,
kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, kDmaRequestMuxLPUART2Tx = 66|0x100U, kDmaRequestMuxLPUART2Rx = 67|0x100U,
kDmaRequestMuxLPUART4Tx = 68|0x100U, kDmaRequestMuxLPUART4Rx = 69|0x100U, kDmaRequestMuxLPUART6Tx = 70|0x100U, kDmaRequestMuxLPUART6Rx = 71|0x100U,
kDmaRequestMuxLPUART8Tx = 72|0x100U, kDmaRequestMuxLPUART8Rx = 73|0x100U, kDmaRequestMuxPxp = 75|0x100U, kDmaRequestMuxLCDIF = 76|0x100U,
kDmaRequestMuxLPSPI2Rx = 77|0x100U, kDmaRequestMuxLPSPI2Tx = 78|0x100U, kDmaRequestMuxLPSPI4Rx = 79|0x100U, kDmaRequestMuxLPSPI4Tx = 80|0x100U,
kDmaRequestMuxLPI2C2 = 81|0x100U, kDmaRequestMuxLPI2C4 = 82|0x100U, kDmaRequestMuxSai3Rx = 83|0x100U, kDmaRequestMuxSai3Tx = 84|0x100U,
kDmaRequestMuxSpdifRx = 85|0x100U, kDmaRequestMuxSpdifTx = 86|0x100U, kDmaRequestMuxADC2 = 88|0x100U, kDmaRequestMuxACMP2 = 89|0x100U,
kDmaRequestMuxACMP4 = 90|0x100U, kDmaRequestMuxEnetTimer0 = 92|0x100U, kDmaRequestMuxEnetTimer1 = 93|0x100U, kDmaRequestMuxXBAR1Request2 = 94|0x100U,
kDmaRequestMuxXBAR1Request3 = 95|0x100U, kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U,
kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U,
kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U,
kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U,
kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,
kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U,
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U,
kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, kDmaRequestMuxEnet2Timer0 = 124|0x100U, kDmaRequestMuxEnet2Timer1 = 125|0x100U
}

| Structure for the DMA hardware request. More...

## Detailed Description

Mapping Information

## Typedef Documentation

## ◆ dma_request_source_t

typedef enum _dma_request_source dma_request_source_t

Structure for the DMA hardware request.

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

## Enumeration Type Documentation

## ◆ _dma_request_source

enum _dma_request_source

Structure for the DMA hardware request.

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

Enumerator
kDmaRequestMuxFlexIO1Request0Request1 | FlexIO1 Request0 and Request1
kDmaRequestMuxFlexIO2Request0Request1 | FlexIO2 Request0 and Request1
kDmaRequestMuxLPUART1Tx | LPUART1 Transmit
kDmaRequestMuxLPUART1Rx | LPUART1 Receive
kDmaRequestMuxLPUART3Tx | LPUART3 Transmit
kDmaRequestMuxLPUART3Rx | LPUART3 Receive
kDmaRequestMuxLPUART5Tx | LPUART5 Transmit
kDmaRequestMuxLPUART5Rx | LPUART5 Receive
kDmaRequestMuxLPUART7Tx | LPUART7 Transmit
kDmaRequestMuxLPUART7Rx | LPUART7 Receive
kDmaRequestMuxCAN3 | CAN3
kDmaRequestMuxCSI | CSI
kDmaRequestMuxLPSPI1Rx | LPSPI1 Receive
kDmaRequestMuxLPSPI1Tx | LPSPI1 Transmit
kDmaRequestMuxLPSPI3Rx | LPSPI3 Receive
kDmaRequestMuxLPSPI3Tx | LPSPI3 Transmit
kDmaRequestMuxLPI2C1 | LPI2C1
kDmaRequestMuxLPI2C3 | LPI2C3
kDmaRequestMuxSai1Rx | SAI1 Receive
kDmaRequestMuxSai1Tx | SAI1 Transmit
kDmaRequestMuxSai2Rx | SAI2 Receive
kDmaRequestMuxSai2Tx | SAI2 Transmit
kDmaRequestMuxADC_ETC | ADC_ETC
kDmaRequestMuxADC1 | ADC1
kDmaRequestMuxACMP1 | ACMP1
kDmaRequestMuxACMP3 | ACMP3
kDmaRequestMuxFlexSPIRx | FlexSPI Receive
kDmaRequestMuxFlexSPITx | FlexSPI Transmit
kDmaRequestMuxXBAR1Request0 | XBAR1 Request 0
kDmaRequestMuxXBAR1Request1 | XBAR1 Request 1
kDmaRequestMuxFlexPWM1CaptureSub0 | FlexPWM1 Capture sub-module0
kDmaRequestMuxFlexPWM1CaptureSub1 | FlexPWM1 Capture sub-module1
kDmaRequestMuxFlexPWM1CaptureSub2 | FlexPWM1 Capture sub-module2
kDmaRequestMuxFlexPWM1CaptureSub3 | FlexPWM1 Capture sub-module3
kDmaRequestMuxFlexPWM1ValueSub0 | FlexPWM1 Value sub-module0
kDmaRequestMuxFlexPWM1ValueSub1 | FlexPWM1 Value sub-module1
kDmaRequestMuxFlexPWM1ValueSub2 | FlexPWM1 Value sub-module2
kDmaRequestMuxFlexPWM1ValueSub3 | FlexPWM1 Value sub-module3
kDmaRequestMuxFlexPWM3CaptureSub0 | FlexPWM3 Capture sub-module0
kDmaRequestMuxFlexPWM3CaptureSub1 | FlexPWM3 Capture sub-module1
kDmaRequestMuxFlexPWM3CaptureSub2 | FlexPWM3 Capture sub-module2
kDmaRequestMuxFlexPWM3CaptureSub3 | FlexPWM3 Capture sub-module3
kDmaRequestMuxFlexPWM3ValueSub0 | FlexPWM3 Value sub-module0
kDmaRequestMuxFlexPWM3ValueSub1 | FlexPWM3 Value sub-module1
kDmaRequestMuxFlexPWM3ValueSub2 | FlexPWM3 Value sub-module2
kDmaRequestMuxFlexPWM3ValueSub3 | FlexPWM3 Value sub-module3
kDmaRequestMuxQTIMER1CaptTimer0 | TMR1 Capture timer 0
kDmaRequestMuxQTIMER1CaptTimer1 | TMR1 Capture timer 1
kDmaRequestMuxQTIMER1CaptTimer2 | TMR1 Capture timer 2
kDmaRequestMuxQTIMER1CaptTimer3 | TMR1 Capture timer 3
kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 | TMR1 cmpld1 in timer 0 or cmpld2 in timer 1
kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 | TMR1 cmpld1 in timer 1 or cmpld2 in timer 0
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 | TMR1 cmpld1 in timer 2 or cmpld2 in timer 3
kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 | TMR1 cmpld1 in timer 3 or cmpld2 in timer 2
kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 | TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1
kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 | TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0
kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 | TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3
kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 | TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2
kDmaRequestMuxFlexSPI2Rx | FlexSPI2 Receive
kDmaRequestMuxFlexSPI2Tx | FlexSPI2 Transmit
kDmaRequestMuxFlexIO1Request2Request3 | FlexIO1 Request2 and Request3
kDmaRequestMuxFlexIO2Request2Request3 | FlexIO2 Request2 and Request3
kDmaRequestMuxLPUART2Tx | LPUART2 Transmit
kDmaRequestMuxLPUART2Rx | LPUART2 Receive
kDmaRequestMuxLPUART4Tx | LPUART4 Transmit
kDmaRequestMuxLPUART4Rx | LPUART4 Receive
kDmaRequestMuxLPUART6Tx | LPUART6 Transmit
kDmaRequestMuxLPUART6Rx | LPUART6 Receive
kDmaRequestMuxLPUART8Tx | LPUART8 Transmit
kDmaRequestMuxLPUART8Rx | LPUART8 Receive
kDmaRequestMuxPxp | PXP
kDmaRequestMuxLCDIF | LCDIF
kDmaRequestMuxLPSPI2Rx | LPSPI2 Receive
kDmaRequestMuxLPSPI2Tx | LPSPI2 Transmit
kDmaRequestMuxLPSPI4Rx | LPSPI4 Receive
kDmaRequestMuxLPSPI4Tx | LPSPI4 Transmit
kDmaRequestMuxLPI2C2 | LPI2C2
kDmaRequestMuxLPI2C4 | LPI2C4
kDmaRequestMuxSai3Rx | SAI3 Receive
kDmaRequestMuxSai3Tx | SAI3 Transmit
kDmaRequestMuxSpdifRx | SPDIF Receive
kDmaRequestMuxSpdifTx | SPDIF Transmit
kDmaRequestMuxADC2 | ADC2
kDmaRequestMuxACMP2 | ACMP2
kDmaRequestMuxACMP4 | ACMP4
kDmaRequestMuxEnetTimer0 | ENET Timer0
kDmaRequestMuxEnetTimer1 | ENET Timer1
kDmaRequestMuxXBAR1Request2 | XBAR1 Request 2
kDmaRequestMuxXBAR1Request3 | XBAR1 Request 3
kDmaRequestMuxFlexPWM2CaptureSub0 | FlexPWM2 Capture sub-module0
kDmaRequestMuxFlexPWM2CaptureSub1 | FlexPWM2 Capture sub-module1
kDmaRequestMuxFlexPWM2CaptureSub2 | FlexPWM2 Capture sub-module2
kDmaRequestMuxFlexPWM2CaptureSub3 | FlexPWM2 Capture sub-module3
kDmaRequestMuxFlexPWM2ValueSub0 | FlexPWM2 Value sub-module0
kDmaRequestMuxFlexPWM2ValueSub1 | FlexPWM2 Value sub-module1
kDmaRequestMuxFlexPWM2ValueSub2 | FlexPWM2 Value sub-module2
kDmaRequestMuxFlexPWM2ValueSub3 | FlexPWM2 Value sub-module3
kDmaRequestMuxFlexPWM4CaptureSub0 | FlexPWM4 Capture sub-module0
kDmaRequestMuxFlexPWM4CaptureSub1 | FlexPWM4 Capture sub-module1
kDmaRequestMuxFlexPWM4CaptureSub2 | FlexPWM4 Capture sub-module2
kDmaRequestMuxFlexPWM4CaptureSub3 | FlexPWM4 Capture sub-module3
kDmaRequestMuxFlexPWM4ValueSub0 | FlexPWM4 Value sub-module0
kDmaRequestMuxFlexPWM4ValueSub1 | FlexPWM4 Value sub-module1
kDmaRequestMuxFlexPWM4ValueSub2 | FlexPWM4 Value sub-module2
kDmaRequestMuxFlexPWM4ValueSub3 | FlexPWM4 Value sub-module3
kDmaRequestMuxQTIMER2CaptTimer0 | TMR2 Capture timer 0
kDmaRequestMuxQTIMER2CaptTimer1 | TMR2 Capture timer 1
kDmaRequestMuxQTIMER2CaptTimer2 | TMR2 Capture timer 2
kDmaRequestMuxQTIMER2CaptTimer3 | TMR2 Capture timer 3
kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 | TMR2 cmpld1 in timer 0 or cmpld2 in timer 1
kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 | TMR2 cmpld1 in timer 1 or cmpld2 in timer 0
kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 | TMR2 cmpld1 in timer 2 or cmpld2 in timer 3
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 | TMR2 cmpld1 in timer 3 or cmpld2 in timer 2
kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 | TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1
kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 | TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0
kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 | TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3
kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 | TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2
kDmaRequestMuxEnet2Timer0 | ENET2 Timer0
kDmaRequestMuxEnet2Timer1 | ENET2 Timer1

Definition at line 305 of file MIMXRT1062.h.