Callisto4Bootloader: AIPSTZ Register Masks

Callisto4Bootloader

AIPSTZ Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » AIPSTZ Peripheral Access Layer

## MPR - Master Priviledge Registers

#define | AIPSTZ_MPR_MPROT5_MASK (0xF00U)
#define | AIPSTZ_MPR_MPROT5_SHIFT (8U)
#define | AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
#define | AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
#define | AIPSTZ_MPR_MPROT3_SHIFT (16U)
#define | AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
#define | AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
#define | AIPSTZ_MPR_MPROT2_SHIFT (20U)
#define | AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
#define | AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
#define | AIPSTZ_MPR_MPROT1_SHIFT (24U)
#define | AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
#define | AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
#define | AIPSTZ_MPR_MPROT0_SHIFT (28U)
#define | AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)

## OPACR - Off-Platform Peripheral Access Control Registers

#define | AIPSTZ_OPACR_OPAC7_MASK (0xFU)
#define | AIPSTZ_OPACR_OPAC7_SHIFT (0U)
#define | AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
#define | AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
#define | AIPSTZ_OPACR_OPAC6_SHIFT (4U)
#define | AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
#define | AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
#define | AIPSTZ_OPACR_OPAC5_SHIFT (8U)
#define | AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
#define | AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
#define | AIPSTZ_OPACR_OPAC4_SHIFT (12U)
#define | AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
#define | AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
#define | AIPSTZ_OPACR_OPAC3_SHIFT (16U)
#define | AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
#define | AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
#define | AIPSTZ_OPACR_OPAC2_SHIFT (20U)
#define | AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
#define | AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
#define | AIPSTZ_OPACR_OPAC1_SHIFT (24U)
#define | AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
#define | AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
#define | AIPSTZ_OPACR_OPAC0_SHIFT (28U)
#define | AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)

## OPACR1 - Off-Platform Peripheral Access Control Registers

#define | AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
#define | AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
#define | AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
#define | AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
#define | AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
#define | AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
#define | AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
#define | AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
#define | AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
#define | AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
#define | AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
#define | AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
#define | AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
#define | AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
#define | AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
#define | AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
#define | AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
#define | AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
#define | AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
#define | AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
#define | AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
#define | AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
#define | AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
#define | AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)

## OPACR2 - Off-Platform Peripheral Access Control Registers

#define | AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
#define | AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
#define | AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
#define | AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
#define | AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
#define | AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
#define | AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
#define | AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
#define | AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
#define | AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
#define | AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
#define | AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
#define | AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
#define | AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
#define | AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
#define | AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
#define | AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
#define | AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
#define | AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
#define | AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
#define | AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
#define | AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
#define | AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
#define | AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)

## OPACR3 - Off-Platform Peripheral Access Control Registers

#define | AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
#define | AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
#define | AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
#define | AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
#define | AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
#define | AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
#define | AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
#define | AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
#define | AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
#define | AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
#define | AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
#define | AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
#define | AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
#define | AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
#define | AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
#define | AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
#define | AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
#define | AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
#define | AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
#define | AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
#define | AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
#define | AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
#define | AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
#define | AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)

## OPACR4 - Off-Platform Peripheral Access Control Registers

#define | AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
#define | AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
#define | AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
#define | AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
#define | AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
#define | AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ AIPSTZ_MPR_MPROT0

#define AIPSTZ_MPR_MPROT0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)

MPROT0 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

Definition at line 2283 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT0_MASK

#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)

Definition at line 2272 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT0_SHIFT

#define AIPSTZ_MPR_MPROT0_SHIFT (28U)

Definition at line 2273 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT1

#define AIPSTZ_MPR_MPROT1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)

MPROT1 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

Definition at line 2271 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT1_MASK

#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)

Definition at line 2260 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT1_SHIFT

#define AIPSTZ_MPR_MPROT1_SHIFT (24U)

Definition at line 2261 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT2

#define AIPSTZ_MPR_MPROT2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)

MPROT2 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

Definition at line 2259 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT2_MASK

#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)

Definition at line 2248 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT2_SHIFT

#define AIPSTZ_MPR_MPROT2_SHIFT (20U)

Definition at line 2249 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT3

#define AIPSTZ_MPR_MPROT3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)

MPROT3 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

Definition at line 2247 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT3_MASK

#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)

Definition at line 2236 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT3_SHIFT

#define AIPSTZ_MPR_MPROT3_SHIFT (16U)

Definition at line 2237 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT5

#define AIPSTZ_MPR_MPROT5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)

MPROT5 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

Definition at line 2235 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT5_MASK

#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)

Definition at line 2224 of file MIMXRT1062.h.

## ◆ AIPSTZ_MPR_MPROT5_SHIFT

#define AIPSTZ_MPR_MPROT5_SHIFT (8U)

Definition at line 2225 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC10

#define AIPSTZ_OPACR1_OPAC10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)

OPAC10 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2529 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC10_MASK

#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)

Definition at line 2513 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC10_SHIFT

#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)

Definition at line 2514 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC11

#define AIPSTZ_OPACR1_OPAC11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)

OPAC11 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2512 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC11_MASK

#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)

Definition at line 2496 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC11_SHIFT

#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)

Definition at line 2497 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC12

#define AIPSTZ_OPACR1_OPAC12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)

OPAC12 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2495 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC12_MASK

#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)

Definition at line 2479 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC12_SHIFT

#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)

Definition at line 2480 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC13

#define AIPSTZ_OPACR1_OPAC13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)

OPAC13 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2478 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC13_MASK

#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)

Definition at line 2462 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC13_SHIFT

#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)

Definition at line 2463 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC14

#define AIPSTZ_OPACR1_OPAC14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)

OPAC14 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2461 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC14_MASK

#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)

Definition at line 2445 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC14_SHIFT

#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)

Definition at line 2446 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC15

#define AIPSTZ_OPACR1_OPAC15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)

OPAC15 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2444 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC15_MASK

#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)

Definition at line 2428 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC15_SHIFT

#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)

Definition at line 2429 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC8

#define AIPSTZ_OPACR1_OPAC8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)

OPAC8 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2563 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC8_MASK

#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)

Definition at line 2547 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC8_SHIFT

#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)

Definition at line 2548 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC9

#define AIPSTZ_OPACR1_OPAC9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)

OPAC9 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2546 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC9_MASK

#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)

Definition at line 2530 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR1_OPAC9_SHIFT

#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)

Definition at line 2531 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC16

#define AIPSTZ_OPACR2_OPAC16 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)

OPAC16 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2703 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC16_MASK

#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)

Definition at line 2687 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC16_SHIFT

#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)

Definition at line 2688 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC17

#define AIPSTZ_OPACR2_OPAC17 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)

OPAC17 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2686 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC17_MASK

#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)

Definition at line 2670 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC17_SHIFT

#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)

Definition at line 2671 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC18

#define AIPSTZ_OPACR2_OPAC18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)

OPAC18 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2669 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC18_MASK

#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)

Definition at line 2653 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC18_SHIFT

#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)

Definition at line 2654 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC19

#define AIPSTZ_OPACR2_OPAC19 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)

OPAC19 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2652 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC19_MASK

#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)

Definition at line 2636 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC19_SHIFT

#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)

Definition at line 2637 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC20

#define AIPSTZ_OPACR2_OPAC20 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)

OPAC20 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2635 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC20_MASK

#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)

Definition at line 2619 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC20_SHIFT

#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)

Definition at line 2620 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC21

#define AIPSTZ_OPACR2_OPAC21 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)

OPAC21 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2618 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC21_MASK

#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)

Definition at line 2602 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC21_SHIFT

#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)

Definition at line 2603 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC22

#define AIPSTZ_OPACR2_OPAC22 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)

OPAC22 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2601 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC22_MASK

#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)

Definition at line 2585 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC22_SHIFT

#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)

Definition at line 2586 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC23

#define AIPSTZ_OPACR2_OPAC23 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)

OPAC23 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2584 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC23_MASK

#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)

Definition at line 2568 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR2_OPAC23_SHIFT

#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)

Definition at line 2569 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC24

#define AIPSTZ_OPACR3_OPAC24 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)

OPAC24 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2843 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC24_MASK

#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)

Definition at line 2827 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC24_SHIFT

#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)

Definition at line 2828 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC25

#define AIPSTZ_OPACR3_OPAC25 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)

OPAC25 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2826 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC25_MASK

#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)

Definition at line 2810 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC25_SHIFT

#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)

Definition at line 2811 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC26

#define AIPSTZ_OPACR3_OPAC26 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)

OPAC26 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2809 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC26_MASK

#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)

Definition at line 2793 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC26_SHIFT

#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)

Definition at line 2794 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC27

#define AIPSTZ_OPACR3_OPAC27 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)

OPAC27 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2792 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC27_MASK

#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)

Definition at line 2776 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC27_SHIFT

#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)

Definition at line 2777 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC28

#define AIPSTZ_OPACR3_OPAC28 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)

OPAC28 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2775 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC28_MASK

#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)

Definition at line 2759 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC28_SHIFT

#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)

Definition at line 2760 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC29

#define AIPSTZ_OPACR3_OPAC29 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)

OPAC29 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2758 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC29_MASK

#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)

Definition at line 2742 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC29_SHIFT

#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)

Definition at line 2743 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC30

#define AIPSTZ_OPACR3_OPAC30 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)

OPAC30 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2741 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC30_MASK

#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)

Definition at line 2725 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC30_SHIFT

#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)

Definition at line 2726 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC31

#define AIPSTZ_OPACR3_OPAC31 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)

OPAC31 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2724 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC31_MASK

#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)

Definition at line 2708 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR3_OPAC31_SHIFT

#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)

Definition at line 2709 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR4_OPAC32

#define AIPSTZ_OPACR4_OPAC32 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)

OPAC32 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2881 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR4_OPAC32_MASK

#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)

Definition at line 2865 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR4_OPAC32_SHIFT

#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)

Definition at line 2866 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR4_OPAC33

#define AIPSTZ_OPACR4_OPAC33 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)

OPAC33 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2864 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR4_OPAC33_MASK

#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)

Definition at line 2848 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR4_OPAC33_SHIFT

#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)

Definition at line 2849 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC0

#define AIPSTZ_OPACR_OPAC0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)

OPAC0 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2423 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC0_MASK

#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)

Definition at line 2407 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC0_SHIFT

#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)

Definition at line 2408 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC1

#define AIPSTZ_OPACR_OPAC1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)

OPAC1 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2406 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC1_MASK

#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)

Definition at line 2390 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC1_SHIFT

#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)

Definition at line 2391 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC2

#define AIPSTZ_OPACR_OPAC2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)

OPAC2 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2389 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC2_MASK

#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)

Definition at line 2373 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC2_SHIFT

#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)

Definition at line 2374 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC3

#define AIPSTZ_OPACR_OPAC3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)

OPAC3 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2372 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC3_MASK

#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)

Definition at line 2356 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC3_SHIFT

#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)

Definition at line 2357 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC4

#define AIPSTZ_OPACR_OPAC4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)

OPAC4 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2355 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC4_MASK

#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)

Definition at line 2339 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC4_SHIFT

#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)

Definition at line 2340 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC5

#define AIPSTZ_OPACR_OPAC5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)

OPAC5 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2338 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC5_MASK

#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)

Definition at line 2322 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC5_SHIFT

#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)

Definition at line 2323 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC6

#define AIPSTZ_OPACR_OPAC6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)

OPAC6 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2321 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC6_MASK

#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)

Definition at line 2305 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC6_SHIFT

#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)

Definition at line 2306 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC7

#define AIPSTZ_OPACR_OPAC7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)

OPAC7 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

Definition at line 2304 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC7_MASK

#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)

Definition at line 2288 of file MIMXRT1062.h.

## ◆ AIPSTZ_OPACR_OPAC7_SHIFT

#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)

Definition at line 2289 of file MIMXRT1062.h.