Callisto4Bootloader: FLEXRAM Register Masks

Callisto4Bootloader

FLEXRAM Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » FLEXRAM Peripheral Access Layer

## TCM_CTRL - TCM CRTL Register

#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)

## INT_STATUS - Interrupt Status Register

#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
#define | TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
#define | TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
#define | TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
#define | TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
#define | TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
#define | TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
#define | TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
#define | TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
#define | TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)

## INT_STAT_EN - Interrupt Status Enable Register

#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)

## INT_SIG_EN - Interrupt Enable Register

#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN

#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)

DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable 0b0..Masked 0b1..Enabled

Definition at line 19238 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK

#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)

Definition at line 19232 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT

#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)

Definition at line 19233 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN

#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)

ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable 0b0..Masked 0b1..Enabled

Definition at line 19231 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK

#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)

Definition at line 19225 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT

#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)

Definition at line 19226 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN

#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)

OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable 0b0..Masked 0b1..Enabled

Definition at line 19245 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK

#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)

Definition at line 19239 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT

#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)

Definition at line 19240 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN

#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)

DTCM_ERR_STAT_EN - DTCM Access Error Status Enable 0b0..Masked 0b1..Enabled

Definition at line 19213 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK

#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)

Definition at line 19207 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT

#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)

Definition at line 19208 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN

#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)

ITCM_ERR_STAT_EN - ITCM Access Error Status Enable 0b0..Masked 0b1..Enabled

Definition at line 19206 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK

#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)

Definition at line 19200 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT

#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)

Definition at line 19201 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN

#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)

OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable 0b0..Masked 0b1..Enabled

Definition at line 19220 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK

#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)

Definition at line 19214 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT

#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)

Definition at line 19215 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_DTCM_ERR_STATUS

#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)

DTCM_ERR_STATUS - DTCM Access Error Status 0b0..DTCM access error does not happen 0b1..DTCM access error happens.

Definition at line 19188 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK

#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)

Definition at line 19182 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT

#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)

Definition at line 19183 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_ITCM_ERR_STATUS

#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)

ITCM_ERR_STATUS - ITCM Access Error Status 0b0..ITCM access error does not happen 0b1..ITCM access error happens.

Definition at line 19181 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK

#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)

Definition at line 19175 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT

#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)

Definition at line 19176 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS

#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)

OCRAM_ERR_STATUS - OCRAM Access Error Status 0b0..OCRAM access error does not happen 0b1..OCRAM access error happens.

Definition at line 19195 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK

#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)

Definition at line 19189 of file MIMXRT1062.h.

## ◆ FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT

#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)

Definition at line 19190 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_FORCE_CLK_ON

#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)

FORCE_CLK_ON - Force RAM Clock Always On

Definition at line 19170 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK

#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)

Definition at line 19166 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT

#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)

Definition at line 19167 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_TCM_RWAIT_EN

#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)

TCM_RWAIT_EN - TCM Read Wait Mode Enable 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.

Definition at line 19165 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK

#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)

Definition at line 19159 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT

#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)

Definition at line 19160 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_TCM_WWAIT_EN

#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)

TCM_WWAIT_EN - TCM Write Wait Mode Enable 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.

Definition at line 19158 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK

#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)

Definition at line 19152 of file MIMXRT1062.h.

## ◆ FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT

#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)

Definition at line 19153 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_ENT_VAL

#define TRNG_INT_STATUS_ENT_VAL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)

ENT_VAL 0b0..Busy generation entropy. Any value read is invalid. 0b1..TRNG can be stopped and entropy is valid if read.

Definition at line 40838 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_ENT_VAL_MASK

#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)

Definition at line 40832 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_ENT_VAL_SHIFT

#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)

Definition at line 40833 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_FRQ_CT_FAIL

#define TRNG_INT_STATUS_FRQ_CT_FAIL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)

FRQ_CT_FAIL 0b0..No hardware nor self test frequency errors. 0b1..The frequency counter has detected a failure.

Definition at line 40845 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_FRQ_CT_FAIL_MASK

#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)

Definition at line 40839 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT

#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)

Definition at line 40840 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_HW_ERR

#define TRNG_INT_STATUS_HW_ERR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)

HW_ERR 0b0..no error 0b1..error detected.

Definition at line 40831 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_HW_ERR_MASK

#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)

Definition at line 40825 of file MIMXRT1062.h.

## ◆ TRNG_INT_STATUS_HW_ERR_SHIFT

#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)

Definition at line 40826 of file MIMXRT1062.h.