Callisto4Bootloader: DCDC Register Masks

Callisto4Bootloader

DCDC Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » DCDC Peripheral Access Layer

## REG0 - DCDC Register 0

#define | DCDC_REG0_PWD_ZCD_MASK (0x1U)
#define | DCDC_REG0_PWD_ZCD_SHIFT (0U)
#define | DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
#define | DCDC_REG0_SEL_CLK_MASK (0x4U)
#define | DCDC_REG0_SEL_CLK_SHIFT (2U)
#define | DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
#define | DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
#define | DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
#define | DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
#define | DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
#define | DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
#define | DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
#define | DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
#define | DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
#define | DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
#define | DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
#define | DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
#define | DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
#define | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
#define | DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
#define | DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
#define | DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
#define | DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
#define | DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
#define | DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)
#define | DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)
#define | DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)
#define | DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
#define | DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
#define | DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
#define | DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
#define | DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
#define | DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
#define | DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
#define | DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
#define | DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
#define | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
#define | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
#define | DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
#define | DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
#define | DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
#define | DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
#define | DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
#define | DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
#define | DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
#define | DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
#define | DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
#define | DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
#define | DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
#define | DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
#define | DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
#define | DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
#define | DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
#define | DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
#define | DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
#define | DCDC_REG0_STS_DC_OK_SHIFT (31U)
#define | DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)

## REG1 - DCDC Register 1

#define | DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
#define | DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
#define | DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
#define | DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
#define | DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
#define | DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
#define | DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
#define | DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
#define | DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
#define | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
#define | DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
#define | DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
#define | DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
#define | DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
#define | DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
#define | DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
#define | DCDC_REG1_VBG_TRIM_SHIFT (24U)
#define | DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)

## REG2 - DCDC Register 2

#define | DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
#define | DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
#define | DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
#define | DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
#define | DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
#define | DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
#define | DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
#define | DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
#define | DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
#define | DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
#define | DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
#define | DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
#define | DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
#define | DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
#define | DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)

## REG3 - DCDC Register 3

#define | DCDC_REG3_TRG_MASK (0x1FU)
#define | DCDC_REG3_TRG_SHIFT (0U)
#define | DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
#define | DCDC_REG3_TARGET_LP_MASK (0x700U)
#define | DCDC_REG3_TARGET_LP_SHIFT (8U)
#define | DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
#define | DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
#define | DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
#define | DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
#define | DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
#define | DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
#define | DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
#define | DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)
#define | DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)
#define | DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)
#define | DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
#define | DCDC_REG3_DISABLE_STEP_SHIFT (30U)
#define | DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ DCDC_REG0_ADJ_POSLIMIT_BUCK

#define DCDC_REG0_ADJ_POSLIMIT_BUCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)

Definition at line 11315 of file MIMXRT1062.h.

## ◆ DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK

#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)

Definition at line 11313 of file MIMXRT1062.h.

## ◆ DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT

#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)

Definition at line 11314 of file MIMXRT1062.h.

## ◆ DCDC_REG0_CUR_SNS_THRSH

#define DCDC_REG0_CUR_SNS_THRSH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)

Definition at line 11303 of file MIMXRT1062.h.

## ◆ DCDC_REG0_CUR_SNS_THRSH_MASK

#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)

Definition at line 11301 of file MIMXRT1062.h.

## ◆ DCDC_REG0_CUR_SNS_THRSH_SHIFT

#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)

Definition at line 11302 of file MIMXRT1062.h.

## ◆ DCDC_REG0_CURRENT_ALERT_RESET

#define DCDC_REG0_CURRENT_ALERT_RESET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)

Definition at line 11339 of file MIMXRT1062.h.

## ◆ DCDC_REG0_CURRENT_ALERT_RESET_MASK

#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)

Definition at line 11337 of file MIMXRT1062.h.

## ◆ DCDC_REG0_CURRENT_ALERT_RESET_SHIFT

#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)

Definition at line 11338 of file MIMXRT1062.h.

## ◆ DCDC_REG0_DISABLE_AUTO_CLK_SWITCH

#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)

Definition at line 11291 of file MIMXRT1062.h.

## ◆ DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK

#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)

Definition at line 11289 of file MIMXRT1062.h.

## ◆ DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT

#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)

Definition at line 11290 of file MIMXRT1062.h.

## ◆ DCDC_REG0_EN_LP_OVERLOAD_SNS

#define DCDC_REG0_EN_LP_OVERLOAD_SNS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)

Definition at line 11318 of file MIMXRT1062.h.

## ◆ DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK

#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)

Definition at line 11316 of file MIMXRT1062.h.

## ◆ DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT

#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)

Definition at line 11317 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_HIGH_HYS

#define DCDC_REG0_LP_HIGH_HYS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)

Definition at line 11330 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_HIGH_HYS_MASK

#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)

Definition at line 11328 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_HIGH_HYS_SHIFT

#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)

Definition at line 11329 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_OVERLOAD_FREQ_SEL

#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)

Definition at line 11327 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK

#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)

Definition at line 11325 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT

#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)

Definition at line 11326 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_OVERLOAD_THRSH

#define DCDC_REG0_LP_OVERLOAD_THRSH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)

Definition at line 11324 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_OVERLOAD_THRSH_MASK

#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)

Definition at line 11322 of file MIMXRT1062.h.

## ◆ DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT

#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)

Definition at line 11323 of file MIMXRT1062.h.

## ◆ DCDC_REG0_OVERCUR_TRIG_ADJ

#define DCDC_REG0_OVERCUR_TRIG_ADJ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)

Definition at line 11309 of file MIMXRT1062.h.

## ◆ DCDC_REG0_OVERCUR_TRIG_ADJ_MASK

#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)

Definition at line 11307 of file MIMXRT1062.h.

## ◆ DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT

#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)

Definition at line 11308 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CMP_BATT_DET

#define DCDC_REG0_PWD_CMP_BATT_DET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)

Definition at line 11312 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CMP_BATT_DET_MASK

#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)

Definition at line 11310 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CMP_BATT_DET_SHIFT

#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)

Definition at line 11311 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CMP_OFFSET

#define DCDC_REG0_PWD_CMP_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)

Definition at line 11333 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CMP_OFFSET_MASK

#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)

Definition at line 11331 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CMP_OFFSET_SHIFT

#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)

Definition at line 11332 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CUR_SNS_CMP

#define DCDC_REG0_PWD_CUR_SNS_CMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)

Definition at line 11300 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CUR_SNS_CMP_MASK

#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)

Definition at line 11298 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT

#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)

Definition at line 11299 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_HIGH_VOLT_DET

#define DCDC_REG0_PWD_HIGH_VOLT_DET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)

Definition at line 11321 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_HIGH_VOLT_DET_MASK

#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)

Definition at line 11319 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT

#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)

Definition at line 11320 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_OSC_INT

#define DCDC_REG0_PWD_OSC_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)

Definition at line 11297 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_OSC_INT_MASK

#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)

Definition at line 11295 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_OSC_INT_SHIFT

#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)

Definition at line 11296 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_OVERCUR_DET

#define DCDC_REG0_PWD_OVERCUR_DET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)

Definition at line 11306 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_OVERCUR_DET_MASK

#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)

Definition at line 11304 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_OVERCUR_DET_SHIFT

#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)

Definition at line 11305 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_ZCD

#define DCDC_REG0_PWD_ZCD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)

Definition at line 11288 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_ZCD_MASK

#define DCDC_REG0_PWD_ZCD_MASK (0x1U)

Definition at line 11286 of file MIMXRT1062.h.

## ◆ DCDC_REG0_PWD_ZCD_SHIFT

#define DCDC_REG0_PWD_ZCD_SHIFT (0U)

Definition at line 11287 of file MIMXRT1062.h.

## ◆ DCDC_REG0_SEL_CLK

#define DCDC_REG0_SEL_CLK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)

Definition at line 11294 of file MIMXRT1062.h.

## ◆ DCDC_REG0_SEL_CLK_MASK

#define DCDC_REG0_SEL_CLK_MASK (0x4U)

Definition at line 11292 of file MIMXRT1062.h.

## ◆ DCDC_REG0_SEL_CLK_SHIFT

#define DCDC_REG0_SEL_CLK_SHIFT (2U)

Definition at line 11293 of file MIMXRT1062.h.

## ◆ DCDC_REG0_STS_DC_OK

#define DCDC_REG0_STS_DC_OK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)

Definition at line 11345 of file MIMXRT1062.h.

## ◆ DCDC_REG0_STS_DC_OK_MASK

#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)

Definition at line 11343 of file MIMXRT1062.h.

## ◆ DCDC_REG0_STS_DC_OK_SHIFT

#define DCDC_REG0_STS_DC_OK_SHIFT (31U)

Definition at line 11344 of file MIMXRT1062.h.

## ◆ DCDC_REG0_XTAL_24M_OK

#define DCDC_REG0_XTAL_24M_OK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)

Definition at line 11342 of file MIMXRT1062.h.

## ◆ DCDC_REG0_XTAL_24M_OK_MASK

#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)

Definition at line 11340 of file MIMXRT1062.h.

## ◆ DCDC_REG0_XTAL_24M_OK_SHIFT

#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)

Definition at line 11341 of file MIMXRT1062.h.

## ◆ DCDC_REG0_XTALOK_DISABLE

#define DCDC_REG0_XTALOK_DISABLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)

Definition at line 11336 of file MIMXRT1062.h.

## ◆ DCDC_REG0_XTALOK_DISABLE_MASK

#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)

Definition at line 11334 of file MIMXRT1062.h.

## ◆ DCDC_REG0_XTALOK_DISABLE_SHIFT

#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)

Definition at line 11335 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LOOPCTRL_EN_HYST

#define DCDC_REG1_LOOPCTRL_EN_HYST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)

Definition at line 11364 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LOOPCTRL_EN_HYST_MASK

#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)

Definition at line 11362 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT

#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)

Definition at line 11363 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LOOPCTRL_HST_THRESH

#define DCDC_REG1_LOOPCTRL_HST_THRESH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)

Definition at line 11361 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LOOPCTRL_HST_THRESH_MASK

#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)

Definition at line 11359 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT

#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)

Definition at line 11360 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LP_CMP_ISRC_SEL

#define DCDC_REG1_LP_CMP_ISRC_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)

Definition at line 11358 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LP_CMP_ISRC_SEL_MASK

#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)

Definition at line 11356 of file MIMXRT1062.h.

## ◆ DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT

#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)

Definition at line 11357 of file MIMXRT1062.h.

## ◆ DCDC_REG1_REG_FBK_SEL

#define DCDC_REG1_REG_FBK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)

Definition at line 11352 of file MIMXRT1062.h.

## ◆ DCDC_REG1_REG_FBK_SEL_MASK

#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)

Definition at line 11350 of file MIMXRT1062.h.

## ◆ DCDC_REG1_REG_FBK_SEL_SHIFT

#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)

Definition at line 11351 of file MIMXRT1062.h.

## ◆ DCDC_REG1_REG_RLOAD_SW

#define DCDC_REG1_REG_RLOAD_SW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)

Definition at line 11355 of file MIMXRT1062.h.

## ◆ DCDC_REG1_REG_RLOAD_SW_MASK

#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)

Definition at line 11353 of file MIMXRT1062.h.

## ◆ DCDC_REG1_REG_RLOAD_SW_SHIFT

#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)

Definition at line 11354 of file MIMXRT1062.h.

## ◆ DCDC_REG1_VBG_TRIM

#define DCDC_REG1_VBG_TRIM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)

Definition at line 11367 of file MIMXRT1062.h.

## ◆ DCDC_REG1_VBG_TRIM_MASK

#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)

Definition at line 11365 of file MIMXRT1062.h.

## ◆ DCDC_REG1_VBG_TRIM_SHIFT

#define DCDC_REG1_VBG_TRIM_SHIFT (24U)

Definition at line 11366 of file MIMXRT1062.h.

## ◆ DCDC_REG2_DCM_SET_CTRL

#define DCDC_REG2_DCM_SET_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)

Definition at line 11395 of file MIMXRT1062.h.

## ◆ DCDC_REG2_DCM_SET_CTRL_MASK

#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)

Definition at line 11393 of file MIMXRT1062.h.

## ◆ DCDC_REG2_DCM_SET_CTRL_SHIFT

#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)

Definition at line 11394 of file MIMXRT1062.h.

## ◆ DCDC_REG2_DISABLE_PULSE_SKIP

#define DCDC_REG2_DISABLE_PULSE_SKIP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)

Definition at line 11392 of file MIMXRT1062.h.

## ◆ DCDC_REG2_DISABLE_PULSE_SKIP_MASK

#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)

Definition at line 11390 of file MIMXRT1062.h.

## ◆ DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT

#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)

Definition at line 11391 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_C

#define DCDC_REG2_LOOPCTRL_DC_C | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)

Definition at line 11374 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_C_MASK

#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)

Definition at line 11372 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_C_SHIFT

#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)

Definition at line 11373 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_FF

#define DCDC_REG2_LOOPCTRL_DC_FF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)

Definition at line 11380 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_FF_MASK

#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)

Definition at line 11378 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_FF_SHIFT

#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)

Definition at line 11379 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_R

#define DCDC_REG2_LOOPCTRL_DC_R | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)

Definition at line 11377 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_R_MASK

#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)

Definition at line 11375 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_DC_R_SHIFT

#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)

Definition at line 11376 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_EN_RCSCALE

#define DCDC_REG2_LOOPCTRL_EN_RCSCALE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)

Definition at line 11383 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK

#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)

Definition at line 11381 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT

#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)

Definition at line 11382 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_HYST_SIGN

#define DCDC_REG2_LOOPCTRL_HYST_SIGN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)

Definition at line 11389 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK

#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)

Definition at line 11387 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT

#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)

Definition at line 11388 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_RCSCALE_THRSH

#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)

Definition at line 11386 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK

#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)

Definition at line 11384 of file MIMXRT1062.h.

## ◆ DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT

#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)

Definition at line 11385 of file MIMXRT1062.h.

## ◆ DCDC_REG3_DISABLE_STEP

#define DCDC_REG3_DISABLE_STEP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)

Definition at line 11417 of file MIMXRT1062.h.

## ◆ DCDC_REG3_DISABLE_STEP_MASK

#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)

Definition at line 11415 of file MIMXRT1062.h.

## ◆ DCDC_REG3_DISABLE_STEP_SHIFT

#define DCDC_REG3_DISABLE_STEP_SHIFT (30U)

Definition at line 11416 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MINPWR_DC_HALFCLK

#define DCDC_REG3_MINPWR_DC_HALFCLK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)

Definition at line 11408 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MINPWR_DC_HALFCLK_MASK

#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)

Definition at line 11406 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT

#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)

Definition at line 11407 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MISC_DELAY_TIMING

#define DCDC_REG3_MISC_DELAY_TIMING | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)

Definition at line 11411 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MISC_DELAY_TIMING_MASK

#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)

Definition at line 11409 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MISC_DELAY_TIMING_SHIFT

#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)

Definition at line 11410 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MISC_DISABLEFET_LOGIC

#define DCDC_REG3_MISC_DISABLEFET_LOGIC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)

Definition at line 11414 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK

#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)

Definition at line 11412 of file MIMXRT1062.h.

## ◆ DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT

#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)

Definition at line 11413 of file MIMXRT1062.h.

## ◆ DCDC_REG3_TARGET_LP

#define DCDC_REG3_TARGET_LP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)

Definition at line 11405 of file MIMXRT1062.h.

## ◆ DCDC_REG3_TARGET_LP_MASK

#define DCDC_REG3_TARGET_LP_MASK (0x700U)

Definition at line 11403 of file MIMXRT1062.h.

## ◆ DCDC_REG3_TARGET_LP_SHIFT

#define DCDC_REG3_TARGET_LP_SHIFT (8U)

Definition at line 11404 of file MIMXRT1062.h.

## ◆ DCDC_REG3_TRG

#define DCDC_REG3_TRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)

Definition at line 11402 of file MIMXRT1062.h.

## ◆ DCDC_REG3_TRG_MASK

#define DCDC_REG3_TRG_MASK (0x1FU)

Definition at line 11400 of file MIMXRT1062.h.

## ◆ DCDC_REG3_TRG_SHIFT

#define DCDC_REG3_TRG_SHIFT (0U)

Definition at line 11401 of file MIMXRT1062.h.