Callisto4Bootloader: ARK/platform_sampler_lpspi3_ad8688.c Source File

Callisto4Bootloader

platform_sampler_lpspi3_ad8688.c
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1 /*
2 * platform_sampler_lspi3_ad8688.c
3 *
4 * Created on: 22 Jun 2020
5 * Author: Nick Pelling
6 */
7
8 #include <cr_section_macros.h>
9
10 #include "fsl_lpspi.h"
11 #include "fsl_gpio.h"
12 #include "fsl_enet.h"
13 #include "fsl_pit.h"
14 #include "fsl_gpt.h"
15
16 #include "FreeRTOS.h"
17 #include "task.h"
18 #include "lwip/err.h"
19
20 #include "enet_mac_if1.h"
21 #include "sav_init.h"
22
23 #include "platform_sampler_lpspi3_ad8688.h"
24
25 // --------------------------------------------------------------------------
26 // FIXME - Need to extend sampler API to work better with plugins!
27 // The following 5 data should be from the ac-analogue plugin
28 // --------------------------------------------------------------------------
29
30 static bool process_ac_ready;
31 static bool time_error;
32 static bool calcs_done;
33 static uint32_t ncycles;
34 static TaskHandle_t xProcessAcHandle;
35
36 // --------------------------------------------------------------------------
37
38 static bool process_bus_started = false;
39 static int16_t sysFreq0;
40 static uint32_t period;
41
42 static uint32_t present_delay_time[MAX_SAMPLE_CHANNELS];
43 static uint32_t last_delay_time[MAX_SAMPLE_CHANNELS];
44
45 static int16_t present_sample_data[MAX_SAMPLE_CHANNELS];
46 static int16_t last_sample_data[MAX_SAMPLE_CHANNELS];
47
48 static uint8_t channel_number;
49 static bool sample_data_flag;
50
51 volatile int16_t sample_counter;
52 volatile uint16_t sample_counter_res;
53 volatile uint16_t sample_index_offset;
54 volatile int16_t sample_offset;
55 volatile uint16_t raw_index_offset;
56 // static uint16_t sample_counter_ps;
57
58 volatile bool ready_to_transfer = false;
59 volatile bool sv_trans_error = false;
60 static uint8_t tx_sv_enable;
61 static uint8_t rx_sv_enable;
62
63 static int8_t tx_active_idx;
64 static int8_t tx_next_idx;
65 static int8_t tx_buffer_gap;
66 static uint32_t sv_frame_length;
67
68 volatile int8_t sample_cycle;
69 static int8_t last_cycle;
70 static struct sv_receive_buffer *rx_buffer_ptr;
71 static struct PROCESS_BUS_CONFIG *sv_config_ptr;
72
73 static int8_t chn_index[MAX_SAMPLE_DATA];
74 static int8_t trm_chn_pos[8];
75 static int8_t rev_chn_pos[8];
76 static uint8_t rev_mac_addr[6];
77
78 static int32_t mu_data[MAX_SAMPLE_CHANNELS];
79 static struct sv_transmit_buffer sv_tx_buffer[MAX_TX_BUFFER];
80 static uint32_t raw_data[TOT_RAW_DATA];
81
82 // --------------------------------------------------------------------------
83 // FORWARD REFERENCES
84 // --------------------------------------------------------------------------
85
86 static void LPSPI3_Initialise(void);
87 static void initGPIO_ADS8688_CS(void);
88 static void initADS8688(void);
89 static void PIT_Initialise(void);
90 static void GPT_Initialise(void);
91
92 static void Write8688(LPSPI_Type *base, uint8_t address, uint16_t data);
93 static bool sav_rx_enabled(uint8_t *);
94 static bool sav_tx_enabled(void);
95
96 // --------------------------------------------------------------------------
97 // GLOBAL FUNCTIONS
98 // --------------------------------------------------------------------------
99
100 bool Sampler_ADS8688_InitHardware(void)
101 {
102 LPSPI3_Initialise();
103 initGPIO_ADS8688_CS();
104
105 initADS8688();
106
107 EnableIRQ(ADS8688_LPSPI_MASTER_IRQN);
108
109 LPSPI_EnableInterrupts(ADS8688_LPSPI_MASTER_BASEADDR, kLPSPI_RxInterruptEnable);
110
111 PIT_Initialise();
112 GPT_Initialise();
113
114 return true;
115 }
116
117 bool Sampler_ADS8688_Setup( const ePLATFORM_SamplerConfig_t *paeSamplerConfig,
118 uint32_t uiNumChannels,
119 volatile stPLATFORM_SampleGrab_t * pastCircularBuffer,
120 uint32_t uiBufferElements )
121 {
122 (void)paeSamplerConfig;
123 (void)uiNumChannels;
124 (void)pastCircularBuffer;
125 (void)uiBufferElements;
126
127 return false;
128 }
129
130 bool Sampler_ADS8688_Start(uint32_t uiPeriod_Nsec)
131 {
132 (void)uiPeriod_Nsec;
133
134 return false;
135 }
136
137 bool Sampler_ADS8688_Adjust(uint32_t uiDelay_Nsec, uint32_t uiPeriod_Nsec)
138 {
139 (void)uiDelay_Nsec;
140 (void)uiPeriod_Nsec;
141
142 return false;
143 }
144
145 bool Sampler_ADS8688_Stop(void)
146 {
147 return false;
148 }
149
150 uint32_t Sampler_ADS8688_GetTimer(void)
151 {
152 return 0;
153 }
154
155 uint32_t Sampler_ADS8688_Grab( uint32_t uiEarliestTimer,
156 volatile stPLATFORM_SampleGrab_t ** papstGrabArray,
157 uint32_t uiMaxSamplesToGrab)
158 {
159 (void)uiEarliestTimer;
160 (void)papstGrabArray;
161 (void)uiMaxSamplesToGrab;
162
163 return 0;
164 }
165
166 // --------------------------------------------------------------------------
167 //
168 // LOCAL FUNCTIONS
169 //
170 // --------------------------------------------------------------------------
171
172 // Local prototypes
173 // static void ethernet_sv_send_callback(unsigned char *data);
174 // Called from tcp thread context, not from spi interrupt
175
176 static void ethernet_sv_send_callback(uint16_t sv_frame_length, unsigned char *data)
177 {
178 enet1_send_frame(data, sv_frame_length);
179 }
180
181
190 static void PIT_Initialise(void)
191 {
192 uint32_t basefreq;
193 uint32_t pitFreq;
194 uint32_t default_period;
195
196 // Structure used to initialize PIT
197 pit_config_t pitConfig;
198
199 basefreq = (uint32_t) PIT_CLOCK_BASEFREQ();
200 pitFreq = (uint32_t) PIT_CLOCK(basefreq);
201
202 // default_period = pitFreq / 1000U; // LX: This should be default to the ac system sampling frequency
203 default_period = ((uint32_t)pitFreq + ((uint32_t)NPC * (uint32_t)sysFreq0)/2)/ ((uint32_t)NPC * sysFreq0) - 1;
204 period = default_period + 1;
205
206 // Initialization for PIT
207 CLOCK_EnableClock( PIT_CLOCK_WHICH );
208
209 /* Set PERCLK_CLK base clock */
210 CLOCK_SetMux( kCLOCK_PerclkMux, PIT_CLOCK_SOURCE_SELECT );
211
212 /* Set PERCLK_CLK divider ratio register */
213 CLOCK_SetDiv( kCLOCK_PerclkDiv, PIT_CLOCK_DIVIDER_RATIO - 1U );
214
215 PIT_GetDefaultConfig(&pitConfig);
216 // pitConfig.enableRunInDebug = false;
217
218 /* Init pit module */
219 PIT_Init(PIT, &pitConfig);
220
221 /* Set timer period for channel 0 */
222 PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, default_period);
223
224 NVIC_SetPriority(PIT_IRQ_ID, PIT_IRQ_PRIORITY);
225
226 /* Enable timer interrupts for channel 0 */
227 PIT_EnableInterrupts(PIT, kPIT_Chnl_0, kPIT_TimerInterruptEnable);
228
229 /* Enable at the NVIC */
230 EnableIRQ(PIT_IRQ_ID);
231
232 // Start timer on PIT channel #0
233 PIT_StartTimer(PIT, kPIT_Chnl_0);
234 }
235
236 static void GPT_Initialise(void)
237 {
238 uint32_t gptFreq;
239 gpt_config_t gptConfig;
240
241 /*Clock setting for GPT*/
242 CLOCK_SetMux(kCLOCK_PerclkMux, SMV_GPT_CLOCK_SOURCE_SELECT);
243 CLOCK_SetDiv(kCLOCK_PerclkDiv, SMV_GPT_CLOCK_DIVIDER_SELECT);
244
245 GPT_GetDefaultConfig(&gptConfig);
246
247 /* Initialize GPT module */
248 GPT_Init(SMV_GPT, &gptConfig);
249
250 /* Divide GPT clock source frequency by 3 inside GPT module */
251 GPT_SetClockDivider(SMV_GPT, 3);
252
253 /* Get GPT clock frequency */
254 gptFreq = SMV_GPT_CLK_FREQ;
255
256 /* GPT frequency is divided by 3 inside module */
257 gptFreq /= 3 * 100000;
258
259 /* Set both GPT modules to 10 us duration */
260 GPT_SetOutputCompareValue(SMV_GPT, kGPT_OutputCompare_Channel1, gptFreq);
261
262 NVIC_SetPriority(GPT_IRQ_ID, GPT_IRQ_PRIORITY);
263
264 /* Enable GPT Output Compare1 interrupt */
265 GPT_EnableInterrupts(SMV_GPT, kGPT_OutputCompare1InterruptEnable);
266
267 /* Enable at the Interrupt */
268 EnableIRQ(GPT_IRQ_ID);
269
270 }
271
272 // --------------------------------------------------------------------------
273
274 static void LPSPI3_Initialise(void)
275 {
276 LPSPI_Type *base = ADS8688_LPSPI_MASTER_BASEADDR; // = LPSPI3
277 uint32_t whichPcs;
278 uint8_t txWatermark;
279 uint32_t usbClock;
280 uint32_t srcClock_Hz;
281 uint8_t g_masterRxWatermark;
282 uint8_t g_masterFifoSize;
283 lpspi_master_config_t masterConfig;
284
285 // Set clock source for LPSPI
286 CLOCK_SetMux(kCLOCK_LpspiMux, LPSPI3_CLOCK_SOURCE_SELECT);
287 CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI3_CLOCK_SOURCE_DIVIDER);
288
289 // Master config
290 masterConfig.baudRate = LPSPI3_TRANSFER_BAUDRATE;
291 masterConfig.bitsPerFrame = 8; // 8 bits format
292 masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; // CPOL = 0
293 masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; // CPHA = 1
294 masterConfig.direction = kLPSPI_MsbFirst;
295
296 masterConfig.pcsToSckDelayInNanoSec = NANOSECS_PER_HALFSECOND / masterConfig.baudRate;
297 masterConfig.lastSckToPcsDelayInNanoSec = NANOSECS_PER_HALFSECOND / masterConfig.baudRate;
298 masterConfig.betweenTransferDelayInNanoSec = NANOSECS_PER_HALFSECOND / masterConfig.baudRate;
299
300 masterConfig.whichPcs = LPSPI3_MASTER_PCS_FOR_INIT;
301 masterConfig.pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
302
303 masterConfig.pinCfg = kLPSPI_SdiInSdoOut; // LX: Originally is kLPSPI_SdiInSdoOut;
304 masterConfig.dataOutConfig = kLpspiDataOutRetained;
305
306 usbClock = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk); // Should be 720MHz
307 srcClock_Hz = LPSPI3_MASTER_CLK_FREQ(usbClock);
308
309 whichPcs = LPSPI3_MASTER_PCS_FOR_INIT;
310
311 // The TX and RX FIFO sizes are always the same
312 g_masterFifoSize = LPSPI_GetRxFifoSize(base);
313
314 // Set the RX and TX watermarks to reduce the ISR times.
315 if (g_masterFifoSize > 1)
316 {
317 txWatermark = 1;
318 g_masterRxWatermark = MAX_SAMPLE_DATA;
319 }
320 else
321 {
322 txWatermark = 0;
323 g_masterRxWatermark = 0;
324 }
325
326 // LX: The masterConfig was set before, it is not necessary to reset here
327 LPSPI_MasterInit(base, &masterConfig, srcClock_Hz);
328
329 LPSPI_SetFifoWatermarks(base, txWatermark, g_masterRxWatermark);
330
331 LPSPI_Enable(base, false);
332 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
333 LPSPI_Enable(base, true);
334
335 // Flush FIFO, clear status, disable all the interrupts.
336 LPSPI_FlushFifo(base, true, true);
337 LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag);
338 LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable);
339
340 // Set the Transmit Command Register (TCR)
341 base->TCR =
342 (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
343 LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs);
344
345 // Wait for LPSPI3's FIFO to empty
346 while (LPSPI_GetTxFifoCount(base))
347 ;
348
349 // Set LPSPI3's interrupt priority
350 NVIC_SetPriority(ADS8688_LPSPI_MASTER_IRQN, LPSPI3_PRIORITY);
351 }
352
353
354
355
356 // --------------------------------------------------------------------------
357 //
358 // GLOBAL IRQ HANDLERS
359 //
360 // --------------------------------------------------------------------------
361
362 /*
363 * The PIT IRQ Handler used by this sampler
364 *
365 * Note: called continuously, but only triggers conversions if sampling is enabled.
366 */
367 void PIT_IRQHandler(void)
368 {
369 uint16_t i;
370 uint16_t sample_counter_accu;
371
372 PIT_ClearStatusFlags(PIT, kPIT_Chnl_0, kPIT_TimerFlag);
373
374 // Reset Receive FIFO
375 ADS8688_LPSPI_MASTER_BASEADDR->CR |= (LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK);
376 last_delay_time[0] = period - present_delay_time[0];
377
378 // Start to scan the input of all channels by writing a reset command
379 // in the command register
380 Write8688(ADS8688_LPSPI_MASTER_BASEADDR, 0xFF, 0xA000);
381
382 // Drop the CS pin to start conversion
383 CS_LOW();
384
385 present_delay_time[0] = period - PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_0);
386 for(i=0; i<=MAX_SAMPLE_DATA; i++)
387 {
388 ADS8688_LPSPI_MASTER_BASEADDR->TDR = 0;
389 }
390
391 channel_number = 0;
392 sample_data_flag = true;
393
394 sample_counter = sample_counter + 1;
395 if(sample_counter >= 32767)
396 sample_counter = 0;
397
398 sample_counter_accu = sample_counter + sample_counter_res;
399 sample_index_offset = sample_counter_accu % DOUBLE_NPC;
400
401 sample_offset = sample_index_offset * MAX_SAMPLE_CHANNELS;
402
403 ARM_errata_838869();
404 }
405
406
407
408 void GPT2_IRQHandler(void)
409 {
410 uint16_t i, j;
411 // uint16_t adc_data_pt;
412
413 GPT_StopTimer(SMV_GPT);
414 /* Clear interrupt flag.*/
415 GPT_ClearStatusFlags(SMV_GPT, kGPT_OutputCompare1Flag);
416
417 // if(tx_buffer_gap < MAX_TX_BUFFER)
418 // {
419 #if VOLTAGE_SAMPLE
420 sv_tx_buffer[tx_next_idx].ConfRef0 = (uint8_t)((period>>8) & 0xFF);
421 sv_tx_buffer[tx_next_idx].ConfRef1 = (uint8_t)(period & 0xFF);
422 #endif
423
424 sv_tx_buffer[tx_next_idx].smpCnt0 = (uint8_t)((sample_counter>>8) & 0xFF);
425 sv_tx_buffer[tx_next_idx].smpCnt1 = (uint8_t)(sample_counter & 0xFF);
426
427 for (i=0; i< MAX_SAMPLE_DATA; i++)
428 {
429 for(j=0; j<4; j++)
430 {
431 if(chn_index[i] == trm_chn_pos[j])
432 {
433 sv_tx_buffer[tx_next_idx].sampleData[j<<3] = (uint8_t)((mu_data[i]>>24) & 0xFF);
434 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+1] = (uint8_t)((mu_data[i]>>16) & 0xFF);
435 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+2] = (uint8_t)((mu_data[i]>>8) & 0xFF);
436 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+3] = (uint8_t)(mu_data[i] & 0xFF);
437 }
438 else if(chn_index[i] == trm_chn_pos[j+4])
439 {
440 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+32] = (uint8_t)((mu_data[i]>>24) & 0xFF);
441 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+33] = (uint8_t)((mu_data[i]>>16) & 0xFF);
442 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+34] = (uint8_t)((mu_data[i]>>8) & 0xFF);
443 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+35] = (uint8_t)(mu_data[i] & 0xFF);
444 }
445 }
446 }
447
448 tx_next_idx++;
449 if(tx_next_idx >= MAX_TX_BUFFER)
450 tx_next_idx = 0;
451 tx_buffer_gap++;
452 if(tx_buffer_gap > MAX_TX_BUFFER)
453 {
454 tx_buffer_gap = 1;
455 sv_trans_error = true;
456 tx_active_idx = tx_next_idx - 1;
457 }
458
459 if (sav_callback_with_block((uint8_t)SAV_TRANSMIT_CALLBACK, (sav_callback_fn)ethernet_sv_send_callback, sv_frame_length, &sv_tx_buffer[tx_active_idx], 0) == ERR_OK) // Do not block. (block version does not work from an interrupt anyway)
460 {
461 tx_buffer_gap--;
462 tx_active_idx++;
463 if(tx_active_idx >= MAX_TX_BUFFER)
464 tx_active_idx = 0;
465 }
466 // } // end of if(tx_buffer_gap < MAX_TX_BUFFER)
467
468 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping
469 exception return operation might vector to incorrect interrupt */
470 ARM_errata_838869();
471 }
472
473
474
475 // --------------------------------------------------------------------------
476
477 /*
478 * The LPSPI3 IRQ Handler used by this sampler
479 *
480 * Note: pulls in the last sample from the LPSPI3 FIFO, and then, if there
481 * are more samples to come in the current set, triggers the next capture
482 */
483 void LPSPI3_IRQHandler(void)
484 {
485 uint8_t i, j;
486
487 // int16_t data_point;
488 uint16_t ADC_value;
489 int32_t interp_data;
490 // int32_t mu_data[MAX_SAMPLE_CHANNELS];
491
492 uint8_t rec_data[MAX_SAMPLE_ADD_1];
493 // BaseType_t xHigherPriorityTaskWoken = pdFALSE;
494
495 // Clear the interrupt status FLAG
496 ADS8688_LPSPI_MASTER_BASEADDR->SR = LPSPI_SR_RDF_MASK;
497
498 if ( sample_data_flag )
499 {
500 // Conversion finished rise the CS pin
501 CS_HIGH();
502
503 sample_data_flag = false;
504
505 for(i=0; i<MAX_SAMPLE_ADD_1; i++)
506 rec_data[i] = ADS8688_LPSPI_MASTER_BASEADDR->RDR;
507
508 ADC_value = (uint16_t)(rec_data[2]<<8) + (uint16_t)rec_data[3];
509
510 last_sample_data[channel_number] = present_sample_data[channel_number];
511 present_sample_data[channel_number] = (int16_t)(ADC_value - MAX_INT15);
512
513 interp_data = (int32_t)last_delay_time[channel_number]*(int32_t)present_sample_data[channel_number]
514 + (int32_t)present_delay_time[channel_number]*(int32_t)last_sample_data[channel_number];
515 interp_data = interp_data / ((int32_t)last_delay_time[channel_number] + (int32_t)present_delay_time[channel_number]);
516
517 mu_data[channel_number] = interp_data;
518
519 if(channel_number < MAX_SAMPLE_DATA)
520 raw_data[sample_offset+chn_index[channel_number]] = mu_data[channel_number];
521
522 if(channel_number == MAX_SAMPLE_CHANNELS_1)
523 {
524 if( !rx_sv_enable )
525 {
526 /*
527 data_point = sample_offset + MAX_SAMPLE_CHANNELS;
528
529 if(data_point == TOT_PPC)
530 {
531 sample_cycle = 1;
532 if((ncycles > 10) && (!calcs_done))
533 {
534 time_error = true;
535 }
536
537 if(process_ac_ready)
538 {
539 vTaskNotifyGiveFromISR(xProcessAcHandle, &xHigherPriorityTaskWoken);
540 portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
541 }
542 }
543
544 else if(data_point == DOUBLE_TOT_PPC)
545 {
546 sample_cycle = 2;
547 if((ncycles > 10) && (!calcs_done))
548 {
549 time_error = true;
550 }
551
552 if(process_ac_ready)
553 {
554 vTaskNotifyGiveFromISR(xProcessAcHandle, &xHigherPriorityTaskWoken);
555 portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
556 }
557 }
558
559 else if(data_point == TRIPLE_TOT_PPC)
560 {
561 sample_cycle = 3;
562 if((ncycles > 10) && (!calcs_done))
563 {
564 time_error = true;
565 }
566 if(process_ac_ready)
567 {
568 vTaskNotifyGiveFromISR(xProcessAcHandle, &xHigherPriorityTaskWoken);
569 portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
570 }
571 }
572
573 else if(data_point >= TOT_RAW_DATA)
574 {
575 sample_cycle = 0;
576 if((ncycles > 10) && (!calcs_done))
577 time_error = true;
578
579 if(process_ac_ready)
580 {
581 vTaskNotifyGiveFromISR(xProcessAcHandle, &xHigherPriorityTaskWoken);
582 portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
583 }
584 }
585 */
586 }
587
588 if(tx_sv_enable && ready_to_transfer)
589 {
590 GPT_StartTimer(SMV_GPT);
591 /*
592 #if VOLTAGE_SAMPLE
593 sv_tx_buffer[tx_next_idx].ConfRef0 = (uint8_t)((period>>8) & 0xFF);
594 sv_tx_buffer[tx_next_idx].ConfRef1 = (uint8_t)(period & 0xFF);
595 #endif
596
597 sv_tx_buffer[tx_next_idx].smpCnt0 = (uint8_t)((sample_counter>>8) & 0xFF);
598 sv_tx_buffer[tx_next_idx].smpCnt1 = (uint8_t)(sample_counter & 0xFF);
599
600 for (i=0; i< MAX_SAMPLE_DATA; i++)
601 {
602 for(j=0; j<4; j++)
603 {
604 if(chn_index[i] == trm_chn_pos[j])
605 {
606 sv_tx_buffer[tx_next_idx].sampleData[j<<3] = (uint8_t)((mu_data[i]>>24) & 0xFF);
607 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+1] = (uint8_t)((mu_data[i]>>16) & 0xFF);
608 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+2] = (uint8_t)((mu_data[i]>>8) & 0xFF);
609 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+3] = (uint8_t)(mu_data[i] & 0xFF);
610 }
611 else if(chn_index[i] == trm_chn_pos[j+4])
612 {
613 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+32] = (uint8_t)((mu_data[i]>>24) & 0xFF);
614 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+33] = (uint8_t)((mu_data[i]>>16) & 0xFF);
615 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+34] = (uint8_t)((mu_data[i]>>8) & 0xFF);
616 sv_tx_buffer[tx_next_idx].sampleData[(j<<3)+35] = (uint8_t)(mu_data[i] & 0xFF);
617 }
618 }
619 }
620
621 tx_next_idx++;
622 if(tx_next_idx >= MAX_TX_BUFFER)
623 tx_next_idx = 0;
624 tx_buffer_gap++;
625 if(tx_buffer_gap > MAX_TX_BUFFER)
626 {
627 tx_buffer_gap = 1;
628 sv_trans_error = true;
629 tx_active_idx = tx_next_idx - 1;
630 }
631
632 if (sav_callback_with_block((uint8_t)SAV_TRANSMIT_CALLBACK, (sav_callback_fn)ethernet_sv_send_callback, sv_frame_length, &sv_tx_buffer[tx_active_idx], 0) == ERR_OK) // Do not block. (block version does not work from an interrupt anyway)
633 {
634 tx_buffer_gap--;
635 tx_active_idx++;
636 if(tx_active_idx >= MAX_TX_BUFFER)
637 tx_active_idx = 0;
638 }
639 // } // end of if(tx_buffer_gap < MAX_TX_BUFFER)
640 */
641 } // end of if(tx_sv_enable && ready_to_transfer)
642 } // end of if(channel_number == MAX_SAMPLE_CHANNELS_1)
643
644 else
645 {
646 sample_data_flag = true;
647
648 // Reset Receive FIFO
649 ADS8688_LPSPI_MASTER_BASEADDR->CR |= (LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK);
650 last_delay_time[channel_number + 1] = period - present_delay_time[channel_number + 1];
651
652 // Start the conversion for another channel by droping the CS pin
653 CS_LOW();
654
655 present_delay_time[channel_number + 1] = period - PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_0);
656
657 channel_number++;
658
659 for(j=0; j<=MAX_SAMPLE_DATA; j++)
660 {
661 ADS8688_LPSPI_MASTER_BASEADDR->TDR = 0;
662 }
663 if(tx_buffer_gap > 0)
664 {
665 if (sav_callback_with_block((uint8_t)SAV_TRANSMIT_CALLBACK, (sav_callback_fn)ethernet_sv_send_callback, sv_frame_length, &sv_tx_buffer[tx_active_idx], 0) == ERR_OK) // Do not block. (block version does not work from an interrupt anyway)ot block. (block version does not work from an interrupt anyway)
666 {
667 tx_buffer_gap--;
668 tx_active_idx++;
669 if(tx_active_idx >= MAX_TX_BUFFER)
670 tx_active_idx = 0;
671 }
672 }
673 }
674 }
675
676 else
677 // Reset Receive FIFO
678 ADS8688_LPSPI_MASTER_BASEADDR->CR |= (LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK);
679
680 ARM_errata_838869();
681 }
682
683 // The following data only used for testing
684 static uint8_t auto_seq_en_reg;
685 static uint8_t channel_power_down_reg;
686 static uint8_t feature_select_reg;
687 static uint8_t range_select_reg[TOTAL_RANGE_SELECT_REGISTER];
688
689 static void initGPIO_ADS8688_CS(void)
690 {
691 /* Define the init structure for the chip select pin */
692 gpio_pin_config_t ps_config_out = {kGPIO_DigitalOutput, 1, kGPIO_NoIntmode};
693
694 /* Init output ADS8688 CS GPIO. */
695 GPIO_PinInit(ADS8688_CS_GPIO, ADS8688_CS_GPIO_PIN, &ps_config_out);
696 }
697
698
699
700
701 static uint8_t Read8688(LPSPI_Type *base, uint8_t address)
702 {
703 uint8_t read_address;
704 // uint8_t data;
705 // uint32_t i;
706
707 __attribute__((unused))
708 uint8_t data1, data2, data3;
709
710 // read_address=(address<<9);
711 read_address= address<<1;
712
713 // Reset Receive & Transmit FIFO
714 base->CR |= (LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK);
715
716 // Drop the CS signal
717 GPIO_PinWrite(ADS8688_CS_GPIO, ADS8688_CS_GPIO_PIN, 0U);
718
719 // Transmit the ADS8688 control byte to ADS8688
720 base->TDR = (uint32_t)read_address;
721 while (LPSPI_GetRxFifoCount(base) == 0);
722 data1 = (uint8_t)(base->RDR & 0xFF);
723
724 base->TDR = 0;
725 while (LPSPI_GetRxFifoCount(base) == 0);
726 data2 = (uint8_t)(base->RDR & 0xFF);
727
728 // There must be a minimum of 24 SCLKs after the CS
729 // falling edge for any read or write operation
730 // to the program register
731 base->TDR = 0;
732 while (LPSPI_GetRxFifoCount(base) == 0);
733 data3 = (uint8_t)(base->RDR & 0xFF);
734
735 // Raise the CS signal
736 GPIO_PinWrite(ADS8688_CS_GPIO, ADS8688_CS_GPIO_PIN, 1U);
737
738 return(data3);
739 }
740
741 //>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
742 // Reads the all the registers from ADS8688
743 static void Read_ADS8688_Internal_Registers(LPSPI_Type *base)
744 {
745 uint8_t i, address;
746
747 auto_seq_en_reg = Read8688(base, 0x01);
748 channel_power_down_reg = Read8688(base, 0x02);
749 feature_select_reg = Read8688(base, 0x03);
750
751 // Read range select registers
752 for(i=0; i<TOTAL_RANGE_SELECT_REGISTER; i++)
753 {
754 // Only read register 0x05 to 0x0c
755 address=i + 5;
756 range_select_reg[i] = Read8688(base, address);
757 }
758
759 // update STATUSCOM register
760 // Configs.int_val=(uint16_t)(internal_registers[2] >> 8);
761 }
762
763
764 //>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
765 // Write each register from ADS8688
766 //>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
767 static void Write8688(LPSPI_Type *base, uint8_t address, uint16_t data)
768 {
769 __attribute__((unused)) uint32_t i;
770 uint16_t write_data;
771 __attribute__((unused)) uint8_t received_command;
772
773 // Write the command register
774 if(address > 0x3F)
775 {
776 write_data= data;
777 }
778 // Write program register
779 else
780 {
781 // bits 15-9: register address; bit 8: write-1, read-0
782 // bits 7-0: data
783 write_data=(address<<9) | data;
784 write_data|=0b100000000;
785 }
786
787 // Reset Receive FIFO
788 base->CR |= (LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK);
789
790 // Drop the CS signal
791 GPIO_PinWrite(ADS8688_CS_GPIO, ADS8688_CS_GPIO_PIN, 0U);
792
793 base->TDR = write_data >> 8;
794 while (LPSPI_GetRxFifoCount(base) == 0);
795 i = base->RDR;
796
797 base->TDR = write_data;
798 while (LPSPI_GetRxFifoCount(base) == 0);
799 i = base->RDR;
800
801 // In order to accurately acquire and convert the input signal on the
802 // first selected channel in the next data frame, the command frame must be
803 // a complete frame of 32 cycles
804 if(address != 0xEF)
805 {
806 base->TDR = 0;
807 while (LPSPI_GetRxFifoCount(base) == 0);
808 if(address == 0xFF)
809 {
810 i = base->RDR;
811 }
812 else
813 {
814 received_command = base->RDR;
815 }
816
817 base->TDR = 0;
818 while (LPSPI_GetRxFifoCount(base) == 0);
819 i = base->RDR;
820 }
821
822 // Raise the CS signal
823 GPIO_PinWrite(ADS8688_CS_GPIO, ADS8688_CS_GPIO_PIN, 1U);
824 }
825
826 // Function to initialise ADS8688 ADC
827 static void initADS8688(void)
828 {
829 uint8_t i;
830 uint8_t write_address;
831 uint16_t write_data;
832
833 //Reset the program registers to their default values
834 write_address = 0xFF;
835 write_data = 0x8500;
836 Write8688(ADS8688_LPSPI_MASTER_BASEADDR, write_address, write_data);
837
838 //Set the SDO format to 0x01
839 write_address = 0x03;
840 write_data = 0x0001;
841 Write8688(ADS8688_LPSPI_MASTER_BASEADDR, write_address, write_data);
842
843 // write range select registers
844 for(i=0; i<TOTAL_RANGE_SELECT_REGISTER; i++)
845 {
846 // Only read register 0x05 to 0x0c
847 write_address=i + 5;
848 write_data = 0x000B;
849 Write8688(ADS8688_LPSPI_MASTER_BASEADDR, write_address, write_data);
850 }
851
852 // Set the device into STABY mode
853 // write_address = 0xFF;
854 // write_data = 0x8200;
855 // Write8688(EXAMPLE_LPSPI_MASTER_BASEADDR, write_address, write_data);
856
857 // Read all the R/W registers of ADS8688
858 Read_ADS8688_Internal_Registers(ADS8688_LPSPI_MASTER_BASEADDR);
859
860 // Start to scan the input of all channels by writing a reset command
861 // in the command register
862 write_address = 0xFF;
863 write_data = 0xA000;
864 Write8688(ADS8688_LPSPI_MASTER_BASEADDR, write_address, write_data);
865 }
866
867
868
869 // The following data only for process_rx_buffer
870 volatile bool static notify_flag0 = false;
871 volatile bool static notify_flag1 = false;
872 volatile bool static notify_flag2 = false;
873 volatile bool static notify_flag3 = false;
874
875 // The following 2 parameters should be from the ac-analogue plugin
876 static int8_t v_chn_pos[4];
877 static int8_t c_chn_pos[4];
878
879 /*
880 * Process an incoming Ethernet Sampled Value (SV) Frame.
881 * This is called from the TCIP task context.
882 */
883 // __RAMFUNC(RAM3)
884 // int8_t process_rx_buffer(struct pbuf *p)
885 int8_t process_rx_buffer(unsigned char *data)
886 {
887 uint8_t i, j, k;
888 uint8_t sv_id_length;
889 int16_t smp_cnt_accu, raw_index;
890 int16_t raw_offset;
891 int32_t sample_data;
892
893 // uint16_t ether_sv_data;
894 uint16_t smp_cnt;
895 // uint32_t ref_period;
896
897 bool channel_matched;
898 // BaseType_t xHigherPriorityTaskWoken = pdFALSE;
899
900 // rx_buffer_ptr = (struct sv_receive_buffer *) p->payload;
901 rx_buffer_ptr = (struct sv_receive_buffer *) data;
902
903 for(i=0; i<6; i++)
904 {
905 if(rev_mac_addr[i] != rx_buffer_ptr->destMac[i])
906 {
907 return DEST_MAC_ERR;
908 }
909 }
910
911 sv_id_length = rx_buffer_ptr->svidLength;
912
913 for(i=0; i<sv_id_length; i++)
914 {
915 if(rx_buffer_ptr->svID[i] != sv_config_ptr->rx_sv_config.MsvID[i])
916 {
917 return SV_ID_ERR;
918 }
919 }
920
921 /*
922 #if !VOLTAGE_SAMPLE
923 // uint32_t ref_period;
924 ref_period = (rx_buffer_ptr->ConfRef0<<8) + rx_buffer_ptr->ConfRef1;
925 if((ref_period >= PMIN) && (ref_period <= PMAX) && (ref_period != period))
926 {
927 period = ref_period;
928 PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, (period-1));
929 }
930 #endif
931 */
932 smp_cnt = (rx_buffer_ptr->smpCnt0<<8) + rx_buffer_ptr->smpCnt1;
933
934 if((smp_cnt == 0) && ( !process_bus_started ))
935 {
936 process_bus_started = true;
937 raw_offset = 0;
938
939 sample_counter_res = 0;
940
941 sample_cycle = 0;
942 last_cycle = -1;
943 }
944
945 if(process_bus_started)
946 {
947 smp_cnt_accu = smp_cnt;
948 raw_index_offset = smp_cnt_accu % DOUBLE_NPC;
949 raw_offset = raw_index_offset * MAX_SAMPLE_CHANNELS;
950
951
952 for(i=0; i<8; i++)
953 {
954 channel_matched = false;
955 for(j=0; j<4 && !channel_matched; j++)
956 {
957 if((rev_chn_pos[i] == v_chn_pos[j]) || (rev_chn_pos[i] == c_chn_pos[j]))
958 {
959 raw_index = raw_offset + rev_chn_pos[i];
960
961 sample_data = 0;
962 for(k=0; k<4; k++)
963 {
964 sample_data = sample_data + (int32_t)(rx_buffer_ptr->sampleData[(i<<3) + k] << (24-(k<<3)));
965 }
966
967 raw_data[raw_index] = sample_data;
968 channel_matched = true;
969 }
970 }
971 }
972
973 if((raw_index_offset >= HALF_NPC_1) && (raw_index_offset < NPC_1))
974 {
975 notify_flag2 = false;
976 if(!notify_flag1)
977 {
978 if((ncycles > 10) && (!calcs_done))
979 time_error = true;
980
981 sample_cycle = 1;
982 notify_flag1 = true;
983 if(process_ac_ready)
984 {
985 xTaskNotifyGive(xProcessAcHandle);
986 // vTaskNotifyGiveFromISR(xProcessAcHandle, &xHigherPriorityTaskWoken);
987 // portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
988 }
989 }
990 }
991 else if((raw_index_offset >= NPC_1) && (raw_index_offset < ONE_HALF_NPC_1))
992 {
993 notify_flag3 = false;
994 if(!notify_flag2)
995 {
996 if((ncycles > 10) && (!calcs_done))
997 time_error = true;
998
999 sample_cycle = 2;
1000 notify_flag2 = true;
1001 if(process_ac_ready)
1002 {
1003 xTaskNotifyGive(xProcessAcHandle);
1004 // vTaskNotifyGiveFromISR(xProcessAcHandle, &xHigherPriorityTaskWoken);
1005 // portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
1006 }
1007 }
1008 }
1009 else if((raw_index_offset >= ONE_HALF_NPC_1) && (raw_index_offset < DOUBLE_NPC_1))
1010 {
1011 notify_flag0 = false;
1012 if(!notify_flag3)
1013 {
1014 if((ncycles > 10) && (!calcs_done))
1015 time_error = true;
1016
1017 sample_cycle = 3;
1018 notify_flag3 = true;
1019 if(process_ac_ready)
1020 {
1021 xTaskNotifyGive(xProcessAcHandle);
1022 // vTaskNotifyGiveFromISR(xProcessAcHandle, &xHigherPriorityTaskWoken);
1023 // portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
1024 }
1025 }
1026 }
1027 else if((raw_index_offset >= 0) && (raw_index_offset < HALF_NPC_1))
1028 {
1029 notify_flag1 = false;
1030 if(!notify_flag0)
1031 {
1032 if((ncycles > 10) && (!calcs_done))
1033 time_error = true;
1034
1035 sample_cycle = 0;
1036 notify_flag0 = true;
1037 if(process_ac_ready)
1038 {
1039 xTaskNotifyGive(xProcessAcHandle);
1040 // vTaskNotifyGiveFromISR(xProcessAcHandle, &xHigherPriorityTaskWoken);
1041 // portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
1042 }
1043 }
1044 }
1045 }
1046
1047
1048 return 0;
1049 }
1050
1051
1052 #if VOLTAGE_SAMPLE
1053 uint8_t hwMacAddr[6] ={0x00, 0x04, 0x9F, 0x05, 0x4A, 0xE7};
1054 #else
1055 uint8_t hwMacAddr[6] ={0x00, 0x04, 0x9F, 0x05, 0x4A, 0xE8};
1056 #endif
1057
1058 static struct ethernet_savif sav_intf;
1059 static struct trans_savif trans_intf;
1060
1061 //__DATA(RAM4) static uint8_t rx_data[MAX_FRAME_LENGTH];
1062 static uint8_t rx_data[MAX_FRAME_LENGTH];
1063
1064 // temp file simulating downloaded config
1065 static struct PROCESS_BUS_CONFIG temp_sv_config
1066 ={1,
1067 80,
1068 0x4000,
1069 0,
1070 0,
1071 /*
1072 0,
1073 { 0x01, 0x0c, 0xcd, 0x04, 0x02, 0xff },
1074 { -1, -1, -1, -1 },
1075 { 4, 5, 6, 7 },
1076 { 0x30,0x30,0x30,0x30,0x30,0x30,0x4D,0x55,0x30,0x31 },
1077
1078 1,
1079 { 0x01, 0x0c, 0xcd, 0x04, 0x01, 0xff },
1080 { 0,1,2,3 },
1081 { -1,-1,-1,-1 },
1082 { 0x30,0x30,0x30,0x30,0x30,0x30,0x4D,0x55,0x30,0x30 }
1083 */
1084 #if VOLTAGE_SAMPLE
1085 {
1086 0,
1087 { 0x01, 0x0c, 0xcd, 0x04, 0x01, 0xff },
1088 { 4, 5, 6, 7 },
1089 { -1, -1, -1, -1 },
1090 { 0x30,0x30,0x30,0x30,0x30,0x30,0x4D,0x55,0x30,0x30 }
1091 },
1092
1093 {
1094 1,
1095 { 0x01, 0x0c, 0xcd, 0x04, 0x02, 0xff },
1096 { -1,-1,-1,-1 },
1097 { 0,1,2,3 },
1098 { 0x30,0x30,0x30,0x30,0x30,0x30,0x4D,0x55,0x30,0x31 }
1099 }
1100
1101 #else
1102
1103 {
1104 1,
1105 { 0x01, 0x0c, 0xcd, 0x04, 0x02, 0xff },
1106 { -1, -1, -1, -1 },
1107 { 0, 1, 2, 3 },
1108 { 0x30,0x30,0x30,0x30,0x30,0x30,0x4D,0x55,0x30,0x31 }
1109 },
1110
1111 {
1112 0,
1113 { 0x01, 0x0c, 0xcd, 0x04, 0x01, 0xff },
1114 { 4, 5, 6, 7 },
1115 { -1, -1, -1, -1 },
1116 { 0x30,0x30,0x30,0x30,0x30,0x30,0x4D,0x55,0x30,0x30 }
1117 }
1118
1119 #endif
1120 };
1121
1122
1123
1124 static void enable_ready_to_transfer(void)
1125 {
1126 ready_to_transfer = true;
1127 }
1128
1129
1130
1131
1132 static bool sav_rx_enabled(uint8_t *sav_mac_addr)
1133 {
1134 if (rx_sv_enable)
1135 {
1136 memcpy(sav_mac_addr, rev_mac_addr, 6);
1137 return true;
1138 }
1139 else
1140 {
1141 sav_mac_addr = NULL;
1142 return false;
1143 }
1144 }
1145
1146
1147
1148 static bool sav_tx_enabled(void)
1149 {
1150 if (tx_sv_enable)
1151 {
1152 return true;
1153 }
1154 else
1155 {
1156 return false;
1157 }
1158 }
1159
1160
1161
1162
1163 static void config_txsv(void)
1164 {
1165 uint8_t i,j;
1166
1167 tx_active_idx = 0;
1168 tx_next_idx = 0;
1169 tx_buffer_gap = 0;
1170
1171 for(i=0; i<4; i++)
1172 {
1173 trm_chn_pos[i] = sv_config_ptr->tx_sv_config.ct_chn[i];
1174 trm_chn_pos[i+4] = sv_config_ptr->tx_sv_config.vt_chn[i];
1175 }
1176
1177 for(i=0; i<MAX_TX_BUFFER; i++)
1178 {
1179 for(j=0; j<6; j++)
1180 {
1181 sv_tx_buffer[i].destMac[j] = sv_config_ptr->tx_sv_config.mac_address[j];
1182 sv_tx_buffer[i].sourceMac[j] = hwMacAddr[j];
1183 }
1184
1185 // This is the VLAN tag
1186 // sv_tx_buffer[i].etherType0 = (uint8_t)((ETHER_HEAD >> 8) & 0xFF);
1187 // sv_tx_buffer[i].etherType1 = (uint8_t)(ETHER_HEAD & 0xFF);
1188
1189 // sv_tx_buffer[i].etherInfo0 = (uint8_t)((ETHER_PRIORITY << 5) + (ETHER_CFI<<4) + ((ETHER_VID>>8) & 0x0F));
1190 // sv_tx_buffer[i].etherInfo1 = (uint8_t)(ETHER_VID & 0xFF);
1191
1192 sv_tx_buffer[i].etherSvData0 = (uint8_t)((ETHER_SV_DATA >> 8) & 0xFF);
1193 sv_tx_buffer[i].etherSvData1 = (uint8_t)(ETHER_SV_DATA & 0xFF);
1194
1195 sv_tx_buffer[i].appID0 = (uint8_t)((sv_config_ptr->app_Id >> 8) & 0xFF);
1196 sv_tx_buffer[i].appID1 = (uint8_t)(sv_config_ptr->app_Id & 0xFF);
1197
1198 sv_tx_buffer[i].svLength0 = (uint8_t)((SV_LENGTH >> 8) & 0xFF);
1199 sv_tx_buffer[i].svLength1 = (uint8_t)(SV_LENGTH & 0xFF);
1200
1201 sv_tx_buffer[i].reserved0 = (uint8_t)((sv_config_ptr->Reserved >> 24) & 0xFF);
1202 sv_tx_buffer[i].reserved1 = (uint8_t)((sv_config_ptr->Reserved >> 16) & 0xFF);
1203 sv_tx_buffer[i].reserved2 = (uint8_t)((sv_config_ptr->Reserved >> 8) & 0xFF);
1204 sv_tx_buffer[i].reserved3 = (uint8_t)(sv_config_ptr->Reserved & 0xFF);
1205
1206 sv_tx_buffer[i].imlicitPdu0 = (uint8_t)IMPLICIT_PDU_0;
1207 sv_tx_buffer[i].pduLength = (uint8_t)PDU_LENGTH;
1208
1209 sv_tx_buffer[i].imlicitInt0 = (uint8_t)IMPLICIT_INT_0;
1210 sv_tx_buffer[i].noAsduLength = (uint8_t)NO_ASDU_LENGTH;
1211 sv_tx_buffer[i].asduNumber = (uint8_t)ASDU_NUMBER;
1212
1213 sv_tx_buffer[i].imlicitSeq2 = (uint8_t)IMPLICIT_SEQ_2;
1214 sv_tx_buffer[i].seqLength = (uint8_t)SEQ_LENGTH;
1215 sv_tx_buffer[i].sequence = (uint8_t)SEQUENCE;
1216 sv_tx_buffer[i].asduLength = (uint8_t)ASDU_LENGTH;
1217
1218 sv_tx_buffer[i].imlicitString0 = (uint8_t)IMPLICIT_STRING_0;
1219 sv_tx_buffer[i].svidLength = (uint8_t)MAX_SVID_LENGTH;
1220
1221 for(j=0; j<MAX_SVID_LENGTH; j++)
1222 {
1223 sv_tx_buffer[i].svID[j] = sv_config_ptr->tx_sv_config.MsvID[j];
1224 }
1225
1226 sv_tx_buffer[i].imlicitInt2 = (uint8_t)IMPLICIT_INT_2;
1227 sv_tx_buffer[i].smpCntLength = (uint8_t)SMP_CNT_LENGTH;
1228 sv_tx_buffer[i].smpCnt0 = 0; // Initialise as zero, update later
1229 sv_tx_buffer[i].smpCnt1 = 0; // Initialise as zero, update later
1230
1231 sv_tx_buffer[i].imlicitInt3 = (uint8_t)IMPLICIT_INT_3;
1232 sv_tx_buffer[i].ConfRefLength = (uint8_t)CONF_REF_LENGTH;
1233
1234 sv_tx_buffer[i].ConfRef0 = (uint8_t)((sv_config_ptr->ConfRev >> 24) & 0xFF);
1235 sv_tx_buffer[i].ConfRef1 = (uint8_t)((sv_config_ptr->ConfRev >> 16) & 0xFF);
1236 sv_tx_buffer[i].ConfRef2 = (uint8_t)((sv_config_ptr->ConfRev >> 8) & 0xFF);
1237 sv_tx_buffer[i].ConfRef3 = (uint8_t)(sv_config_ptr->ConfRev & 0xFF);
1238
1239 sv_tx_buffer[i].imlicitInt5 = (uint8_t)IMPLICIT_INT_5;
1240 sv_tx_buffer[i].smpSynchLength = (uint8_t)SMP_SYNCH_LENGTH;
1241 sv_tx_buffer[i].smpSynch = 0; // Initialise as zero, update later
1242
1243 sv_tx_buffer[i].imlicitData7 = (uint8_t)IMPLICIT_DATA_7;
1244 sv_tx_buffer[i].smpDataLength = (uint8_t)SMP_DATA_LENGTH;
1245
1246 for(j=0; j<SMP_DATA_LENGTH; j++)
1247 {
1248 sv_tx_buffer[i].sampleData[j] = 0; // Initialise as zero, update later
1249 }
1250 }
1251 }
1252
1253 static void config_rxsv(void)
1254 {
1255 uint8_t i;
1256
1257 rx_buffer_ptr = (struct sv_receive_buffer *) rx_data;
1258
1259 for(i=0; i<6; i++)
1260 rev_mac_addr[i] = sv_config_ptr->rx_sv_config.mac_address[i];
1261
1262 // Add something here
1263 // for(i=0; i<MAX_REC_SV; i++)
1264 // {
1265 raw_index_offset = 0;
1266 // }
1267
1268 for(i=0; i<4; i++)
1269 {
1270 rev_chn_pos[i] = sv_config_ptr->rx_sv_config.ct_chn[i];
1271 rev_chn_pos[i+4] = sv_config_ptr->rx_sv_config.vt_chn[i];
1272 }
1273 }
1274
1275 void config_process_bus(void)
1276 {
1277 sysFreq0 = 50;
1278 sv_frame_length = sizeof(sv_tx_buffer[0]);
1279
1280 sv_config_ptr = &temp_sv_config;
1281 tx_sv_enable = sv_config_ptr->tx_sv_config.SvEna;
1282 rx_sv_enable = sv_config_ptr->rx_sv_config.SvEna;
1283
1284 if(tx_sv_enable)
1285 config_txsv();
1286
1287 if(rx_sv_enable)
1288 {
1289 process_bus_started = false;
1290 config_rxsv();
1291 }
1292 else
1293 {
1294 process_bus_started = true;
1295 }
1296
1297 sav_intf.process_rx_buffer = (process_rx_callback_fn) process_rx_buffer;
1298 sav_intf.sav_rx_enabled = (sav_rx_callback_fn) sav_rx_enabled;
1299 trans_intf.sav_tx_enabled = (sav_tx_callback_fn) sav_tx_enabled;
1300 trans_intf.enable_ready_to_transfer = (enable_trans_callback_fn) enable_ready_to_transfer;
1301 set_sav_interface( &sav_intf );
1302 set_trans_interface( &trans_intf );
1303 }
1304
1305
1306 // Only used for ac analog plugin, disable it for the time being
1307
1308 /*
1309 // For synchronise the sampling and ac analogue processing
1310 bool Process_ac_Start( uint32_t tickTime )
1311 {
1312 TickType_t xDelayMs = pdMS_TO_TICKS( tickTime ); // Delay for 15 ms
1313 if(ulTaskNotifyTake(pdFALSE, xDelay15ms) != 0)
1314 {
1315 return true;
1316 }
1317 else
1318 {
1319 return false;
1320 }
1321 }
1322
1323
1324 // --------------------------------------------------------------------------
1325
1326 //
1327 // Setup the ADS8688's register range values and the circular sample buffer
1328 //
1329 bool Sampler_Setup( const ePLATFORM_SamplerConfig_t *paeSamplerConfig,
1330 uint32_t uiNumChannelsReq,
1331 volatile stPLATFORM_SampleGrab_t * pastBuffer,
1332 uint32_t uiBufferElements )
1333 {
1334 bSamplingIsEnabled = false;
1335
1336 // Copy sampler config values over into ADS8688 register range registers
1337 uiNumChannels = uiNumChannelsReq;
1338 // FIXME: write ADS8688 register range values here!!!
1339
1340 // Set up circular buffer
1341 pastCircularBuffer = pastBuffer;
1342 uiCircularBufferEntries = uiBufferElements;
1343 return true;
1344 }
1345
1346 // --------------------------------------------------------------------------
1347
1348 //
1349 // Start capturing blocks of samples into the circular buffer
1350 //
1351 bool Sampler_Start(uint32_t uiPeriod_Nsec)
1352 {
1353 bool bRetVal = false; // Default return value to false
1354 uint32_t uNewPeriod;
1355
1356 if ( (uiNumChannels > 0U)
1357 && (uiNumChannels <= PLATFORM_SAMPLER_MAX_CHANNELS)
1358 && (pastCircularBuffer != NULL) )
1359 {
1360 // Clear circular buffer before starting to sample
1361 memset((void *)pastCircularBuffer, 0, uiCircularBufferEntries * sizeof(pastCircularBuffer[0]));
1362 uiCircularIndex = 0U;
1363 uiLastGrabbedTimestamp = 0xDEADBEEFU;
1364 uiLastGrabbedBufferIndex = 0xFFFFFFFFU;
1365
1366 // Calculate new PIT period
1367 uNewPeriod = CALCULATE_PERIOD(uiPeriod_Nsec,pitFreq);
1368
1369 // Write new PIT periods into the queue of periods
1370 uPeriod[2] = uNewPeriod;
1371 uPeriod[1] = uNewPeriod;
1372
1373 // Enable low-level sampling code
1374 bSamplingIsEnabled = true;
1375 bRetVal = true;
1376 }
1377
1378 return bRetVal;
1379 }
1380
1381 // --------------------------------------------------------------------------
1382
1383 //
1384 // Adjust the period (e.g. to align the sampling period with the AC phase)
1385 //
1386 bool Sampler_Adjust(uint32_t uiDelay_Nsec, uint32_t uiPeriod_Nsec)
1387 {
1388 uint32_t uNextPeriod, uNextNextPeriod;
1389
1390 uNextPeriod = CALCULATE_PERIOD(uiPeriod_Nsec, pitFreq);
1391 uNextNextPeriod = uNextPeriod;
1392
1393 if (uiDelay_Nsec != 0U)
1394 {
1395 uNextPeriod = CALCULATE_PERIOD(uPeriod[0] + uiDelay_Nsec, pitFreq);
1396 }
1397
1398 uPeriod[2] = uNextNextPeriod;
1399 uPeriod[1] = uNextPeriod;
1400
1401 return true;
1402 }
1403
1404 // --------------------------------------------------------------------------
1405
1406 //
1407 // Stop the sampler subsystem
1408 //
1409 bool Sampler_Stop(void)
1410 {
1411 bSamplingIsEnabled = false;
1412 return true;
1413 }
1414
1415 // --------------------------------------------------------------------------
1416
1417 //
1418 // Get the sampler subsystem's current 32-bit timer
1419 //
1420 uint32_t Sampler_GetTimer(void)
1421 {
1422 return PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_0);
1423 }
1424
1425 // --------------------------------------------------------------------------
1426
1427 //
1428 // Grab a sequential series of pointers to timestamped blocks of samples
1429 //
1430 uint32_t Sampler_Grab( uint32_t uiEarliestTimestamp,
1431 volatile stPLATFORM_SampleGrab_t ** papstGrabArray,
1432 uint32_t uiMaxBlocksToGrab)
1433 {
1434 uint32_t uiIndex;
1435 uint32_t uiWriteIndex;
1436 uint32_t uiCurrentIndex;
1437
1438 if ((uiEarliestTimestamp == uiLastGrabbedTimestamp) && (uiLastGrabbedBufferIndex != 0xFFFFFFFFU))
1439 {
1440 uiIndex = uiLastGrabbedBufferIndex;
1441 // Step forward to the next entry in the circular buffer
1442 if (++uiIndex >= uiCircularBufferEntries)
1443 {
1444 uiIndex = 0U;
1445 }
1446 }
1447 else
1448 {
1449 // Very first time around, start at the front of the circular buffer
1450 uiIndex = 0;
1451 }
1452
1453 uiCurrentIndex = uiCircularIndex; // Cache volatile index locally
1454 for (uiWriteIndex = 0U; uiWriteIndex < uiMaxBlocksToGrab; uiWriteIndex++)
1455 {
1456 if (uiIndex == uiCurrentIndex)
1457 {
1458 break;
1459 }
1460 papstGrabArray[uiWriteIndex] = &pastCircularBuffer[uiIndex];
1461 if (++uiIndex >= uiCircularBufferEntries)
1462 {
1463 uiIndex = 0U;
1464 }
1465 }
1466
1467 return uiWriteIndex;
1468 }
1469 */
1470
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Definition: platform_sampler_lpspi3_ad8688.h:33
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Definition: platform_sampler_lpspi3_ad8688.c:155
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Definition: platform_sampler_lpspi3_ad8688.h:59
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Definition: platform_sampler_lpspi3_ad8688.h:145
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Definition: platform_sampler_lpspi3_ad8688.h:116
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Definition: platform_sampler_lpspi3_ad8688.c:190
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Definition: platform_sampler_lpspi3_ad8688.c:885
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Definition: platform_sampler_lpspi3_ad8688.h:190
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Definition: platform_sampler_lpspi3_ad8688.c:52
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Definition: platform_sampler_lpspi3_ad8688.h:110
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Definition: platform_sampler_lpspi3_ad8688.h:68
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Definition: platform_sampler_lpspi3_ad8688.c:1062
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Definition: platform_sampler_lpspi3_ad8688.c:1059
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Definition: platform_sampler_lpspi3_ad8688.h:42
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Definition: platform_sampler_lpspi3_ad8688.h:276
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Definition: platform_sampler_lpspi3_ad8688.c:367
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Definition: platform_sampler_lpspi3_ad8688.c:483
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Definition: platform_sampler_lpspi3_ad8688.h:111
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Definition: platform_sampler_lpspi3_ad8688.c:685
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Definition: platform_sampler_lpspi3_ad8688.h:96
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platform_sampler_lpspi3_ad8688.h
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Definition: platform_sampler_lpspi3_ad8688.h:228
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Definition: platform_sampler_lpspi3_ad8688.c:117
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Definition: platform_sampler_lpspi3_ad8688.h:143
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Definition: platform_sampler_lpspi3_ad8688.h:162
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Definition: platform_sampler_lpspi3_ad8688.h:136
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Definition: platform_sampler_lpspi3_ad8688.h:159
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Definition: platform_sampler_lpspi3_ad8688.c:408
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Definition: platform_sampler_lpspi3_ad8688.h:105
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Definition: platform_sampler_lpspi3_ad8688.c:73
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Definition: platform_sampler_lpspi3_ad8688.c:176
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Definition: platform_sampler_lpspi3_ad8688.h:211
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Definition: platform_sampler_lpspi3_ad8688.h:87
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Definition: platform_sampler_lpspi3_ad8688.h:212
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Definition: MIMXRT1062.h:28210
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Definition: platform_sampler_lpspi3_ad8688.c:43
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Definition: platform_sampler_lpspi3_ad8688.h:279
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Definition: platform_sampler_lpspi3_ad8688.h:128
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Definition: platform_sampler_lpspi3_ad8688.c:45
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Definition: platform_sampler_lpspi3_ad8688.h:216
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Definition: platform_sampler_lpspi3_ad8688.h:39