Callisto4Bootloader: CSU Register Masks

Callisto4Bootloader

Macros
CSU Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » CSU Peripheral Access Layer

## Macros

#define | CSU_CSL_COUNT (32U)

## CSL - Config security level register

#define | CSU_CSL_SUR_S2_MASK (0x1U)
#define | CSU_CSL_SUR_S2_SHIFT (0U)
#define | CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
#define | CSU_CSL_SSR_S2_MASK (0x2U)
#define | CSU_CSL_SSR_S2_SHIFT (1U)
#define | CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
#define | CSU_CSL_NUR_S2_MASK (0x4U)
#define | CSU_CSL_NUR_S2_SHIFT (2U)
#define | CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
#define | CSU_CSL_NSR_S2_MASK (0x8U)
#define | CSU_CSL_NSR_S2_SHIFT (3U)
#define | CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
#define | CSU_CSL_SUW_S2_MASK (0x10U)
#define | CSU_CSL_SUW_S2_SHIFT (4U)
#define | CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
#define | CSU_CSL_SSW_S2_MASK (0x20U)
#define | CSU_CSL_SSW_S2_SHIFT (5U)
#define | CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
#define | CSU_CSL_NUW_S2_MASK (0x40U)
#define | CSU_CSL_NUW_S2_SHIFT (6U)
#define | CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
#define | CSU_CSL_NSW_S2_MASK (0x80U)
#define | CSU_CSL_NSW_S2_SHIFT (7U)
#define | CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
#define | CSU_CSL_LOCK_S2_MASK (0x100U)
#define | CSU_CSL_LOCK_S2_SHIFT (8U)
#define | CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
#define | CSU_CSL_SUR_S1_MASK (0x10000U)
#define | CSU_CSL_SUR_S1_SHIFT (16U)
#define | CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
#define | CSU_CSL_SSR_S1_MASK (0x20000U)
#define | CSU_CSL_SSR_S1_SHIFT (17U)
#define | CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
#define | CSU_CSL_NUR_S1_MASK (0x40000U)
#define | CSU_CSL_NUR_S1_SHIFT (18U)
#define | CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
#define | CSU_CSL_NSR_S1_MASK (0x80000U)
#define | CSU_CSL_NSR_S1_SHIFT (19U)
#define | CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
#define | CSU_CSL_SUW_S1_MASK (0x100000U)
#define | CSU_CSL_SUW_S1_SHIFT (20U)
#define | CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
#define | CSU_CSL_SSW_S1_MASK (0x200000U)
#define | CSU_CSL_SSW_S1_SHIFT (21U)
#define | CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
#define | CSU_CSL_NUW_S1_MASK (0x400000U)
#define | CSU_CSL_NUW_S1_SHIFT (22U)
#define | CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
#define | CSU_CSL_NSW_S1_MASK (0x800000U)
#define | CSU_CSL_NSW_S1_SHIFT (23U)
#define | CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
#define | CSU_CSL_LOCK_S1_MASK (0x1000000U)
#define | CSU_CSL_LOCK_S1_SHIFT (24U)
#define | CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)

## HP0 - HP0 register

#define | CSU_HP0_HP_DMA_MASK (0x4U)
#define | CSU_HP0_HP_DMA_SHIFT (2U)
#define | CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
#define | CSU_HP0_L_DMA_MASK (0x8U)
#define | CSU_HP0_L_DMA_SHIFT (3U)
#define | CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
#define | CSU_HP0_HP_LCDIF_MASK (0x10U)
#define | CSU_HP0_HP_LCDIF_SHIFT (4U)
#define | CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
#define | CSU_HP0_L_LCDIF_MASK (0x20U)
#define | CSU_HP0_L_LCDIF_SHIFT (5U)
#define | CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
#define | CSU_HP0_HP_CSI_MASK (0x40U)
#define | CSU_HP0_HP_CSI_SHIFT (6U)
#define | CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
#define | CSU_HP0_L_CSI_MASK (0x80U)
#define | CSU_HP0_L_CSI_SHIFT (7U)
#define | CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
#define | CSU_HP0_HP_PXP_MASK (0x100U)
#define | CSU_HP0_HP_PXP_SHIFT (8U)
#define | CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
#define | CSU_HP0_L_PXP_MASK (0x200U)
#define | CSU_HP0_L_PXP_SHIFT (9U)
#define | CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
#define | CSU_HP0_HP_DCP_MASK (0x400U)
#define | CSU_HP0_HP_DCP_SHIFT (10U)
#define | CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
#define | CSU_HP0_L_DCP_MASK (0x800U)
#define | CSU_HP0_L_DCP_SHIFT (11U)
#define | CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
#define | CSU_HP0_HP_ENET_MASK (0x4000U)
#define | CSU_HP0_HP_ENET_SHIFT (14U)
#define | CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
#define | CSU_HP0_L_ENET_MASK (0x8000U)
#define | CSU_HP0_L_ENET_SHIFT (15U)
#define | CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
#define | CSU_HP0_HP_USDHC1_MASK (0x10000U)
#define | CSU_HP0_HP_USDHC1_SHIFT (16U)
#define | CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
#define | CSU_HP0_L_USDHC1_MASK (0x20000U)
#define | CSU_HP0_L_USDHC1_SHIFT (17U)
#define | CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
#define | CSU_HP0_HP_USDHC2_MASK (0x40000U)
#define | CSU_HP0_HP_USDHC2_SHIFT (18U)
#define | CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
#define | CSU_HP0_L_USDHC2_MASK (0x80000U)
#define | CSU_HP0_L_USDHC2_SHIFT (19U)
#define | CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
#define | CSU_HP0_HP_TPSMP_MASK (0x100000U)
#define | CSU_HP0_HP_TPSMP_SHIFT (20U)
#define | CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
#define | CSU_HP0_L_TPSMP_MASK (0x200000U)
#define | CSU_HP0_L_TPSMP_SHIFT (21U)
#define | CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
#define | CSU_HP0_HP_USB_MASK (0x400000U)
#define | CSU_HP0_HP_USB_SHIFT (22U)
#define | CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
#define | CSU_HP0_L_USB_MASK (0x800000U)
#define | CSU_HP0_L_USB_SHIFT (23U)
#define | CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)

## SA - Secure access register

#define | CSU_SA_NSA_DMA_MASK (0x4U)
#define | CSU_SA_NSA_DMA_SHIFT (2U)
#define | CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
#define | CSU_SA_L_DMA_MASK (0x8U)
#define | CSU_SA_L_DMA_SHIFT (3U)
#define | CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
#define | CSU_SA_NSA_LCDIF_MASK (0x10U)
#define | CSU_SA_NSA_LCDIF_SHIFT (4U)
#define | CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
#define | CSU_SA_L_LCDIF_MASK (0x20U)
#define | CSU_SA_L_LCDIF_SHIFT (5U)
#define | CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
#define | CSU_SA_NSA_CSI_MASK (0x40U)
#define | CSU_SA_NSA_CSI_SHIFT (6U)
#define | CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
#define | CSU_SA_L_CSI_MASK (0x80U)
#define | CSU_SA_L_CSI_SHIFT (7U)
#define | CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
#define | CSU_SA_NSA_PXP_MASK (0x100U)
#define | CSU_SA_NSA_PXP_SHIFT (8U)
#define | CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
#define | CSU_SA_L_PXP_MASK (0x200U)
#define | CSU_SA_L_PXP_SHIFT (9U)
#define | CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
#define | CSU_SA_NSA_DCP_MASK (0x400U)
#define | CSU_SA_NSA_DCP_SHIFT (10U)
#define | CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
#define | CSU_SA_L_DCP_MASK (0x800U)
#define | CSU_SA_L_DCP_SHIFT (11U)
#define | CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
#define | CSU_SA_NSA_ENET_MASK (0x4000U)
#define | CSU_SA_NSA_ENET_SHIFT (14U)
#define | CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
#define | CSU_SA_L_ENET_MASK (0x8000U)
#define | CSU_SA_L_ENET_SHIFT (15U)
#define | CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
#define | CSU_SA_NSA_USDHC1_MASK (0x10000U)
#define | CSU_SA_NSA_USDHC1_SHIFT (16U)
#define | CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
#define | CSU_SA_L_USDHC1_MASK (0x20000U)
#define | CSU_SA_L_USDHC1_SHIFT (17U)
#define | CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
#define | CSU_SA_NSA_USDHC2_MASK (0x40000U)
#define | CSU_SA_NSA_USDHC2_SHIFT (18U)
#define | CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
#define | CSU_SA_L_USDHC2_MASK (0x80000U)
#define | CSU_SA_L_USDHC2_SHIFT (19U)
#define | CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
#define | CSU_SA_NSA_TPSMP_MASK (0x100000U)
#define | CSU_SA_NSA_TPSMP_SHIFT (20U)
#define | CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
#define | CSU_SA_L_TPSMP_MASK (0x200000U)
#define | CSU_SA_L_TPSMP_SHIFT (21U)
#define | CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
#define | CSU_SA_NSA_USB_MASK (0x400000U)
#define | CSU_SA_NSA_USB_SHIFT (22U)
#define | CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
#define | CSU_SA_L_USB_MASK (0x800000U)
#define | CSU_SA_L_USB_SHIFT (23U)
#define | CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)

## HPCONTROL0 - HPCONTROL0 register

#define | CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
#define | CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
#define | CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
#define | CSU_HPCONTROL0_L_DMA_MASK (0x8U)
#define | CSU_HPCONTROL0_L_DMA_SHIFT (3U)
#define | CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
#define | CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
#define | CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
#define | CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
#define | CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
#define | CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
#define | CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
#define | CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
#define | CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
#define | CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
#define | CSU_HPCONTROL0_L_CSI_MASK (0x80U)
#define | CSU_HPCONTROL0_L_CSI_SHIFT (7U)
#define | CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
#define | CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
#define | CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
#define | CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
#define | CSU_HPCONTROL0_L_PXP_MASK (0x200U)
#define | CSU_HPCONTROL0_L_PXP_SHIFT (9U)
#define | CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
#define | CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
#define | CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
#define | CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
#define | CSU_HPCONTROL0_L_DCP_MASK (0x800U)
#define | CSU_HPCONTROL0_L_DCP_SHIFT (11U)
#define | CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
#define | CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
#define | CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
#define | CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
#define | CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
#define | CSU_HPCONTROL0_L_ENET_SHIFT (15U)
#define | CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
#define | CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
#define | CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
#define | CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
#define | CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
#define | CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
#define | CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
#define | CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
#define | CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
#define | CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
#define | CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
#define | CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
#define | CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
#define | CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
#define | CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
#define | CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
#define | CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
#define | CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
#define | CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
#define | CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
#define | CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
#define | CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
#define | CSU_HPCONTROL0_L_USB_MASK (0x800000U)
#define | CSU_HPCONTROL0_L_USB_SHIFT (23U)
#define | CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ CSU_CSL_COUNT

#define CSU_CSL_COUNT (32U)

Definition at line 10803 of file MIMXRT1062.h.

## ◆ CSU_CSL_LOCK_S1

#define CSU_CSL_LOCK_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)

LOCK_S1 0b0..Not locked. The bits 16-23 can be written by the software. 0b1..The bits 16-23 are locked and can't be written by the software.

Definition at line 10799 of file MIMXRT1062.h.

## ◆ CSU_CSL_LOCK_S1_MASK

#define CSU_CSL_LOCK_S1_MASK (0x1000000U)

Definition at line 10793 of file MIMXRT1062.h.

## ◆ CSU_CSL_LOCK_S1_SHIFT

#define CSU_CSL_LOCK_S1_SHIFT (24U)

Definition at line 10794 of file MIMXRT1062.h.

## ◆ CSU_CSL_LOCK_S2

#define CSU_CSL_LOCK_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)

LOCK_S2 0b0..Not locked. Bits 7-0 can be written by the software. 0b1..Bits 7-0 are locked and cannot be written by the software

Definition at line 10736 of file MIMXRT1062.h.

## ◆ CSU_CSL_LOCK_S2_MASK

#define CSU_CSL_LOCK_S2_MASK (0x100U)

Definition at line 10730 of file MIMXRT1062.h.

## ◆ CSU_CSL_LOCK_S2_SHIFT

#define CSU_CSL_LOCK_S2_SHIFT (8U)

Definition at line 10731 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSR_S1

#define CSU_CSL_NSR_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)

NSR_S1 0b0..The non-secure supervisor read access is disabled for the first slave. 0b1..The non-secure supervisor read access is enabled for the first slave.

Definition at line 10764 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSR_S1_MASK

#define CSU_CSL_NSR_S1_MASK (0x80000U)

Definition at line 10758 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSR_S1_SHIFT

#define CSU_CSL_NSR_S1_SHIFT (19U)

Definition at line 10759 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSR_S2

#define CSU_CSL_NSR_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)

NSR_S2 0b0..The non-secure supervisor read access is disabled for the second slave. 0b1..The non-secure supervisor read access is enabled for the second slave.

Definition at line 10701 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSR_S2_MASK

#define CSU_CSL_NSR_S2_MASK (0x8U)

Definition at line 10695 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSR_S2_SHIFT

#define CSU_CSL_NSR_S2_SHIFT (3U)

Definition at line 10696 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSW_S1

#define CSU_CSL_NSW_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)

NSW_S1 0b0..The non-secure supervisor write access is disabled for the first slave. 0b1..The non-secure supervisor write access is enabled for the first slave

Definition at line 10792 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSW_S1_MASK

#define CSU_CSL_NSW_S1_MASK (0x800000U)

Definition at line 10786 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSW_S1_SHIFT

#define CSU_CSL_NSW_S1_SHIFT (23U)

Definition at line 10787 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSW_S2

#define CSU_CSL_NSW_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)

NSW_S2 0b0..The non-secure supervisor write access is disabled for the second slave. 0b1..The non-secure supervisor write access is enabled for the second slave.

Definition at line 10729 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSW_S2_MASK

#define CSU_CSL_NSW_S2_MASK (0x80U)

Definition at line 10723 of file MIMXRT1062.h.

## ◆ CSU_CSL_NSW_S2_SHIFT

#define CSU_CSL_NSW_S2_SHIFT (7U)

Definition at line 10724 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUR_S1

#define CSU_CSL_NUR_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)

NUR_S1 0b0..The non-secure user read access is disabled for the first slave. 0b1..The non-secure user read access is enabled for the first slave.

Definition at line 10757 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUR_S1_MASK

#define CSU_CSL_NUR_S1_MASK (0x40000U)

Definition at line 10751 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUR_S1_SHIFT

#define CSU_CSL_NUR_S1_SHIFT (18U)

Definition at line 10752 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUR_S2

#define CSU_CSL_NUR_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)

NUR_S2 0b0..The non-secure user read access is disabled for the second slave. 0b1..The non-secure user read access is enabled for the second slave.

Definition at line 10694 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUR_S2_MASK

#define CSU_CSL_NUR_S2_MASK (0x4U)

Definition at line 10688 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUR_S2_SHIFT

#define CSU_CSL_NUR_S2_SHIFT (2U)

Definition at line 10689 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUW_S1

#define CSU_CSL_NUW_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)

NUW_S1 0b0..The non-secure user write access is disabled for the first slave. 0b1..The non-secure user write access is enabled for the first slave.

Definition at line 10785 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUW_S1_MASK

#define CSU_CSL_NUW_S1_MASK (0x400000U)

Definition at line 10779 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUW_S1_SHIFT

#define CSU_CSL_NUW_S1_SHIFT (22U)

Definition at line 10780 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUW_S2

#define CSU_CSL_NUW_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)

NUW_S2 0b0..The non-secure user write access is disabled for the second slave. 0b1..The non-secure user write access is enabled for the second slave.

Definition at line 10722 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUW_S2_MASK

#define CSU_CSL_NUW_S2_MASK (0x40U)

Definition at line 10716 of file MIMXRT1062.h.

## ◆ CSU_CSL_NUW_S2_SHIFT

#define CSU_CSL_NUW_S2_SHIFT (6U)

Definition at line 10717 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSR_S1

#define CSU_CSL_SSR_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)

SSR_S1 0b0..The secure supervisor read access is disabled for the first slave. 0b1..The secure supervisor read access is enabled for the first slave.

Definition at line 10750 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSR_S1_MASK

#define CSU_CSL_SSR_S1_MASK (0x20000U)

Definition at line 10744 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSR_S1_SHIFT

#define CSU_CSL_SSR_S1_SHIFT (17U)

Definition at line 10745 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSR_S2

#define CSU_CSL_SSR_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)

SSR_S2 0b0..The secure supervisor read access is disabled for the second slave. 0b1..The secure supervisor read access is enabled for the second slave.

Definition at line 10687 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSR_S2_MASK

#define CSU_CSL_SSR_S2_MASK (0x2U)

Definition at line 10681 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSR_S2_SHIFT

#define CSU_CSL_SSR_S2_SHIFT (1U)

Definition at line 10682 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSW_S1

#define CSU_CSL_SSW_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)

SSW_S1 0b0..The secure supervisor write access is disabled for the first slave. 0b1..The secure supervisor write access is enabled for the first slave.

Definition at line 10778 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSW_S1_MASK

#define CSU_CSL_SSW_S1_MASK (0x200000U)

Definition at line 10772 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSW_S1_SHIFT

#define CSU_CSL_SSW_S1_SHIFT (21U)

Definition at line 10773 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSW_S2

#define CSU_CSL_SSW_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)

SSW_S2 0b0..The secure supervisor write access is disabled for the second slave. 0b1..The secure supervisor write access is enabled for the second slave.

Definition at line 10715 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSW_S2_MASK

#define CSU_CSL_SSW_S2_MASK (0x20U)

Definition at line 10709 of file MIMXRT1062.h.

## ◆ CSU_CSL_SSW_S2_SHIFT

#define CSU_CSL_SSW_S2_SHIFT (5U)

Definition at line 10710 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUR_S1

#define CSU_CSL_SUR_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)

SUR_S1 0b0..The secure user read access is disabled for the first slave. 0b1..The secure user read access is enabled for the first slave.

Definition at line 10743 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUR_S1_MASK

#define CSU_CSL_SUR_S1_MASK (0x10000U)

Definition at line 10737 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUR_S1_SHIFT

#define CSU_CSL_SUR_S1_SHIFT (16U)

Definition at line 10738 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUR_S2

#define CSU_CSL_SUR_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)

SUR_S2 0b0..The secure user read access is disabled for the second slave. 0b1..The secure user read access is enabled for the second slave.

Definition at line 10680 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUR_S2_MASK

#define CSU_CSL_SUR_S2_MASK (0x1U)

Definition at line 10674 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUR_S2_SHIFT

#define CSU_CSL_SUR_S2_SHIFT (0U)

Definition at line 10675 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUW_S1

#define CSU_CSL_SUW_S1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)

SUW_S1 0b0..The secure user write access is disabled for the first slave. 0b1..The secure user write access is enabled for the first slave.

Definition at line 10771 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUW_S1_MASK

#define CSU_CSL_SUW_S1_MASK (0x100000U)

Definition at line 10765 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUW_S1_SHIFT

#define CSU_CSL_SUW_S1_SHIFT (20U)

Definition at line 10766 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUW_S2

#define CSU_CSL_SUW_S2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)

SUW_S2 0b0..The secure user write access is disabled for the second slave. 0b1..The secure user write access is enabled for the second slave.

Definition at line 10708 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUW_S2_MASK

#define CSU_CSL_SUW_S2_MASK (0x10U)

Definition at line 10702 of file MIMXRT1062.h.

## ◆ CSU_CSL_SUW_S2_SHIFT

#define CSU_CSL_SUW_S2_SHIFT (4U)

Definition at line 10703 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_CSI

#define CSU_HP0_HP_CSI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)

HP_CSI 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10841 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_CSI_MASK

#define CSU_HP0_HP_CSI_MASK (0x40U)

Definition at line 10835 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_CSI_SHIFT

#define CSU_HP0_HP_CSI_SHIFT (6U)

Definition at line 10836 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_DCP

#define CSU_HP0_HP_DCP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)

HP_DCP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10869 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_DCP_MASK

#define CSU_HP0_HP_DCP_MASK (0x400U)

Definition at line 10863 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_DCP_SHIFT

#define CSU_HP0_HP_DCP_SHIFT (10U)

Definition at line 10864 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_DMA

#define CSU_HP0_HP_DMA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)

HP_DMA 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10813 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_DMA_MASK

#define CSU_HP0_HP_DMA_MASK (0x4U)

Definition at line 10807 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_DMA_SHIFT

#define CSU_HP0_HP_DMA_SHIFT (2U)

Definition at line 10808 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_ENET

#define CSU_HP0_HP_ENET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)

HP_ENET 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10883 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_ENET_MASK

#define CSU_HP0_HP_ENET_MASK (0x4000U)

Definition at line 10877 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_ENET_SHIFT

#define CSU_HP0_HP_ENET_SHIFT (14U)

Definition at line 10878 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_LCDIF

#define CSU_HP0_HP_LCDIF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)

HP_LCDIF 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10827 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_LCDIF_MASK

#define CSU_HP0_HP_LCDIF_MASK (0x10U)

Definition at line 10821 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_LCDIF_SHIFT

#define CSU_HP0_HP_LCDIF_SHIFT (4U)

Definition at line 10822 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_PXP

#define CSU_HP0_HP_PXP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)

HP_PXP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10855 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_PXP_MASK

#define CSU_HP0_HP_PXP_MASK (0x100U)

Definition at line 10849 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_PXP_SHIFT

#define CSU_HP0_HP_PXP_SHIFT (8U)

Definition at line 10850 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_TPSMP

#define CSU_HP0_HP_TPSMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)

HP_TPSMP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10925 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_TPSMP_MASK

#define CSU_HP0_HP_TPSMP_MASK (0x100000U)

Definition at line 10919 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_TPSMP_SHIFT

#define CSU_HP0_HP_TPSMP_SHIFT (20U)

Definition at line 10920 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USB

#define CSU_HP0_HP_USB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)

HP_USB 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10939 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USB_MASK

#define CSU_HP0_HP_USB_MASK (0x400000U)

Definition at line 10933 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USB_SHIFT

#define CSU_HP0_HP_USB_SHIFT (22U)

Definition at line 10934 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USDHC1

#define CSU_HP0_HP_USDHC1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)

HP_USDHC1 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10897 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USDHC1_MASK

#define CSU_HP0_HP_USDHC1_MASK (0x10000U)

Definition at line 10891 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USDHC1_SHIFT

#define CSU_HP0_HP_USDHC1_SHIFT (16U)

Definition at line 10892 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USDHC2

#define CSU_HP0_HP_USDHC2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)

HP_USDHC2 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

Definition at line 10911 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USDHC2_MASK

#define CSU_HP0_HP_USDHC2_MASK (0x40000U)

Definition at line 10905 of file MIMXRT1062.h.

## ◆ CSU_HP0_HP_USDHC2_SHIFT

#define CSU_HP0_HP_USDHC2_SHIFT (18U)

Definition at line 10906 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_CSI

#define CSU_HP0_L_CSI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10848 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_CSI_MASK

#define CSU_HP0_L_CSI_MASK (0x80U)

Definition at line 10842 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_CSI_SHIFT

#define CSU_HP0_L_CSI_SHIFT (7U)

Definition at line 10843 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_DCP

#define CSU_HP0_L_DCP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit cannot be written by the software.

Definition at line 10876 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_DCP_MASK

#define CSU_HP0_L_DCP_MASK (0x800U)

Definition at line 10870 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_DCP_SHIFT

#define CSU_HP0_L_DCP_SHIFT (11U)

Definition at line 10871 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_DMA

#define CSU_HP0_L_DMA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10820 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_DMA_MASK

#define CSU_HP0_L_DMA_MASK (0x8U)

Definition at line 10814 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_DMA_SHIFT

#define CSU_HP0_L_DMA_SHIFT (3U)

Definition at line 10815 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_ENET

#define CSU_HP0_L_ENET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10890 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_ENET_MASK

#define CSU_HP0_L_ENET_MASK (0x8000U)

Definition at line 10884 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_ENET_SHIFT

#define CSU_HP0_L_ENET_SHIFT (15U)

Definition at line 10885 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_LCDIF

#define CSU_HP0_L_LCDIF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10834 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_LCDIF_MASK

#define CSU_HP0_L_LCDIF_MASK (0x20U)

Definition at line 10828 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_LCDIF_SHIFT

#define CSU_HP0_L_LCDIF_SHIFT (5U)

Definition at line 10829 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_PXP

#define CSU_HP0_L_PXP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10862 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_PXP_MASK

#define CSU_HP0_L_PXP_MASK (0x200U)

Definition at line 10856 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_PXP_SHIFT

#define CSU_HP0_L_PXP_SHIFT (9U)

Definition at line 10857 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_TPSMP

#define CSU_HP0_L_TPSMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10932 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_TPSMP_MASK

#define CSU_HP0_L_TPSMP_MASK (0x200000U)

Definition at line 10926 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_TPSMP_SHIFT

#define CSU_HP0_L_TPSMP_SHIFT (21U)

Definition at line 10927 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USB

#define CSU_HP0_L_USB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10946 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USB_MASK

#define CSU_HP0_L_USB_MASK (0x800000U)

Definition at line 10940 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USB_SHIFT

#define CSU_HP0_L_USB_SHIFT (23U)

Definition at line 10941 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USDHC1

#define CSU_HP0_L_USDHC1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10904 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USDHC1_MASK

#define CSU_HP0_L_USDHC1_MASK (0x20000U)

Definition at line 10898 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USDHC1_SHIFT

#define CSU_HP0_L_USDHC1_SHIFT (17U)

Definition at line 10899 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USDHC2

#define CSU_HP0_L_USDHC2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10918 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USDHC2_MASK

#define CSU_HP0_L_USDHC2_MASK (0x80000U)

Definition at line 10912 of file MIMXRT1062.h.

## ◆ CSU_HP0_L_USDHC2_SHIFT

#define CSU_HP0_L_USDHC2_SHIFT (19U)

Definition at line 10913 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_CSI

#define CSU_HPCONTROL0_HPC_CSI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)

HPC_CSI 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11129 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_CSI_MASK

#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)

Definition at line 11123 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_CSI_SHIFT

#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)

Definition at line 11124 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_DCP

#define CSU_HPCONTROL0_HPC_DCP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)

HPC_DCP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11157 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_DCP_MASK

#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)

Definition at line 11151 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_DCP_SHIFT

#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)

Definition at line 11152 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_DMA

#define CSU_HPCONTROL0_HPC_DMA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)

HPC_DMA 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11101 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_DMA_MASK

#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)

Definition at line 11095 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_DMA_SHIFT

#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)

Definition at line 11096 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_ENET

#define CSU_HPCONTROL0_HPC_ENET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)

HPC_ENET 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11171 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_ENET_MASK

#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)

Definition at line 11165 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_ENET_SHIFT

#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)

Definition at line 11166 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_LCDIF

#define CSU_HPCONTROL0_HPC_LCDIF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)

HPC_LCDIF 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11115 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_LCDIF_MASK

#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)

Definition at line 11109 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_LCDIF_SHIFT

#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)

Definition at line 11110 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_PXP

#define CSU_HPCONTROL0_HPC_PXP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)

HPC_PXP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11143 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_PXP_MASK

#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)

Definition at line 11137 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_PXP_SHIFT

#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)

Definition at line 11138 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_TPSMP

#define CSU_HPCONTROL0_HPC_TPSMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)

HPC_TPSMP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11213 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_TPSMP_MASK

#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)

Definition at line 11207 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_TPSMP_SHIFT

#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)

Definition at line 11208 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USB

#define CSU_HPCONTROL0_HPC_USB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)

HPC_USB 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11227 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USB_MASK

#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)

Definition at line 11221 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USB_SHIFT

#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)

Definition at line 11222 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USDHC1

#define CSU_HPCONTROL0_HPC_USDHC1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)

HPC_USDHC1 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11185 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USDHC1_MASK

#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)

Definition at line 11179 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USDHC1_SHIFT

#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)

Definition at line 11180 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USDHC2

#define CSU_HPCONTROL0_HPC_USDHC2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)

HPC_USDHC2 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

Definition at line 11199 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USDHC2_MASK

#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)

Definition at line 11193 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_HPC_USDHC2_SHIFT

#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)

Definition at line 11194 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_CSI

#define CSU_HPCONTROL0_L_CSI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11136 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_CSI_MASK

#define CSU_HPCONTROL0_L_CSI_MASK (0x80U)

Definition at line 11130 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_CSI_SHIFT

#define CSU_HPCONTROL0_L_CSI_SHIFT (7U)

Definition at line 11131 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_DCP

#define CSU_HPCONTROL0_L_DCP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11164 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_DCP_MASK

#define CSU_HPCONTROL0_L_DCP_MASK (0x800U)

Definition at line 11158 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_DCP_SHIFT

#define CSU_HPCONTROL0_L_DCP_SHIFT (11U)

Definition at line 11159 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_DMA

#define CSU_HPCONTROL0_L_DMA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11108 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_DMA_MASK

#define CSU_HPCONTROL0_L_DMA_MASK (0x8U)

Definition at line 11102 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_DMA_SHIFT

#define CSU_HPCONTROL0_L_DMA_SHIFT (3U)

Definition at line 11103 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_ENET

#define CSU_HPCONTROL0_L_ENET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11178 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_ENET_MASK

#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)

Definition at line 11172 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_ENET_SHIFT

#define CSU_HPCONTROL0_L_ENET_SHIFT (15U)

Definition at line 11173 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_LCDIF

#define CSU_HPCONTROL0_L_LCDIF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11122 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_LCDIF_MASK

#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)

Definition at line 11116 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_LCDIF_SHIFT

#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)

Definition at line 11117 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_PXP

#define CSU_HPCONTROL0_L_PXP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11150 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_PXP_MASK

#define CSU_HPCONTROL0_L_PXP_MASK (0x200U)

Definition at line 11144 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_PXP_SHIFT

#define CSU_HPCONTROL0_L_PXP_SHIFT (9U)

Definition at line 11145 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_TPSMP

#define CSU_HPCONTROL0_L_TPSMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11220 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_TPSMP_MASK

#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)

Definition at line 11214 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_TPSMP_SHIFT

#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)

Definition at line 11215 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USB

#define CSU_HPCONTROL0_L_USB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11234 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USB_MASK

#define CSU_HPCONTROL0_L_USB_MASK (0x800000U)

Definition at line 11228 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USB_SHIFT

#define CSU_HPCONTROL0_L_USB_SHIFT (23U)

Definition at line 11229 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USDHC1

#define CSU_HPCONTROL0_L_USDHC1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11192 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USDHC1_MASK

#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)

Definition at line 11186 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USDHC1_SHIFT

#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)

Definition at line 11187 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USDHC2

#define CSU_HPCONTROL0_L_USDHC2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11206 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USDHC2_MASK

#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)

Definition at line 11200 of file MIMXRT1062.h.

## ◆ CSU_HPCONTROL0_L_USDHC2_SHIFT

#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)

Definition at line 11201 of file MIMXRT1062.h.

## ◆ CSU_SA_L_CSI

#define CSU_SA_L_CSI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10992 of file MIMXRT1062.h.

## ◆ CSU_SA_L_CSI_MASK

#define CSU_SA_L_CSI_MASK (0x80U)

Definition at line 10986 of file MIMXRT1062.h.

## ◆ CSU_SA_L_CSI_SHIFT

#define CSU_SA_L_CSI_SHIFT (7U)

Definition at line 10987 of file MIMXRT1062.h.

## ◆ CSU_SA_L_DCP

#define CSU_SA_L_DCP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11020 of file MIMXRT1062.h.

## ◆ CSU_SA_L_DCP_MASK

#define CSU_SA_L_DCP_MASK (0x800U)

Definition at line 11014 of file MIMXRT1062.h.

## ◆ CSU_SA_L_DCP_SHIFT

#define CSU_SA_L_DCP_SHIFT (11U)

Definition at line 11015 of file MIMXRT1062.h.

## ◆ CSU_SA_L_DMA

#define CSU_SA_L_DMA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10964 of file MIMXRT1062.h.

## ◆ CSU_SA_L_DMA_MASK

#define CSU_SA_L_DMA_MASK (0x8U)

Definition at line 10958 of file MIMXRT1062.h.

## ◆ CSU_SA_L_DMA_SHIFT

#define CSU_SA_L_DMA_SHIFT (3U)

Definition at line 10959 of file MIMXRT1062.h.

## ◆ CSU_SA_L_ENET

#define CSU_SA_L_ENET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11034 of file MIMXRT1062.h.

## ◆ CSU_SA_L_ENET_MASK

#define CSU_SA_L_ENET_MASK (0x8000U)

Definition at line 11028 of file MIMXRT1062.h.

## ◆ CSU_SA_L_ENET_SHIFT

#define CSU_SA_L_ENET_SHIFT (15U)

Definition at line 11029 of file MIMXRT1062.h.

## ◆ CSU_SA_L_LCDIF

#define CSU_SA_L_LCDIF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 10978 of file MIMXRT1062.h.

## ◆ CSU_SA_L_LCDIF_MASK

#define CSU_SA_L_LCDIF_MASK (0x20U)

Definition at line 10972 of file MIMXRT1062.h.

## ◆ CSU_SA_L_LCDIF_SHIFT

#define CSU_SA_L_LCDIF_SHIFT (5U)

Definition at line 10973 of file MIMXRT1062.h.

## ◆ CSU_SA_L_PXP

#define CSU_SA_L_PXP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11006 of file MIMXRT1062.h.

## ◆ CSU_SA_L_PXP_MASK

#define CSU_SA_L_PXP_MASK (0x200U)

Definition at line 11000 of file MIMXRT1062.h.

## ◆ CSU_SA_L_PXP_SHIFT

#define CSU_SA_L_PXP_SHIFT (9U)

Definition at line 11001 of file MIMXRT1062.h.

## ◆ CSU_SA_L_TPSMP

#define CSU_SA_L_TPSMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11076 of file MIMXRT1062.h.

## ◆ CSU_SA_L_TPSMP_MASK

#define CSU_SA_L_TPSMP_MASK (0x200000U)

Definition at line 11070 of file MIMXRT1062.h.

## ◆ CSU_SA_L_TPSMP_SHIFT

#define CSU_SA_L_TPSMP_SHIFT (21U)

Definition at line 11071 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USB

#define CSU_SA_L_USB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11090 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USB_MASK

#define CSU_SA_L_USB_MASK (0x800000U)

Definition at line 11084 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USB_SHIFT

#define CSU_SA_L_USB_SHIFT (23U)

Definition at line 11085 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USDHC1

#define CSU_SA_L_USDHC1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11048 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USDHC1_MASK

#define CSU_SA_L_USDHC1_MASK (0x20000U)

Definition at line 11042 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USDHC1_SHIFT

#define CSU_SA_L_USDHC1_SHIFT (17U)

Definition at line 11043 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USDHC2

#define CSU_SA_L_USDHC2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

Definition at line 11062 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USDHC2_MASK

#define CSU_SA_L_USDHC2_MASK (0x80000U)

Definition at line 11056 of file MIMXRT1062.h.

## ◆ CSU_SA_L_USDHC2_SHIFT

#define CSU_SA_L_USDHC2_SHIFT (19U)

Definition at line 11057 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_CSI

#define CSU_SA_NSA_CSI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)

NSA_CSI - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 10985 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_CSI_MASK

#define CSU_SA_NSA_CSI_MASK (0x40U)

Definition at line 10979 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_CSI_SHIFT

#define CSU_SA_NSA_CSI_SHIFT (6U)

Definition at line 10980 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_DCP

#define CSU_SA_NSA_DCP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)

NSA_DCP - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 11013 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_DCP_MASK

#define CSU_SA_NSA_DCP_MASK (0x400U)

Definition at line 11007 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_DCP_SHIFT

#define CSU_SA_NSA_DCP_SHIFT (10U)

Definition at line 11008 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_DMA

#define CSU_SA_NSA_DMA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)

NSA_DMA - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 10957 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_DMA_MASK

#define CSU_SA_NSA_DMA_MASK (0x4U)

Definition at line 10951 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_DMA_SHIFT

#define CSU_SA_NSA_DMA_SHIFT (2U)

Definition at line 10952 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_ENET

#define CSU_SA_NSA_ENET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)

NSA_ENET - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 11027 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_ENET_MASK

#define CSU_SA_NSA_ENET_MASK (0x4000U)

Definition at line 11021 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_ENET_SHIFT

#define CSU_SA_NSA_ENET_SHIFT (14U)

Definition at line 11022 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_LCDIF

#define CSU_SA_NSA_LCDIF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)

NSA_LCDIF - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 10971 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_LCDIF_MASK

#define CSU_SA_NSA_LCDIF_MASK (0x10U)

Definition at line 10965 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_LCDIF_SHIFT

#define CSU_SA_NSA_LCDIF_SHIFT (4U)

Definition at line 10966 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_PXP

#define CSU_SA_NSA_PXP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)

NSA_PXP - Non-Secure Access Policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 10999 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_PXP_MASK

#define CSU_SA_NSA_PXP_MASK (0x100U)

Definition at line 10993 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_PXP_SHIFT

#define CSU_SA_NSA_PXP_SHIFT (8U)

Definition at line 10994 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_TPSMP

#define CSU_SA_NSA_TPSMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)

NSA_TPSMP - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 11069 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_TPSMP_MASK

#define CSU_SA_NSA_TPSMP_MASK (0x100000U)

Definition at line 11063 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_TPSMP_SHIFT

#define CSU_SA_NSA_TPSMP_SHIFT (20U)

Definition at line 11064 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USB

#define CSU_SA_NSA_USB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)

NSA_USB - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 11083 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USB_MASK

#define CSU_SA_NSA_USB_MASK (0x400000U)

Definition at line 11077 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USB_SHIFT

#define CSU_SA_NSA_USB_SHIFT (22U)

Definition at line 11078 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USDHC1

#define CSU_SA_NSA_USDHC1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)

NSA_USDHC1 - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 11041 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USDHC1_MASK

#define CSU_SA_NSA_USDHC1_MASK (0x10000U)

Definition at line 11035 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USDHC1_SHIFT

#define CSU_SA_NSA_USDHC1_SHIFT (16U)

Definition at line 11036 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USDHC2

#define CSU_SA_NSA_USDHC2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)

NSA_USDHC2 - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

Definition at line 11055 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USDHC2_MASK

#define CSU_SA_NSA_USDHC2_MASK (0x40000U)

Definition at line 11049 of file MIMXRT1062.h.

## ◆ CSU_SA_NSA_USDHC2_SHIFT

#define CSU_SA_NSA_USDHC2_SHIFT (18U)

Definition at line 11050 of file MIMXRT1062.h.