Callisto4Bootloader: CMSIS/cmsis_armclang.h Source File

Callisto4Bootloader

cmsis_armclang.h
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1 /**************************************************************************/
7 /*
8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
26
27 #ifndef __CMSIS_ARMCLANG_H
28 #define __CMSIS_ARMCLANG_H
29
30 #pragma clang system_header /* treat file as system include file */
31
32 #ifndef __ARM_COMPAT_H
33 #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
34 #endif
35
36 /* CMSIS compiler specific defines */
37 #ifndef __ASM
38 #define __ASM __asm
39 #endif
40 #ifndef __INLINE
41 #define __INLINE __inline
42 #endif
43 #ifndef __STATIC_INLINE
44 #define __STATIC_INLINE static __inline
45 #endif
46 #ifndef __STATIC_FORCEINLINE
47 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
48 #endif
49 #ifndef __NO_RETURN
50 #define __NO_RETURN __attribute__((__noreturn__))
51 #endif
52 #ifndef __USED
53 #define __USED __attribute__((used))
54 #endif
55 #ifndef __WEAK
56 #define __WEAK __attribute__((weak))
57 #endif
58 #ifndef __PACKED
59 #define __PACKED __attribute__((packed, aligned(1)))
60 #endif
61 #ifndef __PACKED_STRUCT
62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
63 #endif
64 #ifndef __PACKED_UNION
65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
66 #endif
67 #ifndef __UNALIGNED_UINT32 /* deprecated */
68 #pragma clang diagnostic push
69 #pragma clang diagnostic ignored "-Wpacked"
70 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
71 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
72 #pragma clang diagnostic pop
73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
74 #endif
75 #ifndef __UNALIGNED_UINT16_WRITE
76 #pragma clang diagnostic push
77 #pragma clang diagnostic ignored "-Wpacked"
78 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
79 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
80 #pragma clang diagnostic pop
81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
82 #endif
83 #ifndef __UNALIGNED_UINT16_READ
84 #pragma clang diagnostic push
85 #pragma clang diagnostic ignored "-Wpacked"
86 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
87 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
88 #pragma clang diagnostic pop
89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
90 #endif
91 #ifndef __UNALIGNED_UINT32_WRITE
92 #pragma clang diagnostic push
93 #pragma clang diagnostic ignored "-Wpacked"
94 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
95 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
96 #pragma clang diagnostic pop
97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
98 #endif
99 #ifndef __UNALIGNED_UINT32_READ
100 #pragma clang diagnostic push
101 #pragma clang diagnostic ignored "-Wpacked"
102 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
104 #pragma clang diagnostic pop
105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
106 #endif
107 #ifndef __ALIGNED
108 #define __ALIGNED(x) __attribute__((aligned(x)))
109 #endif
110 #ifndef __RESTRICT
111 #define __RESTRICT __restrict
112 #endif
113
114
115 /* ########################### Core Function Access ########################### */
126 /* intrinsic void __enable_irq(); see arm_compat.h */
127
128
134 /* intrinsic void __disable_irq(); see arm_compat.h */
135
136
142 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
143 {
144 uint32_t result;
145
146 __ASM volatile ("MRS %0, control" : "=r" (result) );
147 return(result);
148 }
149
150
151 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
152
157 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
158 {
159 uint32_t result;
160
161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
162 return(result);
163 }
164 #endif
165
166
172 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
173 {
174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
175 }
176
177
178 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
179
184 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
185 {
186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
187 }
188 #endif
189
190
196 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
197 {
198 uint32_t result;
199
200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
201 return(result);
202 }
203
204
210 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
211 {
212 uint32_t result;
213
214 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
215 return(result);
216 }
217
218
224 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
225 {
226 uint32_t result;
227
228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
229 return(result);
230 }
231
232
238 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
239 {
240 uint32_t result;
241
242 __ASM volatile ("MRS %0, psp" : "=r" (result) );
243 return(result);
244 }
245
246
247 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
248
253 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
254 {
255 uint32_t result;
256
257 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
258 return(result);
259 }
260 #endif
261
262
268 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
269 {
270 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
271 }
272
273
274 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
275
280 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
281 {
282 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
283 }
284 #endif
285
286
292 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
293 {
294 uint32_t result;
295
296 __ASM volatile ("MRS %0, msp" : "=r" (result) );
297 return(result);
298 }
299
300
301 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
302
307 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
308 {
309 uint32_t result;
310
311 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
312 return(result);
313 }
314 #endif
315
316
322 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
323 {
324 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
325 }
326
327
328 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
329
334 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
335 {
336 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
337 }
338 #endif
339
340
341 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
342
347 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
348 {
349 uint32_t result;
350
351 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
352 return(result);
353 }
354
355
361 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
362 {
363 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
364 }
365 #endif
366
367
373 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
374 {
375 uint32_t result;
376
377 __ASM volatile ("MRS %0, primask" : "=r" (result) );
378 return(result);
379 }
380
381
382 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
383
388 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
389 {
390 uint32_t result;
391
392 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
393 return(result);
394 }
395 #endif
396
397
403 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
404 {
405 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
406 }
407
408
409 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
410
415 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
416 {
417 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
418 }
419 #endif
420
421
422 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
423 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
424 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
425
430 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
431
432
438 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
439
440
446 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
447 {
448 uint32_t result;
449
450 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
451 return(result);
452 }
453
454
455 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
456
461 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
462 {
463 uint32_t result;
464
465 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
466 return(result);
467 }
468 #endif
469
470
476 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
477 {
478 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
479 }
480
481
482 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
483
488 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
489 {
490 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
491 }
492 #endif
493
494
501 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
502 {
503 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
504 }
505
506
512 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
513 {
514 uint32_t result;
515
516 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
517 return(result);
518 }
519
520
521 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
522
527 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
528 {
529 uint32_t result;
530
531 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
532 return(result);
533 }
534 #endif
535
536
542 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
543 {
544 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
545 }
546
547
548 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
549
554 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
555 {
556 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
557 }
558 #endif
559
560 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
561 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
562 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
563
564
565 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
566 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
567
577 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
578 {
579 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
580 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
581 // without main extensions, the non-secure PSPLIM is RAZ/WI
582 return 0U;
583 #else
584 uint32_t result;
585 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
586 return result;
587 #endif
588 }
589
590 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
591
600 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
601 {
602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
603 // without main extensions, the non-secure PSPLIM is RAZ/WI
604 return 0U;
605 #else
606 uint32_t result;
607 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
608 return result;
609 #endif
610 }
611 #endif
612
613
623 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
624 {
625 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
626 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
627 // without main extensions, the non-secure PSPLIM is RAZ/WI
628 (void)ProcStackPtrLimit;
629 #else
630 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
631 #endif
632 }
633
634
635 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
636
645 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
646 {
647 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
648 // without main extensions, the non-secure PSPLIM is RAZ/WI
649 (void)ProcStackPtrLimit;
650 #else
651 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
652 #endif
653 }
654 #endif
655
656
665 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
666 {
667 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
668 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
669 // without main extensions, the non-secure MSPLIM is RAZ/WI
670 return 0U;
671 #else
672 uint32_t result;
673 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
674 return result;
675 #endif
676 }
677
678
679 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
680
688 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
689 {
690 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
691 // without main extensions, the non-secure MSPLIM is RAZ/WI
692 return 0U;
693 #else
694 uint32_t result;
695 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
696 return result;
697 #endif
698 }
699 #endif
700
701
710 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
711 {
712 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
713 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
714 // without main extensions, the non-secure MSPLIM is RAZ/WI
715 (void)MainStackPtrLimit;
716 #else
717 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
718 #endif
719 }
720
721
722 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
723
731 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
732 {
733 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
734 // without main extensions, the non-secure MSPLIM is RAZ/WI
735 (void)MainStackPtrLimit;
736 #else
737 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
738 #endif
739 }
740 #endif
741
742 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
743 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
744
750 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
751 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
752 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
753 #else
754 #define __get_FPSCR() ((uint32_t)0U)
755 #endif
756
762 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
763 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
764 #define __set_FPSCR __builtin_arm_set_fpscr
765 #else
766 #define __set_FPSCR(x) ((void)(x))
767 #endif
768
769
773 /* ########################## Core Instruction Access ######################### */
779 /* Define macros for porting to both thumb1 and thumb2.
780 * For thumb1, use low register (r0-r7), specified by constraint "l"
781 * Otherwise, use general registers, specified by constraint "r" */
782 #if defined (__thumb__) && !defined (__thumb2__)
783 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
784 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
785 #define __CMSIS_GCC_USE_REG(r) "l" (r)
786 #else
787 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
788 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
789 #define __CMSIS_GCC_USE_REG(r) "r" (r)
790 #endif
791
796 #define __NOP __builtin_arm_nop
797
802 #define __WFI __builtin_arm_wfi
803
804
810 #define __WFE __builtin_arm_wfe
811
812
817 #define __SEV __builtin_arm_sev
818
819
826 #define __ISB() __builtin_arm_isb(0xF)
827
833 #define __DSB() __builtin_arm_dsb(0xF)
834
835
841 #define __DMB() __builtin_arm_dmb(0xF)
842
843
850 #define __REV(value) __builtin_bswap32(value)
851
852
859 #define __REV16(value) __ROR(__REV(value), 16)
860
861
868 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
869
870
878 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
879 {
880 op2 %= 32U;
881 if (op2 == 0U)
882 {
883 return op1;
884 }
885 return (op1 >> op2) | (op1 << (32U - op2));
886 }
887
888
896 #define __BKPT(value) __ASM volatile ("bkpt "#value)
897
898
905 #define __RBIT __builtin_arm_rbit
906
913 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
914 {
915 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
916 __builtin_clz(0) is undefined behaviour, so handle this case specially.
917 This guarantees ARM-compatible results if happening to compile on a non-ARM
918 target, and ensures the compiler doesn't decide to activate any
919 optimisations using the logic "value was passed to __builtin_clz, so it
920 is non-zero".
921 ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
922 single CLZ instruction.
923 */
924 if (value == 0U)
925 {
926 return 32U;
927 }
928 return __builtin_clz(value);
929 }
930
931
932 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
933 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
934 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
935 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
936
942 #define __LDREXB (uint8_t)__builtin_arm_ldrex
943
944
951 #define __LDREXH (uint16_t)__builtin_arm_ldrex
952
953
960 #define __LDREXW (uint32_t)__builtin_arm_ldrex
961
962
971 #define __STREXB (uint32_t)__builtin_arm_strex
972
973
982 #define __STREXH (uint32_t)__builtin_arm_strex
983
984
993 #define __STREXW (uint32_t)__builtin_arm_strex
994
995
1000 #define __CLREX __builtin_arm_clrex
1001
1002 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1003 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1004 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1005 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1006
1007
1008 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1009 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1010 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1011
1019 #define __SSAT __builtin_arm_ssat
1020
1021
1029 #define __USAT __builtin_arm_usat
1030
1031
1039 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
1040 {
1041 uint32_t result;
1042
1043 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1044 return(result);
1045 }
1046
1047
1054 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
1055 {
1056 uint32_t result;
1057
1058 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
1059 return ((uint8_t) result); /* Add explicit type cast here */
1060 }
1061
1062
1069 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
1070 {
1071 uint32_t result;
1072
1073 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
1074 return ((uint16_t) result); /* Add explicit type cast here */
1075 }
1076
1077
1084 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
1085 {
1086 uint32_t result;
1087
1088 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
1089 return(result);
1090 }
1091
1092
1099 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
1100 {
1101 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1102 }
1103
1104
1111 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
1112 {
1113 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1114 }
1115
1116
1123 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
1124 {
1125 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
1126 }
1127
1128 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1129 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1130 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1131
1139 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
1140 {
1141 if ((sat >= 1U) && (sat <= 32U))
1142 {
1143 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
1144 const int32_t min = -1 - max ;
1145 if (val > max)
1146 {
1147 return max;
1148 }
1149 else if (val < min)
1150 {
1151 return min;
1152 }
1153 }
1154 return val;
1155 }
1156
1164 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
1165 {
1166 if (sat <= 31U)
1167 {
1168 const uint32_t max = ((1U << sat) - 1U);
1169 if (val > (int32_t)max)
1170 {
1171 return max;
1172 }
1173 else if (val < 0)
1174 {
1175 return 0U;
1176 }
1177 }
1178 return (uint32_t)val;
1179 }
1180
1181 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1182 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1183 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1184
1185
1186 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1187 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1188
1194 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
1195 {
1196 uint32_t result;
1197
1198 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
1199 return ((uint8_t) result);
1200 }
1201
1202
1209 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
1210 {
1211 uint32_t result;
1212
1213 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
1214 return ((uint16_t) result);
1215 }
1216
1217
1224 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
1225 {
1226 uint32_t result;
1227
1228 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
1229 return(result);
1230 }
1231
1232
1239 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
1240 {
1241 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1242 }
1243
1244
1251 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
1252 {
1253 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1254 }
1255
1256
1263 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
1264 {
1265 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1266 }
1267
1268
1275 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
1276
1277
1284 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
1285
1286
1293 #define __LDAEX (uint32_t)__builtin_arm_ldaex
1294
1295
1304 #define __STLEXB (uint32_t)__builtin_arm_stlex
1305
1306
1315 #define __STLEXH (uint32_t)__builtin_arm_stlex
1316
1317
1326 #define __STLEX (uint32_t)__builtin_arm_stlex
1327
1328 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1329 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1330 /* end of group CMSIS_Core_InstructionInterface */
1332
1333
1334 /* ################### Compiler specific Intrinsics ########################### */
1340 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1341
1342 #define __SADD8 __builtin_arm_sadd8
1343 #define __QADD8 __builtin_arm_qadd8
1344 #define __SHADD8 __builtin_arm_shadd8
1345 #define __UADD8 __builtin_arm_uadd8
1346 #define __UQADD8 __builtin_arm_uqadd8
1347 #define __UHADD8 __builtin_arm_uhadd8
1348 #define __SSUB8 __builtin_arm_ssub8
1349 #define __QSUB8 __builtin_arm_qsub8
1350 #define __SHSUB8 __builtin_arm_shsub8
1351 #define __USUB8 __builtin_arm_usub8
1352 #define __UQSUB8 __builtin_arm_uqsub8
1353 #define __UHSUB8 __builtin_arm_uhsub8
1354 #define __SADD16 __builtin_arm_sadd16
1355 #define __QADD16 __builtin_arm_qadd16
1356 #define __SHADD16 __builtin_arm_shadd16
1357 #define __UADD16 __builtin_arm_uadd16
1358 #define __UQADD16 __builtin_arm_uqadd16
1359 #define __UHADD16 __builtin_arm_uhadd16
1360 #define __SSUB16 __builtin_arm_ssub16
1361 #define __QSUB16 __builtin_arm_qsub16
1362 #define __SHSUB16 __builtin_arm_shsub16
1363 #define __USUB16 __builtin_arm_usub16
1364 #define __UQSUB16 __builtin_arm_uqsub16
1365 #define __UHSUB16 __builtin_arm_uhsub16
1366 #define __SASX __builtin_arm_sasx
1367 #define __QASX __builtin_arm_qasx
1368 #define __SHASX __builtin_arm_shasx
1369 #define __UASX __builtin_arm_uasx
1370 #define __UQASX __builtin_arm_uqasx
1371 #define __UHASX __builtin_arm_uhasx
1372 #define __SSAX __builtin_arm_ssax
1373 #define __QSAX __builtin_arm_qsax
1374 #define __SHSAX __builtin_arm_shsax
1375 #define __USAX __builtin_arm_usax
1376 #define __UQSAX __builtin_arm_uqsax
1377 #define __UHSAX __builtin_arm_uhsax
1378 #define __USAD8 __builtin_arm_usad8
1379 #define __USADA8 __builtin_arm_usada8
1380 #define __SSAT16 __builtin_arm_ssat16
1381 #define __USAT16 __builtin_arm_usat16
1382 #define __UXTB16 __builtin_arm_uxtb16
1383 #define __UXTAB16 __builtin_arm_uxtab16
1384 #define __SXTB16 __builtin_arm_sxtb16
1385 #define __SXTAB16 __builtin_arm_sxtab16
1386 #define __SMUAD __builtin_arm_smuad
1387 #define __SMUADX __builtin_arm_smuadx
1388 #define __SMLAD __builtin_arm_smlad
1389 #define __SMLADX __builtin_arm_smladx
1390 #define __SMLALD __builtin_arm_smlald
1391 #define __SMLALDX __builtin_arm_smlaldx
1392 #define __SMUSD __builtin_arm_smusd
1393 #define __SMUSDX __builtin_arm_smusdx
1394 #define __SMLSD __builtin_arm_smlsd
1395 #define __SMLSDX __builtin_arm_smlsdx
1396 #define __SMLSLD __builtin_arm_smlsld
1397 #define __SMLSLDX __builtin_arm_smlsldx
1398 #define __SEL __builtin_arm_sel
1399 #define __QADD __builtin_arm_qadd
1400 #define __QSUB __builtin_arm_qsub
1401
1402 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1403 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1404
1405 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1406 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1407
1408 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1409 {
1410 int32_t result;
1411
1412 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1413 return(result);
1414 }
1415
1416 #endif /* (__ARM_FEATURE_DSP == 1) */
1417
1420 #endif /* __CMSIS_ARMCLANG_H */
__ROR
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
Rotate Right in unsigned value (32 bit)
Definition: cmsis_armclang.h:878
__CLZ
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
Count leading zeros.
Definition: cmsis_armclang.h:913
__get_APSR
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition: cmsis_armcc.h:170
__get_CONTROL
__STATIC_INLINE uint32_t __get_CONTROL(void)
Enable IRQ Interrupts.
Definition: cmsis_armcc.h:134
__set_PSP
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
Definition: cmsis_armcc.h:206
T_UINT32_READ
__PACKED_STRUCT T_UINT32_READ
Definition: cmsis_armclang.h:103
__SMMLA
__STATIC_FORCEINLINE int32_t __SMMLA(int32_t x, int32_t y, int32_t sum)
Definition: arm_math.h:1062
__USAT
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition: cmsis_armclang.h:1164
__PACKED_STRUCT
#define __PACKED_STRUCT
Definition: cmsis_armclang.h:62
__get_IPSR
__STATIC_INLINE uint32_t __get_IPSR(void)
Get IPSR Register.
Definition: cmsis_armcc.h:158
__set_MSP
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
Definition: cmsis_armcc.h:230
__attribute__
struct __attribute__((packed)) T_UINT32
Definition: cmsis_armclang.h:71
__CMSIS_GCC_USE_REG
#define __CMSIS_GCC_USE_REG(r)
Definition: cmsis_armclang.h:789
T_UINT16_READ
__PACKED_STRUCT T_UINT16_READ
Definition: cmsis_armclang.h:87
T_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE
Definition: cmsis_armclang.h:95
T_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE
Definition: cmsis_armclang.h:79
sat
uint32_t sat
Definition: cmsis_armcc.h:741
__SSAT
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition: cmsis_armclang.h:1139
__CMSIS_GCC_OUT_REG
#define __CMSIS_GCC_OUT_REG(r)
Definition: cmsis_armclang.h:787
__ASM
#define __ASM
Definition: cmsis_armclang.h:38
__get_xPSR
__STATIC_INLINE uint32_t __get_xPSR(void)
Get xPSR Register.
Definition: cmsis_armcc.h:182
__get_PRIMASK
__STATIC_INLINE uint32_t __get_PRIMASK(void)
Get Priority Mask.
Definition: cmsis_armcc.h:242
__set_CONTROL
__STATIC_INLINE void __set_CONTROL(uint32_t control)
Set Control Register.
Definition: cmsis_armcc.h:146
__set_PRIMASK
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
Definition: cmsis_armcc.h:254
min
#define min(a, b)
Minimum.
Definition: c4_qspi.h:41
__get_MSP
__STATIC_INLINE uint32_t __get_MSP(void)
Get Main Stack Pointer.
Definition: cmsis_armcc.h:218
max
#define max(a, b)
Maximum.
Definition: c4_qspi.h:26
__STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE
Definition: cmsis_armclang.h:47
__get_PSP
__STATIC_INLINE uint32_t __get_PSP(void)
Get Process Stack Pointer.
Definition: cmsis_armcc.h:194