Callisto4Bootloader: c4_WDOG_reg_t Struct Reference

Callisto4Bootloader

Data Structures | Data Fields
c4_WDOG_reg_t Struct Reference

Structure to overlay on the watchdog registers. More...

`#include <c4_watchdog_types.h>`

## Data Structures

union | c4_WDOG_wicr
| Watchdog Interrupt Control. More...

## Data Fields

union {
struct {
uint16_t WDZST:1
| Watchdog Low Power. More...
uint16_t WDBG:1
| Watchdog DEBUG Enable. More...
uint16_t WDE:1
| Watchdog Enable. More...
uint16_t WDT:1
| WDOG_B Time-out assertion. More...
uint16_t SRS:1
| Software Reset Signal. More...
uint16_t WDA:1
| WDOG_B assertion. More...
uint16_t SRE:1
| Software reset extension. More...
uint16_t WDW:1
| Watchdog Disable for Wait. More...
uint16_t WT:8
| Watchdog Time-out Field. More...
} B
uint16_t R
} | WCR
| The Watchdog Control Register (WDOG_WCR) controls the WDOG operation. More...
union {
struct {
uint16_t WSR
} B
uint16_t R
} | WSR
| Watchdog Service. More...
union {
struct {
uint16_t SFTW:1
| Software Reset. More...
uint16_t TOUT:1
| TOUT. More...
uint16_t rsvd1:2
| reserved More...
uint16_t POR:1
| Power On Reset. Indicates whether the reset is the result of a power on reset. More...
uint16_t rsvd2:11
| reserved More...
} B
uint16_t R
} | WRSR
| Watchdog Reset Status. More...
union c4_WDOG_reg_t::c4_WDOG_wicr | WICR
union {
struct {
uint16_t PDE:1
| Power Down Enable bit. More...
uint16_t resvd:15
} B
uint16_t R
} | WMCR
| Watchdog Miscellaneous Control. More...

## Detailed Description

Structure to overlay on the watchdog registers.

The structure allows access either as whole word registers (.R) or using bitfield structures (.B.xxx).

Definition at line 32 of file c4_watchdog_types.h.

## Field Documentation

## ◆ B [1/4]

struct { ... } c4_WDOG_reg_t::B

Bitfield representation.

Referenced by c4_setWdogInterrupt().

## ◆ B [2/4]

struct { ... } c4_WDOG_reg_t::B

Bitfield representation.

## ◆ B [3/4]

struct { ... } c4_WDOG_reg_t::B

Bitfield representation.

## ◆ B [4/4]

struct { ... } c4_WDOG_reg_t::B

Bitfield representation.

## ◆ PDE

uint16_t c4_WDOG_reg_t::PDE

Power Down Enable bit.

Reset value of this bit is 1, which means the power down counter inside the WDOG is enabled after reset. The software must write 0 to this bit to disable the counter within 16 seconds of reset de-assertion. Once disabled this counter cannot be enabled again. See Power-down counter event for operation of this counter.

Note
  This bit is write-one once only bit. Once software sets this bit it cannot be reset until the next system reset.

- 0b - Power Down Counter of WDOG is disabled.
- 1b - Power Down Counter of WDOG is enabled (Default).

Definition at line 260 of file c4_watchdog_types.h.

## ◆ POR

uint16_t c4_WDOG_reg_t::POR

Power On Reset. Indicates whether the reset is the result of a power on reset.

- 0b - Reset is not the result of a power on reset.
- 1b - Reset is the result of a power on reset.

Definition at line 200 of file c4_watchdog_types.h.

## ◆ R

uint16_t c4_WDOG_reg_t::R

Register representation.

Definition at line 146 of file c4_watchdog_types.h.

## ◆ resvd

uint16_t c4_WDOG_reg_t::resvd

reserved.

Definition at line 273 of file c4_watchdog_types.h.

## ◆ rsvd1

uint16_t c4_WDOG_reg_t::rsvd1

reserved

Definition at line 199 of file c4_watchdog_types.h.

## ◆ rsvd2

uint16_t c4_WDOG_reg_t::rsvd2

reserved

Definition at line 205 of file c4_watchdog_types.h.

## ◆ SFTW

uint16_t c4_WDOG_reg_t::SFTW

Software Reset.

Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit

- 0b - Reset is not the result of a software reset.
- 1b - Reset is the result of a software reset.

Definition at line 185 of file c4_watchdog_types.h.

## ◆ SRE

uint16_t c4_WDOG_reg_t::SRE

Software reset extension.

An option way to generate software reset adopt a new way to generate a more robust software reset. This bit can be set/clear with IP bus and will be reset with power-on reset .

- 0b - using original way to generate software reset (default)
- 1b - using new way to generate software reset.

Definition at line 113 of file c4_watchdog_types.h.

## ◆ SRS

uint16_t c4_WDOG_reg_t::SRS

Software Reset Signal.

Controls the software assertion of the WDOG-generated reset signal WDOG_RESET_B_DEB . This bit automatically resets to "1" after it has been asserted to "0".

Note
  This bit does not generate the software reset to the block.

- 0b - Assert system reset signal.
- 1b - No effect on the system (Default).

Definition at line 96 of file c4_watchdog_types.h.

## ◆ TOUT

uint16_t c4_WDOG_reg_t::TOUT

TOUT.

Timeout. Indicates whether the reset is the result of a WDOG timeout.

- 0b - Reset is not the result of a WDOG timeout.
- 1b - Reset is the result of a WDOG timeout.

Definition at line 192 of file c4_watchdog_types.h.

## ◆ WCR

union { ... } c4_WDOG_reg_t::WCR

The Watchdog Control Register (WDOG_WCR) controls the WDOG operation.

- WDZST, WDBG and WDW are write-once only bits. Once the software does a write access to these bits, they will be locked and cannot be reprogrammed until the next system reset assertion.
- WDE is a write one once only bit. Once software performs a write "1" operation to this bit it cannot be reset/cleared until the next system reset.
- WDT is also a write one once only bit. Once software performs a write "1" operation to this bit it cannot be reset/cleared until the next POR. This bit does not get reset/ cleared due to any system reset.

## ◆ WDA

uint16_t c4_WDOG_reg_t::WDA

WDOG_B assertion.

Controls the software assertion of the WDOG_B signal.

- 0b - Assert WDOG_B output.
- 1b - No effect on system (Default).

Definition at line 106 of file c4_watchdog_types.h.

## ◆ WDBG

uint16_t c4_WDOG_reg_t::WDBG

Watchdog DEBUG Enable.

Determines the operation of the WDOG during DEBUG mode. This bit is write once only.

- 0b - Continue WDOG timer operation (Default).
- 1b - Suspend the watchdog timer.

Definition at line 68 of file c4_watchdog_types.h.

## ◆ WDE

uint16_t c4_WDOG_reg_t::WDE

Watchdog Enable.

Enables or disables the WDOG block. This is a write one once only bit. It is not possible to clear this bit by a software write, once the bit is set.

Note
  This bit can be set/reset in debug mode (exception).

- 0b - Disable the Watchdog (Default).
- 1b - Enable the Watchdog.

Definition at line 76 of file c4_watchdog_types.h.

## ◆ WDT

uint16_t c4_WDOG_reg_t::WDT

WDOG_B Time-out assertion.

Determines if the WDOG_B gets asserted upon a Watchdog Time-out Event. This is a write-one once only bit.

Note
  There is no effect on WDOG_RESET_B_DEB (WDOG Reset) upon writing on this bit. WDOG_B gets asserted along with WDOG_RESET_B_DEB if this bit is set.

- 0b - No effect on WDOG_B (Default).
- 1b - Assert WDOG_B upon a Watchdog Time-out event.

Definition at line 85 of file c4_watchdog_types.h.

## ◆ WDW

uint16_t c4_WDOG_reg_t::WDW

Watchdog Disable for Wait.

This bit determines the operation of WDOG during Low Power WAIT mode. This is a write once only bit.

- 0b - Continue WDOG timer operation (Default).
- 1b - Suspend WDOG timer operation.

Definition at line 122 of file c4_watchdog_types.h.

## ◆ WDZST

uint16_t c4_WDOG_reg_t::WDZST

Watchdog Low Power.

Determines the operation of the WDOG during low-power modes. This bit is write once-only.

Note
  The WDOG can continue/suspend the timer operation in the low-power modes (STOP and DOZE mode).

- 0b - Continue timer operation (Default).
- 1b - Suspend the watchdog timer.

Definition at line 58 of file c4_watchdog_types.h.

## ◆ WICR

union c4_WDOG_reg_t::c4_WDOG_wicr c4_WDOG_reg_t::WICR

Referenced by c4_setWdogInterrupt().

## ◆ WMCR

union { ... } c4_WDOG_reg_t::WMCR

Watchdog Miscellaneous Control.

WDOG_WMCR Controls the Power Down counter operation.

## ◆ WRSR

union { ... } c4_WDOG_reg_t::WRSR

Watchdog Reset Status.

The WRSR is a read-only register that records the source of the output reset assertion. It is not cleared by a hard reset. Therefore, only one bit in the WRSR will always be asserted high. The register will always indicate the source of the last reset generated due to WDOG. Read access to this register is with one wait state. Any write performed on this register will generate a Peripheral Bus Error .

A reset can be generated by the following sources, as listed in priority from highest to lowest:

- Watchdog Time-out
- Software Reset

## ◆ WSR [1/2]

uint16_t c4_WDOG_reg_t::WSR

Definition at line 156 of file c4_watchdog_types.h.

## ◆ WSR [2/2]

union { ... } c4_WDOG_reg_t::WSR

Watchdog Service.

When enabled, the WDOG requires that a service sequence be written to the Watchdog Service Register (WSR) to prevent the timeout condition.

Note
  Executing the service sequence will reload the WDOG timeout counter.

## ◆ WT

uint16_t c4_WDOG_reg_t::WT

Watchdog Time-out Field.

This 8-bit field contains the time-out value that is loaded into the Watchdog counter after the service routine has been performed or after the Watchdog is enabled. After reset, WT[7:0] must have a value written to it before enabling the Watchdog otherwise count value of zero which is 0.5 seconds is loaded into the counter.

Note
  : The time-out value can be written at any point of time but it is loaded to the counter at the time when WDOG is enabled or after the service routine has been performed. For more information see Timeout event.

- 00000000b - 0.5 Seconds (Default).
- 00000001b - 1.0 Seconds.
- 00000010b - 1.5 Seconds.
- 00000011b - 2.0 Seconds.
- 11111111b - 128 Seconds.

Definition at line 130 of file c4_watchdog_types.h.

The documentation for this struct was generated from the following file:

- lib/c4_watchdog_types.h