Callisto4Bootloader: Globals

Callisto4Bootloader

### - p -

- PARSER_KEYWORDS : c4_parser.h
- PGC : MIMXRT1062.h
- PGC_BASE : MIMXRT1062.h
- PGC_BASE_ADDRS : MIMXRT1062.h
- PGC_BASE_PTRS : MIMXRT1062.h
- PGC_CPU_CTRL_PCR : MIMXRT1062.h
- PGC_CPU_CTRL_PCR_MASK : MIMXRT1062.h
- PGC_CPU_CTRL_PCR_SHIFT : MIMXRT1062.h
- PGC_CPU_PDNSCR_ISO : MIMXRT1062.h
- PGC_CPU_PDNSCR_ISO2SW : MIMXRT1062.h
- PGC_CPU_PDNSCR_ISO2SW_MASK : MIMXRT1062.h
- PGC_CPU_PDNSCR_ISO2SW_SHIFT : MIMXRT1062.h
- PGC_CPU_PDNSCR_ISO_MASK : MIMXRT1062.h
- PGC_CPU_PDNSCR_ISO_SHIFT : MIMXRT1062.h
- PGC_CPU_PUPSCR_SW : MIMXRT1062.h
- PGC_CPU_PUPSCR_SW2ISO : MIMXRT1062.h
- PGC_CPU_PUPSCR_SW2ISO_MASK : MIMXRT1062.h
- PGC_CPU_PUPSCR_SW2ISO_SHIFT : MIMXRT1062.h
- PGC_CPU_PUPSCR_SW_MASK : MIMXRT1062.h
- PGC_CPU_PUPSCR_SW_SHIFT : MIMXRT1062.h
- PGC_CPU_SR_PSR : MIMXRT1062.h
- PGC_CPU_SR_PSR_MASK : MIMXRT1062.h
- PGC_CPU_SR_PSR_SHIFT : MIMXRT1062.h
- PGC_MEGA_CTRL_PCR : MIMXRT1062.h
- PGC_MEGA_CTRL_PCR_MASK : MIMXRT1062.h
- PGC_MEGA_CTRL_PCR_SHIFT : MIMXRT1062.h
- PGC_MEGA_PDNSCR_ISO : MIMXRT1062.h
- PGC_MEGA_PDNSCR_ISO2SW : MIMXRT1062.h
- PGC_MEGA_PDNSCR_ISO2SW_MASK : MIMXRT1062.h
- PGC_MEGA_PDNSCR_ISO2SW_SHIFT : MIMXRT1062.h
- PGC_MEGA_PDNSCR_ISO_MASK : MIMXRT1062.h
- PGC_MEGA_PDNSCR_ISO_SHIFT : MIMXRT1062.h
- PGC_MEGA_PUPSCR_SW : MIMXRT1062.h
- PGC_MEGA_PUPSCR_SW2ISO : MIMXRT1062.h
- PGC_MEGA_PUPSCR_SW2ISO_MASK : MIMXRT1062.h
- PGC_MEGA_PUPSCR_SW2ISO_SHIFT : MIMXRT1062.h
- PGC_MEGA_PUPSCR_SW_MASK : MIMXRT1062.h
- PGC_MEGA_PUPSCR_SW_SHIFT : MIMXRT1062.h
- PGC_MEGA_SR_PSR : MIMXRT1062.h
- PGC_MEGA_SR_PSR_MASK : MIMXRT1062.h
- PGC_MEGA_SR_PSR_SHIFT : MIMXRT1062.h
- PI : arm_math.h
- PIT : MIMXRT1062.h
- PIT_BASE : MIMXRT1062.h
- PIT_BASE_ADDRS : MIMXRT1062.h
- PIT_BASE_PTRS : MIMXRT1062.h
- PIT_CVAL_COUNT : MIMXRT1062.h
- PIT_CVAL_TVL : MIMXRT1062.h
- PIT_CVAL_TVL_MASK : MIMXRT1062.h
- PIT_CVAL_TVL_SHIFT : MIMXRT1062.h
- PIT_IRQS : MIMXRT1062.h
- PIT_LDVAL_COUNT : MIMXRT1062.h
- PIT_LDVAL_TSV : MIMXRT1062.h
- PIT_LDVAL_TSV_MASK : MIMXRT1062.h
- PIT_LDVAL_TSV_SHIFT : MIMXRT1062.h
- PIT_LTMR64H_LTH : MIMXRT1062.h
- PIT_LTMR64H_LTH_MASK : MIMXRT1062.h
- PIT_LTMR64H_LTH_SHIFT : MIMXRT1062.h
- PIT_LTMR64L_LTL : MIMXRT1062.h
- PIT_LTMR64L_LTL_MASK : MIMXRT1062.h
- PIT_LTMR64L_LTL_SHIFT : MIMXRT1062.h
- PIT_MCR_FRZ : MIMXRT1062.h
- PIT_MCR_FRZ_MASK : MIMXRT1062.h
- PIT_MCR_FRZ_SHIFT : MIMXRT1062.h
- PIT_MCR_MDIS : MIMXRT1062.h
- PIT_MCR_MDIS_MASK : MIMXRT1062.h
- PIT_MCR_MDIS_SHIFT : MIMXRT1062.h
- PIT_TCTRL_CHN : MIMXRT1062.h
- PIT_TCTRL_CHN_MASK : MIMXRT1062.h
- PIT_TCTRL_CHN_SHIFT : MIMXRT1062.h
- PIT_TCTRL_COUNT : MIMXRT1062.h
- PIT_TCTRL_TEN : MIMXRT1062.h
- PIT_TCTRL_TEN_MASK : MIMXRT1062.h
- PIT_TCTRL_TEN_SHIFT : MIMXRT1062.h
- PIT_TCTRL_TIE : MIMXRT1062.h
- PIT_TCTRL_TIE_MASK : MIMXRT1062.h
- PIT_TCTRL_TIE_SHIFT : MIMXRT1062.h
- PIT_TFLG_COUNT : MIMXRT1062.h
- PIT_TFLG_TIF : MIMXRT1062.h
- PIT_TFLG_TIF_MASK : MIMXRT1062.h
- PIT_TFLG_TIF_SHIFT : MIMXRT1062.h
- PMU : MIMXRT1062.h
- PMU_BASE : MIMXRT1062.h
- PMU_BASE_ADDRS : MIMXRT1062.h
- PMU_BASE_PTRS : MIMXRT1062.h
- PMU_MISC0_CLKGATE_CTRL : MIMXRT1062.h
- PMU_MISC0_CLKGATE_CTRL_MASK : MIMXRT1062.h
- PMU_MISC0_CLKGATE_CTRL_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLKGATE_DELAY : MIMXRT1062.h
- PMU_MISC0_CLKGATE_DELAY_MASK : MIMXRT1062.h
- PMU_MISC0_CLKGATE_DELAY_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_CLKGATE_CTRL : MIMXRT1062.h
- PMU_MISC0_CLR_CLKGATE_CTRL_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_CLKGATE_DELAY : MIMXRT1062.h
- PMU_MISC0_CLR_CLKGATE_DELAY_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_DISCON_HIGH_SNVS : MIMXRT1062.h
- PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_I : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_I_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_I_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_XTALOK : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_XTALOK_EN : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_XTALOK_EN_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_XTALOK_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_OSC_XTALOK_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_PWD : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_PWD_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_PWD_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_SELFBIASOFF : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_VBGADJ : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_VBGADJ_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_VBGUP : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_VBGUP_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_RTC_XTAL_SOURCE : MIMXRT1062.h
- PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_STOP_MODE_CONFIG : MIMXRT1062.h
- PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_VID_PLL_PREDIV : MIMXRT1062.h
- PMU_MISC0_CLR_VID_PLL_PREDIV_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT : MIMXRT1062.h
- PMU_MISC0_CLR_XTAL_24M_PWD : MIMXRT1062.h
- PMU_MISC0_CLR_XTAL_24M_PWD_MASK : MIMXRT1062.h
- PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT : MIMXRT1062.h
- PMU_MISC0_DISCON_HIGH_SNVS : MIMXRT1062.h
- PMU_MISC0_DISCON_HIGH_SNVS_MASK : MIMXRT1062.h
- PMU_MISC0_DISCON_HIGH_SNVS_SHIFT : MIMXRT1062.h
- PMU_MISC0_OSC_I : MIMXRT1062.h
- PMU_MISC0_OSC_I_MASK : MIMXRT1062.h
- PMU_MISC0_OSC_I_SHIFT : MIMXRT1062.h
- PMU_MISC0_OSC_XTALOK : MIMXRT1062.h
- PMU_MISC0_OSC_XTALOK_EN : MIMXRT1062.h
- PMU_MISC0_OSC_XTALOK_EN_MASK : MIMXRT1062.h
- PMU_MISC0_OSC_XTALOK_EN_SHIFT : MIMXRT1062.h
- PMU_MISC0_OSC_XTALOK_MASK : MIMXRT1062.h
- PMU_MISC0_OSC_XTALOK_SHIFT : MIMXRT1062.h
- PMU_MISC0_REFTOP_PWD : MIMXRT1062.h
- PMU_MISC0_REFTOP_PWD_MASK : MIMXRT1062.h
- PMU_MISC0_REFTOP_PWD_SHIFT : MIMXRT1062.h
- PMU_MISC0_REFTOP_SELFBIASOFF : MIMXRT1062.h
- PMU_MISC0_REFTOP_SELFBIASOFF_MASK : MIMXRT1062.h
- PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT : MIMXRT1062.h
- PMU_MISC0_REFTOP_VBGADJ : MIMXRT1062.h
- PMU_MISC0_REFTOP_VBGADJ_MASK : MIMXRT1062.h
- PMU_MISC0_REFTOP_VBGADJ_SHIFT : MIMXRT1062.h
- PMU_MISC0_REFTOP_VBGUP : MIMXRT1062.h
- PMU_MISC0_REFTOP_VBGUP_MASK : MIMXRT1062.h
- PMU_MISC0_REFTOP_VBGUP_SHIFT : MIMXRT1062.h
- PMU_MISC0_RTC_XTAL_SOURCE : MIMXRT1062.h
- PMU_MISC0_RTC_XTAL_SOURCE_MASK : MIMXRT1062.h
- PMU_MISC0_RTC_XTAL_SOURCE_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_CLKGATE_CTRL : MIMXRT1062.h
- PMU_MISC0_SET_CLKGATE_CTRL_MASK : MIMXRT1062.h
- PMU_MISC0_SET_CLKGATE_CTRL_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_CLKGATE_DELAY : MIMXRT1062.h
- PMU_MISC0_SET_CLKGATE_DELAY_MASK : MIMXRT1062.h
- PMU_MISC0_SET_CLKGATE_DELAY_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_DISCON_HIGH_SNVS : MIMXRT1062.h
- PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK : MIMXRT1062.h
- PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_OSC_I : MIMXRT1062.h
- PMU_MISC0_SET_OSC_I_MASK : MIMXRT1062.h
- PMU_MISC0_SET_OSC_I_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_OSC_XTALOK : MIMXRT1062.h
- PMU_MISC0_SET_OSC_XTALOK_EN : MIMXRT1062.h
- PMU_MISC0_SET_OSC_XTALOK_EN_MASK : MIMXRT1062.h
- PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_OSC_XTALOK_MASK : MIMXRT1062.h
- PMU_MISC0_SET_OSC_XTALOK_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_PWD : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_PWD_MASK : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_PWD_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_SELFBIASOFF : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_VBGADJ : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_VBGADJ_MASK : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_VBGUP : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_VBGUP_MASK : MIMXRT1062.h
- PMU_MISC0_SET_REFTOP_VBGUP_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_RTC_XTAL_SOURCE : MIMXRT1062.h
- PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK : MIMXRT1062.h
- PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_STOP_MODE_CONFIG : MIMXRT1062.h
- PMU_MISC0_SET_STOP_MODE_CONFIG_MASK : MIMXRT1062.h
- PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_VID_PLL_PREDIV : MIMXRT1062.h
- PMU_MISC0_SET_VID_PLL_PREDIV_MASK : MIMXRT1062.h
- PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT : MIMXRT1062.h
- PMU_MISC0_SET_XTAL_24M_PWD : MIMXRT1062.h
- PMU_MISC0_SET_XTAL_24M_PWD_MASK : MIMXRT1062.h
- PMU_MISC0_SET_XTAL_24M_PWD_SHIFT : MIMXRT1062.h
- PMU_MISC0_STOP_MODE_CONFIG : MIMXRT1062.h
- PMU_MISC0_STOP_MODE_CONFIG_MASK : MIMXRT1062.h
- PMU_MISC0_STOP_MODE_CONFIG_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_CLKGATE_CTRL : MIMXRT1062.h
- PMU_MISC0_TOG_CLKGATE_CTRL_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_CLKGATE_DELAY : MIMXRT1062.h
- PMU_MISC0_TOG_CLKGATE_DELAY_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_DISCON_HIGH_SNVS : MIMXRT1062.h
- PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_I : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_I_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_I_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_XTALOK : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_XTALOK_EN : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_XTALOK_EN_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_XTALOK_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_OSC_XTALOK_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_PWD : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_PWD_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_PWD_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_SELFBIASOFF : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_VBGADJ : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_VBGADJ_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_VBGUP : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_VBGUP_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_RTC_XTAL_SOURCE : MIMXRT1062.h
- PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_STOP_MODE_CONFIG : MIMXRT1062.h
- PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_VID_PLL_PREDIV : MIMXRT1062.h
- PMU_MISC0_TOG_VID_PLL_PREDIV_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT : MIMXRT1062.h
- PMU_MISC0_TOG_XTAL_24M_PWD : MIMXRT1062.h
- PMU_MISC0_TOG_XTAL_24M_PWD_MASK : MIMXRT1062.h
- PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT : MIMXRT1062.h
- PMU_MISC0_VID_PLL_PREDIV : MIMXRT1062.h
- PMU_MISC0_VID_PLL_PREDIV_MASK : MIMXRT1062.h
- PMU_MISC0_VID_PLL_PREDIV_SHIFT : MIMXRT1062.h
- PMU_MISC0_XTAL_24M_PWD : MIMXRT1062.h
- PMU_MISC0_XTAL_24M_PWD_MASK : MIMXRT1062.h
- PMU_MISC0_XTAL_24M_PWD_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_ANA_BO : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_ANA_BO_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_DIG_BO : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_DIG_BO_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPHIGH : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPLOW : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPLOW_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPPANIC : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_LVDS1_CLK_SEL : MIMXRT1062.h
- PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_LVDS2_CLK_SEL : MIMXRT1062.h
- PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK1_IBEN : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK1_OBEN : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK2_IBEN : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK2_OBEN : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_PFD_480_AUTOGATE_EN : MIMXRT1062.h
- PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT : MIMXRT1062.h
- PMU_MISC1_CLR_PFD_528_AUTOGATE_EN : MIMXRT1062.h
- PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK : MIMXRT1062.h
- PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT : MIMXRT1062.h
- PMU_MISC1_IRQ_ANA_BO : MIMXRT1062.h
- PMU_MISC1_IRQ_ANA_BO_MASK : MIMXRT1062.h
- PMU_MISC1_IRQ_ANA_BO_SHIFT : MIMXRT1062.h
- PMU_MISC1_IRQ_DIG_BO : MIMXRT1062.h
- PMU_MISC1_IRQ_DIG_BO_MASK : MIMXRT1062.h
- PMU_MISC1_IRQ_DIG_BO_SHIFT : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPHIGH : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPHIGH_MASK : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPHIGH_SHIFT : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPLOW : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPLOW_MASK : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPLOW_SHIFT : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPPANIC : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPPANIC_MASK : MIMXRT1062.h
- PMU_MISC1_IRQ_TEMPPANIC_SHIFT : MIMXRT1062.h
- PMU_MISC1_LVDS1_CLK_SEL : MIMXRT1062.h
- PMU_MISC1_LVDS1_CLK_SEL_MASK : MIMXRT1062.h
- PMU_MISC1_LVDS1_CLK_SEL_SHIFT : MIMXRT1062.h
- PMU_MISC1_LVDS2_CLK_SEL : MIMXRT1062.h
- PMU_MISC1_LVDS2_CLK_SEL_MASK : MIMXRT1062.h
- PMU_MISC1_LVDS2_CLK_SEL_SHIFT : MIMXRT1062.h
- PMU_MISC1_LVDSCLK1_IBEN : MIMXRT1062.h
- PMU_MISC1_LVDSCLK1_IBEN_MASK : MIMXRT1062.h
- PMU_MISC1_LVDSCLK1_IBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_LVDSCLK1_OBEN : MIMXRT1062.h
- PMU_MISC1_LVDSCLK1_OBEN_MASK : MIMXRT1062.h
- PMU_MISC1_LVDSCLK1_OBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_LVDSCLK2_IBEN : MIMXRT1062.h
- PMU_MISC1_LVDSCLK2_IBEN_MASK : MIMXRT1062.h
- PMU_MISC1_LVDSCLK2_IBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_LVDSCLK2_OBEN : MIMXRT1062.h
- PMU_MISC1_LVDSCLK2_OBEN_MASK : MIMXRT1062.h
- PMU_MISC1_LVDSCLK2_OBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_PFD_480_AUTOGATE_EN : MIMXRT1062.h
- PMU_MISC1_PFD_480_AUTOGATE_EN_MASK : MIMXRT1062.h
- PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT : MIMXRT1062.h
- PMU_MISC1_PFD_528_AUTOGATE_EN : MIMXRT1062.h
- PMU_MISC1_PFD_528_AUTOGATE_EN_MASK : MIMXRT1062.h
- PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_ANA_BO : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_ANA_BO_MASK : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_ANA_BO_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_DIG_BO : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_DIG_BO_MASK : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_DIG_BO_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPHIGH : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPHIGH_MASK : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPLOW : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPLOW_MASK : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPPANIC : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPPANIC_MASK : MIMXRT1062.h
- PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_LVDS1_CLK_SEL : MIMXRT1062.h
- PMU_MISC1_SET_LVDS1_CLK_SEL_MASK : MIMXRT1062.h
- PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_LVDS2_CLK_SEL : MIMXRT1062.h
- PMU_MISC1_SET_LVDS2_CLK_SEL_MASK : MIMXRT1062.h
- PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK1_IBEN : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK1_IBEN_MASK : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK1_OBEN : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK1_OBEN_MASK : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK2_IBEN : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK2_IBEN_MASK : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK2_OBEN : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK2_OBEN_MASK : MIMXRT1062.h
- PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_PFD_480_AUTOGATE_EN : MIMXRT1062.h
- PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK : MIMXRT1062.h
- PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT : MIMXRT1062.h
- PMU_MISC1_SET_PFD_528_AUTOGATE_EN : MIMXRT1062.h
- PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK : MIMXRT1062.h
- PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_ANA_BO : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_ANA_BO_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_DIG_BO : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_DIG_BO_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPHIGH : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPLOW : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPLOW_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPPANIC : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_LVDS1_CLK_SEL : MIMXRT1062.h
- PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_LVDS2_CLK_SEL : MIMXRT1062.h
- PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK1_IBEN : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK1_OBEN : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK2_IBEN : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK2_OBEN : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_PFD_480_AUTOGATE_EN : MIMXRT1062.h
- PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT : MIMXRT1062.h
- PMU_MISC1_TOG_PFD_528_AUTOGATE_EN : MIMXRT1062.h
- PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK : MIMXRT1062.h
- PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT : MIMXRT1062.h
- PMU_MISC2_AUDIO_DIV_LSB : MIMXRT1062.h
- PMU_MISC2_AUDIO_DIV_LSB_MASK : MIMXRT1062.h
- PMU_MISC2_AUDIO_DIV_LSB_SHIFT : MIMXRT1062.h
- PMU_MISC2_AUDIO_DIV_MSB : MIMXRT1062.h
- PMU_MISC2_AUDIO_DIV_MSB_MASK : MIMXRT1062.h
- PMU_MISC2_AUDIO_DIV_MSB_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_AUDIO_DIV_LSB : MIMXRT1062.h
- PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_AUDIO_DIV_MSB : MIMXRT1062.h
- PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_PLL3_disable : MIMXRT1062.h
- PMU_MISC2_CLR_PLL3_disable_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_PLL3_disable_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_OK : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_OK_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_OK_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_CLR_VIDEO_DIV : MIMXRT1062.h
- PMU_MISC2_CLR_VIDEO_DIV_MASK : MIMXRT1062.h
- PMU_MISC2_CLR_VIDEO_DIV_SHIFT : MIMXRT1062.h
- PMU_MISC2_PLL3_disable : MIMXRT1062.h
- PMU_MISC2_PLL3_disable_MASK : MIMXRT1062.h
- PMU_MISC2_PLL3_disable_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG0_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_REG0_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_REG0_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG0_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_REG0_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_REG0_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG0_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_REG0_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_REG0_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG0_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_REG0_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_REG0_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG1_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_REG1_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_REG1_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG1_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_REG1_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_REG1_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG1_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_REG1_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_REG1_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG1_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_REG1_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_REG1_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG2_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_REG2_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_REG2_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG2_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_REG2_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_REG2_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG2_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_REG2_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_REG2_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG2_OK : MIMXRT1062.h
- PMU_MISC2_REG2_OK_MASK : MIMXRT1062.h
- PMU_MISC2_REG2_OK_SHIFT : MIMXRT1062.h
- PMU_MISC2_REG2_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_REG2_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_REG2_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_AUDIO_DIV_LSB : MIMXRT1062.h
- PMU_MISC2_SET_AUDIO_DIV_LSB_MASK : MIMXRT1062.h
- PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_AUDIO_DIV_MSB : MIMXRT1062.h
- PMU_MISC2_SET_AUDIO_DIV_MSB_MASK : MIMXRT1062.h
- PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_PLL3_disable : MIMXRT1062.h
- PMU_MISC2_SET_PLL3_disable_MASK : MIMXRT1062.h
- PMU_MISC2_SET_PLL3_disable_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG0_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_SET_REG0_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG0_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_SET_REG0_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG0_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG0_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_SET_REG0_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG0_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_SET_REG0_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG0_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG1_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_SET_REG1_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG1_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_SET_REG1_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG1_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG1_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_SET_REG1_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG1_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_SET_REG1_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG1_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG2_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_SET_REG2_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG2_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_SET_REG2_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG2_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG2_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_SET_REG2_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG2_OK : MIMXRT1062.h
- PMU_MISC2_SET_REG2_OK_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG2_OK_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_REG2_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_SET_REG2_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_SET_REG2_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_SET_VIDEO_DIV : MIMXRT1062.h
- PMU_MISC2_SET_VIDEO_DIV_MASK : MIMXRT1062.h
- PMU_MISC2_SET_VIDEO_DIV_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_AUDIO_DIV_LSB : MIMXRT1062.h
- PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_AUDIO_DIV_MSB : MIMXRT1062.h
- PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_PLL3_disable : MIMXRT1062.h
- PMU_MISC2_TOG_PLL3_disable_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_PLL3_disable_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_BO_OFFSET : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_BO_STATUS : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_BO_STATUS_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_ENABLE_BO : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_OK : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_OK_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_OK_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_STEP_TIME : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_STEP_TIME_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT : MIMXRT1062.h
- PMU_MISC2_TOG_VIDEO_DIV : MIMXRT1062.h
- PMU_MISC2_TOG_VIDEO_DIV_MASK : MIMXRT1062.h
- PMU_MISC2_TOG_VIDEO_DIV_SHIFT : MIMXRT1062.h
- PMU_MISC2_VIDEO_DIV : MIMXRT1062.h
- PMU_MISC2_VIDEO_DIV_MASK : MIMXRT1062.h
- PMU_MISC2_VIDEO_DIV_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_BO_OFFSET : MIMXRT1062.h
- PMU_REG_1P1_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_1P1_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_BO_VDD1P1 : MIMXRT1062.h
- PMU_REG_1P1_BO_VDD1P1_MASK : MIMXRT1062.h
- PMU_REG_1P1_BO_VDD1P1_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_BO_OFFSET : MIMXRT1062.h
- PMU_REG_1P1_CLR_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_BO_VDD1P1 : MIMXRT1062.h
- PMU_REG_1P1_CLR_BO_VDD1P1_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_BO : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_PULLDOWN : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_OK_VDD1P1 : MIMXRT1062.h
- PMU_REG_1P1_CLR_OK_VDD1P1_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_1P1_CLR_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_CLR_SELREF_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_BO : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_PULLDOWN : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_PULLDOWN_MASK : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_OK_VDD1P1 : MIMXRT1062.h
- PMU_REG_1P1_OK_VDD1P1_MASK : MIMXRT1062.h
- PMU_REG_1P1_OK_VDD1P1_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_1P1_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_1P1_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SELREF_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_1P1_SELREF_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_BO_OFFSET : MIMXRT1062.h
- PMU_REG_1P1_SET_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_BO_VDD1P1 : MIMXRT1062.h
- PMU_REG_1P1_SET_BO_VDD1P1_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_BO_VDD1P1_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_BO : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_PULLDOWN : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_OK_VDD1P1 : MIMXRT1062.h
- PMU_REG_1P1_SET_OK_VDD1P1_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_OK_VDD1P1_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_1P1_SET_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_SET_SELREF_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_BO_OFFSET : MIMXRT1062.h
- PMU_REG_1P1_TOG_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_BO_VDD1P1 : MIMXRT1062.h
- PMU_REG_1P1_TOG_BO_VDD1P1_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_BO : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_PULLDOWN : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_OK_VDD1P1 : MIMXRT1062.h
- PMU_REG_1P1_TOG_OK_VDD1P1_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_1P1_TOG_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_1P1_TOG_SELREF_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_BO_OFFSET : MIMXRT1062.h
- PMU_REG_2P5_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_2P5_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_BO_VDD2P5 : MIMXRT1062.h
- PMU_REG_2P5_BO_VDD2P5_MASK : MIMXRT1062.h
- PMU_REG_2P5_BO_VDD2P5_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_BO_OFFSET : MIMXRT1062.h
- PMU_REG_2P5_CLR_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_BO_VDD2P5 : MIMXRT1062.h
- PMU_REG_2P5_CLR_BO_VDD2P5_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_BO : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_PULLDOWN : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_OK_VDD2P5 : MIMXRT1062.h
- PMU_REG_2P5_CLR_OK_VDD2P5_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_CLR_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_2P5_CLR_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_BO : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_PULLDOWN : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_PULLDOWN_MASK : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_OK_VDD2P5 : MIMXRT1062.h
- PMU_REG_2P5_OK_VDD2P5_MASK : MIMXRT1062.h
- PMU_REG_2P5_OK_VDD2P5_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_2P5_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_2P5_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_BO_OFFSET : MIMXRT1062.h
- PMU_REG_2P5_SET_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_BO_VDD2P5 : MIMXRT1062.h
- PMU_REG_2P5_SET_BO_VDD2P5_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_BO_VDD2P5_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_BO : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_PULLDOWN : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_OK_VDD2P5 : MIMXRT1062.h
- PMU_REG_2P5_SET_OK_VDD2P5_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_OK_VDD2P5_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_SET_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_2P5_SET_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_BO_OFFSET : MIMXRT1062.h
- PMU_REG_2P5_TOG_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_BO_VDD2P5 : MIMXRT1062.h
- PMU_REG_2P5_TOG_BO_VDD2P5_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_BO : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_PULLDOWN : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_OK_VDD2P5 : MIMXRT1062.h
- PMU_REG_2P5_TOG_OK_VDD2P5_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT : MIMXRT1062.h
- PMU_REG_2P5_TOG_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_2P5_TOG_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_BO_OFFSET : MIMXRT1062.h
- PMU_REG_3P0_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_3P0_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_BO_VDD3P0 : MIMXRT1062.h
- PMU_REG_3P0_BO_VDD3P0_MASK : MIMXRT1062.h
- PMU_REG_3P0_BO_VDD3P0_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_CLR_BO_OFFSET : MIMXRT1062.h
- PMU_REG_3P0_CLR_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_3P0_CLR_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_CLR_BO_VDD3P0 : MIMXRT1062.h
- PMU_REG_3P0_CLR_BO_VDD3P0_MASK : MIMXRT1062.h
- PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_BO : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_CLR_OK_VDD3P0 : MIMXRT1062.h
- PMU_REG_3P0_CLR_OK_VDD3P0_MASK : MIMXRT1062.h
- PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_CLR_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_3P0_CLR_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_CLR_VBUS_SEL : MIMXRT1062.h
- PMU_REG_3P0_CLR_VBUS_SEL_MASK : MIMXRT1062.h
- PMU_REG_3P0_CLR_VBUS_SEL_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_BO : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_3P0_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_OK_VDD3P0 : MIMXRT1062.h
- PMU_REG_3P0_OK_VDD3P0_MASK : MIMXRT1062.h
- PMU_REG_3P0_OK_VDD3P0_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_3P0_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_3P0_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_SET_BO_OFFSET : MIMXRT1062.h
- PMU_REG_3P0_SET_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_3P0_SET_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_SET_BO_VDD3P0 : MIMXRT1062.h
- PMU_REG_3P0_SET_BO_VDD3P0_MASK : MIMXRT1062.h
- PMU_REG_3P0_SET_BO_VDD3P0_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_BO : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_SET_OK_VDD3P0 : MIMXRT1062.h
- PMU_REG_3P0_SET_OK_VDD3P0_MASK : MIMXRT1062.h
- PMU_REG_3P0_SET_OK_VDD3P0_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_SET_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_3P0_SET_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_SET_VBUS_SEL : MIMXRT1062.h
- PMU_REG_3P0_SET_VBUS_SEL_MASK : MIMXRT1062.h
- PMU_REG_3P0_SET_VBUS_SEL_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_TOG_BO_OFFSET : MIMXRT1062.h
- PMU_REG_3P0_TOG_BO_OFFSET_MASK : MIMXRT1062.h
- PMU_REG_3P0_TOG_BO_OFFSET_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_TOG_BO_VDD3P0 : MIMXRT1062.h
- PMU_REG_3P0_TOG_BO_VDD3P0_MASK : MIMXRT1062.h
- PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_BO : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_BO_MASK : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_BO_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_ILIMIT : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_LINREG : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_LINREG_MASK : MIMXRT1062.h
- PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_TOG_OK_VDD3P0 : MIMXRT1062.h
- PMU_REG_3P0_TOG_OK_VDD3P0_MASK : MIMXRT1062.h
- PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_TOG_OUTPUT_TRG : MIMXRT1062.h
- PMU_REG_3P0_TOG_OUTPUT_TRG_MASK : MIMXRT1062.h
- PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_TOG_VBUS_SEL : MIMXRT1062.h
- PMU_REG_3P0_TOG_VBUS_SEL_MASK : MIMXRT1062.h
- PMU_REG_3P0_TOG_VBUS_SEL_SHIFT : MIMXRT1062.h
- PMU_REG_3P0_VBUS_SEL : MIMXRT1062.h
- PMU_REG_3P0_VBUS_SEL_MASK : MIMXRT1062.h
- PMU_REG_3P0_VBUS_SEL_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_CLR_FET_ODRIVE : MIMXRT1062.h
- PMU_REG_CORE_CLR_FET_ODRIVE_MASK : MIMXRT1062.h
- PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_CLR_RAMP_RATE : MIMXRT1062.h
- PMU_REG_CORE_CLR_RAMP_RATE_MASK : MIMXRT1062.h
- PMU_REG_CORE_CLR_RAMP_RATE_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG0_ADJ : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG0_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG0_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG0_TARG : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG0_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG0_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG1_ADJ : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG1_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG1_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG1_TARG : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG1_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG1_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG2_ADJ : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG2_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG2_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG2_TARG : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG2_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_CLR_REG2_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_FET_ODRIVE : MIMXRT1062.h
- PMU_REG_CORE_FET_ODRIVE_MASK : MIMXRT1062.h
- PMU_REG_CORE_FET_ODRIVE_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_RAMP_RATE : MIMXRT1062.h
- PMU_REG_CORE_RAMP_RATE_MASK : MIMXRT1062.h
- PMU_REG_CORE_RAMP_RATE_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_REG0_ADJ : MIMXRT1062.h
- PMU_REG_CORE_REG0_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_REG0_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_REG0_TARG : MIMXRT1062.h
- PMU_REG_CORE_REG0_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_REG0_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_REG1_ADJ : MIMXRT1062.h
- PMU_REG_CORE_REG1_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_REG1_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_REG1_TARG : MIMXRT1062.h
- PMU_REG_CORE_REG1_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_REG1_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_REG2_ADJ : MIMXRT1062.h
- PMU_REG_CORE_REG2_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_REG2_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_REG2_TARG : MIMXRT1062.h
- PMU_REG_CORE_REG2_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_REG2_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_SET_FET_ODRIVE : MIMXRT1062.h
- PMU_REG_CORE_SET_FET_ODRIVE_MASK : MIMXRT1062.h
- PMU_REG_CORE_SET_FET_ODRIVE_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_SET_RAMP_RATE : MIMXRT1062.h
- PMU_REG_CORE_SET_RAMP_RATE_MASK : MIMXRT1062.h
- PMU_REG_CORE_SET_RAMP_RATE_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_SET_REG0_ADJ : MIMXRT1062.h
- PMU_REG_CORE_SET_REG0_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_SET_REG0_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_SET_REG0_TARG : MIMXRT1062.h
- PMU_REG_CORE_SET_REG0_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_SET_REG0_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_SET_REG1_ADJ : MIMXRT1062.h
- PMU_REG_CORE_SET_REG1_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_SET_REG1_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_SET_REG1_TARG : MIMXRT1062.h
- PMU_REG_CORE_SET_REG1_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_SET_REG1_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_SET_REG2_ADJ : MIMXRT1062.h
- PMU_REG_CORE_SET_REG2_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_SET_REG2_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_SET_REG2_TARG : MIMXRT1062.h
- PMU_REG_CORE_SET_REG2_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_SET_REG2_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_TOG_FET_ODRIVE : MIMXRT1062.h
- PMU_REG_CORE_TOG_FET_ODRIVE_MASK : MIMXRT1062.h
- PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_TOG_RAMP_RATE : MIMXRT1062.h
- PMU_REG_CORE_TOG_RAMP_RATE_MASK : MIMXRT1062.h
- PMU_REG_CORE_TOG_RAMP_RATE_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG0_ADJ : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG0_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG0_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG0_TARG : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG0_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG0_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG1_ADJ : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG1_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG1_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG1_TARG : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG1_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG1_TARG_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG2_ADJ : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG2_ADJ_MASK : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG2_ADJ_SHIFT : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG2_TARG : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG2_TARG_MASK : MIMXRT1062.h
- PMU_REG_CORE_TOG_REG2_TARG_SHIFT : MIMXRT1062.h
- PRINT_BIT : c4_watchdog.c
- PRINTF : c4_privilege_modes.c
- PTP_APP_MASTER_TEST : bootloader.c
- PWM1 : MIMXRT1062.h
- PWM1_BASE : MIMXRT1062.h
- PWM2 : MIMXRT1062.h
- PWM2_BASE : MIMXRT1062.h
- PWM3 : MIMXRT1062.h
- PWM3_BASE : MIMXRT1062.h
- PWM4 : MIMXRT1062.h
- PWM4_BASE : MIMXRT1062.h
- PWM_BASE_ADDRS : MIMXRT1062.h
- PWM_BASE_PTRS : MIMXRT1062.h
- PWM_CAPTCOMPA_COUNT : MIMXRT1062.h
- PWM_CAPTCOMPA_EDGCMPA : MIMXRT1062.h
- PWM_CAPTCOMPA_EDGCMPA_MASK : MIMXRT1062.h
- PWM_CAPTCOMPA_EDGCMPA_SHIFT : MIMXRT1062.h
- PWM_CAPTCOMPA_EDGCNTA : MIMXRT1062.h
- PWM_CAPTCOMPA_EDGCNTA_MASK : MIMXRT1062.h
- PWM_CAPTCOMPA_EDGCNTA_SHIFT : MIMXRT1062.h
- PWM_CAPTCOMPB_COUNT : MIMXRT1062.h
- PWM_CAPTCOMPB_EDGCMPB : MIMXRT1062.h
- PWM_CAPTCOMPB_EDGCMPB_MASK : MIMXRT1062.h
- PWM_CAPTCOMPB_EDGCMPB_SHIFT : MIMXRT1062.h
- PWM_CAPTCOMPB_EDGCNTB : MIMXRT1062.h
- PWM_CAPTCOMPB_EDGCNTB_MASK : MIMXRT1062.h
- PWM_CAPTCOMPB_EDGCNTB_SHIFT : MIMXRT1062.h
- PWM_CAPTCOMPX_COUNT : MIMXRT1062.h
- PWM_CAPTCOMPX_EDGCMPX : MIMXRT1062.h
- PWM_CAPTCOMPX_EDGCMPX_MASK : MIMXRT1062.h
- PWM_CAPTCOMPX_EDGCMPX_SHIFT : MIMXRT1062.h
- PWM_CAPTCOMPX_EDGCNTX : MIMXRT1062.h
- PWM_CAPTCOMPX_EDGCNTX_MASK : MIMXRT1062.h
- PWM_CAPTCOMPX_EDGCNTX_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_ARMA : MIMXRT1062.h
- PWM_CAPTCTRLA_ARMA_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_ARMA_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_CA0CNT : MIMXRT1062.h
- PWM_CAPTCTRLA_CA0CNT_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_CA0CNT_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_CA1CNT : MIMXRT1062.h
- PWM_CAPTCTRLA_CA1CNT_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_CA1CNT_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_CFAWM : MIMXRT1062.h
- PWM_CAPTCTRLA_CFAWM_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_CFAWM_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_COUNT : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGA0 : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGA0_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGA0_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGA1 : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGA1_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGA1_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGCNTA_EN : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGCNTA_EN_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_INP_SELA : MIMXRT1062.h
- PWM_CAPTCTRLA_INP_SELA_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_INP_SELA_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLA_ONESHOTA : MIMXRT1062.h
- PWM_CAPTCTRLA_ONESHOTA_MASK : MIMXRT1062.h
- PWM_CAPTCTRLA_ONESHOTA_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_ARMB : MIMXRT1062.h
- PWM_CAPTCTRLB_ARMB_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_ARMB_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_CB0CNT : MIMXRT1062.h
- PWM_CAPTCTRLB_CB0CNT_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_CB0CNT_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_CB1CNT : MIMXRT1062.h
- PWM_CAPTCTRLB_CB1CNT_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_CB1CNT_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_CFBWM : MIMXRT1062.h
- PWM_CAPTCTRLB_CFBWM_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_CFBWM_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_COUNT : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGB0 : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGB0_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGB0_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGB1 : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGB1_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGB1_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGCNTB_EN : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGCNTB_EN_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_INP_SELB : MIMXRT1062.h
- PWM_CAPTCTRLB_INP_SELB_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_INP_SELB_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLB_ONESHOTB : MIMXRT1062.h
- PWM_CAPTCTRLB_ONESHOTB_MASK : MIMXRT1062.h
- PWM_CAPTCTRLB_ONESHOTB_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_ARMX : MIMXRT1062.h
- PWM_CAPTCTRLX_ARMX_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_ARMX_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_CFXWM : MIMXRT1062.h
- PWM_CAPTCTRLX_CFXWM_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_CFXWM_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_COUNT : MIMXRT1062.h
- PWM_CAPTCTRLX_CX0CNT : MIMXRT1062.h
- PWM_CAPTCTRLX_CX0CNT_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_CX0CNT_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_CX1CNT : MIMXRT1062.h
- PWM_CAPTCTRLX_CX1CNT_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_CX1CNT_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGCNTX_EN : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGCNTX_EN_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGX0 : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGX0_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGX0_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGX1 : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGX1_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_EDGX1_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_INP_SELX : MIMXRT1062.h
- PWM_CAPTCTRLX_INP_SELX_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_INP_SELX_SHIFT : MIMXRT1062.h
- PWM_CAPTCTRLX_ONESHOTX : MIMXRT1062.h
- PWM_CAPTCTRLX_ONESHOTX_MASK : MIMXRT1062.h
- PWM_CAPTCTRLX_ONESHOTX_SHIFT : MIMXRT1062.h
- PWM_CAPTURE_IRQS : MIMXRT1062.h
- PWM_CMP_IRQS : MIMXRT1062.h
- PWM_CNT_CNT : MIMXRT1062.h
- PWM_CNT_CNT_MASK : MIMXRT1062.h
- PWM_CNT_CNT_SHIFT : MIMXRT1062.h
- PWM_CNT_COUNT : MIMXRT1062.h
- PWM_CTRL2_CLK_SEL : MIMXRT1062.h
- PWM_CTRL2_CLK_SEL_MASK : MIMXRT1062.h
- PWM_CTRL2_CLK_SEL_SHIFT : MIMXRT1062.h
- PWM_CTRL2_COUNT : MIMXRT1062.h
- PWM_CTRL2_DBGEN : MIMXRT1062.h
- PWM_CTRL2_DBGEN_MASK : MIMXRT1062.h
- PWM_CTRL2_DBGEN_SHIFT : MIMXRT1062.h
- PWM_CTRL2_FORCE : MIMXRT1062.h
- PWM_CTRL2_FORCE_MASK : MIMXRT1062.h
- PWM_CTRL2_FORCE_SEL : MIMXRT1062.h
- PWM_CTRL2_FORCE_SEL_MASK : MIMXRT1062.h
- PWM_CTRL2_FORCE_SEL_SHIFT : MIMXRT1062.h
- PWM_CTRL2_FORCE_SHIFT : MIMXRT1062.h
- PWM_CTRL2_FRCEN : MIMXRT1062.h
- PWM_CTRL2_FRCEN_MASK : MIMXRT1062.h
- PWM_CTRL2_FRCEN_SHIFT : MIMXRT1062.h
- PWM_CTRL2_INDEP : MIMXRT1062.h
- PWM_CTRL2_INDEP_MASK : MIMXRT1062.h
- PWM_CTRL2_INDEP_SHIFT : MIMXRT1062.h
- PWM_CTRL2_INIT_SEL : MIMXRT1062.h
- PWM_CTRL2_INIT_SEL_MASK : MIMXRT1062.h
- PWM_CTRL2_INIT_SEL_SHIFT : MIMXRT1062.h
- PWM_CTRL2_PWM23_INIT : MIMXRT1062.h
- PWM_CTRL2_PWM23_INIT_MASK : MIMXRT1062.h
- PWM_CTRL2_PWM23_INIT_SHIFT : MIMXRT1062.h
- PWM_CTRL2_PWM45_INIT : MIMXRT1062.h
- PWM_CTRL2_PWM45_INIT_MASK : MIMXRT1062.h
- PWM_CTRL2_PWM45_INIT_SHIFT : MIMXRT1062.h
- PWM_CTRL2_PWMX_INIT : MIMXRT1062.h
- PWM_CTRL2_PWMX_INIT_MASK : MIMXRT1062.h
- PWM_CTRL2_PWMX_INIT_SHIFT : MIMXRT1062.h
- PWM_CTRL2_RELOAD_SEL : MIMXRT1062.h
- PWM_CTRL2_RELOAD_SEL_MASK : MIMXRT1062.h
- PWM_CTRL2_RELOAD_SEL_SHIFT : MIMXRT1062.h
- PWM_CTRL2_WAITEN : MIMXRT1062.h
- PWM_CTRL2_WAITEN_MASK : MIMXRT1062.h
- PWM_CTRL2_WAITEN_SHIFT : MIMXRT1062.h
- PWM_CTRL_COMPMODE : MIMXRT1062.h
- PWM_CTRL_COMPMODE_MASK : MIMXRT1062.h
- PWM_CTRL_COMPMODE_SHIFT : MIMXRT1062.h
- PWM_CTRL_COUNT : MIMXRT1062.h
- PWM_CTRL_DBLEN : MIMXRT1062.h
- PWM_CTRL_DBLEN_MASK : MIMXRT1062.h
- PWM_CTRL_DBLEN_SHIFT : MIMXRT1062.h
- PWM_CTRL_DBLX : MIMXRT1062.h
- PWM_CTRL_DBLX_MASK : MIMXRT1062.h
- PWM_CTRL_DBLX_SHIFT : MIMXRT1062.h
- PWM_CTRL_DT : MIMXRT1062.h
- PWM_CTRL_DT_MASK : MIMXRT1062.h
- PWM_CTRL_DT_SHIFT : MIMXRT1062.h
- PWM_CTRL_FULL : MIMXRT1062.h
- PWM_CTRL_FULL_MASK : MIMXRT1062.h
- PWM_CTRL_FULL_SHIFT : MIMXRT1062.h
- PWM_CTRL_HALF : MIMXRT1062.h
- PWM_CTRL_HALF_MASK : MIMXRT1062.h
- PWM_CTRL_HALF_SHIFT : MIMXRT1062.h
- PWM_CTRL_LDFQ : MIMXRT1062.h
- PWM_CTRL_LDFQ_MASK : MIMXRT1062.h
- PWM_CTRL_LDFQ_SHIFT : MIMXRT1062.h
- PWM_CTRL_LDMOD : MIMXRT1062.h
- PWM_CTRL_LDMOD_MASK : MIMXRT1062.h
- PWM_CTRL_LDMOD_SHIFT : MIMXRT1062.h
- PWM_CTRL_PRSC : MIMXRT1062.h
- PWM_CTRL_PRSC_MASK : MIMXRT1062.h
- PWM_CTRL_PRSC_SHIFT : MIMXRT1062.h
- PWM_CTRL_SPLIT : MIMXRT1062.h
- PWM_CTRL_SPLIT_MASK : MIMXRT1062.h
- PWM_CTRL_SPLIT_SHIFT : MIMXRT1062.h
- PWM_CVAL0_CAPTVAL0 : MIMXRT1062.h
- PWM_CVAL0_CAPTVAL0_MASK : MIMXRT1062.h
- PWM_CVAL0_CAPTVAL0_SHIFT : MIMXRT1062.h
- PWM_CVAL0_COUNT : MIMXRT1062.h
- PWM_CVAL0CYC_COUNT : MIMXRT1062.h
- PWM_CVAL0CYC_CVAL0CYC : MIMXRT1062.h
- PWM_CVAL0CYC_CVAL0CYC_MASK : MIMXRT1062.h
- PWM_CVAL0CYC_CVAL0CYC_SHIFT : MIMXRT1062.h
- PWM_CVAL1_CAPTVAL1 : MIMXRT1062.h
- PWM_CVAL1_CAPTVAL1_MASK : MIMXRT1062.h
- PWM_CVAL1_CAPTVAL1_SHIFT : MIMXRT1062.h
- PWM_CVAL1_COUNT : MIMXRT1062.h
- PWM_CVAL1CYC_COUNT : MIMXRT1062.h
- PWM_CVAL1CYC_CVAL1CYC : MIMXRT1062.h
- PWM_CVAL1CYC_CVAL1CYC_MASK : MIMXRT1062.h
- PWM_CVAL1CYC_CVAL1CYC_SHIFT : MIMXRT1062.h
- PWM_CVAL2_CAPTVAL2 : MIMXRT1062.h
- PWM_CVAL2_CAPTVAL2_MASK : MIMXRT1062.h
- PWM_CVAL2_CAPTVAL2_SHIFT : MIMXRT1062.h
- PWM_CVAL2_COUNT : MIMXRT1062.h
- PWM_CVAL2CYC_COUNT : MIMXRT1062.h
- PWM_CVAL2CYC_CVAL2CYC : MIMXRT1062.h
- PWM_CVAL2CYC_CVAL2CYC_MASK : MIMXRT1062.h
- PWM_CVAL2CYC_CVAL2CYC_SHIFT : MIMXRT1062.h
- PWM_CVAL3_CAPTVAL3 : MIMXRT1062.h
- PWM_CVAL3_CAPTVAL3_MASK : MIMXRT1062.h
- PWM_CVAL3_CAPTVAL3_SHIFT : MIMXRT1062.h
- PWM_CVAL3_COUNT : MIMXRT1062.h
- PWM_CVAL3CYC_COUNT : MIMXRT1062.h
- PWM_CVAL3CYC_CVAL3CYC : MIMXRT1062.h
- PWM_CVAL3CYC_CVAL3CYC_MASK : MIMXRT1062.h
- PWM_CVAL3CYC_CVAL3CYC_SHIFT : MIMXRT1062.h
- PWM_CVAL4_CAPTVAL4 : MIMXRT1062.h
- PWM_CVAL4_CAPTVAL4_MASK : MIMXRT1062.h
- PWM_CVAL4_CAPTVAL4_SHIFT : MIMXRT1062.h
- PWM_CVAL4_COUNT : MIMXRT1062.h
- PWM_CVAL4CYC_COUNT : MIMXRT1062.h
- PWM_CVAL4CYC_CVAL4CYC : MIMXRT1062.h
- PWM_CVAL4CYC_CVAL4CYC_MASK : MIMXRT1062.h
- PWM_CVAL4CYC_CVAL4CYC_SHIFT : MIMXRT1062.h
- PWM_CVAL5_CAPTVAL5 : MIMXRT1062.h
- PWM_CVAL5_CAPTVAL5_MASK : MIMXRT1062.h
- PWM_CVAL5_CAPTVAL5_SHIFT : MIMXRT1062.h
- PWM_CVAL5_COUNT : MIMXRT1062.h
- PWM_CVAL5CYC_COUNT : MIMXRT1062.h
- PWM_CVAL5CYC_CVAL5CYC : MIMXRT1062.h
- PWM_CVAL5CYC_CVAL5CYC_MASK : MIMXRT1062.h
- PWM_CVAL5CYC_CVAL5CYC_SHIFT : MIMXRT1062.h
- PWM_DISMAP_COUNT : MIMXRT1062.h
- PWM_DISMAP_COUNT2 : MIMXRT1062.h
- PWM_DISMAP_DIS0A : MIMXRT1062.h
- PWM_DISMAP_DIS0A_MASK : MIMXRT1062.h
- PWM_DISMAP_DIS0A_SHIFT : MIMXRT1062.h
- PWM_DISMAP_DIS0B : MIMXRT1062.h
- PWM_DISMAP_DIS0B_MASK : MIMXRT1062.h
- PWM_DISMAP_DIS0B_SHIFT : MIMXRT1062.h
- PWM_DISMAP_DIS0X : MIMXRT1062.h
- PWM_DISMAP_DIS0X_MASK : MIMXRT1062.h
- PWM_DISMAP_DIS0X_SHIFT : MIMXRT1062.h
- PWM_DISMAP_DIS1A : MIMXRT1062.h
- PWM_DISMAP_DIS1A_MASK : MIMXRT1062.h
- PWM_DISMAP_DIS1A_SHIFT : MIMXRT1062.h
- PWM_DISMAP_DIS1B : MIMXRT1062.h
- PWM_DISMAP_DIS1B_MASK : MIMXRT1062.h
- PWM_DISMAP_DIS1B_SHIFT : MIMXRT1062.h
- PWM_DISMAP_DIS1X : MIMXRT1062.h
- PWM_DISMAP_DIS1X_MASK : MIMXRT1062.h
- PWM_DISMAP_DIS1X_SHIFT : MIMXRT1062.h
- PWM_DMAEN_CA0DE : MIMXRT1062.h
- PWM_DMAEN_CA0DE_MASK : MIMXRT1062.h
- PWM_DMAEN_CA0DE_SHIFT : MIMXRT1062.h
- PWM_DMAEN_CA1DE : MIMXRT1062.h
- PWM_DMAEN_CA1DE_MASK : MIMXRT1062.h
- PWM_DMAEN_CA1DE_SHIFT : MIMXRT1062.h
- PWM_DMAEN_CAPTDE : MIMXRT1062.h
- PWM_DMAEN_CAPTDE_MASK : MIMXRT1062.h
- PWM_DMAEN_CAPTDE_SHIFT : MIMXRT1062.h
- PWM_DMAEN_CB0DE : MIMXRT1062.h
- PWM_DMAEN_CB0DE_MASK : MIMXRT1062.h
- PWM_DMAEN_CB0DE_SHIFT : MIMXRT1062.h
- PWM_DMAEN_CB1DE : MIMXRT1062.h
- PWM_DMAEN_CB1DE_MASK : MIMXRT1062.h
- PWM_DMAEN_CB1DE_SHIFT : MIMXRT1062.h
- PWM_DMAEN_COUNT : MIMXRT1062.h
- PWM_DMAEN_CX0DE : MIMXRT1062.h
- PWM_DMAEN_CX0DE_MASK : MIMXRT1062.h
- PWM_DMAEN_CX0DE_SHIFT : MIMXRT1062.h
- PWM_DMAEN_CX1DE : MIMXRT1062.h
- PWM_DMAEN_CX1DE_MASK : MIMXRT1062.h
- PWM_DMAEN_CX1DE_SHIFT : MIMXRT1062.h
- PWM_DMAEN_FAND : MIMXRT1062.h
- PWM_DMAEN_FAND_MASK : MIMXRT1062.h
- PWM_DMAEN_FAND_SHIFT : MIMXRT1062.h
- PWM_DMAEN_VALDE : MIMXRT1062.h
- PWM_DMAEN_VALDE_MASK : MIMXRT1062.h
- PWM_DMAEN_VALDE_SHIFT : MIMXRT1062.h
- PWM_DTCNT0_COUNT : MIMXRT1062.h
- PWM_DTCNT0_DTCNT0 : MIMXRT1062.h
- PWM_DTCNT0_DTCNT0_MASK : MIMXRT1062.h
- PWM_DTCNT0_DTCNT0_SHIFT : MIMXRT1062.h
- PWM_DTCNT1_COUNT : MIMXRT1062.h
- PWM_DTCNT1_DTCNT1 : MIMXRT1062.h
- PWM_DTCNT1_DTCNT1_MASK : MIMXRT1062.h
- PWM_DTCNT1_DTCNT1_SHIFT : MIMXRT1062.h
- PWM_DTSRCSEL_SM0SEL23 : MIMXRT1062.h
- PWM_DTSRCSEL_SM0SEL23_MASK : MIMXRT1062.h
- PWM_DTSRCSEL_SM0SEL23_SHIFT : MIMXRT1062.h
- PWM_DTSRCSEL_SM0SEL45 : MIMXRT1062.h
- PWM_DTSRCSEL_SM0SEL45_MASK : MIMXRT1062.h
- PWM_DTSRCSEL_SM0SEL45_SHIFT : MIMXRT1062.h
- PWM_DTSRCSEL_SM1SEL23 : MIMXRT1062.h
- PWM_DTSRCSEL_SM1SEL23_MASK : MIMXRT1062.h
- PWM_DTSRCSEL_SM1SEL23_SHIFT : MIMXRT1062.h
- PWM_DTSRCSEL_SM1SEL45 : MIMXRT1062.h
- PWM_DTSRCSEL_SM1SEL45_MASK : MIMXRT1062.h
- PWM_DTSRCSEL_SM1SEL45_SHIFT : MIMXRT1062.h
- PWM_DTSRCSEL_SM2SEL23 : MIMXRT1062.h
- PWM_DTSRCSEL_SM2SEL23_MASK : MIMXRT1062.h
- PWM_DTSRCSEL_SM2SEL23_SHIFT : MIMXRT1062.h
- PWM_DTSRCSEL_SM2SEL45 : MIMXRT1062.h
- PWM_DTSRCSEL_SM2SEL45_MASK : MIMXRT1062.h
- PWM_DTSRCSEL_SM2SEL45_SHIFT : MIMXRT1062.h
- PWM_DTSRCSEL_SM3SEL23 : MIMXRT1062.h
- PWM_DTSRCSEL_SM3SEL23_MASK : MIMXRT1062.h
- PWM_DTSRCSEL_SM3SEL23_SHIFT : MIMXRT1062.h
- PWM_DTSRCSEL_SM3SEL45 : MIMXRT1062.h
- PWM_DTSRCSEL_SM3SEL45_MASK : MIMXRT1062.h
- PWM_DTSRCSEL_SM3SEL45_SHIFT : MIMXRT1062.h
- PWM_FAULT_IRQS : MIMXRT1062.h
- PWM_FCTRL2_NOCOMB : MIMXRT1062.h
- PWM_FCTRL2_NOCOMB_MASK : MIMXRT1062.h
- PWM_FCTRL2_NOCOMB_SHIFT : MIMXRT1062.h
- PWM_FCTRL_FAUTO : MIMXRT1062.h
- PWM_FCTRL_FAUTO_MASK : MIMXRT1062.h
- PWM_FCTRL_FAUTO_SHIFT : MIMXRT1062.h
- PWM_FCTRL_FIE : MIMXRT1062.h
- PWM_FCTRL_FIE_MASK : MIMXRT1062.h
- PWM_FCTRL_FIE_SHIFT : MIMXRT1062.h
- PWM_FCTRL_FLVL : MIMXRT1062.h
- PWM_FCTRL_FLVL_MASK : MIMXRT1062.h
- PWM_FCTRL_FLVL_SHIFT : MIMXRT1062.h
- PWM_FCTRL_FSAFE : MIMXRT1062.h
- PWM_FCTRL_FSAFE_MASK : MIMXRT1062.h
- PWM_FCTRL_FSAFE_SHIFT : MIMXRT1062.h
- PWM_FFILT_FILT_CNT : MIMXRT1062.h
- PWM_FFILT_FILT_CNT_MASK : MIMXRT1062.h
- PWM_FFILT_FILT_CNT_SHIFT : MIMXRT1062.h
- PWM_FFILT_FILT_PER : MIMXRT1062.h
- PWM_FFILT_FILT_PER_MASK : MIMXRT1062.h
- PWM_FFILT_FILT_PER_SHIFT : MIMXRT1062.h
- PWM_FFILT_GSTR : MIMXRT1062.h
- PWM_FFILT_GSTR_MASK : MIMXRT1062.h
- PWM_FFILT_GSTR_SHIFT : MIMXRT1062.h
- PWM_FRACVAL1_COUNT : MIMXRT1062.h
- PWM_FRACVAL1_FRACVAL1 : MIMXRT1062.h
- PWM_FRACVAL1_FRACVAL1_MASK : MIMXRT1062.h
- PWM_FRACVAL1_FRACVAL1_SHIFT : MIMXRT1062.h
- PWM_FRACVAL2_COUNT : MIMXRT1062.h
- PWM_FRACVAL2_FRACVAL2 : MIMXRT1062.h
- PWM_FRACVAL2_FRACVAL2_MASK : MIMXRT1062.h
- PWM_FRACVAL2_FRACVAL2_SHIFT : MIMXRT1062.h
- PWM_FRACVAL3_COUNT : MIMXRT1062.h
- PWM_FRACVAL3_FRACVAL3 : MIMXRT1062.h
- PWM_FRACVAL3_FRACVAL3_MASK : MIMXRT1062.h
- PWM_FRACVAL3_FRACVAL3_SHIFT : MIMXRT1062.h
- PWM_FRACVAL4_COUNT : MIMXRT1062.h
- PWM_FRACVAL4_FRACVAL4 : MIMXRT1062.h
- PWM_FRACVAL4_FRACVAL4_MASK : MIMXRT1062.h
- PWM_FRACVAL4_FRACVAL4_SHIFT : MIMXRT1062.h
- PWM_FRACVAL5_COUNT : MIMXRT1062.h
- PWM_FRACVAL5_FRACVAL5 : MIMXRT1062.h
- PWM_FRACVAL5_FRACVAL5_MASK : MIMXRT1062.h
- PWM_FRACVAL5_FRACVAL5_SHIFT : MIMXRT1062.h
- PWM_FRCTRL_COUNT : MIMXRT1062.h
- PWM_FRCTRL_FRAC1_EN : MIMXRT1062.h
- PWM_FRCTRL_FRAC1_EN_MASK : MIMXRT1062.h
- PWM_FRCTRL_FRAC1_EN_SHIFT : MIMXRT1062.h
- PWM_FRCTRL_FRAC23_EN : MIMXRT1062.h
- PWM_FRCTRL_FRAC23_EN_MASK : MIMXRT1062.h
- PWM_FRCTRL_FRAC23_EN_SHIFT : MIMXRT1062.h
- PWM_FRCTRL_FRAC45_EN : MIMXRT1062.h
- PWM_FRCTRL_FRAC45_EN_MASK : MIMXRT1062.h
- PWM_FRCTRL_FRAC45_EN_SHIFT : MIMXRT1062.h
- PWM_FRCTRL_FRAC_PU : MIMXRT1062.h
- PWM_FRCTRL_FRAC_PU_MASK : MIMXRT1062.h
- PWM_FRCTRL_FRAC_PU_SHIFT : MIMXRT1062.h
- PWM_FRCTRL_TEST : MIMXRT1062.h
- PWM_FRCTRL_TEST_MASK : MIMXRT1062.h
- PWM_FRCTRL_TEST_SHIFT : MIMXRT1062.h
- PWM_FSTS_FFLAG : MIMXRT1062.h
- PWM_FSTS_FFLAG_MASK : MIMXRT1062.h
- PWM_FSTS_FFLAG_SHIFT : MIMXRT1062.h
- PWM_FSTS_FFPIN : MIMXRT1062.h
- PWM_FSTS_FFPIN_MASK : MIMXRT1062.h
- PWM_FSTS_FFPIN_SHIFT : MIMXRT1062.h
- PWM_FSTS_FFULL : MIMXRT1062.h
- PWM_FSTS_FFULL_MASK : MIMXRT1062.h
- PWM_FSTS_FFULL_SHIFT : MIMXRT1062.h
- PWM_FSTS_FHALF : MIMXRT1062.h
- PWM_FSTS_FHALF_MASK : MIMXRT1062.h
- PWM_FSTS_FHALF_SHIFT : MIMXRT1062.h
- PWM_FTST_FTEST : MIMXRT1062.h
- PWM_FTST_FTEST_MASK : MIMXRT1062.h
- PWM_FTST_FTEST_SHIFT : MIMXRT1062.h
- PWM_INIT_COUNT : MIMXRT1062.h
- PWM_INIT_INIT : MIMXRT1062.h
- PWM_INIT_INIT_MASK : MIMXRT1062.h
- PWM_INIT_INIT_SHIFT : MIMXRT1062.h
- PWM_INTEN_CA0IE : MIMXRT1062.h
- PWM_INTEN_CA0IE_MASK : MIMXRT1062.h
- PWM_INTEN_CA0IE_SHIFT : MIMXRT1062.h
- PWM_INTEN_CA1IE : MIMXRT1062.h
- PWM_INTEN_CA1IE_MASK : MIMXRT1062.h
- PWM_INTEN_CA1IE_SHIFT : MIMXRT1062.h
- PWM_INTEN_CB0IE : MIMXRT1062.h
- PWM_INTEN_CB0IE_MASK : MIMXRT1062.h
- PWM_INTEN_CB0IE_SHIFT : MIMXRT1062.h
- PWM_INTEN_CB1IE : MIMXRT1062.h
- PWM_INTEN_CB1IE_MASK : MIMXRT1062.h
- PWM_INTEN_CB1IE_SHIFT : MIMXRT1062.h
- PWM_INTEN_CMPIE : MIMXRT1062.h
- PWM_INTEN_CMPIE_MASK : MIMXRT1062.h
- PWM_INTEN_CMPIE_SHIFT : MIMXRT1062.h
- PWM_INTEN_COUNT : MIMXRT1062.h
- PWM_INTEN_CX0IE : MIMXRT1062.h
- PWM_INTEN_CX0IE_MASK : MIMXRT1062.h
- PWM_INTEN_CX0IE_SHIFT : MIMXRT1062.h
- PWM_INTEN_CX1IE : MIMXRT1062.h
- PWM_INTEN_CX1IE_MASK : MIMXRT1062.h
- PWM_INTEN_CX1IE_SHIFT : MIMXRT1062.h
- PWM_INTEN_REIE : MIMXRT1062.h
- PWM_INTEN_REIE_MASK : MIMXRT1062.h
- PWM_INTEN_REIE_SHIFT : MIMXRT1062.h
- PWM_INTEN_RIE : MIMXRT1062.h
- PWM_INTEN_RIE_MASK : MIMXRT1062.h
- PWM_INTEN_RIE_SHIFT : MIMXRT1062.h
- PWM_MASK_MASKA : MIMXRT1062.h
- PWM_MASK_MASKA_MASK : MIMXRT1062.h
- PWM_MASK_MASKA_SHIFT : MIMXRT1062.h
- PWM_MASK_MASKB : MIMXRT1062.h
- PWM_MASK_MASKB_MASK : MIMXRT1062.h
- PWM_MASK_MASKB_SHIFT : MIMXRT1062.h
- PWM_MASK_MASKX : MIMXRT1062.h
- PWM_MASK_MASKX_MASK : MIMXRT1062.h
- PWM_MASK_MASKX_SHIFT : MIMXRT1062.h
- PWM_MASK_UPDATE_MASK : MIMXRT1062.h
- PWM_MASK_UPDATE_MASK_MASK : MIMXRT1062.h
- PWM_MASK_UPDATE_MASK_SHIFT : MIMXRT1062.h
- PWM_MCTRL2_MONPLL : MIMXRT1062.h
- PWM_MCTRL2_MONPLL_MASK : MIMXRT1062.h
- PWM_MCTRL2_MONPLL_SHIFT : MIMXRT1062.h
- PWM_MCTRL_CLDOK : MIMXRT1062.h
- PWM_MCTRL_CLDOK_MASK : MIMXRT1062.h
- PWM_MCTRL_CLDOK_SHIFT : MIMXRT1062.h
- PWM_MCTRL_IPOL : MIMXRT1062.h
- PWM_MCTRL_IPOL_MASK : MIMXRT1062.h
- PWM_MCTRL_IPOL_SHIFT : MIMXRT1062.h
- PWM_MCTRL_LDOK : MIMXRT1062.h
- PWM_MCTRL_LDOK_MASK : MIMXRT1062.h
- PWM_MCTRL_LDOK_SHIFT : MIMXRT1062.h
- PWM_MCTRL_RUN : MIMXRT1062.h
- PWM_MCTRL_RUN_MASK : MIMXRT1062.h
- PWM_MCTRL_RUN_SHIFT : MIMXRT1062.h
- PWM_OCTRL_COUNT : MIMXRT1062.h
- PWM_OCTRL_POLA : MIMXRT1062.h
- PWM_OCTRL_POLA_MASK : MIMXRT1062.h
- PWM_OCTRL_POLA_SHIFT : MIMXRT1062.h
- PWM_OCTRL_POLB : MIMXRT1062.h
- PWM_OCTRL_POLB_MASK : MIMXRT1062.h
- PWM_OCTRL_POLB_SHIFT : MIMXRT1062.h
- PWM_OCTRL_POLX : MIMXRT1062.h
- PWM_OCTRL_POLX_MASK : MIMXRT1062.h
- PWM_OCTRL_POLX_SHIFT : MIMXRT1062.h
- PWM_OCTRL_PWMA_IN : MIMXRT1062.h
- PWM_OCTRL_PWMA_IN_MASK : MIMXRT1062.h
- PWM_OCTRL_PWMA_IN_SHIFT : MIMXRT1062.h
- PWM_OCTRL_PWMAFS : MIMXRT1062.h
- PWM_OCTRL_PWMAFS_MASK : MIMXRT1062.h
- PWM_OCTRL_PWMAFS_SHIFT : MIMXRT1062.h
- PWM_OCTRL_PWMB_IN : MIMXRT1062.h
- PWM_OCTRL_PWMB_IN_MASK : MIMXRT1062.h
- PWM_OCTRL_PWMB_IN_SHIFT : MIMXRT1062.h
- PWM_OCTRL_PWMBFS : MIMXRT1062.h
- PWM_OCTRL_PWMBFS_MASK : MIMXRT1062.h
- PWM_OCTRL_PWMBFS_SHIFT : MIMXRT1062.h
- PWM_OCTRL_PWMX_IN : MIMXRT1062.h
- PWM_OCTRL_PWMX_IN_MASK : MIMXRT1062.h
- PWM_OCTRL_PWMX_IN_SHIFT : MIMXRT1062.h
- PWM_OCTRL_PWMXFS : MIMXRT1062.h
- PWM_OCTRL_PWMXFS_MASK : MIMXRT1062.h
- PWM_OCTRL_PWMXFS_SHIFT : MIMXRT1062.h
- PWM_OUTEN_PWMA_EN : MIMXRT1062.h
- PWM_OUTEN_PWMA_EN_MASK : MIMXRT1062.h
- PWM_OUTEN_PWMA_EN_SHIFT : MIMXRT1062.h
- PWM_OUTEN_PWMB_EN : MIMXRT1062.h
- PWM_OUTEN_PWMB_EN_MASK : MIMXRT1062.h
- PWM_OUTEN_PWMB_EN_SHIFT : MIMXRT1062.h
- PWM_OUTEN_PWMX_EN : MIMXRT1062.h
- PWM_OUTEN_PWMX_EN_MASK : MIMXRT1062.h
- PWM_OUTEN_PWMX_EN_SHIFT : MIMXRT1062.h
- PWM_RELOAD_ERROR_IRQS : MIMXRT1062.h
- PWM_RELOAD_IRQS : MIMXRT1062.h
- PWM_STS_CFA0 : MIMXRT1062.h
- PWM_STS_CFA0_MASK : MIMXRT1062.h
- PWM_STS_CFA0_SHIFT : MIMXRT1062.h
- PWM_STS_CFA1 : MIMXRT1062.h
- PWM_STS_CFA1_MASK : MIMXRT1062.h
- PWM_STS_CFA1_SHIFT : MIMXRT1062.h
- PWM_STS_CFB0 : MIMXRT1062.h
- PWM_STS_CFB0_MASK : MIMXRT1062.h
- PWM_STS_CFB0_SHIFT : MIMXRT1062.h
- PWM_STS_CFB1 : MIMXRT1062.h
- PWM_STS_CFB1_MASK : MIMXRT1062.h
- PWM_STS_CFB1_SHIFT : MIMXRT1062.h
- PWM_STS_CFX0 : MIMXRT1062.h
- PWM_STS_CFX0_MASK : MIMXRT1062.h
- PWM_STS_CFX0_SHIFT : MIMXRT1062.h
- PWM_STS_CFX1 : MIMXRT1062.h
- PWM_STS_CFX1_MASK : MIMXRT1062.h
- PWM_STS_CFX1_SHIFT : MIMXRT1062.h
- PWM_STS_CMPF : MIMXRT1062.h
- PWM_STS_CMPF_MASK : MIMXRT1062.h
- PWM_STS_CMPF_SHIFT : MIMXRT1062.h
- PWM_STS_COUNT : MIMXRT1062.h
- PWM_STS_REF : MIMXRT1062.h
- PWM_STS_REF_MASK : MIMXRT1062.h
- PWM_STS_REF_SHIFT : MIMXRT1062.h
- PWM_STS_RF : MIMXRT1062.h
- PWM_STS_RF_MASK : MIMXRT1062.h
- PWM_STS_RF_SHIFT : MIMXRT1062.h
- PWM_STS_RUF : MIMXRT1062.h
- PWM_STS_RUF_MASK : MIMXRT1062.h
- PWM_STS_RUF_SHIFT : MIMXRT1062.h
- PWM_SWCOUT_SM0OUT23 : MIMXRT1062.h
- PWM_SWCOUT_SM0OUT23_MASK : MIMXRT1062.h
- PWM_SWCOUT_SM0OUT23_SHIFT : MIMXRT1062.h
- PWM_SWCOUT_SM0OUT45 : MIMXRT1062.h
- PWM_SWCOUT_SM0OUT45_MASK : MIMXRT1062.h
- PWM_SWCOUT_SM0OUT45_SHIFT : MIMXRT1062.h
- PWM_SWCOUT_SM1OUT23 : MIMXRT1062.h
- PWM_SWCOUT_SM1OUT23_MASK : MIMXRT1062.h
- PWM_SWCOUT_SM1OUT23_SHIFT : MIMXRT1062.h
- PWM_SWCOUT_SM1OUT45 : MIMXRT1062.h
- PWM_SWCOUT_SM1OUT45_MASK : MIMXRT1062.h
- PWM_SWCOUT_SM1OUT45_SHIFT : MIMXRT1062.h
- PWM_SWCOUT_SM2OUT23 : MIMXRT1062.h
- PWM_SWCOUT_SM2OUT23_MASK : MIMXRT1062.h
- PWM_SWCOUT_SM2OUT23_SHIFT : MIMXRT1062.h
- PWM_SWCOUT_SM2OUT45 : MIMXRT1062.h
- PWM_SWCOUT_SM2OUT45_MASK : MIMXRT1062.h
- PWM_SWCOUT_SM2OUT45_SHIFT : MIMXRT1062.h
- PWM_SWCOUT_SM3OUT23 : MIMXRT1062.h
- PWM_SWCOUT_SM3OUT23_MASK : MIMXRT1062.h
- PWM_SWCOUT_SM3OUT23_SHIFT : MIMXRT1062.h
- PWM_SWCOUT_SM3OUT45 : MIMXRT1062.h
- PWM_SWCOUT_SM3OUT45_MASK : MIMXRT1062.h
- PWM_SWCOUT_SM3OUT45_SHIFT : MIMXRT1062.h
- PWM_TCTRL_COUNT : MIMXRT1062.h
- PWM_TCTRL_OUT_TRIG_EN : MIMXRT1062.h
- PWM_TCTRL_OUT_TRIG_EN_MASK : MIMXRT1062.h
- PWM_TCTRL_OUT_TRIG_EN_SHIFT : MIMXRT1062.h
- PWM_TCTRL_PWAOT0 : MIMXRT1062.h
- PWM_TCTRL_PWAOT0_MASK : MIMXRT1062.h
- PWM_TCTRL_PWAOT0_SHIFT : MIMXRT1062.h
- PWM_TCTRL_PWBOT1 : MIMXRT1062.h
- PWM_TCTRL_PWBOT1_MASK : MIMXRT1062.h
- PWM_TCTRL_PWBOT1_SHIFT : MIMXRT1062.h
- PWM_TCTRL_TRGFRQ : MIMXRT1062.h
- PWM_TCTRL_TRGFRQ_MASK : MIMXRT1062.h
- PWM_TCTRL_TRGFRQ_SHIFT : MIMXRT1062.h
- PWM_VAL0_COUNT : MIMXRT1062.h
- PWM_VAL0_VAL0 : MIMXRT1062.h
- PWM_VAL0_VAL0_MASK : MIMXRT1062.h
- PWM_VAL0_VAL0_SHIFT : MIMXRT1062.h
- PWM_VAL1_COUNT : MIMXRT1062.h
- PWM_VAL1_VAL1 : MIMXRT1062.h
- PWM_VAL1_VAL1_MASK : MIMXRT1062.h
- PWM_VAL1_VAL1_SHIFT : MIMXRT1062.h
- PWM_VAL2_COUNT : MIMXRT1062.h
- PWM_VAL2_VAL2 : MIMXRT1062.h
- PWM_VAL2_VAL2_MASK : MIMXRT1062.h
- PWM_VAL2_VAL2_SHIFT : MIMXRT1062.h
- PWM_VAL3_COUNT : MIMXRT1062.h
- PWM_VAL3_VAL3 : MIMXRT1062.h
- PWM_VAL3_VAL3_MASK : MIMXRT1062.h
- PWM_VAL3_VAL3_SHIFT : MIMXRT1062.h
- PWM_VAL4_COUNT : MIMXRT1062.h
- PWM_VAL4_VAL4 : MIMXRT1062.h
- PWM_VAL4_VAL4_MASK : MIMXRT1062.h
- PWM_VAL4_VAL4_SHIFT : MIMXRT1062.h
- PWM_VAL5_COUNT : MIMXRT1062.h
- PWM_VAL5_VAL5 : MIMXRT1062.h
- PWM_VAL5_VAL5_MASK : MIMXRT1062.h
- PWM_VAL5_VAL5_SHIFT : MIMXRT1062.h
- PXP : MIMXRT1062.h
- PXP_AS_BUF_ADDR : MIMXRT1062.h
- PXP_AS_BUF_ADDR_MASK : MIMXRT1062.h
- PXP_AS_BUF_ADDR_SHIFT : MIMXRT1062.h
- PXP_AS_CLRKEYHIGH_PIXEL : MIMXRT1062.h
- PXP_AS_CLRKEYHIGH_PIXEL_MASK : MIMXRT1062.h
- PXP_AS_CLRKEYHIGH_PIXEL_SHIFT : MIMXRT1062.h
- PXP_AS_CLRKEYHIGH_RSVD1 : MIMXRT1062.h
- PXP_AS_CLRKEYHIGH_RSVD1_MASK : MIMXRT1062.h
- PXP_AS_CLRKEYHIGH_RSVD1_SHIFT : MIMXRT1062.h
- PXP_AS_CLRKEYLOW_PIXEL : MIMXRT1062.h
- PXP_AS_CLRKEYLOW_PIXEL_MASK : MIMXRT1062.h
- PXP_AS_CLRKEYLOW_PIXEL_SHIFT : MIMXRT1062.h
- PXP_AS_CLRKEYLOW_RSVD1 : MIMXRT1062.h
- PXP_AS_CLRKEYLOW_RSVD1_MASK : MIMXRT1062.h
- PXP_AS_CLRKEYLOW_RSVD1_SHIFT : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA_CTRL : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA_CTRL_MASK : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA_CTRL_SHIFT : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA_INVERT : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA_INVERT_MASK : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA_INVERT_SHIFT : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA_MASK : MIMXRT1062.h
- PXP_AS_CTRL_ALPHA_SHIFT : MIMXRT1062.h
- PXP_AS_CTRL_ENABLE_COLORKEY : MIMXRT1062.h
- PXP_AS_CTRL_ENABLE_COLORKEY_MASK : MIMXRT1062.h
- PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT : MIMXRT1062.h
- PXP_AS_CTRL_FORMAT : MIMXRT1062.h
- PXP_AS_CTRL_FORMAT_MASK : MIMXRT1062.h
- PXP_AS_CTRL_FORMAT_SHIFT : MIMXRT1062.h
- PXP_AS_CTRL_ROP : MIMXRT1062.h
- PXP_AS_CTRL_ROP_MASK : MIMXRT1062.h
- PXP_AS_CTRL_ROP_SHIFT : MIMXRT1062.h
- PXP_AS_CTRL_RSVD0 : MIMXRT1062.h
- PXP_AS_CTRL_RSVD0_MASK : MIMXRT1062.h
- PXP_AS_CTRL_RSVD0_SHIFT : MIMXRT1062.h
- PXP_AS_CTRL_RSVD1 : MIMXRT1062.h
- PXP_AS_CTRL_RSVD1_MASK : MIMXRT1062.h
- PXP_AS_CTRL_RSVD1_SHIFT : MIMXRT1062.h
- PXP_AS_PITCH_PITCH : MIMXRT1062.h
- PXP_AS_PITCH_PITCH_MASK : MIMXRT1062.h
- PXP_AS_PITCH_PITCH_SHIFT : MIMXRT1062.h
- PXP_AS_PITCH_RSVD : MIMXRT1062.h
- PXP_AS_PITCH_RSVD_MASK : MIMXRT1062.h
- PXP_AS_PITCH_RSVD_SHIFT : MIMXRT1062.h
- PXP_BASE : MIMXRT1062.h
- PXP_BASE_ADDRS : MIMXRT1062.h
- PXP_BASE_PTRS : MIMXRT1062.h
- PXP_CSC1_COEF0_BYPASS : MIMXRT1062.h
- PXP_CSC1_COEF0_BYPASS_MASK : MIMXRT1062.h
- PXP_CSC1_COEF0_BYPASS_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF0_C0 : MIMXRT1062.h
- PXP_CSC1_COEF0_C0_MASK : MIMXRT1062.h
- PXP_CSC1_COEF0_C0_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF0_RSVD1 : MIMXRT1062.h
- PXP_CSC1_COEF0_RSVD1_MASK : MIMXRT1062.h
- PXP_CSC1_COEF0_RSVD1_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF0_UV_OFFSET : MIMXRT1062.h
- PXP_CSC1_COEF0_UV_OFFSET_MASK : MIMXRT1062.h
- PXP_CSC1_COEF0_UV_OFFSET_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF0_Y_OFFSET : MIMXRT1062.h
- PXP_CSC1_COEF0_Y_OFFSET_MASK : MIMXRT1062.h
- PXP_CSC1_COEF0_Y_OFFSET_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF0_YCBCR_MODE : MIMXRT1062.h
- PXP_CSC1_COEF0_YCBCR_MODE_MASK : MIMXRT1062.h
- PXP_CSC1_COEF0_YCBCR_MODE_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF1_C1 : MIMXRT1062.h
- PXP_CSC1_COEF1_C1_MASK : MIMXRT1062.h
- PXP_CSC1_COEF1_C1_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF1_C4 : MIMXRT1062.h
- PXP_CSC1_COEF1_C4_MASK : MIMXRT1062.h
- PXP_CSC1_COEF1_C4_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF1_RSVD0 : MIMXRT1062.h
- PXP_CSC1_COEF1_RSVD0_MASK : MIMXRT1062.h
- PXP_CSC1_COEF1_RSVD0_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF1_RSVD1 : MIMXRT1062.h
- PXP_CSC1_COEF1_RSVD1_MASK : MIMXRT1062.h
- PXP_CSC1_COEF1_RSVD1_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF2_C2 : MIMXRT1062.h
- PXP_CSC1_COEF2_C2_MASK : MIMXRT1062.h
- PXP_CSC1_COEF2_C2_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF2_C3 : MIMXRT1062.h
- PXP_CSC1_COEF2_C3_MASK : MIMXRT1062.h
- PXP_CSC1_COEF2_C3_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF2_RSVD0 : MIMXRT1062.h
- PXP_CSC1_COEF2_RSVD0_MASK : MIMXRT1062.h
- PXP_CSC1_COEF2_RSVD0_SHIFT : MIMXRT1062.h
- PXP_CSC1_COEF2_RSVD1 : MIMXRT1062.h
- PXP_CSC1_COEF2_RSVD1_MASK : MIMXRT1062.h
- PXP_CSC1_COEF2_RSVD1_SHIFT : MIMXRT1062.h
- PXP_CTRL_BLOCK_SIZE : MIMXRT1062.h
- PXP_CTRL_BLOCK_SIZE_MASK : MIMXRT1062.h
- PXP_CTRL_BLOCK_SIZE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLKGATE : MIMXRT1062.h
- PXP_CTRL_CLKGATE_MASK : MIMXRT1062.h
- PXP_CTRL_CLKGATE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_BLOCK_SIZE : MIMXRT1062.h
- PXP_CTRL_CLR_BLOCK_SIZE_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_BLOCK_SIZE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_CLKGATE : MIMXRT1062.h
- PXP_CTRL_CLR_CLKGATE_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_CLKGATE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_EN_REPEAT : MIMXRT1062.h
- PXP_CTRL_CLR_EN_REPEAT_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_EN_REPEAT_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_ENABLE : MIMXRT1062.h
- PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE : MIMXRT1062.h
- PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_HFLIP : MIMXRT1062.h
- PXP_CTRL_CLR_HFLIP_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_HFLIP_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_IRQ_ENABLE : MIMXRT1062.h
- PXP_CTRL_CLR_IRQ_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_IRQ_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_NEXT_IRQ_ENABLE : MIMXRT1062.h
- PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_ROT_POS : MIMXRT1062.h
- PXP_CTRL_CLR_ROT_POS_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_ROT_POS_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_ROTATE : MIMXRT1062.h
- PXP_CTRL_CLR_ROTATE_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_ROTATE_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD0 : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD0_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD0_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD1 : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD1_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD1_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD3 : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD3_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD3_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD4 : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD4_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_RSVD4_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_SFTRST : MIMXRT1062.h
- PXP_CTRL_CLR_SFTRST_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_SFTRST_SHIFT : MIMXRT1062.h
- PXP_CTRL_CLR_VFLIP : MIMXRT1062.h
- PXP_CTRL_CLR_VFLIP_MASK : MIMXRT1062.h
- PXP_CTRL_CLR_VFLIP_SHIFT : MIMXRT1062.h
- PXP_CTRL_EN_REPEAT : MIMXRT1062.h
- PXP_CTRL_EN_REPEAT_MASK : MIMXRT1062.h
- PXP_CTRL_EN_REPEAT_SHIFT : MIMXRT1062.h
- PXP_CTRL_ENABLE : MIMXRT1062.h
- PXP_CTRL_ENABLE_LCD_HANDSHAKE : MIMXRT1062.h
- PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK : MIMXRT1062.h
- PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT : MIMXRT1062.h
- PXP_CTRL_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_HFLIP : MIMXRT1062.h
- PXP_CTRL_HFLIP_MASK : MIMXRT1062.h
- PXP_CTRL_HFLIP_SHIFT : MIMXRT1062.h
- PXP_CTRL_IRQ_ENABLE : MIMXRT1062.h
- PXP_CTRL_IRQ_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_IRQ_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_NEXT_IRQ_ENABLE : MIMXRT1062.h
- PXP_CTRL_NEXT_IRQ_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_ROT_POS : MIMXRT1062.h
- PXP_CTRL_ROT_POS_MASK : MIMXRT1062.h
- PXP_CTRL_ROT_POS_SHIFT : MIMXRT1062.h
- PXP_CTRL_ROTATE : MIMXRT1062.h
- PXP_CTRL_ROTATE_MASK : MIMXRT1062.h
- PXP_CTRL_ROTATE_SHIFT : MIMXRT1062.h
- PXP_CTRL_RSVD0 : MIMXRT1062.h
- PXP_CTRL_RSVD0_MASK : MIMXRT1062.h
- PXP_CTRL_RSVD0_SHIFT : MIMXRT1062.h
- PXP_CTRL_RSVD1 : MIMXRT1062.h
- PXP_CTRL_RSVD1_MASK : MIMXRT1062.h
- PXP_CTRL_RSVD1_SHIFT : MIMXRT1062.h
- PXP_CTRL_RSVD3 : MIMXRT1062.h
- PXP_CTRL_RSVD3_MASK : MIMXRT1062.h
- PXP_CTRL_RSVD3_SHIFT : MIMXRT1062.h
- PXP_CTRL_RSVD4 : MIMXRT1062.h
- PXP_CTRL_RSVD4_MASK : MIMXRT1062.h
- PXP_CTRL_RSVD4_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_BLOCK_SIZE : MIMXRT1062.h
- PXP_CTRL_SET_BLOCK_SIZE_MASK : MIMXRT1062.h
- PXP_CTRL_SET_BLOCK_SIZE_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_CLKGATE : MIMXRT1062.h
- PXP_CTRL_SET_CLKGATE_MASK : MIMXRT1062.h
- PXP_CTRL_SET_CLKGATE_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_EN_REPEAT : MIMXRT1062.h
- PXP_CTRL_SET_EN_REPEAT_MASK : MIMXRT1062.h
- PXP_CTRL_SET_EN_REPEAT_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_ENABLE : MIMXRT1062.h
- PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE : MIMXRT1062.h
- PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK : MIMXRT1062.h
- PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_SET_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_HFLIP : MIMXRT1062.h
- PXP_CTRL_SET_HFLIP_MASK : MIMXRT1062.h
- PXP_CTRL_SET_HFLIP_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_IRQ_ENABLE : MIMXRT1062.h
- PXP_CTRL_SET_IRQ_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_SET_IRQ_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_NEXT_IRQ_ENABLE : MIMXRT1062.h
- PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_ROT_POS : MIMXRT1062.h
- PXP_CTRL_SET_ROT_POS_MASK : MIMXRT1062.h
- PXP_CTRL_SET_ROT_POS_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_ROTATE : MIMXRT1062.h
- PXP_CTRL_SET_ROTATE_MASK : MIMXRT1062.h
- PXP_CTRL_SET_ROTATE_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_RSVD0 : MIMXRT1062.h
- PXP_CTRL_SET_RSVD0_MASK : MIMXRT1062.h
- PXP_CTRL_SET_RSVD0_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_RSVD1 : MIMXRT1062.h
- PXP_CTRL_SET_RSVD1_MASK : MIMXRT1062.h
- PXP_CTRL_SET_RSVD1_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_RSVD3 : MIMXRT1062.h
- PXP_CTRL_SET_RSVD3_MASK : MIMXRT1062.h
- PXP_CTRL_SET_RSVD3_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_RSVD4 : MIMXRT1062.h
- PXP_CTRL_SET_RSVD4_MASK : MIMXRT1062.h
- PXP_CTRL_SET_RSVD4_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_SFTRST : MIMXRT1062.h
- PXP_CTRL_SET_SFTRST_MASK : MIMXRT1062.h
- PXP_CTRL_SET_SFTRST_SHIFT : MIMXRT1062.h
- PXP_CTRL_SET_VFLIP : MIMXRT1062.h
- PXP_CTRL_SET_VFLIP_MASK : MIMXRT1062.h
- PXP_CTRL_SET_VFLIP_SHIFT : MIMXRT1062.h
- PXP_CTRL_SFTRST : MIMXRT1062.h
- PXP_CTRL_SFTRST_MASK : MIMXRT1062.h
- PXP_CTRL_SFTRST_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_BLOCK_SIZE : MIMXRT1062.h
- PXP_CTRL_TOG_BLOCK_SIZE_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_BLOCK_SIZE_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_CLKGATE : MIMXRT1062.h
- PXP_CTRL_TOG_CLKGATE_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_CLKGATE_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_EN_REPEAT : MIMXRT1062.h
- PXP_CTRL_TOG_EN_REPEAT_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_EN_REPEAT_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_ENABLE : MIMXRT1062.h
- PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE : MIMXRT1062.h
- PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_HFLIP : MIMXRT1062.h
- PXP_CTRL_TOG_HFLIP_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_HFLIP_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_IRQ_ENABLE : MIMXRT1062.h
- PXP_CTRL_TOG_IRQ_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_IRQ_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_NEXT_IRQ_ENABLE : MIMXRT1062.h
- PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_ROT_POS : MIMXRT1062.h
- PXP_CTRL_TOG_ROT_POS_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_ROT_POS_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_ROTATE : MIMXRT1062.h
- PXP_CTRL_TOG_ROTATE_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_ROTATE_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD0 : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD0_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD0_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD1 : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD1_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD1_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD3 : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD3_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD3_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD4 : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD4_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_RSVD4_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_SFTRST : MIMXRT1062.h
- PXP_CTRL_TOG_SFTRST_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_SFTRST_SHIFT : MIMXRT1062.h
- PXP_CTRL_TOG_VFLIP : MIMXRT1062.h
- PXP_CTRL_TOG_VFLIP_MASK : MIMXRT1062.h
- PXP_CTRL_TOG_VFLIP_SHIFT : MIMXRT1062.h
- PXP_CTRL_VFLIP : MIMXRT1062.h
- PXP_CTRL_VFLIP_MASK : MIMXRT1062.h
- PXP_CTRL_VFLIP_SHIFT : MIMXRT1062.h
- PXP_IRQ0_IRQS : MIMXRT1062.h
- PXP_NEXT_ENABLED : MIMXRT1062.h
- PXP_NEXT_ENABLED_MASK : MIMXRT1062.h
- PXP_NEXT_ENABLED_SHIFT : MIMXRT1062.h
- PXP_NEXT_POINTER : MIMXRT1062.h
- PXP_NEXT_POINTER_MASK : MIMXRT1062.h
- PXP_NEXT_POINTER_SHIFT : MIMXRT1062.h
- PXP_NEXT_RSVD : MIMXRT1062.h
- PXP_NEXT_RSVD_MASK : MIMXRT1062.h
- PXP_NEXT_RSVD_SHIFT : MIMXRT1062.h
- PXP_OUT_AS_LRC_RSVD0 : MIMXRT1062.h
- PXP_OUT_AS_LRC_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_AS_LRC_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_AS_LRC_RSVD1 : MIMXRT1062.h
- PXP_OUT_AS_LRC_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_AS_LRC_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_AS_LRC_X : MIMXRT1062.h
- PXP_OUT_AS_LRC_X_MASK : MIMXRT1062.h
- PXP_OUT_AS_LRC_X_SHIFT : MIMXRT1062.h
- PXP_OUT_AS_LRC_Y : MIMXRT1062.h
- PXP_OUT_AS_LRC_Y_MASK : MIMXRT1062.h
- PXP_OUT_AS_LRC_Y_SHIFT : MIMXRT1062.h
- PXP_OUT_AS_ULC_RSVD0 : MIMXRT1062.h
- PXP_OUT_AS_ULC_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_AS_ULC_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_AS_ULC_RSVD1 : MIMXRT1062.h
- PXP_OUT_AS_ULC_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_AS_ULC_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_AS_ULC_X : MIMXRT1062.h
- PXP_OUT_AS_ULC_X_MASK : MIMXRT1062.h
- PXP_OUT_AS_ULC_X_SHIFT : MIMXRT1062.h
- PXP_OUT_AS_ULC_Y : MIMXRT1062.h
- PXP_OUT_AS_ULC_Y_MASK : MIMXRT1062.h
- PXP_OUT_AS_ULC_Y_SHIFT : MIMXRT1062.h
- PXP_OUT_BUF2_ADDR : MIMXRT1062.h
- PXP_OUT_BUF2_ADDR_MASK : MIMXRT1062.h
- PXP_OUT_BUF2_ADDR_SHIFT : MIMXRT1062.h
- PXP_OUT_BUF_ADDR : MIMXRT1062.h
- PXP_OUT_BUF_ADDR_MASK : MIMXRT1062.h
- PXP_OUT_BUF_ADDR_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_ALPHA : MIMXRT1062.h
- PXP_OUT_CTRL_ALPHA_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_ALPHA_OUTPUT : MIMXRT1062.h
- PXP_OUT_CTRL_ALPHA_OUTPUT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_ALPHA_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_ALPHA : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_ALPHA_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_ALPHA_OUTPUT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_ALPHA_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_FORMAT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_FORMAT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_FORMAT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_RSVD0 : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_RSVD1 : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_CLR_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_FORMAT : MIMXRT1062.h
- PXP_OUT_CTRL_FORMAT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_FORMAT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_INTERLACED_OUTPUT : MIMXRT1062.h
- PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_RSVD0 : MIMXRT1062.h
- PXP_OUT_CTRL_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_RSVD1 : MIMXRT1062.h
- PXP_OUT_CTRL_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_ALPHA : MIMXRT1062.h
- PXP_OUT_CTRL_SET_ALPHA_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_SET_ALPHA_OUTPUT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_ALPHA_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_FORMAT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_FORMAT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_SET_FORMAT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_INTERLACED_OUTPUT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_RSVD0 : MIMXRT1062.h
- PXP_OUT_CTRL_SET_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_SET_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_SET_RSVD1 : MIMXRT1062.h
- PXP_OUT_CTRL_SET_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_SET_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_ALPHA : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_ALPHA_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_ALPHA_OUTPUT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_ALPHA_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_FORMAT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_FORMAT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_FORMAT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_RSVD0 : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_RSVD1 : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_CTRL_TOG_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_LRC_RSVD0 : MIMXRT1062.h
- PXP_OUT_LRC_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_LRC_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_LRC_RSVD1 : MIMXRT1062.h
- PXP_OUT_LRC_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_LRC_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_LRC_X : MIMXRT1062.h
- PXP_OUT_LRC_X_MASK : MIMXRT1062.h
- PXP_OUT_LRC_X_SHIFT : MIMXRT1062.h
- PXP_OUT_LRC_Y : MIMXRT1062.h
- PXP_OUT_LRC_Y_MASK : MIMXRT1062.h
- PXP_OUT_LRC_Y_SHIFT : MIMXRT1062.h
- PXP_OUT_PITCH_PITCH : MIMXRT1062.h
- PXP_OUT_PITCH_PITCH_MASK : MIMXRT1062.h
- PXP_OUT_PITCH_PITCH_SHIFT : MIMXRT1062.h
- PXP_OUT_PITCH_RSVD : MIMXRT1062.h
- PXP_OUT_PITCH_RSVD_MASK : MIMXRT1062.h
- PXP_OUT_PITCH_RSVD_SHIFT : MIMXRT1062.h
- PXP_OUT_PS_LRC_RSVD0 : MIMXRT1062.h
- PXP_OUT_PS_LRC_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_PS_LRC_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_PS_LRC_RSVD1 : MIMXRT1062.h
- PXP_OUT_PS_LRC_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_PS_LRC_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_PS_LRC_X : MIMXRT1062.h
- PXP_OUT_PS_LRC_X_MASK : MIMXRT1062.h
- PXP_OUT_PS_LRC_X_SHIFT : MIMXRT1062.h
- PXP_OUT_PS_LRC_Y : MIMXRT1062.h
- PXP_OUT_PS_LRC_Y_MASK : MIMXRT1062.h
- PXP_OUT_PS_LRC_Y_SHIFT : MIMXRT1062.h
- PXP_OUT_PS_ULC_RSVD0 : MIMXRT1062.h
- PXP_OUT_PS_ULC_RSVD0_MASK : MIMXRT1062.h
- PXP_OUT_PS_ULC_RSVD0_SHIFT : MIMXRT1062.h
- PXP_OUT_PS_ULC_RSVD1 : MIMXRT1062.h
- PXP_OUT_PS_ULC_RSVD1_MASK : MIMXRT1062.h
- PXP_OUT_PS_ULC_RSVD1_SHIFT : MIMXRT1062.h
- PXP_OUT_PS_ULC_X : MIMXRT1062.h
- PXP_OUT_PS_ULC_X_MASK : MIMXRT1062.h
- PXP_OUT_PS_ULC_X_SHIFT : MIMXRT1062.h
- PXP_OUT_PS_ULC_Y : MIMXRT1062.h
- PXP_OUT_PS_ULC_Y_MASK : MIMXRT1062.h
- PXP_OUT_PS_ULC_Y_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK : MIMXRT1062.h
- PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT : MIMXRT1062.h
- PXP_POWER_CTRL : MIMXRT1062.h
- PXP_POWER_CTRL_MASK : MIMXRT1062.h
- PXP_POWER_CTRL_SHIFT : MIMXRT1062.h
- PXP_POWER_ROT_MEM_LP_STATE : MIMXRT1062.h
- PXP_POWER_ROT_MEM_LP_STATE_MASK : MIMXRT1062.h
- PXP_POWER_ROT_MEM_LP_STATE_SHIFT : MIMXRT1062.h
- PXP_PS_BACKGROUND_COLOR : MIMXRT1062.h
- PXP_PS_BACKGROUND_COLOR_MASK : MIMXRT1062.h
- PXP_PS_BACKGROUND_COLOR_SHIFT : MIMXRT1062.h
- PXP_PS_BACKGROUND_RSVD : MIMXRT1062.h
- PXP_PS_BACKGROUND_RSVD_MASK : MIMXRT1062.h
- PXP_PS_BACKGROUND_RSVD_SHIFT : MIMXRT1062.h
- PXP_PS_BUF_ADDR : MIMXRT1062.h
- PXP_PS_BUF_ADDR_MASK : MIMXRT1062.h
- PXP_PS_BUF_ADDR_SHIFT : MIMXRT1062.h
- PXP_PS_CLRKEYHIGH_PIXEL : MIMXRT1062.h
- PXP_PS_CLRKEYHIGH_PIXEL_MASK : MIMXRT1062.h
- PXP_PS_CLRKEYHIGH_PIXEL_SHIFT : MIMXRT1062.h
- PXP_PS_CLRKEYHIGH_RSVD1 : MIMXRT1062.h
- PXP_PS_CLRKEYHIGH_RSVD1_MASK : MIMXRT1062.h
- PXP_PS_CLRKEYHIGH_RSVD1_SHIFT : MIMXRT1062.h
- PXP_PS_CLRKEYLOW_PIXEL : MIMXRT1062.h
- PXP_PS_CLRKEYLOW_PIXEL_MASK : MIMXRT1062.h
- PXP_PS_CLRKEYLOW_PIXEL_SHIFT : MIMXRT1062.h
- PXP_PS_CLRKEYLOW_RSVD1 : MIMXRT1062.h
- PXP_PS_CLRKEYLOW_RSVD1_MASK : MIMXRT1062.h
- PXP_PS_CLRKEYLOW_RSVD1_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_CLR_DECX : MIMXRT1062.h
- PXP_PS_CTRL_CLR_DECX_MASK : MIMXRT1062.h
- PXP_PS_CTRL_CLR_DECX_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_CLR_DECY : MIMXRT1062.h
- PXP_PS_CTRL_CLR_DECY_MASK : MIMXRT1062.h
- PXP_PS_CTRL_CLR_DECY_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_CLR_FORMAT : MIMXRT1062.h
- PXP_PS_CTRL_CLR_FORMAT_MASK : MIMXRT1062.h
- PXP_PS_CTRL_CLR_FORMAT_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_CLR_RSVD0 : MIMXRT1062.h
- PXP_PS_CTRL_CLR_RSVD0_MASK : MIMXRT1062.h
- PXP_PS_CTRL_CLR_RSVD0_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_CLR_RSVD1 : MIMXRT1062.h
- PXP_PS_CTRL_CLR_RSVD1_MASK : MIMXRT1062.h
- PXP_PS_CTRL_CLR_RSVD1_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_CLR_WB_SWAP : MIMXRT1062.h
- PXP_PS_CTRL_CLR_WB_SWAP_MASK : MIMXRT1062.h
- PXP_PS_CTRL_CLR_WB_SWAP_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_DECX : MIMXRT1062.h
- PXP_PS_CTRL_DECX_MASK : MIMXRT1062.h
- PXP_PS_CTRL_DECX_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_DECY : MIMXRT1062.h
- PXP_PS_CTRL_DECY_MASK : MIMXRT1062.h
- PXP_PS_CTRL_DECY_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_FORMAT : MIMXRT1062.h
- PXP_PS_CTRL_FORMAT_MASK : MIMXRT1062.h
- PXP_PS_CTRL_FORMAT_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_RSVD0 : MIMXRT1062.h
- PXP_PS_CTRL_RSVD0_MASK : MIMXRT1062.h
- PXP_PS_CTRL_RSVD0_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_RSVD1 : MIMXRT1062.h
- PXP_PS_CTRL_RSVD1_MASK : MIMXRT1062.h
- PXP_PS_CTRL_RSVD1_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_SET_DECX : MIMXRT1062.h
- PXP_PS_CTRL_SET_DECX_MASK : MIMXRT1062.h
- PXP_PS_CTRL_SET_DECX_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_SET_DECY : MIMXRT1062.h
- PXP_PS_CTRL_SET_DECY_MASK : MIMXRT1062.h
- PXP_PS_CTRL_SET_DECY_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_SET_FORMAT : MIMXRT1062.h
- PXP_PS_CTRL_SET_FORMAT_MASK : MIMXRT1062.h
- PXP_PS_CTRL_SET_FORMAT_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_SET_RSVD0 : MIMXRT1062.h
- PXP_PS_CTRL_SET_RSVD0_MASK : MIMXRT1062.h
- PXP_PS_CTRL_SET_RSVD0_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_SET_RSVD1 : MIMXRT1062.h
- PXP_PS_CTRL_SET_RSVD1_MASK : MIMXRT1062.h
- PXP_PS_CTRL_SET_RSVD1_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_SET_WB_SWAP : MIMXRT1062.h
- PXP_PS_CTRL_SET_WB_SWAP_MASK : MIMXRT1062.h
- PXP_PS_CTRL_SET_WB_SWAP_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_TOG_DECX : MIMXRT1062.h
- PXP_PS_CTRL_TOG_DECX_MASK : MIMXRT1062.h
- PXP_PS_CTRL_TOG_DECX_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_TOG_DECY : MIMXRT1062.h
- PXP_PS_CTRL_TOG_DECY_MASK : MIMXRT1062.h
- PXP_PS_CTRL_TOG_DECY_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_TOG_FORMAT : MIMXRT1062.h
- PXP_PS_CTRL_TOG_FORMAT_MASK : MIMXRT1062.h
- PXP_PS_CTRL_TOG_FORMAT_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_TOG_RSVD0 : MIMXRT1062.h
- PXP_PS_CTRL_TOG_RSVD0_MASK : MIMXRT1062.h
- PXP_PS_CTRL_TOG_RSVD0_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_TOG_RSVD1 : MIMXRT1062.h
- PXP_PS_CTRL_TOG_RSVD1_MASK : MIMXRT1062.h
- PXP_PS_CTRL_TOG_RSVD1_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_TOG_WB_SWAP : MIMXRT1062.h
- PXP_PS_CTRL_TOG_WB_SWAP_MASK : MIMXRT1062.h
- PXP_PS_CTRL_TOG_WB_SWAP_SHIFT : MIMXRT1062.h
- PXP_PS_CTRL_WB_SWAP : MIMXRT1062.h
- PXP_PS_CTRL_WB_SWAP_MASK : MIMXRT1062.h
- PXP_PS_CTRL_WB_SWAP_SHIFT : MIMXRT1062.h
- PXP_PS_OFFSET_RSVD1 : MIMXRT1062.h
- PXP_PS_OFFSET_RSVD1_MASK : MIMXRT1062.h
- PXP_PS_OFFSET_RSVD1_SHIFT : MIMXRT1062.h
- PXP_PS_OFFSET_RSVD2 : MIMXRT1062.h
- PXP_PS_OFFSET_RSVD2_MASK : MIMXRT1062.h
- PXP_PS_OFFSET_RSVD2_SHIFT : MIMXRT1062.h
- PXP_PS_OFFSET_XOFFSET : MIMXRT1062.h
- PXP_PS_OFFSET_XOFFSET_MASK : MIMXRT1062.h
- PXP_PS_OFFSET_XOFFSET_SHIFT : MIMXRT1062.h
- PXP_PS_OFFSET_YOFFSET : MIMXRT1062.h
- PXP_PS_OFFSET_YOFFSET_MASK : MIMXRT1062.h
- PXP_PS_OFFSET_YOFFSET_SHIFT : MIMXRT1062.h
- PXP_PS_PITCH_PITCH : MIMXRT1062.h
- PXP_PS_PITCH_PITCH_MASK : MIMXRT1062.h
- PXP_PS_PITCH_PITCH_SHIFT : MIMXRT1062.h
- PXP_PS_PITCH_RSVD : MIMXRT1062.h
- PXP_PS_PITCH_RSVD_MASK : MIMXRT1062.h
- PXP_PS_PITCH_RSVD_SHIFT : MIMXRT1062.h
- PXP_PS_SCALE_RSVD1 : MIMXRT1062.h
- PXP_PS_SCALE_RSVD1_MASK : MIMXRT1062.h
- PXP_PS_SCALE_RSVD1_SHIFT : MIMXRT1062.h
- PXP_PS_SCALE_RSVD2 : MIMXRT1062.h
- PXP_PS_SCALE_RSVD2_MASK : MIMXRT1062.h
- PXP_PS_SCALE_RSVD2_SHIFT : MIMXRT1062.h
- PXP_PS_SCALE_XSCALE : MIMXRT1062.h
- PXP_PS_SCALE_XSCALE_MASK : MIMXRT1062.h
- PXP_PS_SCALE_XSCALE_SHIFT : MIMXRT1062.h
- PXP_PS_SCALE_YSCALE : MIMXRT1062.h
- PXP_PS_SCALE_YSCALE_MASK : MIMXRT1062.h
- PXP_PS_SCALE_YSCALE_SHIFT : MIMXRT1062.h
- PXP_PS_UBUF_ADDR : MIMXRT1062.h
- PXP_PS_UBUF_ADDR_MASK : MIMXRT1062.h
- PXP_PS_UBUF_ADDR_SHIFT : MIMXRT1062.h
- PXP_PS_VBUF_ADDR : MIMXRT1062.h
- PXP_PS_VBUF_ADDR_MASK : MIMXRT1062.h
- PXP_PS_VBUF_ADDR_SHIFT : MIMXRT1062.h
- PXP_STAT_AXI_ERROR_ID : MIMXRT1062.h
- PXP_STAT_AXI_ERROR_ID_MASK : MIMXRT1062.h
- PXP_STAT_AXI_ERROR_ID_SHIFT : MIMXRT1062.h
- PXP_STAT_AXI_READ_ERROR : MIMXRT1062.h
- PXP_STAT_AXI_READ_ERROR_MASK : MIMXRT1062.h
- PXP_STAT_AXI_READ_ERROR_SHIFT : MIMXRT1062.h
- PXP_STAT_AXI_WRITE_ERROR : MIMXRT1062.h
- PXP_STAT_AXI_WRITE_ERROR_MASK : MIMXRT1062.h
- PXP_STAT_AXI_WRITE_ERROR_SHIFT : MIMXRT1062.h
- PXP_STAT_BLOCKX : MIMXRT1062.h
- PXP_STAT_BLOCKX_MASK : MIMXRT1062.h
- PXP_STAT_BLOCKX_SHIFT : MIMXRT1062.h
- PXP_STAT_BLOCKY : MIMXRT1062.h
- PXP_STAT_BLOCKY_MASK : MIMXRT1062.h
- PXP_STAT_BLOCKY_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_AXI_ERROR_ID : MIMXRT1062.h
- PXP_STAT_CLR_AXI_ERROR_ID_MASK : MIMXRT1062.h
- PXP_STAT_CLR_AXI_ERROR_ID_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_AXI_READ_ERROR : MIMXRT1062.h
- PXP_STAT_CLR_AXI_READ_ERROR_MASK : MIMXRT1062.h
- PXP_STAT_CLR_AXI_READ_ERROR_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_AXI_WRITE_ERROR : MIMXRT1062.h
- PXP_STAT_CLR_AXI_WRITE_ERROR_MASK : MIMXRT1062.h
- PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_BLOCKX : MIMXRT1062.h
- PXP_STAT_CLR_BLOCKX_MASK : MIMXRT1062.h
- PXP_STAT_CLR_BLOCKX_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_BLOCKY : MIMXRT1062.h
- PXP_STAT_CLR_BLOCKY_MASK : MIMXRT1062.h
- PXP_STAT_CLR_BLOCKY_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_IRQ : MIMXRT1062.h
- PXP_STAT_CLR_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_CLR_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ : MIMXRT1062.h
- PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_NEXT_IRQ : MIMXRT1062.h
- PXP_STAT_CLR_NEXT_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_CLR_NEXT_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_CLR_RSVD2 : MIMXRT1062.h
- PXP_STAT_CLR_RSVD2_MASK : MIMXRT1062.h
- PXP_STAT_CLR_RSVD2_SHIFT : MIMXRT1062.h
- PXP_STAT_IRQ : MIMXRT1062.h
- PXP_STAT_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_LUT_DMA_LOAD_DONE_IRQ : MIMXRT1062.h
- PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_NEXT_IRQ : MIMXRT1062.h
- PXP_STAT_NEXT_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_NEXT_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_RSVD2 : MIMXRT1062.h
- PXP_STAT_RSVD2_MASK : MIMXRT1062.h
- PXP_STAT_RSVD2_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_AXI_ERROR_ID : MIMXRT1062.h
- PXP_STAT_SET_AXI_ERROR_ID_MASK : MIMXRT1062.h
- PXP_STAT_SET_AXI_ERROR_ID_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_AXI_READ_ERROR : MIMXRT1062.h
- PXP_STAT_SET_AXI_READ_ERROR_MASK : MIMXRT1062.h
- PXP_STAT_SET_AXI_READ_ERROR_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_AXI_WRITE_ERROR : MIMXRT1062.h
- PXP_STAT_SET_AXI_WRITE_ERROR_MASK : MIMXRT1062.h
- PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_BLOCKX : MIMXRT1062.h
- PXP_STAT_SET_BLOCKX_MASK : MIMXRT1062.h
- PXP_STAT_SET_BLOCKX_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_BLOCKY : MIMXRT1062.h
- PXP_STAT_SET_BLOCKY_MASK : MIMXRT1062.h
- PXP_STAT_SET_BLOCKY_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_IRQ : MIMXRT1062.h
- PXP_STAT_SET_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_SET_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ : MIMXRT1062.h
- PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_NEXT_IRQ : MIMXRT1062.h
- PXP_STAT_SET_NEXT_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_SET_NEXT_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_SET_RSVD2 : MIMXRT1062.h
- PXP_STAT_SET_RSVD2_MASK : MIMXRT1062.h
- PXP_STAT_SET_RSVD2_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_AXI_ERROR_ID : MIMXRT1062.h
- PXP_STAT_TOG_AXI_ERROR_ID_MASK : MIMXRT1062.h
- PXP_STAT_TOG_AXI_ERROR_ID_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_AXI_READ_ERROR : MIMXRT1062.h
- PXP_STAT_TOG_AXI_READ_ERROR_MASK : MIMXRT1062.h
- PXP_STAT_TOG_AXI_READ_ERROR_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_AXI_WRITE_ERROR : MIMXRT1062.h
- PXP_STAT_TOG_AXI_WRITE_ERROR_MASK : MIMXRT1062.h
- PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_BLOCKX : MIMXRT1062.h
- PXP_STAT_TOG_BLOCKX_MASK : MIMXRT1062.h
- PXP_STAT_TOG_BLOCKX_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_BLOCKY : MIMXRT1062.h
- PXP_STAT_TOG_BLOCKY_MASK : MIMXRT1062.h
- PXP_STAT_TOG_BLOCKY_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_IRQ : MIMXRT1062.h
- PXP_STAT_TOG_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_TOG_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ : MIMXRT1062.h
- PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_NEXT_IRQ : MIMXRT1062.h
- PXP_STAT_TOG_NEXT_IRQ_MASK : MIMXRT1062.h
- PXP_STAT_TOG_NEXT_IRQ_SHIFT : MIMXRT1062.h
- PXP_STAT_TOG_RSVD2 : MIMXRT1062.h
- PXP_STAT_TOG_RSVD2_MASK : MIMXRT1062.h
- PXP_STAT_TOG_RSVD2_SHIFT : MIMXRT1062.h