Callisto4Bootloader: CMSIS/core_armv8mbl.h Source File

Callisto4Bootloader

core_armv8mbl.h
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1 /**************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_ARMV8MBL_H_GENERIC
32 #define __CORE_ARMV8MBL_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
63 #include "cmsis_version.h"
64
65 /* CMSIS definitions */
66 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
69 __ARMv8MBL_CMSIS_VERSION_SUB )
71 #define __CORTEX_M ( 2U)
76 #define __FPU_USED 0U
77
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88 #elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93 #elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98 #elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103 #elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108 #elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113 #endif
114
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118 #ifdef __cplusplus
119 }
120 #endif
121
122 #endif /* __CORE_ARMV8MBL_H_GENERIC */
123
124 #ifndef __CMSIS_GENERIC
125
126 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
127 #define __CORE_ARMV8MBL_H_DEPENDANT
128
129 #ifdef __cplusplus
130 extern "C" {
131 #endif
132
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135 #ifndef __ARMv8MBL_REV
136 #define __ARMv8MBL_REV 0x0000U
137 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __FPU_PRESENT
141 #define __FPU_PRESENT 0U
142 #warning "__FPU_PRESENT not defined in device header file; using default!"
143 #endif
144
145 #ifndef __MPU_PRESENT
146 #define __MPU_PRESENT 0U
147 #warning "__MPU_PRESENT not defined in device header file; using default!"
148 #endif
149
150 #ifndef __SAUREGION_PRESENT
151 #define __SAUREGION_PRESENT 0U
152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
153 #endif
154
155 #ifndef __VTOR_PRESENT
156 #define __VTOR_PRESENT 0U
157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
158 #endif
159
160 #ifndef __NVIC_PRIO_BITS
161 #define __NVIC_PRIO_BITS 2U
162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
163 #endif
164
165 #ifndef __Vendor_SysTickConfig
166 #define __Vendor_SysTickConfig 0U
167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
168 #endif
169
170 #ifndef __ETM_PRESENT
171 #define __ETM_PRESENT 0U
172 #warning "__ETM_PRESENT not defined in device header file; using default!"
173 #endif
174
175 #ifndef __MTB_PRESENT
176 #define __MTB_PRESENT 0U
177 #warning "__MTB_PRESENT not defined in device header file; using default!"
178 #endif
179
180 #endif
181
182 /* IO definitions (access restrictions to peripheral registers) */
190 #ifdef __cplusplus
191 #define __I volatile
192 #else
193 #define __I volatile const
194 #endif
195 #define __O volatile
196 #define __IO volatile
198 /* following defines should be used for structure members */
199 #define __IM volatile const
200 #define __OM volatile
201 #define __IOM volatile
203
207 /*******************************************************************************
208 * Register Abstraction
209 Core Register contain:
210 - Core Register
211 - Core NVIC Register
212 - Core SCB Register
213 - Core SysTick Register
214 - Core Debug Register
215 - Core MPU Register
216 - Core SAU Register
217 ******************************************************************************/
218
233 typedef union
234 {
235 struct
236 {
237 uint32_t _reserved0:28;
238 uint32_t V:1;
239 uint32_t C:1;
240 uint32_t Z:1;
241 uint32_t N:1;
242 } b;
243 uint32_t w;
244 } APSR_Type;
245
246 /* APSR Register Definitions */
247 #define APSR_N_Pos 31U
248 #define APSR_N_Msk (1UL << APSR_N_Pos)
250 #define APSR_Z_Pos 30U
251 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
253 #define APSR_C_Pos 29U
254 #define APSR_C_Msk (1UL << APSR_C_Pos)
256 #define APSR_V_Pos 28U
257 #define APSR_V_Msk (1UL << APSR_V_Pos)
263 typedef union
264 {
265 struct
266 {
267 uint32_t ISR:9;
268 uint32_t _reserved0:23;
269 } b;
270 uint32_t w;
271 } IPSR_Type;
272
273 /* IPSR Register Definitions */
274 #define IPSR_ISR_Pos 0U
275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
281 typedef union
282 {
283 struct
284 {
285 uint32_t ISR:9;
286 uint32_t _reserved0:15;
287 uint32_t T:1;
288 uint32_t _reserved1:3;
289 uint32_t V:1;
290 uint32_t C:1;
291 uint32_t Z:1;
292 uint32_t N:1;
293 } b;
294 uint32_t w;
295 } xPSR_Type;
296
297 /* xPSR Register Definitions */
298 #define xPSR_N_Pos 31U
299 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
301 #define xPSR_Z_Pos 30U
302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
304 #define xPSR_C_Pos 29U
305 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
307 #define xPSR_V_Pos 28U
308 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
310 #define xPSR_T_Pos 24U
311 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
313 #define xPSR_ISR_Pos 0U
314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
320 typedef union
321 {
322 struct
323 {
324 uint32_t nPRIV:1;
325 uint32_t SPSEL:1;
326 uint32_t _reserved1:30;
327 } b;
328 uint32_t w;
329 } CONTROL_Type;
330
331 /* CONTROL Register Definitions */
332 #define CONTROL_SPSEL_Pos 1U
333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
335 #define CONTROL_nPRIV_Pos 0U
336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
338
351 typedef struct
352 {
353 __IOM uint32_t ISER[16U];
354 uint32_t RESERVED0[16U];
355 __IOM uint32_t ICER[16U];
356 uint32_t RSERVED1[16U];
357 __IOM uint32_t ISPR[16U];
358 uint32_t RESERVED2[16U];
359 __IOM uint32_t ICPR[16U];
360 uint32_t RESERVED3[16U];
361 __IOM uint32_t IABR[16U];
362 uint32_t RESERVED4[16U];
363 __IOM uint32_t ITNS[16U];
364 uint32_t RESERVED5[16U];
365 __IOM uint32_t IPR[124U];
366 } NVIC_Type;
367
381 typedef struct
382 {
383 __IM uint32_t CPUID;
384 __IOM uint32_t ICSR;
385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
386 __IOM uint32_t VTOR;
387 #else
388 uint32_t RESERVED0;
389 #endif
390 __IOM uint32_t AIRCR;
391 __IOM uint32_t SCR;
392 __IOM uint32_t CCR;
393 uint32_t RESERVED1;
394 __IOM uint32_t SHPR[2U];
395 __IOM uint32_t SHCSR;
396 } SCB_Type;
397
398 /* SCB CPUID Register Definitions */
399 #define SCB_CPUID_IMPLEMENTER_Pos 24U
400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
402 #define SCB_CPUID_VARIANT_Pos 20U
403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
405 #define SCB_CPUID_ARCHITECTURE_Pos 16U
406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
408 #define SCB_CPUID_PARTNO_Pos 4U
409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
411 #define SCB_CPUID_REVISION_Pos 0U
412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
414 /* SCB Interrupt Control State Register Definitions */
415 #define SCB_ICSR_PENDNMISET_Pos 31U
416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
418 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
419 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
421 #define SCB_ICSR_PENDNMICLR_Pos 30U
422 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
424 #define SCB_ICSR_PENDSVSET_Pos 28U
425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
427 #define SCB_ICSR_PENDSVCLR_Pos 27U
428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
430 #define SCB_ICSR_PENDSTSET_Pos 26U
431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
433 #define SCB_ICSR_PENDSTCLR_Pos 25U
434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
436 #define SCB_ICSR_STTNS_Pos 24U
437 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
439 #define SCB_ICSR_ISRPREEMPT_Pos 23U
440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
442 #define SCB_ICSR_ISRPENDING_Pos 22U
443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
445 #define SCB_ICSR_VECTPENDING_Pos 12U
446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
448 #define SCB_ICSR_RETTOBASE_Pos 11U
449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
451 #define SCB_ICSR_VECTACTIVE_Pos 0U
452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
454 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
455 /* SCB Vector Table Offset Register Definitions */
456 #define SCB_VTOR_TBLOFF_Pos 7U
457 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
458 #endif
459
460 /* SCB Application Interrupt and Reset Control Register Definitions */
461 #define SCB_AIRCR_VECTKEY_Pos 16U
462 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
464 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
465 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
467 #define SCB_AIRCR_ENDIANESS_Pos 15U
468 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
470 #define SCB_AIRCR_PRIS_Pos 14U
471 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
473 #define SCB_AIRCR_BFHFNMINS_Pos 13U
474 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
476 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
477 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
479 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
480 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
482 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
483 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
485 /* SCB System Control Register Definitions */
486 #define SCB_SCR_SEVONPEND_Pos 4U
487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
489 #define SCB_SCR_SLEEPDEEPS_Pos 3U
490 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
492 #define SCB_SCR_SLEEPDEEP_Pos 2U
493 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
495 #define SCB_SCR_SLEEPONEXIT_Pos 1U
496 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
498 /* SCB Configuration Control Register Definitions */
499 #define SCB_CCR_BP_Pos 18U
500 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
502 #define SCB_CCR_IC_Pos 17U
503 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
505 #define SCB_CCR_DC_Pos 16U
506 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
508 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
509 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
511 #define SCB_CCR_BFHFNMIGN_Pos 8U
512 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
514 #define SCB_CCR_DIV_0_TRP_Pos 4U
515 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
517 #define SCB_CCR_UNALIGN_TRP_Pos 3U
518 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
520 #define SCB_CCR_USERSETMPEND_Pos 1U
521 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
523 /* SCB System Handler Control and State Register Definitions */
524 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
525 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
527 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
528 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
530 #define SCB_SHCSR_SYSTICKACT_Pos 11U
531 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
533 #define SCB_SHCSR_PENDSVACT_Pos 10U
534 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
536 #define SCB_SHCSR_SVCALLACT_Pos 7U
537 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
539 #define SCB_SHCSR_NMIACT_Pos 5U
540 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
542 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
543 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
545
558 typedef struct
559 {
560 __IOM uint32_t CTRL;
561 __IOM uint32_t LOAD;
562 __IOM uint32_t VAL;
563 __IM uint32_t CALIB;
564 } SysTick_Type;
565
566 /* SysTick Control / Status Register Definitions */
567 #define SysTick_CTRL_COUNTFLAG_Pos 16U
568 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
570 #define SysTick_CTRL_CLKSOURCE_Pos 2U
571 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
573 #define SysTick_CTRL_TICKINT_Pos 1U
574 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
576 #define SysTick_CTRL_ENABLE_Pos 0U
577 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
579 /* SysTick Reload Register Definitions */
580 #define SysTick_LOAD_RELOAD_Pos 0U
581 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
583 /* SysTick Current Register Definitions */
584 #define SysTick_VAL_CURRENT_Pos 0U
585 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
587 /* SysTick Calibration Register Definitions */
588 #define SysTick_CALIB_NOREF_Pos 31U
589 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
591 #define SysTick_CALIB_SKEW_Pos 30U
592 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
594 #define SysTick_CALIB_TENMS_Pos 0U
595 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
597
610 typedef struct
611 {
612 __IOM uint32_t CTRL;
613 uint32_t RESERVED0[6U];
614 __IM uint32_t PCSR;
615 __IOM uint32_t COMP0;
616 uint32_t RESERVED1[1U];
617 __IOM uint32_t FUNCTION0;
618 uint32_t RESERVED2[1U];
619 __IOM uint32_t COMP1;
620 uint32_t RESERVED3[1U];
621 __IOM uint32_t FUNCTION1;
622 uint32_t RESERVED4[1U];
623 __IOM uint32_t COMP2;
624 uint32_t RESERVED5[1U];
625 __IOM uint32_t FUNCTION2;
626 uint32_t RESERVED6[1U];
627 __IOM uint32_t COMP3;
628 uint32_t RESERVED7[1U];
629 __IOM uint32_t FUNCTION3;
630 uint32_t RESERVED8[1U];
631 __IOM uint32_t COMP4;
632 uint32_t RESERVED9[1U];
633 __IOM uint32_t FUNCTION4;
634 uint32_t RESERVED10[1U];
635 __IOM uint32_t COMP5;
636 uint32_t RESERVED11[1U];
637 __IOM uint32_t FUNCTION5;
638 uint32_t RESERVED12[1U];
639 __IOM uint32_t COMP6;
640 uint32_t RESERVED13[1U];
641 __IOM uint32_t FUNCTION6;
642 uint32_t RESERVED14[1U];
643 __IOM uint32_t COMP7;
644 uint32_t RESERVED15[1U];
645 __IOM uint32_t FUNCTION7;
646 uint32_t RESERVED16[1U];
647 __IOM uint32_t COMP8;
648 uint32_t RESERVED17[1U];
649 __IOM uint32_t FUNCTION8;
650 uint32_t RESERVED18[1U];
651 __IOM uint32_t COMP9;
652 uint32_t RESERVED19[1U];
653 __IOM uint32_t FUNCTION9;
654 uint32_t RESERVED20[1U];
655 __IOM uint32_t COMP10;
656 uint32_t RESERVED21[1U];
657 __IOM uint32_t FUNCTION10;
658 uint32_t RESERVED22[1U];
659 __IOM uint32_t COMP11;
660 uint32_t RESERVED23[1U];
661 __IOM uint32_t FUNCTION11;
662 uint32_t RESERVED24[1U];
663 __IOM uint32_t COMP12;
664 uint32_t RESERVED25[1U];
665 __IOM uint32_t FUNCTION12;
666 uint32_t RESERVED26[1U];
667 __IOM uint32_t COMP13;
668 uint32_t RESERVED27[1U];
669 __IOM uint32_t FUNCTION13;
670 uint32_t RESERVED28[1U];
671 __IOM uint32_t COMP14;
672 uint32_t RESERVED29[1U];
673 __IOM uint32_t FUNCTION14;
674 uint32_t RESERVED30[1U];
675 __IOM uint32_t COMP15;
676 uint32_t RESERVED31[1U];
677 __IOM uint32_t FUNCTION15;
678 } DWT_Type;
679
680 /* DWT Control Register Definitions */
681 #define DWT_CTRL_NUMCOMP_Pos 28U
682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
684 #define DWT_CTRL_NOTRCPKT_Pos 27U
685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
687 #define DWT_CTRL_NOEXTTRIG_Pos 26U
688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
690 #define DWT_CTRL_NOCYCCNT_Pos 25U
691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
693 #define DWT_CTRL_NOPRFCNT_Pos 24U
694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
696 /* DWT Comparator Function Register Definitions */
697 #define DWT_FUNCTION_ID_Pos 27U
698 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
700 #define DWT_FUNCTION_MATCHED_Pos 24U
701 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
703 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
704 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
706 #define DWT_FUNCTION_ACTION_Pos 4U
707 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)
709 #define DWT_FUNCTION_MATCH_Pos 0U
710 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
712 /* end of group CMSIS_DWT */
713
714
725 typedef struct
726 {
727 __IM uint32_t SSPSR;
728 __IOM uint32_t CSPSR;
729 uint32_t RESERVED0[2U];
730 __IOM uint32_t ACPR;
731 uint32_t RESERVED1[55U];
732 __IOM uint32_t SPPR;
733 uint32_t RESERVED2[131U];
734 __IM uint32_t FFSR;
735 __IOM uint32_t FFCR;
736 __IOM uint32_t PSCR;
737 uint32_t RESERVED3[809U];
738 __OM uint32_t LAR;
739 __IM uint32_t LSR;
740 uint32_t RESERVED4[4U];
741 __IM uint32_t TYPE;
742 __IM uint32_t DEVTYPE;
743 } TPI_Type;
744
745 /* TPI Asynchronous Clock Prescaler Register Definitions */
746 #define TPI_ACPR_SWOSCALER_Pos 0U
747 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
749 /* TPI Selected Pin Protocol Register Definitions */
750 #define TPI_SPPR_TXMODE_Pos 0U
751 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
753 /* TPI Formatter and Flush Status Register Definitions */
754 #define TPI_FFSR_FtNonStop_Pos 3U
755 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
757 #define TPI_FFSR_TCPresent_Pos 2U
758 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
760 #define TPI_FFSR_FtStopped_Pos 1U
761 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
763 #define TPI_FFSR_FlInProg_Pos 0U
764 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
766 /* TPI Formatter and Flush Control Register Definitions */
767 #define TPI_FFCR_TrigIn_Pos 8U
768 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
770 #define TPI_FFCR_FOnMan_Pos 6U
771 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
773 #define TPI_FFCR_EnFCont_Pos 1U
774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
776 /* TPI Periodic Synchronization Control Register Definitions */
777 #define TPI_PSCR_PSCount_Pos 0U
778 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
780 /* TPI Software Lock Status Register Definitions */
781 #define TPI_LSR_nTT_Pos 1U
782 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
784 #define TPI_LSR_SLK_Pos 1U
785 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
787 #define TPI_LSR_SLI_Pos 0U
788 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
790 /* TPI DEVID Register Definitions */
791 #define TPI_DEVID_NRZVALID_Pos 11U
792 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
794 #define TPI_DEVID_MANCVALID_Pos 10U
795 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
797 #define TPI_DEVID_PTINVALID_Pos 9U
798 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
800 #define TPI_DEVID_FIFOSZ_Pos 6U
801 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
803 /* TPI DEVTYPE Register Definitions */
804 #define TPI_DEVTYPE_SubType_Pos 4U
805 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
807 #define TPI_DEVTYPE_MajorType_Pos 0U
808 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
810 /* end of group CMSIS_TPI */
811
812
813 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
814
824 typedef struct
825 {
826 __IM uint32_t TYPE;
827 __IOM uint32_t CTRL;
828 __IOM uint32_t RNR;
829 __IOM uint32_t RBAR;
830 __IOM uint32_t RLAR;
831 uint32_t RESERVED0[7U];
832 union {
833 __IOM uint32_t MAIR[2];
834 struct {
835 __IOM uint32_t MAIR0;
836 __IOM uint32_t MAIR1;
837 };
838 };
839 } MPU_Type;
840
841 #define MPU_TYPE_RALIASES 1U
842
843 /* MPU Type Register Definitions */
844 #define MPU_TYPE_IREGION_Pos 16U
845 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
847 #define MPU_TYPE_DREGION_Pos 8U
848 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
850 #define MPU_TYPE_SEPARATE_Pos 0U
851 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
853 /* MPU Control Register Definitions */
854 #define MPU_CTRL_PRIVDEFENA_Pos 2U
855 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
857 #define MPU_CTRL_HFNMIENA_Pos 1U
858 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
860 #define MPU_CTRL_ENABLE_Pos 0U
861 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
863 /* MPU Region Number Register Definitions */
864 #define MPU_RNR_REGION_Pos 0U
865 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
867 /* MPU Region Base Address Register Definitions */
868 #define MPU_RBAR_BASE_Pos 5U
869 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
871 #define MPU_RBAR_SH_Pos 3U
872 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
874 #define MPU_RBAR_AP_Pos 1U
875 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
877 #define MPU_RBAR_XN_Pos 0U
878 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
880 /* MPU Region Limit Address Register Definitions */
881 #define MPU_RLAR_LIMIT_Pos 5U
882 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
884 #define MPU_RLAR_AttrIndx_Pos 1U
885 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
887 #define MPU_RLAR_EN_Pos 0U
888 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
890 /* MPU Memory Attribute Indirection Register 0 Definitions */
891 #define MPU_MAIR0_Attr3_Pos 24U
892 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
894 #define MPU_MAIR0_Attr2_Pos 16U
895 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
897 #define MPU_MAIR0_Attr1_Pos 8U
898 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
900 #define MPU_MAIR0_Attr0_Pos 0U
901 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
903 /* MPU Memory Attribute Indirection Register 1 Definitions */
904 #define MPU_MAIR1_Attr7_Pos 24U
905 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
907 #define MPU_MAIR1_Attr6_Pos 16U
908 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
910 #define MPU_MAIR1_Attr5_Pos 8U
911 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
913 #define MPU_MAIR1_Attr4_Pos 0U
914 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
916
917 #endif
918
919
920 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
921
931 typedef struct
932 {
933 __IOM uint32_t CTRL;
934 __IM uint32_t TYPE;
935 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
936 __IOM uint32_t RNR;
937 __IOM uint32_t RBAR;
938 __IOM uint32_t RLAR;
939 #endif
940 } SAU_Type;
941
942 /* SAU Control Register Definitions */
943 #define SAU_CTRL_ALLNS_Pos 1U
944 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
946 #define SAU_CTRL_ENABLE_Pos 0U
947 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
949 /* SAU Type Register Definitions */
950 #define SAU_TYPE_SREGION_Pos 0U
951 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
953 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
954 /* SAU Region Number Register Definitions */
955 #define SAU_RNR_REGION_Pos 0U
956 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
958 /* SAU Region Base Address Register Definitions */
959 #define SAU_RBAR_BADDR_Pos 5U
960 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
962 /* SAU Region Limit Address Register Definitions */
963 #define SAU_RLAR_LADDR_Pos 5U
964 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
966 #define SAU_RLAR_NSC_Pos 1U
967 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
969 #define SAU_RLAR_ENABLE_Pos 0U
970 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
972 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
973
975 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
976
977
988 typedef struct
989 {
990 __IOM uint32_t DHCSR;
991 __OM uint32_t DCRSR;
992 __IOM uint32_t DCRDR;
993 __IOM uint32_t DEMCR;
994 uint32_t RESERVED4[1U];
995 __IOM uint32_t DAUTHCTRL;
996 __IOM uint32_t DSCSR;
997 } CoreDebug_Type;
998
999 /* Debug Halting Control and Status Register Definitions */
1000 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1001 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1006 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1007 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1009 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1010 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1012 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1013 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1015 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1016 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1018 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1019 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1021 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1022 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1024 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1025 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1027 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1028 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1030 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1031 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1033 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1034 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1036 /* Debug Core Register Selector Register Definitions */
1037 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1038 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1040 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1041 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1043 /* Debug Exception and Monitor Control Register */
1044 #define CoreDebug_DEMCR_DWTENA_Pos 24U
1045 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)
1047 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1048 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1050 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1051 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1053 /* Debug Authentication Control Register Definitions */
1054 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1055 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1057 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1058 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1060 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1061 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1063 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1064 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1066 /* Debug Security Control and Status Register Definitions */
1067 #define CoreDebug_DSCSR_CDS_Pos 16U
1068 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1070 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1071 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1073 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1074 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1076
1092 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1093
1100 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1101
1112 /* Memory mapping of Core Hardware */
1113 #define SCS_BASE (0xE000E000UL)
1114 #define DWT_BASE (0xE0001000UL)
1115 #define TPI_BASE (0xE0040000UL)
1116 #define CoreDebug_BASE (0xE000EDF0UL)
1117 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1118 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1119 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1122 #define SCB ((SCB_Type *) SCB_BASE )
1123 #define SysTick ((SysTick_Type *) SysTick_BASE )
1124 #define NVIC ((NVIC_Type *) NVIC_BASE )
1125 #define DWT ((DWT_Type *) DWT_BASE )
1126 #define TPI ((TPI_Type *) TPI_BASE )
1127 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
1129 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1130 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1131 #define MPU ((MPU_Type *) MPU_BASE )
1132 #endif
1133
1134 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1135 #define SAU_BASE (SCS_BASE + 0x0DD0UL)
1136 #define SAU ((SAU_Type *) SAU_BASE )
1137 #endif
1138
1139 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1140 #define SCS_BASE_NS (0xE002E000UL)
1141 #define CoreDebug_BASE_NS (0xE002EDF0UL)
1142 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
1143 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
1144 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
1146 #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
1147 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
1148 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
1149 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
1151 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1152 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
1153 #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
1154 #endif
1155
1156 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1157
1161 /*******************************************************************************
1162 * Hardware Abstraction Layer
1163 Core Function Interface contains:
1164 - Core NVIC Functions
1165 - Core SysTick Functions
1166 - Core Register Access Functions
1167 ******************************************************************************/
1174 /* ########################## NVIC functions #################################### */
1182 #ifdef CMSIS_NVIC_VIRTUAL
1183 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1184 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1185 #endif
1186 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1187 #else
1188 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1189 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1190 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1191 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1192 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1193 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1194 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1195 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1196 #define NVIC_GetActive __NVIC_GetActive
1197 #define NVIC_SetPriority __NVIC_SetPriority
1198 #define NVIC_GetPriority __NVIC_GetPriority
1199 #define NVIC_SystemReset __NVIC_SystemReset
1200 #endif /* CMSIS_NVIC_VIRTUAL */
1201
1202 #ifdef CMSIS_VECTAB_VIRTUAL
1203 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1204 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1205 #endif
1206 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1207 #else
1208 #define NVIC_SetVector __NVIC_SetVector
1209 #define NVIC_GetVector __NVIC_GetVector
1210 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1211
1212 #define NVIC_USER_IRQ_OFFSET 16
1213
1214
1215 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1216
1217 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1218 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1219
1220 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1221 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1222 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1223 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1224 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
1225 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
1226 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
1227 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
1228
1229 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
1230 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
1231 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1232 #else
1233 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
1234 #endif
1235
1236
1237 /* Interrupt Priorities are WORD accessible only under Armv6-M */
1238 /* The following MACROS handle generation of the register offset and byte masks */
1239 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1240 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1241 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1242
1243 #define __NVIC_SetPriorityGrouping(X) (void)(X)
1244 #define __NVIC_GetPriorityGrouping() (0U)
1245
1252 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1253 {
1254 if ((int32_t)(IRQn) >= 0)
1255 {
1256 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1257 }
1258 }
1259
1260
1269 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1270 {
1271 if ((int32_t)(IRQn) >= 0)
1272 {
1273 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1274 }
1275 else
1276 {
1277 return(0U);
1278 }
1279 }
1280
1281
1288 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1289 {
1290 if ((int32_t)(IRQn) >= 0)
1291 {
1292 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1293 __DSB();
1294 __ISB();
1295 }
1296 }
1297
1298
1307 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1308 {
1309 if ((int32_t)(IRQn) >= 0)
1310 {
1311 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1312 }
1313 else
1314 {
1315 return(0U);
1316 }
1317 }
1318
1319
1326 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1327 {
1328 if ((int32_t)(IRQn) >= 0)
1329 {
1330 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1331 }
1332 }
1333
1334
1341 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1342 {
1343 if ((int32_t)(IRQn) >= 0)
1344 {
1345 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1346 }
1347 }
1348
1349
1358 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1359 {
1360 if ((int32_t)(IRQn) >= 0)
1361 {
1362 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1363 }
1364 else
1365 {
1366 return(0U);
1367 }
1368 }
1369
1370
1371 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1372
1380 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1381 {
1382 if ((int32_t)(IRQn) >= 0)
1383 {
1384 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1385 }
1386 else
1387 {
1388 return(0U);
1389 }
1390 }
1391
1392
1401 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1402 {
1403 if ((int32_t)(IRQn) >= 0)
1404 {
1405 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1406 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1407 }
1408 else
1409 {
1410 return(0U);
1411 }
1412 }
1413
1414
1423 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1424 {
1425 if ((int32_t)(IRQn) >= 0)
1426 {
1427 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1428 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1429 }
1430 else
1431 {
1432 return(0U);
1433 }
1434 }
1435 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1436
1437
1447 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1448 {
1449 if ((int32_t)(IRQn) >= 0)
1450 {
1451 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1452 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1453 }
1454 else
1455 {
1456 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1457 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1458 }
1459 }
1460
1461
1471 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1472 {
1473
1474 if ((int32_t)(IRQn) >= 0)
1475 {
1476 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1477 }
1478 else
1479 {
1480 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1481 }
1482 }
1483
1484
1496 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1497 {
1498 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1499 uint32_t PreemptPriorityBits;
1500 uint32_t SubPriorityBits;
1501
1502 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1503 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1504
1505 return (
1506 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1507 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1508 );
1509 }
1510
1511
1523 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1524 {
1525 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1526 uint32_t PreemptPriorityBits;
1527 uint32_t SubPriorityBits;
1528
1529 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1530 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1531
1532 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1533 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1534 }
1535
1536
1547 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1548 {
1549 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1550 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1551 #else
1552 uint32_t *vectors = (uint32_t *)0x0U;
1553 #endif
1554 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1555 }
1556
1557
1566 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1567 {
1568 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1569 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1570 #else
1571 uint32_t *vectors = (uint32_t *)0x0U;
1572 #endif
1573 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1574 }
1575
1576
1581 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1582 {
1583 __DSB(); /* Ensure all outstanding memory accesses included
1584 buffered write are completed before reset */
1585 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1586 SCB_AIRCR_SYSRESETREQ_Msk);
1587 __DSB(); /* Ensure completion of memory access */
1588
1589 for(;;) /* wait until reset */
1590 {
1591 __NOP();
1592 }
1593 }
1594
1595 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1596
1602 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1603 {
1604 if ((int32_t)(IRQn) >= 0)
1605 {
1606 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1607 }
1608 }
1609
1610
1619 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1620 {
1621 if ((int32_t)(IRQn) >= 0)
1622 {
1623 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1624 }
1625 else
1626 {
1627 return(0U);
1628 }
1629 }
1630
1631
1638 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1639 {
1640 if ((int32_t)(IRQn) >= 0)
1641 {
1642 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1643 }
1644 }
1645
1646
1655 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1656 {
1657 if ((int32_t)(IRQn) >= 0)
1658 {
1659 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1660 }
1661 else
1662 {
1663 return(0U);
1664 }
1665 }
1666
1667
1674 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1675 {
1676 if ((int32_t)(IRQn) >= 0)
1677 {
1678 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1679 }
1680 }
1681
1682
1689 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1690 {
1691 if ((int32_t)(IRQn) >= 0)
1692 {
1693 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1694 }
1695 }
1696
1697
1706 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1707 {
1708 if ((int32_t)(IRQn) >= 0)
1709 {
1710 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1711 }
1712 else
1713 {
1714 return(0U);
1715 }
1716 }
1717
1718
1728 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
1729 {
1730 if ((int32_t)(IRQn) >= 0)
1731 {
1732 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1733 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1734 }
1735 else
1736 {
1737 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1738 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1739 }
1740 }
1741
1742
1751 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
1752 {
1753
1754 if ((int32_t)(IRQn) >= 0)
1755 {
1756 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1757 }
1758 else
1759 {
1760 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1761 }
1762 }
1763 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
1764
1767 /* ########################## MPU functions #################################### */
1768
1769 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1770
1771 #include "mpu_armv8.h"
1772
1773 #endif
1774
1775 /* ########################## FPU functions #################################### */
1791 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1792 {
1793 return 0U; /* No FPU */
1794 }
1795
1796
1801 /* ########################## SAU functions #################################### */
1809 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1810
1815 __STATIC_INLINE void TZ_SAU_Enable(void)
1816 {
1817 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
1818 }
1819
1820
1821
1826 __STATIC_INLINE void TZ_SAU_Disable(void)
1827 {
1828 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
1829 }
1830
1831 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1832
1838 /* ################################## SysTick function ############################################ */
1846 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1847
1859 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1860 {
1861 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1862 {
1863 return (1UL); /* Reload value impossible */
1864 }
1865
1866 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1867 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1868 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1869 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1870 SysTick_CTRL_TICKINT_Msk |
1871 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1872 return (0UL); /* Function successful */
1873 }
1874
1875 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1876
1888 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
1889 {
1890 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1891 {
1892 return (1UL); /* Reload value impossible */
1893 }
1894
1895 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1896 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1897 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
1898 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1899 SysTick_CTRL_TICKINT_Msk |
1900 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1901 return (0UL); /* Function successful */
1902 }
1903 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1904
1905 #endif
1906
1912 #ifdef __cplusplus
1913 }
1914 #endif
1915
1916 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
1917
1918 #endif /* __CMSIS_GENERIC */
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1034
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1062.h:268
_IP_IDX
#define _IP_IDX(IRQn)
Definition: core_armv8mbl.h:1238
NVIC
#define NVIC
Definition: core_armv8mbl.h:1122
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:2259
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:2380
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:2274
__IOM
#define __IOM
Definition: core_armv8mbl.h:200
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:2746
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:371
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866
SysTick_IRQn
Definition: MIMXRT1062.h:87
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv8mbl.h:1194
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:2185
mpu_armv8.h
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1387
SysTick
#define SysTick
Definition: core_armv8mbl.h:1121
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:497
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv8mbl.h:572
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:2291
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: core_armv8mbl.h:1237
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:2477
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:2427
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:391
IRQn
IRQn
Definition: MIMXRT1062.h:74
IRQn_Type
enum IRQn IRQn_Type
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:353
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv8mbl.h:579
cmsis_version.h
CMSIS Core(M) Version definitions.
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:2221
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:2503
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:2492
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:422
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:63
__IM
#define __IM
Definition: core_armv8mbl.h:198
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:2240
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv8mbl.h:478
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:2402
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv8mbl.h:575
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_armv81mml.h:1875
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:461
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:2202
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_armcc.h:69
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:314
cmsis_compiler.h
CMSIS compiler generic header file.
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: core_armv8mbl.h:1236
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv8mbl.h:569
SCB
#define SCB
Definition: core_armv8mbl.h:1120
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:2454
__OM
#define __OM
Definition: core_armv8mbl.h:199
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv8mbl.h:1209
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv8mbl.h:459
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1201