Callisto4Bootloader: drivers/fsl_flexspi.c Source File

Callisto4Bootloader

fsl_flexspi.c
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1 /*
2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 *
8 */
9 #include "fsl_flexspi.h"
10 #include <assert.h>
11 #include <stdbool.h>
12 #include "fsl_device_registers.h"
13 //#include "microseconds/microseconds.h"
14
15 /*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18 #define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0ul)
19 #define FLEXSPI_WAIT_TIMEOUT_NS (500000000UL)
20 #define FLEXSPI_FREQ_1GHz (1000000000UL)
21
22 #define FREQ_1MHz (1000000UL)
23 #define FLEXSPI_DLLCR_DEFAULT (0x100UL)
24
25 #define FLEXSPI0_CLK_GATE_OFFSET 13U
26 #define FLEXSPI1_CLK_GATE_OFFSET 15U
27
28 #define CMD_LUT_FOR_IP_CMD 1
29
30 enum
31 {
32 kFlexSpiDelayCellUnit_Min = 75, // 75ps
33 kFlexSpiDelayCellUnit_Max = 225, // 225ps
34 };
35
36 #define FLEXSPI_PINMUX_VAL 0x08
37
38 /*******************************************************************************
39 * Local variables
40 ******************************************************************************/
41 static FLEXSPI_Type *const g_flexSpiInstances[] = FLEXSPI_BASE_PTRS;
42
43 /*******************************************************************************
44 * Prototypes
45 ******************************************************************************/
47 static void flexspi_swreset(FLEXSPI_Type *base);
49 static void flexspi_unlock_lut(FLEXSPI_Type *base);
51 static void flexspi_lock_lut(FLEXSPI_Type *base);
53 static void flexspi_clear_ip_txfifo(FLEXSPI_Type *base);
55 static void flexspi_clear_ip_rxfifo(FLEXSPI_Type *base);
57 static void flexspi_wait_until_ip_idle(FLEXSPI_Type *base);
59 static FLEXSPI_Type *flexspi_get_module_base(uint32_t instance);
61 static void flexspi_clear_error_status(FLEXSPI_Type *base);
63 status_t flexspi_get_ticks(uint32_t *ticks, uint32_t intervalNs, uint32_t freq, uint32_t unit);
64 #if FLEXSPI_FEATURE_HAS_PARALLEL_MODE
65 static status_t flexspi_extract_parallel_data(uint32_t *dst0, uint32_t *dst1, uint32_t *src, uint32_t length);
67 #endif // FLEXSPI_FEATURE_HAS_PARALLEL_MODE
68
70 static status_t flexspi_device_workmode_config(uint32_t instance, flexspi_mem_config_t *config, uint32_t baseAddr);
71 static status_t flexspi_device_workmode_config_all_chips(uint32_t instance, flexspi_mem_config_t *config);
73 static status_t flexspi_device_cmd_config(uint32_t instance, flexspi_mem_config_t *config, uint32_t baseAddr);
74 static status_t flexspi_device_cmd_config_all_chips(uint32_t instance, flexspi_mem_config_t *config);
75
76 /*******************************************************************************
77 * Codes
78 ******************************************************************************/
79 static void flexspi_swreset(FLEXSPI_Type *base)
80 {
81 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
82 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
83 {
84 }
85 }
86
87 static void flexspi_unlock_lut(FLEXSPI_Type *base)
88 {
89 base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
90 base->LUTCR = 0x02;
91 }
92
93 static void flexspi_lock_lut(FLEXSPI_Type *base)
94 {
95 base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
96 base->LUTCR = 0x01;
97 }
98
99 bool flexspi_is_parallel_mode(flexspi_mem_config_t *config)
100 {
101 if (config->controllerMiscOption & FLEXSPI_BITMASK(kFlexSpiMiscOffset_ParallelEnable))
102 {
103 return true;
104 }
105 else
106 {
107 return false;
108 }
109 }
110
111 bool flexspi_is_padsetting_override_enable(flexspi_mem_config_t *config)
112 {
113 if (config->controllerMiscOption & FLEXSPI_BITMASK(kFlexSpiMiscOffset_PadSettingOverrideEnable))
114 {
115 return true;
116 }
117 else
118 {
119 return false;
120 }
121 }
122
123 bool flexspi_is_differential_clock_enable(flexspi_mem_config_t *config)
124 {
125 if (config->controllerMiscOption & FLEXSPI_BITMASK(kFlexSpiMiscOffset_DiffClkEnable))
126 {
127 return true;
128 }
129 else
130 {
131 return false;
132 }
133 }
134
135 bool flexspi_is_word_addressable(flexspi_mem_config_t *config)
136 {
137 if (config->controllerMiscOption & FLEXSPI_BITMASK(kFlexSpiMiscOffset_WordAddressableEnable))
138 {
139 return true;
140 }
141 else
142 {
143 return false;
144 }
145 }
146
147 bool flexspi_is_ck2_enabled(flexspi_mem_config_t *config)
148 {
149 if (config->controllerMiscOption & FLEXSPI_BITMASK(kFlexSpiMiscOffset_Ck2Enable))
150 {
151 return true;
152 }
153 else
154 {
155 return false;
156 }
157 }
158
159 bool flexspi_is_ddr_mode_enable(flexspi_mem_config_t *config)
160 {
161 if (config->controllerMiscOption & FLEXSPI_BITMASK(kFlexSpiMiscOffset_DdrModeEnable))
162 {
163 return true;
164 }
165 else
166 {
167 return false;
168 }
169 }
170
172 status_t flexspi_configure_dll(uint32_t instance, flexspi_mem_config_t *config)
173 {
174 status_t status = kStatus_InvalidArgument;
175 bool mdisConfigRequired;
176
177 do
178 {
179 FLEXSPI_Type *base = flexspi_get_module_base(instance);
180 bool isUnifiedConfig = true;
181 uint32_t flexspiRootClk;
182 uint32_t flexspiDll[2];
183 uint32_t dllValue;
184 uint32_t temp;
185
186 if ((base == NULL) || (config == NULL) ||
187 (config->readSampleClkSrc > kFlexSPIReadSampleClk_ExternalInputFromDqsPad))
188 {
189 break;
190 }
191
192 switch (config->readSampleClkSrc)
193 {
194 case kFlexSPIReadSampleClk_LoopbackInternally:
195 case kFlexSPIReadSampleClk_LoopbackFromDqsPad:
196 case kFlexSPIReadSampleClk_LoopbackFromSckPad:
197 isUnifiedConfig = true;
198 break;
199 case kFlexSPIReadSampleClk_ExternalInputFromDqsPad:
200 if (flexspi_is_ck2_enabled(config))
201 {
202 isUnifiedConfig = true;
203 }
204 else
205 {
206 isUnifiedConfig = false;
207 }
208 break;
209 default: // Never reach here
210 break;
211 }
212
213 if (isUnifiedConfig)
214 {
215 flexspiDll[0] = FLEXSPI_DLLCR_DEFAULT; // 1 fixed delay cells in DLL delay chain)
216 flexspiDll[1] = FLEXSPI_DLLCR_DEFAULT; // 1 fixed delay cells in DLL delay chain)
217 }
218 #if FLEXSPI_ENABLE_OCTAL_FLASH_SUPPORT
219 else
220 {
221 flexspi_get_clock(instance, kFlexSpiClock_SerialRootClock, &flexspiRootClk);
222
223 bool useDLL = false;
224
225 // See FlexSPI Chapter for more details
226 if ((flexspiRootClk >= 100 * FREQ_1MHz) &&
227 (!(config->controllerMiscOption & (1U << kFlexSpiMiscOffset_UseValidTimeForAllFreq))))
228 {
229 useDLL = true;
230 }
231 if (useDLL)
232 {
233 flexspiDll[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F);
234 flexspiDll[1] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F);
235 }
236 // If Serial root closk is lower than 100MHz, DLL is unable to lock on
237 // half cycle of serial root clock because the dealy cell number is limited
238 // in delay chain, Then DLL should be configured as following instead:
239 // OVRDEN = 0x01
240 // OVRDVAL=N; each dealy cell in DLL is about 75ps - 225ps.
241 // The delay of DLL delay chain ( N * delay_cell_delay) should be larger
242 // than device output data valid time (from SCK edge to data valid).
243 // The other condition is that some devices may be incompatible with current
244 // FlexSPI defintions, so, use a backup way to support it.
245 else
246 {
247 for (uint32_t i = 0; i < 2; i++)
248 {
249 uint32_t dataValidTimeH = config->dataValidTime[i].delay_cells;
250 uint32_t dataValidTimeL = config->dataValidTime[i].time_100ps;
251 if (dataValidTimeH < 1)
252 {
253 // Convert the data valid time to n ps.
254 temp = dataValidTimeL * 100ul;
255 if (temp < 1)
256 {
257 uint32_t maxFreq;
258 bool is_ddr_enabled = flexspi_is_ddr_mode_enable(config);
259 flexspi_get_max_supported_freq(instance, &maxFreq, is_ddr_enabled);
260 // For SDR mode, the delay cell configuration must ensure that the delay time is greater
261 // than
262 // Half cycle of max supported frequency
263 if (!is_ddr_enabled)
264 {
265 dllValue = FLEXSPI_FREQ_1GHz / maxFreq / 2 * 1000 / kFlexSpiDelayCellUnit_Min + 1;
266 }
267 // For SDR mode, the delay cell configuration must ensure that the delay time is greater
268 // than
269 // 1/4 cycle of max supported frequency
270 else
271 {
272 dllValue = FLEXSPI_FREQ_1GHz / maxFreq / 4 * 1000 / kFlexSpiDelayCellUnit_Min + 1;
273 }
274 }
275 else
276 {
277 dllValue = temp / kFlexSpiDelayCellUnit_Min;
278 if (dllValue * kFlexSpiDelayCellUnit_Min < temp)
279 {
280 dllValue++;
281 }
282 }
283 }
284 else
285 {
286 dllValue = dataValidTimeH;
287 }
288 // Calculate maximum dll value;
289 temp = (FLEXSPI_DLLCR_OVRDVAL_MASK >> FLEXSPI_DLLCR_OVRDVAL_SHIFT);
290 if (dllValue > temp)
291 {
292 dllValue = temp;
293 }
294 flexspiDll[i] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(dllValue);
295 }
296 }
297 }
298 #endif // FLEXSPI_ENABLE_OCTAL_FLASH_SUPPORT
299
300 if (base->MCR0 & FLEXSPI_MCR0_MDIS_MASK)
301 {
302 mdisConfigRequired = false;
303 }
304 else
305 {
306 mdisConfigRequired = true;
307 }
308
309 if (mdisConfigRequired)
310 {
311 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
312 }
313
314 if (config->sflashA1Size || config->sflashA2Size)
315 {
316 base->DLLCR[0] = flexspiDll[0];
317 }
318 if (config->sflashB1Size || config->sflashB2Size)
319 {
320 base->DLLCR[1] = flexspiDll[1];
321 }
322
323 if (mdisConfigRequired)
324 {
325 base->MCR0 &= (uint32_t)~FLEXSPI_MCR0_MDIS_MASK;
326 }
327
328 status = kStatus_Success;
329 } while (0);
330
331 return status;
332 }
333
334 // Calculate ticks for the timeout interms of specified unit.
335 status_t flexspi_get_ticks(uint32_t *ticks, uint32_t intervalNs, uint32_t freq, uint32_t unit)
336 {
337 status_t status = kStatus_InvalidArgument;
338 do
339 {
340 if ((ticks == NULL) || (freq < 1) || (unit < 1))
341 {
342 break;
343 }
344
345 // Get clock cycle in terms of ns
346 int32_t calculatedTicks;
347 uint32_t cycleNs = FLEXSPI_FREQ_1GHz / freq;
348
349 calculatedTicks = intervalNs / (cycleNs * unit);
350 while (calculatedTicks * cycleNs * unit < intervalNs)
351 {
352 calculatedTicks++;
353 }
354
355 *ticks = calculatedTicks;
356
357 status = kStatus_Success;
358
359 } while (0);
360
361 return status;
362 }
363
364 status_t flexspi_config_mcr1(uint32_t instance, flexspi_mem_config_t *config)
365 {
366 uint32_t seqWaitTicks = 0xFFFFu;
367 uint32_t ahbBusWaitTicks = 0xFFFFu;
368 uint32_t serialRootClockFreq;
369 uint32_t ahbBusClockFreq;
370 FLEXSPI_Type *base = flexspi_get_module_base(instance);
371
372 if ((base == NULL) || (config == NULL))
373 {
374 return kStatus_InvalidArgument;
375 }
376
377 flexspi_get_clock(instance, kFlexSpiClock_SerialRootClock, &serialRootClockFreq);
378 flexspi_get_clock(instance, kFlexSpiClock_AhbClock, &ahbBusClockFreq);
379 flexspi_get_ticks(&seqWaitTicks, FLEXSPI_WAIT_TIMEOUT_NS, serialRootClockFreq, 1024);
380 flexspi_get_ticks(&ahbBusWaitTicks, FLEXSPI_WAIT_TIMEOUT_NS, ahbBusClockFreq, 1024);
381
382 if (seqWaitTicks > 0xFFFF)
383 {
384 seqWaitTicks = 0xFFFF;
385 }
386 if (ahbBusWaitTicks > 0xFFFF)
387 {
388 ahbBusWaitTicks = 0xFFFF;
389 }
390
391 // Configure MCR1
392 base->MCR1 = FLEXSPI_MCR1_SEQWAIT(seqWaitTicks) | FLEXSPI_MCR1_AHBBUSWAIT(ahbBusWaitTicks);
393
394 return kStatus_Success;
395 }
396
397 static void flexspi_clear_ip_txfifo(FLEXSPI_Type *base)
398 {
399 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
400 while (base->IPTXFCR & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
401 {
402 }
403 }
404
405 static void flexspi_clear_ip_rxfifo(FLEXSPI_Type *base)
406 {
407 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
408 while (base->IPRXFCR & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
409 {
410 }
411 }
412
413 static void flexspi_wait_until_ip_idle(FLEXSPI_Type *base)
414 {
415 while ((base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != FLEXSPI_STS0_SEQIDLE_MASK)
416 {
417 }
418 while ((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != FLEXSPI_STS0_ARBIDLE_MASK)
419 {
420 }
421 }
422
423 static FLEXSPI_Type *flexspi_get_module_base(uint32_t instance)
424 {
425 FLEXSPI_Type *baseAddr = NULL;
426 if (instance < sizeof(g_flexSpiInstances) / sizeof(g_flexSpiInstances[0]))
427 {
428 baseAddr = g_flexSpiInstances[instance];
429 }
430 return baseAddr;
431 }
432
433 void flexspi_clear_error_status(FLEXSPI_Type *base)
434 {
435 base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
436 FLEXSPI_INTR_IPCMDGE_MASK;
437 }
438
439 status_t flexspi_config_flash_control_registers(uint32_t instance, flexspi_mem_config_t *config)
440 {
441 status_t status = kStatus_InvalidArgument;
442
443 do
444 {
445 uint32_t index;
446 uint32_t flashSize;
447 uint32_t temp;
448 uint32_t serialClockFrequency;
449 uint32_t csIntervalTicks = 0;
450
451 FLEXSPI_Type *base = flexspi_get_module_base(instance);
452 if ((base == NULL) || (config == NULL))
453 {
454 break;
455 }
456
457 uint32_t *flashSizeStart = (uint32_t *)&config->sflashA1Size;
458
459 for (index = 0; index < FLEXSPI_FLSHCR0_COUNT; index++)
460 {
461 // Configure FLSHCR0
462 flashSize = *flashSizeStart++;
463 base->FLSHCR0[index] = flashSize / 1024;
464
465 // Configure FLSHCR1
466 temp = FLEXSPI_FLSHCR1_TCSS(config->csSetupTime) | FLEXSPI_FLSHCR1_TCSH(config->csHoldTime) |
467 FLEXSPI_FLSHCR1_CAS(config->columnAddressWidth);
468 if (flexspi_is_word_addressable(config))
469 {
470 temp |= FLEXSPI_FLSHCR1_WA_MASK;
471 }
472 // Calculate CS interval
473 if (config->commandInterval)
474 {
475 flexspi_get_clock(instance, kFlexSpiClock_SerialRootClock, &serialClockFrequency);
476 flexspi_get_ticks(&csIntervalTicks, config->commandInterval, serialClockFrequency, 1);
477
478 temp |= FLEXSPI_FLSHCR1_CSINTERVAL(csIntervalTicks);
479 }
480 base->FLSHCR1[index] = temp;
481
482 // Configure FLSHCR2
483 temp = FLEXSPI_FLSHCR2_ARDSEQID(CMD_LUT_SEQ_IDX_READ);
484
485 if (config->lutCustomSeqEnable && FLEXSPI_FLSHCR2_ARDSEQNUM(config->lutCustomSeq[CMD_INDEX_WRITE].seqNum))
486 {
487 temp |= FLEXSPI_FLSHCR2_AWRSEQID(config->lutCustomSeq[CMD_INDEX_WRITE].seqId);
488 temp |= FLEXSPI_FLSHCR2_AWRSEQNUM(config->lutCustomSeq[CMD_INDEX_WRITE].seqNum - 1);
489 }
490 else
491 {
492 temp |= FLEXSPI_FLSHCR2_AWRSEQID(CMD_LUT_SEQ_IDX_WRITE);
493 }
494 base->FLSHCR2[index] = temp;
495 }
496
497 status = kStatus_Success;
498
499 } while (0);
500
501 return status;
502 }
503
504 status_t flexspi_config_ahb_buffers(FLEXSPI_Type *base, flexspi_mem_config_t *config)
505 {
506 uint32_t temp;
507 uint32_t index;
508 status_t status = kStatus_InvalidArgument;
509
510 do
511 {
512 if ((base == NULL) || (config == NULL))
513 {
514 break;
515 }
516
517 if (config->deviceType == kFlexSpiDeviceType_SerialNOR)
518 {
519 // Configure AHBCR
520 temp = base->AHBCR & (~FLEXSPI_AHBCR_APAREN_MASK);
521 // Remove alignment limitation when Flash device works under DDR mode.
522 temp |= FLEXSPI_AHBCR_READADDROPT_MASK;
523 #if FLEXSPI_FEATURE_HAS_PARALLEL_MODE
524 if (flexspi_is_parallel_mode(config))
525 {
526 temp |= FLEXSPI_AHBCR_APAREN_MASK;
527 }
528 #endif // FLEXSPI_FEATURE_HAS_PARALLEL_MODE
529 base->AHBCR = temp;
530 }
531 // Enable prefetch feature
532 base->AHBCR |= FLEXSPI_AHBCR_PREFETCHEN_MASK;
533
534 // Configure AHB RX buffer
535 for (index = 0; index < FLEXSPI_AHBRXBUFCR0_COUNT - 1; index++)
536 {
537 base->AHBRXBUFCR0[index] &=
538 ~(FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK);
539 }
540 status = kStatus_Success;
541
542 } while (0);
543
544 return status;
545 }
546
547 status_t flexspi_device_write_enable(uint32_t instance,
548 flexspi_mem_config_t *config,
549 bool isParallelMode,
550 uint32_t baseAddr)
551 {
552 status_t status = kStatus_InvalidArgument;
553 do
554 {
555 if (config == NULL)
556 {
557 break;
558 }
559 flexspi_xfer_t flashXfer;
560 flashXfer.operation = kFlexSpiOperation_Command;
561 flashXfer.seqNum = 1;
562 flashXfer.seqId = CMD_LUT_SEQ_IDX_WRITEENABLE;
563 #if FLEXSPI_FEATURE_HAS_PARALLEL_MODE
564 flashXfer.isParallelModeEnable = isParallelMode;
565 #else
566 flashXfer.isParallelModeEnable = false;
567 #endif // FLEXSPI_FEATURE_HAS_PARALLEL_MODE
568 flashXfer.baseAddress = baseAddr;
569
570 if (config->lutCustomSeqEnable && config->lutCustomSeq[CMD_INDEX_WRITEENABLE].seqNum)
571 {
572 flashXfer.seqId = config->lutCustomSeq[CMD_INDEX_WRITEENABLE].seqId;
573 flashXfer.seqNum = config->lutCustomSeq[CMD_INDEX_WRITEENABLE].seqNum;
574 }
575 flexspi_update_lut(instance, CMD_LUT_FOR_IP_CMD, &config->lookupTable[4 * flashXfer.seqId], flashXfer.seqNum);
576 flashXfer.seqId = CMD_LUT_FOR_IP_CMD;
577 status = flexspi_command_xfer(instance, &flashXfer);
578
579 } while (0);
580
581 return status;
582 }
583
584 status_t flexspi_device_workmode_config(uint32_t instance, flexspi_mem_config_t *config, uint32_t baseAddr)
585 {
586 status_t status = kStatus_InvalidArgument;
587
588 do
589 {
590 FLEXSPI_Type *base = flexspi_get_module_base(instance);
591 if ((base == NULL) || (config == NULL))
592 {
593 break;
594 }
595
596 // If device is working under DPI/QPI/OPI mode, ignore SPI2XPI command
597 uint32_t read_cmd_pads = (base->LUT[0] >> 8) & 0x03;
598 if ((read_cmd_pads > FLEXSPI_1PAD) && (config->deviceModeType == kDeviceConfigCmdType_Spi2Xpi))
599 {
600 status = kStatus_Success;
601 break;
602 }
603
604 flexspi_xfer_t flashXfer;
605 flashXfer.operation = kFlexSpiOperation_Config;
606 flashXfer.baseAddress = baseAddr;
607 flashXfer.seqId = config->deviceModeSeq.seqId;
608 flashXfer.seqNum = config->deviceModeSeq.seqNum;
609 flashXfer.isParallelModeEnable = false;
610 flashXfer.txBuffer = &config->deviceModeArg;
611 flashXfer.txSize = 4;
612
613 flexspi_device_write_enable(instance, config, false, baseAddr);
614 // Update LUT 1 for device mode config command
615 flexspi_update_lut(instance, CMD_LUT_FOR_IP_CMD, &config->lookupTable[4 * flashXfer.seqId], flashXfer.seqNum);
616 flashXfer.seqId = CMD_LUT_FOR_IP_CMD;
617 status = flexspi_command_xfer(instance, &flashXfer);
618 if (status != kStatus_Success)
619 {
620 break;
621 }
622 if ((!config->waitTimeCfgCommands) && (config->deviceModeType != (uint8_t)kDeviceConfigCmdType_Spi2Xpi) &&
623 (config->deviceModeType != (uint8_t)kDeviceConfigCmdType_Xpi2Spi))
624 {
625 status = flexspi_device_wait_busy(instance, config, false, baseAddr);
626 }
627 else
628 {
629 flexspi_sw_delay_us(config->waitTimeCfgCommands * 100UL);
630 }
631 } while (0);
632
633 return status;
634 }
635 status_t flexspi_device_workmode_config_all_chips(uint32_t instance, flexspi_mem_config_t *config)
636 {
637 status_t status = kStatus_InvalidArgument;
638
639 do
640 {
641 if (config == NULL)
642 {
643 break;
644 }
645 uint32_t baseAddr = 0;
646 uint32_t index;
647 uint32_t currentFlashSize;
648 uint32_t *flashSizeStart = &config->sflashA1Size;
649
650 for (index = 0; index < 4; index++)
651 {
652 currentFlashSize = *flashSizeStart++;
653 if (currentFlashSize > 0)
654 {
655 status = flexspi_device_workmode_config(instance, config, baseAddr);
656 if (status != kStatus_Success)
657 {
658 break;
659 }
660 baseAddr += currentFlashSize;
661 }
662 }
663
664 } while (0);
665
666 return status;
667 }
668
669 status_t flexspi_device_cmd_config(uint32_t instance, flexspi_mem_config_t *config, uint32_t baseAddr)
670 {
671 status_t status = kStatus_InvalidArgument;
672
673 do
674 {
675 FLEXSPI_Type *base = flexspi_get_module_base(instance);
676 if ((base == NULL) || (config == NULL))
677 {
678 break;
679 }
680
681 flexspi_xfer_t flashXfer;
682 uint32_t index;
683 flashXfer.operation = kFlexSpiOperation_Config;
684 flashXfer.baseAddress = baseAddr;
685 flashXfer.isParallelModeEnable = false;
686 flashXfer.txSize = 4;
687
688 for (index = 0; index < 3; index++)
689 {
690 if (config->configCmdSeqs[index].seqId > 0)
691 {
692 // If device is working under DPI/QPI/OPI mode, ignore SPI2XPI command
693 uint32_t read_cmd_pads = (base->LUT[0] >> 8) & 0x03;
694 if ((read_cmd_pads > FLEXSPI_1PAD) && (config->configModeType[index] == kDeviceConfigCmdType_Spi2Xpi))
695 {
696 continue;
697 }
698
699 flashXfer.seqId = config->configCmdSeqs[index].seqId;
700 flashXfer.seqNum = config->configCmdSeqs[index].seqNum;
701 flashXfer.txBuffer = &config->configCmdArgs[index];
702
703 status = flexspi_device_write_enable(instance, config, false, baseAddr);
704 if (status != kStatus_Success)
705 {
706 return status;
707 }
708
709 flexspi_update_lut(instance, CMD_LUT_FOR_IP_CMD, &config->lookupTable[4 * flashXfer.seqId],
710 flashXfer.seqNum);
711 flashXfer.seqId = CMD_LUT_FOR_IP_CMD;
712 status = flexspi_command_xfer(instance, &flashXfer);
713 if (status != kStatus_Success)
714 {
715 return status;
716 }
717
718 if ((!config->waitTimeCfgCommands) &&
719 (config->configModeType[index] != (uint8_t)kDeviceConfigCmdType_Spi2Xpi) &&
720 (config->configModeType[index] != (uint8_t)kDeviceConfigCmdType_Xpi2Spi))
721 {
722 status = flexspi_device_wait_busy(instance, config, false, baseAddr);
723
724 if (status != kStatus_Success)
725 {
726 return status;
727 }
728 }
729 else
730 {
731 flexspi_sw_delay_us(config->waitTimeCfgCommands * 100UL);
732 }
733 }
734 }
735 } while (0);
736
737 return status;
738 }
739
740 status_t flexspi_device_cmd_config_all_chips(uint32_t instance, flexspi_mem_config_t *config)
741 {
742 status_t status = kStatus_InvalidArgument;
743
744 do
745 {
746 if (config == NULL)
747 {
748 break;
749 }
750 uint32_t baseAddr = 0;
751 uint32_t index;
752 uint32_t currentFlashSize;
753 uint32_t *flashSizeStart = &config->sflashA1Size;
754
755 for (index = 0; index < 4; index++)
756 {
757 currentFlashSize = *flashSizeStart++;
758 if (currentFlashSize > 0)
759 {
760 status = flexspi_device_cmd_config(instance, config, baseAddr);
761 if (status != kStatus_Success)
762 {
763 break;
764 }
765 baseAddr += currentFlashSize;
766 }
767 }
768 } while (0);
769
770 return status;
771 }
772
773 status_t flexspi_init(uint32_t instance, flexspi_mem_config_t *config)
774 {
775 uint32_t mcr0;
776 status_t status = kStatus_InvalidArgument;
777
778 do
779 {
780 FLEXSPI_Type *base = flexspi_get_module_base(instance);
781
782 if ((base == NULL) || (config == NULL))
783 {
784 break;
785 }
786
787 /* Determine if the flexspi serial clock should be configured to safe frequency
788 *
789 * ROM configures the FlexSPI Serial clock to 30MHz if one of below case is met:
790 * 1. ROM is required to configure external device to certain modes at safe frequency
791 */
792 bool need_safe_freq = (config->deviceModeCfgEnable || config->configCmdEnable) &&
793 ((config->controllerMiscOption & (1 << kFlexSpiMiscOffset_SafeConfigFreqEnable)));
794
795 if (config->tag != FLEXSPI_CFG_BLK_TAG)
796 {
797 break;
798 }
799
800 /*
801 * !!! Important !!!
802 * The module clock must be disabled during clock switch in order to avoid glitch
803 */
804 flexspi_clock_gate_disable(instance);
805 flexspi_iomux_config(instance, config);
806 if (need_safe_freq)
807 {
808 // Configure FlexSPI serial clock using safe frequency
809 flexspi_clock_config(instance, kFlexSpiSerialClk_SafeFreq, kFlexSpiClk_SDR);
810 }
811 else
812 {
813 // Configure FlexSPI serial clock with specified frequency
814 flexspi_clock_config(instance, config->serialClkFreq, flexspi_is_ddr_mode_enable(config));
815 }
816 // Enable FlexSPI Clock Gate
817 flexspi_clock_gate_enable(instance);
818
819 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
820 flexspi_swreset(base);
821
822 // Disable FlexSPI module during configuring control registers.
823 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
824
825 // Set Clock divider and sample clock source
826 mcr0 = base->MCR0 & (uint32_t) ~(FLEXSPI_MCR0_RXCLKSRC_MASK | FLEXSPI_MCR0_IPGRANTWAIT_MASK |
827 FLEXSPI_MCR0_AHBGRANTWAIT_MASK | FLEXSPI_MCR0_COMBINATIONEN_MASK |
828 FLEXSPI_MCR0_ATDFEN_MASK | FLEXSPI_MCR0_ARDFEN_MASK);
829
830 #if FLEXSPI_HAS_NO_CMD_MODE_SUPPORT
831 // If this condition meets, it means FlexSPI PORT B exists, the the 8 bit is supported by combining PORTA[3:0]
832 // with PORTB[3:0]
833 if ((sizeof(base->FLSHCR1) / sizeof(base->FLSHCR1[0])) > 2)
834 {
835 // Enable Combined mode if Serial FLASH works using Octal pad instructions.
836 if (config->sflashPadType == kSerialFlash_8Pads)
837 {
838 mcr0 |= FLEXSPI_MCR0_COMBINATIONEN_MASK;
839 }
840 }
841 #endif
842
843 // Configure AHBGRANTWAIT and IPGRANTWAIT
844 mcr0 |= FLEXSPI_MCR0_IPGRANTWAIT_MASK | FLEXSPI_MCR0_AHBGRANTWAIT_MASK;
845 // Configure Read sample clock source
846 mcr0 |= FLEXSPI_MCR0_RXCLKSRC(config->readSampleClkSrc);
847 base->MCR0 = mcr0;
848
849 #if FLEXSPI_HAS_NO_CMD_MODE_SUPPORT
850 // Configure MCR1
851 flexspi_config_mcr1(instance, config);
852 #endif
853
854 // Configure MCR2
855 base->MCR2 &= ~FLEXSPI_MCR2_SAMEDEVICEEN_MASK;
856
857 #if FLEXSPI_HAS_NO_CMD_MODE_SUPPORT
858 // If this condition meets, it means FlexSPI PORT B exists, SCKB pads used as PORTB SCK with be used a inverted
859 // SCK for PORTA
860 // Enable differential clock as needed.
861 if ((sizeof(base->FLSHCR1) / sizeof(base->FLSHCR1[0])) > 2)
862 {
863 if (flexspi_is_differential_clock_enable(config))
864 {
865 base->MCR2 |= FLEXSPI_MCR2_SCKBDIFFOPT_MASK;
866 }
867 }
868 #endif
869
870 // Configure AHB buffer
871 flexspi_config_ahb_buffers(base, config);
872
873 // Configure Flash related control registers
874 flexspi_config_flash_control_registers(instance, config);
875
876 // Configure DLLCR
877 flexspi_configure_dll(instance, config);
878
879 // Enable FlexSPI before updating LUT.
880 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
881
882 // Reset all registers except control registers
883 flexspi_swreset(base);
884
885 if (config->deviceModeCfgEnable)
886 {
887 status = flexspi_device_workmode_config_all_chips(instance, config);
888 if (status != kStatus_Success)
889 {
890 break;
891 }
892 }
893
894 if (config->configCmdEnable)
895 {
896 status = flexspi_device_cmd_config_all_chips(instance, config);
897 if (status != kStatus_Success)
898 {
899 break;
900 }
901 }
902
903 // Restore clock
904 if (need_safe_freq)
905 {
906 /*
907 * !!! Important !!!
908 * The module clock must be disabled during clock switch in order to avoid glitch
909 */
910 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
911 // Re-configure FlexSPI Serial clock frequency in order to acheive high performance.
912 flexspi_clock_config(instance, config->serialClkFreq, flexspi_is_ddr_mode_enable(config));
913
914 // Re-Configure MCR1
915 flexspi_config_mcr1(instance, config);
916 // Re-configure DLLCR
917 flexspi_configure_dll(instance, config);
918 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
919 }
920
921 status = kStatus_Success;
922
923 } while (0);
924
925 return status;
926 }
927
928 status_t flexspi_update_lut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber)
929 {
930 status_t status = kStatus_InvalidArgument;
931
932 do
933 {
934 FLEXSPI_Type *base = flexspi_get_module_base(instance);
935
936 if ((base == NULL) || (lutBase == NULL) || (((uint64_t)seqIndex + seqNumber) > 16))
937 {
938 break;
939 }
940
941 flexspi_wait_until_ip_idle(base);
942
943 uint32_t start_index = 0;
944 uint32_t end_index = 0;
945 volatile uint32_t *flexspiLutPtr;
946
947 flexspi_unlock_lut(base);
948
949 start_index = 4 * seqIndex;
950 end_index = 4 * (seqIndex + seqNumber);
951 flexspiLutPtr = &base->LUT[start_index];
952 while (start_index < end_index)
953 {
954 *flexspiLutPtr = *lutBase;
955 start_index++;
956 flexspiLutPtr++;
957 lutBase++;
958 }
959
960 flexspi_lock_lut(base);
961
962 status = kStatus_Success;
963
964 } while (0);
965
966 return status;
967 }
968
969 status_t flexspi_command_xfer(uint32_t instance, flexspi_xfer_t *xfer)
970 {
971 status_t status = kStatus_InvalidArgument;
972 FLEXSPI_Type *base = flexspi_get_module_base(instance);
973
974 do
975 {
976 if ((base == NULL) || (xfer == NULL) || (xfer->operation > kFlexSpiOperation_End))
977 {
978 break;
979 }
980
981 uint32_t temp = 0;
982 #if !FLEXSPI_FEATURE_HAS_PARALLEL_MODE
983 bool isParallelMode = false;
984 #else
985 bool isParallelMode = xfer->isParallelModeEnable;
986 #endif // FLEXSPI_FEATURE_HAS_PARALLEL_MODE
987
988 flexspi_wait_until_ip_idle(base);
989
990 // Clear sequence pointer before sending data to external devices
991 flexspi_clear_sequence_pointer(instance);
992
993 // Clear former pending status before start this transfer.
994 flexspi_clear_error_status(base);
995
996 // Configure base address
997 base->IPCR0 = xfer->baseAddress;
998
999 if (xfer->operation == kFlexSpiOperation_Write)
1000 {
1001 temp = FLEXSPI_IPCR1_IDATSZ(xfer->txSize);
1002 }
1003
1004 if (xfer->operation == kFlexSpiOperation_Read)
1005 {
1006 temp = FLEXSPI_IPCR1_IDATSZ(xfer->rxSize);
1007 }
1008
1009 temp |= FLEXSPI_IPCR1_ISEQID(xfer->seqId) | FLEXSPI_IPCR1_ISEQNUM(xfer->seqNum - 1) |
1010 FLEXSPI_IPCR1_IPAREN((uint32_t)isParallelMode);
1011
1012 base->IPCR1 = temp;
1013
1014 if (xfer->operation == kFlexSpiOperation_Read)
1015 {
1016 register uint32_t xferRemainingSize = xfer->rxSize;
1017 register uint32_t *xferBufferPtr = xfer->rxBuffer;
1018 if ((size_t)xferBufferPtr & 0x03)
1019 {
1020 break;
1021 }
1022 // Set Half RX FIFO size as Watermark size
1023 uint32_t rx_fifo_size = sizeof(base->RFDR);
1024 uint32_t watermark = rx_fifo_size / 8 / 2;
1025 uint32_t burst_rx_size = rx_fifo_size / 2;
1026 base->IPRXFCR = FLEXSPI_IPRXFCR_RXWMRK(watermark - 1);
1027
1028 // Clear FIFO before read
1029 flexspi_clear_ip_rxfifo(base);
1030
1031 // Start Read
1032 base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
1033 while (xferRemainingSize > 0)
1034 {
1035 register volatile uint32_t *rx_fifo_reg = (volatile uint32_t *)&base->RFDR[0];
1036 if (xferRemainingSize >= burst_rx_size)
1037 {
1038 register uint32_t burst_rx_round = burst_rx_size / sizeof(uint32_t);
1039 // Make sure the RX FIFO contains valid data before read
1040 if (base->INTR & FLEXSPI_INTR_IPRXWA_MASK)
1041 {
1042 while (burst_rx_round--)
1043 {
1044 *xferBufferPtr++ = *rx_fifo_reg++;
1045 }
1046 xferRemainingSize -= burst_rx_size;
1047 // Pop up data to RXFIFO for next read.
1048 base->INTR |= FLEXSPI_INTR_IPRXWA_MASK;
1049 }
1050 }
1051 else if ((8 * ((base->IPRXFSTS & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT)) >=
1052 xferRemainingSize)
1053 {
1054 while (xferRemainingSize >= 4)
1055 {
1056 *xferBufferPtr++ = *rx_fifo_reg++;
1057 xferRemainingSize -= 4;
1058 }
1059 if (xferRemainingSize)
1060 {
1061 uint32_t buf = *rx_fifo_reg;
1062 uint8_t *src = (uint8_t *)&buf;
1063 uint8_t *dst = (uint8_t *)xferBufferPtr;
1064 for (uint32_t index = 0; index < xferRemainingSize; index++)
1065 {
1066 *dst++ = *src++;
1067 }
1068 }
1069 xferRemainingSize = 0;
1070 }
1071
1072 // Ensure no error occurs during read
1073 if ((base->INTR & FLEXSPI_INTR_IPCMDERR_MASK) != 0U)
1074 {
1075 break;
1076 }
1077 }
1078 }
1079
1080 if ((xfer->operation == kFlexSpiOperation_Write) || (xfer->operation == kFlexSpiOperation_Config))
1081 {
1082 register int32_t xferRemainingSize = (int32_t)xfer->txSize;
1083 register uint32_t *xferBufferPtr = xfer->txBuffer;
1084 // Enusre that the tx buffer is 4 words aligned for better performance
1085 if ((size_t)xferBufferPtr & 0x03)
1086 {
1087 break;
1088 }
1089
1090 // Set Half TX FIFO size as Watermark size
1091 uint32_t tx_fifo_size = sizeof(base->TFDR);
1092 uint32_t watermark = tx_fifo_size / 8 / 2;
1093 uint32_t burst_tx_size = tx_fifo_size / 2;
1094 base->IPTXFCR = FLEXSPI_IPTXFCR_TXWMRK(watermark - 1);
1095
1096 // Clear FIFO before write
1097 flexspi_clear_ip_txfifo(base);
1098
1099 bool is_transfer_started = false;
1100 while (xferRemainingSize > 0)
1101 {
1102 register volatile uint32_t *tx_fifo_reg = &base->TFDR[0];
1103 // Make sure the TXFIFO is not full before write
1104 if (base->INTR & FLEXSPI_INTR_IPTXWE_MASK)
1105 {
1106 register uint32_t burst_tx_round = burst_tx_size / sizeof(uint32_t);
1107 if (xferRemainingSize >= burst_tx_size)
1108 {
1109 while (burst_tx_round--)
1110 {
1111 *tx_fifo_reg++ = *xferBufferPtr++;
1112 }
1113 xferRemainingSize -= burst_tx_size;
1114 }
1115 else
1116 {
1117 while (burst_tx_round--)
1118 {
1119 if (xferRemainingSize > 0)
1120 {
1121 xferRemainingSize -= 4;
1122 *tx_fifo_reg++ = *xferBufferPtr++;
1123 }
1124 else
1125 {
1126 *tx_fifo_reg++ = 0x0;
1127 }
1128 }
1129 }
1130 if (!is_transfer_started)
1131 {
1132 base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
1133 is_transfer_started = true;
1134 }
1135
1136 base->INTR |= FLEXSPI_INTR_IPTXWE_MASK;
1137 }
1138
1139 // Ensure no error occurs during write
1140 if ((base->INTR & FLEXSPI_INTR_IPCMDERR_MASK) != 0U)
1141 {
1142 break;
1143 }
1144 }
1145 }
1146 if (xfer->operation == kFlexSpiOperation_Command)
1147 {
1148 base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
1149 }
1150
1151 flexspi_wait_until_ip_idle(base);
1152
1153 if (base->INTR & FLEXSPI_INTR_IPCMDERR_MASK)
1154 {
1155 switch ((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT)
1156 {
1157 default:
1158 status = kStatus_FLEXSPI_InvalidSequence;
1159 break;
1160 case kFlexSpiIpCmdError_SequenceExecutionTimeout:
1161 status = kStatus_FLEXSPI_SequenceExecutionTimeout;
1162 break;
1163 }
1164 }
1165 else
1166 {
1167 status = kStatus_Success;
1168 }
1169
1170 } while (0);
1171
1172 return status;
1173 }
1174
1175 void flexspi_wait_idle(uint32_t instance)
1176 {
1177 do
1178 {
1179 FLEXSPI_Type *base = flexspi_get_module_base(instance);
1180 if (base == NULL)
1181 {
1182 break;
1183 }
1184
1185 // Wait until FlexSPI controller becomes idle
1186 while (!(base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK))
1187 {
1188 }
1189
1190 } while (0);
1191 }
1192
1193 void flexspi_clear_cache(uint32_t instance)
1194 {
1195 do
1196 {
1197 FLEXSPI_Type *base = flexspi_get_module_base(instance);
1198 if (base == NULL)
1199 {
1200 break;
1201 }
1202
1203 flexspi_swreset(base);
1204
1205 } while (0);
1206 }
1207
1208 #if FLEXSPI_FEATURE_HAS_PARALLEL_MODE
1209 static status_t flexspi_extract_parallel_data(uint32_t *dst0, uint32_t *dst1, uint32_t *src, uint32_t length)
1210 {
1211 status_t status = kStatus_InvalidArgument;
1212
1213 do
1214 {
1215 uint8_t *dst0Byte = (uint8_t *)dst0;
1216 uint8_t *dst1Byte = (uint8_t *)dst1;
1217 uint8_t *srcByte = (uint8_t *)src;
1218 if ((length < 1) || (length & 1) || (dst0 == NULL) || (dst1 == NULL))
1219 {
1220 break;
1221 }
1222
1223 while (length > 0)
1224 {
1225 *dst0Byte++ = *srcByte++;
1226 *dst1Byte++ = *srcByte++;
1227 length -= 2;
1228 }
1229 status = kStatus_Success;
1230
1231 } while (0);
1232
1233 return status;
1234 }
1235 #endif // FLEXSPI_FEATURE_HAS_PARALLEL_MODE
1236
1237 status_t flexspi_device_wait_busy(uint32_t instance,
1238 flexspi_mem_config_t *config,
1239 bool isParallelMode,
1240 uint32_t baseAddr)
1241 {
1242 status_t status = kStatus_InvalidArgument;
1243
1244 do
1245 {
1246 if (config == NULL)
1247 {
1248 break;
1249 }
1250 uint32_t statusDataBuffer[2];
1251 uint32_t busyMask;
1252 uint32_t busyPolarity;
1253 bool isBusy = false;
1254 #if FLEXSPI_FEATURE_HAS_PARALLEL_MODE
1255 uint32_t status0, status1;
1256 #else
1257 isParallelMode = false;
1258 #endif // FLEXSPI_FEATURE_HAS_PARALLEL_MODE
1259 flexspi_xfer_t flashXfer;
1260
1261 busyMask = 1 << config->busyOffset;
1262 busyPolarity = config->busyBitPolarity;
1263
1264 flashXfer.baseAddress = baseAddr;
1265 flashXfer.operation = kFlexSpiOperation_Read;
1266 flashXfer.seqNum = 1;
1267 flashXfer.seqId = CMD_LUT_SEQ_IDX_READSTATUS;
1268 flashXfer.rxBuffer = &statusDataBuffer[0];
1269
1270 flashXfer.rxSize = isParallelMode ? sizeof(statusDataBuffer) : sizeof(statusDataBuffer[0]);
1271 flashXfer.isParallelModeEnable = isParallelMode;
1272
1273 if (config->lutCustomSeqEnable && config->lutCustomSeq[CMD_INDEX_READSTATUS].seqNum)
1274 {
1275 flashXfer.seqId = config->lutCustomSeq[CMD_INDEX_READSTATUS].seqId;
1276 flashXfer.seqNum = config->lutCustomSeq[CMD_INDEX_READSTATUS].seqNum;
1277 }
1278
1279 flexspi_update_lut(instance, flashXfer.seqId, &config->lookupTable[4 * flashXfer.seqId], flashXfer.seqNum);
1280
1281 bool enableTimeoutCheck = config->timeoutInMs ? true : false;
1282 uint64_t remainingMs = config->timeoutInMs;
1283
1284 do
1285 {
1286 status = flexspi_command_xfer(instance, &flashXfer);
1287 if (status != kStatus_Success)
1288 {
1289 break;
1290 }
1291 else
1292 {
1293 #if FLEXSPI_FEATURE_HAS_PARALLEL_MODE
1294 if (isParallelMode)
1295 {
1296 // Extract parallel data to serial data
1297 flexspi_extract_parallel_data(&status0, &status1, statusDataBuffer, sizeof(statusDataBuffer));
1298
1299 if (busyPolarity)
1300 {
1301 isBusy = ((~status0) & busyMask) | ((~status1) & busyMask);
1302 }
1303 else
1304 {
1305 isBusy = (status0 & busyMask) | (status1 & busyMask);
1306 }
1307 }
1308 else
1309 #endif // FLEXSPI_FEATURE_HAS_PARALLEL_MODE
1310 {
1311 // Busy bit is 0 if polarity is 1
1312 if (busyPolarity)
1313 {
1314 isBusy = (~statusDataBuffer[0]) & busyMask;
1315 }
1316 else
1317 {
1318 isBusy = statusDataBuffer[0] & busyMask;
1319 }
1320 }
1321 }
1322
1323 if (isBusy && enableTimeoutCheck)
1324 {
1325 if (remainingMs > 0)
1326 {
1327 flexspi_sw_delay_us(1000);
1328 remainingMs--;
1329 }
1330 else
1331 {
1332 status = kStatus_FLEXSPI_DeviceTimeout;
1333 break;
1334 }
1335 }
1336
1337 } while (isBusy);
1338
1339 } while (0);
1340
1341 return status;
1342 }
1343
1344 void flexspi_clear_sequence_pointer(uint32_t instance)
1345 {
1346 uint32_t index;
1347
1348 do
1349 {
1350 FLEXSPI_Type *base = flexspi_get_module_base(instance);
1351 if (base == NULL)
1352 {
1353 break;
1354 }
1355
1356 for (index = 0; index < FLEXSPI_FLSHCR2_COUNT; index++)
1357 {
1358 base->FLSHCR2[index] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
1359 }
1360
1361 } while (0);
1362 }
1363
1364 void flexspi_half_clock_control(uint32_t instance, uint32_t option)
1365 {
1366 do
1367 {
1368 FLEXSPI_Type *base = flexspi_get_module_base(instance);
1369
1370 if (base == NULL)
1371 {
1372 break;
1373 }
1374
1375 flexspi_wait_until_ip_idle(base);
1376
1377 if (option)
1378 {
1379 base->MCR0 |= FLEXSPI_MCR0_HSEN_MASK;
1380 }
1381 else
1382 {
1383 base->MCR0 &= (uint32_t)~FLEXSPI_MCR0_HSEN_MASK;
1384 }
1385
1386 } while (0);
1387 }
kDeviceConfigCmdType_Xpi2Spi
Switch from DPI/QPI/OPI to SPI mode.
Definition: fsl_flexspi.h:179
FLEXSPI_MCR0_ARDFEN_MASK
#define FLEXSPI_MCR0_ARDFEN_MASK
Definition: MIMXRT1062.h:19349
FLEXSPI_FLSHCR1_TCSH
#define FLEXSPI_FLSHCR1_TCSH(x)
Definition: MIMXRT1062.h:19694
_lut_sequence::seqNum
uint8_t seqNum
Sequence Number, valid number: 1-16.
Definition: fsl_flexspi.h:168
FLEXSPI_IPRXFCR_RXWMRK
#define FLEXSPI_IPRXFCR_RXWMRK(x)
Definition: MIMXRT1062.h:19865
NULL
#define NULL
Definition: bootloader_common.h:26
flexspi_device_workmode_config_all_chips
static status_t flexspi_device_workmode_config_all_chips(uint32_t instance, flexspi_mem_config_t *config)
Definition: fsl_flexspi.c:631
FLEXSPI_IPCMD_TRG_MASK
#define FLEXSPI_IPCMD_TRG_MASK
Definition: MIMXRT1062.h:19840
fsl_flexspi.h
FLEXSPI_CFG_BLK_TAG
#define FLEXSPI_CFG_BLK_TAG
Definition: fsl_flexspi.h:31
kFlexSpiMiscOffset_UseValidTimeForAllFreq
Bit for DLLCR settings under all modes.
Definition: fsl_flexspi.h:142
FLEXSPI_Type::FLSHCR1
__IO uint32_t FLSHCR1[4]
Definition: MIMXRT1062.h:19293
kFlexSpiClk_SDR
Clock configure for SDR mode.
Definition: fsl_flexspi.h:96
FLEXSPI_MCR1_AHBBUSWAIT
#define FLEXSPI_MCR1_AHBBUSWAIT(x)
Definition: MIMXRT1062.h:19409
FLEXSPI_FLSHCR2_ARDSEQID
#define FLEXSPI_FLSHCR2_ARDSEQID(x)
Definition: MIMXRT1062.h:19731
flexspi_configure_dll
status_t flexspi_configure_dll(uint32_t instance, flexspi_mem_config_t *config)
Configure DLL register.
Definition: fsl_flexspi.c:168
FLEXSPI_FLSHCR2_ARDSEQNUM
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x)
Definition: MIMXRT1062.h:19736
FLEXSPI_Type::FLSHCR2
__IO uint32_t FLSHCR2[4]
Definition: MIMXRT1062.h:19294
kFlexSpiMiscOffset_WordAddressableEnable
Bit for Word Addressable enable.
Definition: fsl_flexspi.h:138
FLEXSPI_IPCR1_ISEQID
#define FLEXSPI_IPCR1_ISEQID(x)
Definition: MIMXRT1062.h:19823
FLEXSPI_DLLCR_OVRDVAL
#define FLEXSPI_DLLCR_OVRDVAL(x)
Definition: MIMXRT1062.h:19918
CMD_LUT_SEQ_IDX_WRITEENABLE
#define CMD_LUT_SEQ_IDX_WRITEENABLE
Definition: fsl_flexspi.h:46
_FlexSPIConfig::deviceModeArg
uint32_t deviceModeArg
sequence number, [31:16] Reserved
Definition: fsl_flexspi.h:208
_FlexSPIConfig::timeoutInMs
uint32_t timeoutInMs
[0x070-0x073] Timeout threshold for read status command
Definition: fsl_flexspi.h:233
kFlexSpiOperation_Write
TX FIFO size is fixed in LUT.
Definition: fsl_flexspi.h:250
_FlexSPIConfig::configModeType
uint8_t configModeType[3]
[0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
Definition: fsl_flexspi.h:210
FLEXSPI_MCR0_IPGRANTWAIT_MASK
#define FLEXSPI_MCR0_IPGRANTWAIT_MASK
Definition: MIMXRT1062.h:19393
FLEXSPI_Type::DLLCR
__IO uint32_t DLLCR[2]
Definition: MIMXRT1062.h:19305
_FlexSPIConfig::tag
uint32_t tag
[0x000-0x003] Tag, fixed value 0x42464346UL
Definition: fsl_flexspi.h:193
FLEXSPI_FLSHCR1_TCSS
#define FLEXSPI_FLSHCR1_TCSS(x)
Definition: MIMXRT1062.h:19689
FLEXSPI_FLSHCR0_COUNT
#define FLEXSPI_FLSHCR0_COUNT
Definition: MIMXRT1062.h:19681
kFlexSPIReadSampleClk_LoopbackFromDqsPad
Definition: fsl_flexspi.h:104
flexspi_dll_time_t::delay_cells
uint8_t delay_cells
Definition: fsl_flexspi.h:187
flexspi_command_xfer
status_t flexspi_command_xfer(uint32_t instance, flexspi_xfer_t *xfer)
Perform FlexSPI command.
Definition: fsl_flexspi.c:965
FLEXSPI_FLSHCR1_CAS
#define FLEXSPI_FLSHCR1_CAS(x)
Definition: MIMXRT1062.h:19704
FLEXSPI_Type::AHBCR
__IO uint32_t AHBCR
Definition: MIMXRT1062.h:19285
FLEXSPI_FLSHCR1_WA_MASK
#define FLEXSPI_FLSHCR1_WA_MASK
Definition: MIMXRT1062.h:19695
_FlexSPIConfig::csSetupTime
uint8_t csSetupTime
[0x00e-0x00e] CS setup time, default value: 3
Definition: fsl_flexspi.h:198
FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK
Definition: MIMXRT1062.h:19646
_lut_sequence::seqId
uint8_t seqId
Sequence Index, valid number: 0-15.
Definition: fsl_flexspi.h:169
_FlexSPIConfig::dataValidTime
flexspi_dll_time_t dataValidTime[2]
[0x078-0x07b] CLK edge to data valid time for PORT A and PORT B
Definition: fsl_flexspi.h:235
_FlexSPIConfig::lookupTable
uint32_t lookupTable[64]
busy flag is 0 when flash device is busy
Definition: fsl_flexspi.h:239
kFlexSpiClock_AhbClock
AHB clock.
Definition: fsl_flexspi.h:275
kFlexSpiDeviceType_SerialNOR
Flash devices are Serial NOR.
Definition: fsl_flexspi.h:149
FREQ_1MHz
#define FREQ_1MHz
Definition: fsl_flexspi.c:21
FLEXSPI_FLSHCR2_AWRSEQID
#define FLEXSPI_FLSHCR2_AWRSEQID(x)
Definition: MIMXRT1062.h:19741
flexspi_device_cmd_config_all_chips
static status_t flexspi_device_cmd_config_all_chips(uint32_t instance, flexspi_mem_config_t *config)
Definition: fsl_flexspi.c:736
FLEXSPI_BASE_PTRS
#define FLEXSPI_BASE_PTRS
Definition: MIMXRT1062.h:20164
FLEXSPI_INTR_IPTXWE_MASK
#define FLEXSPI_INTR_IPTXWE_MASK
Definition: MIMXRT1062.h:19594
FLEXSPI_DLLCR_OVRDEN
#define FLEXSPI_DLLCR_OVRDEN(x)
Definition: MIMXRT1062.h:19913
kFlexSpiDelayCellUnit_Min
Definition: fsl_flexspi.c:31
kFlexSpiOperation_Config
RX buffer are ignored.
Definition: fsl_flexspi.h:248
flexspi_is_padsetting_override_enable
bool flexspi_is_padsetting_override_enable(flexspi_mem_config_t *config)
Check whether Pad Setting Override feature is enabled.
Definition: fsl_flexspi.c:107
FLEXSPI_Type::LUTKEY
__IO uint32_t LUTKEY
Definition: MIMXRT1062.h:19288
kSerialFlash_8Pads
Definition: fsl_flexspi.h:162
flexspi_clear_cache
void flexspi_clear_cache(uint32_t instance)
Clear FlexSPI cache.
Definition: fsl_flexspi.c:1189
flexspi_config_flash_control_registers
status_t flexspi_config_flash_control_registers(uint32_t instance, flexspi_mem_config_t *config)
Definition: fsl_flexspi.c:435
_FlexSpiXfer::baseAddress
uint32_t baseAddress
FlexSPI operation base address.
Definition: fsl_flexspi.h:261
flexspi_lock_lut
static void flexspi_lock_lut(FLEXSPI_Type *base)
Lock LUT.
Definition: fsl_flexspi.c:89
kFlexSpiSerialClk_SafeFreq
Definition: fsl_flexspi.h:90
_FlexSPIConfig::sflashA2Size
uint32_t sflashA2Size
[0x054-0x057] Size of Flash connected to A2
Definition: fsl_flexspi.h:226
_FlexSpiXfer::seqId
uint32_t seqId
Sequence Id.
Definition: fsl_flexspi.h:262
FLEXSPI_Type::IPRXFSTS
__I uint32_t IPRXFSTS
Definition: MIMXRT1062.h:19311
_FlexSpiXfer
FlexSPI Transfer Context.
Definition: fsl_flexspi.h:258
FLEXSPI_INTR_AHBCMDERR_MASK
#define FLEXSPI_INTR_AHBCMDERR_MASK
Definition: MIMXRT1062.h:19583
FLEXSPI_Type::IPRXFCR
__IO uint32_t IPRXFCR
Definition: MIMXRT1062.h:19303
FLEXSPI_MCR0_SWRESET_MASK
#define FLEXSPI_MCR0_SWRESET_MASK
Definition: MIMXRT1062.h:19330
FLEXSPI_INTR_IPCMDGE_MASK
#define FLEXSPI_INTR_IPCMDGE_MASK
Definition: MIMXRT1062.h:19567
flexspi_extract_parallel_data
static status_t flexspi_extract_parallel_data(uint32_t *dst0, uint32_t *dst1, uint32_t *src, uint32_t length)
Extract received data under parallel mode.
Definition: fsl_flexspi.c:1205
kFlexSpiMiscOffset_PadSettingOverrideEnable
Bit for Pad setting override enable.
Definition: fsl_flexspi.h:140
FLEXSPI_STS1_IPCMDERRCODE_SHIFT
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT
Definition: MIMXRT1062.h:19979
kFlexSpiDelayCellUnit_Max
Definition: fsl_flexspi.c:32
i
volatile int i
Definition: excep_test.c:17
FLEXSPI_MCR2_SCKBDIFFOPT_MASK
#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK
Definition: MIMXRT1062.h:19443
FLEXSPI_Type::IPCR0
__IO uint32_t IPCR0
Definition: MIMXRT1062.h:19298
FLEXSPI_Type::AHBRXBUFCR0
__IO uint32_t AHBRXBUFCR0[4]
Definition: MIMXRT1062.h:19290
FLEXSPI_Type
Definition: MIMXRT1062.h:19281
_FlexSpiXfer::operation
flexspi_operation_t operation
FlexSPI operation.
Definition: fsl_flexspi.h:260
flexspi_is_differential_clock_enable
bool flexspi_is_differential_clock_enable(flexspi_mem_config_t *config)
Check whether Differential clock feature is enabled.
Definition: fsl_flexspi.c:119
flexspi_swreset
static void flexspi_swreset(FLEXSPI_Type *base)
Reset internal logical of FlexSPI.
Definition: fsl_flexspi.c:75
FLEXSPI_WAIT_TIMEOUT_NS
#define FLEXSPI_WAIT_TIMEOUT_NS
FlexSPI timeout value, 500ms.
Definition: fsl_flexspi.c:18
flexspi_clock_config
void flexspi_clock_config(uint32_t instance, uint32_t freq, uint32_t sampleClkMode)
Configure Clock for FlexSPI.
flexspi_is_ck2_enabled
bool flexspi_is_ck2_enabled(flexspi_mem_config_t *config)
Check whether CK2 feature is enabled.
Definition: fsl_flexspi.c:143
CMD_LUT_SEQ_IDX_READSTATUS
#define CMD_LUT_SEQ_IDX_READSTATUS
Definition: fsl_flexspi.h:45
kFlexSPIReadSampleClk_LoopbackInternally
Definition: fsl_flexspi.h:103
kFlexSpiOperation_Read
effective
Definition: fsl_flexspi.h:252
FLEXSPI_STS0_ARBIDLE_MASK
#define FLEXSPI_STS0_ARBIDLE_MASK
Definition: MIMXRT1062.h:19932
_FlexSPIConfig::csHoldTime
uint8_t csHoldTime
[0x00d-0x00d] CS hold time, default value: 3
Definition: fsl_flexspi.h:197
FLEXSPI_AHBRXBUFCR0_COUNT
#define FLEXSPI_AHBRXBUFCR0_COUNT
Definition: MIMXRT1062.h:19669
FLEXSPI_BITMASK
#define FLEXSPI_BITMASK(bit_offset)
Generate bit mask.
Definition: fsl_flexspi.h:281
flexspi_device_write_enable
status_t flexspi_device_write_enable(uint32_t instance, flexspi_mem_config_t *config, bool isParallelMode, uint32_t baseAddr)
Send Write enable command to Serial Memory device.
Definition: fsl_flexspi.c:543
FLEXSPI_AHBCR_PREFETCHEN_MASK
#define FLEXSPI_AHBCR_PREFETCHEN_MASK
Definition: MIMXRT1062.h:19485
fsl_device_registers.h
FLEXSPI_AHBCR_READADDROPT_MASK
#define FLEXSPI_AHBCR_READADDROPT_MASK
Definition: MIMXRT1062.h:19490
FLEXSPI_Type::STS0
__I uint32_t STS0
Definition: MIMXRT1062.h:19307
flexspi_init
status_t flexspi_init(uint32_t instance, flexspi_mem_config_t *config)
Initialize FlexSPI.
Definition: fsl_flexspi.c:769
FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK
Definition: MIMXRT1062.h:19656
_FlexSPIConfig::configCmdEnable
uint8_t configCmdEnable
[0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
Definition: fsl_flexspi.h:209
FLEXSPI_MCR0_RXCLKSRC_MASK
#define FLEXSPI_MCR0_RXCLKSRC_MASK
Definition: MIMXRT1062.h:19340
FLEXSPI_IPRXFSTS_FILL_SHIFT
#define FLEXSPI_IPRXFSTS_FILL_SHIFT
Definition: MIMXRT1062.h:20060
flexspi_update_lut
status_t flexspi_update_lut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber)
Configure FlexSPI Lookup table.
Definition: fsl_flexspi.c:924
flexspi_is_parallel_mode
bool flexspi_is_parallel_mode(flexspi_mem_config_t *config)
Check whether Parallel mode feature is enabled.
Definition: fsl_flexspi.c:95
kFlexSpiMiscOffset_DiffClkEnable
Bit for Differential clock enable.
Definition: fsl_flexspi.h:135
_FlexSPIConfig::readSampleClkSrc
uint8_t readSampleClkSrc
[0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
Definition: fsl_flexspi.h:196
flexspi_clear_ip_txfifo
static void flexspi_clear_ip_txfifo(FLEXSPI_Type *base)
Clear IP TXFIFO.
Definition: fsl_flexspi.c:393
flexspi_iomux_config
void flexspi_iomux_config(uint32_t instance, flexspi_mem_config_t *config)
Configure IOMUX for FlexSPI.
flexspi_clear_error_status
static void flexspi_clear_error_status(FLEXSPI_Type *base)
Clear FlexSPI error status.
Definition: fsl_flexspi.c:429
kFlexSpiMiscOffset_Ck2Enable
Bit for CK2 enable.
Definition: fsl_flexspi.h:136
_FlexSpiXfer::isParallelModeEnable
bool isParallelModeEnable
Is a parallel transfer.
Definition: fsl_flexspi.h:264
_FlexSPIConfig::busyOffset
uint16_t busyOffset
[0x07c-0x07d] Busy offset, valid value: 0-31
Definition: fsl_flexspi.h:236
_FlexSPIConfig::busyBitPolarity
uint16_t busyBitPolarity
Definition: fsl_flexspi.h:237
FLEXSPI_1PAD
#define FLEXSPI_1PAD
Definition: fsl_flexspi.h:78
_FlexSPIConfig::deviceType
uint8_t deviceType
details
Definition: fsl_flexspi.h:218
_FlexSPIConfig::configCmdArgs
uint32_t configCmdArgs[3]
[0x030-0x03b] Arguments/Parameters for device Configuration commands
Definition: fsl_flexspi.h:214
_FlexSPIConfig::deviceModeType
uint8_t deviceModeType
Definition: fsl_flexspi.h:202
FLEXSPI_AHBCR_APAREN_MASK
#define FLEXSPI_AHBCR_APAREN_MASK
Definition: MIMXRT1062.h:19461
FLEXSPI_Type::LUTCR
__IO uint32_t LUTCR
Definition: MIMXRT1062.h:19289
_FlexSPIConfig::sflashPadType
uint8_t sflashPadType
[0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
Definition: fsl_flexspi.h:219
FLEXSPI_MCR0_MDIS_MASK
#define FLEXSPI_MCR0_MDIS_MASK
Definition: MIMXRT1062.h:19335
FLEXSPI_Type::RFDR
__I uint32_t RFDR[32]
Definition: MIMXRT1062.h:19314
FLEXSPI_DLLCR_SLVDLYTARGET
#define FLEXSPI_DLLCR_SLVDLYTARGET(x)
Definition: MIMXRT1062.h:19908
FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK
Definition: MIMXRT1062.h:19763
FLEXSPI_Type::LUT
__IO uint32_t LUT[64]
Definition: MIMXRT1062.h:19316
FLEXSPI_DLLCR_DEFAULT
#define FLEXSPI_DLLCR_DEFAULT
Definition: fsl_flexspi.c:22
kStatus_FLEXSPI_InvalidSequence
Status for Invalid Sequence.
Definition: fsl_flexspi.h:128
flexspi_clock_gate_disable
void flexspi_clock_gate_disable(uint32_t instance)
Disable clock gate of FlexSPI.
flexspi_config_mcr1
status_t flexspi_config_mcr1(uint32_t instance, flexspi_mem_config_t *config)
Definition: fsl_flexspi.c:360
FLEXSPI_IPCR1_ISEQNUM
#define FLEXSPI_IPCR1_ISEQNUM(x)
Definition: MIMXRT1062.h:19828
FLEXSPI_Type::IPCR1
__IO uint32_t IPCR1
Definition: MIMXRT1062.h:19299
kFlexSPIReadSampleClk_LoopbackFromSckPad
Definition: fsl_flexspi.h:105
_FlexSPIConfig::deviceModeCfgEnable
uint8_t deviceModeCfgEnable
Serial NAND, need to refer to datasheet.
Definition: fsl_flexspi.h:201
FLEXSPI_IPTXFCR_CLRIPTXF_MASK
#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK
Definition: MIMXRT1062.h:19870
FLEXSPI_FLSHCR1_CSINTERVAL
#define FLEXSPI_FLSHCR1_CSINTERVAL(x)
Definition: MIMXRT1062.h:19719
kDeviceConfigCmdType_Spi2Xpi
Switch from SPI to DPI/QPI/OPI mode.
Definition: fsl_flexspi.h:178
FLEXSPI_FLSHCR2_COUNT
#define FLEXSPI_FLSHCR2_COUNT
Definition: MIMXRT1062.h:19772
_FlexSPIConfig::sflashB1Size
uint32_t sflashB1Size
[0x058-0x05b] Size of Flash connected to B1
Definition: fsl_flexspi.h:227
FLEXSPI_DLLCR_OVRDVAL_MASK
#define FLEXSPI_DLLCR_OVRDVAL_MASK
Definition: MIMXRT1062.h:19914
FLEXSPI_Type::TFDR
__O uint32_t TFDR[32]
Definition: MIMXRT1062.h:19315
flexspi_device_wait_busy
status_t flexspi_device_wait_busy(uint32_t instance, flexspi_mem_config_t *config, bool isParallelMode, uint32_t baseAddr)
Wait until device is idle.
Definition: fsl_flexspi.c:1233
CMD_INDEX_WRITEENABLE
#define CMD_INDEX_WRITEENABLE
Definition: fsl_flexspi.h:41
flexspi_is_word_addressable
bool flexspi_is_word_addressable(flexspi_mem_config_t *config)
Check whether device works under word addressable mode.
Definition: fsl_flexspi.c:131
kFlexSpiOperation_Command
Definition: fsl_flexspi.h:246
flexspi_clear_sequence_pointer
void flexspi_clear_sequence_pointer(uint32_t instance)
Clear FlexSPI sequence pointer.
Definition: fsl_flexspi.c:1340
_FlexSpiXfer::txSize
uint32_t txSize
Tx size in bytes.
Definition: fsl_flexspi.h:266
_FlexSPIConfig::controllerMiscOption
uint32_t controllerMiscOption
Definition: fsl_flexspi.h:216
g_flexSpiInstances
static FLEXSPI_Type *const g_flexSpiInstances[]
Definition: fsl_flexspi.c:39
_FlexSpiXfer::rxSize
uint32_t rxSize
Rx size in bytes.
Definition: fsl_flexspi.h:268
FLEXSPI_Type::MCR1
__IO uint32_t MCR1
Definition: MIMXRT1062.h:19283
FLEXSPI_STS0_SEQIDLE_MASK
#define FLEXSPI_STS0_SEQIDLE_MASK
Definition: MIMXRT1062.h:19926
kFlexSpiClock_SerialRootClock
Serial Root Clock.
Definition: fsl_flexspi.h:276
kFlexSpiMiscOffset_SafeConfigFreqEnable
Bit for Safe Configuration Frequency enable.
Definition: fsl_flexspi.h:139
kFlexSpiMiscOffset_ParallelEnable
Bit for Parallel mode enable.
Definition: fsl_flexspi.h:137
FLEXSPI_IPRXFSTS_FILL_MASK
#define FLEXSPI_IPRXFSTS_FILL_MASK
Definition: MIMXRT1062.h:20059
FLEXSPI_Type::INTR
__IO uint32_t INTR
Definition: MIMXRT1062.h:19287
FLEXSPI_Type::MCR2
__IO uint32_t MCR2
Definition: MIMXRT1062.h:19284
kFlexSpiOperation_End
effective.
Definition: fsl_flexspi.h:254
flexspi_is_ddr_mode_enable
bool flexspi_is_ddr_mode_enable(flexspi_mem_config_t *config)
Check whether DDR mode feature is enabled.
Definition: fsl_flexspi.c:155
kFlexSpiIpCmdError_SequenceExecutionTimeout
Definition: fsl_flexspi.h:119
CMD_INDEX_WRITE
#define CMD_INDEX_WRITE
Definition: fsl_flexspi.h:42
_FlexSPIConfig::waitTimeCfgCommands
uint16_t waitTimeCfgCommands
Generic configuration, etc.
Definition: fsl_flexspi.h:204
FLEXSPI_IPTXFCR_TXWMRK
#define FLEXSPI_IPTXFCR_TXWMRK(x)
Definition: MIMXRT1062.h:19886
_FlexSPIConfig::columnAddressWidth
uint8_t columnAddressWidth
Definition: fsl_flexspi.h:199
_FlexSpiXfer::txBuffer
uint32_t * txBuffer
Tx buffer.
Definition: fsl_flexspi.h:265
FLEXSPI_MCR1_SEQWAIT
#define FLEXSPI_MCR1_SEQWAIT(x)
Definition: MIMXRT1062.h:19412
FLEXSPI_FLSHCR2_AWRSEQNUM
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x)
Definition: MIMXRT1062.h:19746
_FlexSpiXfer::rxBuffer
uint32_t * rxBuffer
Rx buffer.
Definition: fsl_flexspi.h:267
flexspi_device_workmode_config
static status_t flexspi_device_workmode_config(uint32_t instance, flexspi_mem_config_t *config, uint32_t baseAddr)
Configure Device workmode via FlexSPI.
Definition: fsl_flexspi.c:580
flexspi_clear_ip_rxfifo
static void flexspi_clear_ip_rxfifo(FLEXSPI_Type *base)
Clear IP RXFIO.
Definition: fsl_flexspi.c:401
kFlexSPIReadSampleClk_ExternalInputFromDqsPad
Definition: fsl_flexspi.h:106
CMD_INDEX_READSTATUS
#define CMD_INDEX_READSTATUS
Definition: fsl_flexspi.h:40
FLEXSPI_LUT_KEY_VAL
#define FLEXSPI_LUT_KEY_VAL
FlesSPI Unlock/Lock Key.
Definition: fsl_flexspi.c:17
FLEXSPI_DLLCR_OVRDVAL_SHIFT
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT
Definition: MIMXRT1062.h:19915
FLEXSPI_DLLCR_DLLEN
#define FLEXSPI_DLLCR_DLLEN(x)
Definition: MIMXRT1062.h:19895
flexspi_clock_gate_enable
void flexspi_clock_gate_enable(uint32_t instance)
Enable clock gate of FlexSPI.
FLEXSPI_AHBRXBUFCR0_MSTRID_MASK
#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK
Definition: MIMXRT1062.h:19651
flexspi_sw_delay_us
void flexspi_sw_delay_us(uint64_t us)
_FlexSpiXfer::seqNum
uint32_t seqNum
Sequence Number.
Definition: fsl_flexspi.h:263
_FlexSPIConfig::lutCustomSeq
flexspi_lut_seq_t lutCustomSeq[12]
[0x180-0x1af] Customizable LUT Sequences
Definition: fsl_flexspi.h:240
CMD_LUT_SEQ_IDX_READ
#define CMD_LUT_SEQ_IDX_READ
Definition: fsl_flexspi.h:44
_FlexSPIConfig::sflashA1Size
uint32_t sflashA1Size
[0x050-0x053] Size of Flash connected to A1
Definition: fsl_flexspi.h:225
flexspi_get_max_supported_freq
status_t flexspi_get_max_supported_freq(uint32_t instance, uint32_t *freq, uint32_t clkMode)
Get Maximumn clock frequency.
FLEXSPI_FREQ_1GHz
#define FLEXSPI_FREQ_1GHz
Definition: fsl_flexspi.c:19
_FlexSPIConfig::deviceModeSeq
flexspi_lut_seq_t deviceModeSeq
DPI/QPI/OPI switch or reset command.
Definition: fsl_flexspi.h:206
flexspi_dll_time_t::time_100ps
uint8_t time_100ps
Definition: fsl_flexspi.h:186
CMD_LUT_FOR_IP_CMD
#define CMD_LUT_FOR_IP_CMD
LUT sequence id for IP command.
Definition: fsl_flexspi.c:27
flexspi_half_clock_control
void flexspi_half_clock_control(uint32_t instance, uint32_t option)
Half FlexSPI Clock.
Definition: fsl_flexspi.c:1360
_FlexSPIConfig::configCmdSeqs
flexspi_lut_seq_t configCmdSeqs[3]
[0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
Definition: fsl_flexspi.h:212
FLEXSPI_MCR0_ATDFEN_MASK
#define FLEXSPI_MCR0_ATDFEN_MASK
Definition: MIMXRT1062.h:19356
flexspi_unlock_lut
static void flexspi_unlock_lut(FLEXSPI_Type *base)
Unlock LUT.
Definition: fsl_flexspi.c:83
FLEXSPI_IPCR1_IPAREN
#define FLEXSPI_IPCR1_IPAREN(x)
Definition: MIMXRT1062.h:19835
FLEXSPI_MCR0_AHBGRANTWAIT_MASK
#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK
Definition: MIMXRT1062.h:19398
FLEXSPI_MCR2_SAMEDEVICEEN_MASK
#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK
Definition: MIMXRT1062.h:19433
kStatus_FLEXSPI_DeviceTimeout
Status for Device timeout.
Definition: fsl_flexspi.h:129
FLEXSPI_MCR0_HSEN_MASK
#define FLEXSPI_MCR0_HSEN_MASK
Definition: MIMXRT1062.h:19363
FLEXSPI_INTR_AHBCMDGE_MASK
#define FLEXSPI_INTR_AHBCMDGE_MASK
Definition: MIMXRT1062.h:19572
flexspi_get_ticks
status_t flexspi_get_ticks(uint32_t *ticks, uint32_t intervalNs, uint32_t freq, uint32_t unit)
Get interval ticks based on provided interval in terms of nano-seconds, frequency and unit.
Definition: fsl_flexspi.c:331
_FlexSPIConfig::lutCustomSeqEnable
uint8_t lutCustomSeqEnable
Chapter for more details.
Definition: fsl_flexspi.h:222
kStatus_FLEXSPI_SequenceExecutionTimeout
Status for Sequence Execution timeout.
Definition: fsl_flexspi.h:126
FLEXSPI_Type::IPTXFCR
__IO uint32_t IPTXFCR
Definition: MIMXRT1062.h:19304
FLEXSPI_Type::MCR0
__IO uint32_t MCR0
Definition: MIMXRT1062.h:19282
CMD_LUT_SEQ_IDX_WRITE
#define CMD_LUT_SEQ_IDX_WRITE
Definition: fsl_flexspi.h:47
flexspi_wait_idle
void flexspi_wait_idle(uint32_t instance)
Wait until FlexSPI controller becomes idle.
Definition: fsl_flexspi.c:1171
FLEXSPI_Type::STS1
__I uint32_t STS1
Definition: MIMXRT1062.h:19308
flexspi_get_module_base
static FLEXSPI_Type * flexspi_get_module_base(uint32_t instance)
Get FlexSPI instance.
Definition: fsl_flexspi.c:419
flexspi_get_clock
status_t flexspi_get_clock(uint32_t instance, flexspi_clock_type_t type, uint32_t *freq)
Get FlexSPI Clock frequency.
FLEXSPI_IPRXFCR_CLRIPRXF_MASK
#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK
Definition: MIMXRT1062.h:19849
flexspi_device_cmd_config
static status_t flexspi_device_cmd_config(uint32_t instance, flexspi_mem_config_t *config, uint32_t baseAddr)
Configure Device registers via FlexSPI.
Definition: fsl_flexspi.c:665
_FlexSPIConfig
FlexSPI Memory Configuration Block.
Definition: fsl_flexspi.h:191
FLEXSPI_MCR0_RXCLKSRC
#define FLEXSPI_MCR0_RXCLKSRC(x)
Definition: MIMXRT1062.h:19348
FLEXSPI_Type::FLSHCR0
__IO uint32_t FLSHCR0[4]
Definition: MIMXRT1062.h:19292
flexspi_config_ahb_buffers
status_t flexspi_config_ahb_buffers(FLEXSPI_Type *base, flexspi_mem_config_t *config)
Definition: fsl_flexspi.c:500
_FlexSPIConfig::serialClkFreq
uint8_t serialClkFreq
Definition: fsl_flexspi.h:220
_FlexSPIConfig::sflashB2Size
uint32_t sflashB2Size
[0x05c-0x05f] Size of Flash connected to B2
Definition: fsl_flexspi.h:228
FLEXSPI_MCR0_COMBINATIONEN_MASK
#define FLEXSPI_MCR0_COMBINATIONEN_MASK
Definition: MIMXRT1062.h:19377
kFlexSpiMiscOffset_DdrModeEnable
Bit for DDR clock confiuration indication.
Definition: fsl_flexspi.h:141
flexspi_wait_until_ip_idle
static void flexspi_wait_until_ip_idle(FLEXSPI_Type *base)
Wait Until FlexSPI IP is idle.
Definition: fsl_flexspi.c:409
FLEXSPI_INTR_IPRXWA_MASK
#define FLEXSPI_INTR_IPRXWA_MASK
Definition: MIMXRT1062.h:19589
FLEXSPI_Type::IPCMD
__IO uint32_t IPCMD
Definition: MIMXRT1062.h:19301
FLEXSPI_INTR_IPCMDERR_MASK
#define FLEXSPI_INTR_IPCMDERR_MASK
Definition: MIMXRT1062.h:19577
FLEXSPI_STS1_IPCMDERRCODE_MASK
#define FLEXSPI_STS1_IPCMDERRCODE_MASK
Definition: MIMXRT1062.h:19978
_FlexSPIConfig::commandInterval
uint32_t commandInterval
[0x074-0x077] CS deselect interval between two commands
Definition: fsl_flexspi.h:234
FLEXSPI_IPCR1_IDATSZ
#define FLEXSPI_IPCR1_IDATSZ(x)
Definition: MIMXRT1062.h:19818