Callisto4Bootloader: CCM Register Masks

Callisto4Bootloader

CCM Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » CCM Peripheral Access Layer

## CCR - CCM Control Register

#define | CCM_CCR_OSCNT_MASK (0xFFU)
#define | CCM_CCR_OSCNT_SHIFT (0U)
#define | CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
#define | CCM_CCR_COSC_EN_MASK (0x1000U)
#define | CCM_CCR_COSC_EN_SHIFT (12U)
#define | CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
#define | CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
#define | CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
#define | CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
#define | CCM_CCR_RBC_EN_MASK (0x8000000U)
#define | CCM_CCR_RBC_EN_SHIFT (27U)
#define | CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)

## CSR - CCM Status Register

#define | CCM_CSR_REF_EN_B_MASK (0x1U)
#define | CCM_CSR_REF_EN_B_SHIFT (0U)
#define | CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
#define | CCM_CSR_CAMP2_READY_MASK (0x8U)
#define | CCM_CSR_CAMP2_READY_SHIFT (3U)
#define | CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
#define | CCM_CSR_COSC_READY_MASK (0x20U)
#define | CCM_CSR_COSC_READY_SHIFT (5U)
#define | CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)

## CCSR - CCM Clock Switcher Register

#define | CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
#define | CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
#define | CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)

## CACRR - CCM Arm Clock Root Register

#define | CCM_CACRR_ARM_PODF_MASK (0x7U)
#define | CCM_CACRR_ARM_PODF_SHIFT (0U)
#define | CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)

## CBCDR - CCM Bus Clock Divider Register

#define | CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
#define | CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
#define | CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
#define | CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
#define | CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
#define | CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
#define | CCM_CBCDR_IPG_PODF_MASK (0x300U)
#define | CCM_CBCDR_IPG_PODF_SHIFT (8U)
#define | CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
#define | CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
#define | CCM_CBCDR_AHB_PODF_SHIFT (10U)
#define | CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
#define | CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
#define | CCM_CBCDR_SEMC_PODF_SHIFT (16U)
#define | CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
#define | CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
#define | CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
#define | CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
#define | CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
#define | CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
#define | CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)

## CBCMR - CCM Bus Clock Multiplexer Register

#define | CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
#define | CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
#define | CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
#define | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK (0x300U)
#define | CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT (8U)
#define | CCM_CBCMR_FLEXSPI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT)) & CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK)
#define | CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
#define | CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
#define | CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
#define | CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
#define | CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
#define | CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
#define | CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
#define | CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
#define | CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
#define | CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
#define | CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
#define | CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
#define | CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
#define | CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
#define | CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
#define | CCM_CBCMR_FLEXSPI2_PODF_MASK (0xE0000000U)
#define | CCM_CBCMR_FLEXSPI2_PODF_SHIFT (29U)
#define | CCM_CBCMR_FLEXSPI2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_PODF_SHIFT)) & CCM_CBCMR_FLEXSPI2_PODF_MASK)

## CSCMR1 - CCM Serial Clock Multiplexer Register 1

#define | CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
#define | CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
#define | CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
#define | CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
#define | CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
#define | CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
#define | CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
#define | CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
#define | CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
#define | CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
#define | CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
#define | CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
#define | CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
#define | CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
#define | CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
#define | CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
#define | CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
#define | CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
#define | CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
#define | CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
#define | CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
#define | CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
#define | CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
#define | CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
#define | CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
#define | CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
#define | CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)

## CSCMR2 - CCM Serial Clock Multiplexer Register 2

#define | CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
#define | CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
#define | CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
#define | CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
#define | CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
#define | CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
#define | CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
#define | CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
#define | CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)

## CSCDR1 - CCM Serial Clock Divider Register 1

#define | CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
#define | CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
#define | CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
#define | CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
#define | CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
#define | CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
#define | CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
#define | CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
#define | CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
#define | CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
#define | CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
#define | CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
#define | CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
#define | CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
#define | CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)

## CS1CDR - CCM Clock Divider Register

#define | CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
#define | CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
#define | CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
#define | CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
#define | CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
#define | CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
#define | CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
#define | CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
#define | CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
#define | CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
#define | CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
#define | CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
#define | CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
#define | CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
#define | CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
#define | CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
#define | CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
#define | CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)

## CS2CDR - CCM Clock Divider Register

#define | CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
#define | CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
#define | CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
#define | CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
#define | CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
#define | CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)

## CDCDR - CCM D1 Clock Divider Register

#define | CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
#define | CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
#define | CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
#define | CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
#define | CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
#define | CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
#define | CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
#define | CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
#define | CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
#define | CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
#define | CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
#define | CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
#define | CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
#define | CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
#define | CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
#define | CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
#define | CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
#define | CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)

## CSCDR2 - CCM Serial Clock Divider Register 2

#define | CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
#define | CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
#define | CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
#define | CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
#define | CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
#define | CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
#define | CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
#define | CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
#define | CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
#define | CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
#define | CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
#define | CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)

## CSCDR3 - CCM Serial Clock Divider Register 3

#define | CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
#define | CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
#define | CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
#define | CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
#define | CCM_CSCDR3_CSI_PODF_SHIFT (11U)
#define | CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)

## CDHIPR - CCM Divider Handshake In-Process Register

#define | CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
#define | CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
#define | CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
#define | CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
#define | CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
#define | CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
#define | CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
#define | CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
#define | CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
#define | CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
#define | CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
#define | CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
#define | CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
#define | CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
#define | CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)

## CLPCR - CCM Low Power Control Register

#define | CCM_CLPCR_LPM_MASK (0x3U)
#define | CCM_CLPCR_LPM_SHIFT (0U)
#define | CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
#define | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
#define | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
#define | CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
#define | CCM_CLPCR_SBYOS_MASK (0x40U)
#define | CCM_CLPCR_SBYOS_SHIFT (6U)
#define | CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
#define | CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
#define | CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
#define | CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
#define | CCM_CLPCR_VSTBY_MASK (0x100U)
#define | CCM_CLPCR_VSTBY_SHIFT (8U)
#define | CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
#define | CCM_CLPCR_STBY_COUNT_MASK (0x600U)
#define | CCM_CLPCR_STBY_COUNT_SHIFT (9U)
#define | CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
#define | CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
#define | CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
#define | CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
#define | CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
#define | CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
#define | CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
#define | CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
#define | CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
#define | CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
#define | CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
#define | CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
#define | CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
#define | CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
#define | CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
#define | CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
#define | CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
#define | CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
#define | CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)

## CISR - CCM Interrupt Status Register

#define | CCM_CISR_LRF_PLL_MASK (0x1U)
#define | CCM_CISR_LRF_PLL_SHIFT (0U)
#define | CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
#define | CCM_CISR_COSC_READY_MASK (0x40U)
#define | CCM_CISR_COSC_READY_SHIFT (6U)
#define | CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
#define | CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
#define | CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
#define | CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
#define | CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
#define | CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
#define | CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
#define | CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
#define | CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
#define | CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
#define | CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
#define | CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
#define | CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
#define | CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
#define | CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
#define | CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)

## CIMR - CCM Interrupt Mask Register

#define | CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
#define | CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
#define | CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
#define | CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
#define | CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
#define | CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
#define | CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
#define | CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
#define | CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
#define | CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
#define | CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
#define | CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
#define | CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
#define | CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
#define | CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
#define | CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
#define | CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
#define | CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
#define | CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
#define | CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
#define | CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)

## CCOSR - CCM Clock Output Source Register

#define | CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
#define | CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
#define | CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
#define | CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
#define | CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
#define | CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
#define | CCM_CCOSR_CLKO1_EN_MASK (0x80U)
#define | CCM_CCOSR_CLKO1_EN_SHIFT (7U)
#define | CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
#define | CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
#define | CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
#define | CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
#define | CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
#define | CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
#define | CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
#define | CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
#define | CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
#define | CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
#define | CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
#define | CCM_CCOSR_CLKO2_EN_SHIFT (24U)
#define | CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)

## CGPR - CCM General Purpose Register

#define | CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
#define | CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
#define | CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
#define | CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
#define | CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
#define | CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
#define | CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
#define | CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
#define | CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
#define | CCM_CGPR_FPL_MASK (0x10000U)
#define | CCM_CGPR_FPL_SHIFT (16U)
#define | CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
#define | CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
#define | CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
#define | CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)

## CCGR0 - CCM Clock Gating Register 0

#define | CCM_CCGR0_CG0_MASK (0x3U)
#define | CCM_CCGR0_CG0_SHIFT (0U)
#define | CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
#define | CCM_CCGR0_CG1_MASK (0xCU)
#define | CCM_CCGR0_CG1_SHIFT (2U)
#define | CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
#define | CCM_CCGR0_CG2_MASK (0x30U)
#define | CCM_CCGR0_CG2_SHIFT (4U)
#define | CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
#define | CCM_CCGR0_CG3_MASK (0xC0U)
#define | CCM_CCGR0_CG3_SHIFT (6U)
#define | CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
#define | CCM_CCGR0_CG4_MASK (0x300U)
#define | CCM_CCGR0_CG4_SHIFT (8U)
#define | CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
#define | CCM_CCGR0_CG5_MASK (0xC00U)
#define | CCM_CCGR0_CG5_SHIFT (10U)
#define | CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
#define | CCM_CCGR0_CG6_MASK (0x3000U)
#define | CCM_CCGR0_CG6_SHIFT (12U)
#define | CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
#define | CCM_CCGR0_CG7_MASK (0xC000U)
#define | CCM_CCGR0_CG7_SHIFT (14U)
#define | CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
#define | CCM_CCGR0_CG8_MASK (0x30000U)
#define | CCM_CCGR0_CG8_SHIFT (16U)
#define | CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
#define | CCM_CCGR0_CG9_MASK (0xC0000U)
#define | CCM_CCGR0_CG9_SHIFT (18U)
#define | CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
#define | CCM_CCGR0_CG10_MASK (0x300000U)
#define | CCM_CCGR0_CG10_SHIFT (20U)
#define | CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
#define | CCM_CCGR0_CG11_MASK (0xC00000U)
#define | CCM_CCGR0_CG11_SHIFT (22U)
#define | CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
#define | CCM_CCGR0_CG12_MASK (0x3000000U)
#define | CCM_CCGR0_CG12_SHIFT (24U)
#define | CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
#define | CCM_CCGR0_CG13_MASK (0xC000000U)
#define | CCM_CCGR0_CG13_SHIFT (26U)
#define | CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
#define | CCM_CCGR0_CG14_MASK (0x30000000U)
#define | CCM_CCGR0_CG14_SHIFT (28U)
#define | CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
#define | CCM_CCGR0_CG15_MASK (0xC0000000U)
#define | CCM_CCGR0_CG15_SHIFT (30U)
#define | CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)

## CCGR1 - CCM Clock Gating Register 1

#define | CCM_CCGR1_CG0_MASK (0x3U)
#define | CCM_CCGR1_CG0_SHIFT (0U)
#define | CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
#define | CCM_CCGR1_CG1_MASK (0xCU)
#define | CCM_CCGR1_CG1_SHIFT (2U)
#define | CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
#define | CCM_CCGR1_CG2_MASK (0x30U)
#define | CCM_CCGR1_CG2_SHIFT (4U)
#define | CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
#define | CCM_CCGR1_CG3_MASK (0xC0U)
#define | CCM_CCGR1_CG3_SHIFT (6U)
#define | CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
#define | CCM_CCGR1_CG4_MASK (0x300U)
#define | CCM_CCGR1_CG4_SHIFT (8U)
#define | CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
#define | CCM_CCGR1_CG5_MASK (0xC00U)
#define | CCM_CCGR1_CG5_SHIFT (10U)
#define | CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
#define | CCM_CCGR1_CG6_MASK (0x3000U)
#define | CCM_CCGR1_CG6_SHIFT (12U)
#define | CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
#define | CCM_CCGR1_CG7_MASK (0xC000U)
#define | CCM_CCGR1_CG7_SHIFT (14U)
#define | CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
#define | CCM_CCGR1_CG8_MASK (0x30000U)
#define | CCM_CCGR1_CG8_SHIFT (16U)
#define | CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
#define | CCM_CCGR1_CG9_MASK (0xC0000U)
#define | CCM_CCGR1_CG9_SHIFT (18U)
#define | CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
#define | CCM_CCGR1_CG10_MASK (0x300000U)
#define | CCM_CCGR1_CG10_SHIFT (20U)
#define | CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
#define | CCM_CCGR1_CG11_MASK (0xC00000U)
#define | CCM_CCGR1_CG11_SHIFT (22U)
#define | CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
#define | CCM_CCGR1_CG12_MASK (0x3000000U)
#define | CCM_CCGR1_CG12_SHIFT (24U)
#define | CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
#define | CCM_CCGR1_CG13_MASK (0xC000000U)
#define | CCM_CCGR1_CG13_SHIFT (26U)
#define | CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
#define | CCM_CCGR1_CG14_MASK (0x30000000U)
#define | CCM_CCGR1_CG14_SHIFT (28U)
#define | CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
#define | CCM_CCGR1_CG15_MASK (0xC0000000U)
#define | CCM_CCGR1_CG15_SHIFT (30U)
#define | CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)

## CCGR2 - CCM Clock Gating Register 2

#define | CCM_CCGR2_CG0_MASK (0x3U)
#define | CCM_CCGR2_CG0_SHIFT (0U)
#define | CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
#define | CCM_CCGR2_CG1_MASK (0xCU)
#define | CCM_CCGR2_CG1_SHIFT (2U)
#define | CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
#define | CCM_CCGR2_CG2_MASK (0x30U)
#define | CCM_CCGR2_CG2_SHIFT (4U)
#define | CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
#define | CCM_CCGR2_CG3_MASK (0xC0U)
#define | CCM_CCGR2_CG3_SHIFT (6U)
#define | CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
#define | CCM_CCGR2_CG4_MASK (0x300U)
#define | CCM_CCGR2_CG4_SHIFT (8U)
#define | CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
#define | CCM_CCGR2_CG5_MASK (0xC00U)
#define | CCM_CCGR2_CG5_SHIFT (10U)
#define | CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
#define | CCM_CCGR2_CG6_MASK (0x3000U)
#define | CCM_CCGR2_CG6_SHIFT (12U)
#define | CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
#define | CCM_CCGR2_CG7_MASK (0xC000U)
#define | CCM_CCGR2_CG7_SHIFT (14U)
#define | CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
#define | CCM_CCGR2_CG8_MASK (0x30000U)
#define | CCM_CCGR2_CG8_SHIFT (16U)
#define | CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
#define | CCM_CCGR2_CG9_MASK (0xC0000U)
#define | CCM_CCGR2_CG9_SHIFT (18U)
#define | CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
#define | CCM_CCGR2_CG10_MASK (0x300000U)
#define | CCM_CCGR2_CG10_SHIFT (20U)
#define | CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
#define | CCM_CCGR2_CG11_MASK (0xC00000U)
#define | CCM_CCGR2_CG11_SHIFT (22U)
#define | CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
#define | CCM_CCGR2_CG12_MASK (0x3000000U)
#define | CCM_CCGR2_CG12_SHIFT (24U)
#define | CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
#define | CCM_CCGR2_CG13_MASK (0xC000000U)
#define | CCM_CCGR2_CG13_SHIFT (26U)
#define | CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
#define | CCM_CCGR2_CG14_MASK (0x30000000U)
#define | CCM_CCGR2_CG14_SHIFT (28U)
#define | CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
#define | CCM_CCGR2_CG15_MASK (0xC0000000U)
#define | CCM_CCGR2_CG15_SHIFT (30U)
#define | CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)

## CCGR3 - CCM Clock Gating Register 3

#define | CCM_CCGR3_CG0_MASK (0x3U)
#define | CCM_CCGR3_CG0_SHIFT (0U)
#define | CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
#define | CCM_CCGR3_CG1_MASK (0xCU)
#define | CCM_CCGR3_CG1_SHIFT (2U)
#define | CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
#define | CCM_CCGR3_CG2_MASK (0x30U)
#define | CCM_CCGR3_CG2_SHIFT (4U)
#define | CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
#define | CCM_CCGR3_CG3_MASK (0xC0U)
#define | CCM_CCGR3_CG3_SHIFT (6U)
#define | CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
#define | CCM_CCGR3_CG4_MASK (0x300U)
#define | CCM_CCGR3_CG4_SHIFT (8U)
#define | CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
#define | CCM_CCGR3_CG5_MASK (0xC00U)
#define | CCM_CCGR3_CG5_SHIFT (10U)
#define | CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
#define | CCM_CCGR3_CG6_MASK (0x3000U)
#define | CCM_CCGR3_CG6_SHIFT (12U)
#define | CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
#define | CCM_CCGR3_CG7_MASK (0xC000U)
#define | CCM_CCGR3_CG7_SHIFT (14U)
#define | CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
#define | CCM_CCGR3_CG8_MASK (0x30000U)
#define | CCM_CCGR3_CG8_SHIFT (16U)
#define | CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
#define | CCM_CCGR3_CG9_MASK (0xC0000U)
#define | CCM_CCGR3_CG9_SHIFT (18U)
#define | CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
#define | CCM_CCGR3_CG10_MASK (0x300000U)
#define | CCM_CCGR3_CG10_SHIFT (20U)
#define | CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
#define | CCM_CCGR3_CG11_MASK (0xC00000U)
#define | CCM_CCGR3_CG11_SHIFT (22U)
#define | CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
#define | CCM_CCGR3_CG12_MASK (0x3000000U)
#define | CCM_CCGR3_CG12_SHIFT (24U)
#define | CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
#define | CCM_CCGR3_CG13_MASK (0xC000000U)
#define | CCM_CCGR3_CG13_SHIFT (26U)
#define | CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
#define | CCM_CCGR3_CG14_MASK (0x30000000U)
#define | CCM_CCGR3_CG14_SHIFT (28U)
#define | CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
#define | CCM_CCGR3_CG15_MASK (0xC0000000U)
#define | CCM_CCGR3_CG15_SHIFT (30U)
#define | CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)

## CCGR4 - CCM Clock Gating Register 4

#define | CCM_CCGR4_CG0_MASK (0x3U)
#define | CCM_CCGR4_CG0_SHIFT (0U)
#define | CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
#define | CCM_CCGR4_CG1_MASK (0xCU)
#define | CCM_CCGR4_CG1_SHIFT (2U)
#define | CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
#define | CCM_CCGR4_CG2_MASK (0x30U)
#define | CCM_CCGR4_CG2_SHIFT (4U)
#define | CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
#define | CCM_CCGR4_CG3_MASK (0xC0U)
#define | CCM_CCGR4_CG3_SHIFT (6U)
#define | CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
#define | CCM_CCGR4_CG4_MASK (0x300U)
#define | CCM_CCGR4_CG4_SHIFT (8U)
#define | CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
#define | CCM_CCGR4_CG5_MASK (0xC00U)
#define | CCM_CCGR4_CG5_SHIFT (10U)
#define | CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
#define | CCM_CCGR4_CG6_MASK (0x3000U)
#define | CCM_CCGR4_CG6_SHIFT (12U)
#define | CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
#define | CCM_CCGR4_CG7_MASK (0xC000U)
#define | CCM_CCGR4_CG7_SHIFT (14U)
#define | CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
#define | CCM_CCGR4_CG8_MASK (0x30000U)
#define | CCM_CCGR4_CG8_SHIFT (16U)
#define | CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
#define | CCM_CCGR4_CG9_MASK (0xC0000U)
#define | CCM_CCGR4_CG9_SHIFT (18U)
#define | CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
#define | CCM_CCGR4_CG10_MASK (0x300000U)
#define | CCM_CCGR4_CG10_SHIFT (20U)
#define | CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
#define | CCM_CCGR4_CG11_MASK (0xC00000U)
#define | CCM_CCGR4_CG11_SHIFT (22U)
#define | CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
#define | CCM_CCGR4_CG12_MASK (0x3000000U)
#define | CCM_CCGR4_CG12_SHIFT (24U)
#define | CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
#define | CCM_CCGR4_CG13_MASK (0xC000000U)
#define | CCM_CCGR4_CG13_SHIFT (26U)
#define | CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
#define | CCM_CCGR4_CG14_MASK (0x30000000U)
#define | CCM_CCGR4_CG14_SHIFT (28U)
#define | CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
#define | CCM_CCGR4_CG15_MASK (0xC0000000U)
#define | CCM_CCGR4_CG15_SHIFT (30U)
#define | CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)

## CCGR5 - CCM Clock Gating Register 5

#define | CCM_CCGR5_CG0_MASK (0x3U)
#define | CCM_CCGR5_CG0_SHIFT (0U)
#define | CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
#define | CCM_CCGR5_CG1_MASK (0xCU)
#define | CCM_CCGR5_CG1_SHIFT (2U)
#define | CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
#define | CCM_CCGR5_CG2_MASK (0x30U)
#define | CCM_CCGR5_CG2_SHIFT (4U)
#define | CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
#define | CCM_CCGR5_CG3_MASK (0xC0U)
#define | CCM_CCGR5_CG3_SHIFT (6U)
#define | CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
#define | CCM_CCGR5_CG4_MASK (0x300U)
#define | CCM_CCGR5_CG4_SHIFT (8U)
#define | CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
#define | CCM_CCGR5_CG5_MASK (0xC00U)
#define | CCM_CCGR5_CG5_SHIFT (10U)
#define | CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
#define | CCM_CCGR5_CG6_MASK (0x3000U)
#define | CCM_CCGR5_CG6_SHIFT (12U)
#define | CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
#define | CCM_CCGR5_CG7_MASK (0xC000U)
#define | CCM_CCGR5_CG7_SHIFT (14U)
#define | CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
#define | CCM_CCGR5_CG8_MASK (0x30000U)
#define | CCM_CCGR5_CG8_SHIFT (16U)
#define | CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
#define | CCM_CCGR5_CG9_MASK (0xC0000U)
#define | CCM_CCGR5_CG9_SHIFT (18U)
#define | CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
#define | CCM_CCGR5_CG10_MASK (0x300000U)
#define | CCM_CCGR5_CG10_SHIFT (20U)
#define | CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
#define | CCM_CCGR5_CG11_MASK (0xC00000U)
#define | CCM_CCGR5_CG11_SHIFT (22U)
#define | CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
#define | CCM_CCGR5_CG12_MASK (0x3000000U)
#define | CCM_CCGR5_CG12_SHIFT (24U)
#define | CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
#define | CCM_CCGR5_CG13_MASK (0xC000000U)
#define | CCM_CCGR5_CG13_SHIFT (26U)
#define | CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
#define | CCM_CCGR5_CG14_MASK (0x30000000U)
#define | CCM_CCGR5_CG14_SHIFT (28U)
#define | CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
#define | CCM_CCGR5_CG15_MASK (0xC0000000U)
#define | CCM_CCGR5_CG15_SHIFT (30U)
#define | CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)

## CCGR6 - CCM Clock Gating Register 6

#define | CCM_CCGR6_CG0_MASK (0x3U)
#define | CCM_CCGR6_CG0_SHIFT (0U)
#define | CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
#define | CCM_CCGR6_CG1_MASK (0xCU)
#define | CCM_CCGR6_CG1_SHIFT (2U)
#define | CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
#define | CCM_CCGR6_CG2_MASK (0x30U)
#define | CCM_CCGR6_CG2_SHIFT (4U)
#define | CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
#define | CCM_CCGR6_CG3_MASK (0xC0U)
#define | CCM_CCGR6_CG3_SHIFT (6U)
#define | CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
#define | CCM_CCGR6_CG4_MASK (0x300U)
#define | CCM_CCGR6_CG4_SHIFT (8U)
#define | CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
#define | CCM_CCGR6_CG5_MASK (0xC00U)
#define | CCM_CCGR6_CG5_SHIFT (10U)
#define | CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
#define | CCM_CCGR6_CG6_MASK (0x3000U)
#define | CCM_CCGR6_CG6_SHIFT (12U)
#define | CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
#define | CCM_CCGR6_CG7_MASK (0xC000U)
#define | CCM_CCGR6_CG7_SHIFT (14U)
#define | CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
#define | CCM_CCGR6_CG8_MASK (0x30000U)
#define | CCM_CCGR6_CG8_SHIFT (16U)
#define | CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
#define | CCM_CCGR6_CG9_MASK (0xC0000U)
#define | CCM_CCGR6_CG9_SHIFT (18U)
#define | CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
#define | CCM_CCGR6_CG10_MASK (0x300000U)
#define | CCM_CCGR6_CG10_SHIFT (20U)
#define | CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
#define | CCM_CCGR6_CG11_MASK (0xC00000U)
#define | CCM_CCGR6_CG11_SHIFT (22U)
#define | CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
#define | CCM_CCGR6_CG12_MASK (0x3000000U)
#define | CCM_CCGR6_CG12_SHIFT (24U)
#define | CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
#define | CCM_CCGR6_CG13_MASK (0xC000000U)
#define | CCM_CCGR6_CG13_SHIFT (26U)
#define | CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
#define | CCM_CCGR6_CG14_MASK (0x30000000U)
#define | CCM_CCGR6_CG14_SHIFT (28U)
#define | CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
#define | CCM_CCGR6_CG15_MASK (0xC0000000U)
#define | CCM_CCGR6_CG15_SHIFT (30U)
#define | CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)

## CCGR7 - CCM Clock Gating Register 7

#define | CCM_CCGR7_CG0_MASK (0x3U)
#define | CCM_CCGR7_CG0_SHIFT (0U)
#define | CCM_CCGR7_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG0_SHIFT)) & CCM_CCGR7_CG0_MASK)
#define | CCM_CCGR7_CG1_MASK (0xCU)
#define | CCM_CCGR7_CG1_SHIFT (2U)
#define | CCM_CCGR7_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG1_SHIFT)) & CCM_CCGR7_CG1_MASK)
#define | CCM_CCGR7_CG2_MASK (0x30U)
#define | CCM_CCGR7_CG2_SHIFT (4U)
#define | CCM_CCGR7_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG2_SHIFT)) & CCM_CCGR7_CG2_MASK)
#define | CCM_CCGR7_CG3_MASK (0xC0U)
#define | CCM_CCGR7_CG3_SHIFT (6U)
#define | CCM_CCGR7_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG3_SHIFT)) & CCM_CCGR7_CG3_MASK)
#define | CCM_CCGR7_CG4_MASK (0x300U)
#define | CCM_CCGR7_CG4_SHIFT (8U)
#define | CCM_CCGR7_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG4_SHIFT)) & CCM_CCGR7_CG4_MASK)
#define | CCM_CCGR7_CG5_MASK (0xC00U)
#define | CCM_CCGR7_CG5_SHIFT (10U)
#define | CCM_CCGR7_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG5_SHIFT)) & CCM_CCGR7_CG5_MASK)
#define | CCM_CCGR7_CG6_MASK (0x3000U)
#define | CCM_CCGR7_CG6_SHIFT (12U)
#define | CCM_CCGR7_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG6_SHIFT)) & CCM_CCGR7_CG6_MASK)

## CMEOR - CCM Module Enable Overide Register

#define | CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
#define | CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
#define | CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
#define | CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
#define | CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
#define | CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
#define | CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
#define | CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
#define | CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
#define | CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
#define | CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
#define | CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
#define | CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK (0x400U)
#define | CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT (10U)
#define | CCM_CMEOR_MOD_EN_OV_CANFD_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK)
#define | CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
#define | CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
#define | CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
#define | CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
#define | CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
#define | CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ CCM_CACRR_ARM_PODF

#define CCM_CACRR_ARM_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)

ARM_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5409 of file MIMXRT1062.h.

## ◆ CCM_CACRR_ARM_PODF_MASK

#define CCM_CACRR_ARM_PODF_MASK (0x7U)

Definition at line 5397 of file MIMXRT1062.h.

## ◆ CCM_CACRR_ARM_PODF_SHIFT

#define CCM_CACRR_ARM_PODF_SHIFT (0U)

Definition at line 5398 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_AHB_PODF

#define CCM_CBCDR_AHB_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)

AHB_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5449 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_AHB_PODF_MASK

#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)

Definition at line 5437 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_AHB_PODF_SHIFT

#define CCM_CBCDR_AHB_PODF_SHIFT (10U)

Definition at line 5438 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_IPG_PODF

#define CCM_CBCDR_IPG_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)

IPG_PODF 0b00..divide by 1 0b01..divide by 2 0b10..divide by 3 0b11..divide by 4

Definition at line 5436 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_IPG_PODF_MASK

#define CCM_CBCDR_IPG_PODF_MASK (0x300U)

Definition at line 5428 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_IPG_PODF_SHIFT

#define CCM_CBCDR_IPG_PODF_SHIFT (8U)

Definition at line 5429 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_PERIPH_CLK2_PODF

#define CCM_CBCDR_PERIPH_CLK2_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)

PERIPH_CLK2_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5482 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_PERIPH_CLK2_PODF_MASK

#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)

Definition at line 5470 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT

#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)

Definition at line 5471 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_PERIPH_CLK_SEL

#define CCM_CBCDR_PERIPH_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)

PERIPH_CLK_SEL 0b0..derive clock from pre_periph_clk_sel 0b1..derive clock from periph_clk2_clk_divided

Definition at line 5469 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_PERIPH_CLK_SEL_MASK

#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)

Definition at line 5463 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_PERIPH_CLK_SEL_SHIFT

#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)

Definition at line 5464 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_ALT_CLK_SEL

#define CCM_CBCDR_SEMC_ALT_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)

SEMC_ALT_CLK_SEL 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock

Definition at line 5427 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK

#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)

Definition at line 5421 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT

#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)

Definition at line 5422 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_CLK_SEL

#define CCM_CBCDR_SEMC_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)

SEMC_CLK_SEL 0b0..Periph_clk output will be used as SEMC clock root 0b1..SEMC alternative clock will be used as SEMC clock root

Definition at line 5420 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_CLK_SEL_MASK

#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)

Definition at line 5414 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_CLK_SEL_SHIFT

#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)

Definition at line 5415 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_PODF

#define CCM_CBCDR_SEMC_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)

SEMC_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5462 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_PODF_MASK

#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)

Definition at line 5450 of file MIMXRT1062.h.

## ◆ CCM_CBCDR_SEMC_PODF_SHIFT

#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)

Definition at line 5451 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_FLEXSPI2_CLK_SEL

#define CCM_CBCMR_FLEXSPI2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT)) & CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK)

FLEXSPI2_CLK_SEL 0b00..derive clock from PLL2 PFD2 0b01..derive clock from PLL3 PFD0 0b10..derive clock from PLL3 PFD1 0b11..derive clock from PLL2 (pll2_main_clk)

Definition at line 5504 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK

#define CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK (0x300U)

Definition at line 5496 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT

#define CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT (8U)

Definition at line 5497 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_FLEXSPI2_PODF

#define CCM_CBCMR_FLEXSPI2_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_PODF_SHIFT)) & CCM_CBCMR_FLEXSPI2_PODF_MASK)

FLEXSPI2_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5570 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_FLEXSPI2_PODF_MASK

#define CCM_CBCMR_FLEXSPI2_PODF_MASK (0xE0000000U)

Definition at line 5558 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_FLEXSPI2_PODF_SHIFT

#define CCM_CBCMR_FLEXSPI2_PODF_SHIFT (29U)

Definition at line 5559 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LCDIF_PODF

#define CCM_CBCMR_LCDIF_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)

LCDIF_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5544 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LCDIF_PODF_MASK

#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)

Definition at line 5532 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LCDIF_PODF_SHIFT

#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)

Definition at line 5533 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LPSPI_CLK_SEL

#define CCM_CBCMR_LPSPI_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)

LPSPI_CLK_SEL 0b00..derive clock from PLL3 PFD1 clk 0b01..derive clock from PLL3 PFD0 0b10..derive clock from PLL2 0b11..derive clock from PLL2 PFD2

Definition at line 5495 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LPSPI_CLK_SEL_MASK

#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)

Definition at line 5487 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LPSPI_CLK_SEL_SHIFT

#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)

Definition at line 5488 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LPSPI_PODF

#define CCM_CBCMR_LPSPI_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)

LPSPI_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5557 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LPSPI_PODF_MASK

#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)

Definition at line 5545 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_LPSPI_PODF_SHIFT

#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)

Definition at line 5546 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_PERIPH_CLK2_SEL

#define CCM_CBCMR_PERIPH_CLK2_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)

PERIPH_CLK2_SEL 0b00..derive clock from pll3_sw_clk 0b01..derive clock from osc_clk (pll1_ref_clk) 0b10..derive clock from pll2_bypass_clk 0b11..reserved

Definition at line 5513 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_PERIPH_CLK2_SEL_MASK

#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)

Definition at line 5505 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT

#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)

Definition at line 5506 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_PRE_PERIPH_CLK_SEL

#define CCM_CBCMR_PRE_PERIPH_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)

PRE_PERIPH_CLK_SEL 0b00..derive clock from PLL2 0b01..derive clock from PLL2 PFD2 0b10..derive clock from PLL2 PFD0 0b11..derive clock from divided PLL1

Definition at line 5531 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK

#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)

Definition at line 5523 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT

#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)

Definition at line 5524 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_TRACE_CLK_SEL

#define CCM_CBCMR_TRACE_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)

TRACE_CLK_SEL 0b00..derive clock from PLL2 0b01..derive clock from PLL2 PFD2 0b10..derive clock from PLL2 PFD0 0b11..derive clock from PLL2 PFD1

Definition at line 5522 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_TRACE_CLK_SEL_MASK

#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)

Definition at line 5514 of file MIMXRT1062.h.

## ◆ CCM_CBCMR_TRACE_CLK_SEL_SHIFT

#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)

Definition at line 5515 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG0

#define CCM_CCGR0_CG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)

Definition at line 6779 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG0_MASK

#define CCM_CCGR0_CG0_MASK (0x3U)

Definition at line 6777 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG0_SHIFT

#define CCM_CCGR0_CG0_SHIFT (0U)

Definition at line 6778 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG1

#define CCM_CCGR0_CG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)

Definition at line 6782 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG10

#define CCM_CCGR0_CG10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)

Definition at line 6809 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG10_MASK

#define CCM_CCGR0_CG10_MASK (0x300000U)

Definition at line 6807 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG10_SHIFT

#define CCM_CCGR0_CG10_SHIFT (20U)

Definition at line 6808 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG11

#define CCM_CCGR0_CG11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)

Definition at line 6812 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG11_MASK

#define CCM_CCGR0_CG11_MASK (0xC00000U)

Definition at line 6810 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG11_SHIFT

#define CCM_CCGR0_CG11_SHIFT (22U)

Definition at line 6811 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG12

#define CCM_CCGR0_CG12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)

Definition at line 6815 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG12_MASK

#define CCM_CCGR0_CG12_MASK (0x3000000U)

Definition at line 6813 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG12_SHIFT

#define CCM_CCGR0_CG12_SHIFT (24U)

Definition at line 6814 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG13

#define CCM_CCGR0_CG13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)

Definition at line 6818 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG13_MASK

#define CCM_CCGR0_CG13_MASK (0xC000000U)

Definition at line 6816 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG13_SHIFT

#define CCM_CCGR0_CG13_SHIFT (26U)

Definition at line 6817 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG14

#define CCM_CCGR0_CG14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)

Definition at line 6821 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG14_MASK

#define CCM_CCGR0_CG14_MASK (0x30000000U)

Definition at line 6819 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG14_SHIFT

#define CCM_CCGR0_CG14_SHIFT (28U)

Definition at line 6820 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG15

#define CCM_CCGR0_CG15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)

Definition at line 6824 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG15_MASK

#define CCM_CCGR0_CG15_MASK (0xC0000000U)

Definition at line 6822 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG15_SHIFT

#define CCM_CCGR0_CG15_SHIFT (30U)

Definition at line 6823 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG1_MASK

#define CCM_CCGR0_CG1_MASK (0xCU)

Definition at line 6780 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG1_SHIFT

#define CCM_CCGR0_CG1_SHIFT (2U)

Definition at line 6781 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG2

#define CCM_CCGR0_CG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)

Definition at line 6785 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG2_MASK

#define CCM_CCGR0_CG2_MASK (0x30U)

Definition at line 6783 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG2_SHIFT

#define CCM_CCGR0_CG2_SHIFT (4U)

Definition at line 6784 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG3

#define CCM_CCGR0_CG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)

Definition at line 6788 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG3_MASK

#define CCM_CCGR0_CG3_MASK (0xC0U)

Definition at line 6786 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG3_SHIFT

#define CCM_CCGR0_CG3_SHIFT (6U)

Definition at line 6787 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG4

#define CCM_CCGR0_CG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)

Definition at line 6791 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG4_MASK

#define CCM_CCGR0_CG4_MASK (0x300U)

Definition at line 6789 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG4_SHIFT

#define CCM_CCGR0_CG4_SHIFT (8U)

Definition at line 6790 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG5

#define CCM_CCGR0_CG5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)

Definition at line 6794 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG5_MASK

#define CCM_CCGR0_CG5_MASK (0xC00U)

Definition at line 6792 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG5_SHIFT

#define CCM_CCGR0_CG5_SHIFT (10U)

Definition at line 6793 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG6

#define CCM_CCGR0_CG6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)

Definition at line 6797 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG6_MASK

#define CCM_CCGR0_CG6_MASK (0x3000U)

Definition at line 6795 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG6_SHIFT

#define CCM_CCGR0_CG6_SHIFT (12U)

Definition at line 6796 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG7

#define CCM_CCGR0_CG7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)

Definition at line 6800 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG7_MASK

#define CCM_CCGR0_CG7_MASK (0xC000U)

Definition at line 6798 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG7_SHIFT

#define CCM_CCGR0_CG7_SHIFT (14U)

Definition at line 6799 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG8

#define CCM_CCGR0_CG8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)

Definition at line 6803 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG8_MASK

#define CCM_CCGR0_CG8_MASK (0x30000U)

Definition at line 6801 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG8_SHIFT

#define CCM_CCGR0_CG8_SHIFT (16U)

Definition at line 6802 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG9

#define CCM_CCGR0_CG9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)

Definition at line 6806 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG9_MASK

#define CCM_CCGR0_CG9_MASK (0xC0000U)

Definition at line 6804 of file MIMXRT1062.h.

## ◆ CCM_CCGR0_CG9_SHIFT

#define CCM_CCGR0_CG9_SHIFT (18U)

Definition at line 6805 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG0

#define CCM_CCGR1_CG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)

Definition at line 6831 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG0_MASK

#define CCM_CCGR1_CG0_MASK (0x3U)

Definition at line 6829 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG0_SHIFT

#define CCM_CCGR1_CG0_SHIFT (0U)

Definition at line 6830 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG1

#define CCM_CCGR1_CG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)

Definition at line 6834 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG10

#define CCM_CCGR1_CG10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)

Definition at line 6861 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG10_MASK

#define CCM_CCGR1_CG10_MASK (0x300000U)

Definition at line 6859 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG10_SHIFT

#define CCM_CCGR1_CG10_SHIFT (20U)

Definition at line 6860 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG11

#define CCM_CCGR1_CG11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)

Definition at line 6864 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG11_MASK

#define CCM_CCGR1_CG11_MASK (0xC00000U)

Definition at line 6862 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG11_SHIFT

#define CCM_CCGR1_CG11_SHIFT (22U)

Definition at line 6863 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG12

#define CCM_CCGR1_CG12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)

Definition at line 6867 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG12_MASK

#define CCM_CCGR1_CG12_MASK (0x3000000U)

Definition at line 6865 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG12_SHIFT

#define CCM_CCGR1_CG12_SHIFT (24U)

Definition at line 6866 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG13

#define CCM_CCGR1_CG13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)

Definition at line 6870 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG13_MASK

#define CCM_CCGR1_CG13_MASK (0xC000000U)

Definition at line 6868 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG13_SHIFT

#define CCM_CCGR1_CG13_SHIFT (26U)

Definition at line 6869 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG14

#define CCM_CCGR1_CG14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)

Definition at line 6873 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG14_MASK

#define CCM_CCGR1_CG14_MASK (0x30000000U)

Definition at line 6871 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG14_SHIFT

#define CCM_CCGR1_CG14_SHIFT (28U)

Definition at line 6872 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG15

#define CCM_CCGR1_CG15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)

Definition at line 6876 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG15_MASK

#define CCM_CCGR1_CG15_MASK (0xC0000000U)

Definition at line 6874 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG15_SHIFT

#define CCM_CCGR1_CG15_SHIFT (30U)

Definition at line 6875 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG1_MASK

#define CCM_CCGR1_CG1_MASK (0xCU)

Definition at line 6832 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG1_SHIFT

#define CCM_CCGR1_CG1_SHIFT (2U)

Definition at line 6833 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG2

#define CCM_CCGR1_CG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)

Definition at line 6837 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG2_MASK

#define CCM_CCGR1_CG2_MASK (0x30U)

Definition at line 6835 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG2_SHIFT

#define CCM_CCGR1_CG2_SHIFT (4U)

Definition at line 6836 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG3

#define CCM_CCGR1_CG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)

Definition at line 6840 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG3_MASK

#define CCM_CCGR1_CG3_MASK (0xC0U)

Definition at line 6838 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG3_SHIFT

#define CCM_CCGR1_CG3_SHIFT (6U)

Definition at line 6839 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG4

#define CCM_CCGR1_CG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)

Definition at line 6843 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG4_MASK

#define CCM_CCGR1_CG4_MASK (0x300U)

Definition at line 6841 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG4_SHIFT

#define CCM_CCGR1_CG4_SHIFT (8U)

Definition at line 6842 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG5

#define CCM_CCGR1_CG5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)

Definition at line 6846 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG5_MASK

#define CCM_CCGR1_CG5_MASK (0xC00U)

Definition at line 6844 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG5_SHIFT

#define CCM_CCGR1_CG5_SHIFT (10U)

Definition at line 6845 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG6

#define CCM_CCGR1_CG6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)

Definition at line 6849 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG6_MASK

#define CCM_CCGR1_CG6_MASK (0x3000U)

Definition at line 6847 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG6_SHIFT

#define CCM_CCGR1_CG6_SHIFT (12U)

Definition at line 6848 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG7

#define CCM_CCGR1_CG7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)

Definition at line 6852 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG7_MASK

#define CCM_CCGR1_CG7_MASK (0xC000U)

Definition at line 6850 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG7_SHIFT

#define CCM_CCGR1_CG7_SHIFT (14U)

Definition at line 6851 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG8

#define CCM_CCGR1_CG8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)

Definition at line 6855 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG8_MASK

#define CCM_CCGR1_CG8_MASK (0x30000U)

Definition at line 6853 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG8_SHIFT

#define CCM_CCGR1_CG8_SHIFT (16U)

Definition at line 6854 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG9

#define CCM_CCGR1_CG9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)

Definition at line 6858 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG9_MASK

#define CCM_CCGR1_CG9_MASK (0xC0000U)

Definition at line 6856 of file MIMXRT1062.h.

## ◆ CCM_CCGR1_CG9_SHIFT

#define CCM_CCGR1_CG9_SHIFT (18U)

Definition at line 6857 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG0

#define CCM_CCGR2_CG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)

Definition at line 6883 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG0_MASK

#define CCM_CCGR2_CG0_MASK (0x3U)

Definition at line 6881 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG0_SHIFT

#define CCM_CCGR2_CG0_SHIFT (0U)

Definition at line 6882 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG1

#define CCM_CCGR2_CG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)

Definition at line 6886 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG10

#define CCM_CCGR2_CG10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)

Definition at line 6913 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG10_MASK

#define CCM_CCGR2_CG10_MASK (0x300000U)

Definition at line 6911 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG10_SHIFT

#define CCM_CCGR2_CG10_SHIFT (20U)

Definition at line 6912 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG11

#define CCM_CCGR2_CG11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)

Definition at line 6916 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG11_MASK

#define CCM_CCGR2_CG11_MASK (0xC00000U)

Definition at line 6914 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG11_SHIFT

#define CCM_CCGR2_CG11_SHIFT (22U)

Definition at line 6915 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG12

#define CCM_CCGR2_CG12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)

Definition at line 6919 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG12_MASK

#define CCM_CCGR2_CG12_MASK (0x3000000U)

Definition at line 6917 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG12_SHIFT

#define CCM_CCGR2_CG12_SHIFT (24U)

Definition at line 6918 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG13

#define CCM_CCGR2_CG13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)

Definition at line 6922 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG13_MASK

#define CCM_CCGR2_CG13_MASK (0xC000000U)

Definition at line 6920 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG13_SHIFT

#define CCM_CCGR2_CG13_SHIFT (26U)

Definition at line 6921 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG14

#define CCM_CCGR2_CG14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)

Definition at line 6925 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG14_MASK

#define CCM_CCGR2_CG14_MASK (0x30000000U)

Definition at line 6923 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG14_SHIFT

#define CCM_CCGR2_CG14_SHIFT (28U)

Definition at line 6924 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG15

#define CCM_CCGR2_CG15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)

Definition at line 6928 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG15_MASK

#define CCM_CCGR2_CG15_MASK (0xC0000000U)

Definition at line 6926 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG15_SHIFT

#define CCM_CCGR2_CG15_SHIFT (30U)

Definition at line 6927 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG1_MASK

#define CCM_CCGR2_CG1_MASK (0xCU)

Definition at line 6884 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG1_SHIFT

#define CCM_CCGR2_CG1_SHIFT (2U)

Definition at line 6885 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG2

#define CCM_CCGR2_CG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)

Definition at line 6889 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG2_MASK

#define CCM_CCGR2_CG2_MASK (0x30U)

Definition at line 6887 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG2_SHIFT

#define CCM_CCGR2_CG2_SHIFT (4U)

Definition at line 6888 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG3

#define CCM_CCGR2_CG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)

Definition at line 6892 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG3_MASK

#define CCM_CCGR2_CG3_MASK (0xC0U)

Definition at line 6890 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG3_SHIFT

#define CCM_CCGR2_CG3_SHIFT (6U)

Definition at line 6891 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG4

#define CCM_CCGR2_CG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)

Definition at line 6895 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG4_MASK

#define CCM_CCGR2_CG4_MASK (0x300U)

Definition at line 6893 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG4_SHIFT

#define CCM_CCGR2_CG4_SHIFT (8U)

Definition at line 6894 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG5

#define CCM_CCGR2_CG5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)

Definition at line 6898 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG5_MASK

#define CCM_CCGR2_CG5_MASK (0xC00U)

Definition at line 6896 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG5_SHIFT

#define CCM_CCGR2_CG5_SHIFT (10U)

Definition at line 6897 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG6

#define CCM_CCGR2_CG6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)

Definition at line 6901 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG6_MASK

#define CCM_CCGR2_CG6_MASK (0x3000U)

Definition at line 6899 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG6_SHIFT

#define CCM_CCGR2_CG6_SHIFT (12U)

Definition at line 6900 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG7

#define CCM_CCGR2_CG7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)

Definition at line 6904 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG7_MASK

#define CCM_CCGR2_CG7_MASK (0xC000U)

Definition at line 6902 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG7_SHIFT

#define CCM_CCGR2_CG7_SHIFT (14U)

Definition at line 6903 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG8

#define CCM_CCGR2_CG8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)

Definition at line 6907 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG8_MASK

#define CCM_CCGR2_CG8_MASK (0x30000U)

Definition at line 6905 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG8_SHIFT

#define CCM_CCGR2_CG8_SHIFT (16U)

Definition at line 6906 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG9

#define CCM_CCGR2_CG9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)

Definition at line 6910 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG9_MASK

#define CCM_CCGR2_CG9_MASK (0xC0000U)

Definition at line 6908 of file MIMXRT1062.h.

## ◆ CCM_CCGR2_CG9_SHIFT

#define CCM_CCGR2_CG9_SHIFT (18U)

Definition at line 6909 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG0

#define CCM_CCGR3_CG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)

Definition at line 6935 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG0_MASK

#define CCM_CCGR3_CG0_MASK (0x3U)

Definition at line 6933 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG0_SHIFT

#define CCM_CCGR3_CG0_SHIFT (0U)

Definition at line 6934 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG1

#define CCM_CCGR3_CG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)

Definition at line 6938 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG10

#define CCM_CCGR3_CG10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)

Definition at line 6965 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG10_MASK

#define CCM_CCGR3_CG10_MASK (0x300000U)

Definition at line 6963 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG10_SHIFT

#define CCM_CCGR3_CG10_SHIFT (20U)

Definition at line 6964 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG11

#define CCM_CCGR3_CG11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)

Definition at line 6968 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG11_MASK

#define CCM_CCGR3_CG11_MASK (0xC00000U)

Definition at line 6966 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG11_SHIFT

#define CCM_CCGR3_CG11_SHIFT (22U)

Definition at line 6967 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG12

#define CCM_CCGR3_CG12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)

Definition at line 6971 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG12_MASK

#define CCM_CCGR3_CG12_MASK (0x3000000U)

Definition at line 6969 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG12_SHIFT

#define CCM_CCGR3_CG12_SHIFT (24U)

Definition at line 6970 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG13

#define CCM_CCGR3_CG13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)

Definition at line 6974 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG13_MASK

#define CCM_CCGR3_CG13_MASK (0xC000000U)

Definition at line 6972 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG13_SHIFT

#define CCM_CCGR3_CG13_SHIFT (26U)

Definition at line 6973 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG14

#define CCM_CCGR3_CG14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)

CG14 - The OCRAM clock cannot be turned off when the CM cache is running on this device.

Definition at line 6979 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG14_MASK

#define CCM_CCGR3_CG14_MASK (0x30000000U)

Definition at line 6975 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG14_SHIFT

#define CCM_CCGR3_CG14_SHIFT (28U)

Definition at line 6976 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG15

#define CCM_CCGR3_CG15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)

Definition at line 6982 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG15_MASK

#define CCM_CCGR3_CG15_MASK (0xC0000000U)

Definition at line 6980 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG15_SHIFT

#define CCM_CCGR3_CG15_SHIFT (30U)

Definition at line 6981 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG1_MASK

#define CCM_CCGR3_CG1_MASK (0xCU)

Definition at line 6936 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG1_SHIFT

#define CCM_CCGR3_CG1_SHIFT (2U)

Definition at line 6937 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG2

#define CCM_CCGR3_CG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)

Definition at line 6941 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG2_MASK

#define CCM_CCGR3_CG2_MASK (0x30U)

Definition at line 6939 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG2_SHIFT

#define CCM_CCGR3_CG2_SHIFT (4U)

Definition at line 6940 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG3

#define CCM_CCGR3_CG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)

Definition at line 6944 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG3_MASK

#define CCM_CCGR3_CG3_MASK (0xC0U)

Definition at line 6942 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG3_SHIFT

#define CCM_CCGR3_CG3_SHIFT (6U)

Definition at line 6943 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG4

#define CCM_CCGR3_CG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)

Definition at line 6947 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG4_MASK

#define CCM_CCGR3_CG4_MASK (0x300U)

Definition at line 6945 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG4_SHIFT

#define CCM_CCGR3_CG4_SHIFT (8U)

Definition at line 6946 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG5

#define CCM_CCGR3_CG5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)

Definition at line 6950 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG5_MASK

#define CCM_CCGR3_CG5_MASK (0xC00U)

Definition at line 6948 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG5_SHIFT

#define CCM_CCGR3_CG5_SHIFT (10U)

Definition at line 6949 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG6

#define CCM_CCGR3_CG6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)

Definition at line 6953 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG6_MASK

#define CCM_CCGR3_CG6_MASK (0x3000U)

Definition at line 6951 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG6_SHIFT

#define CCM_CCGR3_CG6_SHIFT (12U)

Definition at line 6952 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG7

#define CCM_CCGR3_CG7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)

Definition at line 6956 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG7_MASK

#define CCM_CCGR3_CG7_MASK (0xC000U)

Definition at line 6954 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG7_SHIFT

#define CCM_CCGR3_CG7_SHIFT (14U)

Definition at line 6955 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG8

#define CCM_CCGR3_CG8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)

Definition at line 6959 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG8_MASK

#define CCM_CCGR3_CG8_MASK (0x30000U)

Definition at line 6957 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG8_SHIFT

#define CCM_CCGR3_CG8_SHIFT (16U)

Definition at line 6958 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG9

#define CCM_CCGR3_CG9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)

Definition at line 6962 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG9_MASK

#define CCM_CCGR3_CG9_MASK (0xC0000U)

Definition at line 6960 of file MIMXRT1062.h.

## ◆ CCM_CCGR3_CG9_SHIFT

#define CCM_CCGR3_CG9_SHIFT (18U)

Definition at line 6961 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG0

#define CCM_CCGR4_CG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)

Definition at line 6989 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG0_MASK

#define CCM_CCGR4_CG0_MASK (0x3U)

Definition at line 6987 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG0_SHIFT

#define CCM_CCGR4_CG0_SHIFT (0U)

Definition at line 6988 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG1

#define CCM_CCGR4_CG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)

Definition at line 6992 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG10

#define CCM_CCGR4_CG10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)

Definition at line 7019 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG10_MASK

#define CCM_CCGR4_CG10_MASK (0x300000U)

Definition at line 7017 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG10_SHIFT

#define CCM_CCGR4_CG10_SHIFT (20U)

Definition at line 7018 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG11

#define CCM_CCGR4_CG11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)

Definition at line 7022 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG11_MASK

#define CCM_CCGR4_CG11_MASK (0xC00000U)

Definition at line 7020 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG11_SHIFT

#define CCM_CCGR4_CG11_SHIFT (22U)

Definition at line 7021 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG12

#define CCM_CCGR4_CG12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)

Definition at line 7025 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG12_MASK

#define CCM_CCGR4_CG12_MASK (0x3000000U)

Definition at line 7023 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG12_SHIFT

#define CCM_CCGR4_CG12_SHIFT (24U)

Definition at line 7024 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG13

#define CCM_CCGR4_CG13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)

Definition at line 7028 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG13_MASK

#define CCM_CCGR4_CG13_MASK (0xC000000U)

Definition at line 7026 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG13_SHIFT

#define CCM_CCGR4_CG13_SHIFT (26U)

Definition at line 7027 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG14

#define CCM_CCGR4_CG14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)

Definition at line 7031 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG14_MASK

#define CCM_CCGR4_CG14_MASK (0x30000000U)

Definition at line 7029 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG14_SHIFT

#define CCM_CCGR4_CG14_SHIFT (28U)

Definition at line 7030 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG15

#define CCM_CCGR4_CG15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)

Definition at line 7034 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG15_MASK

#define CCM_CCGR4_CG15_MASK (0xC0000000U)

Definition at line 7032 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG15_SHIFT

#define CCM_CCGR4_CG15_SHIFT (30U)

Definition at line 7033 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG1_MASK

#define CCM_CCGR4_CG1_MASK (0xCU)

Definition at line 6990 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG1_SHIFT

#define CCM_CCGR4_CG1_SHIFT (2U)

Definition at line 6991 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG2

#define CCM_CCGR4_CG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)

Definition at line 6995 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG2_MASK

#define CCM_CCGR4_CG2_MASK (0x30U)

Definition at line 6993 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG2_SHIFT

#define CCM_CCGR4_CG2_SHIFT (4U)

Definition at line 6994 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG3

#define CCM_CCGR4_CG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)

Definition at line 6998 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG3_MASK

#define CCM_CCGR4_CG3_MASK (0xC0U)

Definition at line 6996 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG3_SHIFT

#define CCM_CCGR4_CG3_SHIFT (6U)

Definition at line 6997 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG4

#define CCM_CCGR4_CG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)

Definition at line 7001 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG4_MASK

#define CCM_CCGR4_CG4_MASK (0x300U)

Definition at line 6999 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG4_SHIFT

#define CCM_CCGR4_CG4_SHIFT (8U)

Definition at line 7000 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG5

#define CCM_CCGR4_CG5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)

Definition at line 7004 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG5_MASK

#define CCM_CCGR4_CG5_MASK (0xC00U)

Definition at line 7002 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG5_SHIFT

#define CCM_CCGR4_CG5_SHIFT (10U)

Definition at line 7003 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG6

#define CCM_CCGR4_CG6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)

Definition at line 7007 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG6_MASK

#define CCM_CCGR4_CG6_MASK (0x3000U)

Definition at line 7005 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG6_SHIFT

#define CCM_CCGR4_CG6_SHIFT (12U)

Definition at line 7006 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG7

#define CCM_CCGR4_CG7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)

Definition at line 7010 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG7_MASK

#define CCM_CCGR4_CG7_MASK (0xC000U)

Definition at line 7008 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG7_SHIFT

#define CCM_CCGR4_CG7_SHIFT (14U)

Definition at line 7009 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG8

#define CCM_CCGR4_CG8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)

Definition at line 7013 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG8_MASK

#define CCM_CCGR4_CG8_MASK (0x30000U)

Definition at line 7011 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG8_SHIFT

#define CCM_CCGR4_CG8_SHIFT (16U)

Definition at line 7012 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG9

#define CCM_CCGR4_CG9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)

Definition at line 7016 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG9_MASK

#define CCM_CCGR4_CG9_MASK (0xC0000U)

Definition at line 7014 of file MIMXRT1062.h.

## ◆ CCM_CCGR4_CG9_SHIFT

#define CCM_CCGR4_CG9_SHIFT (18U)

Definition at line 7015 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG0

#define CCM_CCGR5_CG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)

Definition at line 7041 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG0_MASK

#define CCM_CCGR5_CG0_MASK (0x3U)

Definition at line 7039 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG0_SHIFT

#define CCM_CCGR5_CG0_SHIFT (0U)

Definition at line 7040 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG1

#define CCM_CCGR5_CG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)

Definition at line 7044 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG10

#define CCM_CCGR5_CG10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)

Definition at line 7071 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG10_MASK

#define CCM_CCGR5_CG10_MASK (0x300000U)

Definition at line 7069 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG10_SHIFT

#define CCM_CCGR5_CG10_SHIFT (20U)

Definition at line 7070 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG11

#define CCM_CCGR5_CG11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)

Definition at line 7074 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG11_MASK

#define CCM_CCGR5_CG11_MASK (0xC00000U)

Definition at line 7072 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG11_SHIFT

#define CCM_CCGR5_CG11_SHIFT (22U)

Definition at line 7073 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG12

#define CCM_CCGR5_CG12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)

Definition at line 7077 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG12_MASK

#define CCM_CCGR5_CG12_MASK (0x3000000U)

Definition at line 7075 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG12_SHIFT

#define CCM_CCGR5_CG12_SHIFT (24U)

Definition at line 7076 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG13

#define CCM_CCGR5_CG13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)

Definition at line 7080 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG13_MASK

#define CCM_CCGR5_CG13_MASK (0xC000000U)

Definition at line 7078 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG13_SHIFT

#define CCM_CCGR5_CG13_SHIFT (26U)

Definition at line 7079 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG14

#define CCM_CCGR5_CG14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)

Definition at line 7083 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG14_MASK

#define CCM_CCGR5_CG14_MASK (0x30000000U)

Definition at line 7081 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG14_SHIFT

#define CCM_CCGR5_CG14_SHIFT (28U)

Definition at line 7082 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG15

#define CCM_CCGR5_CG15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)

Definition at line 7086 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG15_MASK

#define CCM_CCGR5_CG15_MASK (0xC0000000U)

Definition at line 7084 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG15_SHIFT

#define CCM_CCGR5_CG15_SHIFT (30U)

Definition at line 7085 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG1_MASK

#define CCM_CCGR5_CG1_MASK (0xCU)

Definition at line 7042 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG1_SHIFT

#define CCM_CCGR5_CG1_SHIFT (2U)

Definition at line 7043 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG2

#define CCM_CCGR5_CG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)

Definition at line 7047 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG2_MASK

#define CCM_CCGR5_CG2_MASK (0x30U)

Definition at line 7045 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG2_SHIFT

#define CCM_CCGR5_CG2_SHIFT (4U)

Definition at line 7046 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG3

#define CCM_CCGR5_CG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)

Definition at line 7050 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG3_MASK

#define CCM_CCGR5_CG3_MASK (0xC0U)

Definition at line 7048 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG3_SHIFT

#define CCM_CCGR5_CG3_SHIFT (6U)

Definition at line 7049 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG4

#define CCM_CCGR5_CG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)

Definition at line 7053 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG4_MASK

#define CCM_CCGR5_CG4_MASK (0x300U)

Definition at line 7051 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG4_SHIFT

#define CCM_CCGR5_CG4_SHIFT (8U)

Definition at line 7052 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG5

#define CCM_CCGR5_CG5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)

Definition at line 7056 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG5_MASK

#define CCM_CCGR5_CG5_MASK (0xC00U)

Definition at line 7054 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG5_SHIFT

#define CCM_CCGR5_CG5_SHIFT (10U)

Definition at line 7055 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG6

#define CCM_CCGR5_CG6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)

Definition at line 7059 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG6_MASK

#define CCM_CCGR5_CG6_MASK (0x3000U)

Definition at line 7057 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG6_SHIFT

#define CCM_CCGR5_CG6_SHIFT (12U)

Definition at line 7058 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG7

#define CCM_CCGR5_CG7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)

Definition at line 7062 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG7_MASK

#define CCM_CCGR5_CG7_MASK (0xC000U)

Definition at line 7060 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG7_SHIFT

#define CCM_CCGR5_CG7_SHIFT (14U)

Definition at line 7061 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG8

#define CCM_CCGR5_CG8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)

Definition at line 7065 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG8_MASK

#define CCM_CCGR5_CG8_MASK (0x30000U)

Definition at line 7063 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG8_SHIFT

#define CCM_CCGR5_CG8_SHIFT (16U)

Definition at line 7064 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG9

#define CCM_CCGR5_CG9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)

Definition at line 7068 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG9_MASK

#define CCM_CCGR5_CG9_MASK (0xC0000U)

Definition at line 7066 of file MIMXRT1062.h.

## ◆ CCM_CCGR5_CG9_SHIFT

#define CCM_CCGR5_CG9_SHIFT (18U)

Definition at line 7067 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG0

#define CCM_CCGR6_CG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)

Definition at line 7093 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG0_MASK

#define CCM_CCGR6_CG0_MASK (0x3U)

Definition at line 7091 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG0_SHIFT

#define CCM_CCGR6_CG0_SHIFT (0U)

Definition at line 7092 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG1

#define CCM_CCGR6_CG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)

Definition at line 7096 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG10

#define CCM_CCGR6_CG10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)

Definition at line 7123 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG10_MASK

#define CCM_CCGR6_CG10_MASK (0x300000U)

Definition at line 7121 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG10_SHIFT

#define CCM_CCGR6_CG10_SHIFT (20U)

Definition at line 7122 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG11

#define CCM_CCGR6_CG11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)

Definition at line 7126 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG11_MASK

#define CCM_CCGR6_CG11_MASK (0xC00000U)

Definition at line 7124 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG11_SHIFT

#define CCM_CCGR6_CG11_SHIFT (22U)

Definition at line 7125 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG12

#define CCM_CCGR6_CG12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)

Definition at line 7129 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG12_MASK

#define CCM_CCGR6_CG12_MASK (0x3000000U)

Definition at line 7127 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG12_SHIFT

#define CCM_CCGR6_CG12_SHIFT (24U)

Definition at line 7128 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG13

#define CCM_CCGR6_CG13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)

Definition at line 7132 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG13_MASK

#define CCM_CCGR6_CG13_MASK (0xC000000U)

Definition at line 7130 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG13_SHIFT

#define CCM_CCGR6_CG13_SHIFT (26U)

Definition at line 7131 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG14

#define CCM_CCGR6_CG14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)

Definition at line 7135 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG14_MASK

#define CCM_CCGR6_CG14_MASK (0x30000000U)

Definition at line 7133 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG14_SHIFT

#define CCM_CCGR6_CG14_SHIFT (28U)

Definition at line 7134 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG15

#define CCM_CCGR6_CG15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)

Definition at line 7138 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG15_MASK

#define CCM_CCGR6_CG15_MASK (0xC0000000U)

Definition at line 7136 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG15_SHIFT

#define CCM_CCGR6_CG15_SHIFT (30U)

Definition at line 7137 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG1_MASK

#define CCM_CCGR6_CG1_MASK (0xCU)

Definition at line 7094 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG1_SHIFT

#define CCM_CCGR6_CG1_SHIFT (2U)

Definition at line 7095 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG2

#define CCM_CCGR6_CG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)

Definition at line 7099 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG2_MASK

#define CCM_CCGR6_CG2_MASK (0x30U)

Definition at line 7097 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG2_SHIFT

#define CCM_CCGR6_CG2_SHIFT (4U)

Definition at line 7098 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG3

#define CCM_CCGR6_CG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)

Definition at line 7102 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG3_MASK

#define CCM_CCGR6_CG3_MASK (0xC0U)

Definition at line 7100 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG3_SHIFT

#define CCM_CCGR6_CG3_SHIFT (6U)

Definition at line 7101 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG4

#define CCM_CCGR6_CG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)

Definition at line 7105 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG4_MASK

#define CCM_CCGR6_CG4_MASK (0x300U)

Definition at line 7103 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG4_SHIFT

#define CCM_CCGR6_CG4_SHIFT (8U)

Definition at line 7104 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG5

#define CCM_CCGR6_CG5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)

Definition at line 7108 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG5_MASK

#define CCM_CCGR6_CG5_MASK (0xC00U)

Definition at line 7106 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG5_SHIFT

#define CCM_CCGR6_CG5_SHIFT (10U)

Definition at line 7107 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG6

#define CCM_CCGR6_CG6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)

Definition at line 7111 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG6_MASK

#define CCM_CCGR6_CG6_MASK (0x3000U)

Definition at line 7109 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG6_SHIFT

#define CCM_CCGR6_CG6_SHIFT (12U)

Definition at line 7110 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG7

#define CCM_CCGR6_CG7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)

Definition at line 7114 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG7_MASK

#define CCM_CCGR6_CG7_MASK (0xC000U)

Definition at line 7112 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG7_SHIFT

#define CCM_CCGR6_CG7_SHIFT (14U)

Definition at line 7113 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG8

#define CCM_CCGR6_CG8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)

Definition at line 7117 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG8_MASK

#define CCM_CCGR6_CG8_MASK (0x30000U)

Definition at line 7115 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG8_SHIFT

#define CCM_CCGR6_CG8_SHIFT (16U)

Definition at line 7116 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG9

#define CCM_CCGR6_CG9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)

Definition at line 7120 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG9_MASK

#define CCM_CCGR6_CG9_MASK (0xC0000U)

Definition at line 7118 of file MIMXRT1062.h.

## ◆ CCM_CCGR6_CG9_SHIFT

#define CCM_CCGR6_CG9_SHIFT (18U)

Definition at line 7119 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG0

#define CCM_CCGR7_CG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG0_SHIFT)) & CCM_CCGR7_CG0_MASK)

Definition at line 7145 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG0_MASK

#define CCM_CCGR7_CG0_MASK (0x3U)

Definition at line 7143 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG0_SHIFT

#define CCM_CCGR7_CG0_SHIFT (0U)

Definition at line 7144 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG1

#define CCM_CCGR7_CG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG1_SHIFT)) & CCM_CCGR7_CG1_MASK)

Definition at line 7148 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG1_MASK

#define CCM_CCGR7_CG1_MASK (0xCU)

Definition at line 7146 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG1_SHIFT

#define CCM_CCGR7_CG1_SHIFT (2U)

Definition at line 7147 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG2

#define CCM_CCGR7_CG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG2_SHIFT)) & CCM_CCGR7_CG2_MASK)

Definition at line 7151 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG2_MASK

#define CCM_CCGR7_CG2_MASK (0x30U)

Definition at line 7149 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG2_SHIFT

#define CCM_CCGR7_CG2_SHIFT (4U)

Definition at line 7150 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG3

#define CCM_CCGR7_CG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG3_SHIFT)) & CCM_CCGR7_CG3_MASK)

Definition at line 7154 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG3_MASK

#define CCM_CCGR7_CG3_MASK (0xC0U)

Definition at line 7152 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG3_SHIFT

#define CCM_CCGR7_CG3_SHIFT (6U)

Definition at line 7153 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG4

#define CCM_CCGR7_CG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG4_SHIFT)) & CCM_CCGR7_CG4_MASK)

Definition at line 7157 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG4_MASK

#define CCM_CCGR7_CG4_MASK (0x300U)

Definition at line 7155 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG4_SHIFT

#define CCM_CCGR7_CG4_SHIFT (8U)

Definition at line 7156 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG5

#define CCM_CCGR7_CG5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG5_SHIFT)) & CCM_CCGR7_CG5_MASK)

Definition at line 7160 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG5_MASK

#define CCM_CCGR7_CG5_MASK (0xC00U)

Definition at line 7158 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG5_SHIFT

#define CCM_CCGR7_CG5_SHIFT (10U)

Definition at line 7159 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG6

#define CCM_CCGR7_CG6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG6_SHIFT)) & CCM_CCGR7_CG6_MASK)

Definition at line 7163 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG6_MASK

#define CCM_CCGR7_CG6_MASK (0x3000U)

Definition at line 7161 of file MIMXRT1062.h.

## ◆ CCM_CCGR7_CG6_SHIFT

#define CCM_CCGR7_CG6_SHIFT (12U)

Definition at line 7162 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLK_OUT_SEL

#define CCM_CCOSR_CLK_OUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)

CLK_OUT_SEL 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock

Definition at line 6693 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLK_OUT_SEL_MASK

#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)

Definition at line 6687 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLK_OUT_SEL_SHIFT

#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)

Definition at line 6688 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_DIV

#define CCM_CCOSR_CLKO1_DIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)

CLKO1_DIV 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 6679 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_DIV_MASK

#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)

Definition at line 6667 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_DIV_SHIFT

#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)

Definition at line 6668 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_EN

#define CCM_CCOSR_CLKO1_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)

CLKO1_EN 0b0..CCM_CLKO1 disabled. 0b1..CCM_CLKO1 enabled.

Definition at line 6686 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_EN_MASK

#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)

Definition at line 6680 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_EN_SHIFT

#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)

Definition at line 6681 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_SEL

#define CCM_CCOSR_CLKO1_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)

CLKO1_SEL 0b0000..USB1 PLL clock (divided by 2) 0b0001..SYS PLL clock (divided by 2) 0b0011..VIDEO PLL clock (divided by 2) 0b0101..semc_clk_root 0b0110..Reserved 0b1010..lcdif_pix_clk_root 0b1011..ahb_clk_root 0b1100..ipg_clk_root 0b1101..perclk_root 0b1110..ckil_sync_clk_root 0b1111..pll4_main_clk

Definition at line 6666 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_SEL_MASK

#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)

Definition at line 6651 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO1_SEL_SHIFT

#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)

Definition at line 6652 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_DIV

#define CCM_CCOSR_CLKO2_DIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)

CLKO2_DIV 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 6724 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_DIV_MASK

#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)

Definition at line 6712 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_DIV_SHIFT

#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)

Definition at line 6713 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_EN

#define CCM_CCOSR_CLKO2_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)

CLKO2_EN 0b0..CCM_CLKO2 disabled. 0b1..CCM_CLKO2 enabled.

Definition at line 6731 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_EN_MASK

#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)

Definition at line 6725 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_EN_SHIFT

#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)

Definition at line 6726 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_SEL

#define CCM_CCOSR_CLKO2_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)

CLKO2_SEL 0b00011..usdhc1_clk_root 0b00110..lpi2c_clk_root 0b01011..csi_clk_root 0b01110..osc_clk 0b10001..usdhc2_clk_root 0b10010..sai1_clk_root 0b10011..sai2_clk_root 0b10100..sai3_clk_root (shared with ADC1 and ADC2 alt_clk root) 0b10111..can_clk_root (FlexCAN, shared with CANFD) 0b11011..flexspi_clk_root 0b11100..uart_clk_root 0b11101..spdif0_clk_root 0b11111..Reserved

Definition at line 6711 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_SEL_MASK

#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)

Definition at line 6694 of file MIMXRT1062.h.

## ◆ CCM_CCOSR_CLKO2_SEL_SHIFT

#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)

Definition at line 6695 of file MIMXRT1062.h.

## ◆ CCM_CCR_COSC_EN

#define CCM_CCR_COSC_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)

COSC_EN 0b0..disable on chip oscillator 0b1..enable on chip oscillator

Definition at line 5341 of file MIMXRT1062.h.

## ◆ CCM_CCR_COSC_EN_MASK

#define CCM_CCR_COSC_EN_MASK (0x1000U)

Definition at line 5335 of file MIMXRT1062.h.

## ◆ CCM_CCR_COSC_EN_SHIFT

#define CCM_CCR_COSC_EN_SHIFT (12U)

Definition at line 5336 of file MIMXRT1062.h.

## ◆ CCM_CCR_OSCNT

#define CCM_CCR_OSCNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)

OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened.

Definition at line 5334 of file MIMXRT1062.h.

## ◆ CCM_CCR_OSCNT_MASK

#define CCM_CCR_OSCNT_MASK (0xFFU)

Definition at line 5326 of file MIMXRT1062.h.

## ◆ CCM_CCR_OSCNT_SHIFT

#define CCM_CCR_OSCNT_SHIFT (0U)

Definition at line 5327 of file MIMXRT1062.h.

## ◆ CCM_CCR_RBC_EN

#define CCM_CCR_RBC_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)

RBC_EN 0b1..REG_BYPASS_COUNTER enabled. 0b0..REG_BYPASS_COUNTER disabled

Definition at line 5356 of file MIMXRT1062.h.

## ◆ CCM_CCR_RBC_EN_MASK

#define CCM_CCR_RBC_EN_MASK (0x8000000U)

Definition at line 5350 of file MIMXRT1062.h.

## ◆ CCM_CCR_RBC_EN_SHIFT

#define CCM_CCR_RBC_EN_SHIFT (27U)

Definition at line 5351 of file MIMXRT1062.h.

## ◆ CCM_CCR_REG_BYPASS_COUNT

#define CCM_CCR_REG_BYPASS_COUNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)

REG_BYPASS_COUNT 0b000000..no delay 0b000001..1 CKIL clock period delay 0b111111..63 CKIL clock periods delay

Definition at line 5349 of file MIMXRT1062.h.

## ◆ CCM_CCR_REG_BYPASS_COUNT_MASK

#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)

Definition at line 5342 of file MIMXRT1062.h.

## ◆ CCM_CCR_REG_BYPASS_COUNT_SHIFT

#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)

Definition at line 5343 of file MIMXRT1062.h.

## ◆ CCM_CCSR_PLL3_SW_CLK_SEL

#define CCM_CCSR_PLL3_SW_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)

PLL3_SW_CLK_SEL 0b0..pll3_main_clk 0b1..pll3 bypass clock

Definition at line 5392 of file MIMXRT1062.h.

## ◆ CCM_CCSR_PLL3_SW_CLK_SEL_MASK

#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)

Definition at line 5386 of file MIMXRT1062.h.

## ◆ CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT

#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)

Definition at line 5387 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_PODF

#define CCM_CDCDR_FLEXIO1_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)

FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 6228 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_PODF_MASK

#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)

Definition at line 6216 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT

#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)

Definition at line 6217 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_PRED

#define CCM_CDCDR_FLEXIO1_CLK_PRED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)

FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 6241 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_PRED_MASK

#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)

Definition at line 6229 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT

#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)

Definition at line 6230 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_SEL

#define CCM_CDCDR_FLEXIO1_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)

FLEXIO1_CLK_SEL 0b00..derive clock from PLL4 0b01..derive clock from PLL3 PFD2 0b10..derive clock from PLL5 0b11..derive clock from pll3_sw_clk

Definition at line 6215 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_SEL_MASK

#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)

Definition at line 6207 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT

#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)

Definition at line 6208 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_PODF

#define CCM_CDCDR_SPDIF0_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)

SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 6263 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_PODF_MASK

#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)

Definition at line 6251 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT

#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)

Definition at line 6252 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_PRED

#define CCM_CDCDR_SPDIF0_CLK_PRED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)

SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 6276 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_PRED_MASK

#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)

Definition at line 6264 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT

#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)

Definition at line 6265 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_SEL

#define CCM_CDCDR_SPDIF0_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)

SPDIF0_CLK_SEL 0b00..derive clock from PLL4 0b01..derive clock from PLL3 PFD2 0b10..derive clock from PLL5 0b11..derive clock from pll3_sw_clk

Definition at line 6250 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_SEL_MASK

#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)

Definition at line 6242 of file MIMXRT1062.h.

## ◆ CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT

#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)

Definition at line 6243 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_AHB_PODF_BUSY

#define CCM_CDHIPR_AHB_PODF_BUSY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)

AHB_PODF_BUSY 0b0..divider is not busy and its value represents the actual division. 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied.

Definition at line 6428 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_AHB_PODF_BUSY_MASK

#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)

Definition at line 6421 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_AHB_PODF_BUSY_SHIFT

#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)

Definition at line 6422 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_ARM_PODF_BUSY

#define CCM_CDHIPR_ARM_PODF_BUSY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)

ARM_PODF_BUSY 0b0..divider is not busy and its value represents the actual division. 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied.

Definition at line 6452 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_ARM_PODF_BUSY_MASK

#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)

Definition at line 6445 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_ARM_PODF_BUSY_SHIFT

#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)

Definition at line 6446 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY

#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)

PERIPH2_CLK_SEL_BUSY 0b0..mux is not busy and its value represents the actual division. 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied.

Definition at line 6436 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK

#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)

Definition at line 6429 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT

#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)

Definition at line 6430 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_PERIPH_CLK_SEL_BUSY

#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)

PERIPH_CLK_SEL_BUSY 0b0..mux is not busy and its value represents the actual division. 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied.

Definition at line 6444 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK

#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)

Definition at line 6437 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT

#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)

Definition at line 6438 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_SEMC_PODF_BUSY

#define CCM_CDHIPR_SEMC_PODF_BUSY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)

SEMC_PODF_BUSY 0b0..divider is not busy and its value represents the actual division. 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied.

Definition at line 6420 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_SEMC_PODF_BUSY_MASK

#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)

Definition at line 6413 of file MIMXRT1062.h.

## ◆ CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT

#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)

Definition at line 6414 of file MIMXRT1062.h.

## ◆ CCM_CGPR_EFUSE_PROG_SUPPLY_GATE

#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)

EFUSE_PROG_SUPPLY_GATE 0b0..fuse programing supply voltage is gated off to the efuse module 0b1..allow fuse programing.

Definition at line 6749 of file MIMXRT1062.h.

## ◆ CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK

#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)

Definition at line 6743 of file MIMXRT1062.h.

## ◆ CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT

#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)

Definition at line 6744 of file MIMXRT1062.h.

## ◆ CCM_CGPR_FPL

#define CCM_CGPR_FPL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)

FPL - Fast PLL enable. 0b0..Engage PLL enable default way. 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.

Definition at line 6764 of file MIMXRT1062.h.

## ◆ CCM_CGPR_FPL_MASK

#define CCM_CGPR_FPL_MASK (0x10000U)

Definition at line 6758 of file MIMXRT1062.h.

## ◆ CCM_CGPR_FPL_SHIFT

#define CCM_CGPR_FPL_SHIFT (16U)

Definition at line 6759 of file MIMXRT1062.h.

## ◆ CCM_CGPR_INT_MEM_CLK_LPM

#define CCM_CGPR_INT_MEM_CLK_LPM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)

INT_MEM_CLK_LPM 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)

Definition at line 6772 of file MIMXRT1062.h.

## ◆ CCM_CGPR_INT_MEM_CLK_LPM_MASK

#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)

Definition at line 6765 of file MIMXRT1062.h.

## ◆ CCM_CGPR_INT_MEM_CLK_LPM_SHIFT

#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)

Definition at line 6766 of file MIMXRT1062.h.

## ◆ CCM_CGPR_PMIC_DELAY_SCALER

#define CCM_CGPR_PMIC_DELAY_SCALER | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)

PMIC_DELAY_SCALER 0b0..clock is not divided 0b1..clock is divided /8

Definition at line 6742 of file MIMXRT1062.h.

## ◆ CCM_CGPR_PMIC_DELAY_SCALER_MASK

#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)

Definition at line 6736 of file MIMXRT1062.h.

## ◆ CCM_CGPR_PMIC_DELAY_SCALER_SHIFT

#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)

Definition at line 6737 of file MIMXRT1062.h.

## ◆ CCM_CGPR_SYS_MEM_DS_CTRL

#define CCM_CGPR_SYS_MEM_DS_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)

SYS_MEM_DS_CTRL 0b00..Disable memory DS mode always 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode

Definition at line 6757 of file MIMXRT1062.h.

## ◆ CCM_CGPR_SYS_MEM_DS_CTRL_MASK

#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)

Definition at line 6750 of file MIMXRT1062.h.

## ◆ CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT

#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)

Definition at line 6751 of file MIMXRT1062.h.

## ◆ CCM_CIMR_ARM_PODF_LOADED

#define CCM_CIMR_ARM_PODF_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)

ARM_PODF_LOADED 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created 0b1..mask interrupt due to frequency change of arm_podf

Definition at line 6646 of file MIMXRT1062.h.

## ◆ CCM_CIMR_ARM_PODF_LOADED_MASK

#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)

Definition at line 6640 of file MIMXRT1062.h.

## ◆ CCM_CIMR_ARM_PODF_LOADED_SHIFT

#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)

Definition at line 6641 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_AHB_PODF_LOADED

#define CCM_CIMR_MASK_AHB_PODF_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)

MASK_AHB_PODF_LOADED 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created 0b1..mask interrupt due to frequency change of ahb_podf

Definition at line 6632 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_AHB_PODF_LOADED_MASK

#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)

Definition at line 6626 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT

#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)

Definition at line 6627 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_COSC_READY

#define CCM_CIMR_MASK_COSC_READY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)

MASK_COSC_READY 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created 0b1..mask interrupt due to on board oscillator ready

Definition at line 6611 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_COSC_READY_MASK

#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)

Definition at line 6605 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_COSC_READY_SHIFT

#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)

Definition at line 6606 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_LRF_PLL

#define CCM_CIMR_MASK_LRF_PLL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)

MASK_LRF_PLL 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created 0b1..mask interrupt due to lrf of PLLs

Definition at line 6604 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_LRF_PLL_MASK

#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)

Definition at line 6598 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_LRF_PLL_SHIFT

#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)

Definition at line 6599 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED

#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)

MASK_PERIPH2_CLK_SEL_LOADED 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created 0b1..mask interrupt due to update of periph2_clk_sel

Definition at line 6625 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK

#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)

Definition at line 6619 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT

#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)

Definition at line 6620 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED

#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)

MASK_PERIPH_CLK_SEL_LOADED 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created 0b1..mask interrupt due to update of periph_clk_sel

Definition at line 6639 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK

#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)

Definition at line 6633 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT

#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)

Definition at line 6634 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_SEMC_PODF_LOADED

#define CCM_CIMR_MASK_SEMC_PODF_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)

MASK_SEMC_PODF_LOADED 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created 0b1..mask interrupt due to frequency change of semc_podf

Definition at line 6618 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK

#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)

Definition at line 6612 of file MIMXRT1062.h.

## ◆ CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT

#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)

Definition at line 6613 of file MIMXRT1062.h.

## ◆ CCM_CISR_AHB_PODF_LOADED

#define CCM_CISR_AHB_PODF_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)

AHB_PODF_LOADED 0b0..interrupt is not generated due to frequency change of ahb_podf 0b1..interrupt generated due to frequency change of ahb_podf

Definition at line 6579 of file MIMXRT1062.h.

## ◆ CCM_CISR_AHB_PODF_LOADED_MASK

#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)

Definition at line 6573 of file MIMXRT1062.h.

## ◆ CCM_CISR_AHB_PODF_LOADED_SHIFT

#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)

Definition at line 6574 of file MIMXRT1062.h.

## ◆ CCM_CISR_ARM_PODF_LOADED

#define CCM_CISR_ARM_PODF_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)

ARM_PODF_LOADED 0b0..interrupt is not generated due to frequency change of arm_podf 0b1..interrupt generated due to frequency change of arm_podf

Definition at line 6593 of file MIMXRT1062.h.

## ◆ CCM_CISR_ARM_PODF_LOADED_MASK

#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)

Definition at line 6587 of file MIMXRT1062.h.

## ◆ CCM_CISR_ARM_PODF_LOADED_SHIFT

#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)

Definition at line 6588 of file MIMXRT1062.h.

## ◆ CCM_CISR_COSC_READY

#define CCM_CISR_COSC_READY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)

COSC_READY 0b0..interrupt is not generated due to on board oscillator ready 0b1..interrupt generated due to on board oscillator ready

Definition at line 6558 of file MIMXRT1062.h.

## ◆ CCM_CISR_COSC_READY_MASK

#define CCM_CISR_COSC_READY_MASK (0x40U)

Definition at line 6552 of file MIMXRT1062.h.

## ◆ CCM_CISR_COSC_READY_SHIFT

#define CCM_CISR_COSC_READY_SHIFT (6U)

Definition at line 6553 of file MIMXRT1062.h.

## ◆ CCM_CISR_LRF_PLL

#define CCM_CISR_LRF_PLL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)

LRF_PLL 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs

Definition at line 6551 of file MIMXRT1062.h.

## ◆ CCM_CISR_LRF_PLL_MASK

#define CCM_CISR_LRF_PLL_MASK (0x1U)

Definition at line 6545 of file MIMXRT1062.h.

## ◆ CCM_CISR_LRF_PLL_SHIFT

#define CCM_CISR_LRF_PLL_SHIFT (0U)

Definition at line 6546 of file MIMXRT1062.h.

## ◆ CCM_CISR_PERIPH2_CLK_SEL_LOADED

#define CCM_CISR_PERIPH2_CLK_SEL_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)

PERIPH2_CLK_SEL_LOADED 0b0..interrupt is not generated due to frequency change of periph2_clk_sel 0b1..interrupt generated due to frequency change of periph2_clk_sel

Definition at line 6572 of file MIMXRT1062.h.

## ◆ CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK

#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)

Definition at line 6566 of file MIMXRT1062.h.

## ◆ CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT

#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)

Definition at line 6567 of file MIMXRT1062.h.

## ◆ CCM_CISR_PERIPH_CLK_SEL_LOADED

#define CCM_CISR_PERIPH_CLK_SEL_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)

PERIPH_CLK_SEL_LOADED 0b0..interrupt is not generated due to update of periph_clk_sel. 0b1..interrupt generated due to update of periph_clk_sel.

Definition at line 6586 of file MIMXRT1062.h.

## ◆ CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK

#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)

Definition at line 6580 of file MIMXRT1062.h.

## ◆ CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT

#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)

Definition at line 6581 of file MIMXRT1062.h.

## ◆ CCM_CISR_SEMC_PODF_LOADED

#define CCM_CISR_SEMC_PODF_LOADED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)

SEMC_PODF_LOADED 0b0..interrupt is not generated due to frequency change of semc_podf 0b1..interrupt generated due to frequency change of semc_podf

Definition at line 6565 of file MIMXRT1062.h.

## ◆ CCM_CISR_SEMC_PODF_LOADED_MASK

#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)

Definition at line 6559 of file MIMXRT1062.h.

## ◆ CCM_CISR_SEMC_PODF_LOADED_SHIFT

#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)

Definition at line 6560 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_ARM_CLK_DIS_ON_LPM

#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)

ARM_CLK_DIS_ON_LPM 0b0..ARM clock enabled on wait mode. 0b1..ARM clock disabled on wait mode. .

Definition at line 6472 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK

#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)

Definition at line 6466 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT

#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)

Definition at line 6467 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_BYPASS_LPM_HS0

#define CCM_CLPCR_BYPASS_LPM_HS0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)

Definition at line 6519 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_BYPASS_LPM_HS0_MASK

#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)

Definition at line 6517 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_BYPASS_LPM_HS0_SHIFT

#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)

Definition at line 6518 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_BYPASS_LPM_HS1

#define CCM_CLPCR_BYPASS_LPM_HS1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)

Definition at line 6516 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_BYPASS_LPM_HS1_MASK

#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)

Definition at line 6514 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_BYPASS_LPM_HS1_SHIFT

#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)

Definition at line 6515 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_COSC_PWRDOWN

#define CCM_CLPCR_COSC_PWRDOWN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)

COSC_PWRDOWN 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.

Definition at line 6513 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_COSC_PWRDOWN_MASK

#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)

Definition at line 6507 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_COSC_PWRDOWN_SHIFT

#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)

Definition at line 6508 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_DIS_REF_OSC

#define CCM_CLPCR_DIS_REF_OSC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)

DIS_REF_OSC 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'

Definition at line 6490 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_DIS_REF_OSC_MASK

#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)

Definition at line 6484 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_DIS_REF_OSC_SHIFT

#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)

Definition at line 6485 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_LPM

#define CCM_CLPCR_LPM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)

LPM 0b00..Remain in run mode 0b01..Transfer to wait mode 0b10..Transfer to stop mode 0b11..Reserved

Definition at line 6465 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_LPM_MASK

#define CCM_CLPCR_LPM_MASK (0x3U)

Definition at line 6457 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_LPM_SHIFT

#define CCM_CLPCR_LPM_SHIFT (0U)

Definition at line 6458 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_CORE0_WFI

#define CCM_CLPCR_MASK_CORE0_WFI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)

MASK_CORE0_WFI 0b0..WFI of core0 is not masked 0b1..WFI of core0 is masked

Definition at line 6526 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_CORE0_WFI_MASK

#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)

Definition at line 6520 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_CORE0_WFI_SHIFT

#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)

Definition at line 6521 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_L2CC_IDLE

#define CCM_CLPCR_MASK_L2CC_IDLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)

MASK_L2CC_IDLE 0b1..L2CC IDLE is masked 0b0..L2CC IDLE is not masked

Definition at line 6540 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_L2CC_IDLE_MASK

#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)

Definition at line 6534 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_L2CC_IDLE_SHIFT

#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)

Definition at line 6535 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_SCU_IDLE

#define CCM_CLPCR_MASK_SCU_IDLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)

MASK_SCU_IDLE 0b1..SCU IDLE is masked 0b0..SCU IDLE is not masked

Definition at line 6533 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_SCU_IDLE_MASK

#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)

Definition at line 6527 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_MASK_SCU_IDLE_SHIFT

#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)

Definition at line 6528 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_SBYOS

#define CCM_CLPCR_SBYOS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)

SBYOS 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process.

Definition at line 6483 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_SBYOS_MASK

#define CCM_CLPCR_SBYOS_MASK (0x40U)

Definition at line 6473 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_SBYOS_SHIFT

#define CCM_CLPCR_SBYOS_SHIFT (6U)

Definition at line 6474 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_STBY_COUNT

#define CCM_CLPCR_STBY_COUNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)

STBY_COUNT 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles

Definition at line 6506 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_STBY_COUNT_MASK

#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)

Definition at line 6498 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_STBY_COUNT_SHIFT

#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)

Definition at line 6499 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_VSTBY

#define CCM_CLPCR_VSTBY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)

VSTBY 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').

Definition at line 6497 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_VSTBY_MASK

#define CCM_CLPCR_VSTBY_MASK (0x100U)

Definition at line 6491 of file MIMXRT1062.h.

## ◆ CCM_CLPCR_VSTBY_SHIFT

#define CCM_CLPCR_VSTBY_SHIFT (8U)

Definition at line 6492 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CAN1_CPI

#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)

MOD_EN_OV_CAN1_CPI 0b0..don't overide module enable signal 0b1..overide module enable signal

Definition at line 7216 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK

#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)

Definition at line 7210 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT

#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)

Definition at line 7211 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CAN2_CPI

#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)

MOD_EN_OV_CAN2_CPI 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 7209 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK

#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)

Definition at line 7203 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT

#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)

Definition at line 7204 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CANFD_CPI

#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK)

MOD_EN_OV_CANFD_CPI 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 7202 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK

#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK (0x400U)

Definition at line 7196 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT

#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT (10U)

Definition at line 7197 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_GPT

#define CCM_CMEOR_MOD_EN_OV_GPT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)

MOD_EN_OV_GPT 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 7174 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_GPT_MASK

#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)

Definition at line 7168 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_GPT_SHIFT

#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)

Definition at line 7169 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_PIT

#define CCM_CMEOR_MOD_EN_OV_PIT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)

MOD_EN_OV_PIT 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 7181 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_PIT_MASK

#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)

Definition at line 7175 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_PIT_SHIFT

#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)

Definition at line 7176 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_TRNG

#define CCM_CMEOR_MOD_EN_OV_TRNG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)

MOD_EN_OV_TRNG 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 7195 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_TRNG_MASK

#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)

Definition at line 7189 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT

#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)

Definition at line 7190 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_USDHC

#define CCM_CMEOR_MOD_EN_USDHC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)

MOD_EN_USDHC 0b0..don't override module enable signal 0b1..override module enable signal

Definition at line 7188 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_USDHC_MASK

#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)

Definition at line 7182 of file MIMXRT1062.h.

## ◆ CCM_CMEOR_MOD_EN_USDHC_SHIFT

#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)

Definition at line 7183 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_FLEXIO2_CLK_PODF

#define CCM_CS1CDR_FLEXIO2_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)

FLEXIO2_CLK_PODF - Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated. 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 3 0b011..Divide by 4 0b100..Divide by 5 0b101..Divide by 6 0b110..Divide by 7 0b111..Divide by 8

Definition at line 6115 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK

#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)

Definition at line 6103 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT

#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)

Definition at line 6104 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_FLEXIO2_CLK_PRED

#define CCM_CS1CDR_FLEXIO2_CLK_PRED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)

FLEXIO2_CLK_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 6019 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK

#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)

Definition at line 6007 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT

#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)

Definition at line 6008 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI1_CLK_PODF

#define CCM_CS1CDR_SAI1_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)

SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 5993 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI1_CLK_PODF_MASK

#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)

Definition at line 5924 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI1_CLK_PODF_SHIFT

#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)

Definition at line 5925 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI1_CLK_PRED

#define CCM_CS1CDR_SAI1_CLK_PRED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)

SAI1_CLK_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 6006 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI1_CLK_PRED_MASK

#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)

Definition at line 5994 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI1_CLK_PRED_SHIFT

#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)

Definition at line 5995 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI3_CLK_PODF

#define CCM_CS1CDR_SAI3_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)

SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 6089 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI3_CLK_PODF_MASK

#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)

Definition at line 6020 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI3_CLK_PODF_SHIFT

#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)

Definition at line 6021 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI3_CLK_PRED

#define CCM_CS1CDR_SAI3_CLK_PRED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)

SAI3_CLK_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 6102 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI3_CLK_PRED_MASK

#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)

Definition at line 6090 of file MIMXRT1062.h.

## ◆ CCM_CS1CDR_SAI3_CLK_PRED_SHIFT

#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)

Definition at line 6091 of file MIMXRT1062.h.

## ◆ CCM_CS2CDR_SAI2_CLK_PODF

#define CCM_CS2CDR_SAI2_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)

SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 6189 of file MIMXRT1062.h.

## ◆ CCM_CS2CDR_SAI2_CLK_PODF_MASK

#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)

Definition at line 6120 of file MIMXRT1062.h.

## ◆ CCM_CS2CDR_SAI2_CLK_PODF_SHIFT

#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)

Definition at line 6121 of file MIMXRT1062.h.

## ◆ CCM_CS2CDR_SAI2_CLK_PRED

#define CCM_CS2CDR_SAI2_CLK_PRED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)

SAI2_CLK_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 6202 of file MIMXRT1062.h.

## ◆ CCM_CS2CDR_SAI2_CLK_PRED_MASK

#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)

Definition at line 6190 of file MIMXRT1062.h.

## ◆ CCM_CS2CDR_SAI2_CLK_PRED_SHIFT

#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)

Definition at line 6191 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_TRACE_PODF

#define CCM_CSCDR1_TRACE_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)

TRACE_PODF 0b00..divide by 1 0b01..divide by 2 0b10..divide by 3 0b11..divide by 4

Definition at line 5919 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_TRACE_PODF_MASK

#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)

Definition at line 5911 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_TRACE_PODF_SHIFT

#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)

Definition at line 5912 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_UART_CLK_PODF

#define CCM_CSCDR1_UART_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)

UART_CLK_PODF - Divider for uart clock podf. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 5877 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_UART_CLK_PODF_MASK

#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)

Definition at line 5809 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_UART_CLK_PODF_SHIFT

#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)

Definition at line 5810 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_UART_CLK_SEL

#define CCM_CSCDR1_UART_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)

UART_CLK_SEL 0b0..derive clock from pll3_80m 0b1..derive clock from osc_clk

Definition at line 5884 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_UART_CLK_SEL_MASK

#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)

Definition at line 5878 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_UART_CLK_SEL_SHIFT

#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)

Definition at line 5879 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_USDHC1_PODF

#define CCM_CSCDR1_USDHC1_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)

USDHC1_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5897 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_USDHC1_PODF_MASK

#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)

Definition at line 5885 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_USDHC1_PODF_SHIFT

#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)

Definition at line 5886 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_USDHC2_PODF

#define CCM_CSCDR1_USDHC2_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)

USDHC2_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5910 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_USDHC2_PODF_MASK

#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)

Definition at line 5898 of file MIMXRT1062.h.

## ◆ CCM_CSCDR1_USDHC2_PODF_SHIFT

#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)

Definition at line 5899 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LCDIF_PRE_CLK_SEL

#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)

LCDIF_PRE_CLK_SEL 0b000..derive clock from PLL2 0b001..derive clock from PLL3 PFD3 0b010..derive clock from PLL5 0b011..derive clock from PLL2 PFD0 0b100..derive clock from PLL2 PFD1 0b101..derive clock from PLL3 PFD1

Definition at line 6304 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK

#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)

Definition at line 6294 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT

#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)

Definition at line 6295 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LCDIF_PRED

#define CCM_CSCDR2_LCDIF_PRED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)

LCDIF_PRED 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 6293 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LCDIF_PRED_MASK

#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)

Definition at line 6281 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LCDIF_PRED_SHIFT

#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)

Definition at line 6282 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LPI2C_CLK_PODF

#define CCM_CSCDR2_LPI2C_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)

LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 6382 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LPI2C_CLK_PODF_MASK

#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)

Definition at line 6312 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT

#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)

Definition at line 6313 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LPI2C_CLK_SEL

#define CCM_CSCDR2_LPI2C_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)

LPI2C_CLK_SEL 0b0..derive clock from pll3_60m 0b1..derive clock from osc_clk

Definition at line 6311 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LPI2C_CLK_SEL_MASK

#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)

Definition at line 6305 of file MIMXRT1062.h.

## ◆ CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT

#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)

Definition at line 6306 of file MIMXRT1062.h.

## ◆ CCM_CSCDR3_CSI_CLK_SEL

#define CCM_CSCDR3_CSI_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)

CSI_CLK_SEL 0b00..derive clock from osc_clk (24M) 0b01..derive clock from PLL2 PFD2 0b10..derive clock from pll3_120M 0b11..derive clock from PLL3 PFD1

Definition at line 6395 of file MIMXRT1062.h.

## ◆ CCM_CSCDR3_CSI_CLK_SEL_MASK

#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)

Definition at line 6387 of file MIMXRT1062.h.

## ◆ CCM_CSCDR3_CSI_CLK_SEL_SHIFT

#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)

Definition at line 6388 of file MIMXRT1062.h.

## ◆ CCM_CSCDR3_CSI_PODF

#define CCM_CSCDR3_CSI_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)

CSI_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 6408 of file MIMXRT1062.h.

## ◆ CCM_CSCDR3_CSI_PODF_MASK

#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)

Definition at line 6396 of file MIMXRT1062.h.

## ◆ CCM_CSCDR3_CSI_PODF_SHIFT

#define CCM_CSCDR3_CSI_PODF_SHIFT (11U)

Definition at line 6397 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_FLEXSPI_CLK_SEL

#define CCM_CSCMR1_FLEXSPI_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)

FLEXSPI_CLK_SEL 0b00..derive clock from semc_clk_root_pre 0b01..derive clock from pll3_sw_clk 0b10..derive clock from PLL2 PFD2 0b11..derive clock from PLL3 PFD0

Definition at line 5713 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK

#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)

Definition at line 5705 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT

#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)

Definition at line 5706 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_FLEXSPI_PODF

#define CCM_CSCMR1_FLEXSPI_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)

FLEXSPI_PODF 0b000..divide by 1 0b001..divide by 2 0b010..divide by 3 0b011..divide by 4 0b100..divide by 5 0b101..divide by 6 0b110..divide by 7 0b111..divide by 8

Definition at line 5704 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_FLEXSPI_PODF_MASK

#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)

Definition at line 5692 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_FLEXSPI_PODF_SHIFT

#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)

Definition at line 5693 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_PERCLK_CLK_SEL

#define CCM_CSCMR1_PERCLK_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)

PERCLK_CLK_SEL 0b0..derive clock from ipg clk root 0b1..derive clock from osc_clk

Definition at line 5650 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_PERCLK_CLK_SEL_MASK

#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)

Definition at line 5644 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT

#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)

Definition at line 5645 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_PERCLK_PODF

#define CCM_CSCMR1_PERCLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)

PERCLK_PODF - Divider for perclk podf. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 5643 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_PERCLK_PODF_MASK

#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)

Definition at line 5575 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_PERCLK_PODF_SHIFT

#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)

Definition at line 5576 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI1_CLK_SEL

#define CCM_CSCMR1_SAI1_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)

SAI1_CLK_SEL 0b00..derive clock from PLL3 PFD2 0b01..derive clock from PLL5 0b10..derive clock from PLL4 0b11..Reserved

Definition at line 5659 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI1_CLK_SEL_MASK

#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)

Definition at line 5651 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI1_CLK_SEL_SHIFT

#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)

Definition at line 5652 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI2_CLK_SEL

#define CCM_CSCMR1_SAI2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)

SAI2_CLK_SEL 0b00..derive clock from PLL3 PFD2 0b01..derive clock from PLL5 0b10..derive clock from PLL4 0b11..Reserved

Definition at line 5668 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI2_CLK_SEL_MASK

#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)

Definition at line 5660 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI2_CLK_SEL_SHIFT

#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)

Definition at line 5661 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI3_CLK_SEL

#define CCM_CSCMR1_SAI3_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)

SAI3_CLK_SEL 0b00..derive clock from PLL3 PFD2 0b01..derive clock from PLL5 0b10..derive clock from PLL4 0b11..Reserved

Definition at line 5677 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI3_CLK_SEL_MASK

#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)

Definition at line 5669 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_SAI3_CLK_SEL_SHIFT

#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)

Definition at line 5670 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_USDHC1_CLK_SEL

#define CCM_CSCMR1_USDHC1_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)

USDHC1_CLK_SEL 0b0..derive clock from PLL2 PFD2 0b1..derive clock from PLL2 PFD0

Definition at line 5684 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_USDHC1_CLK_SEL_MASK

#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)

Definition at line 5678 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT

#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)

Definition at line 5679 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_USDHC2_CLK_SEL

#define CCM_CSCMR1_USDHC2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)

USDHC2_CLK_SEL 0b0..derive clock from PLL2 PFD2 0b1..derive clock from PLL2 PFD0

Definition at line 5691 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_USDHC2_CLK_SEL_MASK

#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)

Definition at line 5685 of file MIMXRT1062.h.

## ◆ CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT

#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)

Definition at line 5686 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_CAN_CLK_PODF

#define CCM_CSCMR2_CAN_CLK_PODF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)

CAN_CLK_PODF - Divider for CAN/CANFD clock podf. 0b000000..Divide by 1 0b000001..Divide by 2 0b000010..Divide by 3 0b000011..Divide by 4 0b000100..Divide by 5 0b000101..Divide by 6 0b000110..Divide by 7 0b000111..Divide by 8 0b001000..Divide by 9 0b001001..Divide by 10 0b001010..Divide by 11 0b001011..Divide by 12 0b001100..Divide by 13 0b001101..Divide by 14 0b001110..Divide by 15 0b001111..Divide by 16 0b010000..Divide by 17 0b010001..Divide by 18 0b010010..Divide by 19 0b010011..Divide by 20 0b010100..Divide by 21 0b010101..Divide by 22 0b010110..Divide by 23 0b010111..Divide by 24 0b011000..Divide by 25 0b011001..Divide by 26 0b011010..Divide by 27 0b011011..Divide by 28 0b011100..Divide by 29 0b011101..Divide by 30 0b011110..Divide by 31 0b011111..Divide by 32 0b100000..Divide by 33 0b100001..Divide by 34 0b100010..Divide by 35 0b100011..Divide by 36 0b100100..Divide by 37 0b100101..Divide by 38 0b100110..Divide by 39 0b100111..Divide by 40 0b101000..Divide by 41 0b101001..Divide by 42 0b101010..Divide by 43 0b101011..Divide by 44 0b101100..Divide by 45 0b101101..Divide by 46 0b101110..Divide by 47 0b101111..Divide by 48 0b110000..Divide by 49 0b110001..Divide by 50 0b110010..Divide by 51 0b110011..Divide by 52 0b110100..Divide by 53 0b110101..Divide by 54 0b110110..Divide by 55 0b110111..Divide by 56 0b111000..Divide by 57 0b111001..Divide by 58 0b111010..Divide by 59 0b111011..Divide by 60 0b111100..Divide by 61 0b111101..Divide by 62 0b111110..Divide by 63 0b111111..Divide by 64

Definition at line 5786 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_CAN_CLK_PODF_MASK

#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)

Definition at line 5718 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_CAN_CLK_PODF_SHIFT

#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)

Definition at line 5719 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_CAN_CLK_SEL

#define CCM_CSCMR2_CAN_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)

CAN_CLK_SEL 0b00..derive clock from pll3_sw_clk divided clock (60M) 0b01..derive clock from osc_clk (24M) 0b10..derive clock from pll3_sw_clk divided clock (80M) 0b11..Disable FlexCAN clock

Definition at line 5795 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_CAN_CLK_SEL_MASK

#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)

Definition at line 5787 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_CAN_CLK_SEL_SHIFT

#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)

Definition at line 5788 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_FLEXIO2_CLK_SEL

#define CCM_CSCMR2_FLEXIO2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)

FLEXIO2_CLK_SEL 0b00..derive clock from PLL4 divided clock 0b01..derive clock from PLL3 PFD2 clock 0b10..derive clock from PLL5 clock 0b11..derive clock from pll3_sw_clk

Definition at line 5804 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK

#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)

Definition at line 5796 of file MIMXRT1062.h.

## ◆ CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT

#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)

Definition at line 5797 of file MIMXRT1062.h.

## ◆ CCM_CSR_CAMP2_READY

#define CCM_CSR_CAMP2_READY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)

CAMP2_READY 0b0..CAMP2 is not ready. 0b1..CAMP2 is ready.

Definition at line 5374 of file MIMXRT1062.h.

## ◆ CCM_CSR_CAMP2_READY_MASK

#define CCM_CSR_CAMP2_READY_MASK (0x8U)

Definition at line 5368 of file MIMXRT1062.h.

## ◆ CCM_CSR_CAMP2_READY_SHIFT

#define CCM_CSR_CAMP2_READY_SHIFT (3U)

Definition at line 5369 of file MIMXRT1062.h.

## ◆ CCM_CSR_COSC_READY

#define CCM_CSR_COSC_READY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)

COSC_READY 0b0..on board oscillator is not ready. 0b1..on board oscillator is ready.

Definition at line 5381 of file MIMXRT1062.h.

## ◆ CCM_CSR_COSC_READY_MASK

#define CCM_CSR_COSC_READY_MASK (0x20U)

Definition at line 5375 of file MIMXRT1062.h.

## ◆ CCM_CSR_COSC_READY_SHIFT

#define CCM_CSR_COSC_READY_SHIFT (5U)

Definition at line 5376 of file MIMXRT1062.h.

## ◆ CCM_CSR_REF_EN_B

#define CCM_CSR_REF_EN_B | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)

REF_EN_B 0b0..value of CCM_REF_EN_B is '0' 0b1..value of CCM_REF_EN_B is '1'

Definition at line 5367 of file MIMXRT1062.h.

## ◆ CCM_CSR_REF_EN_B_MASK

#define CCM_CSR_REF_EN_B_MASK (0x1U)

Definition at line 5361 of file MIMXRT1062.h.

## ◆ CCM_CSR_REF_EN_B_SHIFT

#define CCM_CSR_REF_EN_B_SHIFT (0U)

Definition at line 5362 of file MIMXRT1062.h.