Callisto4Bootloader: System Control Block (SCB)

Callisto4Bootloader

Modules | Data Structures
System Control Block (SCB)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC)

Type definitions for the System Control Block Registers. More...

## Modules

| System Controls not in SCB (SCnSCB)
| Type definitions for the System Control and ID Register not in the SCB.

## Data Structures

struct | SCB_Type
| Structure type to access the System Control Block (SCB). More...
#define | SCB_CPUID_IMPLEMENTER_Pos 24U
#define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
#define | SCB_CPUID_VARIANT_Pos 20U
#define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
#define | SCB_CPUID_ARCHITECTURE_Pos 16U
#define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
#define | SCB_CPUID_PARTNO_Pos 4U
#define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
#define | SCB_CPUID_REVISION_Pos 0U
#define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
#define | SCB_ICSR_PENDNMISET_Pos 31U
#define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
#define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
#define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
#define | SCB_ICSR_PENDNMICLR_Pos 30U
#define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
#define | SCB_ICSR_PENDSVSET_Pos 28U
#define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
#define | SCB_ICSR_PENDSVCLR_Pos 27U
#define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
#define | SCB_ICSR_PENDSTSET_Pos 26U
#define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
#define | SCB_ICSR_PENDSTCLR_Pos 25U
#define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
#define | SCB_ICSR_STTNS_Pos 24U
#define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
#define | SCB_ICSR_ISRPREEMPT_Pos 23U
#define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
#define | SCB_ICSR_ISRPENDING_Pos 22U
#define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
#define | SCB_ICSR_VECTPENDING_Pos 12U
#define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
#define | SCB_ICSR_RETTOBASE_Pos 11U
#define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
#define | SCB_ICSR_VECTACTIVE_Pos 0U
#define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
#define | SCB_VTOR_TBLOFF_Pos 7U
#define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
#define | SCB_AIRCR_VECTKEY_Pos 16U
#define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
#define | SCB_AIRCR_VECTKEYSTAT_Pos 16U
#define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
#define | SCB_AIRCR_ENDIANESS_Pos 15U
#define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
#define | SCB_AIRCR_PRIS_Pos 14U
#define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
#define | SCB_AIRCR_BFHFNMINS_Pos 13U
#define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
#define | SCB_AIRCR_PRIGROUP_Pos 8U
#define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
#define | SCB_AIRCR_SYSRESETREQS_Pos 3U
#define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
#define | SCB_AIRCR_SYSRESETREQ_Pos 2U
#define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
#define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U
#define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
#define | SCB_SCR_SEVONPEND_Pos 4U
#define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
#define | SCB_SCR_SLEEPDEEPS_Pos 3U
#define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
#define | SCB_SCR_SLEEPDEEP_Pos 2U
#define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
#define | SCB_SCR_SLEEPONEXIT_Pos 1U
#define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
#define | SCB_CCR_BP_Pos 18U
#define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
#define | SCB_CCR_IC_Pos 17U
#define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
#define | SCB_CCR_DC_Pos 16U
#define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
#define | SCB_CCR_STKOFHFNMIGN_Pos 10U
#define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
#define | SCB_CCR_BFHFNMIGN_Pos 8U
#define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
#define | SCB_CCR_DIV_0_TRP_Pos 4U
#define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
#define | SCB_CCR_UNALIGN_TRP_Pos 3U
#define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
#define | SCB_CCR_USERSETMPEND_Pos 1U
#define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
#define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U
#define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
#define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
#define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
#define | SCB_SHCSR_SECUREFAULTENA_Pos 19U
#define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
#define | SCB_SHCSR_USGFAULTENA_Pos 18U
#define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
#define | SCB_SHCSR_BUSFAULTENA_Pos 17U
#define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
#define | SCB_SHCSR_MEMFAULTENA_Pos 16U
#define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
#define | SCB_SHCSR_SVCALLPENDED_Pos 15U
#define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
#define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U
#define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
#define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U
#define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
#define | SCB_SHCSR_USGFAULTPENDED_Pos 12U
#define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
#define | SCB_SHCSR_SYSTICKACT_Pos 11U
#define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
#define | SCB_SHCSR_PENDSVACT_Pos 10U
#define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
#define | SCB_SHCSR_MONITORACT_Pos 8U
#define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
#define | SCB_SHCSR_SVCALLACT_Pos 7U
#define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
#define | SCB_SHCSR_NMIACT_Pos 5U
#define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
#define | SCB_SHCSR_SECUREFAULTACT_Pos 4U
#define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
#define | SCB_SHCSR_USGFAULTACT_Pos 3U
#define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
#define | SCB_SHCSR_HARDFAULTACT_Pos 2U
#define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
#define | SCB_SHCSR_BUSFAULTACT_Pos 1U
#define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
#define | SCB_SHCSR_MEMFAULTACT_Pos 0U
#define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
#define | SCB_CFSR_USGFAULTSR_Pos 16U
#define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
#define | SCB_CFSR_BUSFAULTSR_Pos 8U
#define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
#define | SCB_CFSR_MEMFAULTSR_Pos 0U
#define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
#define | SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
#define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
#define | SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
#define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
#define | SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
#define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
#define | SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
#define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
#define | SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
#define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
#define | SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
#define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
#define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
#define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
#define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
#define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
#define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
#define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
#define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
#define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
#define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
#define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
#define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
#define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
#define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
#define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
#define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
#define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
#define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
#define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
#define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
#define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
#define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
#define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
#define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
#define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
#define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
#define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
#define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
#define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
#define | SCB_HFSR_DEBUGEVT_Pos 31U
#define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
#define | SCB_HFSR_FORCED_Pos 30U
#define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
#define | SCB_HFSR_VECTTBL_Pos 1U
#define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
#define | SCB_DFSR_EXTERNAL_Pos 4U
#define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
#define | SCB_DFSR_VCATCH_Pos 3U
#define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
#define | SCB_DFSR_DWTTRAP_Pos 2U
#define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
#define | SCB_DFSR_BKPT_Pos 1U
#define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
#define | SCB_DFSR_HALTED_Pos 0U
#define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
#define | SCB_NSACR_CP11_Pos 11U
#define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
#define | SCB_NSACR_CP10_Pos 10U
#define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
#define | SCB_NSACR_CPn_Pos 0U
#define | SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
#define | SCB_CLIDR_LOUU_Pos 27U
#define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
#define | SCB_CLIDR_LOC_Pos 24U
#define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
#define | SCB_CTR_FORMAT_Pos 29U
#define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
#define | SCB_CTR_CWG_Pos 24U
#define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
#define | SCB_CTR_ERG_Pos 20U
#define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
#define | SCB_CTR_DMINLINE_Pos 16U
#define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
#define | SCB_CTR_IMINLINE_Pos 0U
#define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
#define | SCB_CCSIDR_WT_Pos 31U
#define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
#define | SCB_CCSIDR_WB_Pos 30U
#define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
#define | SCB_CCSIDR_RA_Pos 29U
#define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
#define | SCB_CCSIDR_WA_Pos 28U
#define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
#define | SCB_CCSIDR_NUMSETS_Pos 13U
#define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
#define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
#define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define | SCB_CCSIDR_LINESIZE_Pos 0U
#define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
#define | SCB_CSSELR_LEVEL_Pos 1U
#define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
#define | SCB_CSSELR_IND_Pos 0U
#define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
#define | SCB_STIR_INTID_Pos 0U
#define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
#define | SCB_DCISW_WAY_Pos 30U
#define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
#define | SCB_DCISW_SET_Pos 5U
#define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
#define | SCB_DCCSW_WAY_Pos 30U
#define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
#define | SCB_DCCSW_SET_Pos 5U
#define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
#define | SCB_DCCISW_WAY_Pos 30U
#define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
#define | SCB_DCCISW_SET_Pos 5U
#define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
#define | SCB_ITCMCR_SZ_Pos 3U
#define | SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
#define | SCB_ITCMCR_RETEN_Pos 2U
#define | SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
#define | SCB_ITCMCR_RMW_Pos 1U
#define | SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
#define | SCB_ITCMCR_EN_Pos 0U
#define | SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
#define | SCB_DTCMCR_SZ_Pos 3U
#define | SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
#define | SCB_DTCMCR_RETEN_Pos 2U
#define | SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
#define | SCB_DTCMCR_RMW_Pos 1U
#define | SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
#define | SCB_DTCMCR_EN_Pos 0U
#define | SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
#define | SCB_AHBPCR_SZ_Pos 1U
#define | SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
#define | SCB_AHBPCR_EN_Pos 0U
#define | SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
#define | SCB_CACR_FORCEWT_Pos 2U
#define | SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
#define | SCB_CACR_ECCEN_Pos 1U
#define | SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
#define | SCB_CACR_SIWT_Pos 0U
#define | SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
#define | SCB_AHBSCR_INITCOUNT_Pos 11U
#define | SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
#define | SCB_AHBSCR_TPRI_Pos 2U
#define | SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
#define | SCB_AHBSCR_CTL_Pos 0U
#define | SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
#define | SCB_ABFSR_AXIMTYPE_Pos 8U
#define | SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
#define | SCB_ABFSR_EPPB_Pos 4U
#define | SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
#define | SCB_ABFSR_AXIM_Pos 3U
#define | SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
#define | SCB_ABFSR_AHBP_Pos 2U
#define | SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
#define | SCB_ABFSR_DTCM_Pos 1U
#define | SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
#define | SCB_ABFSR_ITCM_Pos 0U
#define | SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
#define | SCB_CPUID_IMPLEMENTER_Pos 24U
#define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
#define | SCB_CPUID_VARIANT_Pos 20U
#define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
#define | SCB_CPUID_ARCHITECTURE_Pos 16U
#define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
#define | SCB_CPUID_PARTNO_Pos 4U
#define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
#define | SCB_CPUID_REVISION_Pos 0U
#define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
#define | SCB_ICSR_PENDNMISET_Pos 31U
#define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
#define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
#define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
#define | SCB_ICSR_PENDNMICLR_Pos 30U
#define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
#define | SCB_ICSR_PENDSVSET_Pos 28U
#define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
#define | SCB_ICSR_PENDSVCLR_Pos 27U
#define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
#define | SCB_ICSR_PENDSTSET_Pos 26U
#define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
#define | SCB_ICSR_PENDSTCLR_Pos 25U
#define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
#define | SCB_ICSR_STTNS_Pos 24U
#define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
#define | SCB_ICSR_ISRPREEMPT_Pos 23U
#define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
#define | SCB_ICSR_ISRPENDING_Pos 22U
#define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
#define | SCB_ICSR_VECTPENDING_Pos 12U
#define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
#define | SCB_ICSR_RETTOBASE_Pos 11U
#define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
#define | SCB_ICSR_VECTACTIVE_Pos 0U
#define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
#define | SCB_AIRCR_VECTKEY_Pos 16U
#define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
#define | SCB_AIRCR_VECTKEYSTAT_Pos 16U
#define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
#define | SCB_AIRCR_ENDIANESS_Pos 15U
#define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
#define | SCB_AIRCR_PRIS_Pos 14U
#define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
#define | SCB_AIRCR_BFHFNMINS_Pos 13U
#define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
#define | SCB_AIRCR_SYSRESETREQS_Pos 3U
#define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
#define | SCB_AIRCR_SYSRESETREQ_Pos 2U
#define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
#define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U
#define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
#define | SCB_SCR_SEVONPEND_Pos 4U
#define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
#define | SCB_SCR_SLEEPDEEPS_Pos 3U
#define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
#define | SCB_SCR_SLEEPDEEP_Pos 2U
#define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
#define | SCB_SCR_SLEEPONEXIT_Pos 1U
#define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
#define | SCB_CCR_BP_Pos 18U
#define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
#define | SCB_CCR_IC_Pos 17U
#define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
#define | SCB_CCR_DC_Pos 16U
#define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
#define | SCB_CCR_STKOFHFNMIGN_Pos 10U
#define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
#define | SCB_CCR_BFHFNMIGN_Pos 8U
#define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
#define | SCB_CCR_DIV_0_TRP_Pos 4U
#define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
#define | SCB_CCR_UNALIGN_TRP_Pos 3U
#define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
#define | SCB_CCR_USERSETMPEND_Pos 1U
#define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
#define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U
#define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
#define | SCB_SHCSR_SVCALLPENDED_Pos 15U
#define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
#define | SCB_SHCSR_SYSTICKACT_Pos 11U
#define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
#define | SCB_SHCSR_PENDSVACT_Pos 10U
#define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
#define | SCB_SHCSR_SVCALLACT_Pos 7U
#define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
#define | SCB_SHCSR_NMIACT_Pos 5U
#define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
#define | SCB_SHCSR_HARDFAULTACT_Pos 2U
#define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
#define | SCB_CPUID_IMPLEMENTER_Pos 24U
#define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
#define | SCB_CPUID_VARIANT_Pos 20U
#define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
#define | SCB_CPUID_ARCHITECTURE_Pos 16U
#define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
#define | SCB_CPUID_PARTNO_Pos 4U
#define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
#define | SCB_CPUID_REVISION_Pos 0U
#define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
#define | SCB_ICSR_PENDNMISET_Pos 31U
#define | SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
#define | SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
#define | SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
#define | SCB_ICSR_PENDNMICLR_Pos 30U
#define | SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
#define | SCB_ICSR_PENDSVSET_Pos 28U
#define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
#define | SCB_ICSR_PENDSVCLR_Pos 27U
#define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
#define | SCB_ICSR_PENDSTSET_Pos 26U
#define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
#define | SCB_ICSR_PENDSTCLR_Pos 25U
#define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
#define | SCB_ICSR_STTNS_Pos 24U
#define | SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
#define | SCB_ICSR_ISRPREEMPT_Pos 23U
#define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
#define | SCB_ICSR_ISRPENDING_Pos 22U
#define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
#define | SCB_ICSR_VECTPENDING_Pos 12U
#define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
#define | SCB_ICSR_RETTOBASE_Pos 11U
#define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
#define | SCB_ICSR_VECTACTIVE_Pos 0U
#define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
#define | SCB_VTOR_TBLOFF_Pos 7U
#define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
#define | SCB_AIRCR_VECTKEY_Pos 16U
#define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
#define | SCB_AIRCR_VECTKEYSTAT_Pos 16U
#define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
#define | SCB_AIRCR_ENDIANESS_Pos 15U
#define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
#define | SCB_AIRCR_PRIS_Pos 14U
#define | SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
#define | SCB_AIRCR_BFHFNMINS_Pos 13U
#define | SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
#define | SCB_AIRCR_PRIGROUP_Pos 8U
#define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
#define | SCB_AIRCR_SYSRESETREQS_Pos 3U
#define | SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
#define | SCB_AIRCR_SYSRESETREQ_Pos 2U
#define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
#define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U
#define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
#define | SCB_SCR_SEVONPEND_Pos 4U
#define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
#define | SCB_SCR_SLEEPDEEPS_Pos 3U
#define | SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
#define | SCB_SCR_SLEEPDEEP_Pos 2U
#define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
#define | SCB_SCR_SLEEPONEXIT_Pos 1U
#define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
#define | SCB_CCR_BP_Pos 18U
#define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
#define | SCB_CCR_IC_Pos 17U
#define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
#define | SCB_CCR_DC_Pos 16U
#define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
#define | SCB_CCR_STKOFHFNMIGN_Pos 10U
#define | SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
#define | SCB_CCR_BFHFNMIGN_Pos 8U
#define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
#define | SCB_CCR_DIV_0_TRP_Pos 4U
#define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
#define | SCB_CCR_UNALIGN_TRP_Pos 3U
#define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
#define | SCB_CCR_USERSETMPEND_Pos 1U
#define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
#define | SCB_SHCSR_HARDFAULTPENDED_Pos 21U
#define | SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
#define | SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
#define | SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
#define | SCB_SHCSR_SECUREFAULTENA_Pos 19U
#define | SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
#define | SCB_SHCSR_USGFAULTENA_Pos 18U
#define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
#define | SCB_SHCSR_BUSFAULTENA_Pos 17U
#define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
#define | SCB_SHCSR_MEMFAULTENA_Pos 16U
#define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
#define | SCB_SHCSR_SVCALLPENDED_Pos 15U
#define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
#define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U
#define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
#define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U
#define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
#define | SCB_SHCSR_USGFAULTPENDED_Pos 12U
#define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
#define | SCB_SHCSR_SYSTICKACT_Pos 11U
#define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
#define | SCB_SHCSR_PENDSVACT_Pos 10U
#define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
#define | SCB_SHCSR_MONITORACT_Pos 8U
#define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
#define | SCB_SHCSR_SVCALLACT_Pos 7U
#define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
#define | SCB_SHCSR_NMIACT_Pos 5U
#define | SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
#define | SCB_SHCSR_SECUREFAULTACT_Pos 4U
#define | SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
#define | SCB_SHCSR_USGFAULTACT_Pos 3U
#define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
#define | SCB_SHCSR_HARDFAULTACT_Pos 2U
#define | SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
#define | SCB_SHCSR_BUSFAULTACT_Pos 1U
#define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
#define | SCB_SHCSR_MEMFAULTACT_Pos 0U
#define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
#define | SCB_CFSR_USGFAULTSR_Pos 16U
#define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
#define | SCB_CFSR_BUSFAULTSR_Pos 8U
#define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
#define | SCB_CFSR_MEMFAULTSR_Pos 0U
#define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
#define | SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
#define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
#define | SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
#define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
#define | SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
#define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
#define | SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
#define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
#define | SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
#define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
#define | SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
#define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
#define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
#define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
#define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
#define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
#define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
#define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
#define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
#define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
#define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
#define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
#define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
#define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
#define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
#define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
#define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
#define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
#define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
#define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
#define | SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
#define | SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
#define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
#define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
#define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
#define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
#define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
#define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
#define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
#define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
#define | SCB_HFSR_DEBUGEVT_Pos 31U
#define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
#define | SCB_HFSR_FORCED_Pos 30U
#define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
#define | SCB_HFSR_VECTTBL_Pos 1U
#define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
#define | SCB_DFSR_EXTERNAL_Pos 4U
#define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
#define | SCB_DFSR_VCATCH_Pos 3U
#define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
#define | SCB_DFSR_DWTTRAP_Pos 2U
#define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
#define | SCB_DFSR_BKPT_Pos 1U
#define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
#define | SCB_DFSR_HALTED_Pos 0U
#define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
#define | SCB_NSACR_CP11_Pos 11U
#define | SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
#define | SCB_NSACR_CP10_Pos 10U
#define | SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
#define | SCB_NSACR_CPn_Pos 0U
#define | SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
#define | SCB_CLIDR_LOUU_Pos 27U
#define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
#define | SCB_CLIDR_LOC_Pos 24U
#define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
#define | SCB_CTR_FORMAT_Pos 29U
#define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
#define | SCB_CTR_CWG_Pos 24U
#define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
#define | SCB_CTR_ERG_Pos 20U
#define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
#define | SCB_CTR_DMINLINE_Pos 16U
#define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
#define | SCB_CTR_IMINLINE_Pos 0U
#define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
#define | SCB_CCSIDR_WT_Pos 31U
#define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
#define | SCB_CCSIDR_WB_Pos 30U
#define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
#define | SCB_CCSIDR_RA_Pos 29U
#define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
#define | SCB_CCSIDR_WA_Pos 28U
#define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
#define | SCB_CCSIDR_NUMSETS_Pos 13U
#define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
#define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
#define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define | SCB_CCSIDR_LINESIZE_Pos 0U
#define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
#define | SCB_CSSELR_LEVEL_Pos 1U
#define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
#define | SCB_CSSELR_IND_Pos 0U
#define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
#define | SCB_STIR_INTID_Pos 0U
#define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
#define | SCB_DCISW_WAY_Pos 30U
#define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
#define | SCB_DCISW_SET_Pos 5U
#define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
#define | SCB_DCCSW_WAY_Pos 30U
#define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
#define | SCB_DCCSW_SET_Pos 5U
#define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
#define | SCB_DCCISW_WAY_Pos 30U
#define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
#define | SCB_DCCISW_SET_Pos 5U
#define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
#define | SCB_CPUID_IMPLEMENTER_Pos 24U
#define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
#define | SCB_CPUID_VARIANT_Pos 20U
#define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
#define | SCB_CPUID_ARCHITECTURE_Pos 16U
#define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
#define | SCB_CPUID_PARTNO_Pos 4U
#define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
#define | SCB_CPUID_REVISION_Pos 0U
#define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
#define | SCB_ICSR_NMIPENDSET_Pos 31U
#define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
#define | SCB_ICSR_PENDSVSET_Pos 28U
#define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
#define | SCB_ICSR_PENDSVCLR_Pos 27U
#define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
#define | SCB_ICSR_PENDSTSET_Pos 26U
#define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
#define | SCB_ICSR_PENDSTCLR_Pos 25U
#define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
#define | SCB_ICSR_ISRPREEMPT_Pos 23U
#define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
#define | SCB_ICSR_ISRPENDING_Pos 22U
#define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
#define | SCB_ICSR_VECTPENDING_Pos 12U
#define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
#define | SCB_ICSR_RETTOBASE_Pos 11U
#define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
#define | SCB_ICSR_VECTACTIVE_Pos 0U
#define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
#define | SCB_VTOR_TBLOFF_Pos 7U
#define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
#define | SCB_AIRCR_VECTKEY_Pos 16U
#define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
#define | SCB_AIRCR_VECTKEYSTAT_Pos 16U
#define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
#define | SCB_AIRCR_ENDIANESS_Pos 15U
#define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
#define | SCB_AIRCR_PRIGROUP_Pos 8U
#define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
#define | SCB_AIRCR_SYSRESETREQ_Pos 2U
#define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
#define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U
#define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
#define | SCB_AIRCR_VECTRESET_Pos 0U
#define | SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
#define | SCB_SCR_SEVONPEND_Pos 4U
#define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
#define | SCB_SCR_SLEEPDEEP_Pos 2U
#define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
#define | SCB_SCR_SLEEPONEXIT_Pos 1U
#define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
#define | SCB_CCR_BP_Pos 18U
#define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
#define | SCB_CCR_IC_Pos 17U
#define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
#define | SCB_CCR_DC_Pos 16U
#define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
#define | SCB_CCR_STKALIGN_Pos 9U
#define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
#define | SCB_CCR_BFHFNMIGN_Pos 8U
#define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
#define | SCB_CCR_DIV_0_TRP_Pos 4U
#define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
#define | SCB_CCR_UNALIGN_TRP_Pos 3U
#define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
#define | SCB_CCR_USERSETMPEND_Pos 1U
#define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
#define | SCB_CCR_NONBASETHRDENA_Pos 0U
#define | SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
#define | SCB_SHCSR_USGFAULTENA_Pos 18U
#define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
#define | SCB_SHCSR_BUSFAULTENA_Pos 17U
#define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
#define | SCB_SHCSR_MEMFAULTENA_Pos 16U
#define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
#define | SCB_SHCSR_SVCALLPENDED_Pos 15U
#define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
#define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U
#define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
#define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U
#define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
#define | SCB_SHCSR_USGFAULTPENDED_Pos 12U
#define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
#define | SCB_SHCSR_SYSTICKACT_Pos 11U
#define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
#define | SCB_SHCSR_PENDSVACT_Pos 10U
#define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
#define | SCB_SHCSR_MONITORACT_Pos 8U
#define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
#define | SCB_SHCSR_SVCALLACT_Pos 7U
#define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
#define | SCB_SHCSR_USGFAULTACT_Pos 3U
#define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
#define | SCB_SHCSR_BUSFAULTACT_Pos 1U
#define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
#define | SCB_SHCSR_MEMFAULTACT_Pos 0U
#define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
#define | SCB_CFSR_USGFAULTSR_Pos 16U
#define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
#define | SCB_CFSR_BUSFAULTSR_Pos 8U
#define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
#define | SCB_CFSR_MEMFAULTSR_Pos 0U
#define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
#define | SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
#define | SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
#define | SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
#define | SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
#define | SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
#define | SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
#define | SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
#define | SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
#define | SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
#define | SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
#define | SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
#define | SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
#define | SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
#define | SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
#define | SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
#define | SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
#define | SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
#define | SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
#define | SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
#define | SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
#define | SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
#define | SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
#define | SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
#define | SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
#define | SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
#define | SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
#define | SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
#define | SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
#define | SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
#define | SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
#define | SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
#define | SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
#define | SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
#define | SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
#define | SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
#define | SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
#define | SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
#define | SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
#define | SCB_HFSR_DEBUGEVT_Pos 31U
#define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
#define | SCB_HFSR_FORCED_Pos 30U
#define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
#define | SCB_HFSR_VECTTBL_Pos 1U
#define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
#define | SCB_DFSR_EXTERNAL_Pos 4U
#define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
#define | SCB_DFSR_VCATCH_Pos 3U
#define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
#define | SCB_DFSR_DWTTRAP_Pos 2U
#define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
#define | SCB_DFSR_BKPT_Pos 1U
#define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
#define | SCB_DFSR_HALTED_Pos 0U
#define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
#define | SCB_CLIDR_LOUU_Pos 27U
#define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
#define | SCB_CLIDR_LOC_Pos 24U
#define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
#define | SCB_CTR_FORMAT_Pos 29U
#define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
#define | SCB_CTR_CWG_Pos 24U
#define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
#define | SCB_CTR_ERG_Pos 20U
#define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
#define | SCB_CTR_DMINLINE_Pos 16U
#define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
#define | SCB_CTR_IMINLINE_Pos 0U
#define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
#define | SCB_CCSIDR_WT_Pos 31U
#define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
#define | SCB_CCSIDR_WB_Pos 30U
#define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
#define | SCB_CCSIDR_RA_Pos 29U
#define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
#define | SCB_CCSIDR_WA_Pos 28U
#define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
#define | SCB_CCSIDR_NUMSETS_Pos 13U
#define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
#define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
#define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define | SCB_CCSIDR_LINESIZE_Pos 0U
#define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
#define | SCB_CSSELR_LEVEL_Pos 1U
#define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
#define | SCB_CSSELR_IND_Pos 0U
#define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
#define | SCB_STIR_INTID_Pos 0U
#define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
#define | SCB_DCISW_WAY_Pos 30U
#define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
#define | SCB_DCISW_SET_Pos 5U
#define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
#define | SCB_DCCSW_WAY_Pos 30U
#define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
#define | SCB_DCCSW_SET_Pos 5U
#define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
#define | SCB_DCCISW_WAY_Pos 30U
#define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
#define | SCB_DCCISW_SET_Pos 5U
#define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
#define | SCB_ITCMCR_SZ_Pos 3U
#define | SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
#define | SCB_ITCMCR_RETEN_Pos 2U
#define | SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
#define | SCB_ITCMCR_RMW_Pos 1U
#define | SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
#define | SCB_ITCMCR_EN_Pos 0U
#define | SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
#define | SCB_DTCMCR_SZ_Pos 3U
#define | SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
#define | SCB_DTCMCR_RETEN_Pos 2U
#define | SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
#define | SCB_DTCMCR_RMW_Pos 1U
#define | SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
#define | SCB_DTCMCR_EN_Pos 0U
#define | SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
#define | SCB_AHBPCR_SZ_Pos 1U
#define | SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
#define | SCB_AHBPCR_EN_Pos 0U
#define | SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
#define | SCB_CACR_FORCEWT_Pos 2U
#define | SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
#define | SCB_CACR_ECCEN_Pos 1U
#define | SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
#define | SCB_CACR_SIWT_Pos 0U
#define | SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
#define | SCB_AHBSCR_INITCOUNT_Pos 11U
#define | SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
#define | SCB_AHBSCR_TPRI_Pos 2U
#define | SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
#define | SCB_AHBSCR_CTL_Pos 0U
#define | SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
#define | SCB_ABFSR_AXIMTYPE_Pos 8U
#define | SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
#define | SCB_ABFSR_EPPB_Pos 4U
#define | SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
#define | SCB_ABFSR_AXIM_Pos 3U
#define | SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
#define | SCB_ABFSR_AHBP_Pos 2U
#define | SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
#define | SCB_ABFSR_DTCM_Pos 1U
#define | SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
#define | SCB_ABFSR_ITCM_Pos 0U
#define | SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

## Detailed Description

Type definitions for the System Control Block Registers.

## Macro Definition Documentation

## ◆ SCB_ABFSR_AHBP_Msk [1/2]

#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 898 of file core_cm7.h.

## ◆ SCB_ABFSR_AHBP_Msk [2/2]

#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 988 of file core_armv81mml.h.

## ◆ SCB_ABFSR_AHBP_Pos [1/2]

#define SCB_ABFSR_AHBP_Pos 2U

SCB ABFSR: AHBP Position

Definition at line 897 of file core_cm7.h.

## ◆ SCB_ABFSR_AHBP_Pos [2/2]

#define SCB_ABFSR_AHBP_Pos 2U

SCB ABFSR: AHBP Position

Definition at line 987 of file core_armv81mml.h.

## ◆ SCB_ABFSR_AXIM_Msk [1/2]

#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 895 of file core_cm7.h.

## ◆ SCB_ABFSR_AXIM_Msk [2/2]

#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 985 of file core_armv81mml.h.

## ◆ SCB_ABFSR_AXIM_Pos [1/2]

#define SCB_ABFSR_AXIM_Pos 3U

SCB ABFSR: AXIM Position

Definition at line 894 of file core_cm7.h.

## ◆ SCB_ABFSR_AXIM_Pos [2/2]

#define SCB_ABFSR_AXIM_Pos 3U

SCB ABFSR: AXIM Position

Definition at line 984 of file core_armv81mml.h.

## ◆ SCB_ABFSR_AXIMTYPE_Msk [1/2]

#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 889 of file core_cm7.h.

## ◆ SCB_ABFSR_AXIMTYPE_Msk [2/2]

#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 979 of file core_armv81mml.h.

## ◆ SCB_ABFSR_AXIMTYPE_Pos [1/2]

#define SCB_ABFSR_AXIMTYPE_Pos 8U

SCB ABFSR: AXIMTYPE Position

Definition at line 888 of file core_cm7.h.

## ◆ SCB_ABFSR_AXIMTYPE_Pos [2/2]

#define SCB_ABFSR_AXIMTYPE_Pos 8U

SCB ABFSR: AXIMTYPE Position

Definition at line 978 of file core_armv81mml.h.

## ◆ SCB_ABFSR_DTCM_Msk [1/2]

#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 901 of file core_cm7.h.

## ◆ SCB_ABFSR_DTCM_Msk [2/2]

#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 991 of file core_armv81mml.h.

## ◆ SCB_ABFSR_DTCM_Pos [1/2]

#define SCB_ABFSR_DTCM_Pos 1U

SCB ABFSR: DTCM Position

Definition at line 900 of file core_cm7.h.

## ◆ SCB_ABFSR_DTCM_Pos [2/2]

#define SCB_ABFSR_DTCM_Pos 1U

SCB ABFSR: DTCM Position

Definition at line 990 of file core_armv81mml.h.

## ◆ SCB_ABFSR_EPPB_Msk [1/2]

#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 892 of file core_cm7.h.

## ◆ SCB_ABFSR_EPPB_Msk [2/2]

#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 982 of file core_armv81mml.h.

## ◆ SCB_ABFSR_EPPB_Pos [1/2]

#define SCB_ABFSR_EPPB_Pos 4U

SCB ABFSR: EPPB Position

Definition at line 891 of file core_cm7.h.

## ◆ SCB_ABFSR_EPPB_Pos [2/2]

#define SCB_ABFSR_EPPB_Pos 4U

SCB ABFSR: EPPB Position

Definition at line 981 of file core_armv81mml.h.

## ◆ SCB_ABFSR_ITCM_Msk [1/2]

#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 904 of file core_cm7.h.

## ◆ SCB_ABFSR_ITCM_Msk [2/2]

#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 994 of file core_armv81mml.h.

## ◆ SCB_ABFSR_ITCM_Pos [1/2]

#define SCB_ABFSR_ITCM_Pos 0U

SCB ABFSR: ITCM Position

Definition at line 903 of file core_cm7.h.

## ◆ SCB_ABFSR_ITCM_Pos [2/2]

#define SCB_ABFSR_ITCM_Pos 0U

SCB ABFSR: ITCM Position

Definition at line 993 of file core_armv81mml.h.

## ◆ SCB_AHBPCR_EN_Msk [1/2]

#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 865 of file core_cm7.h.

## ◆ SCB_AHBPCR_EN_Msk [2/2]

#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 955 of file core_armv81mml.h.

## ◆ SCB_AHBPCR_EN_Pos [1/2]

#define SCB_AHBPCR_EN_Pos 0U

SCB AHBPCR: EN Position

Definition at line 864 of file core_cm7.h.

## ◆ SCB_AHBPCR_EN_Pos [2/2]

#define SCB_AHBPCR_EN_Pos 0U

SCB AHBPCR: EN Position

Definition at line 954 of file core_armv81mml.h.

## ◆ SCB_AHBPCR_SZ_Msk [1/2]

#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 862 of file core_cm7.h.

## ◆ SCB_AHBPCR_SZ_Msk [2/2]

#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 952 of file core_armv81mml.h.

## ◆ SCB_AHBPCR_SZ_Pos [1/2]

#define SCB_AHBPCR_SZ_Pos 1U

SCB AHBPCR: SZ Position

Definition at line 861 of file core_cm7.h.

## ◆ SCB_AHBPCR_SZ_Pos [2/2]

#define SCB_AHBPCR_SZ_Pos 1U

SCB AHBPCR: SZ Position

Definition at line 951 of file core_armv81mml.h.

## ◆ SCB_AHBSCR_CTL_Msk [1/2]

#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 885 of file core_cm7.h.

## ◆ SCB_AHBSCR_CTL_Msk [2/2]

#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 975 of file core_armv81mml.h.

## ◆ SCB_AHBSCR_CTL_Pos [1/2]

#define SCB_AHBSCR_CTL_Pos 0U

SCB AHBSCR: CTL Position

Definition at line 884 of file core_cm7.h.

## ◆ SCB_AHBSCR_CTL_Pos [2/2]

#define SCB_AHBSCR_CTL_Pos 0U

SCB AHBSCR: CTL Position

Definition at line 974 of file core_armv81mml.h.

## ◆ SCB_AHBSCR_INITCOUNT_Msk [1/2]

#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 879 of file core_cm7.h.

## ◆ SCB_AHBSCR_INITCOUNT_Msk [2/2]

#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 969 of file core_armv81mml.h.

## ◆ SCB_AHBSCR_INITCOUNT_Pos [1/2]

#define SCB_AHBSCR_INITCOUNT_Pos 11U

SCB AHBSCR: INITCOUNT Position

Definition at line 878 of file core_cm7.h.

## ◆ SCB_AHBSCR_INITCOUNT_Pos [2/2]

#define SCB_AHBSCR_INITCOUNT_Pos 11U

SCB AHBSCR: INITCOUNT Position

Definition at line 968 of file core_armv81mml.h.

## ◆ SCB_AHBSCR_TPRI_Msk [1/2]

#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 882 of file core_cm7.h.

## ◆ SCB_AHBSCR_TPRI_Msk [2/2]

#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 972 of file core_armv81mml.h.

## ◆ SCB_AHBSCR_TPRI_Pos [1/2]

#define SCB_AHBSCR_TPRI_Pos 2U

SCB AHBSCR: TPRI Position

Definition at line 881 of file core_cm7.h.

## ◆ SCB_AHBSCR_TPRI_Pos [2/2]

#define SCB_AHBSCR_TPRI_Pos 2U

SCB AHBSCR: TPRI Position

Definition at line 971 of file core_armv81mml.h.

## ◆ SCB_AIRCR_BFHFNMINS_Msk [1/3]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 472 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_BFHFNMINS_Msk [2/3]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 615 of file core_armv8mml.h.

## ◆ SCB_AIRCR_BFHFNMINS_Msk [3/3]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 625 of file core_armv81mml.h.

## ◆ SCB_AIRCR_BFHFNMINS_Pos [1/3]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 471 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_BFHFNMINS_Pos [2/3]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 614 of file core_armv8mml.h.

## ◆ SCB_AIRCR_BFHFNMINS_Pos [3/3]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 624 of file core_armv81mml.h.

## ◆ SCB_AIRCR_ENDIANESS_Msk [1/4]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 466 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_ENDIANESS_Msk [2/4]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 566 of file core_cm7.h.

## ◆ SCB_AIRCR_ENDIANESS_Msk [3/4]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 609 of file core_armv8mml.h.

## ◆ SCB_AIRCR_ENDIANESS_Msk [4/4]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 619 of file core_armv81mml.h.

## ◆ SCB_AIRCR_ENDIANESS_Pos [1/4]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 465 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_ENDIANESS_Pos [2/4]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 565 of file core_cm7.h.

## ◆ SCB_AIRCR_ENDIANESS_Pos [3/4]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 608 of file core_armv8mml.h.

## ◆ SCB_AIRCR_ENDIANESS_Pos [4/4]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 618 of file core_armv81mml.h.

## ◆ SCB_AIRCR_PRIGROUP_Msk [1/3]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 569 of file core_cm7.h.

## ◆ SCB_AIRCR_PRIGROUP_Msk [2/3]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 618 of file core_armv8mml.h.

## ◆ SCB_AIRCR_PRIGROUP_Msk [3/3]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 628 of file core_armv81mml.h.

## ◆ SCB_AIRCR_PRIGROUP_Pos [1/3]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 568 of file core_cm7.h.

## ◆ SCB_AIRCR_PRIGROUP_Pos [2/3]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 617 of file core_armv8mml.h.

## ◆ SCB_AIRCR_PRIGROUP_Pos [3/3]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 627 of file core_armv81mml.h.

## ◆ SCB_AIRCR_PRIS_Msk [1/3]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 469 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_PRIS_Msk [2/3]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 612 of file core_armv8mml.h.

## ◆ SCB_AIRCR_PRIS_Msk [3/3]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 622 of file core_armv81mml.h.

## ◆ SCB_AIRCR_PRIS_Pos [1/3]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 468 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_PRIS_Pos [2/3]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 611 of file core_armv8mml.h.

## ◆ SCB_AIRCR_PRIS_Pos [3/3]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 621 of file core_armv81mml.h.

## ◆ SCB_AIRCR_SYSRESETREQ_Msk [1/4]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 478 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_SYSRESETREQ_Msk [2/4]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 572 of file core_cm7.h.

## ◆ SCB_AIRCR_SYSRESETREQ_Msk [3/4]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 624 of file core_armv8mml.h.

## ◆ SCB_AIRCR_SYSRESETREQ_Msk [4/4]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 634 of file core_armv81mml.h.

## ◆ SCB_AIRCR_SYSRESETREQ_Pos [1/4]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 477 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_SYSRESETREQ_Pos [2/4]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 571 of file core_cm7.h.

## ◆ SCB_AIRCR_SYSRESETREQ_Pos [3/4]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 623 of file core_armv8mml.h.

## ◆ SCB_AIRCR_SYSRESETREQ_Pos [4/4]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 633 of file core_armv81mml.h.

## ◆ SCB_AIRCR_SYSRESETREQS_Msk [1/3]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 475 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_SYSRESETREQS_Msk [2/3]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 621 of file core_armv8mml.h.

## ◆ SCB_AIRCR_SYSRESETREQS_Msk [3/3]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 631 of file core_armv81mml.h.

## ◆ SCB_AIRCR_SYSRESETREQS_Pos [1/3]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 474 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_SYSRESETREQS_Pos [2/3]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 620 of file core_armv8mml.h.

## ◆ SCB_AIRCR_SYSRESETREQS_Pos [3/3]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 630 of file core_armv81mml.h.

## ◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/4]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 481 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/4]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 575 of file core_cm7.h.

## ◆ SCB_AIRCR_VECTCLRACTIVE_Msk [3/4]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 627 of file core_armv8mml.h.

## ◆ SCB_AIRCR_VECTCLRACTIVE_Msk [4/4]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 637 of file core_armv81mml.h.

## ◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/4]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 480 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/4]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 574 of file core_cm7.h.

## ◆ SCB_AIRCR_VECTCLRACTIVE_Pos [3/4]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 626 of file core_armv8mml.h.

## ◆ SCB_AIRCR_VECTCLRACTIVE_Pos [4/4]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 636 of file core_armv81mml.h.

## ◆ SCB_AIRCR_VECTKEY_Msk [1/4]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 460 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_VECTKEY_Msk [2/4]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 560 of file core_cm7.h.

## ◆ SCB_AIRCR_VECTKEY_Msk [3/4]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 603 of file core_armv8mml.h.

## ◆ SCB_AIRCR_VECTKEY_Msk [4/4]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 613 of file core_armv81mml.h.

## ◆ SCB_AIRCR_VECTKEY_Pos [1/4]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 459 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_VECTKEY_Pos [2/4]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 559 of file core_cm7.h.

## ◆ SCB_AIRCR_VECTKEY_Pos [3/4]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 602 of file core_armv8mml.h.

## ◆ SCB_AIRCR_VECTKEY_Pos [4/4]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 612 of file core_armv81mml.h.

## ◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/4]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 463 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/4]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 563 of file core_cm7.h.

## ◆ SCB_AIRCR_VECTKEYSTAT_Msk [3/4]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 606 of file core_armv8mml.h.

## ◆ SCB_AIRCR_VECTKEYSTAT_Msk [4/4]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 616 of file core_armv81mml.h.

## ◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/4]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 462 of file core_armv8mbl.h.

## ◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/4]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 562 of file core_cm7.h.

## ◆ SCB_AIRCR_VECTKEYSTAT_Pos [3/4]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 605 of file core_armv8mml.h.

## ◆ SCB_AIRCR_VECTKEYSTAT_Pos [4/4]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 615 of file core_armv81mml.h.

## ◆ SCB_AIRCR_VECTRESET_Msk

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 578 of file core_cm7.h.

## ◆ SCB_AIRCR_VECTRESET_Pos

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 577 of file core_cm7.h.

## ◆ SCB_CACR_ECCEN_Msk [1/2]

#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 872 of file core_cm7.h.

## ◆ SCB_CACR_ECCEN_Msk [2/2]

#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 962 of file core_armv81mml.h.

## ◆ SCB_CACR_ECCEN_Pos [1/2]

#define SCB_CACR_ECCEN_Pos 1U

SCB CACR: ECCEN Position

Definition at line 871 of file core_cm7.h.

## ◆ SCB_CACR_ECCEN_Pos [2/2]

#define SCB_CACR_ECCEN_Pos 1U

SCB CACR: ECCEN Position

Definition at line 961 of file core_armv81mml.h.

## ◆ SCB_CACR_FORCEWT_Msk [1/2]

#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 869 of file core_cm7.h.

## ◆ SCB_CACR_FORCEWT_Msk [2/2]

#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 959 of file core_armv81mml.h.

## ◆ SCB_CACR_FORCEWT_Pos [1/2]

#define SCB_CACR_FORCEWT_Pos 2U

SCB CACR: FORCEWT Position

Definition at line 868 of file core_cm7.h.

## ◆ SCB_CACR_FORCEWT_Pos [2/2]

#define SCB_CACR_FORCEWT_Pos 2U

SCB CACR: FORCEWT Position

Definition at line 958 of file core_armv81mml.h.

## ◆ SCB_CACR_SIWT_Msk [1/2]

#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 875 of file core_cm7.h.

## ◆ SCB_CACR_SIWT_Msk [2/2]

#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 965 of file core_armv81mml.h.

## ◆ SCB_CACR_SIWT_Pos [1/2]

#define SCB_CACR_SIWT_Pos 0U

SCB CACR: SIWT Position

Definition at line 874 of file core_cm7.h.

## ◆ SCB_CACR_SIWT_Pos [2/2]

#define SCB_CACR_SIWT_Pos 0U

SCB CACR: SIWT Position

Definition at line 964 of file core_armv81mml.h.

## ◆ SCB_CCR_BFHFNMIGN_Msk [1/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 510 of file core_armv8mbl.h.

## ◆ SCB_CCR_BFHFNMIGN_Msk [2/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 604 of file core_cm7.h.

## ◆ SCB_CCR_BFHFNMIGN_Msk [3/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 656 of file core_armv8mml.h.

## ◆ SCB_CCR_BFHFNMIGN_Msk [4/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 666 of file core_armv81mml.h.

## ◆ SCB_CCR_BFHFNMIGN_Pos [1/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 509 of file core_armv8mbl.h.

## ◆ SCB_CCR_BFHFNMIGN_Pos [2/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 603 of file core_cm7.h.

## ◆ SCB_CCR_BFHFNMIGN_Pos [3/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 655 of file core_armv8mml.h.

## ◆ SCB_CCR_BFHFNMIGN_Pos [4/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 665 of file core_armv81mml.h.

## ◆ SCB_CCR_BP_Msk [1/4]

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 498 of file core_armv8mbl.h.

## ◆ SCB_CCR_BP_Msk [2/4]

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 592 of file core_cm7.h.

## ◆ SCB_CCR_BP_Msk [3/4]

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 644 of file core_armv8mml.h.

## ◆ SCB_CCR_BP_Msk [4/4]

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 654 of file core_armv81mml.h.

## ◆ SCB_CCR_BP_Pos [1/4]

#define SCB_CCR_BP_Pos 18U

SCB CCR: BP Position

Definition at line 497 of file core_armv8mbl.h.

## ◆ SCB_CCR_BP_Pos [2/4]

#define SCB_CCR_BP_Pos 18U

SCB CCR: Branch prediction enable bit Position

Definition at line 591 of file core_cm7.h.

## ◆ SCB_CCR_BP_Pos [3/4]

#define SCB_CCR_BP_Pos 18U

SCB CCR: BP Position

Definition at line 643 of file core_armv8mml.h.

## ◆ SCB_CCR_BP_Pos [4/4]

#define SCB_CCR_BP_Pos 18U

SCB CCR: BP Position

Definition at line 653 of file core_armv81mml.h.

## ◆ SCB_CCR_DC_Msk [1/4]

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 504 of file core_armv8mbl.h.

## ◆ SCB_CCR_DC_Msk [2/4]

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 598 of file core_cm7.h.

## ◆ SCB_CCR_DC_Msk [3/4]

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 650 of file core_armv8mml.h.

## ◆ SCB_CCR_DC_Msk [4/4]

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 660 of file core_armv81mml.h.

## ◆ SCB_CCR_DC_Pos [1/4]

#define SCB_CCR_DC_Pos 16U

SCB CCR: DC Position

Definition at line 503 of file core_armv8mbl.h.

## ◆ SCB_CCR_DC_Pos [2/4]

#define SCB_CCR_DC_Pos 16U

SCB CCR: Cache enable bit Position

Definition at line 597 of file core_cm7.h.

## ◆ SCB_CCR_DC_Pos [3/4]

#define SCB_CCR_DC_Pos 16U

SCB CCR: DC Position

Definition at line 649 of file core_armv8mml.h.

## ◆ SCB_CCR_DC_Pos [4/4]

#define SCB_CCR_DC_Pos 16U

SCB CCR: DC Position

Definition at line 659 of file core_armv81mml.h.

## ◆ SCB_CCR_DIV_0_TRP_Msk [1/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 513 of file core_armv8mbl.h.

## ◆ SCB_CCR_DIV_0_TRP_Msk [2/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 607 of file core_cm7.h.

## ◆ SCB_CCR_DIV_0_TRP_Msk [3/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 659 of file core_armv8mml.h.

## ◆ SCB_CCR_DIV_0_TRP_Msk [4/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 669 of file core_armv81mml.h.

## ◆ SCB_CCR_DIV_0_TRP_Pos [1/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

Definition at line 512 of file core_armv8mbl.h.

## ◆ SCB_CCR_DIV_0_TRP_Pos [2/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

Definition at line 606 of file core_cm7.h.

## ◆ SCB_CCR_DIV_0_TRP_Pos [3/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

Definition at line 658 of file core_armv8mml.h.

## ◆ SCB_CCR_DIV_0_TRP_Pos [4/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

Definition at line 668 of file core_armv81mml.h.

## ◆ SCB_CCR_IC_Msk [1/4]

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 501 of file core_armv8mbl.h.

## ◆ SCB_CCR_IC_Msk [2/4]

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 595 of file core_cm7.h.

## ◆ SCB_CCR_IC_Msk [3/4]

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 647 of file core_armv8mml.h.

## ◆ SCB_CCR_IC_Msk [4/4]

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 657 of file core_armv81mml.h.

## ◆ SCB_CCR_IC_Pos [1/4]

#define SCB_CCR_IC_Pos 17U

SCB CCR: IC Position

Definition at line 500 of file core_armv8mbl.h.

## ◆ SCB_CCR_IC_Pos [2/4]

#define SCB_CCR_IC_Pos 17U

SCB CCR: Instruction cache enable bit Position

Definition at line 594 of file core_cm7.h.

## ◆ SCB_CCR_IC_Pos [3/4]

#define SCB_CCR_IC_Pos 17U

SCB CCR: IC Position

Definition at line 646 of file core_armv8mml.h.

## ◆ SCB_CCR_IC_Pos [4/4]

#define SCB_CCR_IC_Pos 17U

SCB CCR: IC Position

Definition at line 656 of file core_armv81mml.h.

## ◆ SCB_CCR_NONBASETHRDENA_Msk

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 616 of file core_cm7.h.

## ◆ SCB_CCR_NONBASETHRDENA_Pos

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 615 of file core_cm7.h.

## ◆ SCB_CCR_STKALIGN_Msk

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 601 of file core_cm7.h.

## ◆ SCB_CCR_STKALIGN_Pos

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 600 of file core_cm7.h.

## ◆ SCB_CCR_STKOFHFNMIGN_Msk [1/3]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 507 of file core_armv8mbl.h.

## ◆ SCB_CCR_STKOFHFNMIGN_Msk [2/3]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 653 of file core_armv8mml.h.

## ◆ SCB_CCR_STKOFHFNMIGN_Msk [3/3]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 663 of file core_armv81mml.h.

## ◆ SCB_CCR_STKOFHFNMIGN_Pos [1/3]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 506 of file core_armv8mbl.h.

## ◆ SCB_CCR_STKOFHFNMIGN_Pos [2/3]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 652 of file core_armv8mml.h.

## ◆ SCB_CCR_STKOFHFNMIGN_Pos [3/3]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 662 of file core_armv81mml.h.

## ◆ SCB_CCR_UNALIGN_TRP_Msk [1/4]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 516 of file core_armv8mbl.h.

## ◆ SCB_CCR_UNALIGN_TRP_Msk [2/4]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 610 of file core_cm7.h.

## ◆ SCB_CCR_UNALIGN_TRP_Msk [3/4]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 662 of file core_armv8mml.h.

## ◆ SCB_CCR_UNALIGN_TRP_Msk [4/4]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 672 of file core_armv81mml.h.

## ◆ SCB_CCR_UNALIGN_TRP_Pos [1/4]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 515 of file core_armv8mbl.h.

## ◆ SCB_CCR_UNALIGN_TRP_Pos [2/4]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 609 of file core_cm7.h.

## ◆ SCB_CCR_UNALIGN_TRP_Pos [3/4]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 661 of file core_armv8mml.h.

## ◆ SCB_CCR_UNALIGN_TRP_Pos [4/4]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 671 of file core_armv81mml.h.

## ◆ SCB_CCR_USERSETMPEND_Msk [1/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 519 of file core_armv8mbl.h.

## ◆ SCB_CCR_USERSETMPEND_Msk [2/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 613 of file core_cm7.h.

## ◆ SCB_CCR_USERSETMPEND_Msk [3/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 665 of file core_armv8mml.h.

## ◆ SCB_CCR_USERSETMPEND_Msk [4/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 675 of file core_armv81mml.h.

## ◆ SCB_CCR_USERSETMPEND_Pos [1/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 518 of file core_armv8mbl.h.

## ◆ SCB_CCR_USERSETMPEND_Pos [2/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 612 of file core_cm7.h.

## ◆ SCB_CCR_USERSETMPEND_Pos [3/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 664 of file core_armv8mml.h.

## ◆ SCB_CCR_USERSETMPEND_Pos [4/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 674 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [1/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 797 of file core_cm7.h.

## ◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [2/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 877 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [3/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 887 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [1/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 796 of file core_cm7.h.

## ◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [2/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 876 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [3/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 886 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_LINESIZE_Msk [1/3]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 800 of file core_cm7.h.

## ◆ SCB_CCSIDR_LINESIZE_Msk [2/3]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 880 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_LINESIZE_Msk [3/3]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 890 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_LINESIZE_Pos [1/3]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 799 of file core_cm7.h.

## ◆ SCB_CCSIDR_LINESIZE_Pos [2/3]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 879 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_LINESIZE_Pos [3/3]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 889 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_NUMSETS_Msk [1/3]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 794 of file core_cm7.h.

## ◆ SCB_CCSIDR_NUMSETS_Msk [2/3]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 874 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_NUMSETS_Msk [3/3]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 884 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_NUMSETS_Pos [1/3]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 793 of file core_cm7.h.

## ◆ SCB_CCSIDR_NUMSETS_Pos [2/3]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 873 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_NUMSETS_Pos [3/3]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 883 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_RA_Msk [1/3]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 788 of file core_cm7.h.

## ◆ SCB_CCSIDR_RA_Msk [2/3]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 868 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_RA_Msk [3/3]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 878 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_RA_Pos [1/3]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 787 of file core_cm7.h.

## ◆ SCB_CCSIDR_RA_Pos [2/3]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 867 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_RA_Pos [3/3]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 877 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_WA_Msk [1/3]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 791 of file core_cm7.h.

## ◆ SCB_CCSIDR_WA_Msk [2/3]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 871 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_WA_Msk [3/3]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 881 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_WA_Pos [1/3]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 790 of file core_cm7.h.

## ◆ SCB_CCSIDR_WA_Pos [2/3]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 870 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_WA_Pos [3/3]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 880 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_WB_Msk [1/3]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 785 of file core_cm7.h.

## ◆ SCB_CCSIDR_WB_Msk [2/3]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 865 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_WB_Msk [3/3]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 875 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_WB_Pos [1/3]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 784 of file core_cm7.h.

## ◆ SCB_CCSIDR_WB_Pos [2/3]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 864 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_WB_Pos [3/3]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 874 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_WT_Msk [1/3]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 782 of file core_cm7.h.

## ◆ SCB_CCSIDR_WT_Msk [2/3]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 862 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_WT_Msk [3/3]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 872 of file core_armv81mml.h.

## ◆ SCB_CCSIDR_WT_Pos [1/3]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 781 of file core_cm7.h.

## ◆ SCB_CCSIDR_WT_Pos [2/3]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 861 of file core_armv8mml.h.

## ◆ SCB_CCSIDR_WT_Pos [3/3]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 871 of file core_armv81mml.h.

## ◆ SCB_CFSR_BFARVALID_Msk [1/3]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 692 of file core_cm7.h.

## ◆ SCB_CFSR_BFARVALID_Msk [2/3]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 759 of file core_armv8mml.h.

## ◆ SCB_CFSR_BFARVALID_Msk [3/3]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 769 of file core_armv81mml.h.

## ◆ SCB_CFSR_BFARVALID_Pos [1/3]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 691 of file core_cm7.h.

## ◆ SCB_CFSR_BFARVALID_Pos [2/3]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 758 of file core_armv8mml.h.

## ◆ SCB_CFSR_BFARVALID_Pos [3/3]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 768 of file core_armv81mml.h.

## ◆ SCB_CFSR_BUSFAULTSR_Msk [1/3]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 666 of file core_cm7.h.

## ◆ SCB_CFSR_BUSFAULTSR_Msk [2/3]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 733 of file core_armv8mml.h.

## ◆ SCB_CFSR_BUSFAULTSR_Msk [3/3]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 743 of file core_armv81mml.h.

## ◆ SCB_CFSR_BUSFAULTSR_Pos [1/3]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 665 of file core_cm7.h.

## ◆ SCB_CFSR_BUSFAULTSR_Pos [2/3]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 732 of file core_armv8mml.h.

## ◆ SCB_CFSR_BUSFAULTSR_Pos [3/3]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 742 of file core_armv81mml.h.

## ◆ SCB_CFSR_DACCVIOL_Msk [1/3]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 685 of file core_cm7.h.

## ◆ SCB_CFSR_DACCVIOL_Msk [2/3]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 752 of file core_armv8mml.h.

## ◆ SCB_CFSR_DACCVIOL_Msk [3/3]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 762 of file core_armv81mml.h.

## ◆ SCB_CFSR_DACCVIOL_Pos [1/3]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 684 of file core_cm7.h.

## ◆ SCB_CFSR_DACCVIOL_Pos [2/3]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 751 of file core_armv8mml.h.

## ◆ SCB_CFSR_DACCVIOL_Pos [3/3]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 761 of file core_armv81mml.h.

## ◆ SCB_CFSR_DIVBYZERO_Msk [1/3]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 714 of file core_cm7.h.

## ◆ SCB_CFSR_DIVBYZERO_Msk [2/3]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 781 of file core_armv8mml.h.

## ◆ SCB_CFSR_DIVBYZERO_Msk [3/3]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 791 of file core_armv81mml.h.

## ◆ SCB_CFSR_DIVBYZERO_Pos [1/3]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 713 of file core_cm7.h.

## ◆ SCB_CFSR_DIVBYZERO_Pos [2/3]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 780 of file core_armv8mml.h.

## ◆ SCB_CFSR_DIVBYZERO_Pos [3/3]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 790 of file core_armv81mml.h.

## ◆ SCB_CFSR_IACCVIOL_Msk [1/3]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 688 of file core_cm7.h.

## ◆ SCB_CFSR_IACCVIOL_Msk [2/3]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 755 of file core_armv8mml.h.

## ◆ SCB_CFSR_IACCVIOL_Msk [3/3]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 765 of file core_armv81mml.h.

## ◆ SCB_CFSR_IACCVIOL_Pos [1/3]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 687 of file core_cm7.h.

## ◆ SCB_CFSR_IACCVIOL_Pos [2/3]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 754 of file core_armv8mml.h.

## ◆ SCB_CFSR_IACCVIOL_Pos [3/3]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 764 of file core_armv81mml.h.

## ◆ SCB_CFSR_IBUSERR_Msk [1/3]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 710 of file core_cm7.h.

## ◆ SCB_CFSR_IBUSERR_Msk [2/3]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 777 of file core_armv8mml.h.

## ◆ SCB_CFSR_IBUSERR_Msk [3/3]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 787 of file core_armv81mml.h.

## ◆ SCB_CFSR_IBUSERR_Pos [1/3]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 709 of file core_cm7.h.

## ◆ SCB_CFSR_IBUSERR_Pos [2/3]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 776 of file core_armv8mml.h.

## ◆ SCB_CFSR_IBUSERR_Pos [3/3]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 786 of file core_armv81mml.h.

## ◆ SCB_CFSR_IMPRECISERR_Msk [1/3]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 704 of file core_cm7.h.

## ◆ SCB_CFSR_IMPRECISERR_Msk [2/3]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 771 of file core_armv8mml.h.

## ◆ SCB_CFSR_IMPRECISERR_Msk [3/3]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 781 of file core_armv81mml.h.

## ◆ SCB_CFSR_IMPRECISERR_Pos [1/3]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 703 of file core_cm7.h.

## ◆ SCB_CFSR_IMPRECISERR_Pos [2/3]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 770 of file core_armv8mml.h.

## ◆ SCB_CFSR_IMPRECISERR_Pos [3/3]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 780 of file core_armv81mml.h.

## ◆ SCB_CFSR_INVPC_Msk [1/3]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 723 of file core_cm7.h.

## ◆ SCB_CFSR_INVPC_Msk [2/3]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 793 of file core_armv8mml.h.

## ◆ SCB_CFSR_INVPC_Msk [3/3]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 803 of file core_armv81mml.h.

## ◆ SCB_CFSR_INVPC_Pos [1/3]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 722 of file core_cm7.h.

## ◆ SCB_CFSR_INVPC_Pos [2/3]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 792 of file core_armv8mml.h.

## ◆ SCB_CFSR_INVPC_Pos [3/3]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 802 of file core_armv81mml.h.

## ◆ SCB_CFSR_INVSTATE_Msk [1/3]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 726 of file core_cm7.h.

## ◆ SCB_CFSR_INVSTATE_Msk [2/3]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 796 of file core_armv8mml.h.

## ◆ SCB_CFSR_INVSTATE_Msk [3/3]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 806 of file core_armv81mml.h.

## ◆ SCB_CFSR_INVSTATE_Pos [1/3]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 725 of file core_cm7.h.

## ◆ SCB_CFSR_INVSTATE_Pos [2/3]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 795 of file core_armv8mml.h.

## ◆ SCB_CFSR_INVSTATE_Pos [3/3]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 805 of file core_armv81mml.h.

## ◆ SCB_CFSR_LSPERR_Msk [1/3]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 695 of file core_cm7.h.

## ◆ SCB_CFSR_LSPERR_Msk [2/3]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 762 of file core_armv8mml.h.

## ◆ SCB_CFSR_LSPERR_Msk [3/3]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 772 of file core_armv81mml.h.

## ◆ SCB_CFSR_LSPERR_Pos [1/3]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 694 of file core_cm7.h.

## ◆ SCB_CFSR_LSPERR_Pos [2/3]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 761 of file core_armv8mml.h.

## ◆ SCB_CFSR_LSPERR_Pos [3/3]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 771 of file core_armv81mml.h.

## ◆ SCB_CFSR_MEMFAULTSR_Msk [1/3]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 669 of file core_cm7.h.

## ◆ SCB_CFSR_MEMFAULTSR_Msk [2/3]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 736 of file core_armv8mml.h.

## ◆ SCB_CFSR_MEMFAULTSR_Msk [3/3]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 746 of file core_armv81mml.h.

## ◆ SCB_CFSR_MEMFAULTSR_Pos [1/3]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 668 of file core_cm7.h.

## ◆ SCB_CFSR_MEMFAULTSR_Pos [2/3]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 735 of file core_armv8mml.h.

## ◆ SCB_CFSR_MEMFAULTSR_Pos [3/3]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 745 of file core_armv81mml.h.

## ◆ SCB_CFSR_MLSPERR_Msk [1/3]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 676 of file core_cm7.h.

## ◆ SCB_CFSR_MLSPERR_Msk [2/3]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 743 of file core_armv8mml.h.

## ◆ SCB_CFSR_MLSPERR_Msk [3/3]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 753 of file core_armv81mml.h.

## ◆ SCB_CFSR_MLSPERR_Pos [1/3]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 675 of file core_cm7.h.

## ◆ SCB_CFSR_MLSPERR_Pos [2/3]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 742 of file core_armv8mml.h.

## ◆ SCB_CFSR_MLSPERR_Pos [3/3]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 752 of file core_armv81mml.h.

## ◆ SCB_CFSR_MMARVALID_Msk [1/3]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 673 of file core_cm7.h.

## ◆ SCB_CFSR_MMARVALID_Msk [2/3]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 740 of file core_armv8mml.h.

## ◆ SCB_CFSR_MMARVALID_Msk [3/3]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 750 of file core_armv81mml.h.

## ◆ SCB_CFSR_MMARVALID_Pos [1/3]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 672 of file core_cm7.h.

## ◆ SCB_CFSR_MMARVALID_Pos [2/3]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 739 of file core_armv8mml.h.

## ◆ SCB_CFSR_MMARVALID_Pos [3/3]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 749 of file core_armv81mml.h.

## ◆ SCB_CFSR_MSTKERR_Msk [1/3]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 679 of file core_cm7.h.

## ◆ SCB_CFSR_MSTKERR_Msk [2/3]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 746 of file core_armv8mml.h.

## ◆ SCB_CFSR_MSTKERR_Msk [3/3]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 756 of file core_armv81mml.h.

## ◆ SCB_CFSR_MSTKERR_Pos [1/3]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 678 of file core_cm7.h.

## ◆ SCB_CFSR_MSTKERR_Pos [2/3]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 745 of file core_armv8mml.h.

## ◆ SCB_CFSR_MSTKERR_Pos [3/3]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 755 of file core_armv81mml.h.

## ◆ SCB_CFSR_MUNSTKERR_Msk [1/3]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 682 of file core_cm7.h.

## ◆ SCB_CFSR_MUNSTKERR_Msk [2/3]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 749 of file core_armv8mml.h.

## ◆ SCB_CFSR_MUNSTKERR_Msk [3/3]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 759 of file core_armv81mml.h.

## ◆ SCB_CFSR_MUNSTKERR_Pos [1/3]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 681 of file core_cm7.h.

## ◆ SCB_CFSR_MUNSTKERR_Pos [2/3]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 748 of file core_armv8mml.h.

## ◆ SCB_CFSR_MUNSTKERR_Pos [3/3]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 758 of file core_armv81mml.h.

## ◆ SCB_CFSR_NOCP_Msk [1/3]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 720 of file core_cm7.h.

## ◆ SCB_CFSR_NOCP_Msk [2/3]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 790 of file core_armv8mml.h.

## ◆ SCB_CFSR_NOCP_Msk [3/3]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 800 of file core_armv81mml.h.

## ◆ SCB_CFSR_NOCP_Pos [1/3]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 719 of file core_cm7.h.

## ◆ SCB_CFSR_NOCP_Pos [2/3]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 789 of file core_armv8mml.h.

## ◆ SCB_CFSR_NOCP_Pos [3/3]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 799 of file core_armv81mml.h.

## ◆ SCB_CFSR_PRECISERR_Msk [1/3]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 707 of file core_cm7.h.

## ◆ SCB_CFSR_PRECISERR_Msk [2/3]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 774 of file core_armv8mml.h.

## ◆ SCB_CFSR_PRECISERR_Msk [3/3]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 784 of file core_armv81mml.h.

## ◆ SCB_CFSR_PRECISERR_Pos [1/3]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 706 of file core_cm7.h.

## ◆ SCB_CFSR_PRECISERR_Pos [2/3]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 773 of file core_armv8mml.h.

## ◆ SCB_CFSR_PRECISERR_Pos [3/3]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 783 of file core_armv81mml.h.

## ◆ SCB_CFSR_STKERR_Msk [1/3]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 698 of file core_cm7.h.

## ◆ SCB_CFSR_STKERR_Msk [2/3]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 765 of file core_armv8mml.h.

## ◆ SCB_CFSR_STKERR_Msk [3/3]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 775 of file core_armv81mml.h.

## ◆ SCB_CFSR_STKERR_Pos [1/3]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 697 of file core_cm7.h.

## ◆ SCB_CFSR_STKERR_Pos [2/3]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 764 of file core_armv8mml.h.

## ◆ SCB_CFSR_STKERR_Pos [3/3]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 774 of file core_armv81mml.h.

## ◆ SCB_CFSR_STKOF_Msk [1/2]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 787 of file core_armv8mml.h.

## ◆ SCB_CFSR_STKOF_Msk [2/2]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 797 of file core_armv81mml.h.

## ◆ SCB_CFSR_STKOF_Pos [1/2]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 786 of file core_armv8mml.h.

## ◆ SCB_CFSR_STKOF_Pos [2/2]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 796 of file core_armv81mml.h.

## ◆ SCB_CFSR_UNALIGNED_Msk [1/3]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 717 of file core_cm7.h.

## ◆ SCB_CFSR_UNALIGNED_Msk [2/3]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 784 of file core_armv8mml.h.

## ◆ SCB_CFSR_UNALIGNED_Msk [3/3]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 794 of file core_armv81mml.h.

## ◆ SCB_CFSR_UNALIGNED_Pos [1/3]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 716 of file core_cm7.h.

## ◆ SCB_CFSR_UNALIGNED_Pos [2/3]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 783 of file core_armv8mml.h.

## ◆ SCB_CFSR_UNALIGNED_Pos [3/3]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 793 of file core_armv81mml.h.

## ◆ SCB_CFSR_UNDEFINSTR_Msk [1/3]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 729 of file core_cm7.h.

## ◆ SCB_CFSR_UNDEFINSTR_Msk [2/3]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 799 of file core_armv8mml.h.

## ◆ SCB_CFSR_UNDEFINSTR_Msk [3/3]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 809 of file core_armv81mml.h.

## ◆ SCB_CFSR_UNDEFINSTR_Pos [1/3]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 728 of file core_cm7.h.

## ◆ SCB_CFSR_UNDEFINSTR_Pos [2/3]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 798 of file core_armv8mml.h.

## ◆ SCB_CFSR_UNDEFINSTR_Pos [3/3]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 808 of file core_armv81mml.h.

## ◆ SCB_CFSR_UNSTKERR_Msk [1/3]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 701 of file core_cm7.h.

## ◆ SCB_CFSR_UNSTKERR_Msk [2/3]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 768 of file core_armv8mml.h.

## ◆ SCB_CFSR_UNSTKERR_Msk [3/3]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 778 of file core_armv81mml.h.

## ◆ SCB_CFSR_UNSTKERR_Pos [1/3]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 700 of file core_cm7.h.

## ◆ SCB_CFSR_UNSTKERR_Pos [2/3]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 767 of file core_armv8mml.h.

## ◆ SCB_CFSR_UNSTKERR_Pos [3/3]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 777 of file core_armv81mml.h.

## ◆ SCB_CFSR_USGFAULTSR_Msk [1/3]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 663 of file core_cm7.h.

## ◆ SCB_CFSR_USGFAULTSR_Msk [2/3]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 730 of file core_armv8mml.h.

## ◆ SCB_CFSR_USGFAULTSR_Msk [3/3]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 740 of file core_armv81mml.h.

## ◆ SCB_CFSR_USGFAULTSR_Pos [1/3]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 662 of file core_cm7.h.

## ◆ SCB_CFSR_USGFAULTSR_Pos [2/3]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 729 of file core_armv8mml.h.

## ◆ SCB_CFSR_USGFAULTSR_Pos [3/3]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 739 of file core_armv81mml.h.

## ◆ SCB_CLIDR_LOC_Msk [1/3]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 762 of file core_cm7.h.

## ◆ SCB_CLIDR_LOC_Msk [2/3]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 842 of file core_armv8mml.h.

## ◆ SCB_CLIDR_LOC_Msk [3/3]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 852 of file core_armv81mml.h.

## ◆ SCB_CLIDR_LOC_Pos [1/3]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 761 of file core_cm7.h.

## ◆ SCB_CLIDR_LOC_Pos [2/3]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 841 of file core_armv8mml.h.

## ◆ SCB_CLIDR_LOC_Pos [3/3]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 851 of file core_armv81mml.h.

## ◆ SCB_CLIDR_LOUU_Msk [1/3]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 759 of file core_cm7.h.

## ◆ SCB_CLIDR_LOUU_Msk [2/3]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 839 of file core_armv8mml.h.

## ◆ SCB_CLIDR_LOUU_Msk [3/3]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 849 of file core_armv81mml.h.

## ◆ SCB_CLIDR_LOUU_Pos [1/3]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 758 of file core_cm7.h.

## ◆ SCB_CLIDR_LOUU_Pos [2/3]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 838 of file core_armv8mml.h.

## ◆ SCB_CLIDR_LOUU_Pos [3/3]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 848 of file core_armv81mml.h.

## ◆ SCB_CPUID_ARCHITECTURE_Msk [1/4]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 404 of file core_armv8mbl.h.

## ◆ SCB_CPUID_ARCHITECTURE_Msk [2/4]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 515 of file core_cm7.h.

## ◆ SCB_CPUID_ARCHITECTURE_Msk [3/4]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 549 of file core_armv8mml.h.

## ◆ SCB_CPUID_ARCHITECTURE_Msk [4/4]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 559 of file core_armv81mml.h.

## ◆ SCB_CPUID_ARCHITECTURE_Pos [1/4]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 403 of file core_armv8mbl.h.

## ◆ SCB_CPUID_ARCHITECTURE_Pos [2/4]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 514 of file core_cm7.h.

## ◆ SCB_CPUID_ARCHITECTURE_Pos [3/4]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 548 of file core_armv8mml.h.

## ◆ SCB_CPUID_ARCHITECTURE_Pos [4/4]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 558 of file core_armv81mml.h.

## ◆ SCB_CPUID_IMPLEMENTER_Msk [1/4]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 398 of file core_armv8mbl.h.

## ◆ SCB_CPUID_IMPLEMENTER_Msk [2/4]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 509 of file core_cm7.h.

## ◆ SCB_CPUID_IMPLEMENTER_Msk [3/4]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 543 of file core_armv8mml.h.

## ◆ SCB_CPUID_IMPLEMENTER_Msk [4/4]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 553 of file core_armv81mml.h.

## ◆ SCB_CPUID_IMPLEMENTER_Pos [1/4]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 397 of file core_armv8mbl.h.

## ◆ SCB_CPUID_IMPLEMENTER_Pos [2/4]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 508 of file core_cm7.h.

## ◆ SCB_CPUID_IMPLEMENTER_Pos [3/4]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 542 of file core_armv8mml.h.

## ◆ SCB_CPUID_IMPLEMENTER_Pos [4/4]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 552 of file core_armv81mml.h.

## ◆ SCB_CPUID_PARTNO_Msk [1/4]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 407 of file core_armv8mbl.h.

## ◆ SCB_CPUID_PARTNO_Msk [2/4]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 518 of file core_cm7.h.

## ◆ SCB_CPUID_PARTNO_Msk [3/4]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 552 of file core_armv8mml.h.

## ◆ SCB_CPUID_PARTNO_Msk [4/4]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 562 of file core_armv81mml.h.

## ◆ SCB_CPUID_PARTNO_Pos [1/4]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 406 of file core_armv8mbl.h.

## ◆ SCB_CPUID_PARTNO_Pos [2/4]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 517 of file core_cm7.h.

## ◆ SCB_CPUID_PARTNO_Pos [3/4]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 551 of file core_armv8mml.h.

## ◆ SCB_CPUID_PARTNO_Pos [4/4]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 561 of file core_armv81mml.h.

## ◆ SCB_CPUID_REVISION_Msk [1/4]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 410 of file core_armv8mbl.h.

## ◆ SCB_CPUID_REVISION_Msk [2/4]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 521 of file core_cm7.h.

## ◆ SCB_CPUID_REVISION_Msk [3/4]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 555 of file core_armv8mml.h.

## ◆ SCB_CPUID_REVISION_Msk [4/4]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 565 of file core_armv81mml.h.

## ◆ SCB_CPUID_REVISION_Pos [1/4]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 409 of file core_armv8mbl.h.

## ◆ SCB_CPUID_REVISION_Pos [2/4]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 520 of file core_cm7.h.

## ◆ SCB_CPUID_REVISION_Pos [3/4]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 554 of file core_armv8mml.h.

## ◆ SCB_CPUID_REVISION_Pos [4/4]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 564 of file core_armv81mml.h.

## ◆ SCB_CPUID_VARIANT_Msk [1/4]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 401 of file core_armv8mbl.h.

## ◆ SCB_CPUID_VARIANT_Msk [2/4]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 512 of file core_cm7.h.

## ◆ SCB_CPUID_VARIANT_Msk [3/4]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 546 of file core_armv8mml.h.

## ◆ SCB_CPUID_VARIANT_Msk [4/4]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 556 of file core_armv81mml.h.

## ◆ SCB_CPUID_VARIANT_Pos [1/4]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 400 of file core_armv8mbl.h.

## ◆ SCB_CPUID_VARIANT_Pos [2/4]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 511 of file core_cm7.h.

## ◆ SCB_CPUID_VARIANT_Pos [3/4]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 545 of file core_armv8mml.h.

## ◆ SCB_CPUID_VARIANT_Pos [4/4]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 555 of file core_armv81mml.h.

## ◆ SCB_CSSELR_IND_Msk [1/3]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 807 of file core_cm7.h.

## ◆ SCB_CSSELR_IND_Msk [2/3]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 887 of file core_armv8mml.h.

## ◆ SCB_CSSELR_IND_Msk [3/3]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 897 of file core_armv81mml.h.

## ◆ SCB_CSSELR_IND_Pos [1/3]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

Definition at line 806 of file core_cm7.h.

## ◆ SCB_CSSELR_IND_Pos [2/3]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

Definition at line 886 of file core_armv8mml.h.

## ◆ SCB_CSSELR_IND_Pos [3/3]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

Definition at line 896 of file core_armv81mml.h.

## ◆ SCB_CSSELR_LEVEL_Msk [1/3]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 804 of file core_cm7.h.

## ◆ SCB_CSSELR_LEVEL_Msk [2/3]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 884 of file core_armv8mml.h.

## ◆ SCB_CSSELR_LEVEL_Msk [3/3]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 894 of file core_armv81mml.h.

## ◆ SCB_CSSELR_LEVEL_Pos [1/3]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

Definition at line 803 of file core_cm7.h.

## ◆ SCB_CSSELR_LEVEL_Pos [2/3]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

Definition at line 883 of file core_armv8mml.h.

## ◆ SCB_CSSELR_LEVEL_Pos [3/3]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

Definition at line 893 of file core_armv81mml.h.

## ◆ SCB_CTR_CWG_Msk [1/3]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 769 of file core_cm7.h.

## ◆ SCB_CTR_CWG_Msk [2/3]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 849 of file core_armv8mml.h.

## ◆ SCB_CTR_CWG_Msk [3/3]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 859 of file core_armv81mml.h.

## ◆ SCB_CTR_CWG_Pos [1/3]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

Definition at line 768 of file core_cm7.h.

## ◆ SCB_CTR_CWG_Pos [2/3]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

Definition at line 848 of file core_armv8mml.h.

## ◆ SCB_CTR_CWG_Pos [3/3]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

Definition at line 858 of file core_armv81mml.h.

## ◆ SCB_CTR_DMINLINE_Msk [1/3]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 775 of file core_cm7.h.

## ◆ SCB_CTR_DMINLINE_Msk [2/3]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 855 of file core_armv8mml.h.

## ◆ SCB_CTR_DMINLINE_Msk [3/3]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 865 of file core_armv81mml.h.

## ◆ SCB_CTR_DMINLINE_Pos [1/3]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

Definition at line 774 of file core_cm7.h.

## ◆ SCB_CTR_DMINLINE_Pos [2/3]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

Definition at line 854 of file core_armv8mml.h.

## ◆ SCB_CTR_DMINLINE_Pos [3/3]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

Definition at line 864 of file core_armv81mml.h.

## ◆ SCB_CTR_ERG_Msk [1/3]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 772 of file core_cm7.h.

## ◆ SCB_CTR_ERG_Msk [2/3]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 852 of file core_armv8mml.h.

## ◆ SCB_CTR_ERG_Msk [3/3]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 862 of file core_armv81mml.h.

## ◆ SCB_CTR_ERG_Pos [1/3]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

Definition at line 771 of file core_cm7.h.

## ◆ SCB_CTR_ERG_Pos [2/3]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

Definition at line 851 of file core_armv8mml.h.

## ◆ SCB_CTR_ERG_Pos [3/3]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

Definition at line 861 of file core_armv81mml.h.

## ◆ SCB_CTR_FORMAT_Msk [1/3]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 766 of file core_cm7.h.

## ◆ SCB_CTR_FORMAT_Msk [2/3]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 846 of file core_armv8mml.h.

## ◆ SCB_CTR_FORMAT_Msk [3/3]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 856 of file core_armv81mml.h.

## ◆ SCB_CTR_FORMAT_Pos [1/3]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

Definition at line 765 of file core_cm7.h.

## ◆ SCB_CTR_FORMAT_Pos [2/3]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

Definition at line 845 of file core_armv8mml.h.

## ◆ SCB_CTR_FORMAT_Pos [3/3]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

Definition at line 855 of file core_armv81mml.h.

## ◆ SCB_CTR_IMINLINE_Msk [1/3]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 778 of file core_cm7.h.

## ◆ SCB_CTR_IMINLINE_Msk [2/3]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 858 of file core_armv8mml.h.

## ◆ SCB_CTR_IMINLINE_Msk [3/3]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 868 of file core_armv81mml.h.

## ◆ SCB_CTR_IMINLINE_Pos [1/3]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

Definition at line 777 of file core_cm7.h.

## ◆ SCB_CTR_IMINLINE_Pos [2/3]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

Definition at line 857 of file core_armv8mml.h.

## ◆ SCB_CTR_IMINLINE_Pos [3/3]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

Definition at line 867 of file core_armv81mml.h.

## ◆ SCB_DCCISW_SET_Msk [1/3]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 832 of file core_cm7.h.

## ◆ SCB_DCCISW_SET_Msk [2/3]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 912 of file core_armv8mml.h.

## ◆ SCB_DCCISW_SET_Msk [3/3]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 922 of file core_armv81mml.h.

## ◆ SCB_DCCISW_SET_Pos [1/3]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

Definition at line 831 of file core_cm7.h.

## ◆ SCB_DCCISW_SET_Pos [2/3]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

Definition at line 911 of file core_armv8mml.h.

## ◆ SCB_DCCISW_SET_Pos [3/3]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

Definition at line 921 of file core_armv81mml.h.

## ◆ SCB_DCCISW_WAY_Msk [1/3]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 829 of file core_cm7.h.

## ◆ SCB_DCCISW_WAY_Msk [2/3]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 909 of file core_armv8mml.h.

## ◆ SCB_DCCISW_WAY_Msk [3/3]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 919 of file core_armv81mml.h.

## ◆ SCB_DCCISW_WAY_Pos [1/3]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

Definition at line 828 of file core_cm7.h.

## ◆ SCB_DCCISW_WAY_Pos [2/3]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

Definition at line 908 of file core_armv8mml.h.

## ◆ SCB_DCCISW_WAY_Pos [3/3]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

Definition at line 918 of file core_armv81mml.h.

## ◆ SCB_DCCSW_SET_Msk [1/3]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 825 of file core_cm7.h.

## ◆ SCB_DCCSW_SET_Msk [2/3]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 905 of file core_armv8mml.h.

## ◆ SCB_DCCSW_SET_Msk [3/3]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 915 of file core_armv81mml.h.

## ◆ SCB_DCCSW_SET_Pos [1/3]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

Definition at line 824 of file core_cm7.h.

## ◆ SCB_DCCSW_SET_Pos [2/3]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

Definition at line 904 of file core_armv8mml.h.

## ◆ SCB_DCCSW_SET_Pos [3/3]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

Definition at line 914 of file core_armv81mml.h.

## ◆ SCB_DCCSW_WAY_Msk [1/3]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 822 of file core_cm7.h.

## ◆ SCB_DCCSW_WAY_Msk [2/3]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 902 of file core_armv8mml.h.

## ◆ SCB_DCCSW_WAY_Msk [3/3]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 912 of file core_armv81mml.h.

## ◆ SCB_DCCSW_WAY_Pos [1/3]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

Definition at line 821 of file core_cm7.h.

## ◆ SCB_DCCSW_WAY_Pos [2/3]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

Definition at line 901 of file core_armv8mml.h.

## ◆ SCB_DCCSW_WAY_Pos [3/3]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

Definition at line 911 of file core_armv81mml.h.

## ◆ SCB_DCISW_SET_Msk [1/3]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 818 of file core_cm7.h.

## ◆ SCB_DCISW_SET_Msk [2/3]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 898 of file core_armv8mml.h.

## ◆ SCB_DCISW_SET_Msk [3/3]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 908 of file core_armv81mml.h.

## ◆ SCB_DCISW_SET_Pos [1/3]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

Definition at line 817 of file core_cm7.h.

## ◆ SCB_DCISW_SET_Pos [2/3]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

Definition at line 897 of file core_armv8mml.h.

## ◆ SCB_DCISW_SET_Pos [3/3]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

Definition at line 907 of file core_armv81mml.h.

## ◆ SCB_DCISW_WAY_Msk [1/3]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 815 of file core_cm7.h.

## ◆ SCB_DCISW_WAY_Msk [2/3]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 895 of file core_armv8mml.h.

## ◆ SCB_DCISW_WAY_Msk [3/3]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 905 of file core_armv81mml.h.

## ◆ SCB_DCISW_WAY_Pos [1/3]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

Definition at line 814 of file core_cm7.h.

## ◆ SCB_DCISW_WAY_Pos [2/3]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

Definition at line 894 of file core_armv8mml.h.

## ◆ SCB_DCISW_WAY_Pos [3/3]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

Definition at line 904 of file core_armv81mml.h.

## ◆ SCB_DFSR_BKPT_Msk [1/3]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 752 of file core_cm7.h.

## ◆ SCB_DFSR_BKPT_Msk [2/3]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 822 of file core_armv8mml.h.

## ◆ SCB_DFSR_BKPT_Msk [3/3]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 832 of file core_armv81mml.h.

## ◆ SCB_DFSR_BKPT_Pos [1/3]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 751 of file core_cm7.h.

## ◆ SCB_DFSR_BKPT_Pos [2/3]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 821 of file core_armv8mml.h.

## ◆ SCB_DFSR_BKPT_Pos [3/3]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 831 of file core_armv81mml.h.

## ◆ SCB_DFSR_DWTTRAP_Msk [1/3]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 749 of file core_cm7.h.

## ◆ SCB_DFSR_DWTTRAP_Msk [2/3]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 819 of file core_armv8mml.h.

## ◆ SCB_DFSR_DWTTRAP_Msk [3/3]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 829 of file core_armv81mml.h.

## ◆ SCB_DFSR_DWTTRAP_Pos [1/3]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 748 of file core_cm7.h.

## ◆ SCB_DFSR_DWTTRAP_Pos [2/3]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 818 of file core_armv8mml.h.

## ◆ SCB_DFSR_DWTTRAP_Pos [3/3]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 828 of file core_armv81mml.h.

## ◆ SCB_DFSR_EXTERNAL_Msk [1/3]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 743 of file core_cm7.h.

## ◆ SCB_DFSR_EXTERNAL_Msk [2/3]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 813 of file core_armv8mml.h.

## ◆ SCB_DFSR_EXTERNAL_Msk [3/3]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 823 of file core_armv81mml.h.

## ◆ SCB_DFSR_EXTERNAL_Pos [1/3]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 742 of file core_cm7.h.

## ◆ SCB_DFSR_EXTERNAL_Pos [2/3]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 812 of file core_armv8mml.h.

## ◆ SCB_DFSR_EXTERNAL_Pos [3/3]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 822 of file core_armv81mml.h.

## ◆ SCB_DFSR_HALTED_Msk [1/3]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 755 of file core_cm7.h.

## ◆ SCB_DFSR_HALTED_Msk [2/3]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 825 of file core_armv8mml.h.

## ◆ SCB_DFSR_HALTED_Msk [3/3]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 835 of file core_armv81mml.h.

## ◆ SCB_DFSR_HALTED_Pos [1/3]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 754 of file core_cm7.h.

## ◆ SCB_DFSR_HALTED_Pos [2/3]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 824 of file core_armv8mml.h.

## ◆ SCB_DFSR_HALTED_Pos [3/3]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 834 of file core_armv81mml.h.

## ◆ SCB_DFSR_VCATCH_Msk [1/3]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 746 of file core_cm7.h.

## ◆ SCB_DFSR_VCATCH_Msk [2/3]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 816 of file core_armv8mml.h.

## ◆ SCB_DFSR_VCATCH_Msk [3/3]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 826 of file core_armv81mml.h.

## ◆ SCB_DFSR_VCATCH_Pos [1/3]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 745 of file core_cm7.h.

## ◆ SCB_DFSR_VCATCH_Pos [2/3]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 815 of file core_armv8mml.h.

## ◆ SCB_DFSR_VCATCH_Pos [3/3]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 825 of file core_armv81mml.h.

## ◆ SCB_DTCMCR_EN_Msk [1/2]

#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 858 of file core_cm7.h.

## ◆ SCB_DTCMCR_EN_Msk [2/2]

#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 948 of file core_armv81mml.h.

## ◆ SCB_DTCMCR_EN_Pos [1/2]

#define SCB_DTCMCR_EN_Pos 0U

SCB DTCMCR: EN Position

Definition at line 857 of file core_cm7.h.

## ◆ SCB_DTCMCR_EN_Pos [2/2]

#define SCB_DTCMCR_EN_Pos 0U

SCB DTCMCR: EN Position

Definition at line 947 of file core_armv81mml.h.

## ◆ SCB_DTCMCR_RETEN_Msk [1/2]

#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 852 of file core_cm7.h.

## ◆ SCB_DTCMCR_RETEN_Msk [2/2]

#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 942 of file core_armv81mml.h.

## ◆ SCB_DTCMCR_RETEN_Pos [1/2]

#define SCB_DTCMCR_RETEN_Pos 2U

SCB DTCMCR: RETEN Position

Definition at line 851 of file core_cm7.h.

## ◆ SCB_DTCMCR_RETEN_Pos [2/2]

#define SCB_DTCMCR_RETEN_Pos 2U

SCB DTCMCR: RETEN Position

Definition at line 941 of file core_armv81mml.h.

## ◆ SCB_DTCMCR_RMW_Msk [1/2]

#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 855 of file core_cm7.h.

## ◆ SCB_DTCMCR_RMW_Msk [2/2]

#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 945 of file core_armv81mml.h.

## ◆ SCB_DTCMCR_RMW_Pos [1/2]

#define SCB_DTCMCR_RMW_Pos 1U

SCB DTCMCR: RMW Position

Definition at line 854 of file core_cm7.h.

## ◆ SCB_DTCMCR_RMW_Pos [2/2]

#define SCB_DTCMCR_RMW_Pos 1U

SCB DTCMCR: RMW Position

Definition at line 944 of file core_armv81mml.h.

## ◆ SCB_DTCMCR_SZ_Msk [1/2]

#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 849 of file core_cm7.h.

## ◆ SCB_DTCMCR_SZ_Msk [2/2]

#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 939 of file core_armv81mml.h.

## ◆ SCB_DTCMCR_SZ_Pos [1/2]

#define SCB_DTCMCR_SZ_Pos 3U

SCB DTCMCR: SZ Position

Definition at line 848 of file core_cm7.h.

## ◆ SCB_DTCMCR_SZ_Pos [2/2]

#define SCB_DTCMCR_SZ_Pos 3U

SCB DTCMCR: SZ Position

Definition at line 938 of file core_armv81mml.h.

## ◆ SCB_HFSR_DEBUGEVT_Msk [1/3]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 733 of file core_cm7.h.

## ◆ SCB_HFSR_DEBUGEVT_Msk [2/3]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 803 of file core_armv8mml.h.

## ◆ SCB_HFSR_DEBUGEVT_Msk [3/3]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 813 of file core_armv81mml.h.

## ◆ SCB_HFSR_DEBUGEVT_Pos [1/3]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 732 of file core_cm7.h.

## ◆ SCB_HFSR_DEBUGEVT_Pos [2/3]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 802 of file core_armv8mml.h.

## ◆ SCB_HFSR_DEBUGEVT_Pos [3/3]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 812 of file core_armv81mml.h.

## ◆ SCB_HFSR_FORCED_Msk [1/3]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 736 of file core_cm7.h.

## ◆ SCB_HFSR_FORCED_Msk [2/3]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 806 of file core_armv8mml.h.

## ◆ SCB_HFSR_FORCED_Msk [3/3]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 816 of file core_armv81mml.h.

## ◆ SCB_HFSR_FORCED_Pos [1/3]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 735 of file core_cm7.h.

## ◆ SCB_HFSR_FORCED_Pos [2/3]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 805 of file core_armv8mml.h.

## ◆ SCB_HFSR_FORCED_Pos [3/3]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 815 of file core_armv81mml.h.

## ◆ SCB_HFSR_VECTTBL_Msk [1/3]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 739 of file core_cm7.h.

## ◆ SCB_HFSR_VECTTBL_Msk [2/3]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 809 of file core_armv8mml.h.

## ◆ SCB_HFSR_VECTTBL_Msk [3/3]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 819 of file core_armv81mml.h.

## ◆ SCB_HFSR_VECTTBL_Pos [1/3]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 738 of file core_cm7.h.

## ◆ SCB_HFSR_VECTTBL_Pos [2/3]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 808 of file core_armv8mml.h.

## ◆ SCB_HFSR_VECTTBL_Pos [3/3]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 818 of file core_armv81mml.h.

## ◆ SCB_ICSR_ISRPENDING_Msk [1/4]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 441 of file core_armv8mbl.h.

## ◆ SCB_ICSR_ISRPENDING_Msk [2/4]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 543 of file core_cm7.h.

## ◆ SCB_ICSR_ISRPENDING_Msk [3/4]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 586 of file core_armv8mml.h.

## ◆ SCB_ICSR_ISRPENDING_Msk [4/4]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 596 of file core_armv81mml.h.

## ◆ SCB_ICSR_ISRPENDING_Pos [1/4]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 440 of file core_armv8mbl.h.

## ◆ SCB_ICSR_ISRPENDING_Pos [2/4]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 542 of file core_cm7.h.

## ◆ SCB_ICSR_ISRPENDING_Pos [3/4]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 585 of file core_armv8mml.h.

## ◆ SCB_ICSR_ISRPENDING_Pos [4/4]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 595 of file core_armv81mml.h.

## ◆ SCB_ICSR_ISRPREEMPT_Msk [1/4]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 438 of file core_armv8mbl.h.

## ◆ SCB_ICSR_ISRPREEMPT_Msk [2/4]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 540 of file core_cm7.h.

## ◆ SCB_ICSR_ISRPREEMPT_Msk [3/4]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 583 of file core_armv8mml.h.

## ◆ SCB_ICSR_ISRPREEMPT_Msk [4/4]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 593 of file core_armv81mml.h.

## ◆ SCB_ICSR_ISRPREEMPT_Pos [1/4]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 437 of file core_armv8mbl.h.

## ◆ SCB_ICSR_ISRPREEMPT_Pos [2/4]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 539 of file core_cm7.h.

## ◆ SCB_ICSR_ISRPREEMPT_Pos [3/4]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 582 of file core_armv8mml.h.

## ◆ SCB_ICSR_ISRPREEMPT_Pos [4/4]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 592 of file core_armv81mml.h.

## ◆ SCB_ICSR_NMIPENDSET_Msk [1/4]

#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 417 of file core_armv8mbl.h.

## ◆ SCB_ICSR_NMIPENDSET_Msk [2/4]

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 525 of file core_cm7.h.

## ◆ SCB_ICSR_NMIPENDSET_Msk [3/4]

#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 562 of file core_armv8mml.h.

## ◆ SCB_ICSR_NMIPENDSET_Msk [4/4]

#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 572 of file core_armv81mml.h.

## ◆ SCB_ICSR_NMIPENDSET_Pos [1/4]

#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 416 of file core_armv8mbl.h.

## ◆ SCB_ICSR_NMIPENDSET_Pos [2/4]

#define SCB_ICSR_NMIPENDSET_Pos 31U

SCB ICSR: NMIPENDSET Position

Definition at line 524 of file core_cm7.h.

## ◆ SCB_ICSR_NMIPENDSET_Pos [3/4]

#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 561 of file core_armv8mml.h.

## ◆ SCB_ICSR_NMIPENDSET_Pos [4/4]

#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 571 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDNMICLR_Msk [1/3]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 420 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDNMICLR_Msk [2/3]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 565 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDNMICLR_Msk [3/3]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 575 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDNMICLR_Pos [1/3]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 419 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDNMICLR_Pos [2/3]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 564 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDNMICLR_Pos [3/3]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 574 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDNMISET_Msk [1/3]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 414 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDNMISET_Msk [2/3]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 559 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDNMISET_Msk [3/3]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 569 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDNMISET_Pos [1/3]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 413 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDNMISET_Pos [2/3]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 558 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDNMISET_Pos [3/3]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 568 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDSTCLR_Msk [1/4]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 432 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDSTCLR_Msk [2/4]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 537 of file core_cm7.h.

## ◆ SCB_ICSR_PENDSTCLR_Msk [3/4]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 577 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDSTCLR_Msk [4/4]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 587 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDSTCLR_Pos [1/4]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 431 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDSTCLR_Pos [2/4]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 536 of file core_cm7.h.

## ◆ SCB_ICSR_PENDSTCLR_Pos [3/4]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 576 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDSTCLR_Pos [4/4]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 586 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDSTSET_Msk [1/4]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 429 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDSTSET_Msk [2/4]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 534 of file core_cm7.h.

## ◆ SCB_ICSR_PENDSTSET_Msk [3/4]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 574 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDSTSET_Msk [4/4]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 584 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDSTSET_Pos [1/4]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 428 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDSTSET_Pos [2/4]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 533 of file core_cm7.h.

## ◆ SCB_ICSR_PENDSTSET_Pos [3/4]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 573 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDSTSET_Pos [4/4]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 583 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDSVCLR_Msk [1/4]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 426 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDSVCLR_Msk [2/4]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 531 of file core_cm7.h.

## ◆ SCB_ICSR_PENDSVCLR_Msk [3/4]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 571 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDSVCLR_Msk [4/4]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 581 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDSVCLR_Pos [1/4]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 425 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDSVCLR_Pos [2/4]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 530 of file core_cm7.h.

## ◆ SCB_ICSR_PENDSVCLR_Pos [3/4]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 570 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDSVCLR_Pos [4/4]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 580 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDSVSET_Msk [1/4]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 423 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDSVSET_Msk [2/4]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 528 of file core_cm7.h.

## ◆ SCB_ICSR_PENDSVSET_Msk [3/4]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 568 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDSVSET_Msk [4/4]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 578 of file core_armv81mml.h.

## ◆ SCB_ICSR_PENDSVSET_Pos [1/4]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 422 of file core_armv8mbl.h.

## ◆ SCB_ICSR_PENDSVSET_Pos [2/4]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 527 of file core_cm7.h.

## ◆ SCB_ICSR_PENDSVSET_Pos [3/4]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 567 of file core_armv8mml.h.

## ◆ SCB_ICSR_PENDSVSET_Pos [4/4]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 577 of file core_armv81mml.h.

## ◆ SCB_ICSR_RETTOBASE_Msk [1/4]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 447 of file core_armv8mbl.h.

## ◆ SCB_ICSR_RETTOBASE_Msk [2/4]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 549 of file core_cm7.h.

## ◆ SCB_ICSR_RETTOBASE_Msk [3/4]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 592 of file core_armv8mml.h.

## ◆ SCB_ICSR_RETTOBASE_Msk [4/4]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 602 of file core_armv81mml.h.

## ◆ SCB_ICSR_RETTOBASE_Pos [1/4]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 446 of file core_armv8mbl.h.

## ◆ SCB_ICSR_RETTOBASE_Pos [2/4]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 548 of file core_cm7.h.

## ◆ SCB_ICSR_RETTOBASE_Pos [3/4]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 591 of file core_armv8mml.h.

## ◆ SCB_ICSR_RETTOBASE_Pos [4/4]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 601 of file core_armv81mml.h.

## ◆ SCB_ICSR_STTNS_Msk [1/3]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 435 of file core_armv8mbl.h.

## ◆ SCB_ICSR_STTNS_Msk [2/3]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 580 of file core_armv8mml.h.

## ◆ SCB_ICSR_STTNS_Msk [3/3]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 590 of file core_armv81mml.h.

## ◆ SCB_ICSR_STTNS_Pos [1/3]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 434 of file core_armv8mbl.h.

## ◆ SCB_ICSR_STTNS_Pos [2/3]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 579 of file core_armv8mml.h.

## ◆ SCB_ICSR_STTNS_Pos [3/3]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 589 of file core_armv81mml.h.

## ◆ SCB_ICSR_VECTACTIVE_Msk [1/4]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 450 of file core_armv8mbl.h.

## ◆ SCB_ICSR_VECTACTIVE_Msk [2/4]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 552 of file core_cm7.h.

## ◆ SCB_ICSR_VECTACTIVE_Msk [3/4]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 595 of file core_armv8mml.h.

## ◆ SCB_ICSR_VECTACTIVE_Msk [4/4]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 605 of file core_armv81mml.h.

## ◆ SCB_ICSR_VECTACTIVE_Pos [1/4]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 449 of file core_armv8mbl.h.

## ◆ SCB_ICSR_VECTACTIVE_Pos [2/4]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 551 of file core_cm7.h.

## ◆ SCB_ICSR_VECTACTIVE_Pos [3/4]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 594 of file core_armv8mml.h.

## ◆ SCB_ICSR_VECTACTIVE_Pos [4/4]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 604 of file core_armv81mml.h.

## ◆ SCB_ICSR_VECTPENDING_Msk [1/4]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 444 of file core_armv8mbl.h.

## ◆ SCB_ICSR_VECTPENDING_Msk [2/4]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 546 of file core_cm7.h.

## ◆ SCB_ICSR_VECTPENDING_Msk [3/4]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 589 of file core_armv8mml.h.

## ◆ SCB_ICSR_VECTPENDING_Msk [4/4]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 599 of file core_armv81mml.h.

## ◆ SCB_ICSR_VECTPENDING_Pos [1/4]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 443 of file core_armv8mbl.h.

## ◆ SCB_ICSR_VECTPENDING_Pos [2/4]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 545 of file core_cm7.h.

## ◆ SCB_ICSR_VECTPENDING_Pos [3/4]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 588 of file core_armv8mml.h.

## ◆ SCB_ICSR_VECTPENDING_Pos [4/4]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 598 of file core_armv81mml.h.

## ◆ SCB_ITCMCR_EN_Msk [1/2]

#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 845 of file core_cm7.h.

## ◆ SCB_ITCMCR_EN_Msk [2/2]

#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 935 of file core_armv81mml.h.

## ◆ SCB_ITCMCR_EN_Pos [1/2]

#define SCB_ITCMCR_EN_Pos 0U

SCB ITCMCR: EN Position

Definition at line 844 of file core_cm7.h.

## ◆ SCB_ITCMCR_EN_Pos [2/2]

#define SCB_ITCMCR_EN_Pos 0U

SCB ITCMCR: EN Position

Definition at line 934 of file core_armv81mml.h.

## ◆ SCB_ITCMCR_RETEN_Msk [1/2]

#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 839 of file core_cm7.h.

## ◆ SCB_ITCMCR_RETEN_Msk [2/2]

#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 929 of file core_armv81mml.h.

## ◆ SCB_ITCMCR_RETEN_Pos [1/2]

#define SCB_ITCMCR_RETEN_Pos 2U

SCB ITCMCR: RETEN Position

Definition at line 838 of file core_cm7.h.

## ◆ SCB_ITCMCR_RETEN_Pos [2/2]

#define SCB_ITCMCR_RETEN_Pos 2U

SCB ITCMCR: RETEN Position

Definition at line 928 of file core_armv81mml.h.

## ◆ SCB_ITCMCR_RMW_Msk [1/2]

#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 842 of file core_cm7.h.

## ◆ SCB_ITCMCR_RMW_Msk [2/2]

#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 932 of file core_armv81mml.h.

## ◆ SCB_ITCMCR_RMW_Pos [1/2]

#define SCB_ITCMCR_RMW_Pos 1U

SCB ITCMCR: RMW Position

Definition at line 841 of file core_cm7.h.

## ◆ SCB_ITCMCR_RMW_Pos [2/2]

#define SCB_ITCMCR_RMW_Pos 1U

SCB ITCMCR: RMW Position

Definition at line 931 of file core_armv81mml.h.

## ◆ SCB_ITCMCR_SZ_Msk [1/2]

#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 836 of file core_cm7.h.

## ◆ SCB_ITCMCR_SZ_Msk [2/2]

#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 926 of file core_armv81mml.h.

## ◆ SCB_ITCMCR_SZ_Pos [1/2]

#define SCB_ITCMCR_SZ_Pos 3U

SCB ITCMCR: SZ Position

Definition at line 835 of file core_cm7.h.

## ◆ SCB_ITCMCR_SZ_Pos [2/2]

#define SCB_ITCMCR_SZ_Pos 3U

SCB ITCMCR: SZ Position

Definition at line 925 of file core_armv81mml.h.

## ◆ SCB_NSACR_CP10_Msk [1/2]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 832 of file core_armv8mml.h.

## ◆ SCB_NSACR_CP10_Msk [2/2]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 842 of file core_armv81mml.h.

## ◆ SCB_NSACR_CP10_Pos [1/2]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

Definition at line 831 of file core_armv8mml.h.

## ◆ SCB_NSACR_CP10_Pos [2/2]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

Definition at line 841 of file core_armv81mml.h.

## ◆ SCB_NSACR_CP11_Msk [1/2]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 829 of file core_armv8mml.h.

## ◆ SCB_NSACR_CP11_Msk [2/2]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 839 of file core_armv81mml.h.

## ◆ SCB_NSACR_CP11_Pos [1/2]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

Definition at line 828 of file core_armv8mml.h.

## ◆ SCB_NSACR_CP11_Pos [2/2]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

Definition at line 838 of file core_armv81mml.h.

## ◆ SCB_NSACR_CPn_Msk [1/2]

#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 835 of file core_armv8mml.h.

## ◆ SCB_NSACR_CPn_Msk [2/2]

#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 845 of file core_armv81mml.h.

## ◆ SCB_NSACR_CPn_Pos [1/2]

#define SCB_NSACR_CPn_Pos 0U

SCB NSACR: CPn Position

Definition at line 834 of file core_armv8mml.h.

## ◆ SCB_NSACR_CPn_Pos [2/2]

#define SCB_NSACR_CPn_Pos 0U

SCB NSACR: CPn Position

Definition at line 844 of file core_armv81mml.h.

## ◆ SCB_SCR_SEVONPEND_Msk [1/4]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 485 of file core_armv8mbl.h.

## ◆ SCB_SCR_SEVONPEND_Msk [2/4]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 582 of file core_cm7.h.

## ◆ SCB_SCR_SEVONPEND_Msk [3/4]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 631 of file core_armv8mml.h.

## ◆ SCB_SCR_SEVONPEND_Msk [4/4]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 641 of file core_armv81mml.h.

## ◆ SCB_SCR_SEVONPEND_Pos [1/4]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 484 of file core_armv8mbl.h.

## ◆ SCB_SCR_SEVONPEND_Pos [2/4]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 581 of file core_cm7.h.

## ◆ SCB_SCR_SEVONPEND_Pos [3/4]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 630 of file core_armv8mml.h.

## ◆ SCB_SCR_SEVONPEND_Pos [4/4]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 640 of file core_armv81mml.h.

## ◆ SCB_SCR_SLEEPDEEP_Msk [1/4]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 491 of file core_armv8mbl.h.

## ◆ SCB_SCR_SLEEPDEEP_Msk [2/4]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 585 of file core_cm7.h.

## ◆ SCB_SCR_SLEEPDEEP_Msk [3/4]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 637 of file core_armv8mml.h.

## ◆ SCB_SCR_SLEEPDEEP_Msk [4/4]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 647 of file core_armv81mml.h.

## ◆ SCB_SCR_SLEEPDEEP_Pos [1/4]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 490 of file core_armv8mbl.h.

## ◆ SCB_SCR_SLEEPDEEP_Pos [2/4]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 584 of file core_cm7.h.

## ◆ SCB_SCR_SLEEPDEEP_Pos [3/4]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 636 of file core_armv8mml.h.

## ◆ SCB_SCR_SLEEPDEEP_Pos [4/4]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 646 of file core_armv81mml.h.

## ◆ SCB_SCR_SLEEPDEEPS_Msk [1/3]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 488 of file core_armv8mbl.h.

## ◆ SCB_SCR_SLEEPDEEPS_Msk [2/3]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 634 of file core_armv8mml.h.

## ◆ SCB_SCR_SLEEPDEEPS_Msk [3/3]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 644 of file core_armv81mml.h.

## ◆ SCB_SCR_SLEEPDEEPS_Pos [1/3]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 487 of file core_armv8mbl.h.

## ◆ SCB_SCR_SLEEPDEEPS_Pos [2/3]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 633 of file core_armv8mml.h.

## ◆ SCB_SCR_SLEEPDEEPS_Pos [3/3]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 643 of file core_armv81mml.h.

## ◆ SCB_SCR_SLEEPONEXIT_Msk [1/4]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 494 of file core_armv8mbl.h.

## ◆ SCB_SCR_SLEEPONEXIT_Msk [2/4]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 588 of file core_cm7.h.

## ◆ SCB_SCR_SLEEPONEXIT_Msk [3/4]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 640 of file core_armv8mml.h.

## ◆ SCB_SCR_SLEEPONEXIT_Msk [4/4]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 650 of file core_armv81mml.h.

## ◆ SCB_SCR_SLEEPONEXIT_Pos [1/4]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 493 of file core_armv8mbl.h.

## ◆ SCB_SCR_SLEEPONEXIT_Pos [2/4]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 587 of file core_cm7.h.

## ◆ SCB_SCR_SLEEPONEXIT_Pos [3/4]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 639 of file core_armv8mml.h.

## ◆ SCB_SCR_SLEEPONEXIT_Pos [4/4]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 649 of file core_armv81mml.h.

## ◆ SCB_SHCSR_BUSFAULTACT_Msk [1/3]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 656 of file core_cm7.h.

## ◆ SCB_SHCSR_BUSFAULTACT_Msk [2/3]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 723 of file core_armv8mml.h.

## ◆ SCB_SHCSR_BUSFAULTACT_Msk [3/3]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 733 of file core_armv81mml.h.

## ◆ SCB_SHCSR_BUSFAULTACT_Pos [1/3]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 655 of file core_cm7.h.

## ◆ SCB_SHCSR_BUSFAULTACT_Pos [2/3]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 722 of file core_armv8mml.h.

## ◆ SCB_SHCSR_BUSFAULTACT_Pos [3/3]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 732 of file core_armv81mml.h.

## ◆ SCB_SHCSR_BUSFAULTENA_Msk [1/3]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 623 of file core_cm7.h.

## ◆ SCB_SHCSR_BUSFAULTENA_Msk [2/3]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 681 of file core_armv8mml.h.

## ◆ SCB_SHCSR_BUSFAULTENA_Msk [3/3]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 691 of file core_armv81mml.h.

## ◆ SCB_SHCSR_BUSFAULTENA_Pos [1/3]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 622 of file core_cm7.h.

## ◆ SCB_SHCSR_BUSFAULTENA_Pos [2/3]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 680 of file core_armv8mml.h.

## ◆ SCB_SHCSR_BUSFAULTENA_Pos [3/3]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 690 of file core_armv81mml.h.

## ◆ SCB_SHCSR_BUSFAULTPENDED_Msk [1/3]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 632 of file core_cm7.h.

## ◆ SCB_SHCSR_BUSFAULTPENDED_Msk [2/3]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 690 of file core_armv8mml.h.

## ◆ SCB_SHCSR_BUSFAULTPENDED_Msk [3/3]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 700 of file core_armv81mml.h.

## ◆ SCB_SHCSR_BUSFAULTPENDED_Pos [1/3]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 631 of file core_cm7.h.

## ◆ SCB_SHCSR_BUSFAULTPENDED_Pos [2/3]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 689 of file core_armv8mml.h.

## ◆ SCB_SHCSR_BUSFAULTPENDED_Pos [3/3]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 699 of file core_armv81mml.h.

## ◆ SCB_SHCSR_HARDFAULTACT_Msk [1/3]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 541 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_HARDFAULTACT_Msk [2/3]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 720 of file core_armv8mml.h.

## ◆ SCB_SHCSR_HARDFAULTACT_Msk [3/3]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 730 of file core_armv81mml.h.

## ◆ SCB_SHCSR_HARDFAULTACT_Pos [1/3]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 540 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_HARDFAULTACT_Pos [2/3]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 719 of file core_armv8mml.h.

## ◆ SCB_SHCSR_HARDFAULTACT_Pos [3/3]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 729 of file core_armv81mml.h.

## ◆ SCB_SHCSR_HARDFAULTPENDED_Msk [1/3]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 523 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_HARDFAULTPENDED_Msk [2/3]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 669 of file core_armv8mml.h.

## ◆ SCB_SHCSR_HARDFAULTPENDED_Msk [3/3]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 679 of file core_armv81mml.h.

## ◆ SCB_SHCSR_HARDFAULTPENDED_Pos [1/3]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 522 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_HARDFAULTPENDED_Pos [2/3]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 668 of file core_armv8mml.h.

## ◆ SCB_SHCSR_HARDFAULTPENDED_Pos [3/3]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 678 of file core_armv81mml.h.

## ◆ SCB_SHCSR_MEMFAULTACT_Msk [1/3]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 659 of file core_cm7.h.

## ◆ SCB_SHCSR_MEMFAULTACT_Msk [2/3]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 726 of file core_armv8mml.h.

## ◆ SCB_SHCSR_MEMFAULTACT_Msk [3/3]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 736 of file core_armv81mml.h.

## ◆ SCB_SHCSR_MEMFAULTACT_Pos [1/3]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 658 of file core_cm7.h.

## ◆ SCB_SHCSR_MEMFAULTACT_Pos [2/3]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 725 of file core_armv8mml.h.

## ◆ SCB_SHCSR_MEMFAULTACT_Pos [3/3]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 735 of file core_armv81mml.h.

## ◆ SCB_SHCSR_MEMFAULTENA_Msk [1/3]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 626 of file core_cm7.h.

## ◆ SCB_SHCSR_MEMFAULTENA_Msk [2/3]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 684 of file core_armv8mml.h.

## ◆ SCB_SHCSR_MEMFAULTENA_Msk [3/3]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 694 of file core_armv81mml.h.

## ◆ SCB_SHCSR_MEMFAULTENA_Pos [1/3]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 625 of file core_cm7.h.

## ◆ SCB_SHCSR_MEMFAULTENA_Pos [2/3]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 683 of file core_armv8mml.h.

## ◆ SCB_SHCSR_MEMFAULTENA_Pos [3/3]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 693 of file core_armv81mml.h.

## ◆ SCB_SHCSR_MEMFAULTPENDED_Msk [1/3]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 635 of file core_cm7.h.

## ◆ SCB_SHCSR_MEMFAULTPENDED_Msk [2/3]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 693 of file core_armv8mml.h.

## ◆ SCB_SHCSR_MEMFAULTPENDED_Msk [3/3]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 703 of file core_armv81mml.h.

## ◆ SCB_SHCSR_MEMFAULTPENDED_Pos [1/3]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 634 of file core_cm7.h.

## ◆ SCB_SHCSR_MEMFAULTPENDED_Pos [2/3]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 692 of file core_armv8mml.h.

## ◆ SCB_SHCSR_MEMFAULTPENDED_Pos [3/3]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 702 of file core_armv81mml.h.

## ◆ SCB_SHCSR_MONITORACT_Msk [1/3]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 647 of file core_cm7.h.

## ◆ SCB_SHCSR_MONITORACT_Msk [2/3]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 705 of file core_armv8mml.h.

## ◆ SCB_SHCSR_MONITORACT_Msk [3/3]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 715 of file core_armv81mml.h.

## ◆ SCB_SHCSR_MONITORACT_Pos [1/3]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 646 of file core_cm7.h.

## ◆ SCB_SHCSR_MONITORACT_Pos [2/3]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 704 of file core_armv8mml.h.

## ◆ SCB_SHCSR_MONITORACT_Pos [3/3]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 714 of file core_armv81mml.h.

## ◆ SCB_SHCSR_NMIACT_Msk [1/3]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 538 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_NMIACT_Msk [2/3]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 711 of file core_armv8mml.h.

## ◆ SCB_SHCSR_NMIACT_Msk [3/3]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 721 of file core_armv81mml.h.

## ◆ SCB_SHCSR_NMIACT_Pos [1/3]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 537 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_NMIACT_Pos [2/3]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 710 of file core_armv8mml.h.

## ◆ SCB_SHCSR_NMIACT_Pos [3/3]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 720 of file core_armv81mml.h.

## ◆ SCB_SHCSR_PENDSVACT_Msk [1/4]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 532 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_PENDSVACT_Msk [2/4]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 644 of file core_cm7.h.

## ◆ SCB_SHCSR_PENDSVACT_Msk [3/4]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 702 of file core_armv8mml.h.

## ◆ SCB_SHCSR_PENDSVACT_Msk [4/4]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 712 of file core_armv81mml.h.

## ◆ SCB_SHCSR_PENDSVACT_Pos [1/4]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 531 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_PENDSVACT_Pos [2/4]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 643 of file core_cm7.h.

## ◆ SCB_SHCSR_PENDSVACT_Pos [3/4]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 701 of file core_armv8mml.h.

## ◆ SCB_SHCSR_PENDSVACT_Pos [4/4]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 711 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SECUREFAULTACT_Msk [1/2]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 714 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SECUREFAULTACT_Msk [2/2]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 724 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SECUREFAULTACT_Pos [1/2]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 713 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SECUREFAULTACT_Pos [2/2]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 723 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SECUREFAULTENA_Msk [1/2]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 675 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SECUREFAULTENA_Msk [2/2]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 685 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SECUREFAULTENA_Pos [1/2]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 674 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SECUREFAULTENA_Pos [2/2]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 684 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [1/2]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 672 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [2/2]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 682 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [1/2]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 671 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [2/2]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 681 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SVCALLACT_Msk [1/4]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 535 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_SVCALLACT_Msk [2/4]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 650 of file core_cm7.h.

## ◆ SCB_SHCSR_SVCALLACT_Msk [3/4]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 708 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SVCALLACT_Msk [4/4]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 718 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SVCALLACT_Pos [1/4]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 534 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_SVCALLACT_Pos [2/4]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 649 of file core_cm7.h.

## ◆ SCB_SHCSR_SVCALLACT_Pos [3/4]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 707 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SVCALLACT_Pos [4/4]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 717 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SVCALLPENDED_Msk [1/4]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 526 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_SVCALLPENDED_Msk [2/4]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 629 of file core_cm7.h.

## ◆ SCB_SHCSR_SVCALLPENDED_Msk [3/4]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 687 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SVCALLPENDED_Msk [4/4]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 697 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SVCALLPENDED_Pos [1/4]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 525 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_SVCALLPENDED_Pos [2/4]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 628 of file core_cm7.h.

## ◆ SCB_SHCSR_SVCALLPENDED_Pos [3/4]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 686 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SVCALLPENDED_Pos [4/4]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 696 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SYSTICKACT_Msk [1/4]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 529 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_SYSTICKACT_Msk [2/4]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 641 of file core_cm7.h.

## ◆ SCB_SHCSR_SYSTICKACT_Msk [3/4]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 699 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SYSTICKACT_Msk [4/4]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 709 of file core_armv81mml.h.

## ◆ SCB_SHCSR_SYSTICKACT_Pos [1/4]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 528 of file core_armv8mbl.h.

## ◆ SCB_SHCSR_SYSTICKACT_Pos [2/4]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 640 of file core_cm7.h.

## ◆ SCB_SHCSR_SYSTICKACT_Pos [3/4]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 698 of file core_armv8mml.h.

## ◆ SCB_SHCSR_SYSTICKACT_Pos [4/4]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 708 of file core_armv81mml.h.

## ◆ SCB_SHCSR_USGFAULTACT_Msk [1/3]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 653 of file core_cm7.h.

## ◆ SCB_SHCSR_USGFAULTACT_Msk [2/3]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 717 of file core_armv8mml.h.

## ◆ SCB_SHCSR_USGFAULTACT_Msk [3/3]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 727 of file core_armv81mml.h.

## ◆ SCB_SHCSR_USGFAULTACT_Pos [1/3]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 652 of file core_cm7.h.

## ◆ SCB_SHCSR_USGFAULTACT_Pos [2/3]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 716 of file core_armv8mml.h.

## ◆ SCB_SHCSR_USGFAULTACT_Pos [3/3]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 726 of file core_armv81mml.h.

## ◆ SCB_SHCSR_USGFAULTENA_Msk [1/3]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 620 of file core_cm7.h.

## ◆ SCB_SHCSR_USGFAULTENA_Msk [2/3]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 678 of file core_armv8mml.h.

## ◆ SCB_SHCSR_USGFAULTENA_Msk [3/3]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 688 of file core_armv81mml.h.

## ◆ SCB_SHCSR_USGFAULTENA_Pos [1/3]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 619 of file core_cm7.h.

## ◆ SCB_SHCSR_USGFAULTENA_Pos [2/3]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 677 of file core_armv8mml.h.

## ◆ SCB_SHCSR_USGFAULTENA_Pos [3/3]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 687 of file core_armv81mml.h.

## ◆ SCB_SHCSR_USGFAULTPENDED_Msk [1/3]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 638 of file core_cm7.h.

## ◆ SCB_SHCSR_USGFAULTPENDED_Msk [2/3]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 696 of file core_armv8mml.h.

## ◆ SCB_SHCSR_USGFAULTPENDED_Msk [3/3]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 706 of file core_armv81mml.h.

## ◆ SCB_SHCSR_USGFAULTPENDED_Pos [1/3]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 637 of file core_cm7.h.

## ◆ SCB_SHCSR_USGFAULTPENDED_Pos [2/3]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 695 of file core_armv8mml.h.

## ◆ SCB_SHCSR_USGFAULTPENDED_Pos [3/3]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 705 of file core_armv81mml.h.

## ◆ SCB_STIR_INTID_Msk [1/3]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 811 of file core_cm7.h.

## ◆ SCB_STIR_INTID_Msk [2/3]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 891 of file core_armv8mml.h.

## ◆ SCB_STIR_INTID_Msk [3/3]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 901 of file core_armv81mml.h.

## ◆ SCB_STIR_INTID_Pos [1/3]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

Definition at line 810 of file core_cm7.h.

## ◆ SCB_STIR_INTID_Pos [2/3]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

Definition at line 890 of file core_armv8mml.h.

## ◆ SCB_STIR_INTID_Pos [3/3]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

Definition at line 900 of file core_armv81mml.h.

## ◆ SCB_VTOR_TBLOFF_Msk [1/3]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 556 of file core_cm7.h.

## ◆ SCB_VTOR_TBLOFF_Msk [2/3]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 599 of file core_armv8mml.h.

## ◆ SCB_VTOR_TBLOFF_Msk [3/3]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 609 of file core_armv81mml.h.

## ◆ SCB_VTOR_TBLOFF_Pos [1/3]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 555 of file core_cm7.h.

## ◆ SCB_VTOR_TBLOFF_Pos [2/3]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 598 of file core_armv8mml.h.

## ◆ SCB_VTOR_TBLOFF_Pos [3/3]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 608 of file core_armv81mml.h.