Callisto4Bootloader: DMA Register Masks

Callisto4Bootloader

Macros
DMA Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » DMA Peripheral Access Layer

## Macros

#define | DMA_SADDR_COUNT (32U)
#define | DMA_SOFF_COUNT (32U)
#define | DMA_ATTR_COUNT (32U)
#define | DMA_NBYTES_MLNO_COUNT (32U)
#define | DMA_NBYTES_MLOFFNO_COUNT (32U)
#define | DMA_NBYTES_MLOFFYES_COUNT (32U)
#define | DMA_SLAST_COUNT (32U)
#define | DMA_DADDR_COUNT (32U)
#define | DMA_DOFF_COUNT (32U)
#define | DMA_CITER_ELINKNO_COUNT (32U)
#define | DMA_CITER_ELINKYES_COUNT (32U)
#define | DMA_DLAST_SGA_COUNT (32U)
#define | DMA_CSR_COUNT (32U)
#define | DMA_BITER_ELINKNO_COUNT (32U)
#define | DMA_BITER_ELINKYES_COUNT (32U)

## CR - Control Register

#define | DMA_CR_EDBG_MASK (0x2U)
#define | DMA_CR_EDBG_SHIFT (1U)
#define | DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
#define | DMA_CR_ERCA_MASK (0x4U)
#define | DMA_CR_ERCA_SHIFT (2U)
#define | DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
#define | DMA_CR_ERGA_MASK (0x8U)
#define | DMA_CR_ERGA_SHIFT (3U)
#define | DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
#define | DMA_CR_HOE_MASK (0x10U)
#define | DMA_CR_HOE_SHIFT (4U)
#define | DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
#define | DMA_CR_HALT_MASK (0x20U)
#define | DMA_CR_HALT_SHIFT (5U)
#define | DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
#define | DMA_CR_CLM_MASK (0x40U)
#define | DMA_CR_CLM_SHIFT (6U)
#define | DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
#define | DMA_CR_EMLM_MASK (0x80U)
#define | DMA_CR_EMLM_SHIFT (7U)
#define | DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
#define | DMA_CR_GRP0PRI_MASK (0x100U)
#define | DMA_CR_GRP0PRI_SHIFT (8U)
#define | DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
#define | DMA_CR_GRP1PRI_MASK (0x400U)
#define | DMA_CR_GRP1PRI_SHIFT (10U)
#define | DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
#define | DMA_CR_ECX_MASK (0x10000U)
#define | DMA_CR_ECX_SHIFT (16U)
#define | DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
#define | DMA_CR_CX_MASK (0x20000U)
#define | DMA_CR_CX_SHIFT (17U)
#define | DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
#define | DMA_CR_ACTIVE_MASK (0x80000000U)
#define | DMA_CR_ACTIVE_SHIFT (31U)
#define | DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
#define | LPSPI_CR_MEN_MASK (0x1U)
#define | LPSPI_CR_MEN_SHIFT (0U)
#define | LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
#define | LPSPI_CR_RST_MASK (0x2U)
#define | LPSPI_CR_RST_SHIFT (1U)
#define | LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
#define | LPSPI_CR_DOZEN_MASK (0x4U)
#define | LPSPI_CR_DOZEN_SHIFT (2U)
#define | LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
#define | LPSPI_CR_DBGEN_MASK (0x8U)
#define | LPSPI_CR_DBGEN_SHIFT (3U)
#define | LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
#define | LPSPI_CR_RTF_MASK (0x100U)
#define | LPSPI_CR_RTF_SHIFT (8U)
#define | LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
#define | LPSPI_CR_RRF_MASK (0x200U)
#define | LPSPI_CR_RRF_SHIFT (9U)
#define | LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

## ES - Error Status Register

#define | DMA_ES_DBE_MASK (0x1U)
#define | DMA_ES_DBE_SHIFT (0U)
#define | DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
#define | DMA_ES_SBE_MASK (0x2U)
#define | DMA_ES_SBE_SHIFT (1U)
#define | DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
#define | DMA_ES_SGE_MASK (0x4U)
#define | DMA_ES_SGE_SHIFT (2U)
#define | DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
#define | DMA_ES_NCE_MASK (0x8U)
#define | DMA_ES_NCE_SHIFT (3U)
#define | DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
#define | DMA_ES_DOE_MASK (0x10U)
#define | DMA_ES_DOE_SHIFT (4U)
#define | DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
#define | DMA_ES_DAE_MASK (0x20U)
#define | DMA_ES_DAE_SHIFT (5U)
#define | DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
#define | DMA_ES_SOE_MASK (0x40U)
#define | DMA_ES_SOE_SHIFT (6U)
#define | DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
#define | DMA_ES_SAE_MASK (0x80U)
#define | DMA_ES_SAE_SHIFT (7U)
#define | DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
#define | DMA_ES_ERRCHN_MASK (0x1F00U)
#define | DMA_ES_ERRCHN_SHIFT (8U)
#define | DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
#define | DMA_ES_CPE_MASK (0x4000U)
#define | DMA_ES_CPE_SHIFT (14U)
#define | DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
#define | DMA_ES_GPE_MASK (0x8000U)
#define | DMA_ES_GPE_SHIFT (15U)
#define | DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
#define | DMA_ES_ECX_MASK (0x10000U)
#define | DMA_ES_ECX_SHIFT (16U)
#define | DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
#define | DMA_ES_VLD_MASK (0x80000000U)
#define | DMA_ES_VLD_SHIFT (31U)
#define | DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

## ERQ - Enable Request Register

#define | DMA_ERQ_ERQ0_MASK (0x1U)
#define | DMA_ERQ_ERQ0_SHIFT (0U)
#define | DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
#define | DMA_ERQ_ERQ1_MASK (0x2U)
#define | DMA_ERQ_ERQ1_SHIFT (1U)
#define | DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
#define | DMA_ERQ_ERQ2_MASK (0x4U)
#define | DMA_ERQ_ERQ2_SHIFT (2U)
#define | DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
#define | DMA_ERQ_ERQ3_MASK (0x8U)
#define | DMA_ERQ_ERQ3_SHIFT (3U)
#define | DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
#define | DMA_ERQ_ERQ4_MASK (0x10U)
#define | DMA_ERQ_ERQ4_SHIFT (4U)
#define | DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
#define | DMA_ERQ_ERQ5_MASK (0x20U)
#define | DMA_ERQ_ERQ5_SHIFT (5U)
#define | DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
#define | DMA_ERQ_ERQ6_MASK (0x40U)
#define | DMA_ERQ_ERQ6_SHIFT (6U)
#define | DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
#define | DMA_ERQ_ERQ7_MASK (0x80U)
#define | DMA_ERQ_ERQ7_SHIFT (7U)
#define | DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
#define | DMA_ERQ_ERQ8_MASK (0x100U)
#define | DMA_ERQ_ERQ8_SHIFT (8U)
#define | DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
#define | DMA_ERQ_ERQ9_MASK (0x200U)
#define | DMA_ERQ_ERQ9_SHIFT (9U)
#define | DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
#define | DMA_ERQ_ERQ10_MASK (0x400U)
#define | DMA_ERQ_ERQ10_SHIFT (10U)
#define | DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
#define | DMA_ERQ_ERQ11_MASK (0x800U)
#define | DMA_ERQ_ERQ11_SHIFT (11U)
#define | DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
#define | DMA_ERQ_ERQ12_MASK (0x1000U)
#define | DMA_ERQ_ERQ12_SHIFT (12U)
#define | DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
#define | DMA_ERQ_ERQ13_MASK (0x2000U)
#define | DMA_ERQ_ERQ13_SHIFT (13U)
#define | DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
#define | DMA_ERQ_ERQ14_MASK (0x4000U)
#define | DMA_ERQ_ERQ14_SHIFT (14U)
#define | DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
#define | DMA_ERQ_ERQ15_MASK (0x8000U)
#define | DMA_ERQ_ERQ15_SHIFT (15U)
#define | DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
#define | DMA_ERQ_ERQ16_MASK (0x10000U)
#define | DMA_ERQ_ERQ16_SHIFT (16U)
#define | DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
#define | DMA_ERQ_ERQ17_MASK (0x20000U)
#define | DMA_ERQ_ERQ17_SHIFT (17U)
#define | DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
#define | DMA_ERQ_ERQ18_MASK (0x40000U)
#define | DMA_ERQ_ERQ18_SHIFT (18U)
#define | DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
#define | DMA_ERQ_ERQ19_MASK (0x80000U)
#define | DMA_ERQ_ERQ19_SHIFT (19U)
#define | DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
#define | DMA_ERQ_ERQ20_MASK (0x100000U)
#define | DMA_ERQ_ERQ20_SHIFT (20U)
#define | DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
#define | DMA_ERQ_ERQ21_MASK (0x200000U)
#define | DMA_ERQ_ERQ21_SHIFT (21U)
#define | DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
#define | DMA_ERQ_ERQ22_MASK (0x400000U)
#define | DMA_ERQ_ERQ22_SHIFT (22U)
#define | DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
#define | DMA_ERQ_ERQ23_MASK (0x800000U)
#define | DMA_ERQ_ERQ23_SHIFT (23U)
#define | DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
#define | DMA_ERQ_ERQ24_MASK (0x1000000U)
#define | DMA_ERQ_ERQ24_SHIFT (24U)
#define | DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
#define | DMA_ERQ_ERQ25_MASK (0x2000000U)
#define | DMA_ERQ_ERQ25_SHIFT (25U)
#define | DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
#define | DMA_ERQ_ERQ26_MASK (0x4000000U)
#define | DMA_ERQ_ERQ26_SHIFT (26U)
#define | DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
#define | DMA_ERQ_ERQ27_MASK (0x8000000U)
#define | DMA_ERQ_ERQ27_SHIFT (27U)
#define | DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
#define | DMA_ERQ_ERQ28_MASK (0x10000000U)
#define | DMA_ERQ_ERQ28_SHIFT (28U)
#define | DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
#define | DMA_ERQ_ERQ29_MASK (0x20000000U)
#define | DMA_ERQ_ERQ29_SHIFT (29U)
#define | DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
#define | DMA_ERQ_ERQ30_MASK (0x40000000U)
#define | DMA_ERQ_ERQ30_SHIFT (30U)
#define | DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
#define | DMA_ERQ_ERQ31_MASK (0x80000000U)
#define | DMA_ERQ_ERQ31_SHIFT (31U)
#define | DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

## EEI - Enable Error Interrupt Register

#define | DMA_EEI_EEI0_MASK (0x1U)
#define | DMA_EEI_EEI0_SHIFT (0U)
#define | DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
#define | DMA_EEI_EEI1_MASK (0x2U)
#define | DMA_EEI_EEI1_SHIFT (1U)
#define | DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
#define | DMA_EEI_EEI2_MASK (0x4U)
#define | DMA_EEI_EEI2_SHIFT (2U)
#define | DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
#define | DMA_EEI_EEI3_MASK (0x8U)
#define | DMA_EEI_EEI3_SHIFT (3U)
#define | DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
#define | DMA_EEI_EEI4_MASK (0x10U)
#define | DMA_EEI_EEI4_SHIFT (4U)
#define | DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
#define | DMA_EEI_EEI5_MASK (0x20U)
#define | DMA_EEI_EEI5_SHIFT (5U)
#define | DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
#define | DMA_EEI_EEI6_MASK (0x40U)
#define | DMA_EEI_EEI6_SHIFT (6U)
#define | DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
#define | DMA_EEI_EEI7_MASK (0x80U)
#define | DMA_EEI_EEI7_SHIFT (7U)
#define | DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
#define | DMA_EEI_EEI8_MASK (0x100U)
#define | DMA_EEI_EEI8_SHIFT (8U)
#define | DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
#define | DMA_EEI_EEI9_MASK (0x200U)
#define | DMA_EEI_EEI9_SHIFT (9U)
#define | DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
#define | DMA_EEI_EEI10_MASK (0x400U)
#define | DMA_EEI_EEI10_SHIFT (10U)
#define | DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
#define | DMA_EEI_EEI11_MASK (0x800U)
#define | DMA_EEI_EEI11_SHIFT (11U)
#define | DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
#define | DMA_EEI_EEI12_MASK (0x1000U)
#define | DMA_EEI_EEI12_SHIFT (12U)
#define | DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
#define | DMA_EEI_EEI13_MASK (0x2000U)
#define | DMA_EEI_EEI13_SHIFT (13U)
#define | DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
#define | DMA_EEI_EEI14_MASK (0x4000U)
#define | DMA_EEI_EEI14_SHIFT (14U)
#define | DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
#define | DMA_EEI_EEI15_MASK (0x8000U)
#define | DMA_EEI_EEI15_SHIFT (15U)
#define | DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
#define | DMA_EEI_EEI16_MASK (0x10000U)
#define | DMA_EEI_EEI16_SHIFT (16U)
#define | DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
#define | DMA_EEI_EEI17_MASK (0x20000U)
#define | DMA_EEI_EEI17_SHIFT (17U)
#define | DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
#define | DMA_EEI_EEI18_MASK (0x40000U)
#define | DMA_EEI_EEI18_SHIFT (18U)
#define | DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
#define | DMA_EEI_EEI19_MASK (0x80000U)
#define | DMA_EEI_EEI19_SHIFT (19U)
#define | DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
#define | DMA_EEI_EEI20_MASK (0x100000U)
#define | DMA_EEI_EEI20_SHIFT (20U)
#define | DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
#define | DMA_EEI_EEI21_MASK (0x200000U)
#define | DMA_EEI_EEI21_SHIFT (21U)
#define | DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
#define | DMA_EEI_EEI22_MASK (0x400000U)
#define | DMA_EEI_EEI22_SHIFT (22U)
#define | DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
#define | DMA_EEI_EEI23_MASK (0x800000U)
#define | DMA_EEI_EEI23_SHIFT (23U)
#define | DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
#define | DMA_EEI_EEI24_MASK (0x1000000U)
#define | DMA_EEI_EEI24_SHIFT (24U)
#define | DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
#define | DMA_EEI_EEI25_MASK (0x2000000U)
#define | DMA_EEI_EEI25_SHIFT (25U)
#define | DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
#define | DMA_EEI_EEI26_MASK (0x4000000U)
#define | DMA_EEI_EEI26_SHIFT (26U)
#define | DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
#define | DMA_EEI_EEI27_MASK (0x8000000U)
#define | DMA_EEI_EEI27_SHIFT (27U)
#define | DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
#define | DMA_EEI_EEI28_MASK (0x10000000U)
#define | DMA_EEI_EEI28_SHIFT (28U)
#define | DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
#define | DMA_EEI_EEI29_MASK (0x20000000U)
#define | DMA_EEI_EEI29_SHIFT (29U)
#define | DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
#define | DMA_EEI_EEI30_MASK (0x40000000U)
#define | DMA_EEI_EEI30_SHIFT (30U)
#define | DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
#define | DMA_EEI_EEI31_MASK (0x80000000U)
#define | DMA_EEI_EEI31_SHIFT (31U)
#define | DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

## CEEI - Clear Enable Error Interrupt Register

#define | DMA_CEEI_CEEI_MASK (0x1FU)
#define | DMA_CEEI_CEEI_SHIFT (0U)
#define | DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
#define | DMA_CEEI_CAEE_MASK (0x40U)
#define | DMA_CEEI_CAEE_SHIFT (6U)
#define | DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
#define | DMA_CEEI_NOP_MASK (0x80U)
#define | DMA_CEEI_NOP_SHIFT (7U)
#define | DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

## SEEI - Set Enable Error Interrupt Register

#define | DMA_SEEI_SEEI_MASK (0x1FU)
#define | DMA_SEEI_SEEI_SHIFT (0U)
#define | DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
#define | DMA_SEEI_SAEE_MASK (0x40U)
#define | DMA_SEEI_SAEE_SHIFT (6U)
#define | DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
#define | DMA_SEEI_NOP_MASK (0x80U)
#define | DMA_SEEI_NOP_SHIFT (7U)
#define | DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

## CERQ - Clear Enable Request Register

#define | DMA_CERQ_CERQ_MASK (0x1FU)
#define | DMA_CERQ_CERQ_SHIFT (0U)
#define | DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
#define | DMA_CERQ_CAER_MASK (0x40U)
#define | DMA_CERQ_CAER_SHIFT (6U)
#define | DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
#define | DMA_CERQ_NOP_MASK (0x80U)
#define | DMA_CERQ_NOP_SHIFT (7U)
#define | DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

## SERQ - Set Enable Request Register

#define | DMA_SERQ_SERQ_MASK (0x1FU)
#define | DMA_SERQ_SERQ_SHIFT (0U)
#define | DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
#define | DMA_SERQ_SAER_MASK (0x40U)
#define | DMA_SERQ_SAER_SHIFT (6U)
#define | DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
#define | DMA_SERQ_NOP_MASK (0x80U)
#define | DMA_SERQ_NOP_SHIFT (7U)
#define | DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

## CDNE - Clear DONE Status Bit Register

#define | DMA_CDNE_CDNE_MASK (0x1FU)
#define | DMA_CDNE_CDNE_SHIFT (0U)
#define | DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
#define | DMA_CDNE_CADN_MASK (0x40U)
#define | DMA_CDNE_CADN_SHIFT (6U)
#define | DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
#define | DMA_CDNE_NOP_MASK (0x80U)
#define | DMA_CDNE_NOP_SHIFT (7U)
#define | DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

## SSRT - Set START Bit Register

#define | DMA_SSRT_SSRT_MASK (0x1FU)
#define | DMA_SSRT_SSRT_SHIFT (0U)
#define | DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
#define | DMA_SSRT_SAST_MASK (0x40U)
#define | DMA_SSRT_SAST_SHIFT (6U)
#define | DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
#define | DMA_SSRT_NOP_MASK (0x80U)
#define | DMA_SSRT_NOP_SHIFT (7U)
#define | DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

## CERR - Clear Error Register

#define | DMA_CERR_CERR_MASK (0x1FU)
#define | DMA_CERR_CERR_SHIFT (0U)
#define | DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
#define | DMA_CERR_CAEI_MASK (0x40U)
#define | DMA_CERR_CAEI_SHIFT (6U)
#define | DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
#define | DMA_CERR_NOP_MASK (0x80U)
#define | DMA_CERR_NOP_SHIFT (7U)
#define | DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

## CINT - Clear Interrupt Request Register

#define | DMA_CINT_CINT_MASK (0x1FU)
#define | DMA_CINT_CINT_SHIFT (0U)
#define | DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
#define | DMA_CINT_CAIR_MASK (0x40U)
#define | DMA_CINT_CAIR_SHIFT (6U)
#define | DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
#define | DMA_CINT_NOP_MASK (0x80U)
#define | DMA_CINT_NOP_SHIFT (7U)
#define | DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

## INT - Interrupt Request Register

#define | DMA_INT_INT0_MASK (0x1U)
#define | DMA_INT_INT0_SHIFT (0U)
#define | DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
#define | DMA_INT_INT1_MASK (0x2U)
#define | DMA_INT_INT1_SHIFT (1U)
#define | DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
#define | DMA_INT_INT2_MASK (0x4U)
#define | DMA_INT_INT2_SHIFT (2U)
#define | DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
#define | DMA_INT_INT3_MASK (0x8U)
#define | DMA_INT_INT3_SHIFT (3U)
#define | DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
#define | DMA_INT_INT4_MASK (0x10U)
#define | DMA_INT_INT4_SHIFT (4U)
#define | DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
#define | DMA_INT_INT5_MASK (0x20U)
#define | DMA_INT_INT5_SHIFT (5U)
#define | DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
#define | DMA_INT_INT6_MASK (0x40U)
#define | DMA_INT_INT6_SHIFT (6U)
#define | DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
#define | DMA_INT_INT7_MASK (0x80U)
#define | DMA_INT_INT7_SHIFT (7U)
#define | DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
#define | DMA_INT_INT8_MASK (0x100U)
#define | DMA_INT_INT8_SHIFT (8U)
#define | DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
#define | DMA_INT_INT9_MASK (0x200U)
#define | DMA_INT_INT9_SHIFT (9U)
#define | DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
#define | DMA_INT_INT10_MASK (0x400U)
#define | DMA_INT_INT10_SHIFT (10U)
#define | DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
#define | DMA_INT_INT11_MASK (0x800U)
#define | DMA_INT_INT11_SHIFT (11U)
#define | DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
#define | DMA_INT_INT12_MASK (0x1000U)
#define | DMA_INT_INT12_SHIFT (12U)
#define | DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
#define | DMA_INT_INT13_MASK (0x2000U)
#define | DMA_INT_INT13_SHIFT (13U)
#define | DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
#define | DMA_INT_INT14_MASK (0x4000U)
#define | DMA_INT_INT14_SHIFT (14U)
#define | DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
#define | DMA_INT_INT15_MASK (0x8000U)
#define | DMA_INT_INT15_SHIFT (15U)
#define | DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
#define | DMA_INT_INT16_MASK (0x10000U)
#define | DMA_INT_INT16_SHIFT (16U)
#define | DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
#define | DMA_INT_INT17_MASK (0x20000U)
#define | DMA_INT_INT17_SHIFT (17U)
#define | DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
#define | DMA_INT_INT18_MASK (0x40000U)
#define | DMA_INT_INT18_SHIFT (18U)
#define | DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
#define | DMA_INT_INT19_MASK (0x80000U)
#define | DMA_INT_INT19_SHIFT (19U)
#define | DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
#define | DMA_INT_INT20_MASK (0x100000U)
#define | DMA_INT_INT20_SHIFT (20U)
#define | DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
#define | DMA_INT_INT21_MASK (0x200000U)
#define | DMA_INT_INT21_SHIFT (21U)
#define | DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
#define | DMA_INT_INT22_MASK (0x400000U)
#define | DMA_INT_INT22_SHIFT (22U)
#define | DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
#define | DMA_INT_INT23_MASK (0x800000U)
#define | DMA_INT_INT23_SHIFT (23U)
#define | DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
#define | DMA_INT_INT24_MASK (0x1000000U)
#define | DMA_INT_INT24_SHIFT (24U)
#define | DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
#define | DMA_INT_INT25_MASK (0x2000000U)
#define | DMA_INT_INT25_SHIFT (25U)
#define | DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
#define | DMA_INT_INT26_MASK (0x4000000U)
#define | DMA_INT_INT26_SHIFT (26U)
#define | DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
#define | DMA_INT_INT27_MASK (0x8000000U)
#define | DMA_INT_INT27_SHIFT (27U)
#define | DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
#define | DMA_INT_INT28_MASK (0x10000000U)
#define | DMA_INT_INT28_SHIFT (28U)
#define | DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
#define | DMA_INT_INT29_MASK (0x20000000U)
#define | DMA_INT_INT29_SHIFT (29U)
#define | DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
#define | DMA_INT_INT30_MASK (0x40000000U)
#define | DMA_INT_INT30_SHIFT (30U)
#define | DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
#define | DMA_INT_INT31_MASK (0x80000000U)
#define | DMA_INT_INT31_SHIFT (31U)
#define | DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

## ERR - Error Register

#define | DMA_ERR_ERR0_MASK (0x1U)
#define | DMA_ERR_ERR0_SHIFT (0U)
#define | DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
#define | DMA_ERR_ERR1_MASK (0x2U)
#define | DMA_ERR_ERR1_SHIFT (1U)
#define | DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
#define | DMA_ERR_ERR2_MASK (0x4U)
#define | DMA_ERR_ERR2_SHIFT (2U)
#define | DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
#define | DMA_ERR_ERR3_MASK (0x8U)
#define | DMA_ERR_ERR3_SHIFT (3U)
#define | DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
#define | DMA_ERR_ERR4_MASK (0x10U)
#define | DMA_ERR_ERR4_SHIFT (4U)
#define | DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
#define | DMA_ERR_ERR5_MASK (0x20U)
#define | DMA_ERR_ERR5_SHIFT (5U)
#define | DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
#define | DMA_ERR_ERR6_MASK (0x40U)
#define | DMA_ERR_ERR6_SHIFT (6U)
#define | DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
#define | DMA_ERR_ERR7_MASK (0x80U)
#define | DMA_ERR_ERR7_SHIFT (7U)
#define | DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
#define | DMA_ERR_ERR8_MASK (0x100U)
#define | DMA_ERR_ERR8_SHIFT (8U)
#define | DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
#define | DMA_ERR_ERR9_MASK (0x200U)
#define | DMA_ERR_ERR9_SHIFT (9U)
#define | DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
#define | DMA_ERR_ERR10_MASK (0x400U)
#define | DMA_ERR_ERR10_SHIFT (10U)
#define | DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
#define | DMA_ERR_ERR11_MASK (0x800U)
#define | DMA_ERR_ERR11_SHIFT (11U)
#define | DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
#define | DMA_ERR_ERR12_MASK (0x1000U)
#define | DMA_ERR_ERR12_SHIFT (12U)
#define | DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
#define | DMA_ERR_ERR13_MASK (0x2000U)
#define | DMA_ERR_ERR13_SHIFT (13U)
#define | DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
#define | DMA_ERR_ERR14_MASK (0x4000U)
#define | DMA_ERR_ERR14_SHIFT (14U)
#define | DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
#define | DMA_ERR_ERR15_MASK (0x8000U)
#define | DMA_ERR_ERR15_SHIFT (15U)
#define | DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
#define | DMA_ERR_ERR16_MASK (0x10000U)
#define | DMA_ERR_ERR16_SHIFT (16U)
#define | DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
#define | DMA_ERR_ERR17_MASK (0x20000U)
#define | DMA_ERR_ERR17_SHIFT (17U)
#define | DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
#define | DMA_ERR_ERR18_MASK (0x40000U)
#define | DMA_ERR_ERR18_SHIFT (18U)
#define | DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
#define | DMA_ERR_ERR19_MASK (0x80000U)
#define | DMA_ERR_ERR19_SHIFT (19U)
#define | DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
#define | DMA_ERR_ERR20_MASK (0x100000U)
#define | DMA_ERR_ERR20_SHIFT (20U)
#define | DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
#define | DMA_ERR_ERR21_MASK (0x200000U)
#define | DMA_ERR_ERR21_SHIFT (21U)
#define | DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
#define | DMA_ERR_ERR22_MASK (0x400000U)
#define | DMA_ERR_ERR22_SHIFT (22U)
#define | DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
#define | DMA_ERR_ERR23_MASK (0x800000U)
#define | DMA_ERR_ERR23_SHIFT (23U)
#define | DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
#define | DMA_ERR_ERR24_MASK (0x1000000U)
#define | DMA_ERR_ERR24_SHIFT (24U)
#define | DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
#define | DMA_ERR_ERR25_MASK (0x2000000U)
#define | DMA_ERR_ERR25_SHIFT (25U)
#define | DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
#define | DMA_ERR_ERR26_MASK (0x4000000U)
#define | DMA_ERR_ERR26_SHIFT (26U)
#define | DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
#define | DMA_ERR_ERR27_MASK (0x8000000U)
#define | DMA_ERR_ERR27_SHIFT (27U)
#define | DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
#define | DMA_ERR_ERR28_MASK (0x10000000U)
#define | DMA_ERR_ERR28_SHIFT (28U)
#define | DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
#define | DMA_ERR_ERR29_MASK (0x20000000U)
#define | DMA_ERR_ERR29_SHIFT (29U)
#define | DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
#define | DMA_ERR_ERR30_MASK (0x40000000U)
#define | DMA_ERR_ERR30_SHIFT (30U)
#define | DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
#define | DMA_ERR_ERR31_MASK (0x80000000U)
#define | DMA_ERR_ERR31_SHIFT (31U)
#define | DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

## HRS - Hardware Request Status Register

#define | DMA_HRS_HRS0_MASK (0x1U)
#define | DMA_HRS_HRS0_SHIFT (0U)
#define | DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
#define | DMA_HRS_HRS1_MASK (0x2U)
#define | DMA_HRS_HRS1_SHIFT (1U)
#define | DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
#define | DMA_HRS_HRS2_MASK (0x4U)
#define | DMA_HRS_HRS2_SHIFT (2U)
#define | DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
#define | DMA_HRS_HRS3_MASK (0x8U)
#define | DMA_HRS_HRS3_SHIFT (3U)
#define | DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
#define | DMA_HRS_HRS4_MASK (0x10U)
#define | DMA_HRS_HRS4_SHIFT (4U)
#define | DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
#define | DMA_HRS_HRS5_MASK (0x20U)
#define | DMA_HRS_HRS5_SHIFT (5U)
#define | DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
#define | DMA_HRS_HRS6_MASK (0x40U)
#define | DMA_HRS_HRS6_SHIFT (6U)
#define | DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
#define | DMA_HRS_HRS7_MASK (0x80U)
#define | DMA_HRS_HRS7_SHIFT (7U)
#define | DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
#define | DMA_HRS_HRS8_MASK (0x100U)
#define | DMA_HRS_HRS8_SHIFT (8U)
#define | DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
#define | DMA_HRS_HRS9_MASK (0x200U)
#define | DMA_HRS_HRS9_SHIFT (9U)
#define | DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
#define | DMA_HRS_HRS10_MASK (0x400U)
#define | DMA_HRS_HRS10_SHIFT (10U)
#define | DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
#define | DMA_HRS_HRS11_MASK (0x800U)
#define | DMA_HRS_HRS11_SHIFT (11U)
#define | DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
#define | DMA_HRS_HRS12_MASK (0x1000U)
#define | DMA_HRS_HRS12_SHIFT (12U)
#define | DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
#define | DMA_HRS_HRS13_MASK (0x2000U)
#define | DMA_HRS_HRS13_SHIFT (13U)
#define | DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
#define | DMA_HRS_HRS14_MASK (0x4000U)
#define | DMA_HRS_HRS14_SHIFT (14U)
#define | DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
#define | DMA_HRS_HRS15_MASK (0x8000U)
#define | DMA_HRS_HRS15_SHIFT (15U)
#define | DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
#define | DMA_HRS_HRS16_MASK (0x10000U)
#define | DMA_HRS_HRS16_SHIFT (16U)
#define | DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
#define | DMA_HRS_HRS17_MASK (0x20000U)
#define | DMA_HRS_HRS17_SHIFT (17U)
#define | DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
#define | DMA_HRS_HRS18_MASK (0x40000U)
#define | DMA_HRS_HRS18_SHIFT (18U)
#define | DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
#define | DMA_HRS_HRS19_MASK (0x80000U)
#define | DMA_HRS_HRS19_SHIFT (19U)
#define | DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
#define | DMA_HRS_HRS20_MASK (0x100000U)
#define | DMA_HRS_HRS20_SHIFT (20U)
#define | DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
#define | DMA_HRS_HRS21_MASK (0x200000U)
#define | DMA_HRS_HRS21_SHIFT (21U)
#define | DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
#define | DMA_HRS_HRS22_MASK (0x400000U)
#define | DMA_HRS_HRS22_SHIFT (22U)
#define | DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
#define | DMA_HRS_HRS23_MASK (0x800000U)
#define | DMA_HRS_HRS23_SHIFT (23U)
#define | DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
#define | DMA_HRS_HRS24_MASK (0x1000000U)
#define | DMA_HRS_HRS24_SHIFT (24U)
#define | DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
#define | DMA_HRS_HRS25_MASK (0x2000000U)
#define | DMA_HRS_HRS25_SHIFT (25U)
#define | DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
#define | DMA_HRS_HRS26_MASK (0x4000000U)
#define | DMA_HRS_HRS26_SHIFT (26U)
#define | DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
#define | DMA_HRS_HRS27_MASK (0x8000000U)
#define | DMA_HRS_HRS27_SHIFT (27U)
#define | DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
#define | DMA_HRS_HRS28_MASK (0x10000000U)
#define | DMA_HRS_HRS28_SHIFT (28U)
#define | DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
#define | DMA_HRS_HRS29_MASK (0x20000000U)
#define | DMA_HRS_HRS29_SHIFT (29U)
#define | DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
#define | DMA_HRS_HRS30_MASK (0x40000000U)
#define | DMA_HRS_HRS30_SHIFT (30U)
#define | DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
#define | DMA_HRS_HRS31_MASK (0x80000000U)
#define | DMA_HRS_HRS31_SHIFT (31U)
#define | DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

## EARS - Enable Asynchronous Request in Stop Register

#define | DMA_EARS_EDREQ_0_MASK (0x1U)
#define | DMA_EARS_EDREQ_0_SHIFT (0U)
#define | DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
#define | DMA_EARS_EDREQ_1_MASK (0x2U)
#define | DMA_EARS_EDREQ_1_SHIFT (1U)
#define | DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
#define | DMA_EARS_EDREQ_2_MASK (0x4U)
#define | DMA_EARS_EDREQ_2_SHIFT (2U)
#define | DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
#define | DMA_EARS_EDREQ_3_MASK (0x8U)
#define | DMA_EARS_EDREQ_3_SHIFT (3U)
#define | DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
#define | DMA_EARS_EDREQ_4_MASK (0x10U)
#define | DMA_EARS_EDREQ_4_SHIFT (4U)
#define | DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
#define | DMA_EARS_EDREQ_5_MASK (0x20U)
#define | DMA_EARS_EDREQ_5_SHIFT (5U)
#define | DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
#define | DMA_EARS_EDREQ_6_MASK (0x40U)
#define | DMA_EARS_EDREQ_6_SHIFT (6U)
#define | DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
#define | DMA_EARS_EDREQ_7_MASK (0x80U)
#define | DMA_EARS_EDREQ_7_SHIFT (7U)
#define | DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
#define | DMA_EARS_EDREQ_8_MASK (0x100U)
#define | DMA_EARS_EDREQ_8_SHIFT (8U)
#define | DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
#define | DMA_EARS_EDREQ_9_MASK (0x200U)
#define | DMA_EARS_EDREQ_9_SHIFT (9U)
#define | DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
#define | DMA_EARS_EDREQ_10_MASK (0x400U)
#define | DMA_EARS_EDREQ_10_SHIFT (10U)
#define | DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
#define | DMA_EARS_EDREQ_11_MASK (0x800U)
#define | DMA_EARS_EDREQ_11_SHIFT (11U)
#define | DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
#define | DMA_EARS_EDREQ_12_MASK (0x1000U)
#define | DMA_EARS_EDREQ_12_SHIFT (12U)
#define | DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
#define | DMA_EARS_EDREQ_13_MASK (0x2000U)
#define | DMA_EARS_EDREQ_13_SHIFT (13U)
#define | DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
#define | DMA_EARS_EDREQ_14_MASK (0x4000U)
#define | DMA_EARS_EDREQ_14_SHIFT (14U)
#define | DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
#define | DMA_EARS_EDREQ_15_MASK (0x8000U)
#define | DMA_EARS_EDREQ_15_SHIFT (15U)
#define | DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
#define | DMA_EARS_EDREQ_16_MASK (0x10000U)
#define | DMA_EARS_EDREQ_16_SHIFT (16U)
#define | DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
#define | DMA_EARS_EDREQ_17_MASK (0x20000U)
#define | DMA_EARS_EDREQ_17_SHIFT (17U)
#define | DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
#define | DMA_EARS_EDREQ_18_MASK (0x40000U)
#define | DMA_EARS_EDREQ_18_SHIFT (18U)
#define | DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
#define | DMA_EARS_EDREQ_19_MASK (0x80000U)
#define | DMA_EARS_EDREQ_19_SHIFT (19U)
#define | DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
#define | DMA_EARS_EDREQ_20_MASK (0x100000U)
#define | DMA_EARS_EDREQ_20_SHIFT (20U)
#define | DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
#define | DMA_EARS_EDREQ_21_MASK (0x200000U)
#define | DMA_EARS_EDREQ_21_SHIFT (21U)
#define | DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
#define | DMA_EARS_EDREQ_22_MASK (0x400000U)
#define | DMA_EARS_EDREQ_22_SHIFT (22U)
#define | DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
#define | DMA_EARS_EDREQ_23_MASK (0x800000U)
#define | DMA_EARS_EDREQ_23_SHIFT (23U)
#define | DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
#define | DMA_EARS_EDREQ_24_MASK (0x1000000U)
#define | DMA_EARS_EDREQ_24_SHIFT (24U)
#define | DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
#define | DMA_EARS_EDREQ_25_MASK (0x2000000U)
#define | DMA_EARS_EDREQ_25_SHIFT (25U)
#define | DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
#define | DMA_EARS_EDREQ_26_MASK (0x4000000U)
#define | DMA_EARS_EDREQ_26_SHIFT (26U)
#define | DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
#define | DMA_EARS_EDREQ_27_MASK (0x8000000U)
#define | DMA_EARS_EDREQ_27_SHIFT (27U)
#define | DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
#define | DMA_EARS_EDREQ_28_MASK (0x10000000U)
#define | DMA_EARS_EDREQ_28_SHIFT (28U)
#define | DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
#define | DMA_EARS_EDREQ_29_MASK (0x20000000U)
#define | DMA_EARS_EDREQ_29_SHIFT (29U)
#define | DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
#define | DMA_EARS_EDREQ_30_MASK (0x40000000U)
#define | DMA_EARS_EDREQ_30_SHIFT (30U)
#define | DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
#define | DMA_EARS_EDREQ_31_MASK (0x80000000U)
#define | DMA_EARS_EDREQ_31_SHIFT (31U)
#define | DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

## DCHPRI3 - Channel n Priority Register

#define | DMA_DCHPRI3_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI3_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
#define | DMA_DCHPRI3_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI3_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
#define | DMA_DCHPRI3_DPA_MASK (0x40U)
#define | DMA_DCHPRI3_DPA_SHIFT (6U)
#define | DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
#define | DMA_DCHPRI3_ECP_MASK (0x80U)
#define | DMA_DCHPRI3_ECP_SHIFT (7U)
#define | DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

## DCHPRI2 - Channel n Priority Register

#define | DMA_DCHPRI2_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI2_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
#define | DMA_DCHPRI2_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI2_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
#define | DMA_DCHPRI2_DPA_MASK (0x40U)
#define | DMA_DCHPRI2_DPA_SHIFT (6U)
#define | DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
#define | DMA_DCHPRI2_ECP_MASK (0x80U)
#define | DMA_DCHPRI2_ECP_SHIFT (7U)
#define | DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

## DCHPRI1 - Channel n Priority Register

#define | DMA_DCHPRI1_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI1_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
#define | DMA_DCHPRI1_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI1_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
#define | DMA_DCHPRI1_DPA_MASK (0x40U)
#define | DMA_DCHPRI1_DPA_SHIFT (6U)
#define | DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
#define | DMA_DCHPRI1_ECP_MASK (0x80U)
#define | DMA_DCHPRI1_ECP_SHIFT (7U)
#define | DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

## DCHPRI0 - Channel n Priority Register

#define | DMA_DCHPRI0_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI0_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
#define | DMA_DCHPRI0_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI0_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
#define | DMA_DCHPRI0_DPA_MASK (0x40U)
#define | DMA_DCHPRI0_DPA_SHIFT (6U)
#define | DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
#define | DMA_DCHPRI0_ECP_MASK (0x80U)
#define | DMA_DCHPRI0_ECP_SHIFT (7U)
#define | DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

## DCHPRI7 - Channel n Priority Register

#define | DMA_DCHPRI7_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI7_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
#define | DMA_DCHPRI7_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI7_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
#define | DMA_DCHPRI7_DPA_MASK (0x40U)
#define | DMA_DCHPRI7_DPA_SHIFT (6U)
#define | DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
#define | DMA_DCHPRI7_ECP_MASK (0x80U)
#define | DMA_DCHPRI7_ECP_SHIFT (7U)
#define | DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

## DCHPRI6 - Channel n Priority Register

#define | DMA_DCHPRI6_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI6_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
#define | DMA_DCHPRI6_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI6_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
#define | DMA_DCHPRI6_DPA_MASK (0x40U)
#define | DMA_DCHPRI6_DPA_SHIFT (6U)
#define | DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
#define | DMA_DCHPRI6_ECP_MASK (0x80U)
#define | DMA_DCHPRI6_ECP_SHIFT (7U)
#define | DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

## DCHPRI5 - Channel n Priority Register

#define | DMA_DCHPRI5_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI5_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
#define | DMA_DCHPRI5_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI5_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
#define | DMA_DCHPRI5_DPA_MASK (0x40U)
#define | DMA_DCHPRI5_DPA_SHIFT (6U)
#define | DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
#define | DMA_DCHPRI5_ECP_MASK (0x80U)
#define | DMA_DCHPRI5_ECP_SHIFT (7U)
#define | DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

## DCHPRI4 - Channel n Priority Register

#define | DMA_DCHPRI4_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI4_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
#define | DMA_DCHPRI4_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI4_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
#define | DMA_DCHPRI4_DPA_MASK (0x40U)
#define | DMA_DCHPRI4_DPA_SHIFT (6U)
#define | DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
#define | DMA_DCHPRI4_ECP_MASK (0x80U)
#define | DMA_DCHPRI4_ECP_SHIFT (7U)
#define | DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

## DCHPRI11 - Channel n Priority Register

#define | DMA_DCHPRI11_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI11_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
#define | DMA_DCHPRI11_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI11_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
#define | DMA_DCHPRI11_DPA_MASK (0x40U)
#define | DMA_DCHPRI11_DPA_SHIFT (6U)
#define | DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
#define | DMA_DCHPRI11_ECP_MASK (0x80U)
#define | DMA_DCHPRI11_ECP_SHIFT (7U)
#define | DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

## DCHPRI10 - Channel n Priority Register

#define | DMA_DCHPRI10_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI10_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
#define | DMA_DCHPRI10_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI10_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
#define | DMA_DCHPRI10_DPA_MASK (0x40U)
#define | DMA_DCHPRI10_DPA_SHIFT (6U)
#define | DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
#define | DMA_DCHPRI10_ECP_MASK (0x80U)
#define | DMA_DCHPRI10_ECP_SHIFT (7U)
#define | DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

## DCHPRI9 - Channel n Priority Register

#define | DMA_DCHPRI9_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI9_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
#define | DMA_DCHPRI9_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI9_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
#define | DMA_DCHPRI9_DPA_MASK (0x40U)
#define | DMA_DCHPRI9_DPA_SHIFT (6U)
#define | DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
#define | DMA_DCHPRI9_ECP_MASK (0x80U)
#define | DMA_DCHPRI9_ECP_SHIFT (7U)
#define | DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

## DCHPRI8 - Channel n Priority Register

#define | DMA_DCHPRI8_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI8_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
#define | DMA_DCHPRI8_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI8_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
#define | DMA_DCHPRI8_DPA_MASK (0x40U)
#define | DMA_DCHPRI8_DPA_SHIFT (6U)
#define | DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
#define | DMA_DCHPRI8_ECP_MASK (0x80U)
#define | DMA_DCHPRI8_ECP_SHIFT (7U)
#define | DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

## DCHPRI15 - Channel n Priority Register

#define | DMA_DCHPRI15_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI15_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
#define | DMA_DCHPRI15_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI15_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
#define | DMA_DCHPRI15_DPA_MASK (0x40U)
#define | DMA_DCHPRI15_DPA_SHIFT (6U)
#define | DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
#define | DMA_DCHPRI15_ECP_MASK (0x80U)
#define | DMA_DCHPRI15_ECP_SHIFT (7U)
#define | DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

## DCHPRI14 - Channel n Priority Register

#define | DMA_DCHPRI14_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI14_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
#define | DMA_DCHPRI14_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI14_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
#define | DMA_DCHPRI14_DPA_MASK (0x40U)
#define | DMA_DCHPRI14_DPA_SHIFT (6U)
#define | DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
#define | DMA_DCHPRI14_ECP_MASK (0x80U)
#define | DMA_DCHPRI14_ECP_SHIFT (7U)
#define | DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

## DCHPRI13 - Channel n Priority Register

#define | DMA_DCHPRI13_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI13_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
#define | DMA_DCHPRI13_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI13_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
#define | DMA_DCHPRI13_DPA_MASK (0x40U)
#define | DMA_DCHPRI13_DPA_SHIFT (6U)
#define | DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
#define | DMA_DCHPRI13_ECP_MASK (0x80U)
#define | DMA_DCHPRI13_ECP_SHIFT (7U)
#define | DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

## DCHPRI12 - Channel n Priority Register

#define | DMA_DCHPRI12_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI12_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
#define | DMA_DCHPRI12_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI12_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
#define | DMA_DCHPRI12_DPA_MASK (0x40U)
#define | DMA_DCHPRI12_DPA_SHIFT (6U)
#define | DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
#define | DMA_DCHPRI12_ECP_MASK (0x80U)
#define | DMA_DCHPRI12_ECP_SHIFT (7U)
#define | DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

## DCHPRI19 - Channel n Priority Register

#define | DMA_DCHPRI19_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI19_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
#define | DMA_DCHPRI19_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI19_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
#define | DMA_DCHPRI19_DPA_MASK (0x40U)
#define | DMA_DCHPRI19_DPA_SHIFT (6U)
#define | DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
#define | DMA_DCHPRI19_ECP_MASK (0x80U)
#define | DMA_DCHPRI19_ECP_SHIFT (7U)
#define | DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

## DCHPRI18 - Channel n Priority Register

#define | DMA_DCHPRI18_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI18_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
#define | DMA_DCHPRI18_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI18_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
#define | DMA_DCHPRI18_DPA_MASK (0x40U)
#define | DMA_DCHPRI18_DPA_SHIFT (6U)
#define | DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
#define | DMA_DCHPRI18_ECP_MASK (0x80U)
#define | DMA_DCHPRI18_ECP_SHIFT (7U)
#define | DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

## DCHPRI17 - Channel n Priority Register

#define | DMA_DCHPRI17_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI17_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
#define | DMA_DCHPRI17_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI17_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
#define | DMA_DCHPRI17_DPA_MASK (0x40U)
#define | DMA_DCHPRI17_DPA_SHIFT (6U)
#define | DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
#define | DMA_DCHPRI17_ECP_MASK (0x80U)
#define | DMA_DCHPRI17_ECP_SHIFT (7U)
#define | DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

## DCHPRI16 - Channel n Priority Register

#define | DMA_DCHPRI16_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI16_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
#define | DMA_DCHPRI16_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI16_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
#define | DMA_DCHPRI16_DPA_MASK (0x40U)
#define | DMA_DCHPRI16_DPA_SHIFT (6U)
#define | DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
#define | DMA_DCHPRI16_ECP_MASK (0x80U)
#define | DMA_DCHPRI16_ECP_SHIFT (7U)
#define | DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

## DCHPRI23 - Channel n Priority Register

#define | DMA_DCHPRI23_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI23_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
#define | DMA_DCHPRI23_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI23_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
#define | DMA_DCHPRI23_DPA_MASK (0x40U)
#define | DMA_DCHPRI23_DPA_SHIFT (6U)
#define | DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
#define | DMA_DCHPRI23_ECP_MASK (0x80U)
#define | DMA_DCHPRI23_ECP_SHIFT (7U)
#define | DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

## DCHPRI22 - Channel n Priority Register

#define | DMA_DCHPRI22_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI22_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
#define | DMA_DCHPRI22_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI22_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
#define | DMA_DCHPRI22_DPA_MASK (0x40U)
#define | DMA_DCHPRI22_DPA_SHIFT (6U)
#define | DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
#define | DMA_DCHPRI22_ECP_MASK (0x80U)
#define | DMA_DCHPRI22_ECP_SHIFT (7U)
#define | DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

## DCHPRI21 - Channel n Priority Register

#define | DMA_DCHPRI21_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI21_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
#define | DMA_DCHPRI21_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI21_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
#define | DMA_DCHPRI21_DPA_MASK (0x40U)
#define | DMA_DCHPRI21_DPA_SHIFT (6U)
#define | DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
#define | DMA_DCHPRI21_ECP_MASK (0x80U)
#define | DMA_DCHPRI21_ECP_SHIFT (7U)
#define | DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

## DCHPRI20 - Channel n Priority Register

#define | DMA_DCHPRI20_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI20_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
#define | DMA_DCHPRI20_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI20_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
#define | DMA_DCHPRI20_DPA_MASK (0x40U)
#define | DMA_DCHPRI20_DPA_SHIFT (6U)
#define | DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
#define | DMA_DCHPRI20_ECP_MASK (0x80U)
#define | DMA_DCHPRI20_ECP_SHIFT (7U)
#define | DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

## DCHPRI27 - Channel n Priority Register

#define | DMA_DCHPRI27_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI27_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
#define | DMA_DCHPRI27_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI27_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
#define | DMA_DCHPRI27_DPA_MASK (0x40U)
#define | DMA_DCHPRI27_DPA_SHIFT (6U)
#define | DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
#define | DMA_DCHPRI27_ECP_MASK (0x80U)
#define | DMA_DCHPRI27_ECP_SHIFT (7U)
#define | DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

## DCHPRI26 - Channel n Priority Register

#define | DMA_DCHPRI26_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI26_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
#define | DMA_DCHPRI26_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI26_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
#define | DMA_DCHPRI26_DPA_MASK (0x40U)
#define | DMA_DCHPRI26_DPA_SHIFT (6U)
#define | DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
#define | DMA_DCHPRI26_ECP_MASK (0x80U)
#define | DMA_DCHPRI26_ECP_SHIFT (7U)
#define | DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

## DCHPRI25 - Channel n Priority Register

#define | DMA_DCHPRI25_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI25_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
#define | DMA_DCHPRI25_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI25_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
#define | DMA_DCHPRI25_DPA_MASK (0x40U)
#define | DMA_DCHPRI25_DPA_SHIFT (6U)
#define | DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
#define | DMA_DCHPRI25_ECP_MASK (0x80U)
#define | DMA_DCHPRI25_ECP_SHIFT (7U)
#define | DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

## DCHPRI24 - Channel n Priority Register

#define | DMA_DCHPRI24_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI24_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
#define | DMA_DCHPRI24_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI24_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
#define | DMA_DCHPRI24_DPA_MASK (0x40U)
#define | DMA_DCHPRI24_DPA_SHIFT (6U)
#define | DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
#define | DMA_DCHPRI24_ECP_MASK (0x80U)
#define | DMA_DCHPRI24_ECP_SHIFT (7U)
#define | DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

## DCHPRI31 - Channel n Priority Register

#define | DMA_DCHPRI31_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI31_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
#define | DMA_DCHPRI31_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI31_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
#define | DMA_DCHPRI31_DPA_MASK (0x40U)
#define | DMA_DCHPRI31_DPA_SHIFT (6U)
#define | DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
#define | DMA_DCHPRI31_ECP_MASK (0x80U)
#define | DMA_DCHPRI31_ECP_SHIFT (7U)
#define | DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

## DCHPRI30 - Channel n Priority Register

#define | DMA_DCHPRI30_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI30_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
#define | DMA_DCHPRI30_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI30_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
#define | DMA_DCHPRI30_DPA_MASK (0x40U)
#define | DMA_DCHPRI30_DPA_SHIFT (6U)
#define | DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
#define | DMA_DCHPRI30_ECP_MASK (0x80U)
#define | DMA_DCHPRI30_ECP_SHIFT (7U)
#define | DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

## DCHPRI29 - Channel n Priority Register

#define | DMA_DCHPRI29_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI29_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
#define | DMA_DCHPRI29_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI29_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
#define | DMA_DCHPRI29_DPA_MASK (0x40U)
#define | DMA_DCHPRI29_DPA_SHIFT (6U)
#define | DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
#define | DMA_DCHPRI29_ECP_MASK (0x80U)
#define | DMA_DCHPRI29_ECP_SHIFT (7U)
#define | DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

## DCHPRI28 - Channel n Priority Register

#define | DMA_DCHPRI28_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI28_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
#define | DMA_DCHPRI28_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI28_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
#define | DMA_DCHPRI28_DPA_MASK (0x40U)
#define | DMA_DCHPRI28_DPA_SHIFT (6U)
#define | DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
#define | DMA_DCHPRI28_ECP_MASK (0x80U)
#define | DMA_DCHPRI28_ECP_SHIFT (7U)
#define | DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

## SADDR - TCD Source Address

#define | DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define | DMA_SADDR_SADDR_SHIFT (0U)
#define | DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

## SOFF - TCD Signed Source Address Offset

#define | DMA_SOFF_SOFF_MASK (0xFFFFU)
#define | DMA_SOFF_SOFF_SHIFT (0U)
#define | DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

## ATTR - TCD Transfer Attributes

#define | DMA_ATTR_DSIZE_MASK (0x7U)
#define | DMA_ATTR_DSIZE_SHIFT (0U)
#define | DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
#define | DMA_ATTR_DMOD_MASK (0xF8U)
#define | DMA_ATTR_DMOD_SHIFT (3U)
#define | DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
#define | DMA_ATTR_SSIZE_MASK (0x700U)
#define | DMA_ATTR_SSIZE_SHIFT (8U)
#define | DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
#define | DMA_ATTR_SMOD_MASK (0xF800U)
#define | DMA_ATTR_SMOD_SHIFT (11U)
#define | DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

## NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)

#define | DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
#define | DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
#define | DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

## NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)

#define | DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define | DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
#define | DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define | DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define | DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
#define | DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
#define | DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define | DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
#define | DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

## NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)

#define | DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define | DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
#define | DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define | DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define | DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
#define | DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define | DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define | DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
#define | DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
#define | DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define | DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
#define | DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

## SLAST - TCD Last Source Address Adjustment

#define | DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
#define | DMA_SLAST_SLAST_SHIFT (0U)
#define | DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

## DADDR - TCD Destination Address

#define | DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define | DMA_DADDR_DADDR_SHIFT (0U)
#define | DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

## DOFF - TCD Signed Destination Address Offset

#define | DMA_DOFF_DOFF_MASK (0xFFFFU)
#define | DMA_DOFF_DOFF_SHIFT (0U)
#define | DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

## CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

#define | DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define | DMA_CITER_ELINKNO_CITER_SHIFT (0U)
#define | DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
#define | DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define | DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
#define | DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

## CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

#define | DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define | DMA_CITER_ELINKYES_CITER_SHIFT (0U)
#define | DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
#define | DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define | DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
#define | DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
#define | DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define | DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
#define | DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

## DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address

#define | DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
#define | DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
#define | DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

## CSR - TCD Control and Status

#define | DMA_CSR_START_MASK (0x1U)
#define | DMA_CSR_START_SHIFT (0U)
#define | DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
#define | DMA_CSR_INTMAJOR_MASK (0x2U)
#define | DMA_CSR_INTMAJOR_SHIFT (1U)
#define | DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
#define | DMA_CSR_INTHALF_MASK (0x4U)
#define | DMA_CSR_INTHALF_SHIFT (2U)
#define | DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
#define | DMA_CSR_DREQ_MASK (0x8U)
#define | DMA_CSR_DREQ_SHIFT (3U)
#define | DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
#define | DMA_CSR_ESG_MASK (0x10U)
#define | DMA_CSR_ESG_SHIFT (4U)
#define | DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
#define | DMA_CSR_MAJORELINK_MASK (0x20U)
#define | DMA_CSR_MAJORELINK_SHIFT (5U)
#define | DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
#define | DMA_CSR_ACTIVE_MASK (0x40U)
#define | DMA_CSR_ACTIVE_SHIFT (6U)
#define | DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
#define | DMA_CSR_DONE_MASK (0x80U)
#define | DMA_CSR_DONE_SHIFT (7U)
#define | DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
#define | DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
#define | DMA_CSR_MAJORLINKCH_SHIFT (8U)
#define | DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
#define | DMA_CSR_BWC_MASK (0xC000U)
#define | DMA_CSR_BWC_SHIFT (14U)
#define | DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

## BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

#define | DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define | DMA_BITER_ELINKNO_BITER_SHIFT (0U)
#define | DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
#define | DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define | DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
#define | DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

## BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

#define | DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define | DMA_BITER_ELINKYES_BITER_SHIFT (0U)
#define | DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
#define | DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define | DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
#define | DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
#define | DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define | DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
#define | DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ DMA_ATTR_COUNT

#define DMA_ATTR_COUNT (32U)

Definition at line 15930 of file MIMXRT1062.h.

## ◆ DMA_ATTR_DMOD

#define DMA_ATTR_DMOD | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

DMOD - Destination Address Modulo

Definition at line 15899 of file MIMXRT1062.h.

## ◆ DMA_ATTR_DMOD_MASK

#define DMA_ATTR_DMOD_MASK (0xF8U)

Definition at line 15895 of file MIMXRT1062.h.

## ◆ DMA_ATTR_DMOD_SHIFT

#define DMA_ATTR_DMOD_SHIFT (3U)

Definition at line 15896 of file MIMXRT1062.h.

## ◆ DMA_ATTR_DSIZE

#define DMA_ATTR_DSIZE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

DSIZE - Destination data transfer size

Definition at line 15894 of file MIMXRT1062.h.

## ◆ DMA_ATTR_DSIZE_MASK

#define DMA_ATTR_DSIZE_MASK (0x7U)

Definition at line 15890 of file MIMXRT1062.h.

## ◆ DMA_ATTR_DSIZE_SHIFT

#define DMA_ATTR_DSIZE_SHIFT (0U)

Definition at line 15891 of file MIMXRT1062.h.

## ◆ DMA_ATTR_SMOD

#define DMA_ATTR_SMOD | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.

Definition at line 15926 of file MIMXRT1062.h.

## ◆ DMA_ATTR_SMOD_MASK

#define DMA_ATTR_SMOD_MASK (0xF800U)

Definition at line 15913 of file MIMXRT1062.h.

## ◆ DMA_ATTR_SMOD_SHIFT

#define DMA_ATTR_SMOD_SHIFT (11U)

Definition at line 15914 of file MIMXRT1062.h.

## ◆ DMA_ATTR_SSIZE

#define DMA_ATTR_SSIZE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..64-bit 0b100..Reserved 0b101..32-byte burst (4 beats of 64 bits) 0b110..Reserved 0b111..Reserved

Definition at line 15912 of file MIMXRT1062.h.

## ◆ DMA_ATTR_SSIZE_MASK

#define DMA_ATTR_SSIZE_MASK (0x700U)

Definition at line 15900 of file MIMXRT1062.h.

## ◆ DMA_ATTR_SSIZE_SHIFT

#define DMA_ATTR_SSIZE_SHIFT (8U)

Definition at line 15901 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKNO_BITER

#define DMA_BITER_ELINKNO_BITER | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

BITER - Starting Major Iteration Count

Definition at line 16173 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKNO_BITER_MASK

#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)

Definition at line 16169 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKNO_BITER_SHIFT

#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)

Definition at line 16170 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKNO_COUNT

#define DMA_BITER_ELINKNO_COUNT (32U)

Definition at line 16184 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKNO_ELINK

#define DMA_BITER_ELINKNO_ELINK | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

Definition at line 16180 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKNO_ELINK_MASK

#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)

Definition at line 16174 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKNO_ELINK_SHIFT

#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)

Definition at line 16175 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_BITER

#define DMA_BITER_ELINKYES_BITER | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

BITER - Starting major iteration count

Definition at line 16192 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_BITER_MASK

#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)

Definition at line 16188 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_BITER_SHIFT

#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)

Definition at line 16189 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_COUNT

#define DMA_BITER_ELINKYES_COUNT (32U)

Definition at line 16208 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_ELINK

#define DMA_BITER_ELINKYES_ELINK | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

Definition at line 16204 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_ELINK_MASK

#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)

Definition at line 16198 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_ELINK_SHIFT

#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)

Definition at line 16199 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_LINKCH

#define DMA_BITER_ELINKYES_LINKCH | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

LINKCH - Link Channel Number

Definition at line 16197 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_LINKCH_MASK

#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)

Definition at line 16193 of file MIMXRT1062.h.

## ◆ DMA_BITER_ELINKYES_LINKCH_SHIFT

#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)

Definition at line 16194 of file MIMXRT1062.h.

## ◆ DMA_CDNE_CADN

#define DMA_CDNE_CADN | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE Bits 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0b1..Clears all bits in TCDn_CSR[DONE]

Definition at line 13977 of file MIMXRT1062.h.

## ◆ DMA_CDNE_CADN_MASK

#define DMA_CDNE_CADN_MASK (0x40U)

Definition at line 13971 of file MIMXRT1062.h.

## ◆ DMA_CDNE_CADN_SHIFT

#define DMA_CDNE_CADN_SHIFT (6U)

Definition at line 13972 of file MIMXRT1062.h.

## ◆ DMA_CDNE_CDNE

#define DMA_CDNE_CDNE | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

CDNE - Clear DONE Bit

Definition at line 13970 of file MIMXRT1062.h.

## ◆ DMA_CDNE_CDNE_MASK

#define DMA_CDNE_CDNE_MASK (0x1FU)

Definition at line 13966 of file MIMXRT1062.h.

## ◆ DMA_CDNE_CDNE_SHIFT

#define DMA_CDNE_CDNE_SHIFT (0U)

Definition at line 13967 of file MIMXRT1062.h.

## ◆ DMA_CDNE_NOP

#define DMA_CDNE_NOP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 13984 of file MIMXRT1062.h.

## ◆ DMA_CDNE_NOP_MASK

#define DMA_CDNE_NOP_MASK (0x80U)

Definition at line 13978 of file MIMXRT1062.h.

## ◆ DMA_CDNE_NOP_SHIFT

#define DMA_CDNE_NOP_SHIFT (7U)

Definition at line 13979 of file MIMXRT1062.h.

## ◆ DMA_CEEI_CAEE

#define DMA_CEEI_CAEE | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Clear only the EEI bit specified in the CEEI field 0b1..Clear all bits in EEI

Definition at line 13885 of file MIMXRT1062.h.

## ◆ DMA_CEEI_CAEE_MASK

#define DMA_CEEI_CAEE_MASK (0x40U)

Definition at line 13879 of file MIMXRT1062.h.

## ◆ DMA_CEEI_CAEE_SHIFT

#define DMA_CEEI_CAEE_SHIFT (6U)

Definition at line 13880 of file MIMXRT1062.h.

## ◆ DMA_CEEI_CEEI

#define DMA_CEEI_CEEI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

CEEI - Clear Enable Error Interrupt

Definition at line 13878 of file MIMXRT1062.h.

## ◆ DMA_CEEI_CEEI_MASK

#define DMA_CEEI_CEEI_MASK (0x1FU)

Definition at line 13874 of file MIMXRT1062.h.

## ◆ DMA_CEEI_CEEI_SHIFT

#define DMA_CEEI_CEEI_SHIFT (0U)

Definition at line 13875 of file MIMXRT1062.h.

## ◆ DMA_CEEI_NOP

#define DMA_CEEI_NOP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 13892 of file MIMXRT1062.h.

## ◆ DMA_CEEI_NOP_MASK

#define DMA_CEEI_NOP_MASK (0x80U)

Definition at line 13886 of file MIMXRT1062.h.

## ◆ DMA_CEEI_NOP_SHIFT

#define DMA_CEEI_NOP_SHIFT (7U)

Definition at line 13887 of file MIMXRT1062.h.

## ◆ DMA_CERQ_CAER

#define DMA_CERQ_CAER | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Clear only the ERQ bit specified in the CERQ field 0b1..Clear all bits in ERQ

Definition at line 13931 of file MIMXRT1062.h.

## ◆ DMA_CERQ_CAER_MASK

#define DMA_CERQ_CAER_MASK (0x40U)

Definition at line 13925 of file MIMXRT1062.h.

## ◆ DMA_CERQ_CAER_SHIFT

#define DMA_CERQ_CAER_SHIFT (6U)

Definition at line 13926 of file MIMXRT1062.h.

## ◆ DMA_CERQ_CERQ

#define DMA_CERQ_CERQ | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

CERQ - Clear Enable Request

Definition at line 13924 of file MIMXRT1062.h.

## ◆ DMA_CERQ_CERQ_MASK

#define DMA_CERQ_CERQ_MASK (0x1FU)

Definition at line 13920 of file MIMXRT1062.h.

## ◆ DMA_CERQ_CERQ_SHIFT

#define DMA_CERQ_CERQ_SHIFT (0U)

Definition at line 13921 of file MIMXRT1062.h.

## ◆ DMA_CERQ_NOP

#define DMA_CERQ_NOP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 13938 of file MIMXRT1062.h.

## ◆ DMA_CERQ_NOP_MASK

#define DMA_CERQ_NOP_MASK (0x80U)

Definition at line 13932 of file MIMXRT1062.h.

## ◆ DMA_CERQ_NOP_SHIFT

#define DMA_CERQ_NOP_SHIFT (7U)

Definition at line 13933 of file MIMXRT1062.h.

## ◆ DMA_CERR_CAEI

#define DMA_CERR_CAEI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Clear only the ERR bit specified in the CERR field 0b1..Clear all bits in ERR

Definition at line 14023 of file MIMXRT1062.h.

## ◆ DMA_CERR_CAEI_MASK

#define DMA_CERR_CAEI_MASK (0x40U)

Definition at line 14017 of file MIMXRT1062.h.

## ◆ DMA_CERR_CAEI_SHIFT

#define DMA_CERR_CAEI_SHIFT (6U)

Definition at line 14018 of file MIMXRT1062.h.

## ◆ DMA_CERR_CERR

#define DMA_CERR_CERR | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

CERR - Clear Error Indicator

Definition at line 14016 of file MIMXRT1062.h.

## ◆ DMA_CERR_CERR_MASK

#define DMA_CERR_CERR_MASK (0x1FU)

Definition at line 14012 of file MIMXRT1062.h.

## ◆ DMA_CERR_CERR_SHIFT

#define DMA_CERR_CERR_SHIFT (0U)

Definition at line 14013 of file MIMXRT1062.h.

## ◆ DMA_CERR_NOP

#define DMA_CERR_NOP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 14030 of file MIMXRT1062.h.

## ◆ DMA_CERR_NOP_MASK

#define DMA_CERR_NOP_MASK (0x80U)

Definition at line 14024 of file MIMXRT1062.h.

## ◆ DMA_CERR_NOP_SHIFT

#define DMA_CERR_NOP_SHIFT (7U)

Definition at line 14025 of file MIMXRT1062.h.

## ◆ DMA_CINT_CAIR

#define DMA_CINT_CAIR | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT bit specified in the CINT field 0b1..Clear all bits in INT

Definition at line 14046 of file MIMXRT1062.h.

## ◆ DMA_CINT_CAIR_MASK

#define DMA_CINT_CAIR_MASK (0x40U)

Definition at line 14040 of file MIMXRT1062.h.

## ◆ DMA_CINT_CAIR_SHIFT

#define DMA_CINT_CAIR_SHIFT (6U)

Definition at line 14041 of file MIMXRT1062.h.

## ◆ DMA_CINT_CINT

#define DMA_CINT_CINT | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

CINT - Clear Interrupt Request

Definition at line 14039 of file MIMXRT1062.h.

## ◆ DMA_CINT_CINT_MASK

#define DMA_CINT_CINT_MASK (0x1FU)

Definition at line 14035 of file MIMXRT1062.h.

## ◆ DMA_CINT_CINT_SHIFT

#define DMA_CINT_CINT_SHIFT (0U)

Definition at line 14036 of file MIMXRT1062.h.

## ◆ DMA_CINT_NOP

#define DMA_CINT_NOP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 14053 of file MIMXRT1062.h.

## ◆ DMA_CINT_NOP_MASK

#define DMA_CINT_NOP_MASK (0x80U)

Definition at line 14047 of file MIMXRT1062.h.

## ◆ DMA_CINT_NOP_SHIFT

#define DMA_CINT_NOP_SHIFT (7U)

Definition at line 14048 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKNO_CITER

#define DMA_CITER_ELINKNO_CITER | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

CITER - Current Major Iteration Count

Definition at line 16044 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKNO_CITER_MASK

#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)

Definition at line 16040 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKNO_CITER_SHIFT

#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)

Definition at line 16041 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKNO_COUNT

#define DMA_CITER_ELINKNO_COUNT (32U)

Definition at line 16055 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKNO_ELINK

#define DMA_CITER_ELINKNO_ELINK | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

Definition at line 16051 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKNO_ELINK_MASK

#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)

Definition at line 16045 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKNO_ELINK_SHIFT

#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)

Definition at line 16046 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_CITER

#define DMA_CITER_ELINKYES_CITER | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

CITER - Current Major Iteration Count

Definition at line 16063 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_CITER_MASK

#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)

Definition at line 16059 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_CITER_SHIFT

#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)

Definition at line 16060 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_COUNT

#define DMA_CITER_ELINKYES_COUNT (32U)

Definition at line 16079 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_ELINK

#define DMA_CITER_ELINKYES_ELINK | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

Definition at line 16075 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_ELINK_MASK

#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)

Definition at line 16069 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_ELINK_SHIFT

#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)

Definition at line 16070 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_LINKCH

#define DMA_CITER_ELINKYES_LINKCH | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

LINKCH - Minor Loop Link Channel Number

Definition at line 16068 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_LINKCH_MASK

#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)

Definition at line 16064 of file MIMXRT1062.h.

## ◆ DMA_CITER_ELINKYES_LINKCH_SHIFT

#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)

Definition at line 16065 of file MIMXRT1062.h.

## ◆ DMA_CR_ACTIVE

#define DMA_CR_ACTIVE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)

ACTIVE - DMA Active Status 0b0..eDMA is idle. 0b1..eDMA is executing a channel.

Definition at line 13315 of file MIMXRT1062.h.

## ◆ DMA_CR_ACTIVE_MASK

#define DMA_CR_ACTIVE_MASK (0x80000000U)

Definition at line 13309 of file MIMXRT1062.h.

## ◆ DMA_CR_ACTIVE_SHIFT

#define DMA_CR_ACTIVE_SHIFT (31U)

Definition at line 13310 of file MIMXRT1062.h.

## ◆ DMA_CR_CLM

#define DMA_CR_CLM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.

Definition at line 13269 of file MIMXRT1062.h.

## ◆ DMA_CR_CLM_MASK

#define DMA_CR_CLM_MASK (0x40U)

Definition at line 13260 of file MIMXRT1062.h.

## ◆ DMA_CR_CLM_SHIFT

#define DMA_CR_CLM_SHIFT (6U)

Definition at line 13261 of file MIMXRT1062.h.

## ◆ DMA_CR_CX

#define DMA_CR_CX | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.

Definition at line 13308 of file MIMXRT1062.h.

## ◆ DMA_CR_CX_MASK

#define DMA_CR_CX_MASK (0x20000U)

Definition at line 13300 of file MIMXRT1062.h.

## ◆ DMA_CR_CX_SHIFT

#define DMA_CR_CX_SHIFT (17U)

Definition at line 13301 of file MIMXRT1062.h.

## ◆ DMA_CR_ECX

#define DMA_CR_ECX | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.

Definition at line 13299 of file MIMXRT1062.h.

## ◆ DMA_CR_ECX_MASK

#define DMA_CR_ECX_MASK (0x10000U)

Definition at line 13289 of file MIMXRT1062.h.

## ◆ DMA_CR_ECX_SHIFT

#define DMA_CR_ECX_SHIFT (16U)

Definition at line 13290 of file MIMXRT1062.h.

## ◆ DMA_CR_EDBG

#define DMA_CR_EDBG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When in debug mode, the DMA continues to operate. 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.

Definition at line 13231 of file MIMXRT1062.h.

## ◆ DMA_CR_EDBG_MASK

#define DMA_CR_EDBG_MASK (0x2U)

Definition at line 13224 of file MIMXRT1062.h.

## ◆ DMA_CR_EDBG_SHIFT

#define DMA_CR_EDBG_SHIFT (1U)

Definition at line 13225 of file MIMXRT1062.h.

## ◆ DMA_CR_EMLM

#define DMA_CR_EMLM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.

Definition at line 13278 of file MIMXRT1062.h.

## ◆ DMA_CR_EMLM_MASK

#define DMA_CR_EMLM_MASK (0x80U)

Definition at line 13270 of file MIMXRT1062.h.

## ◆ DMA_CR_EMLM_SHIFT

#define DMA_CR_EMLM_SHIFT (7U)

Definition at line 13271 of file MIMXRT1062.h.

## ◆ DMA_CR_ERCA

#define DMA_CR_ERCA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection within each group. 0b1..Round robin arbitration is used for channel selection within each group.

Definition at line 13238 of file MIMXRT1062.h.

## ◆ DMA_CR_ERCA_MASK

#define DMA_CR_ERCA_MASK (0x4U)

Definition at line 13232 of file MIMXRT1062.h.

## ◆ DMA_CR_ERCA_SHIFT

#define DMA_CR_ERCA_SHIFT (2U)

Definition at line 13233 of file MIMXRT1062.h.

## ◆ DMA_CR_ERGA

#define DMA_CR_ERGA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

ERGA - Enable Round Robin Group Arbitration 0b0..Fixed priority arbitration is used for selection among the groups. 0b1..Round robin arbitration is used for selection among the groups.

Definition at line 13245 of file MIMXRT1062.h.

## ◆ DMA_CR_ERGA_MASK

#define DMA_CR_ERGA_MASK (0x8U)

Definition at line 13239 of file MIMXRT1062.h.

## ◆ DMA_CR_ERGA_SHIFT

#define DMA_CR_ERGA_SHIFT (3U)

Definition at line 13240 of file MIMXRT1062.h.

## ◆ DMA_CR_GRP0PRI

#define DMA_CR_GRP0PRI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

GRP0PRI - Channel Group 0 Priority

Definition at line 13283 of file MIMXRT1062.h.

## ◆ DMA_CR_GRP0PRI_MASK

#define DMA_CR_GRP0PRI_MASK (0x100U)

Definition at line 13279 of file MIMXRT1062.h.

## ◆ DMA_CR_GRP0PRI_SHIFT

#define DMA_CR_GRP0PRI_SHIFT (8U)

Definition at line 13280 of file MIMXRT1062.h.

## ◆ DMA_CR_GRP1PRI

#define DMA_CR_GRP1PRI | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

GRP1PRI - Channel Group 1 Priority

Definition at line 13288 of file MIMXRT1062.h.

## ◆ DMA_CR_GRP1PRI_MASK

#define DMA_CR_GRP1PRI_MASK (0x400U)

Definition at line 13284 of file MIMXRT1062.h.

## ◆ DMA_CR_GRP1PRI_SHIFT

#define DMA_CR_GRP1PRI_SHIFT (10U)

Definition at line 13285 of file MIMXRT1062.h.

## ◆ DMA_CR_HALT

#define DMA_CR_HALT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt DMA Operations 0b0..Normal operation 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.

Definition at line 13259 of file MIMXRT1062.h.

## ◆ DMA_CR_HALT_MASK

#define DMA_CR_HALT_MASK (0x20U)

Definition at line 13253 of file MIMXRT1062.h.

## ◆ DMA_CR_HALT_SHIFT

#define DMA_CR_HALT_SHIFT (5U)

Definition at line 13254 of file MIMXRT1062.h.

## ◆ DMA_CR_HOE

#define DMA_CR_HOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

Definition at line 13252 of file MIMXRT1062.h.

## ◆ DMA_CR_HOE_MASK

#define DMA_CR_HOE_MASK (0x10U)

Definition at line 13246 of file MIMXRT1062.h.

## ◆ DMA_CR_HOE_SHIFT

#define DMA_CR_HOE_SHIFT (4U)

Definition at line 13247 of file MIMXRT1062.h.

## ◆ DMA_CSR_ACTIVE

#define DMA_CSR_ACTIVE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

ACTIVE - Channel Active

Definition at line 16142 of file MIMXRT1062.h.

## ◆ DMA_CSR_ACTIVE_MASK

#define DMA_CSR_ACTIVE_MASK (0x40U)

Definition at line 16138 of file MIMXRT1062.h.

## ◆ DMA_CSR_ACTIVE_SHIFT

#define DMA_CSR_ACTIVE_SHIFT (6U)

Definition at line 16139 of file MIMXRT1062.h.

## ◆ DMA_CSR_BWC

#define DMA_CSR_BWC | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls. 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

Definition at line 16161 of file MIMXRT1062.h.

## ◆ DMA_CSR_BWC_MASK

#define DMA_CSR_BWC_MASK (0xC000U)

Definition at line 16153 of file MIMXRT1062.h.

## ◆ DMA_CSR_BWC_SHIFT

#define DMA_CSR_BWC_SHIFT (14U)

Definition at line 16154 of file MIMXRT1062.h.

## ◆ DMA_CSR_COUNT

#define DMA_CSR_COUNT (32U)

Definition at line 16165 of file MIMXRT1062.h.

## ◆ DMA_CSR_DONE

#define DMA_CSR_DONE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

DONE - Channel Done

Definition at line 16147 of file MIMXRT1062.h.

## ◆ DMA_CSR_DONE_MASK

#define DMA_CSR_DONE_MASK (0x80U)

Definition at line 16143 of file MIMXRT1062.h.

## ◆ DMA_CSR_DONE_SHIFT

#define DMA_CSR_DONE_SHIFT (7U)

Definition at line 16144 of file MIMXRT1062.h.

## ◆ DMA_CSR_DREQ

#define DMA_CSR_DREQ | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected. 0b1..The channel's ERQ bit is cleared when the major loop is complete.

Definition at line 16122 of file MIMXRT1062.h.

## ◆ DMA_CSR_DREQ_MASK

#define DMA_CSR_DREQ_MASK (0x8U)

Definition at line 16116 of file MIMXRT1062.h.

## ◆ DMA_CSR_DREQ_SHIFT

#define DMA_CSR_DREQ_SHIFT (3U)

Definition at line 16117 of file MIMXRT1062.h.

## ◆ DMA_CSR_ESG

#define DMA_CSR_ESG | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format. 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.

Definition at line 16130 of file MIMXRT1062.h.

## ◆ DMA_CSR_ESG_MASK

#define DMA_CSR_ESG_MASK (0x10U)

Definition at line 16123 of file MIMXRT1062.h.

## ◆ DMA_CSR_ESG_SHIFT

#define DMA_CSR_ESG_SHIFT (4U)

Definition at line 16124 of file MIMXRT1062.h.

## ◆ DMA_CSR_INTHALF

#define DMA_CSR_INTHALF | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled. 0b1..The half-point interrupt is enabled.

Definition at line 16115 of file MIMXRT1062.h.

## ◆ DMA_CSR_INTHALF_MASK

#define DMA_CSR_INTHALF_MASK (0x4U)

Definition at line 16109 of file MIMXRT1062.h.

## ◆ DMA_CSR_INTHALF_SHIFT

#define DMA_CSR_INTHALF_SHIFT (2U)

Definition at line 16110 of file MIMXRT1062.h.

## ◆ DMA_CSR_INTMAJOR

#define DMA_CSR_INTMAJOR | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..The end-of-major loop interrupt is disabled. 0b1..The end-of-major loop interrupt is enabled.

Definition at line 16108 of file MIMXRT1062.h.

## ◆ DMA_CSR_INTMAJOR_MASK

#define DMA_CSR_INTMAJOR_MASK (0x2U)

Definition at line 16102 of file MIMXRT1062.h.

## ◆ DMA_CSR_INTMAJOR_SHIFT

#define DMA_CSR_INTMAJOR_SHIFT (1U)

Definition at line 16103 of file MIMXRT1062.h.

## ◆ DMA_CSR_MAJORELINK

#define DMA_CSR_MAJORELINK | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled. 0b1..The channel-to-channel linking is enabled.

Definition at line 16137 of file MIMXRT1062.h.

## ◆ DMA_CSR_MAJORELINK_MASK

#define DMA_CSR_MAJORELINK_MASK (0x20U)

Definition at line 16131 of file MIMXRT1062.h.

## ◆ DMA_CSR_MAJORELINK_SHIFT

#define DMA_CSR_MAJORELINK_SHIFT (5U)

Definition at line 16132 of file MIMXRT1062.h.

## ◆ DMA_CSR_MAJORLINKCH

#define DMA_CSR_MAJORLINKCH | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

MAJORLINKCH - Major Loop Link Channel Number

Definition at line 16152 of file MIMXRT1062.h.

## ◆ DMA_CSR_MAJORLINKCH_MASK

#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)

Definition at line 16148 of file MIMXRT1062.h.

## ◆ DMA_CSR_MAJORLINKCH_SHIFT

#define DMA_CSR_MAJORLINKCH_SHIFT (8U)

Definition at line 16149 of file MIMXRT1062.h.

## ◆ DMA_CSR_START

#define DMA_CSR_START | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..The channel is not explicitly started. 0b1..The channel is explicitly started via a software initiated service request.

Definition at line 16101 of file MIMXRT1062.h.

## ◆ DMA_CSR_START_MASK

#define DMA_CSR_START_MASK (0x1U)

Definition at line 16095 of file MIMXRT1062.h.

## ◆ DMA_CSR_START_SHIFT

#define DMA_CSR_START_SHIFT (0U)

Definition at line 16096 of file MIMXRT1062.h.

## ◆ DMA_DADDR_COUNT

#define DMA_DADDR_COUNT (32U)

Definition at line 16024 of file MIMXRT1062.h.

## ◆ DMA_DADDR_DADDR

#define DMA_DADDR_DADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

DADDR - Destination Address

Definition at line 16020 of file MIMXRT1062.h.

## ◆ DMA_DADDR_DADDR_MASK

#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)

Definition at line 16016 of file MIMXRT1062.h.

## ◆ DMA_DADDR_DADDR_SHIFT

#define DMA_DADDR_DADDR_SHIFT (0U)

Definition at line 16017 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_CHPRI

#define DMA_DCHPRI0_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15058 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_CHPRI_MASK

#define DMA_DCHPRI0_CHPRI_MASK (0xFU)

Definition at line 15054 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_CHPRI_SHIFT

#define DMA_DCHPRI0_CHPRI_SHIFT (0U)

Definition at line 15055 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_DPA

#define DMA_DCHPRI0_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15070 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_DPA_MASK

#define DMA_DCHPRI0_DPA_MASK (0x40U)

Definition at line 15064 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_DPA_SHIFT

#define DMA_DCHPRI0_DPA_SHIFT (6U)

Definition at line 15065 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_ECP

#define DMA_DCHPRI0_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15077 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_ECP_MASK

#define DMA_DCHPRI0_ECP_MASK (0x80U)

Definition at line 15071 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_ECP_SHIFT

#define DMA_DCHPRI0_ECP_SHIFT (7U)

Definition at line 15072 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_GRPPRI

#define DMA_DCHPRI0_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15063 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_GRPPRI_MASK

#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)

Definition at line 15059 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI0_GRPPRI_SHIFT

#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)

Definition at line 15060 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_CHPRI

#define DMA_DCHPRI10_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15226 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_CHPRI_MASK

#define DMA_DCHPRI10_CHPRI_MASK (0xFU)

Definition at line 15222 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_CHPRI_SHIFT

#define DMA_DCHPRI10_CHPRI_SHIFT (0U)

Definition at line 15223 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_DPA

#define DMA_DCHPRI10_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15238 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_DPA_MASK

#define DMA_DCHPRI10_DPA_MASK (0x40U)

Definition at line 15232 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_DPA_SHIFT

#define DMA_DCHPRI10_DPA_SHIFT (6U)

Definition at line 15233 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_ECP

#define DMA_DCHPRI10_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15245 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_ECP_MASK

#define DMA_DCHPRI10_ECP_MASK (0x80U)

Definition at line 15239 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_ECP_SHIFT

#define DMA_DCHPRI10_ECP_SHIFT (7U)

Definition at line 15240 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_GRPPRI

#define DMA_DCHPRI10_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15231 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_GRPPRI_MASK

#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)

Definition at line 15227 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI10_GRPPRI_SHIFT

#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)

Definition at line 15228 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_CHPRI

#define DMA_DCHPRI11_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15198 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_CHPRI_MASK

#define DMA_DCHPRI11_CHPRI_MASK (0xFU)

Definition at line 15194 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_CHPRI_SHIFT

#define DMA_DCHPRI11_CHPRI_SHIFT (0U)

Definition at line 15195 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_DPA

#define DMA_DCHPRI11_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15210 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_DPA_MASK

#define DMA_DCHPRI11_DPA_MASK (0x40U)

Definition at line 15204 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_DPA_SHIFT

#define DMA_DCHPRI11_DPA_SHIFT (6U)

Definition at line 15205 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_ECP

#define DMA_DCHPRI11_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15217 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_ECP_MASK

#define DMA_DCHPRI11_ECP_MASK (0x80U)

Definition at line 15211 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_ECP_SHIFT

#define DMA_DCHPRI11_ECP_SHIFT (7U)

Definition at line 15212 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_GRPPRI

#define DMA_DCHPRI11_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15203 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_GRPPRI_MASK

#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)

Definition at line 15199 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI11_GRPPRI_SHIFT

#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)

Definition at line 15200 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_CHPRI

#define DMA_DCHPRI12_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15394 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_CHPRI_MASK

#define DMA_DCHPRI12_CHPRI_MASK (0xFU)

Definition at line 15390 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_CHPRI_SHIFT

#define DMA_DCHPRI12_CHPRI_SHIFT (0U)

Definition at line 15391 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_DPA

#define DMA_DCHPRI12_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15406 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_DPA_MASK

#define DMA_DCHPRI12_DPA_MASK (0x40U)

Definition at line 15400 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_DPA_SHIFT

#define DMA_DCHPRI12_DPA_SHIFT (6U)

Definition at line 15401 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_ECP

#define DMA_DCHPRI12_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15413 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_ECP_MASK

#define DMA_DCHPRI12_ECP_MASK (0x80U)

Definition at line 15407 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_ECP_SHIFT

#define DMA_DCHPRI12_ECP_SHIFT (7U)

Definition at line 15408 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_GRPPRI

#define DMA_DCHPRI12_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15399 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_GRPPRI_MASK

#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)

Definition at line 15395 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI12_GRPPRI_SHIFT

#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)

Definition at line 15396 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_CHPRI

#define DMA_DCHPRI13_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15366 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_CHPRI_MASK

#define DMA_DCHPRI13_CHPRI_MASK (0xFU)

Definition at line 15362 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_CHPRI_SHIFT

#define DMA_DCHPRI13_CHPRI_SHIFT (0U)

Definition at line 15363 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_DPA

#define DMA_DCHPRI13_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15378 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_DPA_MASK

#define DMA_DCHPRI13_DPA_MASK (0x40U)

Definition at line 15372 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_DPA_SHIFT

#define DMA_DCHPRI13_DPA_SHIFT (6U)

Definition at line 15373 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_ECP

#define DMA_DCHPRI13_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15385 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_ECP_MASK

#define DMA_DCHPRI13_ECP_MASK (0x80U)

Definition at line 15379 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_ECP_SHIFT

#define DMA_DCHPRI13_ECP_SHIFT (7U)

Definition at line 15380 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_GRPPRI

#define DMA_DCHPRI13_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15371 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_GRPPRI_MASK

#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)

Definition at line 15367 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI13_GRPPRI_SHIFT

#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)

Definition at line 15368 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_CHPRI

#define DMA_DCHPRI14_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15338 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_CHPRI_MASK

#define DMA_DCHPRI14_CHPRI_MASK (0xFU)

Definition at line 15334 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_CHPRI_SHIFT

#define DMA_DCHPRI14_CHPRI_SHIFT (0U)

Definition at line 15335 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_DPA

#define DMA_DCHPRI14_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15350 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_DPA_MASK

#define DMA_DCHPRI14_DPA_MASK (0x40U)

Definition at line 15344 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_DPA_SHIFT

#define DMA_DCHPRI14_DPA_SHIFT (6U)

Definition at line 15345 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_ECP

#define DMA_DCHPRI14_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15357 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_ECP_MASK

#define DMA_DCHPRI14_ECP_MASK (0x80U)

Definition at line 15351 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_ECP_SHIFT

#define DMA_DCHPRI14_ECP_SHIFT (7U)

Definition at line 15352 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_GRPPRI

#define DMA_DCHPRI14_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15343 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_GRPPRI_MASK

#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)

Definition at line 15339 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI14_GRPPRI_SHIFT

#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)

Definition at line 15340 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_CHPRI

#define DMA_DCHPRI15_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15310 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_CHPRI_MASK

#define DMA_DCHPRI15_CHPRI_MASK (0xFU)

Definition at line 15306 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_CHPRI_SHIFT

#define DMA_DCHPRI15_CHPRI_SHIFT (0U)

Definition at line 15307 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_DPA

#define DMA_DCHPRI15_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15322 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_DPA_MASK

#define DMA_DCHPRI15_DPA_MASK (0x40U)

Definition at line 15316 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_DPA_SHIFT

#define DMA_DCHPRI15_DPA_SHIFT (6U)

Definition at line 15317 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_ECP

#define DMA_DCHPRI15_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15329 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_ECP_MASK

#define DMA_DCHPRI15_ECP_MASK (0x80U)

Definition at line 15323 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_ECP_SHIFT

#define DMA_DCHPRI15_ECP_SHIFT (7U)

Definition at line 15324 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_GRPPRI

#define DMA_DCHPRI15_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15315 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_GRPPRI_MASK

#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)

Definition at line 15311 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI15_GRPPRI_SHIFT

#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)

Definition at line 15312 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_CHPRI

#define DMA_DCHPRI16_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15506 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_CHPRI_MASK

#define DMA_DCHPRI16_CHPRI_MASK (0xFU)

Definition at line 15502 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_CHPRI_SHIFT

#define DMA_DCHPRI16_CHPRI_SHIFT (0U)

Definition at line 15503 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_DPA

#define DMA_DCHPRI16_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15518 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_DPA_MASK

#define DMA_DCHPRI16_DPA_MASK (0x40U)

Definition at line 15512 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_DPA_SHIFT

#define DMA_DCHPRI16_DPA_SHIFT (6U)

Definition at line 15513 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_ECP

#define DMA_DCHPRI16_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15525 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_ECP_MASK

#define DMA_DCHPRI16_ECP_MASK (0x80U)

Definition at line 15519 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_ECP_SHIFT

#define DMA_DCHPRI16_ECP_SHIFT (7U)

Definition at line 15520 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_GRPPRI

#define DMA_DCHPRI16_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15511 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_GRPPRI_MASK

#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)

Definition at line 15507 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI16_GRPPRI_SHIFT

#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)

Definition at line 15508 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_CHPRI

#define DMA_DCHPRI17_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15478 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_CHPRI_MASK

#define DMA_DCHPRI17_CHPRI_MASK (0xFU)

Definition at line 15474 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_CHPRI_SHIFT

#define DMA_DCHPRI17_CHPRI_SHIFT (0U)

Definition at line 15475 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_DPA

#define DMA_DCHPRI17_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15490 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_DPA_MASK

#define DMA_DCHPRI17_DPA_MASK (0x40U)

Definition at line 15484 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_DPA_SHIFT

#define DMA_DCHPRI17_DPA_SHIFT (6U)

Definition at line 15485 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_ECP

#define DMA_DCHPRI17_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15497 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_ECP_MASK

#define DMA_DCHPRI17_ECP_MASK (0x80U)

Definition at line 15491 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_ECP_SHIFT

#define DMA_DCHPRI17_ECP_SHIFT (7U)

Definition at line 15492 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_GRPPRI

#define DMA_DCHPRI17_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15483 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_GRPPRI_MASK

#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)

Definition at line 15479 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI17_GRPPRI_SHIFT

#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)

Definition at line 15480 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_CHPRI

#define DMA_DCHPRI18_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15450 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_CHPRI_MASK

#define DMA_DCHPRI18_CHPRI_MASK (0xFU)

Definition at line 15446 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_CHPRI_SHIFT

#define DMA_DCHPRI18_CHPRI_SHIFT (0U)

Definition at line 15447 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_DPA

#define DMA_DCHPRI18_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15462 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_DPA_MASK

#define DMA_DCHPRI18_DPA_MASK (0x40U)

Definition at line 15456 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_DPA_SHIFT

#define DMA_DCHPRI18_DPA_SHIFT (6U)

Definition at line 15457 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_ECP

#define DMA_DCHPRI18_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15469 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_ECP_MASK

#define DMA_DCHPRI18_ECP_MASK (0x80U)

Definition at line 15463 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_ECP_SHIFT

#define DMA_DCHPRI18_ECP_SHIFT (7U)

Definition at line 15464 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_GRPPRI

#define DMA_DCHPRI18_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15455 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_GRPPRI_MASK

#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)

Definition at line 15451 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI18_GRPPRI_SHIFT

#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)

Definition at line 15452 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_CHPRI

#define DMA_DCHPRI19_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15422 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_CHPRI_MASK

#define DMA_DCHPRI19_CHPRI_MASK (0xFU)

Definition at line 15418 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_CHPRI_SHIFT

#define DMA_DCHPRI19_CHPRI_SHIFT (0U)

Definition at line 15419 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_DPA

#define DMA_DCHPRI19_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15434 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_DPA_MASK

#define DMA_DCHPRI19_DPA_MASK (0x40U)

Definition at line 15428 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_DPA_SHIFT

#define DMA_DCHPRI19_DPA_SHIFT (6U)

Definition at line 15429 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_ECP

#define DMA_DCHPRI19_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15441 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_ECP_MASK

#define DMA_DCHPRI19_ECP_MASK (0x80U)

Definition at line 15435 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_ECP_SHIFT

#define DMA_DCHPRI19_ECP_SHIFT (7U)

Definition at line 15436 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_GRPPRI

#define DMA_DCHPRI19_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15427 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_GRPPRI_MASK

#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)

Definition at line 15423 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI19_GRPPRI_SHIFT

#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)

Definition at line 15424 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_CHPRI

#define DMA_DCHPRI1_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15030 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_CHPRI_MASK

#define DMA_DCHPRI1_CHPRI_MASK (0xFU)

Definition at line 15026 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_CHPRI_SHIFT

#define DMA_DCHPRI1_CHPRI_SHIFT (0U)

Definition at line 15027 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_DPA

#define DMA_DCHPRI1_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15042 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_DPA_MASK

#define DMA_DCHPRI1_DPA_MASK (0x40U)

Definition at line 15036 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_DPA_SHIFT

#define DMA_DCHPRI1_DPA_SHIFT (6U)

Definition at line 15037 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_ECP

#define DMA_DCHPRI1_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15049 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_ECP_MASK

#define DMA_DCHPRI1_ECP_MASK (0x80U)

Definition at line 15043 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_ECP_SHIFT

#define DMA_DCHPRI1_ECP_SHIFT (7U)

Definition at line 15044 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_GRPPRI

#define DMA_DCHPRI1_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15035 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_GRPPRI_MASK

#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)

Definition at line 15031 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI1_GRPPRI_SHIFT

#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)

Definition at line 15032 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_CHPRI

#define DMA_DCHPRI20_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15618 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_CHPRI_MASK

#define DMA_DCHPRI20_CHPRI_MASK (0xFU)

Definition at line 15614 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_CHPRI_SHIFT

#define DMA_DCHPRI20_CHPRI_SHIFT (0U)

Definition at line 15615 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_DPA

#define DMA_DCHPRI20_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15630 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_DPA_MASK

#define DMA_DCHPRI20_DPA_MASK (0x40U)

Definition at line 15624 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_DPA_SHIFT

#define DMA_DCHPRI20_DPA_SHIFT (6U)

Definition at line 15625 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_ECP

#define DMA_DCHPRI20_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15637 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_ECP_MASK

#define DMA_DCHPRI20_ECP_MASK (0x80U)

Definition at line 15631 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_ECP_SHIFT

#define DMA_DCHPRI20_ECP_SHIFT (7U)

Definition at line 15632 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_GRPPRI

#define DMA_DCHPRI20_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15623 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_GRPPRI_MASK

#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)

Definition at line 15619 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI20_GRPPRI_SHIFT

#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)

Definition at line 15620 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_CHPRI

#define DMA_DCHPRI21_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15590 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_CHPRI_MASK

#define DMA_DCHPRI21_CHPRI_MASK (0xFU)

Definition at line 15586 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_CHPRI_SHIFT

#define DMA_DCHPRI21_CHPRI_SHIFT (0U)

Definition at line 15587 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_DPA

#define DMA_DCHPRI21_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15602 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_DPA_MASK

#define DMA_DCHPRI21_DPA_MASK (0x40U)

Definition at line 15596 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_DPA_SHIFT

#define DMA_DCHPRI21_DPA_SHIFT (6U)

Definition at line 15597 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_ECP

#define DMA_DCHPRI21_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15609 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_ECP_MASK

#define DMA_DCHPRI21_ECP_MASK (0x80U)

Definition at line 15603 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_ECP_SHIFT

#define DMA_DCHPRI21_ECP_SHIFT (7U)

Definition at line 15604 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_GRPPRI

#define DMA_DCHPRI21_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15595 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_GRPPRI_MASK

#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)

Definition at line 15591 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI21_GRPPRI_SHIFT

#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)

Definition at line 15592 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_CHPRI

#define DMA_DCHPRI22_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15562 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_CHPRI_MASK

#define DMA_DCHPRI22_CHPRI_MASK (0xFU)

Definition at line 15558 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_CHPRI_SHIFT

#define DMA_DCHPRI22_CHPRI_SHIFT (0U)

Definition at line 15559 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_DPA

#define DMA_DCHPRI22_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15574 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_DPA_MASK

#define DMA_DCHPRI22_DPA_MASK (0x40U)

Definition at line 15568 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_DPA_SHIFT

#define DMA_DCHPRI22_DPA_SHIFT (6U)

Definition at line 15569 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_ECP

#define DMA_DCHPRI22_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15581 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_ECP_MASK

#define DMA_DCHPRI22_ECP_MASK (0x80U)

Definition at line 15575 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_ECP_SHIFT

#define DMA_DCHPRI22_ECP_SHIFT (7U)

Definition at line 15576 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_GRPPRI

#define DMA_DCHPRI22_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15567 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_GRPPRI_MASK

#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)

Definition at line 15563 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI22_GRPPRI_SHIFT

#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)

Definition at line 15564 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_CHPRI

#define DMA_DCHPRI23_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15534 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_CHPRI_MASK

#define DMA_DCHPRI23_CHPRI_MASK (0xFU)

Definition at line 15530 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_CHPRI_SHIFT

#define DMA_DCHPRI23_CHPRI_SHIFT (0U)

Definition at line 15531 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_DPA

#define DMA_DCHPRI23_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15546 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_DPA_MASK

#define DMA_DCHPRI23_DPA_MASK (0x40U)

Definition at line 15540 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_DPA_SHIFT

#define DMA_DCHPRI23_DPA_SHIFT (6U)

Definition at line 15541 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_ECP

#define DMA_DCHPRI23_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15553 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_ECP_MASK

#define DMA_DCHPRI23_ECP_MASK (0x80U)

Definition at line 15547 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_ECP_SHIFT

#define DMA_DCHPRI23_ECP_SHIFT (7U)

Definition at line 15548 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_GRPPRI

#define DMA_DCHPRI23_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15539 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_GRPPRI_MASK

#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)

Definition at line 15535 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI23_GRPPRI_SHIFT

#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)

Definition at line 15536 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_CHPRI

#define DMA_DCHPRI24_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15730 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_CHPRI_MASK

#define DMA_DCHPRI24_CHPRI_MASK (0xFU)

Definition at line 15726 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_CHPRI_SHIFT

#define DMA_DCHPRI24_CHPRI_SHIFT (0U)

Definition at line 15727 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_DPA

#define DMA_DCHPRI24_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15742 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_DPA_MASK

#define DMA_DCHPRI24_DPA_MASK (0x40U)

Definition at line 15736 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_DPA_SHIFT

#define DMA_DCHPRI24_DPA_SHIFT (6U)

Definition at line 15737 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_ECP

#define DMA_DCHPRI24_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15749 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_ECP_MASK

#define DMA_DCHPRI24_ECP_MASK (0x80U)

Definition at line 15743 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_ECP_SHIFT

#define DMA_DCHPRI24_ECP_SHIFT (7U)

Definition at line 15744 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_GRPPRI

#define DMA_DCHPRI24_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15735 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_GRPPRI_MASK

#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)

Definition at line 15731 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI24_GRPPRI_SHIFT

#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)

Definition at line 15732 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_CHPRI

#define DMA_DCHPRI25_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15702 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_CHPRI_MASK

#define DMA_DCHPRI25_CHPRI_MASK (0xFU)

Definition at line 15698 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_CHPRI_SHIFT

#define DMA_DCHPRI25_CHPRI_SHIFT (0U)

Definition at line 15699 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_DPA

#define DMA_DCHPRI25_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15714 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_DPA_MASK

#define DMA_DCHPRI25_DPA_MASK (0x40U)

Definition at line 15708 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_DPA_SHIFT

#define DMA_DCHPRI25_DPA_SHIFT (6U)

Definition at line 15709 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_ECP

#define DMA_DCHPRI25_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15721 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_ECP_MASK

#define DMA_DCHPRI25_ECP_MASK (0x80U)

Definition at line 15715 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_ECP_SHIFT

#define DMA_DCHPRI25_ECP_SHIFT (7U)

Definition at line 15716 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_GRPPRI

#define DMA_DCHPRI25_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15707 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_GRPPRI_MASK

#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)

Definition at line 15703 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI25_GRPPRI_SHIFT

#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)

Definition at line 15704 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_CHPRI

#define DMA_DCHPRI26_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15674 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_CHPRI_MASK

#define DMA_DCHPRI26_CHPRI_MASK (0xFU)

Definition at line 15670 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_CHPRI_SHIFT

#define DMA_DCHPRI26_CHPRI_SHIFT (0U)

Definition at line 15671 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_DPA

#define DMA_DCHPRI26_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15686 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_DPA_MASK

#define DMA_DCHPRI26_DPA_MASK (0x40U)

Definition at line 15680 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_DPA_SHIFT

#define DMA_DCHPRI26_DPA_SHIFT (6U)

Definition at line 15681 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_ECP

#define DMA_DCHPRI26_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15693 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_ECP_MASK

#define DMA_DCHPRI26_ECP_MASK (0x80U)

Definition at line 15687 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_ECP_SHIFT

#define DMA_DCHPRI26_ECP_SHIFT (7U)

Definition at line 15688 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_GRPPRI

#define DMA_DCHPRI26_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15679 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_GRPPRI_MASK

#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)

Definition at line 15675 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI26_GRPPRI_SHIFT

#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)

Definition at line 15676 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_CHPRI

#define DMA_DCHPRI27_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15646 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_CHPRI_MASK

#define DMA_DCHPRI27_CHPRI_MASK (0xFU)

Definition at line 15642 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_CHPRI_SHIFT

#define DMA_DCHPRI27_CHPRI_SHIFT (0U)

Definition at line 15643 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_DPA

#define DMA_DCHPRI27_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15658 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_DPA_MASK

#define DMA_DCHPRI27_DPA_MASK (0x40U)

Definition at line 15652 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_DPA_SHIFT

#define DMA_DCHPRI27_DPA_SHIFT (6U)

Definition at line 15653 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_ECP

#define DMA_DCHPRI27_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15665 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_ECP_MASK

#define DMA_DCHPRI27_ECP_MASK (0x80U)

Definition at line 15659 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_ECP_SHIFT

#define DMA_DCHPRI27_ECP_SHIFT (7U)

Definition at line 15660 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_GRPPRI

#define DMA_DCHPRI27_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15651 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_GRPPRI_MASK

#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)

Definition at line 15647 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI27_GRPPRI_SHIFT

#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)

Definition at line 15648 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_CHPRI

#define DMA_DCHPRI28_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15842 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_CHPRI_MASK

#define DMA_DCHPRI28_CHPRI_MASK (0xFU)

Definition at line 15838 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_CHPRI_SHIFT

#define DMA_DCHPRI28_CHPRI_SHIFT (0U)

Definition at line 15839 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_DPA

#define DMA_DCHPRI28_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15854 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_DPA_MASK

#define DMA_DCHPRI28_DPA_MASK (0x40U)

Definition at line 15848 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_DPA_SHIFT

#define DMA_DCHPRI28_DPA_SHIFT (6U)

Definition at line 15849 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_ECP

#define DMA_DCHPRI28_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15861 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_ECP_MASK

#define DMA_DCHPRI28_ECP_MASK (0x80U)

Definition at line 15855 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_ECP_SHIFT

#define DMA_DCHPRI28_ECP_SHIFT (7U)

Definition at line 15856 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_GRPPRI

#define DMA_DCHPRI28_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15847 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_GRPPRI_MASK

#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)

Definition at line 15843 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI28_GRPPRI_SHIFT

#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)

Definition at line 15844 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_CHPRI

#define DMA_DCHPRI29_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15814 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_CHPRI_MASK

#define DMA_DCHPRI29_CHPRI_MASK (0xFU)

Definition at line 15810 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_CHPRI_SHIFT

#define DMA_DCHPRI29_CHPRI_SHIFT (0U)

Definition at line 15811 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_DPA

#define DMA_DCHPRI29_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15826 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_DPA_MASK

#define DMA_DCHPRI29_DPA_MASK (0x40U)

Definition at line 15820 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_DPA_SHIFT

#define DMA_DCHPRI29_DPA_SHIFT (6U)

Definition at line 15821 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_ECP

#define DMA_DCHPRI29_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15833 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_ECP_MASK

#define DMA_DCHPRI29_ECP_MASK (0x80U)

Definition at line 15827 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_ECP_SHIFT

#define DMA_DCHPRI29_ECP_SHIFT (7U)

Definition at line 15828 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_GRPPRI

#define DMA_DCHPRI29_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15819 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_GRPPRI_MASK

#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)

Definition at line 15815 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI29_GRPPRI_SHIFT

#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)

Definition at line 15816 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_CHPRI

#define DMA_DCHPRI2_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15002 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_CHPRI_MASK

#define DMA_DCHPRI2_CHPRI_MASK (0xFU)

Definition at line 14998 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_CHPRI_SHIFT

#define DMA_DCHPRI2_CHPRI_SHIFT (0U)

Definition at line 14999 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_DPA

#define DMA_DCHPRI2_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15014 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_DPA_MASK

#define DMA_DCHPRI2_DPA_MASK (0x40U)

Definition at line 15008 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_DPA_SHIFT

#define DMA_DCHPRI2_DPA_SHIFT (6U)

Definition at line 15009 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_ECP

#define DMA_DCHPRI2_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15021 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_ECP_MASK

#define DMA_DCHPRI2_ECP_MASK (0x80U)

Definition at line 15015 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_ECP_SHIFT

#define DMA_DCHPRI2_ECP_SHIFT (7U)

Definition at line 15016 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_GRPPRI

#define DMA_DCHPRI2_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15007 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_GRPPRI_MASK

#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)

Definition at line 15003 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI2_GRPPRI_SHIFT

#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)

Definition at line 15004 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_CHPRI

#define DMA_DCHPRI30_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15786 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_CHPRI_MASK

#define DMA_DCHPRI30_CHPRI_MASK (0xFU)

Definition at line 15782 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_CHPRI_SHIFT

#define DMA_DCHPRI30_CHPRI_SHIFT (0U)

Definition at line 15783 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_DPA

#define DMA_DCHPRI30_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15798 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_DPA_MASK

#define DMA_DCHPRI30_DPA_MASK (0x40U)

Definition at line 15792 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_DPA_SHIFT

#define DMA_DCHPRI30_DPA_SHIFT (6U)

Definition at line 15793 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_ECP

#define DMA_DCHPRI30_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15805 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_ECP_MASK

#define DMA_DCHPRI30_ECP_MASK (0x80U)

Definition at line 15799 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_ECP_SHIFT

#define DMA_DCHPRI30_ECP_SHIFT (7U)

Definition at line 15800 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_GRPPRI

#define DMA_DCHPRI30_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15791 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_GRPPRI_MASK

#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)

Definition at line 15787 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI30_GRPPRI_SHIFT

#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)

Definition at line 15788 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_CHPRI

#define DMA_DCHPRI31_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15758 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_CHPRI_MASK

#define DMA_DCHPRI31_CHPRI_MASK (0xFU)

Definition at line 15754 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_CHPRI_SHIFT

#define DMA_DCHPRI31_CHPRI_SHIFT (0U)

Definition at line 15755 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_DPA

#define DMA_DCHPRI31_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15770 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_DPA_MASK

#define DMA_DCHPRI31_DPA_MASK (0x40U)

Definition at line 15764 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_DPA_SHIFT

#define DMA_DCHPRI31_DPA_SHIFT (6U)

Definition at line 15765 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_ECP

#define DMA_DCHPRI31_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15777 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_ECP_MASK

#define DMA_DCHPRI31_ECP_MASK (0x80U)

Definition at line 15771 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_ECP_SHIFT

#define DMA_DCHPRI31_ECP_SHIFT (7U)

Definition at line 15772 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_GRPPRI

#define DMA_DCHPRI31_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15763 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_GRPPRI_MASK

#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)

Definition at line 15759 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI31_GRPPRI_SHIFT

#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)

Definition at line 15760 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_CHPRI

#define DMA_DCHPRI3_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 14974 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_CHPRI_MASK

#define DMA_DCHPRI3_CHPRI_MASK (0xFU)

Definition at line 14970 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_CHPRI_SHIFT

#define DMA_DCHPRI3_CHPRI_SHIFT (0U)

Definition at line 14971 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_DPA

#define DMA_DCHPRI3_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 14986 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_DPA_MASK

#define DMA_DCHPRI3_DPA_MASK (0x40U)

Definition at line 14980 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_DPA_SHIFT

#define DMA_DCHPRI3_DPA_SHIFT (6U)

Definition at line 14981 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_ECP

#define DMA_DCHPRI3_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 14993 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_ECP_MASK

#define DMA_DCHPRI3_ECP_MASK (0x80U)

Definition at line 14987 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_ECP_SHIFT

#define DMA_DCHPRI3_ECP_SHIFT (7U)

Definition at line 14988 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_GRPPRI

#define DMA_DCHPRI3_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 14979 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_GRPPRI_MASK

#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)

Definition at line 14975 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI3_GRPPRI_SHIFT

#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)

Definition at line 14976 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_CHPRI

#define DMA_DCHPRI4_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15170 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_CHPRI_MASK

#define DMA_DCHPRI4_CHPRI_MASK (0xFU)

Definition at line 15166 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_CHPRI_SHIFT

#define DMA_DCHPRI4_CHPRI_SHIFT (0U)

Definition at line 15167 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_DPA

#define DMA_DCHPRI4_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15182 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_DPA_MASK

#define DMA_DCHPRI4_DPA_MASK (0x40U)

Definition at line 15176 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_DPA_SHIFT

#define DMA_DCHPRI4_DPA_SHIFT (6U)

Definition at line 15177 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_ECP

#define DMA_DCHPRI4_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15189 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_ECP_MASK

#define DMA_DCHPRI4_ECP_MASK (0x80U)

Definition at line 15183 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_ECP_SHIFT

#define DMA_DCHPRI4_ECP_SHIFT (7U)

Definition at line 15184 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_GRPPRI

#define DMA_DCHPRI4_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15175 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_GRPPRI_MASK

#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)

Definition at line 15171 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI4_GRPPRI_SHIFT

#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)

Definition at line 15172 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_CHPRI

#define DMA_DCHPRI5_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15142 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_CHPRI_MASK

#define DMA_DCHPRI5_CHPRI_MASK (0xFU)

Definition at line 15138 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_CHPRI_SHIFT

#define DMA_DCHPRI5_CHPRI_SHIFT (0U)

Definition at line 15139 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_DPA

#define DMA_DCHPRI5_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15154 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_DPA_MASK

#define DMA_DCHPRI5_DPA_MASK (0x40U)

Definition at line 15148 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_DPA_SHIFT

#define DMA_DCHPRI5_DPA_SHIFT (6U)

Definition at line 15149 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_ECP

#define DMA_DCHPRI5_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15161 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_ECP_MASK

#define DMA_DCHPRI5_ECP_MASK (0x80U)

Definition at line 15155 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_ECP_SHIFT

#define DMA_DCHPRI5_ECP_SHIFT (7U)

Definition at line 15156 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_GRPPRI

#define DMA_DCHPRI5_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15147 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_GRPPRI_MASK

#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)

Definition at line 15143 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI5_GRPPRI_SHIFT

#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)

Definition at line 15144 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_CHPRI

#define DMA_DCHPRI6_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15114 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_CHPRI_MASK

#define DMA_DCHPRI6_CHPRI_MASK (0xFU)

Definition at line 15110 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_CHPRI_SHIFT

#define DMA_DCHPRI6_CHPRI_SHIFT (0U)

Definition at line 15111 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_DPA

#define DMA_DCHPRI6_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15126 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_DPA_MASK

#define DMA_DCHPRI6_DPA_MASK (0x40U)

Definition at line 15120 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_DPA_SHIFT

#define DMA_DCHPRI6_DPA_SHIFT (6U)

Definition at line 15121 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_ECP

#define DMA_DCHPRI6_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15133 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_ECP_MASK

#define DMA_DCHPRI6_ECP_MASK (0x80U)

Definition at line 15127 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_ECP_SHIFT

#define DMA_DCHPRI6_ECP_SHIFT (7U)

Definition at line 15128 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_GRPPRI

#define DMA_DCHPRI6_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15119 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_GRPPRI_MASK

#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)

Definition at line 15115 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI6_GRPPRI_SHIFT

#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)

Definition at line 15116 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_CHPRI

#define DMA_DCHPRI7_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15086 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_CHPRI_MASK

#define DMA_DCHPRI7_CHPRI_MASK (0xFU)

Definition at line 15082 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_CHPRI_SHIFT

#define DMA_DCHPRI7_CHPRI_SHIFT (0U)

Definition at line 15083 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_DPA

#define DMA_DCHPRI7_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15098 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_DPA_MASK

#define DMA_DCHPRI7_DPA_MASK (0x40U)

Definition at line 15092 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_DPA_SHIFT

#define DMA_DCHPRI7_DPA_SHIFT (6U)

Definition at line 15093 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_ECP

#define DMA_DCHPRI7_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15105 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_ECP_MASK

#define DMA_DCHPRI7_ECP_MASK (0x80U)

Definition at line 15099 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_ECP_SHIFT

#define DMA_DCHPRI7_ECP_SHIFT (7U)

Definition at line 15100 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_GRPPRI

#define DMA_DCHPRI7_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15091 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_GRPPRI_MASK

#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)

Definition at line 15087 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI7_GRPPRI_SHIFT

#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)

Definition at line 15088 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_CHPRI

#define DMA_DCHPRI8_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15282 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_CHPRI_MASK

#define DMA_DCHPRI8_CHPRI_MASK (0xFU)

Definition at line 15278 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_CHPRI_SHIFT

#define DMA_DCHPRI8_CHPRI_SHIFT (0U)

Definition at line 15279 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_DPA

#define DMA_DCHPRI8_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15294 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_DPA_MASK

#define DMA_DCHPRI8_DPA_MASK (0x40U)

Definition at line 15288 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_DPA_SHIFT

#define DMA_DCHPRI8_DPA_SHIFT (6U)

Definition at line 15289 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_ECP

#define DMA_DCHPRI8_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15301 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_ECP_MASK

#define DMA_DCHPRI8_ECP_MASK (0x80U)

Definition at line 15295 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_ECP_SHIFT

#define DMA_DCHPRI8_ECP_SHIFT (7U)

Definition at line 15296 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_GRPPRI

#define DMA_DCHPRI8_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15287 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_GRPPRI_MASK

#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)

Definition at line 15283 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI8_GRPPRI_SHIFT

#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)

Definition at line 15284 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_CHPRI

#define DMA_DCHPRI9_CHPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

Definition at line 15254 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_CHPRI_MASK

#define DMA_DCHPRI9_CHPRI_MASK (0xFU)

Definition at line 15250 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_CHPRI_SHIFT

#define DMA_DCHPRI9_CHPRI_SHIFT (0U)

Definition at line 15251 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_DPA

#define DMA_DCHPRI9_DPA | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

Definition at line 15266 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_DPA_MASK

#define DMA_DCHPRI9_DPA_MASK (0x40U)

Definition at line 15260 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_DPA_SHIFT

#define DMA_DCHPRI9_DPA_SHIFT (6U)

Definition at line 15261 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_ECP

#define DMA_DCHPRI9_ECP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

Definition at line 15273 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_ECP_MASK

#define DMA_DCHPRI9_ECP_MASK (0x80U)

Definition at line 15267 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_ECP_SHIFT

#define DMA_DCHPRI9_ECP_SHIFT (7U)

Definition at line 15268 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_GRPPRI

#define DMA_DCHPRI9_GRPPRI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

Definition at line 15259 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_GRPPRI_MASK

#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)

Definition at line 15255 of file MIMXRT1062.h.

## ◆ DMA_DCHPRI9_GRPPRI_SHIFT

#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)

Definition at line 15256 of file MIMXRT1062.h.

## ◆ DMA_DLAST_SGA_COUNT

#define DMA_DLAST_SGA_COUNT (32U)

Definition at line 16091 of file MIMXRT1062.h.

## ◆ DMA_DLAST_SGA_DLASTSGA

#define DMA_DLAST_SGA_DLASTSGA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

DLASTSGA - DLASTSGA

Definition at line 16087 of file MIMXRT1062.h.

## ◆ DMA_DLAST_SGA_DLASTSGA_MASK

#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)

Definition at line 16083 of file MIMXRT1062.h.

## ◆ DMA_DLAST_SGA_DLASTSGA_SHIFT

#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)

Definition at line 16084 of file MIMXRT1062.h.

## ◆ DMA_DOFF_COUNT

#define DMA_DOFF_COUNT (32U)

Definition at line 16036 of file MIMXRT1062.h.

## ◆ DMA_DOFF_DOFF

#define DMA_DOFF_DOFF | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

DOFF - Destination Address Signed Offset

Definition at line 16032 of file MIMXRT1062.h.

## ◆ DMA_DOFF_DOFF_MASK

#define DMA_DOFF_DOFF_MASK (0xFFFFU)

Definition at line 16028 of file MIMXRT1062.h.

## ◆ DMA_DOFF_DOFF_SHIFT

#define DMA_DOFF_DOFF_SHIFT (0U)

Definition at line 16029 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_0

#define DMA_EARS_EDREQ_0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 0b0..Disable asynchronous DMA request for channel 0. 0b1..Enable asynchronous DMA request for channel 0.

Definition at line 14748 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_0_MASK

#define DMA_EARS_EDREQ_0_MASK (0x1U)

Definition at line 14742 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_0_SHIFT

#define DMA_EARS_EDREQ_0_SHIFT (0U)

Definition at line 14743 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_1

#define DMA_EARS_EDREQ_1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 0b0..Disable asynchronous DMA request for channel 1 0b1..Enable asynchronous DMA request for channel 1.

Definition at line 14755 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_10

#define DMA_EARS_EDREQ_10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 0b0..Disable asynchronous DMA request for channel 10. 0b1..Enable asynchronous DMA request for channel 10.

Definition at line 14818 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_10_MASK

#define DMA_EARS_EDREQ_10_MASK (0x400U)

Definition at line 14812 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_10_SHIFT

#define DMA_EARS_EDREQ_10_SHIFT (10U)

Definition at line 14813 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_11

#define DMA_EARS_EDREQ_11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 0b0..Disable asynchronous DMA request for channel 11. 0b1..Enable asynchronous DMA request for channel 11.

Definition at line 14825 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_11_MASK

#define DMA_EARS_EDREQ_11_MASK (0x800U)

Definition at line 14819 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_11_SHIFT

#define DMA_EARS_EDREQ_11_SHIFT (11U)

Definition at line 14820 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_12

#define DMA_EARS_EDREQ_12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 0b0..Disable asynchronous DMA request for channel 12. 0b1..Enable asynchronous DMA request for channel 12.

Definition at line 14832 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_12_MASK

#define DMA_EARS_EDREQ_12_MASK (0x1000U)

Definition at line 14826 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_12_SHIFT

#define DMA_EARS_EDREQ_12_SHIFT (12U)

Definition at line 14827 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_13

#define DMA_EARS_EDREQ_13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 0b0..Disable asynchronous DMA request for channel 13. 0b1..Enable asynchronous DMA request for channel 13.

Definition at line 14839 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_13_MASK

#define DMA_EARS_EDREQ_13_MASK (0x2000U)

Definition at line 14833 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_13_SHIFT

#define DMA_EARS_EDREQ_13_SHIFT (13U)

Definition at line 14834 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_14

#define DMA_EARS_EDREQ_14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 0b0..Disable asynchronous DMA request for channel 14. 0b1..Enable asynchronous DMA request for channel 14.

Definition at line 14846 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_14_MASK

#define DMA_EARS_EDREQ_14_MASK (0x4000U)

Definition at line 14840 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_14_SHIFT

#define DMA_EARS_EDREQ_14_SHIFT (14U)

Definition at line 14841 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_15

#define DMA_EARS_EDREQ_15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 0b0..Disable asynchronous DMA request for channel 15. 0b1..Enable asynchronous DMA request for channel 15.

Definition at line 14853 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_15_MASK

#define DMA_EARS_EDREQ_15_MASK (0x8000U)

Definition at line 14847 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_15_SHIFT

#define DMA_EARS_EDREQ_15_SHIFT (15U)

Definition at line 14848 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_16

#define DMA_EARS_EDREQ_16 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 0b0..Disable asynchronous DMA request for channel 16 0b1..Enable asynchronous DMA request for channel 16

Definition at line 14860 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_16_MASK

#define DMA_EARS_EDREQ_16_MASK (0x10000U)

Definition at line 14854 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_16_SHIFT

#define DMA_EARS_EDREQ_16_SHIFT (16U)

Definition at line 14855 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_17

#define DMA_EARS_EDREQ_17 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 0b0..Disable asynchronous DMA request for channel 17 0b1..Enable asynchronous DMA request for channel 17

Definition at line 14867 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_17_MASK

#define DMA_EARS_EDREQ_17_MASK (0x20000U)

Definition at line 14861 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_17_SHIFT

#define DMA_EARS_EDREQ_17_SHIFT (17U)

Definition at line 14862 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_18

#define DMA_EARS_EDREQ_18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 0b0..Disable asynchronous DMA request for channel 18 0b1..Enable asynchronous DMA request for channel 18

Definition at line 14874 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_18_MASK

#define DMA_EARS_EDREQ_18_MASK (0x40000U)

Definition at line 14868 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_18_SHIFT

#define DMA_EARS_EDREQ_18_SHIFT (18U)

Definition at line 14869 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_19

#define DMA_EARS_EDREQ_19 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 0b0..Disable asynchronous DMA request for channel 19 0b1..Enable asynchronous DMA request for channel 19

Definition at line 14881 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_19_MASK

#define DMA_EARS_EDREQ_19_MASK (0x80000U)

Definition at line 14875 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_19_SHIFT

#define DMA_EARS_EDREQ_19_SHIFT (19U)

Definition at line 14876 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_1_MASK

#define DMA_EARS_EDREQ_1_MASK (0x2U)

Definition at line 14749 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_1_SHIFT

#define DMA_EARS_EDREQ_1_SHIFT (1U)

Definition at line 14750 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_2

#define DMA_EARS_EDREQ_2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 0b0..Disable asynchronous DMA request for channel 2. 0b1..Enable asynchronous DMA request for channel 2.

Definition at line 14762 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_20

#define DMA_EARS_EDREQ_20 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 0b0..Disable asynchronous DMA request for channel 20 0b1..Enable asynchronous DMA request for channel 20

Definition at line 14888 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_20_MASK

#define DMA_EARS_EDREQ_20_MASK (0x100000U)

Definition at line 14882 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_20_SHIFT

#define DMA_EARS_EDREQ_20_SHIFT (20U)

Definition at line 14883 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_21

#define DMA_EARS_EDREQ_21 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 0b0..Disable asynchronous DMA request for channel 21 0b1..Enable asynchronous DMA request for channel 21

Definition at line 14895 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_21_MASK

#define DMA_EARS_EDREQ_21_MASK (0x200000U)

Definition at line 14889 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_21_SHIFT

#define DMA_EARS_EDREQ_21_SHIFT (21U)

Definition at line 14890 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_22

#define DMA_EARS_EDREQ_22 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 0b0..Disable asynchronous DMA request for channel 22 0b1..Enable asynchronous DMA request for channel 22

Definition at line 14902 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_22_MASK

#define DMA_EARS_EDREQ_22_MASK (0x400000U)

Definition at line 14896 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_22_SHIFT

#define DMA_EARS_EDREQ_22_SHIFT (22U)

Definition at line 14897 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_23

#define DMA_EARS_EDREQ_23 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 0b0..Disable asynchronous DMA request for channel 23 0b1..Enable asynchronous DMA request for channel 23

Definition at line 14909 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_23_MASK

#define DMA_EARS_EDREQ_23_MASK (0x800000U)

Definition at line 14903 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_23_SHIFT

#define DMA_EARS_EDREQ_23_SHIFT (23U)

Definition at line 14904 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_24

#define DMA_EARS_EDREQ_24 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 0b0..Disable asynchronous DMA request for channel 24 0b1..Enable asynchronous DMA request for channel 24

Definition at line 14916 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_24_MASK

#define DMA_EARS_EDREQ_24_MASK (0x1000000U)

Definition at line 14910 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_24_SHIFT

#define DMA_EARS_EDREQ_24_SHIFT (24U)

Definition at line 14911 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_25

#define DMA_EARS_EDREQ_25 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 0b0..Disable asynchronous DMA request for channel 25 0b1..Enable asynchronous DMA request for channel 25

Definition at line 14923 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_25_MASK

#define DMA_EARS_EDREQ_25_MASK (0x2000000U)

Definition at line 14917 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_25_SHIFT

#define DMA_EARS_EDREQ_25_SHIFT (25U)

Definition at line 14918 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_26

#define DMA_EARS_EDREQ_26 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 0b0..Disable asynchronous DMA request for channel 26 0b1..Enable asynchronous DMA request for channel 26

Definition at line 14930 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_26_MASK

#define DMA_EARS_EDREQ_26_MASK (0x4000000U)

Definition at line 14924 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_26_SHIFT

#define DMA_EARS_EDREQ_26_SHIFT (26U)

Definition at line 14925 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_27

#define DMA_EARS_EDREQ_27 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 0b0..Disable asynchronous DMA request for channel 27 0b1..Enable asynchronous DMA request for channel 27

Definition at line 14937 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_27_MASK

#define DMA_EARS_EDREQ_27_MASK (0x8000000U)

Definition at line 14931 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_27_SHIFT

#define DMA_EARS_EDREQ_27_SHIFT (27U)

Definition at line 14932 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_28

#define DMA_EARS_EDREQ_28 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 0b0..Disable asynchronous DMA request for channel 28 0b1..Enable asynchronous DMA request for channel 28

Definition at line 14944 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_28_MASK

#define DMA_EARS_EDREQ_28_MASK (0x10000000U)

Definition at line 14938 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_28_SHIFT

#define DMA_EARS_EDREQ_28_SHIFT (28U)

Definition at line 14939 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_29

#define DMA_EARS_EDREQ_29 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 0b0..Disable asynchronous DMA request for channel 29 0b1..Enable asynchronous DMA request for channel 29

Definition at line 14951 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_29_MASK

#define DMA_EARS_EDREQ_29_MASK (0x20000000U)

Definition at line 14945 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_29_SHIFT

#define DMA_EARS_EDREQ_29_SHIFT (29U)

Definition at line 14946 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_2_MASK

#define DMA_EARS_EDREQ_2_MASK (0x4U)

Definition at line 14756 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_2_SHIFT

#define DMA_EARS_EDREQ_2_SHIFT (2U)

Definition at line 14757 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_3

#define DMA_EARS_EDREQ_3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 0b0..Disable asynchronous DMA request for channel 3. 0b1..Enable asynchronous DMA request for channel 3.

Definition at line 14769 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_30

#define DMA_EARS_EDREQ_30 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 0b0..Disable asynchronous DMA request for channel 30 0b1..Enable asynchronous DMA request for channel 30

Definition at line 14958 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_30_MASK

#define DMA_EARS_EDREQ_30_MASK (0x40000000U)

Definition at line 14952 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_30_SHIFT

#define DMA_EARS_EDREQ_30_SHIFT (30U)

Definition at line 14953 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_31

#define DMA_EARS_EDREQ_31 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 0b0..Disable asynchronous DMA request for channel 31 0b1..Enable asynchronous DMA request for channel 31

Definition at line 14965 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_31_MASK

#define DMA_EARS_EDREQ_31_MASK (0x80000000U)

Definition at line 14959 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_31_SHIFT

#define DMA_EARS_EDREQ_31_SHIFT (31U)

Definition at line 14960 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_3_MASK

#define DMA_EARS_EDREQ_3_MASK (0x8U)

Definition at line 14763 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_3_SHIFT

#define DMA_EARS_EDREQ_3_SHIFT (3U)

Definition at line 14764 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_4

#define DMA_EARS_EDREQ_4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 0b0..Disable asynchronous DMA request for channel 4. 0b1..Enable asynchronous DMA request for channel 4.

Definition at line 14776 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_4_MASK

#define DMA_EARS_EDREQ_4_MASK (0x10U)

Definition at line 14770 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_4_SHIFT

#define DMA_EARS_EDREQ_4_SHIFT (4U)

Definition at line 14771 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_5

#define DMA_EARS_EDREQ_5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 0b0..Disable asynchronous DMA request for channel 5. 0b1..Enable asynchronous DMA request for channel 5.

Definition at line 14783 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_5_MASK

#define DMA_EARS_EDREQ_5_MASK (0x20U)

Definition at line 14777 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_5_SHIFT

#define DMA_EARS_EDREQ_5_SHIFT (5U)

Definition at line 14778 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_6

#define DMA_EARS_EDREQ_6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 0b0..Disable asynchronous DMA request for channel 6. 0b1..Enable asynchronous DMA request for channel 6.

Definition at line 14790 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_6_MASK

#define DMA_EARS_EDREQ_6_MASK (0x40U)

Definition at line 14784 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_6_SHIFT

#define DMA_EARS_EDREQ_6_SHIFT (6U)

Definition at line 14785 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_7

#define DMA_EARS_EDREQ_7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 0b0..Disable asynchronous DMA request for channel 7. 0b1..Enable asynchronous DMA request for channel 7.

Definition at line 14797 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_7_MASK

#define DMA_EARS_EDREQ_7_MASK (0x80U)

Definition at line 14791 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_7_SHIFT

#define DMA_EARS_EDREQ_7_SHIFT (7U)

Definition at line 14792 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_8

#define DMA_EARS_EDREQ_8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 0b0..Disable asynchronous DMA request for channel 8. 0b1..Enable asynchronous DMA request for channel 8.

Definition at line 14804 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_8_MASK

#define DMA_EARS_EDREQ_8_MASK (0x100U)

Definition at line 14798 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_8_SHIFT

#define DMA_EARS_EDREQ_8_SHIFT (8U)

Definition at line 14799 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_9

#define DMA_EARS_EDREQ_9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 0b0..Disable asynchronous DMA request for channel 9. 0b1..Enable asynchronous DMA request for channel 9.

Definition at line 14811 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_9_MASK

#define DMA_EARS_EDREQ_9_MASK (0x200U)

Definition at line 14805 of file MIMXRT1062.h.

## ◆ DMA_EARS_EDREQ_9_SHIFT

#define DMA_EARS_EDREQ_9_SHIFT (9U)

Definition at line 14806 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI0

#define DMA_EEI_EEI0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13652 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI0_MASK

#define DMA_EEI_EEI0_MASK (0x1U)

Definition at line 13646 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI0_SHIFT

#define DMA_EEI_EEI0_SHIFT (0U)

Definition at line 13647 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI1

#define DMA_EEI_EEI1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13659 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI10

#define DMA_EEI_EEI10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13722 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI10_MASK

#define DMA_EEI_EEI10_MASK (0x400U)

Definition at line 13716 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI10_SHIFT

#define DMA_EEI_EEI10_SHIFT (10U)

Definition at line 13717 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI11

#define DMA_EEI_EEI11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13729 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI11_MASK

#define DMA_EEI_EEI11_MASK (0x800U)

Definition at line 13723 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI11_SHIFT

#define DMA_EEI_EEI11_SHIFT (11U)

Definition at line 13724 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI12

#define DMA_EEI_EEI12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13736 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI12_MASK

#define DMA_EEI_EEI12_MASK (0x1000U)

Definition at line 13730 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI12_SHIFT

#define DMA_EEI_EEI12_SHIFT (12U)

Definition at line 13731 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI13

#define DMA_EEI_EEI13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13743 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI13_MASK

#define DMA_EEI_EEI13_MASK (0x2000U)

Definition at line 13737 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI13_SHIFT

#define DMA_EEI_EEI13_SHIFT (13U)

Definition at line 13738 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI14

#define DMA_EEI_EEI14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13750 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI14_MASK

#define DMA_EEI_EEI14_MASK (0x4000U)

Definition at line 13744 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI14_SHIFT

#define DMA_EEI_EEI14_SHIFT (14U)

Definition at line 13745 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI15

#define DMA_EEI_EEI15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13757 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI15_MASK

#define DMA_EEI_EEI15_MASK (0x8000U)

Definition at line 13751 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI15_SHIFT

#define DMA_EEI_EEI15_SHIFT (15U)

Definition at line 13752 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI16

#define DMA_EEI_EEI16 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

EEI16 - Enable Error Interrupt 16 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13764 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI16_MASK

#define DMA_EEI_EEI16_MASK (0x10000U)

Definition at line 13758 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI16_SHIFT

#define DMA_EEI_EEI16_SHIFT (16U)

Definition at line 13759 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI17

#define DMA_EEI_EEI17 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

EEI17 - Enable Error Interrupt 17 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13771 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI17_MASK

#define DMA_EEI_EEI17_MASK (0x20000U)

Definition at line 13765 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI17_SHIFT

#define DMA_EEI_EEI17_SHIFT (17U)

Definition at line 13766 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI18

#define DMA_EEI_EEI18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

EEI18 - Enable Error Interrupt 18 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13778 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI18_MASK

#define DMA_EEI_EEI18_MASK (0x40000U)

Definition at line 13772 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI18_SHIFT

#define DMA_EEI_EEI18_SHIFT (18U)

Definition at line 13773 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI19

#define DMA_EEI_EEI19 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

EEI19 - Enable Error Interrupt 19 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13785 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI19_MASK

#define DMA_EEI_EEI19_MASK (0x80000U)

Definition at line 13779 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI19_SHIFT

#define DMA_EEI_EEI19_SHIFT (19U)

Definition at line 13780 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI1_MASK

#define DMA_EEI_EEI1_MASK (0x2U)

Definition at line 13653 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI1_SHIFT

#define DMA_EEI_EEI1_SHIFT (1U)

Definition at line 13654 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI2

#define DMA_EEI_EEI2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13666 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI20

#define DMA_EEI_EEI20 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

EEI20 - Enable Error Interrupt 20 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13792 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI20_MASK

#define DMA_EEI_EEI20_MASK (0x100000U)

Definition at line 13786 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI20_SHIFT

#define DMA_EEI_EEI20_SHIFT (20U)

Definition at line 13787 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI21

#define DMA_EEI_EEI21 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

EEI21 - Enable Error Interrupt 21 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13799 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI21_MASK

#define DMA_EEI_EEI21_MASK (0x200000U)

Definition at line 13793 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI21_SHIFT

#define DMA_EEI_EEI21_SHIFT (21U)

Definition at line 13794 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI22

#define DMA_EEI_EEI22 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

EEI22 - Enable Error Interrupt 22 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13806 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI22_MASK

#define DMA_EEI_EEI22_MASK (0x400000U)

Definition at line 13800 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI22_SHIFT

#define DMA_EEI_EEI22_SHIFT (22U)

Definition at line 13801 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI23

#define DMA_EEI_EEI23 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

EEI23 - Enable Error Interrupt 23 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13813 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI23_MASK

#define DMA_EEI_EEI23_MASK (0x800000U)

Definition at line 13807 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI23_SHIFT

#define DMA_EEI_EEI23_SHIFT (23U)

Definition at line 13808 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI24

#define DMA_EEI_EEI24 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

EEI24 - Enable Error Interrupt 24 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13820 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI24_MASK

#define DMA_EEI_EEI24_MASK (0x1000000U)

Definition at line 13814 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI24_SHIFT

#define DMA_EEI_EEI24_SHIFT (24U)

Definition at line 13815 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI25

#define DMA_EEI_EEI25 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

EEI25 - Enable Error Interrupt 25 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13827 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI25_MASK

#define DMA_EEI_EEI25_MASK (0x2000000U)

Definition at line 13821 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI25_SHIFT

#define DMA_EEI_EEI25_SHIFT (25U)

Definition at line 13822 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI26

#define DMA_EEI_EEI26 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

EEI26 - Enable Error Interrupt 26 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13834 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI26_MASK

#define DMA_EEI_EEI26_MASK (0x4000000U)

Definition at line 13828 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI26_SHIFT

#define DMA_EEI_EEI26_SHIFT (26U)

Definition at line 13829 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI27

#define DMA_EEI_EEI27 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

EEI27 - Enable Error Interrupt 27 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13841 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI27_MASK

#define DMA_EEI_EEI27_MASK (0x8000000U)

Definition at line 13835 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI27_SHIFT

#define DMA_EEI_EEI27_SHIFT (27U)

Definition at line 13836 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI28

#define DMA_EEI_EEI28 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

EEI28 - Enable Error Interrupt 28 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13848 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI28_MASK

#define DMA_EEI_EEI28_MASK (0x10000000U)

Definition at line 13842 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI28_SHIFT

#define DMA_EEI_EEI28_SHIFT (28U)

Definition at line 13843 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI29

#define DMA_EEI_EEI29 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

EEI29 - Enable Error Interrupt 29 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13855 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI29_MASK

#define DMA_EEI_EEI29_MASK (0x20000000U)

Definition at line 13849 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI29_SHIFT

#define DMA_EEI_EEI29_SHIFT (29U)

Definition at line 13850 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI2_MASK

#define DMA_EEI_EEI2_MASK (0x4U)

Definition at line 13660 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI2_SHIFT

#define DMA_EEI_EEI2_SHIFT (2U)

Definition at line 13661 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI3

#define DMA_EEI_EEI3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13673 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI30

#define DMA_EEI_EEI30 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

EEI30 - Enable Error Interrupt 30 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13862 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI30_MASK

#define DMA_EEI_EEI30_MASK (0x40000000U)

Definition at line 13856 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI30_SHIFT

#define DMA_EEI_EEI30_SHIFT (30U)

Definition at line 13857 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI31

#define DMA_EEI_EEI31 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

EEI31 - Enable Error Interrupt 31 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13869 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI31_MASK

#define DMA_EEI_EEI31_MASK (0x80000000U)

Definition at line 13863 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI31_SHIFT

#define DMA_EEI_EEI31_SHIFT (31U)

Definition at line 13864 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI3_MASK

#define DMA_EEI_EEI3_MASK (0x8U)

Definition at line 13667 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI3_SHIFT

#define DMA_EEI_EEI3_SHIFT (3U)

Definition at line 13668 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI4

#define DMA_EEI_EEI4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13680 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI4_MASK

#define DMA_EEI_EEI4_MASK (0x10U)

Definition at line 13674 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI4_SHIFT

#define DMA_EEI_EEI4_SHIFT (4U)

Definition at line 13675 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI5

#define DMA_EEI_EEI5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13687 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI5_MASK

#define DMA_EEI_EEI5_MASK (0x20U)

Definition at line 13681 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI5_SHIFT

#define DMA_EEI_EEI5_SHIFT (5U)

Definition at line 13682 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI6

#define DMA_EEI_EEI6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13694 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI6_MASK

#define DMA_EEI_EEI6_MASK (0x40U)

Definition at line 13688 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI6_SHIFT

#define DMA_EEI_EEI6_SHIFT (6U)

Definition at line 13689 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI7

#define DMA_EEI_EEI7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13701 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI7_MASK

#define DMA_EEI_EEI7_MASK (0x80U)

Definition at line 13695 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI7_SHIFT

#define DMA_EEI_EEI7_SHIFT (7U)

Definition at line 13696 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI8

#define DMA_EEI_EEI8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13708 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI8_MASK

#define DMA_EEI_EEI8_MASK (0x100U)

Definition at line 13702 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI8_SHIFT

#define DMA_EEI_EEI8_SHIFT (8U)

Definition at line 13703 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI9

#define DMA_EEI_EEI9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

Definition at line 13715 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI9_MASK

#define DMA_EEI_EEI9_MASK (0x200U)

Definition at line 13709 of file MIMXRT1062.h.

## ◆ DMA_EEI_EEI9_SHIFT

#define DMA_EEI_EEI9_SHIFT (9U)

Definition at line 13710 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ0

#define DMA_ERQ_ERQ0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13424 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ0_MASK

#define DMA_ERQ_ERQ0_MASK (0x1U)

Definition at line 13418 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ0_SHIFT

#define DMA_ERQ_ERQ0_SHIFT (0U)

Definition at line 13419 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ1

#define DMA_ERQ_ERQ1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13431 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ10

#define DMA_ERQ_ERQ10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13494 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ10_MASK

#define DMA_ERQ_ERQ10_MASK (0x400U)

Definition at line 13488 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ10_SHIFT

#define DMA_ERQ_ERQ10_SHIFT (10U)

Definition at line 13489 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ11

#define DMA_ERQ_ERQ11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13501 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ11_MASK

#define DMA_ERQ_ERQ11_MASK (0x800U)

Definition at line 13495 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ11_SHIFT

#define DMA_ERQ_ERQ11_SHIFT (11U)

Definition at line 13496 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ12

#define DMA_ERQ_ERQ12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13508 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ12_MASK

#define DMA_ERQ_ERQ12_MASK (0x1000U)

Definition at line 13502 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ12_SHIFT

#define DMA_ERQ_ERQ12_SHIFT (12U)

Definition at line 13503 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ13

#define DMA_ERQ_ERQ13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13515 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ13_MASK

#define DMA_ERQ_ERQ13_MASK (0x2000U)

Definition at line 13509 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ13_SHIFT

#define DMA_ERQ_ERQ13_SHIFT (13U)

Definition at line 13510 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ14

#define DMA_ERQ_ERQ14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13522 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ14_MASK

#define DMA_ERQ_ERQ14_MASK (0x4000U)

Definition at line 13516 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ14_SHIFT

#define DMA_ERQ_ERQ14_SHIFT (14U)

Definition at line 13517 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ15

#define DMA_ERQ_ERQ15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13529 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ15_MASK

#define DMA_ERQ_ERQ15_MASK (0x8000U)

Definition at line 13523 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ15_SHIFT

#define DMA_ERQ_ERQ15_SHIFT (15U)

Definition at line 13524 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ16

#define DMA_ERQ_ERQ16 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

ERQ16 - Enable DMA Request 16 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13536 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ16_MASK

#define DMA_ERQ_ERQ16_MASK (0x10000U)

Definition at line 13530 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ16_SHIFT

#define DMA_ERQ_ERQ16_SHIFT (16U)

Definition at line 13531 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ17

#define DMA_ERQ_ERQ17 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

ERQ17 - Enable DMA Request 17 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13543 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ17_MASK

#define DMA_ERQ_ERQ17_MASK (0x20000U)

Definition at line 13537 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ17_SHIFT

#define DMA_ERQ_ERQ17_SHIFT (17U)

Definition at line 13538 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ18

#define DMA_ERQ_ERQ18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

ERQ18 - Enable DMA Request 18 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13550 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ18_MASK

#define DMA_ERQ_ERQ18_MASK (0x40000U)

Definition at line 13544 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ18_SHIFT

#define DMA_ERQ_ERQ18_SHIFT (18U)

Definition at line 13545 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ19

#define DMA_ERQ_ERQ19 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

ERQ19 - Enable DMA Request 19 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13557 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ19_MASK

#define DMA_ERQ_ERQ19_MASK (0x80000U)

Definition at line 13551 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ19_SHIFT

#define DMA_ERQ_ERQ19_SHIFT (19U)

Definition at line 13552 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ1_MASK

#define DMA_ERQ_ERQ1_MASK (0x2U)

Definition at line 13425 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ1_SHIFT

#define DMA_ERQ_ERQ1_SHIFT (1U)

Definition at line 13426 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ2

#define DMA_ERQ_ERQ2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13438 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ20

#define DMA_ERQ_ERQ20 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

ERQ20 - Enable DMA Request 20 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13564 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ20_MASK

#define DMA_ERQ_ERQ20_MASK (0x100000U)

Definition at line 13558 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ20_SHIFT

#define DMA_ERQ_ERQ20_SHIFT (20U)

Definition at line 13559 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ21

#define DMA_ERQ_ERQ21 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

ERQ21 - Enable DMA Request 21 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13571 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ21_MASK

#define DMA_ERQ_ERQ21_MASK (0x200000U)

Definition at line 13565 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ21_SHIFT

#define DMA_ERQ_ERQ21_SHIFT (21U)

Definition at line 13566 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ22

#define DMA_ERQ_ERQ22 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

ERQ22 - Enable DMA Request 22 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13578 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ22_MASK

#define DMA_ERQ_ERQ22_MASK (0x400000U)

Definition at line 13572 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ22_SHIFT

#define DMA_ERQ_ERQ22_SHIFT (22U)

Definition at line 13573 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ23

#define DMA_ERQ_ERQ23 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

ERQ23 - Enable DMA Request 23 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13585 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ23_MASK

#define DMA_ERQ_ERQ23_MASK (0x800000U)

Definition at line 13579 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ23_SHIFT

#define DMA_ERQ_ERQ23_SHIFT (23U)

Definition at line 13580 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ24

#define DMA_ERQ_ERQ24 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

ERQ24 - Enable DMA Request 24 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13592 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ24_MASK

#define DMA_ERQ_ERQ24_MASK (0x1000000U)

Definition at line 13586 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ24_SHIFT

#define DMA_ERQ_ERQ24_SHIFT (24U)

Definition at line 13587 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ25

#define DMA_ERQ_ERQ25 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

ERQ25 - Enable DMA Request 25 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13599 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ25_MASK

#define DMA_ERQ_ERQ25_MASK (0x2000000U)

Definition at line 13593 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ25_SHIFT

#define DMA_ERQ_ERQ25_SHIFT (25U)

Definition at line 13594 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ26

#define DMA_ERQ_ERQ26 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

ERQ26 - Enable DMA Request 26 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13606 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ26_MASK

#define DMA_ERQ_ERQ26_MASK (0x4000000U)

Definition at line 13600 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ26_SHIFT

#define DMA_ERQ_ERQ26_SHIFT (26U)

Definition at line 13601 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ27

#define DMA_ERQ_ERQ27 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

ERQ27 - Enable DMA Request 27 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13613 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ27_MASK

#define DMA_ERQ_ERQ27_MASK (0x8000000U)

Definition at line 13607 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ27_SHIFT

#define DMA_ERQ_ERQ27_SHIFT (27U)

Definition at line 13608 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ28

#define DMA_ERQ_ERQ28 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

ERQ28 - Enable DMA Request 28 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13620 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ28_MASK

#define DMA_ERQ_ERQ28_MASK (0x10000000U)

Definition at line 13614 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ28_SHIFT

#define DMA_ERQ_ERQ28_SHIFT (28U)

Definition at line 13615 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ29

#define DMA_ERQ_ERQ29 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

ERQ29 - Enable DMA Request 29 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13627 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ29_MASK

#define DMA_ERQ_ERQ29_MASK (0x20000000U)

Definition at line 13621 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ29_SHIFT

#define DMA_ERQ_ERQ29_SHIFT (29U)

Definition at line 13622 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ2_MASK

#define DMA_ERQ_ERQ2_MASK (0x4U)

Definition at line 13432 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ2_SHIFT

#define DMA_ERQ_ERQ2_SHIFT (2U)

Definition at line 13433 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ3

#define DMA_ERQ_ERQ3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13445 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ30

#define DMA_ERQ_ERQ30 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

ERQ30 - Enable DMA Request 30 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13634 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ30_MASK

#define DMA_ERQ_ERQ30_MASK (0x40000000U)

Definition at line 13628 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ30_SHIFT

#define DMA_ERQ_ERQ30_SHIFT (30U)

Definition at line 13629 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ31

#define DMA_ERQ_ERQ31 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

ERQ31 - Enable DMA Request 31 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13641 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ31_MASK

#define DMA_ERQ_ERQ31_MASK (0x80000000U)

Definition at line 13635 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ31_SHIFT

#define DMA_ERQ_ERQ31_SHIFT (31U)

Definition at line 13636 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ3_MASK

#define DMA_ERQ_ERQ3_MASK (0x8U)

Definition at line 13439 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ3_SHIFT

#define DMA_ERQ_ERQ3_SHIFT (3U)

Definition at line 13440 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ4

#define DMA_ERQ_ERQ4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13452 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ4_MASK

#define DMA_ERQ_ERQ4_MASK (0x10U)

Definition at line 13446 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ4_SHIFT

#define DMA_ERQ_ERQ4_SHIFT (4U)

Definition at line 13447 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ5

#define DMA_ERQ_ERQ5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13459 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ5_MASK

#define DMA_ERQ_ERQ5_MASK (0x20U)

Definition at line 13453 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ5_SHIFT

#define DMA_ERQ_ERQ5_SHIFT (5U)

Definition at line 13454 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ6

#define DMA_ERQ_ERQ6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13466 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ6_MASK

#define DMA_ERQ_ERQ6_MASK (0x40U)

Definition at line 13460 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ6_SHIFT

#define DMA_ERQ_ERQ6_SHIFT (6U)

Definition at line 13461 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ7

#define DMA_ERQ_ERQ7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13473 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ7_MASK

#define DMA_ERQ_ERQ7_MASK (0x80U)

Definition at line 13467 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ7_SHIFT

#define DMA_ERQ_ERQ7_SHIFT (7U)

Definition at line 13468 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ8

#define DMA_ERQ_ERQ8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13480 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ8_MASK

#define DMA_ERQ_ERQ8_MASK (0x100U)

Definition at line 13474 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ8_SHIFT

#define DMA_ERQ_ERQ8_SHIFT (8U)

Definition at line 13475 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ9

#define DMA_ERQ_ERQ9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

Definition at line 13487 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ9_MASK

#define DMA_ERQ_ERQ9_MASK (0x200U)

Definition at line 13481 of file MIMXRT1062.h.

## ◆ DMA_ERQ_ERQ9_SHIFT

#define DMA_ERQ_ERQ9_SHIFT (9U)

Definition at line 13482 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR0

#define DMA_ERR_ERR0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14292 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR0_MASK

#define DMA_ERR_ERR0_MASK (0x1U)

Definition at line 14286 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR0_SHIFT

#define DMA_ERR_ERR0_SHIFT (0U)

Definition at line 14287 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR1

#define DMA_ERR_ERR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14299 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR10

#define DMA_ERR_ERR10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14362 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR10_MASK

#define DMA_ERR_ERR10_MASK (0x400U)

Definition at line 14356 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR10_SHIFT

#define DMA_ERR_ERR10_SHIFT (10U)

Definition at line 14357 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR11

#define DMA_ERR_ERR11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14369 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR11_MASK

#define DMA_ERR_ERR11_MASK (0x800U)

Definition at line 14363 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR11_SHIFT

#define DMA_ERR_ERR11_SHIFT (11U)

Definition at line 14364 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR12

#define DMA_ERR_ERR12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14376 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR12_MASK

#define DMA_ERR_ERR12_MASK (0x1000U)

Definition at line 14370 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR12_SHIFT

#define DMA_ERR_ERR12_SHIFT (12U)

Definition at line 14371 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR13

#define DMA_ERR_ERR13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14383 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR13_MASK

#define DMA_ERR_ERR13_MASK (0x2000U)

Definition at line 14377 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR13_SHIFT

#define DMA_ERR_ERR13_SHIFT (13U)

Definition at line 14378 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR14

#define DMA_ERR_ERR14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14390 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR14_MASK

#define DMA_ERR_ERR14_MASK (0x4000U)

Definition at line 14384 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR14_SHIFT

#define DMA_ERR_ERR14_SHIFT (14U)

Definition at line 14385 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR15

#define DMA_ERR_ERR15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14397 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR15_MASK

#define DMA_ERR_ERR15_MASK (0x8000U)

Definition at line 14391 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR15_SHIFT

#define DMA_ERR_ERR15_SHIFT (15U)

Definition at line 14392 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR16

#define DMA_ERR_ERR16 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

ERR16 - Error In Channel 16 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14404 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR16_MASK

#define DMA_ERR_ERR16_MASK (0x10000U)

Definition at line 14398 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR16_SHIFT

#define DMA_ERR_ERR16_SHIFT (16U)

Definition at line 14399 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR17

#define DMA_ERR_ERR17 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

ERR17 - Error In Channel 17 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14411 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR17_MASK

#define DMA_ERR_ERR17_MASK (0x20000U)

Definition at line 14405 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR17_SHIFT

#define DMA_ERR_ERR17_SHIFT (17U)

Definition at line 14406 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR18

#define DMA_ERR_ERR18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

ERR18 - Error In Channel 18 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14418 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR18_MASK

#define DMA_ERR_ERR18_MASK (0x40000U)

Definition at line 14412 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR18_SHIFT

#define DMA_ERR_ERR18_SHIFT (18U)

Definition at line 14413 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR19

#define DMA_ERR_ERR19 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

ERR19 - Error In Channel 19 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14425 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR19_MASK

#define DMA_ERR_ERR19_MASK (0x80000U)

Definition at line 14419 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR19_SHIFT

#define DMA_ERR_ERR19_SHIFT (19U)

Definition at line 14420 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR1_MASK

#define DMA_ERR_ERR1_MASK (0x2U)

Definition at line 14293 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR1_SHIFT

#define DMA_ERR_ERR1_SHIFT (1U)

Definition at line 14294 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR2

#define DMA_ERR_ERR2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14306 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR20

#define DMA_ERR_ERR20 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

ERR20 - Error In Channel 20 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14432 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR20_MASK

#define DMA_ERR_ERR20_MASK (0x100000U)

Definition at line 14426 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR20_SHIFT

#define DMA_ERR_ERR20_SHIFT (20U)

Definition at line 14427 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR21

#define DMA_ERR_ERR21 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

ERR21 - Error In Channel 21 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14439 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR21_MASK

#define DMA_ERR_ERR21_MASK (0x200000U)

Definition at line 14433 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR21_SHIFT

#define DMA_ERR_ERR21_SHIFT (21U)

Definition at line 14434 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR22

#define DMA_ERR_ERR22 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

ERR22 - Error In Channel 22 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14446 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR22_MASK

#define DMA_ERR_ERR22_MASK (0x400000U)

Definition at line 14440 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR22_SHIFT

#define DMA_ERR_ERR22_SHIFT (22U)

Definition at line 14441 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR23

#define DMA_ERR_ERR23 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

ERR23 - Error In Channel 23 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14453 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR23_MASK

#define DMA_ERR_ERR23_MASK (0x800000U)

Definition at line 14447 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR23_SHIFT

#define DMA_ERR_ERR23_SHIFT (23U)

Definition at line 14448 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR24

#define DMA_ERR_ERR24 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

ERR24 - Error In Channel 24 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14460 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR24_MASK

#define DMA_ERR_ERR24_MASK (0x1000000U)

Definition at line 14454 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR24_SHIFT

#define DMA_ERR_ERR24_SHIFT (24U)

Definition at line 14455 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR25

#define DMA_ERR_ERR25 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

ERR25 - Error In Channel 25 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14467 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR25_MASK

#define DMA_ERR_ERR25_MASK (0x2000000U)

Definition at line 14461 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR25_SHIFT

#define DMA_ERR_ERR25_SHIFT (25U)

Definition at line 14462 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR26

#define DMA_ERR_ERR26 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

ERR26 - Error In Channel 26 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14474 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR26_MASK

#define DMA_ERR_ERR26_MASK (0x4000000U)

Definition at line 14468 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR26_SHIFT

#define DMA_ERR_ERR26_SHIFT (26U)

Definition at line 14469 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR27

#define DMA_ERR_ERR27 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

ERR27 - Error In Channel 27 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14481 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR27_MASK

#define DMA_ERR_ERR27_MASK (0x8000000U)

Definition at line 14475 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR27_SHIFT

#define DMA_ERR_ERR27_SHIFT (27U)

Definition at line 14476 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR28

#define DMA_ERR_ERR28 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

ERR28 - Error In Channel 28 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14488 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR28_MASK

#define DMA_ERR_ERR28_MASK (0x10000000U)

Definition at line 14482 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR28_SHIFT

#define DMA_ERR_ERR28_SHIFT (28U)

Definition at line 14483 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR29

#define DMA_ERR_ERR29 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

ERR29 - Error In Channel 29 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14495 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR29_MASK

#define DMA_ERR_ERR29_MASK (0x20000000U)

Definition at line 14489 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR29_SHIFT

#define DMA_ERR_ERR29_SHIFT (29U)

Definition at line 14490 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR2_MASK

#define DMA_ERR_ERR2_MASK (0x4U)

Definition at line 14300 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR2_SHIFT

#define DMA_ERR_ERR2_SHIFT (2U)

Definition at line 14301 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR3

#define DMA_ERR_ERR3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14313 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR30

#define DMA_ERR_ERR30 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

ERR30 - Error In Channel 30 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14502 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR30_MASK

#define DMA_ERR_ERR30_MASK (0x40000000U)

Definition at line 14496 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR30_SHIFT

#define DMA_ERR_ERR30_SHIFT (30U)

Definition at line 14497 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR31

#define DMA_ERR_ERR31 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

ERR31 - Error In Channel 31 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14509 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR31_MASK

#define DMA_ERR_ERR31_MASK (0x80000000U)

Definition at line 14503 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR31_SHIFT

#define DMA_ERR_ERR31_SHIFT (31U)

Definition at line 14504 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR3_MASK

#define DMA_ERR_ERR3_MASK (0x8U)

Definition at line 14307 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR3_SHIFT

#define DMA_ERR_ERR3_SHIFT (3U)

Definition at line 14308 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR4

#define DMA_ERR_ERR4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14320 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR4_MASK

#define DMA_ERR_ERR4_MASK (0x10U)

Definition at line 14314 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR4_SHIFT

#define DMA_ERR_ERR4_SHIFT (4U)

Definition at line 14315 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR5

#define DMA_ERR_ERR5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14327 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR5_MASK

#define DMA_ERR_ERR5_MASK (0x20U)

Definition at line 14321 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR5_SHIFT

#define DMA_ERR_ERR5_SHIFT (5U)

Definition at line 14322 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR6

#define DMA_ERR_ERR6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14334 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR6_MASK

#define DMA_ERR_ERR6_MASK (0x40U)

Definition at line 14328 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR6_SHIFT

#define DMA_ERR_ERR6_SHIFT (6U)

Definition at line 14329 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR7

#define DMA_ERR_ERR7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14341 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR7_MASK

#define DMA_ERR_ERR7_MASK (0x80U)

Definition at line 14335 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR7_SHIFT

#define DMA_ERR_ERR7_SHIFT (7U)

Definition at line 14336 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR8

#define DMA_ERR_ERR8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14348 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR8_MASK

#define DMA_ERR_ERR8_MASK (0x100U)

Definition at line 14342 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR8_SHIFT

#define DMA_ERR_ERR8_SHIFT (8U)

Definition at line 14343 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR9

#define DMA_ERR_ERR9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

Definition at line 14355 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR9_MASK

#define DMA_ERR_ERR9_MASK (0x200U)

Definition at line 14349 of file MIMXRT1062.h.

## ◆ DMA_ERR_ERR9_SHIFT

#define DMA_ERR_ERR9_SHIFT (9U)

Definition at line 14350 of file MIMXRT1062.h.

## ◆ DMA_ES_CPE

#define DMA_ES_CPE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

Definition at line 13392 of file MIMXRT1062.h.

## ◆ DMA_ES_CPE_MASK

#define DMA_ES_CPE_MASK (0x4000U)

Definition at line 13385 of file MIMXRT1062.h.

## ◆ DMA_ES_CPE_SHIFT

#define DMA_ES_CPE_SHIFT (14U)

Definition at line 13386 of file MIMXRT1062.h.

## ◆ DMA_ES_DAE

#define DMA_ES_DAE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

Definition at line 13365 of file MIMXRT1062.h.

## ◆ DMA_ES_DAE_MASK

#define DMA_ES_DAE_MASK (0x20U)

Definition at line 13359 of file MIMXRT1062.h.

## ◆ DMA_ES_DAE_SHIFT

#define DMA_ES_DAE_SHIFT (5U)

Definition at line 13360 of file MIMXRT1062.h.

## ◆ DMA_ES_DBE

#define DMA_ES_DBE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error 0b1..The last recorded error was a bus error on a destination write

Definition at line 13326 of file MIMXRT1062.h.

## ◆ DMA_ES_DBE_MASK

#define DMA_ES_DBE_MASK (0x1U)

Definition at line 13320 of file MIMXRT1062.h.

## ◆ DMA_ES_DBE_SHIFT

#define DMA_ES_DBE_SHIFT (0U)

Definition at line 13321 of file MIMXRT1062.h.

## ◆ DMA_ES_DOE

#define DMA_ES_DOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

Definition at line 13358 of file MIMXRT1062.h.

## ◆ DMA_ES_DOE_MASK

#define DMA_ES_DOE_MASK (0x10U)

Definition at line 13352 of file MIMXRT1062.h.

## ◆ DMA_ES_DOE_SHIFT

#define DMA_ES_DOE_SHIFT (4U)

Definition at line 13353 of file MIMXRT1062.h.

## ◆ DMA_ES_ECX

#define DMA_ES_ECX | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input

Definition at line 13406 of file MIMXRT1062.h.

## ◆ DMA_ES_ECX_MASK

#define DMA_ES_ECX_MASK (0x10000U)

Definition at line 13400 of file MIMXRT1062.h.

## ◆ DMA_ES_ECX_SHIFT

#define DMA_ES_ECX_SHIFT (16U)

Definition at line 13401 of file MIMXRT1062.h.

## ◆ DMA_ES_ERRCHN

#define DMA_ES_ERRCHN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

ERRCHN - Error Channel Number or Canceled Channel Number

Definition at line 13384 of file MIMXRT1062.h.

## ◆ DMA_ES_ERRCHN_MASK

#define DMA_ES_ERRCHN_MASK (0x1F00U)

Definition at line 13380 of file MIMXRT1062.h.

## ◆ DMA_ES_ERRCHN_SHIFT

#define DMA_ES_ERRCHN_SHIFT (8U)

Definition at line 13381 of file MIMXRT1062.h.

## ◆ DMA_ES_GPE

#define DMA_ES_GPE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

GPE - Group Priority Error 0b0..No group priority error 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.

Definition at line 13399 of file MIMXRT1062.h.

## ◆ DMA_ES_GPE_MASK

#define DMA_ES_GPE_MASK (0x8000U)

Definition at line 13393 of file MIMXRT1062.h.

## ◆ DMA_ES_GPE_SHIFT

#define DMA_ES_GPE_SHIFT (15U)

Definition at line 13394 of file MIMXRT1062.h.

## ◆ DMA_ES_NCE

#define DMA_ES_NCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]

Definition at line 13351 of file MIMXRT1062.h.

## ◆ DMA_ES_NCE_MASK

#define DMA_ES_NCE_MASK (0x8U)

Definition at line 13343 of file MIMXRT1062.h.

## ◆ DMA_ES_NCE_SHIFT

#define DMA_ES_NCE_SHIFT (3U)

Definition at line 13344 of file MIMXRT1062.h.

## ◆ DMA_ES_SAE

#define DMA_ES_SAE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

Definition at line 13379 of file MIMXRT1062.h.

## ◆ DMA_ES_SAE_MASK

#define DMA_ES_SAE_MASK (0x80U)

Definition at line 13373 of file MIMXRT1062.h.

## ◆ DMA_ES_SAE_SHIFT

#define DMA_ES_SAE_SHIFT (7U)

Definition at line 13374 of file MIMXRT1062.h.

## ◆ DMA_ES_SBE

#define DMA_ES_SBE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error 0b1..The last recorded error was a bus error on a source read

Definition at line 13333 of file MIMXRT1062.h.

## ◆ DMA_ES_SBE_MASK

#define DMA_ES_SBE_MASK (0x2U)

Definition at line 13327 of file MIMXRT1062.h.

## ◆ DMA_ES_SBE_SHIFT

#define DMA_ES_SBE_SHIFT (1U)

Definition at line 13328 of file MIMXRT1062.h.

## ◆ DMA_ES_SGE

#define DMA_ES_SGE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.

Definition at line 13342 of file MIMXRT1062.h.

## ◆ DMA_ES_SGE_MASK

#define DMA_ES_SGE_MASK (0x4U)

Definition at line 13334 of file MIMXRT1062.h.

## ◆ DMA_ES_SGE_SHIFT

#define DMA_ES_SGE_SHIFT (2U)

Definition at line 13335 of file MIMXRT1062.h.

## ◆ DMA_ES_SOE

#define DMA_ES_SOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

Definition at line 13372 of file MIMXRT1062.h.

## ◆ DMA_ES_SOE_MASK

#define DMA_ES_SOE_MASK (0x40U)

Definition at line 13366 of file MIMXRT1062.h.

## ◆ DMA_ES_SOE_SHIFT

#define DMA_ES_SOE_SHIFT (6U)

Definition at line 13367 of file MIMXRT1062.h.

## ◆ DMA_ES_VLD

#define DMA_ES_VLD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD - VLD 0b0..No ERR bits are set. 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.

Definition at line 13413 of file MIMXRT1062.h.

## ◆ DMA_ES_VLD_MASK

#define DMA_ES_VLD_MASK (0x80000000U)

Definition at line 13407 of file MIMXRT1062.h.

## ◆ DMA_ES_VLD_SHIFT

#define DMA_ES_VLD_SHIFT (31U)

Definition at line 13408 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS0

#define DMA_HRS_HRS0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

Definition at line 14520 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS0_MASK

#define DMA_HRS_HRS0_MASK (0x1U)

Definition at line 14514 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS0_SHIFT

#define DMA_HRS_HRS0_SHIFT (0U)

Definition at line 14515 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS1

#define DMA_HRS_HRS1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

Definition at line 14527 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS10

#define DMA_HRS_HRS10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

Definition at line 14590 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS10_MASK

#define DMA_HRS_HRS10_MASK (0x400U)

Definition at line 14584 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS10_SHIFT

#define DMA_HRS_HRS10_SHIFT (10U)

Definition at line 14585 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS11

#define DMA_HRS_HRS11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

Definition at line 14597 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS11_MASK

#define DMA_HRS_HRS11_MASK (0x800U)

Definition at line 14591 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS11_SHIFT

#define DMA_HRS_HRS11_SHIFT (11U)

Definition at line 14592 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS12

#define DMA_HRS_HRS12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

Definition at line 14604 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS12_MASK

#define DMA_HRS_HRS12_MASK (0x1000U)

Definition at line 14598 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS12_SHIFT

#define DMA_HRS_HRS12_SHIFT (12U)

Definition at line 14599 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS13

#define DMA_HRS_HRS13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

Definition at line 14611 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS13_MASK

#define DMA_HRS_HRS13_MASK (0x2000U)

Definition at line 14605 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS13_SHIFT

#define DMA_HRS_HRS13_SHIFT (13U)

Definition at line 14606 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS14

#define DMA_HRS_HRS14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

Definition at line 14618 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS14_MASK

#define DMA_HRS_HRS14_MASK (0x4000U)

Definition at line 14612 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS14_SHIFT

#define DMA_HRS_HRS14_SHIFT (14U)

Definition at line 14613 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS15

#define DMA_HRS_HRS15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

Definition at line 14625 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS15_MASK

#define DMA_HRS_HRS15_MASK (0x8000U)

Definition at line 14619 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS15_SHIFT

#define DMA_HRS_HRS15_SHIFT (15U)

Definition at line 14620 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS16

#define DMA_HRS_HRS16 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

HRS16 - Hardware Request Status Channel 16 0b0..A hardware service request for channel 16 is not present 0b1..A hardware service request for channel 16 is present

Definition at line 14632 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS16_MASK

#define DMA_HRS_HRS16_MASK (0x10000U)

Definition at line 14626 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS16_SHIFT

#define DMA_HRS_HRS16_SHIFT (16U)

Definition at line 14627 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS17

#define DMA_HRS_HRS17 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

HRS17 - Hardware Request Status Channel 17 0b0..A hardware service request for channel 17 is not present 0b1..A hardware service request for channel 17 is present

Definition at line 14639 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS17_MASK

#define DMA_HRS_HRS17_MASK (0x20000U)

Definition at line 14633 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS17_SHIFT

#define DMA_HRS_HRS17_SHIFT (17U)

Definition at line 14634 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS18

#define DMA_HRS_HRS18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

HRS18 - Hardware Request Status Channel 18 0b0..A hardware service request for channel 18 is not present 0b1..A hardware service request for channel 18 is present

Definition at line 14646 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS18_MASK

#define DMA_HRS_HRS18_MASK (0x40000U)

Definition at line 14640 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS18_SHIFT

#define DMA_HRS_HRS18_SHIFT (18U)

Definition at line 14641 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS19

#define DMA_HRS_HRS19 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

HRS19 - Hardware Request Status Channel 19 0b0..A hardware service request for channel 19 is not present 0b1..A hardware service request for channel 19 is present

Definition at line 14653 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS19_MASK

#define DMA_HRS_HRS19_MASK (0x80000U)

Definition at line 14647 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS19_SHIFT

#define DMA_HRS_HRS19_SHIFT (19U)

Definition at line 14648 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS1_MASK

#define DMA_HRS_HRS1_MASK (0x2U)

Definition at line 14521 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS1_SHIFT

#define DMA_HRS_HRS1_SHIFT (1U)

Definition at line 14522 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS2

#define DMA_HRS_HRS2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

Definition at line 14534 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS20

#define DMA_HRS_HRS20 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

HRS20 - Hardware Request Status Channel 20 0b0..A hardware service request for channel 20 is not present 0b1..A hardware service request for channel 20 is present

Definition at line 14660 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS20_MASK

#define DMA_HRS_HRS20_MASK (0x100000U)

Definition at line 14654 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS20_SHIFT

#define DMA_HRS_HRS20_SHIFT (20U)

Definition at line 14655 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS21

#define DMA_HRS_HRS21 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

HRS21 - Hardware Request Status Channel 21 0b0..A hardware service request for channel 21 is not present 0b1..A hardware service request for channel 21 is present

Definition at line 14667 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS21_MASK

#define DMA_HRS_HRS21_MASK (0x200000U)

Definition at line 14661 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS21_SHIFT

#define DMA_HRS_HRS21_SHIFT (21U)

Definition at line 14662 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS22

#define DMA_HRS_HRS22 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

HRS22 - Hardware Request Status Channel 22 0b0..A hardware service request for channel 22 is not present 0b1..A hardware service request for channel 22 is present

Definition at line 14674 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS22_MASK

#define DMA_HRS_HRS22_MASK (0x400000U)

Definition at line 14668 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS22_SHIFT

#define DMA_HRS_HRS22_SHIFT (22U)

Definition at line 14669 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS23

#define DMA_HRS_HRS23 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

HRS23 - Hardware Request Status Channel 23 0b0..A hardware service request for channel 23 is not present 0b1..A hardware service request for channel 23 is present

Definition at line 14681 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS23_MASK

#define DMA_HRS_HRS23_MASK (0x800000U)

Definition at line 14675 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS23_SHIFT

#define DMA_HRS_HRS23_SHIFT (23U)

Definition at line 14676 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS24

#define DMA_HRS_HRS24 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

HRS24 - Hardware Request Status Channel 24 0b0..A hardware service request for channel 24 is not present 0b1..A hardware service request for channel 24 is present

Definition at line 14688 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS24_MASK

#define DMA_HRS_HRS24_MASK (0x1000000U)

Definition at line 14682 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS24_SHIFT

#define DMA_HRS_HRS24_SHIFT (24U)

Definition at line 14683 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS25

#define DMA_HRS_HRS25 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

HRS25 - Hardware Request Status Channel 25 0b0..A hardware service request for channel 25 is not present 0b1..A hardware service request for channel 25 is present

Definition at line 14695 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS25_MASK

#define DMA_HRS_HRS25_MASK (0x2000000U)

Definition at line 14689 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS25_SHIFT

#define DMA_HRS_HRS25_SHIFT (25U)

Definition at line 14690 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS26

#define DMA_HRS_HRS26 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

HRS26 - Hardware Request Status Channel 26 0b0..A hardware service request for channel 26 is not present 0b1..A hardware service request for channel 26 is present

Definition at line 14702 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS26_MASK

#define DMA_HRS_HRS26_MASK (0x4000000U)

Definition at line 14696 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS26_SHIFT

#define DMA_HRS_HRS26_SHIFT (26U)

Definition at line 14697 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS27

#define DMA_HRS_HRS27 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

HRS27 - Hardware Request Status Channel 27 0b0..A hardware service request for channel 27 is not present 0b1..A hardware service request for channel 27 is present

Definition at line 14709 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS27_MASK

#define DMA_HRS_HRS27_MASK (0x8000000U)

Definition at line 14703 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS27_SHIFT

#define DMA_HRS_HRS27_SHIFT (27U)

Definition at line 14704 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS28

#define DMA_HRS_HRS28 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

HRS28 - Hardware Request Status Channel 28 0b0..A hardware service request for channel 28 is not present 0b1..A hardware service request for channel 28 is present

Definition at line 14716 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS28_MASK

#define DMA_HRS_HRS28_MASK (0x10000000U)

Definition at line 14710 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS28_SHIFT

#define DMA_HRS_HRS28_SHIFT (28U)

Definition at line 14711 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS29

#define DMA_HRS_HRS29 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

HRS29 - Hardware Request Status Channel 29 0b0..A hardware service request for channel 29 is not preset 0b1..A hardware service request for channel 29 is present

Definition at line 14723 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS29_MASK

#define DMA_HRS_HRS29_MASK (0x20000000U)

Definition at line 14717 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS29_SHIFT

#define DMA_HRS_HRS29_SHIFT (29U)

Definition at line 14718 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS2_MASK

#define DMA_HRS_HRS2_MASK (0x4U)

Definition at line 14528 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS2_SHIFT

#define DMA_HRS_HRS2_SHIFT (2U)

Definition at line 14529 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS3

#define DMA_HRS_HRS3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

Definition at line 14541 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS30

#define DMA_HRS_HRS30 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

HRS30 - Hardware Request Status Channel 30 0b0..A hardware service request for channel 30 is not present 0b1..A hardware service request for channel 30 is present

Definition at line 14730 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS30_MASK

#define DMA_HRS_HRS30_MASK (0x40000000U)

Definition at line 14724 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS30_SHIFT

#define DMA_HRS_HRS30_SHIFT (30U)

Definition at line 14725 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS31

#define DMA_HRS_HRS31 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

HRS31 - Hardware Request Status Channel 31 0b0..A hardware service request for channel 31 is not present 0b1..A hardware service request for channel 31 is present

Definition at line 14737 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS31_MASK

#define DMA_HRS_HRS31_MASK (0x80000000U)

Definition at line 14731 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS31_SHIFT

#define DMA_HRS_HRS31_SHIFT (31U)

Definition at line 14732 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS3_MASK

#define DMA_HRS_HRS3_MASK (0x8U)

Definition at line 14535 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS3_SHIFT

#define DMA_HRS_HRS3_SHIFT (3U)

Definition at line 14536 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS4

#define DMA_HRS_HRS4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

Definition at line 14548 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS4_MASK

#define DMA_HRS_HRS4_MASK (0x10U)

Definition at line 14542 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS4_SHIFT

#define DMA_HRS_HRS4_SHIFT (4U)

Definition at line 14543 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS5

#define DMA_HRS_HRS5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

Definition at line 14555 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS5_MASK

#define DMA_HRS_HRS5_MASK (0x20U)

Definition at line 14549 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS5_SHIFT

#define DMA_HRS_HRS5_SHIFT (5U)

Definition at line 14550 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS6

#define DMA_HRS_HRS6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

Definition at line 14562 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS6_MASK

#define DMA_HRS_HRS6_MASK (0x40U)

Definition at line 14556 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS6_SHIFT

#define DMA_HRS_HRS6_SHIFT (6U)

Definition at line 14557 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS7

#define DMA_HRS_HRS7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

Definition at line 14569 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS7_MASK

#define DMA_HRS_HRS7_MASK (0x80U)

Definition at line 14563 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS7_SHIFT

#define DMA_HRS_HRS7_SHIFT (7U)

Definition at line 14564 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS8

#define DMA_HRS_HRS8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

Definition at line 14576 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS8_MASK

#define DMA_HRS_HRS8_MASK (0x100U)

Definition at line 14570 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS8_SHIFT

#define DMA_HRS_HRS8_SHIFT (8U)

Definition at line 14571 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS9

#define DMA_HRS_HRS9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

Definition at line 14583 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS9_MASK

#define DMA_HRS_HRS9_MASK (0x200U)

Definition at line 14577 of file MIMXRT1062.h.

## ◆ DMA_HRS_HRS9_SHIFT

#define DMA_HRS_HRS9_SHIFT (9U)

Definition at line 14578 of file MIMXRT1062.h.

## ◆ DMA_INT_INT0

#define DMA_INT_INT0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14064 of file MIMXRT1062.h.

## ◆ DMA_INT_INT0_MASK

#define DMA_INT_INT0_MASK (0x1U)

Definition at line 14058 of file MIMXRT1062.h.

## ◆ DMA_INT_INT0_SHIFT

#define DMA_INT_INT0_SHIFT (0U)

Definition at line 14059 of file MIMXRT1062.h.

## ◆ DMA_INT_INT1

#define DMA_INT_INT1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14071 of file MIMXRT1062.h.

## ◆ DMA_INT_INT10

#define DMA_INT_INT10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14134 of file MIMXRT1062.h.

## ◆ DMA_INT_INT10_MASK

#define DMA_INT_INT10_MASK (0x400U)

Definition at line 14128 of file MIMXRT1062.h.

## ◆ DMA_INT_INT10_SHIFT

#define DMA_INT_INT10_SHIFT (10U)

Definition at line 14129 of file MIMXRT1062.h.

## ◆ DMA_INT_INT11

#define DMA_INT_INT11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14141 of file MIMXRT1062.h.

## ◆ DMA_INT_INT11_MASK

#define DMA_INT_INT11_MASK (0x800U)

Definition at line 14135 of file MIMXRT1062.h.

## ◆ DMA_INT_INT11_SHIFT

#define DMA_INT_INT11_SHIFT (11U)

Definition at line 14136 of file MIMXRT1062.h.

## ◆ DMA_INT_INT12

#define DMA_INT_INT12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14148 of file MIMXRT1062.h.

## ◆ DMA_INT_INT12_MASK

#define DMA_INT_INT12_MASK (0x1000U)

Definition at line 14142 of file MIMXRT1062.h.

## ◆ DMA_INT_INT12_SHIFT

#define DMA_INT_INT12_SHIFT (12U)

Definition at line 14143 of file MIMXRT1062.h.

## ◆ DMA_INT_INT13

#define DMA_INT_INT13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14155 of file MIMXRT1062.h.

## ◆ DMA_INT_INT13_MASK

#define DMA_INT_INT13_MASK (0x2000U)

Definition at line 14149 of file MIMXRT1062.h.

## ◆ DMA_INT_INT13_SHIFT

#define DMA_INT_INT13_SHIFT (13U)

Definition at line 14150 of file MIMXRT1062.h.

## ◆ DMA_INT_INT14

#define DMA_INT_INT14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14162 of file MIMXRT1062.h.

## ◆ DMA_INT_INT14_MASK

#define DMA_INT_INT14_MASK (0x4000U)

Definition at line 14156 of file MIMXRT1062.h.

## ◆ DMA_INT_INT14_SHIFT

#define DMA_INT_INT14_SHIFT (14U)

Definition at line 14157 of file MIMXRT1062.h.

## ◆ DMA_INT_INT15

#define DMA_INT_INT15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14169 of file MIMXRT1062.h.

## ◆ DMA_INT_INT15_MASK

#define DMA_INT_INT15_MASK (0x8000U)

Definition at line 14163 of file MIMXRT1062.h.

## ◆ DMA_INT_INT15_SHIFT

#define DMA_INT_INT15_SHIFT (15U)

Definition at line 14164 of file MIMXRT1062.h.

## ◆ DMA_INT_INT16

#define DMA_INT_INT16 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

INT16 - Interrupt Request 16 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14176 of file MIMXRT1062.h.

## ◆ DMA_INT_INT16_MASK

#define DMA_INT_INT16_MASK (0x10000U)

Definition at line 14170 of file MIMXRT1062.h.

## ◆ DMA_INT_INT16_SHIFT

#define DMA_INT_INT16_SHIFT (16U)

Definition at line 14171 of file MIMXRT1062.h.

## ◆ DMA_INT_INT17

#define DMA_INT_INT17 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

INT17 - Interrupt Request 17 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14183 of file MIMXRT1062.h.

## ◆ DMA_INT_INT17_MASK

#define DMA_INT_INT17_MASK (0x20000U)

Definition at line 14177 of file MIMXRT1062.h.

## ◆ DMA_INT_INT17_SHIFT

#define DMA_INT_INT17_SHIFT (17U)

Definition at line 14178 of file MIMXRT1062.h.

## ◆ DMA_INT_INT18

#define DMA_INT_INT18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

INT18 - Interrupt Request 18 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14190 of file MIMXRT1062.h.

## ◆ DMA_INT_INT18_MASK

#define DMA_INT_INT18_MASK (0x40000U)

Definition at line 14184 of file MIMXRT1062.h.

## ◆ DMA_INT_INT18_SHIFT

#define DMA_INT_INT18_SHIFT (18U)

Definition at line 14185 of file MIMXRT1062.h.

## ◆ DMA_INT_INT19

#define DMA_INT_INT19 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

INT19 - Interrupt Request 19 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14197 of file MIMXRT1062.h.

## ◆ DMA_INT_INT19_MASK

#define DMA_INT_INT19_MASK (0x80000U)

Definition at line 14191 of file MIMXRT1062.h.

## ◆ DMA_INT_INT19_SHIFT

#define DMA_INT_INT19_SHIFT (19U)

Definition at line 14192 of file MIMXRT1062.h.

## ◆ DMA_INT_INT1_MASK

#define DMA_INT_INT1_MASK (0x2U)

Definition at line 14065 of file MIMXRT1062.h.

## ◆ DMA_INT_INT1_SHIFT

#define DMA_INT_INT1_SHIFT (1U)

Definition at line 14066 of file MIMXRT1062.h.

## ◆ DMA_INT_INT2

#define DMA_INT_INT2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14078 of file MIMXRT1062.h.

## ◆ DMA_INT_INT20

#define DMA_INT_INT20 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

INT20 - Interrupt Request 20 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14204 of file MIMXRT1062.h.

## ◆ DMA_INT_INT20_MASK

#define DMA_INT_INT20_MASK (0x100000U)

Definition at line 14198 of file MIMXRT1062.h.

## ◆ DMA_INT_INT20_SHIFT

#define DMA_INT_INT20_SHIFT (20U)

Definition at line 14199 of file MIMXRT1062.h.

## ◆ DMA_INT_INT21

#define DMA_INT_INT21 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

INT21 - Interrupt Request 21 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14211 of file MIMXRT1062.h.

## ◆ DMA_INT_INT21_MASK

#define DMA_INT_INT21_MASK (0x200000U)

Definition at line 14205 of file MIMXRT1062.h.

## ◆ DMA_INT_INT21_SHIFT

#define DMA_INT_INT21_SHIFT (21U)

Definition at line 14206 of file MIMXRT1062.h.

## ◆ DMA_INT_INT22

#define DMA_INT_INT22 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

INT22 - Interrupt Request 22 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14218 of file MIMXRT1062.h.

## ◆ DMA_INT_INT22_MASK

#define DMA_INT_INT22_MASK (0x400000U)

Definition at line 14212 of file MIMXRT1062.h.

## ◆ DMA_INT_INT22_SHIFT

#define DMA_INT_INT22_SHIFT (22U)

Definition at line 14213 of file MIMXRT1062.h.

## ◆ DMA_INT_INT23

#define DMA_INT_INT23 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

INT23 - Interrupt Request 23 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14225 of file MIMXRT1062.h.

## ◆ DMA_INT_INT23_MASK

#define DMA_INT_INT23_MASK (0x800000U)

Definition at line 14219 of file MIMXRT1062.h.

## ◆ DMA_INT_INT23_SHIFT

#define DMA_INT_INT23_SHIFT (23U)

Definition at line 14220 of file MIMXRT1062.h.

## ◆ DMA_INT_INT24

#define DMA_INT_INT24 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

INT24 - Interrupt Request 24 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14232 of file MIMXRT1062.h.

## ◆ DMA_INT_INT24_MASK

#define DMA_INT_INT24_MASK (0x1000000U)

Definition at line 14226 of file MIMXRT1062.h.

## ◆ DMA_INT_INT24_SHIFT

#define DMA_INT_INT24_SHIFT (24U)

Definition at line 14227 of file MIMXRT1062.h.

## ◆ DMA_INT_INT25

#define DMA_INT_INT25 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

INT25 - Interrupt Request 25 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14239 of file MIMXRT1062.h.

## ◆ DMA_INT_INT25_MASK

#define DMA_INT_INT25_MASK (0x2000000U)

Definition at line 14233 of file MIMXRT1062.h.

## ◆ DMA_INT_INT25_SHIFT

#define DMA_INT_INT25_SHIFT (25U)

Definition at line 14234 of file MIMXRT1062.h.

## ◆ DMA_INT_INT26

#define DMA_INT_INT26 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

INT26 - Interrupt Request 26 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14246 of file MIMXRT1062.h.

## ◆ DMA_INT_INT26_MASK

#define DMA_INT_INT26_MASK (0x4000000U)

Definition at line 14240 of file MIMXRT1062.h.

## ◆ DMA_INT_INT26_SHIFT

#define DMA_INT_INT26_SHIFT (26U)

Definition at line 14241 of file MIMXRT1062.h.

## ◆ DMA_INT_INT27

#define DMA_INT_INT27 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

INT27 - Interrupt Request 27 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14253 of file MIMXRT1062.h.

## ◆ DMA_INT_INT27_MASK

#define DMA_INT_INT27_MASK (0x8000000U)

Definition at line 14247 of file MIMXRT1062.h.

## ◆ DMA_INT_INT27_SHIFT

#define DMA_INT_INT27_SHIFT (27U)

Definition at line 14248 of file MIMXRT1062.h.

## ◆ DMA_INT_INT28

#define DMA_INT_INT28 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

INT28 - Interrupt Request 28 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14260 of file MIMXRT1062.h.

## ◆ DMA_INT_INT28_MASK

#define DMA_INT_INT28_MASK (0x10000000U)

Definition at line 14254 of file MIMXRT1062.h.

## ◆ DMA_INT_INT28_SHIFT

#define DMA_INT_INT28_SHIFT (28U)

Definition at line 14255 of file MIMXRT1062.h.

## ◆ DMA_INT_INT29

#define DMA_INT_INT29 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

INT29 - Interrupt Request 29 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14267 of file MIMXRT1062.h.

## ◆ DMA_INT_INT29_MASK

#define DMA_INT_INT29_MASK (0x20000000U)

Definition at line 14261 of file MIMXRT1062.h.

## ◆ DMA_INT_INT29_SHIFT

#define DMA_INT_INT29_SHIFT (29U)

Definition at line 14262 of file MIMXRT1062.h.

## ◆ DMA_INT_INT2_MASK

#define DMA_INT_INT2_MASK (0x4U)

Definition at line 14072 of file MIMXRT1062.h.

## ◆ DMA_INT_INT2_SHIFT

#define DMA_INT_INT2_SHIFT (2U)

Definition at line 14073 of file MIMXRT1062.h.

## ◆ DMA_INT_INT3

#define DMA_INT_INT3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14085 of file MIMXRT1062.h.

## ◆ DMA_INT_INT30

#define DMA_INT_INT30 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

INT30 - Interrupt Request 30 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14274 of file MIMXRT1062.h.

## ◆ DMA_INT_INT30_MASK

#define DMA_INT_INT30_MASK (0x40000000U)

Definition at line 14268 of file MIMXRT1062.h.

## ◆ DMA_INT_INT30_SHIFT

#define DMA_INT_INT30_SHIFT (30U)

Definition at line 14269 of file MIMXRT1062.h.

## ◆ DMA_INT_INT31

#define DMA_INT_INT31 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

INT31 - Interrupt Request 31 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14281 of file MIMXRT1062.h.

## ◆ DMA_INT_INT31_MASK

#define DMA_INT_INT31_MASK (0x80000000U)

Definition at line 14275 of file MIMXRT1062.h.

## ◆ DMA_INT_INT31_SHIFT

#define DMA_INT_INT31_SHIFT (31U)

Definition at line 14276 of file MIMXRT1062.h.

## ◆ DMA_INT_INT3_MASK

#define DMA_INT_INT3_MASK (0x8U)

Definition at line 14079 of file MIMXRT1062.h.

## ◆ DMA_INT_INT3_SHIFT

#define DMA_INT_INT3_SHIFT (3U)

Definition at line 14080 of file MIMXRT1062.h.

## ◆ DMA_INT_INT4

#define DMA_INT_INT4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14092 of file MIMXRT1062.h.

## ◆ DMA_INT_INT4_MASK

#define DMA_INT_INT4_MASK (0x10U)

Definition at line 14086 of file MIMXRT1062.h.

## ◆ DMA_INT_INT4_SHIFT

#define DMA_INT_INT4_SHIFT (4U)

Definition at line 14087 of file MIMXRT1062.h.

## ◆ DMA_INT_INT5

#define DMA_INT_INT5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14099 of file MIMXRT1062.h.

## ◆ DMA_INT_INT5_MASK

#define DMA_INT_INT5_MASK (0x20U)

Definition at line 14093 of file MIMXRT1062.h.

## ◆ DMA_INT_INT5_SHIFT

#define DMA_INT_INT5_SHIFT (5U)

Definition at line 14094 of file MIMXRT1062.h.

## ◆ DMA_INT_INT6

#define DMA_INT_INT6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14106 of file MIMXRT1062.h.

## ◆ DMA_INT_INT6_MASK

#define DMA_INT_INT6_MASK (0x40U)

Definition at line 14100 of file MIMXRT1062.h.

## ◆ DMA_INT_INT6_SHIFT

#define DMA_INT_INT6_SHIFT (6U)

Definition at line 14101 of file MIMXRT1062.h.

## ◆ DMA_INT_INT7

#define DMA_INT_INT7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14113 of file MIMXRT1062.h.

## ◆ DMA_INT_INT7_MASK

#define DMA_INT_INT7_MASK (0x80U)

Definition at line 14107 of file MIMXRT1062.h.

## ◆ DMA_INT_INT7_SHIFT

#define DMA_INT_INT7_SHIFT (7U)

Definition at line 14108 of file MIMXRT1062.h.

## ◆ DMA_INT_INT8

#define DMA_INT_INT8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14120 of file MIMXRT1062.h.

## ◆ DMA_INT_INT8_MASK

#define DMA_INT_INT8_MASK (0x100U)

Definition at line 14114 of file MIMXRT1062.h.

## ◆ DMA_INT_INT8_SHIFT

#define DMA_INT_INT8_SHIFT (8U)

Definition at line 14115 of file MIMXRT1062.h.

## ◆ DMA_INT_INT9

#define DMA_INT_INT9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

Definition at line 14127 of file MIMXRT1062.h.

## ◆ DMA_INT_INT9_MASK

#define DMA_INT_INT9_MASK (0x200U)

Definition at line 14121 of file MIMXRT1062.h.

## ◆ DMA_INT_INT9_SHIFT

#define DMA_INT_INT9_SHIFT (9U)

Definition at line 14122 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLNO_COUNT

#define DMA_NBYTES_MLNO_COUNT (32U)

Definition at line 15942 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLNO_NBYTES

#define DMA_NBYTES_MLNO_NBYTES | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

Definition at line 15938 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLNO_NBYTES_MASK

#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)

Definition at line 15934 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLNO_NBYTES_SHIFT

#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)

Definition at line 15935 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_COUNT

#define DMA_NBYTES_MLOFFNO_COUNT (32U)

Definition at line 15968 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_DMLOE

#define DMA_NBYTES_MLOFFNO_DMLOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

Definition at line 15957 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_DMLOE_MASK

#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)

Definition at line 15951 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_DMLOE_SHIFT

#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)

Definition at line 15952 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_NBYTES

#define DMA_NBYTES_MLOFFNO_NBYTES | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

Definition at line 15950 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_NBYTES_MASK

#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)

Definition at line 15946 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_NBYTES_SHIFT

#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)

Definition at line 15947 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_SMLOE

#define DMA_NBYTES_MLOFFNO_SMLOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

Definition at line 15964 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_SMLOE_MASK

#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)

Definition at line 15958 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFNO_SMLOE_SHIFT

#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)

Definition at line 15959 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_COUNT

#define DMA_NBYTES_MLOFFYES_COUNT (32U)

Definition at line 16000 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_DMLOE

#define DMA_NBYTES_MLOFFYES_DMLOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

Definition at line 15989 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_DMLOE_MASK

#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)

Definition at line 15983 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_DMLOE_SHIFT

#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)

Definition at line 15984 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_MLOFF

#define DMA_NBYTES_MLOFFYES_MLOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

MLOFF - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

Definition at line 15982 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_MLOFF_MASK

#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)

Definition at line 15977 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_MLOFF_SHIFT

#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)

Definition at line 15978 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_NBYTES

#define DMA_NBYTES_MLOFFYES_NBYTES | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

Definition at line 15976 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_NBYTES_MASK

#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)

Definition at line 15972 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_NBYTES_SHIFT

#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)

Definition at line 15973 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_SMLOE

#define DMA_NBYTES_MLOFFYES_SMLOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

Definition at line 15996 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_SMLOE_MASK

#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)

Definition at line 15990 of file MIMXRT1062.h.

## ◆ DMA_NBYTES_MLOFFYES_SMLOE_SHIFT

#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)

Definition at line 15991 of file MIMXRT1062.h.

## ◆ DMA_SADDR_COUNT

#define DMA_SADDR_COUNT (32U)

Definition at line 15874 of file MIMXRT1062.h.

## ◆ DMA_SADDR_SADDR

#define DMA_SADDR_SADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

SADDR - Source Address

Definition at line 15870 of file MIMXRT1062.h.

## ◆ DMA_SADDR_SADDR_MASK

#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)

Definition at line 15866 of file MIMXRT1062.h.

## ◆ DMA_SADDR_SADDR_SHIFT

#define DMA_SADDR_SADDR_SHIFT (0U)

Definition at line 15867 of file MIMXRT1062.h.

## ◆ DMA_SEEI_NOP

#define DMA_SEEI_NOP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 13915 of file MIMXRT1062.h.

## ◆ DMA_SEEI_NOP_MASK

#define DMA_SEEI_NOP_MASK (0x80U)

Definition at line 13909 of file MIMXRT1062.h.

## ◆ DMA_SEEI_NOP_SHIFT

#define DMA_SEEI_NOP_SHIFT (7U)

Definition at line 13910 of file MIMXRT1062.h.

## ◆ DMA_SEEI_SAEE

#define DMA_SEEI_SAEE | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Sets All Enable Error Interrupts 0b0..Set only the EEI bit specified in the SEEI field. 0b1..Sets all bits in EEI

Definition at line 13908 of file MIMXRT1062.h.

## ◆ DMA_SEEI_SAEE_MASK

#define DMA_SEEI_SAEE_MASK (0x40U)

Definition at line 13902 of file MIMXRT1062.h.

## ◆ DMA_SEEI_SAEE_SHIFT

#define DMA_SEEI_SAEE_SHIFT (6U)

Definition at line 13903 of file MIMXRT1062.h.

## ◆ DMA_SEEI_SEEI

#define DMA_SEEI_SEEI | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

SEEI - Set Enable Error Interrupt

Definition at line 13901 of file MIMXRT1062.h.

## ◆ DMA_SEEI_SEEI_MASK

#define DMA_SEEI_SEEI_MASK (0x1FU)

Definition at line 13897 of file MIMXRT1062.h.

## ◆ DMA_SEEI_SEEI_SHIFT

#define DMA_SEEI_SEEI_SHIFT (0U)

Definition at line 13898 of file MIMXRT1062.h.

## ◆ DMA_SERQ_NOP

#define DMA_SERQ_NOP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 13961 of file MIMXRT1062.h.

## ◆ DMA_SERQ_NOP_MASK

#define DMA_SERQ_NOP_MASK (0x80U)

Definition at line 13955 of file MIMXRT1062.h.

## ◆ DMA_SERQ_NOP_SHIFT

#define DMA_SERQ_NOP_SHIFT (7U)

Definition at line 13956 of file MIMXRT1062.h.

## ◆ DMA_SERQ_SAER

#define DMA_SERQ_SAER | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Set only the ERQ bit specified in the SERQ field 0b1..Set all bits in ERQ

Definition at line 13954 of file MIMXRT1062.h.

## ◆ DMA_SERQ_SAER_MASK

#define DMA_SERQ_SAER_MASK (0x40U)

Definition at line 13948 of file MIMXRT1062.h.

## ◆ DMA_SERQ_SAER_SHIFT

#define DMA_SERQ_SAER_SHIFT (6U)

Definition at line 13949 of file MIMXRT1062.h.

## ◆ DMA_SERQ_SERQ

#define DMA_SERQ_SERQ | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

SERQ - Set Enable Request

Definition at line 13947 of file MIMXRT1062.h.

## ◆ DMA_SERQ_SERQ_MASK

#define DMA_SERQ_SERQ_MASK (0x1FU)

Definition at line 13943 of file MIMXRT1062.h.

## ◆ DMA_SERQ_SERQ_SHIFT

#define DMA_SERQ_SERQ_SHIFT (0U)

Definition at line 13944 of file MIMXRT1062.h.

## ◆ DMA_SLAST_COUNT

#define DMA_SLAST_COUNT (32U)

Definition at line 16012 of file MIMXRT1062.h.

## ◆ DMA_SLAST_SLAST

#define DMA_SLAST_SLAST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

SLAST - Last Source Address Adjustment

Definition at line 16008 of file MIMXRT1062.h.

## ◆ DMA_SLAST_SLAST_MASK

#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)

Definition at line 16004 of file MIMXRT1062.h.

## ◆ DMA_SLAST_SLAST_SHIFT

#define DMA_SLAST_SLAST_SHIFT (0U)

Definition at line 16005 of file MIMXRT1062.h.

## ◆ DMA_SOFF_COUNT

#define DMA_SOFF_COUNT (32U)

Definition at line 15886 of file MIMXRT1062.h.

## ◆ DMA_SOFF_SOFF

#define DMA_SOFF_SOFF | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

SOFF - Source address signed offset

Definition at line 15882 of file MIMXRT1062.h.

## ◆ DMA_SOFF_SOFF_MASK

#define DMA_SOFF_SOFF_MASK (0xFFFFU)

Definition at line 15878 of file MIMXRT1062.h.

## ◆ DMA_SOFF_SOFF_SHIFT

#define DMA_SOFF_SOFF_SHIFT (0U)

Definition at line 15879 of file MIMXRT1062.h.

## ◆ DMA_SSRT_NOP

#define DMA_SSRT_NOP | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

Definition at line 14007 of file MIMXRT1062.h.

## ◆ DMA_SSRT_NOP_MASK

#define DMA_SSRT_NOP_MASK (0x80U)

Definition at line 14001 of file MIMXRT1062.h.

## ◆ DMA_SSRT_NOP_SHIFT

#define DMA_SSRT_NOP_SHIFT (7U)

Definition at line 14002 of file MIMXRT1062.h.

## ◆ DMA_SSRT_SAST

#define DMA_SSRT_SAST | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START Bits (activates all channels) 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field 0b1..Set all bits in TCDn_CSR[START]

Definition at line 14000 of file MIMXRT1062.h.

## ◆ DMA_SSRT_SAST_MASK

#define DMA_SSRT_SAST_MASK (0x40U)

Definition at line 13994 of file MIMXRT1062.h.

## ◆ DMA_SSRT_SAST_SHIFT

#define DMA_SSRT_SAST_SHIFT (6U)

Definition at line 13995 of file MIMXRT1062.h.

## ◆ DMA_SSRT_SSRT

#define DMA_SSRT_SSRT | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

SSRT - Set START Bit

Definition at line 13993 of file MIMXRT1062.h.

## ◆ DMA_SSRT_SSRT_MASK

#define DMA_SSRT_SSRT_MASK (0x1FU)

Definition at line 13989 of file MIMXRT1062.h.

## ◆ DMA_SSRT_SSRT_SHIFT

#define DMA_SSRT_SSRT_SHIFT (0U)

Definition at line 13990 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DBGEN

#define LPSPI_CR_DBGEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..Module is disabled in debug mode 0b1..Module is enabled in debug mode

Definition at line 27826 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DBGEN_MASK

#define LPSPI_CR_DBGEN_MASK (0x8U)

Definition at line 27820 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DBGEN_SHIFT

#define LPSPI_CR_DBGEN_SHIFT (3U)

Definition at line 27821 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DOZEN

#define LPSPI_CR_DOZEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

DOZEN - Doze mode enable 0b0..Module is enabled in Doze mode 0b1..Module is disabled in Doze mode

Definition at line 27819 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DOZEN_MASK

#define LPSPI_CR_DOZEN_MASK (0x4U)

Definition at line 27813 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DOZEN_SHIFT

#define LPSPI_CR_DOZEN_SHIFT (2U)

Definition at line 27814 of file MIMXRT1062.h.

## ◆ LPSPI_CR_MEN

#define LPSPI_CR_MEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

MEN - Module Enable 0b0..Module is disabled 0b1..Module is enabled

Definition at line 27805 of file MIMXRT1062.h.

## ◆ LPSPI_CR_MEN_MASK

#define LPSPI_CR_MEN_MASK (0x1U)

Definition at line 27799 of file MIMXRT1062.h.

## ◆ LPSPI_CR_MEN_SHIFT

#define LPSPI_CR_MEN_SHIFT (0U)

Definition at line 27800 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RRF

#define LPSPI_CR_RRF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive FIFO is reset

Definition at line 27840 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RRF_MASK

#define LPSPI_CR_RRF_MASK (0x200U)

Definition at line 27834 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RRF_SHIFT

#define LPSPI_CR_RRF_SHIFT (9U)

Definition at line 27835 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RST

#define LPSPI_CR_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

RST - Software Reset 0b0..Module is not reset 0b1..Module is reset

Definition at line 27812 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RST_MASK

#define LPSPI_CR_RST_MASK (0x2U)

Definition at line 27806 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RST_SHIFT

#define LPSPI_CR_RST_SHIFT (1U)

Definition at line 27807 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RTF

#define LPSPI_CR_RTF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit FIFO is reset

Definition at line 27833 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RTF_MASK

#define LPSPI_CR_RTF_MASK (0x100U)

Definition at line 27827 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RTF_SHIFT

#define LPSPI_CR_RTF_SHIFT (8U)

Definition at line 27828 of file MIMXRT1062.h.