Callisto4Bootloader: board/clock_config.c Source File

Callisto4Bootloader

clock_config.c
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1 /*
2 * How to setup clock using clock driver functions:
3 *
4 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
5 *
6 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
7 *
8 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
9 *
10 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
11 *
12 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
13 *
14 */
15
16 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
17 !!GlobalInfo
18 product: Clocks v7.0
19 processor: MIMXRT1062xxxxA
20 package_id: MIMXRT1062DVL6A
21 mcu_data: ksdk2_0
22 processor_version: 7.0.1
23 board: MIMXRT1060-EVK
24 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
25
26 #include "clock_config.h"
27 #include "fsl_iomuxc.h"
28
29 /*******************************************************************************
30 * Definitions
31 ******************************************************************************/
32
33 /*******************************************************************************
34 * Variables
35 ******************************************************************************/
36 /* System clock frequency. */
37 extern uint32_t SystemCoreClock;
38
39 /*******************************************************************************
40 ************************ BOARD_InitBootClocks function ************************
41 ******************************************************************************/
42 void BOARD_InitBootClocks(void)
43 {
44 BOARD_BootClockRUN();
45 }
46
47 /*******************************************************************************
48 ********************** Configuration BOARD_BootClockRUN ***********************
49 ******************************************************************************/
50 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
51 !!Configuration
52 name: BOARD_BootClockRUN
53 called_from_default_init: true
54 outputs:
55 - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
56 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
57 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
58 - {id: CLK_1M.outFreq, value: 1 MHz}
59 - {id: CLK_24M.outFreq, value: 24 MHz}
60 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
61 - {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
62 - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
63 - {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
64 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
65 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
66 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
67 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
68 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
69 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
70 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
71 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
72 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
73 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
74 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
75 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
76 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
77 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
78 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
79 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
80 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
81 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
82 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
83 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
84 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
85 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
86 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
87 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
88 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
89 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
90 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
91 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
92 - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
93 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
94 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
95 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
96 settings:
97 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
98 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
99 - {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
100 - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
101 - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
102 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
103 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
104 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
105 - {id: CCM.SEMC_PODF.scale, value: '8'}
106 - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
107 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
108 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
109 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
110 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
111 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
112 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
113 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
114 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
115 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
116 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
117 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
118 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
119 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
120 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
121 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
122 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
123 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
124 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
125 - {id: CCM_ANALOG.PLL4.div, value: '47'}
126 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
127 - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
128 - {id: CCM_ANALOG.PLL5.num, value: '0'}
129 - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
130 - {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
131 - {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
132 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
133 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
134 - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
135 sources:
136 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
137 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
138
139 /*******************************************************************************
140 * Variables for BOARD_BootClockRUN configuration
141 ******************************************************************************/
142 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
143 {
144 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
145 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
146 };
147 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
148 {
149 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
150 .numerator = 0, /* 30 bit numerator of fractional loop divider */
151 .denominator = 1, /* 30 bit denominator of fractional loop divider */
152 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
153 };
154 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
155 {
156 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
157 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
158 };
159 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
160 {
161 .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
162 .postDivider = 8, /* Divider after PLL */
163 .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
164 .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
165 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
166 };
167 /*******************************************************************************
168 * Code for BOARD_BootClockRUN configuration
169 ******************************************************************************/
170 void BOARD_BootClockRUN(void)
171 {
172 /* Init RTC OSC clock frequency. */
173 CLOCK_SetRtcXtalFreq(32768U);
174 /* Enable 1MHz clock output. */
175 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
176 /* Use free 1MHz clock output. */
177 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
178 /* Set XTAL 24MHz clock frequency. */
179 CLOCK_SetXtalFreq(24000000U);
180 /* Enable XTAL 24MHz clock source. */
181 CLOCK_InitExternalClk(0);
182 /* Enable internal RC. */
183 CLOCK_InitRcOsc24M();
184 /* Switch clock source to external OSC. */
185 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
186 /* Set Oscillator ready counter value. */
187 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
188 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
189 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
190 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
191 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
192 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
193 /* Waiting for DCDC_STS_DC_OK bit is asserted */
194 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
195 {
196 }
197 /* Set AHB_PODF. */
198 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
199 /* Disable IPG clock gate. */
200 CLOCK_DisableClock(kCLOCK_Adc1);
201 CLOCK_DisableClock(kCLOCK_Adc2);
202 CLOCK_DisableClock(kCLOCK_Xbar1);
203 CLOCK_DisableClock(kCLOCK_Xbar2);
204 CLOCK_DisableClock(kCLOCK_Xbar3);
205 /* Set IPG_PODF. */
206 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
207 /* Set ARM_PODF. */
208 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
209 /* Set PERIPH_CLK2_PODF. */
210 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
211 /* Disable PERCLK clock gate. */
212 CLOCK_DisableClock(kCLOCK_Gpt1);
213 CLOCK_DisableClock(kCLOCK_Gpt1S);
214 CLOCK_DisableClock(kCLOCK_Gpt2);
215 CLOCK_DisableClock(kCLOCK_Gpt2S);
216 CLOCK_DisableClock(kCLOCK_Pit);
217 /* Set PERCLK_PODF. */
218 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
219 /* Disable USDHC1 clock gate. */
220 CLOCK_DisableClock(kCLOCK_Usdhc1);
221 /* Set USDHC1_PODF. */
222 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
223 /* Set Usdhc1 clock source. */
224 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
225 /* Disable USDHC2 clock gate. */
226 CLOCK_DisableClock(kCLOCK_Usdhc2);
227 /* Set USDHC2_PODF. */
228 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
229 /* Set Usdhc2 clock source. */
230 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
231 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
232 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
233 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
234 #ifndef SKIP_SYSCLK_INIT
235 /* Disable Semc clock gate. */
236 CLOCK_DisableClock(kCLOCK_Semc);
237 /* Set SEMC_PODF. */
238 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
239 /* Set Semc alt clock source. */
240 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
241 /* Set Semc clock source. */
242 CLOCK_SetMux(kCLOCK_SemcMux, 0);
243 #endif
244 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
245 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
246 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
247 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
248 /* Disable Flexspi clock gate. */
249 CLOCK_DisableClock(kCLOCK_FlexSpi);
250 /* Set FLEXSPI_PODF. */
251 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
252 /* Set Flexspi clock source. */
253 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
254 #endif
255 /* Disable Flexspi2 clock gate. */
256 CLOCK_DisableClock(kCLOCK_FlexSpi2);
257 /* Set FLEXSPI2_PODF. */
258 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
259 /* Set Flexspi2 clock source. */
260 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
261 /* Disable CSI clock gate. */
262 CLOCK_DisableClock(kCLOCK_Csi);
263 /* Set CSI_PODF. */
264 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
265 /* Set Csi clock source. */
266 CLOCK_SetMux(kCLOCK_CsiMux, 0);
267 /* Disable LPSPI clock gate. */
268 CLOCK_DisableClock(kCLOCK_Lpspi1);
269 CLOCK_DisableClock(kCLOCK_Lpspi2);
270 CLOCK_DisableClock(kCLOCK_Lpspi3);
271 CLOCK_DisableClock(kCLOCK_Lpspi4);
272 /* Set LPSPI_PODF. */
273 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
274 /* Set Lpspi clock source. */
275 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
276 /* Disable TRACE clock gate. */
277 CLOCK_DisableClock(kCLOCK_Trace);
278 /* Set TRACE_PODF. */
279 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
280 /* Set Trace clock source. */
281 CLOCK_SetMux(kCLOCK_TraceMux, 2);
282 /* Disable SAI1 clock gate. */
283 CLOCK_DisableClock(kCLOCK_Sai1);
284 /* Set SAI1_CLK_PRED. */
285 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
286 /* Set SAI1_CLK_PODF. */
287 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
288 /* Set Sai1 clock source. */
289 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
290 /* Disable SAI2 clock gate. */
291 CLOCK_DisableClock(kCLOCK_Sai2);
292 /* Set SAI2_CLK_PRED. */
293 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
294 /* Set SAI2_CLK_PODF. */
295 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
296 /* Set Sai2 clock source. */
297 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
298 /* Disable SAI3 clock gate. */
299 CLOCK_DisableClock(kCLOCK_Sai3);
300 /* Set SAI3_CLK_PRED. */
301 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
302 /* Set SAI3_CLK_PODF. */
303 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
304 /* Set Sai3 clock source. */
305 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
306 /* Disable Lpi2c clock gate. */
307 CLOCK_DisableClock(kCLOCK_Lpi2c1);
308 CLOCK_DisableClock(kCLOCK_Lpi2c2);
309 CLOCK_DisableClock(kCLOCK_Lpi2c3);
310 /* Set LPI2C_CLK_PODF. */
311 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
312 /* Set Lpi2c clock source. */
313 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
314 /* Disable CAN clock gate. */
315 CLOCK_DisableClock(kCLOCK_Can1);
316 CLOCK_DisableClock(kCLOCK_Can2);
317 CLOCK_DisableClock(kCLOCK_Can3);
318 CLOCK_DisableClock(kCLOCK_Can1S);
319 CLOCK_DisableClock(kCLOCK_Can2S);
320 CLOCK_DisableClock(kCLOCK_Can3S);
321 /* Set CAN_CLK_PODF. */
322 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
323 /* Set Can clock source. */
324 CLOCK_SetMux(kCLOCK_CanMux, 2);
325 /* Disable UART clock gate. */
326 CLOCK_DisableClock(kCLOCK_Lpuart1);
327 CLOCK_DisableClock(kCLOCK_Lpuart2);
328 CLOCK_DisableClock(kCLOCK_Lpuart3);
329 CLOCK_DisableClock(kCLOCK_Lpuart4);
330 CLOCK_DisableClock(kCLOCK_Lpuart5);
331 CLOCK_DisableClock(kCLOCK_Lpuart6);
332 CLOCK_DisableClock(kCLOCK_Lpuart7);
333 CLOCK_DisableClock(kCLOCK_Lpuart8);
334 /* Set UART_CLK_PODF. */
335 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
336 /* Set Uart clock source. */
337 CLOCK_SetMux(kCLOCK_UartMux, 0);
338 /* Disable LCDIF clock gate. */
339 CLOCK_DisableClock(kCLOCK_LcdPixel);
340 /* Set LCDIF_PRED. */
341 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
342 /* Set LCDIF_CLK_PODF. */
343 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
344 /* Set Lcdif pre clock source. */
345 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
346 /* Disable SPDIF clock gate. */
347 CLOCK_DisableClock(kCLOCK_Spdif);
348 /* Set SPDIF0_CLK_PRED. */
349 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
350 /* Set SPDIF0_CLK_PODF. */
351 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
352 /* Set Spdif clock source. */
353 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
354 /* Disable Flexio1 clock gate. */
355 CLOCK_DisableClock(kCLOCK_Flexio1);
356 /* Set FLEXIO1_CLK_PRED. */
357 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
358 /* Set FLEXIO1_CLK_PODF. */
359 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
360 /* Set Flexio1 clock source. */
361 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
362 /* Disable Flexio2 clock gate. */
363 CLOCK_DisableClock(kCLOCK_Flexio2);
364 /* Set FLEXIO2_CLK_PRED. */
365 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
366 /* Set FLEXIO2_CLK_PODF. */
367 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
368 /* Set Flexio2 clock source. */
369 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
370 /* Set Pll3 sw clock source. */
371 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
372 /* Init ARM PLL. */
373 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
374 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
375 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
376 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
377 #ifndef SKIP_SYSCLK_INIT
378 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
379 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
380 #endif
381 /* Init System PLL. */
382 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
383 /* Init System pfd0. */
384 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
385 /* Init System pfd1. */
386 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
387 /* Init System pfd2. */
388 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
389 /* Init System pfd3. */
390 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
391 #endif
392 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
393 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
394 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
395 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
396 /* Init Usb1 PLL. */
397 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
398 /* Init Usb1 pfd0. */
399 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
400 /* Init Usb1 pfd1. */
401 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
402 /* Init Usb1 pfd2. */
403 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
404 /* Init Usb1 pfd3. */
405 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
406 /* Disable Usb1 PLL output for USBPHY1. */
407 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
408 #endif
409 /* DeInit Audio PLL. */
410 CLOCK_DeinitAudioPll();
411 /* Bypass Audio PLL. */
412 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
413 /* Set divider for Audio PLL. */
414 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
415 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
416 /* Enable Audio PLL output. */
417 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
418 /* Init Video PLL. */
419 uint32_t pllVideo;
420 /* Disable Video PLL output before initial Video PLL. */
421 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
422 /* Bypass PLL first */
423 CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
424 CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
425 CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
426 CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
427 pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
428 CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
429 pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
430 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
431 CCM_ANALOG->PLL_VIDEO = pllVideo;
432 while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
433 {
434 }
435 /* Disable bypass for Video PLL. */
436 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
437 /* DeInit Enet PLL. */
438 CLOCK_DeinitEnetPll();
439 /* Bypass Enet PLL. */
440 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
441 /* Set Enet output divider. */
442 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
443 /* Enable Enet output. */
444 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
445 /* Set Enet2 output divider. */
446 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
447 /* Enable Enet2 output. */
448 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
449 /* Enable Enet25M output. */
450 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
451 /* DeInit Usb2 PLL. */
452 CLOCK_DeinitUsb2Pll();
453 /* Bypass Usb2 PLL. */
454 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
455 /* Enable Usb2 PLL output. */
456 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
457 /* Set preperiph clock source. */
458 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
459 /* Set periph clock source. */
460 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
461 /* Set periph clock2 clock source. */
462 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
463 /* Set per clock source. */
464 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
465 /* Set lvds1 clock source. */
466 CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
467 /* Set clock out1 divider. */
468 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
469 /* Set clock out1 source. */
470 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
471 /* Set clock out2 divider. */
472 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
473 /* Set clock out2 source. */
474 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
475 /* Set clock out1 drives clock out1. */
476 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
477 /* Disable clock out1. */
478 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
479 /* Disable clock out2. */
480 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
481 /* Set SAI1 MCLK1 clock source. */
482 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
483 /* Set SAI1 MCLK2 clock source. */
484 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
485 /* Set SAI1 MCLK3 clock source. */
486 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
487 /* Set SAI2 MCLK3 clock source. */
488 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
489 /* Set SAI3 MCLK3 clock source. */
490 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
491 /* Set MQS configuration. */
492 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
493 /* Set ENET1 Tx clock source. */
494 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
495 /* Set ENET2 Tx clock source. */
496 #if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
497 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
498 #else
499 IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
500 #endif
501 /* Set GPT1 High frequency reference clock source. */
502 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
503 /* Set GPT2 High frequency reference clock source. */
504 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
505 /* Set SystemCoreClock variable. */
506 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
507 }
508
videoPllConfig_BOARD_BootClockRUN
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN
Video PLL set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:154
CCM_CCOSR_CLKO1_SEL
#define CCM_CCOSR_CLKO1_SEL(x)
Definition: MIMXRT1062.h:6666
CCM_CCOSR_CLKO1_DIV
#define CCM_CCOSR_CLKO1_DIV(x)
Definition: MIMXRT1062.h:6679
CCM_ANALOG_MISC1_LVDS1_CLK_SEL
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x)
Definition: MIMXRT1062.h:9048
clock_config.h
XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK
#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK
Definition: MIMXRT1062.h:48409
CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK
#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK
Definition: MIMXRT1062.h:9281
CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK
Definition: MIMXRT1062.h:8168
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x)
Definition: MIMXRT1062.h:8023
CCM_CCOSR_CLKO1_DIV_MASK
#define CCM_CCOSR_CLKO1_DIV_MASK
Definition: MIMXRT1062.h:6667
IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK
Definition: MIMXRT1062.h:23078
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK
Definition: MIMXRT1062.h:8015
CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT
#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(x)
Definition: MIMXRT1062.h:8179
DCDC_REG3_TRG
#define DCDC_REG3_TRG(x)
Definition: MIMXRT1062.h:11402
BOARD_BOOTCLOCKRUN_CORE_CLOCK
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK
Definition: clock_config.h:32
CCM_CCOSR_CLKO2_EN_MASK
#define CCM_CCOSR_CLKO2_EN_MASK
Definition: MIMXRT1062.h:6725
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK
#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK
Definition: MIMXRT1062.h:8012
CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK
#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK
Definition: MIMXRT1062.h:9304
XTALOSC24M
#define XTALOSC24M
Definition: MIMXRT1062.h:48478
IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK
Definition: MIMXRT1062.h:23071
CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK
#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK
Definition: MIMXRT1062.h:7456
armPllConfig_BOARD_BootClockRUN
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN
Arm PLL set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:137
CCM_CCOSR_CLKO2_DIV_MASK
#define CCM_CCOSR_CLKO2_DIV_MASK
Definition: MIMXRT1062.h:6712
CCM_ANALOG_PLL_ENET_ENABLE_MASK
#define CCM_ANALOG_PLL_ENET_ENABLE_MASK
Definition: MIMXRT1062.h:8183
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK
#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK
Definition: MIMXRT1062.h:8201
DCDC
#define DCDC
Definition: MIMXRT1062.h:11430
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_MIMXRT1062.c:65
BOARD_InitBootClocks
void BOARD_InitBootClocks(void)
This function executes default configuration of clocks.
Definition: clock_config.c:39
CCM_ANALOG_PLL_AUDIO_ENABLE_MASK
#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK
Definition: MIMXRT1062.h:7850
CCM_CCOSR_CLKO2_SEL
#define CCM_CCOSR_CLKO2_SEL(x)
Definition: MIMXRT1062.h:6711
CCM_ANALOG
#define CCM_ANALOG
Definition: MIMXRT1062.h:9704
CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK
Definition: MIMXRT1062.h:9028
CCM_CCOSR_CLKO1_SEL_MASK
#define CCM_CCOSR_CLKO1_SEL_MASK
Definition: MIMXRT1062.h:6651
CCM_CCOSR_CLKO2_SEL_MASK
#define CCM_CCOSR_CLKO2_SEL_MASK
Definition: MIMXRT1062.h:6694
CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK
#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK
Definition: MIMXRT1062.h:8009
CCM_CCOSR_CLKO1_EN_MASK
#define CCM_CCOSR_CLKO1_EN_MASK
Definition: MIMXRT1062.h:6680
IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK
#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK
Definition: MIMXRT1062.h:22305
CCM_CCOSR_CLKO2_DIV
#define CCM_CCOSR_CLKO2_DIV(x)
Definition: MIMXRT1062.h:6724
CCM_ANALOG_MISC2_VIDEO_DIV_MASK
#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK
Definition: MIMXRT1062.h:9338
CCM_ANALOG_PLL_VIDEO_DIV_SELECT
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x)
Definition: MIMXRT1062.h:8008
XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK
#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK
Definition: MIMXRT1062.h:48412
CCM
#define CCM
Definition: MIMXRT1062.h:7229
CCM_ANALOG_PLL_VIDEO_DENOM_B
#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x)
Definition: MIMXRT1062.h:8163
DCDC_REG0_STS_DC_OK_MASK
#define DCDC_REG0_STS_DC_OK_MASK
Definition: MIMXRT1062.h:11343
IOMUXC_GPR
#define IOMUXC_GPR
Definition: MIMXRT1062.h:24372
CCM_CCR_OSCNT
#define CCM_CCR_OSCNT(x)
Definition: MIMXRT1062.h:5334
CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK
Definition: MIMXRT1062.h:8006
CCM_ANALOG_PLL_VIDEO_NUM_A
#define CCM_ANALOG_PLL_VIDEO_NUM_A(x)
Definition: MIMXRT1062.h:8156
CCM_ANALOG_PLL_USB2_ENABLE_MASK
#define CCM_ANALOG_PLL_USB2_ENABLE_MASK
Definition: MIMXRT1062.h:7594
CCM_CCOSR_CLK_OUT_SEL_MASK
#define CCM_CCOSR_CLK_OUT_SEL_MASK
Definition: MIMXRT1062.h:6687
BOARD_BootClockRUN
void BOARD_BootClockRUN(void)
This function executes configuration of clocks.
Definition: clock_config.c:164
CCM_CCR_OSCNT_MASK
#define CCM_CCR_OSCNT_MASK
Definition: MIMXRT1062.h:5326
CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK
#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK
Definition: MIMXRT1062.h:8198
CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT
#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x)
Definition: MIMXRT1062.h:8035
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK
#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK
Definition: MIMXRT1062.h:8024
CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK
#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK
Definition: MIMXRT1062.h:8171
CCM_ANALOG_MISC2_VIDEO_DIV
#define CCM_ANALOG_MISC2_VIDEO_DIV(x)
Definition: MIMXRT1062.h:9346
CCM_ANALOG_PLL_VIDEO_LOCK_MASK
#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK
Definition: MIMXRT1062.h:8036
DCDC_REG3_TRG_MASK
#define DCDC_REG3_TRG_MASK
Definition: MIMXRT1062.h:11400
usb1PllConfig_BOARD_BootClockRUN
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN
Usb1 PLL set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:149
sysPllConfig_BOARD_BootClockRUN
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN
Sys PLL for BOARD_BootClockRUN configuration.
Definition: clock_config.c:142
CCM_ANALOG_PLL_ENET_DIV_SELECT
#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x)
Definition: MIMXRT1062.h:8170