Callisto4Bootloader: Instrumentation Trace Macrocell (ITM)

Callisto4Bootloader

Modules | Data Structures
Instrumentation Trace Macrocell (ITM)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick)

Type definitions for the Instrumentation Trace Macrocell (ITM) More...

## Modules

| Data Watchpoint and Trace (DWT)
| Type definitions for the Data Watchpoint and Trace (DWT)

## Data Structures

struct | ITM_Type
| Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
#define | ITM_STIM_DISABLED_Pos 1U
#define | ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
#define | ITM_STIM_FIFOREADY_Pos 0U
#define | ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
#define | ITM_TPR_PRIVMASK_Pos 0U
#define | ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define | ITM_TCR_BUSY_Pos 23U
#define | ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
#define | ITM_TCR_TRACEBUSID_Pos 16U
#define | ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
#define | ITM_TCR_GTSFREQ_Pos 10U
#define | ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
#define | ITM_TCR_TSPRESCALE_Pos 8U
#define | ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
#define | ITM_TCR_STALLENA_Pos 5U
#define | ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
#define | ITM_TCR_SWOENA_Pos 4U
#define | ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
#define | ITM_TCR_DWTENA_Pos 3U
#define | ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
#define | ITM_TCR_SYNCENA_Pos 2U
#define | ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
#define | ITM_TCR_TSENA_Pos 1U
#define | ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
#define | ITM_TCR_ITMENA_Pos 0U
#define | ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define | ITM_IWR_ATVALIDM_Pos 0U
#define | ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
#define | ITM_IRR_ATREADYM_Pos 0U
#define | ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
#define | ITM_IMCR_INTEGRATION_Pos 0U
#define | ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
#define | ITM_LSR_ByteAcc_Pos 2U
#define | ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
#define | ITM_LSR_Access_Pos 1U
#define | ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
#define | ITM_LSR_Present_Pos 0U
#define | ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
#define | ITM_STIM_DISABLED_Pos 1U
#define | ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
#define | ITM_STIM_FIFOREADY_Pos 0U
#define | ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
#define | ITM_TPR_PRIVMASK_Pos 0U
#define | ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define | ITM_TCR_BUSY_Pos 23U
#define | ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
#define | ITM_TCR_TRACEBUSID_Pos 16U
#define | ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
#define | ITM_TCR_GTSFREQ_Pos 10U
#define | ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
#define | ITM_TCR_TSPRESCALE_Pos 8U
#define | ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
#define | ITM_TCR_STALLENA_Pos 5U
#define | ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
#define | ITM_TCR_SWOENA_Pos 4U
#define | ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
#define | ITM_TCR_DWTENA_Pos 3U
#define | ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
#define | ITM_TCR_SYNCENA_Pos 2U
#define | ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
#define | ITM_TCR_TSENA_Pos 1U
#define | ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
#define | ITM_TCR_ITMENA_Pos 0U
#define | ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define | ITM_LSR_ByteAcc_Pos 2U
#define | ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
#define | ITM_LSR_Access_Pos 1U
#define | ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
#define | ITM_LSR_Present_Pos 0U
#define | ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
#define | ITM_TPR_PRIVMASK_Pos 0U
#define | ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define | ITM_TCR_BUSY_Pos 23U
#define | ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
#define | ITM_TCR_TraceBusID_Pos 16U
#define | ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define | ITM_TCR_GTSFREQ_Pos 10U
#define | ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
#define | ITM_TCR_TSPrescale_Pos 8U
#define | ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
#define | ITM_TCR_SWOENA_Pos 4U
#define | ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
#define | ITM_TCR_DWTENA_Pos 3U
#define | ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
#define | ITM_TCR_SYNCENA_Pos 2U
#define | ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
#define | ITM_TCR_TSENA_Pos 1U
#define | ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
#define | ITM_TCR_ITMENA_Pos 0U
#define | ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define | ITM_LSR_ByteAcc_Pos 2U
#define | ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
#define | ITM_LSR_Access_Pos 1U
#define | ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
#define | ITM_LSR_Present_Pos 0U
#define | ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

## Detailed Description

Type definitions for the Instrumentation Trace Macrocell (ITM)

## Macro Definition Documentation

## ◆ ITM_IMCR_INTEGRATION_Msk

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

Definition at line 1176 of file core_armv81mml.h.

## ◆ ITM_IMCR_INTEGRATION_Pos

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

Definition at line 1175 of file core_armv81mml.h.

## ◆ ITM_IRR_ATREADYM_Msk

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

Definition at line 1172 of file core_armv81mml.h.

## ◆ ITM_IRR_ATREADYM_Pos

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

Definition at line 1171 of file core_armv81mml.h.

## ◆ ITM_IWR_ATVALIDM_Msk

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

Definition at line 1168 of file core_armv81mml.h.

## ◆ ITM_IWR_ATVALIDM_Pos

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

Definition at line 1167 of file core_armv81mml.h.

## ◆ ITM_LSR_Access_Msk [1/3]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1086 of file core_armv8mml.h.

## ◆ ITM_LSR_Access_Msk [2/3]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1099 of file core_cm7.h.

## ◆ ITM_LSR_Access_Msk [3/3]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1183 of file core_armv81mml.h.

## ◆ ITM_LSR_Access_Pos [1/3]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1085 of file core_armv8mml.h.

## ◆ ITM_LSR_Access_Pos [2/3]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1098 of file core_cm7.h.

## ◆ ITM_LSR_Access_Pos [3/3]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1182 of file core_armv81mml.h.

## ◆ ITM_LSR_ByteAcc_Msk [1/3]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1083 of file core_armv8mml.h.

## ◆ ITM_LSR_ByteAcc_Msk [2/3]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1096 of file core_cm7.h.

## ◆ ITM_LSR_ByteAcc_Msk [3/3]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1180 of file core_armv81mml.h.

## ◆ ITM_LSR_ByteAcc_Pos [1/3]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1082 of file core_armv8mml.h.

## ◆ ITM_LSR_ByteAcc_Pos [2/3]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1095 of file core_cm7.h.

## ◆ ITM_LSR_ByteAcc_Pos [3/3]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1179 of file core_armv81mml.h.

## ◆ ITM_LSR_Present_Msk [1/3]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1089 of file core_armv8mml.h.

## ◆ ITM_LSR_Present_Msk [2/3]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1102 of file core_cm7.h.

## ◆ ITM_LSR_Present_Msk [3/3]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1186 of file core_armv81mml.h.

## ◆ ITM_LSR_Present_Pos [1/3]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1088 of file core_armv8mml.h.

## ◆ ITM_LSR_Present_Pos [2/3]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1101 of file core_cm7.h.

## ◆ ITM_LSR_Present_Pos [3/3]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1185 of file core_armv81mml.h.

## ◆ ITM_STIM_DISABLED_Msk [1/2]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1041 of file core_armv8mml.h.

## ◆ ITM_STIM_DISABLED_Msk [2/2]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1126 of file core_armv81mml.h.

## ◆ ITM_STIM_DISABLED_Pos [1/2]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1040 of file core_armv8mml.h.

## ◆ ITM_STIM_DISABLED_Pos [2/2]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1125 of file core_armv81mml.h.

## ◆ ITM_STIM_FIFOREADY_Msk [1/2]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1044 of file core_armv8mml.h.

## ◆ ITM_STIM_FIFOREADY_Msk [2/2]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1129 of file core_armv81mml.h.

## ◆ ITM_STIM_FIFOREADY_Pos [1/2]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1043 of file core_armv8mml.h.

## ◆ ITM_STIM_FIFOREADY_Pos [2/2]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1128 of file core_armv81mml.h.

## ◆ ITM_TCR_BUSY_Msk [1/3]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1052 of file core_armv8mml.h.

## ◆ ITM_TCR_BUSY_Msk [2/3]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1068 of file core_cm7.h.

## ◆ ITM_TCR_BUSY_Msk [3/3]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1137 of file core_armv81mml.h.

## ◆ ITM_TCR_BUSY_Pos [1/3]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1051 of file core_armv8mml.h.

## ◆ ITM_TCR_BUSY_Pos [2/3]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1067 of file core_cm7.h.

## ◆ ITM_TCR_BUSY_Pos [3/3]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1136 of file core_armv81mml.h.

## ◆ ITM_TCR_DWTENA_Msk [1/3]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1070 of file core_armv8mml.h.

## ◆ ITM_TCR_DWTENA_Msk [2/3]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1083 of file core_cm7.h.

## ◆ ITM_TCR_DWTENA_Msk [3/3]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1155 of file core_armv81mml.h.

## ◆ ITM_TCR_DWTENA_Pos [1/3]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1069 of file core_armv8mml.h.

## ◆ ITM_TCR_DWTENA_Pos [2/3]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1082 of file core_cm7.h.

## ◆ ITM_TCR_DWTENA_Pos [3/3]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1154 of file core_armv81mml.h.

## ◆ ITM_TCR_GTSFREQ_Msk [1/3]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1058 of file core_armv8mml.h.

## ◆ ITM_TCR_GTSFREQ_Msk [2/3]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1074 of file core_cm7.h.

## ◆ ITM_TCR_GTSFREQ_Msk [3/3]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1143 of file core_armv81mml.h.

## ◆ ITM_TCR_GTSFREQ_Pos [1/3]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1057 of file core_armv8mml.h.

## ◆ ITM_TCR_GTSFREQ_Pos [2/3]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1073 of file core_cm7.h.

## ◆ ITM_TCR_GTSFREQ_Pos [3/3]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1142 of file core_armv81mml.h.

## ◆ ITM_TCR_ITMENA_Msk [1/3]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1079 of file core_armv8mml.h.

## ◆ ITM_TCR_ITMENA_Msk [2/3]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1092 of file core_cm7.h.

## ◆ ITM_TCR_ITMENA_Msk [3/3]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1164 of file core_armv81mml.h.

## ◆ ITM_TCR_ITMENA_Pos [1/3]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1078 of file core_armv8mml.h.

## ◆ ITM_TCR_ITMENA_Pos [2/3]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1091 of file core_cm7.h.

## ◆ ITM_TCR_ITMENA_Pos [3/3]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1163 of file core_armv81mml.h.

## ◆ ITM_TCR_STALLENA_Msk [1/2]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1064 of file core_armv8mml.h.

## ◆ ITM_TCR_STALLENA_Msk [2/2]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1149 of file core_armv81mml.h.

## ◆ ITM_TCR_STALLENA_Pos [1/2]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1063 of file core_armv8mml.h.

## ◆ ITM_TCR_STALLENA_Pos [2/2]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1148 of file core_armv81mml.h.

## ◆ ITM_TCR_SWOENA_Msk [1/3]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1067 of file core_armv8mml.h.

## ◆ ITM_TCR_SWOENA_Msk [2/3]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1080 of file core_cm7.h.

## ◆ ITM_TCR_SWOENA_Msk [3/3]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1152 of file core_armv81mml.h.

## ◆ ITM_TCR_SWOENA_Pos [1/3]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1066 of file core_armv8mml.h.

## ◆ ITM_TCR_SWOENA_Pos [2/3]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1079 of file core_cm7.h.

## ◆ ITM_TCR_SWOENA_Pos [3/3]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1151 of file core_armv81mml.h.

## ◆ ITM_TCR_SYNCENA_Msk [1/3]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1073 of file core_armv8mml.h.

## ◆ ITM_TCR_SYNCENA_Msk [2/3]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1086 of file core_cm7.h.

## ◆ ITM_TCR_SYNCENA_Msk [3/3]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1158 of file core_armv81mml.h.

## ◆ ITM_TCR_SYNCENA_Pos [1/3]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1072 of file core_armv8mml.h.

## ◆ ITM_TCR_SYNCENA_Pos [2/3]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1085 of file core_cm7.h.

## ◆ ITM_TCR_SYNCENA_Pos [3/3]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1157 of file core_armv81mml.h.

## ◆ ITM_TCR_TRACEBUSID_Msk [1/2]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1055 of file core_armv8mml.h.

## ◆ ITM_TCR_TraceBusID_Msk

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 1071 of file core_cm7.h.

## ◆ ITM_TCR_TRACEBUSID_Msk [2/2]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1140 of file core_armv81mml.h.

## ◆ ITM_TCR_TRACEBUSID_Pos [1/2]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1054 of file core_armv8mml.h.

## ◆ ITM_TCR_TraceBusID_Pos

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1070 of file core_cm7.h.

## ◆ ITM_TCR_TRACEBUSID_Pos [2/2]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1139 of file core_armv81mml.h.

## ◆ ITM_TCR_TSENA_Msk [1/3]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1076 of file core_armv8mml.h.

## ◆ ITM_TCR_TSENA_Msk [2/3]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1089 of file core_cm7.h.

## ◆ ITM_TCR_TSENA_Msk [3/3]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1161 of file core_armv81mml.h.

## ◆ ITM_TCR_TSENA_Pos [1/3]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1075 of file core_armv8mml.h.

## ◆ ITM_TCR_TSENA_Pos [2/3]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1088 of file core_cm7.h.

## ◆ ITM_TCR_TSENA_Pos [3/3]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1160 of file core_armv81mml.h.

## ◆ ITM_TCR_TSPRESCALE_Msk [1/2]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1061 of file core_armv8mml.h.

## ◆ ITM_TCR_TSPrescale_Msk

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 1077 of file core_cm7.h.

## ◆ ITM_TCR_TSPRESCALE_Msk [2/2]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1146 of file core_armv81mml.h.

## ◆ ITM_TCR_TSPRESCALE_Pos [1/2]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1060 of file core_armv8mml.h.

## ◆ ITM_TCR_TSPrescale_Pos

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 1076 of file core_cm7.h.

## ◆ ITM_TCR_TSPRESCALE_Pos [2/2]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1145 of file core_armv81mml.h.

## ◆ ITM_TPR_PRIVMASK_Msk [1/3]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1048 of file core_armv8mml.h.

## ◆ ITM_TPR_PRIVMASK_Msk [2/3]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1064 of file core_cm7.h.

## ◆ ITM_TPR_PRIVMASK_Msk [3/3]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1133 of file core_armv81mml.h.

## ◆ ITM_TPR_PRIVMASK_Pos [1/3]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 1047 of file core_armv8mml.h.

## ◆ ITM_TPR_PRIVMASK_Pos [2/3]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 1063 of file core_cm7.h.

## ◆ ITM_TPR_PRIVMASK_Pos [3/3]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 1132 of file core_armv81mml.h.