Callisto4Bootloader: SEMC Register Masks

Callisto4Bootloader

Macros
SEMC Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » SEMC Peripheral Access Layer

## Macros

#define | SEMC_BR_COUNT (9U)

## INTEN - Interrupt Enable Register

#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U)
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U)
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U)
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U)
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)

## IPCMD - IP Command register

#define | SEMC_IPCMD_CMD_MASK (0xFFFFU)
#define | SEMC_IPCMD_CMD_SHIFT (0U)
#define | SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
#define | SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
#define | SEMC_IPCMD_KEY_SHIFT (16U)
#define | SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)

## STS0 - Status register 0

#define | SEMC_STS0_IDLE_MASK (0x1U)
#define | SEMC_STS0_IDLE_SHIFT (0U)
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
#define | SEMC_STS0_NARDY_MASK (0x2U)
#define | SEMC_STS0_NARDY_SHIFT (1U)
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)

## STS2 - Status register 2

#define | SEMC_STS2_NDWRPEND_MASK (0x8U)
#define | SEMC_STS2_NDWRPEND_SHIFT (3U)
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)

## MCR - Module Control Register

#define | SEMC_MCR_SWRST_MASK (0x1U)
#define | SEMC_MCR_SWRST_SHIFT (0U)
#define | SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
#define | SEMC_MCR_MDIS_MASK (0x2U)
#define | SEMC_MCR_MDIS_SHIFT (1U)
#define | SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
#define | SEMC_MCR_DQSMD_MASK (0x4U)
#define | SEMC_MCR_DQSMD_SHIFT (2U)
#define | SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
#define | SEMC_MCR_WPOL0_MASK (0x40U)
#define | SEMC_MCR_WPOL0_SHIFT (6U)
#define | SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
#define | SEMC_MCR_WPOL1_MASK (0x80U)
#define | SEMC_MCR_WPOL1_SHIFT (7U)
#define | SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
#define | SEMC_MCR_DQSSEL_MASK (0x400U)
#define | SEMC_MCR_DQSSEL_SHIFT (10U)
#define | SEMC_MCR_DQSSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSSEL_SHIFT)) & SEMC_MCR_DQSSEL_MASK)
#define | SEMC_MCR_DLLSEL_MASK (0x800U)
#define | SEMC_MCR_DLLSEL_SHIFT (11U)
#define | SEMC_MCR_DLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DLLSEL_SHIFT)) & SEMC_MCR_DLLSEL_MASK)
#define | SEMC_MCR_CTO_MASK (0xFF0000U)
#define | SEMC_MCR_CTO_SHIFT (16U)
#define | SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
#define | SEMC_MCR_BTO_MASK (0x1F000000U)
#define | SEMC_MCR_BTO_SHIFT (24U)
#define | SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)

## IOCR - IO Mux Control Register

#define | SEMC_IOCR_MUX_A8_MASK (0x7U)
#define | SEMC_IOCR_MUX_A8_SHIFT (0U)
#define | SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
#define | SEMC_IOCR_MUX_CSX0_MASK (0x38U)
#define | SEMC_IOCR_MUX_CSX0_SHIFT (3U)
#define | SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
#define | SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
#define | SEMC_IOCR_MUX_CSX1_SHIFT (6U)
#define | SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
#define | SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
#define | SEMC_IOCR_MUX_CSX2_SHIFT (9U)
#define | SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
#define | SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
#define | SEMC_IOCR_MUX_CSX3_SHIFT (12U)
#define | SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
#define | SEMC_IOCR_MUX_RDY_MASK (0x38000U)
#define | SEMC_IOCR_MUX_RDY_SHIFT (15U)
#define | SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
#define | SEMC_IOCR_MUX_CLKX0_MASK (0x1000000U)
#define | SEMC_IOCR_MUX_CLKX0_SHIFT (24U)
#define | SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
#define | SEMC_IOCR_MUX_CLKX1_MASK (0x2000000U)
#define | SEMC_IOCR_MUX_CLKX1_SHIFT (25U)
#define | SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)

## BMCR0 - Master Bus (AXI) Control Register 0

#define | SEMC_BMCR0_WQOS_MASK (0xFU)
#define | SEMC_BMCR0_WQOS_SHIFT (0U)
#define | SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
#define | SEMC_BMCR0_WAGE_MASK (0xF0U)
#define | SEMC_BMCR0_WAGE_SHIFT (4U)
#define | SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
#define | SEMC_BMCR0_WSH_MASK (0xFF00U)
#define | SEMC_BMCR0_WSH_SHIFT (8U)
#define | SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
#define | SEMC_BMCR0_WRWS_MASK (0xFF0000U)
#define | SEMC_BMCR0_WRWS_SHIFT (16U)
#define | SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)

## BMCR1 - Master Bus (AXI) Control Register 1

#define | SEMC_BMCR1_WQOS_MASK (0xFU)
#define | SEMC_BMCR1_WQOS_SHIFT (0U)
#define | SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
#define | SEMC_BMCR1_WAGE_MASK (0xF0U)
#define | SEMC_BMCR1_WAGE_SHIFT (4U)
#define | SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
#define | SEMC_BMCR1_WPH_MASK (0xFF00U)
#define | SEMC_BMCR1_WPH_SHIFT (8U)
#define | SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
#define | SEMC_BMCR1_WRWS_MASK (0xFF0000U)
#define | SEMC_BMCR1_WRWS_SHIFT (16U)
#define | SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
#define | SEMC_BMCR1_WBR_MASK (0xFF000000U)
#define | SEMC_BMCR1_WBR_SHIFT (24U)
#define | SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)

## BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device)

#define | SEMC_BR_VLD_MASK (0x1U)
#define | SEMC_BR_VLD_SHIFT (0U)
#define | SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
#define | SEMC_BR_MS_MASK (0x3EU)
#define | SEMC_BR_MS_SHIFT (1U)
#define | SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
#define | SEMC_BR_BA_MASK (0xFFFFF000U)
#define | SEMC_BR_BA_SHIFT (12U)
#define | SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)

## DLLCR - DLL Control Register

#define | SEMC_DLLCR_DLLEN_MASK (0x1U)
#define | SEMC_DLLCR_DLLEN_SHIFT (0U)
#define | SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
#define | SEMC_DLLCR_DLLRESET_MASK (0x2U)
#define | SEMC_DLLCR_DLLRESET_SHIFT (1U)
#define | SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
#define | SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U)
#define | SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U)
#define | SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
#define | SEMC_DLLCR_OVRDEN_MASK (0x100U)
#define | SEMC_DLLCR_OVRDEN_SHIFT (8U)
#define | SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
#define | SEMC_DLLCR_OVRDVAL_MASK (0x7E00U)
#define | SEMC_DLLCR_OVRDVAL_SHIFT (9U)
#define | SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)

## INTR - Interrupt Enable Register

#define | SEMC_INTR_IPCMDDONE_MASK (0x1U)
#define | SEMC_INTR_IPCMDDONE_SHIFT (0U)
#define | SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
#define | SEMC_INTR_IPCMDERR_MASK (0x2U)
#define | SEMC_INTR_IPCMDERR_SHIFT (1U)
#define | SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
#define | SEMC_INTR_AXICMDERR_MASK (0x4U)
#define | SEMC_INTR_AXICMDERR_SHIFT (2U)
#define | SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
#define | SEMC_INTR_AXIBUSERR_MASK (0x8U)
#define | SEMC_INTR_AXIBUSERR_SHIFT (3U)
#define | SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
#define | SEMC_INTR_NDPAGEEND_MASK (0x10U)
#define | SEMC_INTR_NDPAGEEND_SHIFT (4U)
#define | SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
#define | SEMC_INTR_NDNOPEND_MASK (0x20U)
#define | SEMC_INTR_NDNOPEND_SHIFT (5U)
#define | SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)

## SDRAMCR0 - SDRAM control register 0

#define | SEMC_SDRAMCR0_PS_MASK (0x1U)
#define | SEMC_SDRAMCR0_PS_SHIFT (0U)
#define | SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
#define | SEMC_SDRAMCR0_BL_MASK (0x70U)
#define | SEMC_SDRAMCR0_BL_SHIFT (4U)
#define | SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
#define | SEMC_SDRAMCR0_COL8_MASK (0x80U)
#define | SEMC_SDRAMCR0_COL8_SHIFT (7U)
#define | SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
#define | SEMC_SDRAMCR0_COL_MASK (0x300U)
#define | SEMC_SDRAMCR0_COL_SHIFT (8U)
#define | SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
#define | SEMC_SDRAMCR0_CL_MASK (0xC00U)
#define | SEMC_SDRAMCR0_CL_SHIFT (10U)
#define | SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
#define | SEMC_SDRAMCR0_BANK2_MASK (0x4000U)
#define | SEMC_SDRAMCR0_BANK2_SHIFT (14U)
#define | SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)

## SDRAMCR1 - SDRAM control register 1

#define | SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
#define | SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
#define | SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
#define | SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
#define | SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
#define | SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
#define | SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
#define | SEMC_SDRAMCR1_RFRC_SHIFT (8U)
#define | SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
#define | SEMC_SDRAMCR1_WRC_MASK (0xE000U)
#define | SEMC_SDRAMCR1_WRC_SHIFT (13U)
#define | SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
#define | SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
#define | SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
#define | SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
#define | SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
#define | SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
#define | SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)

## SDRAMCR2 - SDRAM control register 2

#define | SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
#define | SEMC_SDRAMCR2_SRRC_SHIFT (0U)
#define | SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
#define | SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
#define | SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
#define | SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
#define | SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
#define | SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
#define | SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
#define | SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
#define | SEMC_SDRAMCR2_ITO_SHIFT (24U)
#define | SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)

## SDRAMCR3 - SDRAM control register 3

#define | SEMC_SDRAMCR3_REN_MASK (0x1U)
#define | SEMC_SDRAMCR3_REN_SHIFT (0U)
#define | SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
#define | SEMC_SDRAMCR3_REBL_MASK (0xEU)
#define | SEMC_SDRAMCR3_REBL_SHIFT (1U)
#define | SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
#define | SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
#define | SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
#define | SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
#define | SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
#define | SEMC_SDRAMCR3_RT_SHIFT (16U)
#define | SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
#define | SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
#define | SEMC_SDRAMCR3_UT_SHIFT (24U)
#define | SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)

## NANDCR0 - NAND control register 0

#define | SEMC_NANDCR0_PS_MASK (0x1U)
#define | SEMC_NANDCR0_PS_SHIFT (0U)
#define | SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
#define | SEMC_NANDCR0_SYNCEN_MASK (0x2U)
#define | SEMC_NANDCR0_SYNCEN_SHIFT (1U)
#define | SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
#define | SEMC_NANDCR0_BL_MASK (0x70U)
#define | SEMC_NANDCR0_BL_SHIFT (4U)
#define | SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
#define | SEMC_NANDCR0_EDO_MASK (0x80U)
#define | SEMC_NANDCR0_EDO_SHIFT (7U)
#define | SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
#define | SEMC_NANDCR0_COL_MASK (0x700U)
#define | SEMC_NANDCR0_COL_SHIFT (8U)
#define | SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)

## NANDCR1 - NAND control register 1

#define | SEMC_NANDCR1_CES_MASK (0xFU)
#define | SEMC_NANDCR1_CES_SHIFT (0U)
#define | SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
#define | SEMC_NANDCR1_CEH_MASK (0xF0U)
#define | SEMC_NANDCR1_CEH_SHIFT (4U)
#define | SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
#define | SEMC_NANDCR1_WEL_MASK (0xF00U)
#define | SEMC_NANDCR1_WEL_SHIFT (8U)
#define | SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
#define | SEMC_NANDCR1_WEH_MASK (0xF000U)
#define | SEMC_NANDCR1_WEH_SHIFT (12U)
#define | SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
#define | SEMC_NANDCR1_REL_MASK (0xF0000U)
#define | SEMC_NANDCR1_REL_SHIFT (16U)
#define | SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
#define | SEMC_NANDCR1_REH_MASK (0xF00000U)
#define | SEMC_NANDCR1_REH_SHIFT (20U)
#define | SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
#define | SEMC_NANDCR1_TA_MASK (0xF000000U)
#define | SEMC_NANDCR1_TA_SHIFT (24U)
#define | SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
#define | SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
#define | SEMC_NANDCR1_CEITV_SHIFT (28U)
#define | SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)

## NANDCR2 - NAND control register 2

#define | SEMC_NANDCR2_TWHR_MASK (0x3FU)
#define | SEMC_NANDCR2_TWHR_SHIFT (0U)
#define | SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
#define | SEMC_NANDCR2_TRHW_MASK (0xFC0U)
#define | SEMC_NANDCR2_TRHW_SHIFT (6U)
#define | SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
#define | SEMC_NANDCR2_TADL_MASK (0x3F000U)
#define | SEMC_NANDCR2_TADL_SHIFT (12U)
#define | SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
#define | SEMC_NANDCR2_TRR_MASK (0xFC0000U)
#define | SEMC_NANDCR2_TRR_SHIFT (18U)
#define | SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
#define | SEMC_NANDCR2_TWB_MASK (0x3F000000U)
#define | SEMC_NANDCR2_TWB_SHIFT (24U)
#define | SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)

## NANDCR3 - NAND control register 3

#define | SEMC_NANDCR3_NDOPT1_MASK (0x1U)
#define | SEMC_NANDCR3_NDOPT1_SHIFT (0U)
#define | SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
#define | SEMC_NANDCR3_NDOPT2_MASK (0x2U)
#define | SEMC_NANDCR3_NDOPT2_SHIFT (1U)
#define | SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
#define | SEMC_NANDCR3_NDOPT3_MASK (0x4U)
#define | SEMC_NANDCR3_NDOPT3_SHIFT (2U)
#define | SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
#define | SEMC_NANDCR3_CLE_MASK (0x8U)
#define | SEMC_NANDCR3_CLE_SHIFT (3U)
#define | SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
#define | SEMC_NANDCR3_RDS_MASK (0xF0000U)
#define | SEMC_NANDCR3_RDS_SHIFT (16U)
#define | SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
#define | SEMC_NANDCR3_RDH_MASK (0xF00000U)
#define | SEMC_NANDCR3_RDH_SHIFT (20U)
#define | SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
#define | SEMC_NANDCR3_WDS_MASK (0xF000000U)
#define | SEMC_NANDCR3_WDS_SHIFT (24U)
#define | SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
#define | SEMC_NANDCR3_WDH_MASK (0xF0000000U)
#define | SEMC_NANDCR3_WDH_SHIFT (28U)
#define | SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)

## NORCR0 - NOR control register 0

#define | SEMC_NORCR0_PS_MASK (0x1U)
#define | SEMC_NORCR0_PS_SHIFT (0U)
#define | SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
#define | SEMC_NORCR0_SYNCEN_MASK (0x2U)
#define | SEMC_NORCR0_SYNCEN_SHIFT (1U)
#define | SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
#define | SEMC_NORCR0_BL_MASK (0x70U)
#define | SEMC_NORCR0_BL_SHIFT (4U)
#define | SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
#define | SEMC_NORCR0_AM_MASK (0x300U)
#define | SEMC_NORCR0_AM_SHIFT (8U)
#define | SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
#define | SEMC_NORCR0_ADVP_MASK (0x400U)
#define | SEMC_NORCR0_ADVP_SHIFT (10U)
#define | SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
#define | SEMC_NORCR0_ADVH_MASK (0x800U)
#define | SEMC_NORCR0_ADVH_SHIFT (11U)
#define | SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
#define | SEMC_NORCR0_COL_MASK (0xF000U)
#define | SEMC_NORCR0_COL_SHIFT (12U)
#define | SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)

## NORCR1 - NOR control register 1

#define | SEMC_NORCR1_CES_MASK (0xFU)
#define | SEMC_NORCR1_CES_SHIFT (0U)
#define | SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
#define | SEMC_NORCR1_CEH_MASK (0xF0U)
#define | SEMC_NORCR1_CEH_SHIFT (4U)
#define | SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
#define | SEMC_NORCR1_AS_MASK (0xF00U)
#define | SEMC_NORCR1_AS_SHIFT (8U)
#define | SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
#define | SEMC_NORCR1_AH_MASK (0xF000U)
#define | SEMC_NORCR1_AH_SHIFT (12U)
#define | SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
#define | SEMC_NORCR1_WEL_MASK (0xF0000U)
#define | SEMC_NORCR1_WEL_SHIFT (16U)
#define | SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
#define | SEMC_NORCR1_WEH_MASK (0xF00000U)
#define | SEMC_NORCR1_WEH_SHIFT (20U)
#define | SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
#define | SEMC_NORCR1_REL_MASK (0xF000000U)
#define | SEMC_NORCR1_REL_SHIFT (24U)
#define | SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
#define | SEMC_NORCR1_REH_MASK (0xF0000000U)
#define | SEMC_NORCR1_REH_SHIFT (28U)
#define | SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)

## NORCR2 - NOR control register 2

#define | SEMC_NORCR2_TA_MASK (0xF00U)
#define | SEMC_NORCR2_TA_SHIFT (8U)
#define | SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
#define | SEMC_NORCR2_AWDH_MASK (0xF000U)
#define | SEMC_NORCR2_AWDH_SHIFT (12U)
#define | SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
#define | SEMC_NORCR2_LC_MASK (0xF0000U)
#define | SEMC_NORCR2_LC_SHIFT (16U)
#define | SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
#define | SEMC_NORCR2_RD_MASK (0xF00000U)
#define | SEMC_NORCR2_RD_SHIFT (20U)
#define | SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
#define | SEMC_NORCR2_CEITV_MASK (0xF000000U)
#define | SEMC_NORCR2_CEITV_SHIFT (24U)
#define | SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
#define | SEMC_NORCR2_RDH_MASK (0xF0000000U)
#define | SEMC_NORCR2_RDH_SHIFT (28U)
#define | SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)

## NORCR3 - NOR control register 3

#define | SEMC_NORCR3_ASSR_MASK (0xFU)
#define | SEMC_NORCR3_ASSR_SHIFT (0U)
#define | SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
#define | SEMC_NORCR3_AHSR_MASK (0xF0U)
#define | SEMC_NORCR3_AHSR_SHIFT (4U)
#define | SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)

## SRAMCR0 - SRAM control register 0

#define | SEMC_SRAMCR0_PS_MASK (0x1U)
#define | SEMC_SRAMCR0_PS_SHIFT (0U)
#define | SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
#define | SEMC_SRAMCR0_SYNCEN_MASK (0x2U)
#define | SEMC_SRAMCR0_SYNCEN_SHIFT (1U)
#define | SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
#define | SEMC_SRAMCR0_BL_MASK (0x70U)
#define | SEMC_SRAMCR0_BL_SHIFT (4U)
#define | SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
#define | SEMC_SRAMCR0_AM_MASK (0x300U)
#define | SEMC_SRAMCR0_AM_SHIFT (8U)
#define | SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
#define | SEMC_SRAMCR0_ADVP_MASK (0x400U)
#define | SEMC_SRAMCR0_ADVP_SHIFT (10U)
#define | SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
#define | SEMC_SRAMCR0_ADVH_MASK (0x800U)
#define | SEMC_SRAMCR0_ADVH_SHIFT (11U)
#define | SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
#define | SEMC_SRAMCR0_COL_MASK (0xF000U)
#define | SEMC_SRAMCR0_COL_SHIFT (12U)
#define | SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)

## SRAMCR1 - SRAM control register 1

#define | SEMC_SRAMCR1_CES_MASK (0xFU)
#define | SEMC_SRAMCR1_CES_SHIFT (0U)
#define | SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
#define | SEMC_SRAMCR1_CEH_MASK (0xF0U)
#define | SEMC_SRAMCR1_CEH_SHIFT (4U)
#define | SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
#define | SEMC_SRAMCR1_AS_MASK (0xF00U)
#define | SEMC_SRAMCR1_AS_SHIFT (8U)
#define | SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
#define | SEMC_SRAMCR1_AH_MASK (0xF000U)
#define | SEMC_SRAMCR1_AH_SHIFT (12U)
#define | SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
#define | SEMC_SRAMCR1_WEL_MASK (0xF0000U)
#define | SEMC_SRAMCR1_WEL_SHIFT (16U)
#define | SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
#define | SEMC_SRAMCR1_WEH_MASK (0xF00000U)
#define | SEMC_SRAMCR1_WEH_SHIFT (20U)
#define | SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
#define | SEMC_SRAMCR1_REL_MASK (0xF000000U)
#define | SEMC_SRAMCR1_REL_SHIFT (24U)
#define | SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
#define | SEMC_SRAMCR1_REH_MASK (0xF0000000U)
#define | SEMC_SRAMCR1_REH_SHIFT (28U)
#define | SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)

## SRAMCR2 - SRAM control register 2

#define | SEMC_SRAMCR2_WDS_MASK (0xFU)
#define | SEMC_SRAMCR2_WDS_SHIFT (0U)
#define | SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
#define | SEMC_SRAMCR2_WDH_MASK (0xF0U)
#define | SEMC_SRAMCR2_WDH_SHIFT (4U)
#define | SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
#define | SEMC_SRAMCR2_TA_MASK (0xF00U)
#define | SEMC_SRAMCR2_TA_SHIFT (8U)
#define | SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
#define | SEMC_SRAMCR2_AWDH_MASK (0xF000U)
#define | SEMC_SRAMCR2_AWDH_SHIFT (12U)
#define | SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
#define | SEMC_SRAMCR2_LC_MASK (0xF0000U)
#define | SEMC_SRAMCR2_LC_SHIFT (16U)
#define | SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
#define | SEMC_SRAMCR2_RD_MASK (0xF00000U)
#define | SEMC_SRAMCR2_RD_SHIFT (20U)
#define | SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
#define | SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
#define | SEMC_SRAMCR2_CEITV_SHIFT (24U)
#define | SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
#define | SEMC_SRAMCR2_RDH_MASK (0xF0000000U)
#define | SEMC_SRAMCR2_RDH_SHIFT (28U)
#define | SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)

## DBICR0 - DBI-B control register 0

#define | SEMC_DBICR0_PS_MASK (0x1U)
#define | SEMC_DBICR0_PS_SHIFT (0U)
#define | SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
#define | SEMC_DBICR0_BL_MASK (0x70U)
#define | SEMC_DBICR0_BL_SHIFT (4U)
#define | SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
#define | SEMC_DBICR0_COL_MASK (0xF000U)
#define | SEMC_DBICR0_COL_SHIFT (12U)
#define | SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)

## DBICR1 - DBI-B control register 1

#define | SEMC_DBICR1_CES_MASK (0xFU)
#define | SEMC_DBICR1_CES_SHIFT (0U)
#define | SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
#define | SEMC_DBICR1_CEH_MASK (0xF0U)
#define | SEMC_DBICR1_CEH_SHIFT (4U)
#define | SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
#define | SEMC_DBICR1_WEL_MASK (0xF00U)
#define | SEMC_DBICR1_WEL_SHIFT (8U)
#define | SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
#define | SEMC_DBICR1_WEH_MASK (0xF000U)
#define | SEMC_DBICR1_WEH_SHIFT (12U)
#define | SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
#define | SEMC_DBICR1_REL_MASK (0x3F0000U)
#define | SEMC_DBICR1_REL_SHIFT (16U)
#define | SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
#define | SEMC_DBICR1_REH_MASK (0xFC00000U)
#define | SEMC_DBICR1_REH_SHIFT (22U)
#define | SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
#define | SEMC_DBICR1_CEITV_MASK (0xF0000000U)
#define | SEMC_DBICR1_CEITV_SHIFT (28U)
#define | SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)

## IPCR0 - IP Command control register 0

#define | SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
#define | SEMC_IPCR0_SA_SHIFT (0U)
#define | SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)

## IPCR1 - IP Command control register 1

#define | SEMC_IPCR1_DATSZ_MASK (0x7U)
#define | SEMC_IPCR1_DATSZ_SHIFT (0U)
#define | SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
#define | SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U)
#define | SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U)
#define | SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)

## IPCR2 - IP Command control register 2

#define | SEMC_IPCR2_BM0_MASK (0x1U)
#define | SEMC_IPCR2_BM0_SHIFT (0U)
#define | SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
#define | SEMC_IPCR2_BM1_MASK (0x2U)
#define | SEMC_IPCR2_BM1_SHIFT (1U)
#define | SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
#define | SEMC_IPCR2_BM2_MASK (0x4U)
#define | SEMC_IPCR2_BM2_SHIFT (2U)
#define | SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
#define | SEMC_IPCR2_BM3_MASK (0x8U)
#define | SEMC_IPCR2_BM3_SHIFT (3U)
#define | SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)

## IPTXDAT - TX DATA register (for IP Command)

#define | SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
#define | SEMC_IPTXDAT_DAT_SHIFT (0U)
#define | SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)

## IPRXDAT - RX DATA register (for IP Command)

#define | SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
#define | SEMC_IPRXDAT_DAT_SHIFT (0U)
#define | SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)

## STS12 - Status register 12

#define | SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
#define | SEMC_STS12_NDADDR_SHIFT (0U)
#define | SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)

## STS13 - Status register 13

#define | SEMC_STS13_SLVLOCK_MASK (0x1U)
#define | SEMC_STS13_SLVLOCK_SHIFT (0U)
#define | SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
#define | SEMC_STS13_REFLOCK_MASK (0x2U)
#define | SEMC_STS13_REFLOCK_SHIFT (1U)
#define | SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
#define | SEMC_STS13_SLVSEL_MASK (0xFCU)
#define | SEMC_STS13_SLVSEL_SHIFT (2U)
#define | SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
#define | SEMC_STS13_REFSEL_MASK (0x3F00U)
#define | SEMC_STS13_REFSEL_SHIFT (8U)
#define | SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ SEMC_BMCR0_WAGE

#define SEMC_BMCR0_WAGE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)

WAGE - Weight of Aging

Definition at line 36580 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WAGE_MASK

#define SEMC_BMCR0_WAGE_MASK (0xF0U)

Definition at line 36576 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WAGE_SHIFT

#define SEMC_BMCR0_WAGE_SHIFT (4U)

Definition at line 36577 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WQOS

#define SEMC_BMCR0_WQOS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)

WQOS - Weight of QoS

Definition at line 36575 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WQOS_MASK

#define SEMC_BMCR0_WQOS_MASK (0xFU)

Definition at line 36571 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WQOS_SHIFT

#define SEMC_BMCR0_WQOS_SHIFT (0U)

Definition at line 36572 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WRWS

#define SEMC_BMCR0_WRWS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)

WRWS - Weight of Slave Hit (Read/Write switch)

Definition at line 36590 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WRWS_MASK

#define SEMC_BMCR0_WRWS_MASK (0xFF0000U)

Definition at line 36586 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WRWS_SHIFT

#define SEMC_BMCR0_WRWS_SHIFT (16U)

Definition at line 36587 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WSH

#define SEMC_BMCR0_WSH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)

WSH - Weight of Slave Hit (no read/write switch)

Definition at line 36585 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WSH_MASK

#define SEMC_BMCR0_WSH_MASK (0xFF00U)

Definition at line 36581 of file MIMXRT1062.h.

## ◆ SEMC_BMCR0_WSH_SHIFT

#define SEMC_BMCR0_WSH_SHIFT (8U)

Definition at line 36582 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WAGE

#define SEMC_BMCR1_WAGE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)

WAGE - Weight of Aging

Definition at line 36604 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WAGE_MASK

#define SEMC_BMCR1_WAGE_MASK (0xF0U)

Definition at line 36600 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WAGE_SHIFT

#define SEMC_BMCR1_WAGE_SHIFT (4U)

Definition at line 36601 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WBR

#define SEMC_BMCR1_WBR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)

WBR - Weight of Bank Rotation

Definition at line 36619 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WBR_MASK

#define SEMC_BMCR1_WBR_MASK (0xFF000000U)

Definition at line 36615 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WBR_SHIFT

#define SEMC_BMCR1_WBR_SHIFT (24U)

Definition at line 36616 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WPH

#define SEMC_BMCR1_WPH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)

WPH - Weight of Page Hit

Definition at line 36609 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WPH_MASK

#define SEMC_BMCR1_WPH_MASK (0xFF00U)

Definition at line 36605 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WPH_SHIFT

#define SEMC_BMCR1_WPH_SHIFT (8U)

Definition at line 36606 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WQOS

#define SEMC_BMCR1_WQOS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)

WQOS - Weight of QoS

Definition at line 36599 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WQOS_MASK

#define SEMC_BMCR1_WQOS_MASK (0xFU)

Definition at line 36595 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WQOS_SHIFT

#define SEMC_BMCR1_WQOS_SHIFT (0U)

Definition at line 36596 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WRWS

#define SEMC_BMCR1_WRWS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)

WRWS - Weight of Read/Write switch

Definition at line 36614 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WRWS_MASK

#define SEMC_BMCR1_WRWS_MASK (0xFF0000U)

Definition at line 36610 of file MIMXRT1062.h.

## ◆ SEMC_BMCR1_WRWS_SHIFT

#define SEMC_BMCR1_WRWS_SHIFT (16U)

Definition at line 36611 of file MIMXRT1062.h.

## ◆ SEMC_BR_BA

#define SEMC_BR_BA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)

BA - Base Address

Definition at line 36670 of file MIMXRT1062.h.

## ◆ SEMC_BR_BA_MASK

#define SEMC_BR_BA_MASK (0xFFFFF000U)

Definition at line 36666 of file MIMXRT1062.h.

## ◆ SEMC_BR_BA_SHIFT

#define SEMC_BR_BA_SHIFT (12U)

Definition at line 36667 of file MIMXRT1062.h.

## ◆ SEMC_BR_COUNT

#define SEMC_BR_COUNT (9U)

Definition at line 36674 of file MIMXRT1062.h.

## ◆ SEMC_BR_MS

#define SEMC_BR_MS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)

MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100..4GB 0b10101..4GB 0b10110..4GB 0b10111..4GB 0b11000..4GB 0b11001..4GB 0b11010..4GB 0b11011..4GB 0b11100..4GB 0b11101..4GB 0b11110..4GB 0b11111..4GB

Definition at line 36665 of file MIMXRT1062.h.

## ◆ SEMC_BR_MS_MASK

#define SEMC_BR_MS_MASK (0x3EU)

Definition at line 36629 of file MIMXRT1062.h.

## ◆ SEMC_BR_MS_SHIFT

#define SEMC_BR_MS_SHIFT (1U)

Definition at line 36630 of file MIMXRT1062.h.

## ◆ SEMC_BR_VLD

#define SEMC_BR_VLD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)

VLD - Valid

Definition at line 36628 of file MIMXRT1062.h.

## ◆ SEMC_BR_VLD_MASK

#define SEMC_BR_VLD_MASK (0x1U)

Definition at line 36624 of file MIMXRT1062.h.

## ◆ SEMC_BR_VLD_SHIFT

#define SEMC_BR_VLD_SHIFT (0U)

Definition at line 36625 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_BL

#define SEMC_DBICR0_BL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64

Definition at line 37458 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_BL_MASK

#define SEMC_DBICR0_BL_MASK (0x70U)

Definition at line 37446 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_BL_SHIFT

#define SEMC_DBICR0_BL_SHIFT (4U)

Definition at line 37447 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_COL

#define SEMC_DBICR0_COL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)

COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits

Definition at line 37479 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_COL_MASK

#define SEMC_DBICR0_COL_MASK (0xF000U)

Definition at line 37459 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_COL_SHIFT

#define SEMC_DBICR0_COL_SHIFT (12U)

Definition at line 37460 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_PS

#define SEMC_DBICR0_PS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 37445 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_PS_MASK

#define SEMC_DBICR0_PS_MASK (0x1U)

Definition at line 37439 of file MIMXRT1062.h.

## ◆ SEMC_DBICR0_PS_SHIFT

#define SEMC_DBICR0_PS_SHIFT (0U)

Definition at line 37440 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CEH

#define SEMC_DBICR1_CEH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)

CEH - CSX Hold Time

Definition at line 37493 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CEH_MASK

#define SEMC_DBICR1_CEH_MASK (0xF0U)

Definition at line 37489 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CEH_SHIFT

#define SEMC_DBICR1_CEH_SHIFT (4U)

Definition at line 37490 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CEITV

#define SEMC_DBICR1_CEITV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)

CEITV - CSX interval min time

Definition at line 37518 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CEITV_MASK

#define SEMC_DBICR1_CEITV_MASK (0xF0000000U)

Definition at line 37514 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CEITV_SHIFT

#define SEMC_DBICR1_CEITV_SHIFT (28U)

Definition at line 37515 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CES

#define SEMC_DBICR1_CES | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)

CES - CSX Setup Time

Definition at line 37488 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CES_MASK

#define SEMC_DBICR1_CES_MASK (0xFU)

Definition at line 37484 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_CES_SHIFT

#define SEMC_DBICR1_CES_SHIFT (0U)

Definition at line 37485 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_REH

#define SEMC_DBICR1_REH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)

REH - RDX High Time

Definition at line 37513 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_REH_MASK

#define SEMC_DBICR1_REH_MASK (0xFC00000U)

Definition at line 37509 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_REH_SHIFT

#define SEMC_DBICR1_REH_SHIFT (22U)

Definition at line 37510 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_REL

#define SEMC_DBICR1_REL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)

REL - RDX Low Time

Definition at line 37508 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_REL_MASK

#define SEMC_DBICR1_REL_MASK (0x3F0000U)

Definition at line 37504 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_REL_SHIFT

#define SEMC_DBICR1_REL_SHIFT (16U)

Definition at line 37505 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_WEH

#define SEMC_DBICR1_WEH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)

WEH - WRX High Time

Definition at line 37503 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_WEH_MASK

#define SEMC_DBICR1_WEH_MASK (0xF000U)

Definition at line 37499 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_WEH_SHIFT

#define SEMC_DBICR1_WEH_SHIFT (12U)

Definition at line 37500 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_WEL

#define SEMC_DBICR1_WEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)

WEL - WRX Low Time

Definition at line 37498 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_WEL_MASK

#define SEMC_DBICR1_WEL_MASK (0xF00U)

Definition at line 37494 of file MIMXRT1062.h.

## ◆ SEMC_DBICR1_WEL_SHIFT

#define SEMC_DBICR1_WEL_SHIFT (8U)

Definition at line 37495 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_DLLEN

#define SEMC_DLLCR_DLLEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)

DLLEN - DLL calibration enable.

Definition at line 36682 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_DLLEN_MASK

#define SEMC_DLLCR_DLLEN_MASK (0x1U)

Definition at line 36678 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_DLLEN_SHIFT

#define SEMC_DLLCR_DLLEN_SHIFT (0U)

Definition at line 36679 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_DLLRESET

#define SEMC_DLLCR_DLLRESET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)

DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).

Definition at line 36690 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_DLLRESET_MASK

#define SEMC_DLLCR_DLLRESET_MASK (0x2U)

Definition at line 36683 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_DLLRESET_SHIFT

#define SEMC_DLLCR_DLLRESET_SHIFT (1U)

Definition at line 36684 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_OVRDEN

#define SEMC_DLLCR_OVRDEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)

OVRDEN - Slave clock delay line delay cell number selection override enable.

Definition at line 36700 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_OVRDEN_MASK

#define SEMC_DLLCR_OVRDEN_MASK (0x100U)

Definition at line 36696 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_OVRDEN_SHIFT

#define SEMC_DLLCR_OVRDEN_SHIFT (8U)

Definition at line 36697 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_OVRDVAL

#define SEMC_DLLCR_OVRDVAL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)

OVRDVAL - Slave clock delay line delay cell number selection override value.

Definition at line 36705 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_OVRDVAL_MASK

#define SEMC_DLLCR_OVRDVAL_MASK (0x7E00U)

Definition at line 36701 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_OVRDVAL_SHIFT

#define SEMC_DLLCR_OVRDVAL_SHIFT (9U)

Definition at line 36702 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_SLVDLYTARGET

#define SEMC_DLLCR_SLVDLYTARGET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)

SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (ipgclock).

Definition at line 36695 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_SLVDLYTARGET_MASK

#define SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U)

Definition at line 36691 of file MIMXRT1062.h.

## ◆ SEMC_DLLCR_SLVDLYTARGET_SHIFT

#define SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U)

Definition at line 36692 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_AXIBUSERREN

#define SEMC_INTEN_AXIBUSERREN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)

AXIBUSERREN - AXI bus error interrupt enable

Definition at line 36729 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_AXIBUSERREN_MASK

#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)

Definition at line 36725 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_AXIBUSERREN_SHIFT

#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)

Definition at line 36726 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_AXICMDERREN

#define SEMC_INTEN_AXICMDERREN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)

AXICMDERREN - AXI command error interrupt enable

Definition at line 36724 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_AXICMDERREN_MASK

#define SEMC_INTEN_AXICMDERREN_MASK (0x4U)

Definition at line 36720 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_AXICMDERREN_SHIFT

#define SEMC_INTEN_AXICMDERREN_SHIFT (2U)

Definition at line 36721 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_IPCMDDONEEN

#define SEMC_INTEN_IPCMDDONEEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)

IPCMDDONEEN - IP command done interrupt enable

Definition at line 36714 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_IPCMDDONEEN_MASK

#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)

Definition at line 36710 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_IPCMDDONEEN_SHIFT

#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)

Definition at line 36711 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_IPCMDERREN

#define SEMC_INTEN_IPCMDERREN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)

IPCMDERREN - IP command error interrupt enable

Definition at line 36719 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_IPCMDERREN_MASK

#define SEMC_INTEN_IPCMDERREN_MASK (0x2U)

Definition at line 36715 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_IPCMDERREN_SHIFT

#define SEMC_INTEN_IPCMDERREN_SHIFT (1U)

Definition at line 36716 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_NDNOPENDEN

#define SEMC_INTEN_NDNOPENDEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)

NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation. 0b0..Disable 0b1..Enable

Definition at line 36743 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_NDNOPENDEN_MASK

#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)

Definition at line 36737 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_NDNOPENDEN_SHIFT

#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)

Definition at line 36738 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_NDPAGEENDEN

#define SEMC_INTEN_NDPAGEENDEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)

NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation. 0b0..Disable 0b1..Enable

Definition at line 36736 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_NDPAGEENDEN_MASK

#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)

Definition at line 36730 of file MIMXRT1062.h.

## ◆ SEMC_INTEN_NDPAGEENDEN_SHIFT

#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)

Definition at line 36731 of file MIMXRT1062.h.

## ◆ SEMC_INTR_AXIBUSERR

#define SEMC_INTR_AXIBUSERR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)

AXIBUSERR - AXI bus error interrupt

Definition at line 36767 of file MIMXRT1062.h.

## ◆ SEMC_INTR_AXIBUSERR_MASK

#define SEMC_INTR_AXIBUSERR_MASK (0x8U)

Definition at line 36763 of file MIMXRT1062.h.

## ◆ SEMC_INTR_AXIBUSERR_SHIFT

#define SEMC_INTR_AXIBUSERR_SHIFT (3U)

Definition at line 36764 of file MIMXRT1062.h.

## ◆ SEMC_INTR_AXICMDERR

#define SEMC_INTR_AXICMDERR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)

AXICMDERR - AXI command error interrupt

Definition at line 36762 of file MIMXRT1062.h.

## ◆ SEMC_INTR_AXICMDERR_MASK

#define SEMC_INTR_AXICMDERR_MASK (0x4U)

Definition at line 36758 of file MIMXRT1062.h.

## ◆ SEMC_INTR_AXICMDERR_SHIFT

#define SEMC_INTR_AXICMDERR_SHIFT (2U)

Definition at line 36759 of file MIMXRT1062.h.

## ◆ SEMC_INTR_IPCMDDONE

#define SEMC_INTR_IPCMDDONE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)

IPCMDDONE - IP command normal done interrupt

Definition at line 36752 of file MIMXRT1062.h.

## ◆ SEMC_INTR_IPCMDDONE_MASK

#define SEMC_INTR_IPCMDDONE_MASK (0x1U)

Definition at line 36748 of file MIMXRT1062.h.

## ◆ SEMC_INTR_IPCMDDONE_SHIFT

#define SEMC_INTR_IPCMDDONE_SHIFT (0U)

Definition at line 36749 of file MIMXRT1062.h.

## ◆ SEMC_INTR_IPCMDERR

#define SEMC_INTR_IPCMDERR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)

IPCMDERR - IP command error done interrupt

Definition at line 36757 of file MIMXRT1062.h.

## ◆ SEMC_INTR_IPCMDERR_MASK

#define SEMC_INTR_IPCMDERR_MASK (0x2U)

Definition at line 36753 of file MIMXRT1062.h.

## ◆ SEMC_INTR_IPCMDERR_SHIFT

#define SEMC_INTR_IPCMDERR_SHIFT (1U)

Definition at line 36754 of file MIMXRT1062.h.

## ◆ SEMC_INTR_NDNOPEND

#define SEMC_INTR_NDNOPEND | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)

NDNOPEND - This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface.

Definition at line 36777 of file MIMXRT1062.h.

## ◆ SEMC_INTR_NDNOPEND_MASK

#define SEMC_INTR_NDNOPEND_MASK (0x20U)

Definition at line 36773 of file MIMXRT1062.h.

## ◆ SEMC_INTR_NDNOPEND_SHIFT

#define SEMC_INTR_NDNOPEND_SHIFT (5U)

Definition at line 36774 of file MIMXRT1062.h.

## ◆ SEMC_INTR_NDPAGEEND

#define SEMC_INTR_NDPAGEEND | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)

NDPAGEEND - This interrupt is generated when the last address of one page in NAND device is written by AXI command

Definition at line 36772 of file MIMXRT1062.h.

## ◆ SEMC_INTR_NDPAGEEND_MASK

#define SEMC_INTR_NDPAGEEND_MASK (0x10U)

Definition at line 36768 of file MIMXRT1062.h.

## ◆ SEMC_INTR_NDPAGEEND_SHIFT

#define SEMC_INTR_NDPAGEEND_SHIFT (4U)

Definition at line 36769 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_A8

#define SEMC_IOCR_MUX_A8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)

MUX_A8 - SEMC_A8 output selection 0b000..SDRAM Address bit (A8) 0b001..NAND CE# 0b010..NOR CE# 0b011..PSRAM CE# 0b100..DBI CSX 0b101..SDRAM Address bit (A8) 0b110..SDRAM Address bit (A8) 0b111..SDRAM Address bit (A8)

Definition at line 36487 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_A8_MASK

#define SEMC_IOCR_MUX_A8_MASK (0x7U)

Definition at line 36475 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_A8_SHIFT

#define SEMC_IOCR_MUX_A8_SHIFT (0U)

Definition at line 36476 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CLKX0

#define SEMC_IOCR_MUX_CLKX0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)

MUX_CLKX0 - SEMC_CLKX0 function selection 0b0..NOR clock 0b1..SRAM clock

Definition at line 36559 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CLKX0_MASK

#define SEMC_IOCR_MUX_CLKX0_MASK (0x1000000U)

Definition at line 36553 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CLKX0_SHIFT

#define SEMC_IOCR_MUX_CLKX0_SHIFT (24U)

Definition at line 36554 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CLKX1

#define SEMC_IOCR_MUX_CLKX1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)

MUX_CLKX1 - SEMC_CLKX1 function selection 0b0..NOR clock 0b1..SRAM clock

Definition at line 36566 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CLKX1_MASK

#define SEMC_IOCR_MUX_CLKX1_MASK (0x2000000U)

Definition at line 36560 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CLKX1_SHIFT

#define SEMC_IOCR_MUX_CLKX1_SHIFT (25U)

Definition at line 36561 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX0

#define SEMC_IOCR_MUX_CSX0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)

MUX_CSX0 - SEMC_CSX0 output selection 0b000..NOR/PSRAM Address bit 24 (A24) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX

Definition at line 36500 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX0_MASK

#define SEMC_IOCR_MUX_CSX0_MASK (0x38U)

Definition at line 36488 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX0_SHIFT

#define SEMC_IOCR_MUX_CSX0_SHIFT (3U)

Definition at line 36489 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX1

#define SEMC_IOCR_MUX_CSX1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)

MUX_CSX1 - SEMC_CSX1 output selection 0b000..NOR/PSRAM Address bit 25 (A25) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX

Definition at line 36513 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX1_MASK

#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)

Definition at line 36501 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX1_SHIFT

#define SEMC_IOCR_MUX_CSX1_SHIFT (6U)

Definition at line 36502 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX2

#define SEMC_IOCR_MUX_CSX2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)

MUX_CSX2 - SEMC_CSX2 output selection 0b000..NOR/PSRAM Address bit 26 (A26) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX

Definition at line 36526 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX2_MASK

#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U)

Definition at line 36514 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX2_SHIFT

#define SEMC_IOCR_MUX_CSX2_SHIFT (9U)

Definition at line 36515 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX3

#define SEMC_IOCR_MUX_CSX3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)

MUX_CSX3 - SEMC_CSX3 output selection 0b000..NOR/PSRAM Address bit 27 (A27) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX

Definition at line 36539 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX3_MASK

#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U)

Definition at line 36527 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_CSX3_SHIFT

#define SEMC_IOCR_MUX_CSX3_SHIFT (12U)

Definition at line 36528 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_RDY

#define SEMC_IOCR_MUX_RDY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)

MUX_RDY - SEMC_RDY function selection 0b000..NAND Ready/Wait# input 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NOR CE# 0b101..PSRAM CE# 0b110..DBI CSX 0b111..NOR/PSRAM Address bit 27

Definition at line 36552 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_RDY_MASK

#define SEMC_IOCR_MUX_RDY_MASK (0x38000U)

Definition at line 36540 of file MIMXRT1062.h.

## ◆ SEMC_IOCR_MUX_RDY_SHIFT

#define SEMC_IOCR_MUX_RDY_SHIFT (15U)

Definition at line 36541 of file MIMXRT1062.h.

## ◆ SEMC_IPCMD_CMD

#define SEMC_IPCMD_CMD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)

Definition at line 37588 of file MIMXRT1062.h.

## ◆ SEMC_IPCMD_CMD_MASK

#define SEMC_IPCMD_CMD_MASK (0xFFFFU)

Definition at line 37586 of file MIMXRT1062.h.

## ◆ SEMC_IPCMD_CMD_SHIFT

#define SEMC_IPCMD_CMD_SHIFT (0U)

Definition at line 37587 of file MIMXRT1062.h.

## ◆ SEMC_IPCMD_KEY

#define SEMC_IPCMD_KEY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)

Definition at line 37591 of file MIMXRT1062.h.

## ◆ SEMC_IPCMD_KEY_MASK

#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)

Definition at line 37589 of file MIMXRT1062.h.

## ◆ SEMC_IPCMD_KEY_SHIFT

#define SEMC_IPCMD_KEY_SHIFT (16U)

Definition at line 37590 of file MIMXRT1062.h.

## ◆ SEMC_IPCR0_SA

#define SEMC_IPCR0_SA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)

SA - Slave address

Definition at line 37527 of file MIMXRT1062.h.

## ◆ SEMC_IPCR0_SA_MASK

#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)

Definition at line 37523 of file MIMXRT1062.h.

## ◆ SEMC_IPCR0_SA_SHIFT

#define SEMC_IPCR0_SA_SHIFT (0U)

Definition at line 37524 of file MIMXRT1062.h.

## ◆ SEMC_IPCR1_DATSZ

#define SEMC_IPCR1_DATSZ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)

DATSZ - Data Size in Byte 0b000..4 0b001..1 0b010..2 0b011..3 0b100..4 0b101..4 0b110..4 0b111..4

Definition at line 37544 of file MIMXRT1062.h.

## ◆ SEMC_IPCR1_DATSZ_MASK

#define SEMC_IPCR1_DATSZ_MASK (0x7U)

Definition at line 37532 of file MIMXRT1062.h.

## ◆ SEMC_IPCR1_DATSZ_SHIFT

#define SEMC_IPCR1_DATSZ_SHIFT (0U)

Definition at line 37533 of file MIMXRT1062.h.

## ◆ SEMC_IPCR1_NAND_EXT_ADDR

#define SEMC_IPCR1_NAND_EXT_ADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)

NAND_EXT_ADDR - NAND Extended Address

Definition at line 37549 of file MIMXRT1062.h.

## ◆ SEMC_IPCR1_NAND_EXT_ADDR_MASK

#define SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U)

Definition at line 37545 of file MIMXRT1062.h.

## ◆ SEMC_IPCR1_NAND_EXT_ADDR_SHIFT

#define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U)

Definition at line 37546 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM0

#define SEMC_IPCR2_BM0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)

BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) 0b0..Byte Unmasked 0b1..Byte Masked

Definition at line 37560 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM0_MASK

#define SEMC_IPCR2_BM0_MASK (0x1U)

Definition at line 37554 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM0_SHIFT

#define SEMC_IPCR2_BM0_SHIFT (0U)

Definition at line 37555 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM1

#define SEMC_IPCR2_BM1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)

BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) 0b0..Byte Unmasked 0b1..Byte Masked

Definition at line 37567 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM1_MASK

#define SEMC_IPCR2_BM1_MASK (0x2U)

Definition at line 37561 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM1_SHIFT

#define SEMC_IPCR2_BM1_SHIFT (1U)

Definition at line 37562 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM2

#define SEMC_IPCR2_BM2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)

BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) 0b0..Byte Unmasked 0b1..Byte Masked

Definition at line 37574 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM2_MASK

#define SEMC_IPCR2_BM2_MASK (0x4U)

Definition at line 37568 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM2_SHIFT

#define SEMC_IPCR2_BM2_SHIFT (2U)

Definition at line 37569 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM3

#define SEMC_IPCR2_BM3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)

BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) 0b0..Byte Unmasked 0b1..Byte Masked

Definition at line 37581 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM3_MASK

#define SEMC_IPCR2_BM3_MASK (0x8U)

Definition at line 37575 of file MIMXRT1062.h.

## ◆ SEMC_IPCR2_BM3_SHIFT

#define SEMC_IPCR2_BM3_SHIFT (3U)

Definition at line 37576 of file MIMXRT1062.h.

## ◆ SEMC_IPRXDAT_DAT

#define SEMC_IPRXDAT_DAT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)

Definition at line 37605 of file MIMXRT1062.h.

## ◆ SEMC_IPRXDAT_DAT_MASK

#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)

Definition at line 37603 of file MIMXRT1062.h.

## ◆ SEMC_IPRXDAT_DAT_SHIFT

#define SEMC_IPRXDAT_DAT_SHIFT (0U)

Definition at line 37604 of file MIMXRT1062.h.

## ◆ SEMC_IPTXDAT_DAT

#define SEMC_IPTXDAT_DAT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)

Definition at line 37598 of file MIMXRT1062.h.

## ◆ SEMC_IPTXDAT_DAT_MASK

#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)

Definition at line 37596 of file MIMXRT1062.h.

## ◆ SEMC_IPTXDAT_DAT_SHIFT

#define SEMC_IPTXDAT_DAT_SHIFT (0U)

Definition at line 37597 of file MIMXRT1062.h.

## ◆ SEMC_MCR_BTO

#define SEMC_MCR_BTO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)

BTO - Bus timeout cycles 0b00000..255*1 0b00001-0b11110..255*2 - 255*2^30 0b11111..255*2^31

Definition at line 36470 of file MIMXRT1062.h.

## ◆ SEMC_MCR_BTO_MASK

#define SEMC_MCR_BTO_MASK (0x1F000000U)

Definition at line 36463 of file MIMXRT1062.h.

## ◆ SEMC_MCR_BTO_SHIFT

#define SEMC_MCR_BTO_SHIFT (24U)

Definition at line 36464 of file MIMXRT1062.h.

## ◆ SEMC_MCR_CTO

#define SEMC_MCR_CTO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)

CTO - Command Execution timeout cycles

Definition at line 36462 of file MIMXRT1062.h.

## ◆ SEMC_MCR_CTO_MASK

#define SEMC_MCR_CTO_MASK (0xFF0000U)

Definition at line 36458 of file MIMXRT1062.h.

## ◆ SEMC_MCR_CTO_SHIFT

#define SEMC_MCR_CTO_SHIFT (16U)

Definition at line 36459 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DLLSEL

#define SEMC_MCR_DLLSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DLLSEL_SHIFT)) & SEMC_MCR_DLLSEL_MASK)

DLLSEL - Select DLL delay chain clock input. 0b0..DLL delay chain clock input is from NAND device's DQS pad. For NAND synchronous mode only. 0b1..DLL delay chain clock input is from internal clock. For SDRAM, NOR and SRAM synchronous mode only.

Definition at line 36457 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DLLSEL_MASK

#define SEMC_MCR_DLLSEL_MASK (0x800U)

Definition at line 36451 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DLLSEL_SHIFT

#define SEMC_MCR_DLLSEL_SHIFT (11U)

Definition at line 36452 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DQSMD

#define SEMC_MCR_DQSMD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)

DQSMD - DQS (read strobe) mode 0b0..Dummy read strobe loopbacked internally 0b1..Dummy read strobe loopbacked from DQS pad or DLL delay chain. Details information at descriptions of DQSSEL bit.

Definition at line 36429 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DQSMD_MASK

#define SEMC_MCR_DQSMD_MASK (0x4U)

Definition at line 36423 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DQSMD_SHIFT

#define SEMC_MCR_DQSMD_SHIFT (2U)

Definition at line 36424 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DQSSEL

#define SEMC_MCR_DQSSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSSEL_SHIFT)) & SEMC_MCR_DQSSEL_MASK)

DQSSEL - Select DQS source when DQSMD and DLLSEL both set. 0b0..SDRAM/NOR/SRAM read clock source is from DQS pad in synchronous mode. 0b1..SDRAM/NOR/SRAM read clock source is from DLL delay chain in synchronous mode.

Definition at line 36450 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DQSSEL_MASK

#define SEMC_MCR_DQSSEL_MASK (0x400U)

Definition at line 36444 of file MIMXRT1062.h.

## ◆ SEMC_MCR_DQSSEL_SHIFT

#define SEMC_MCR_DQSSEL_SHIFT (10U)

Definition at line 36445 of file MIMXRT1062.h.

## ◆ SEMC_MCR_MDIS

#define SEMC_MCR_MDIS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Module enabled 0b1..Module disabled.

Definition at line 36422 of file MIMXRT1062.h.

## ◆ SEMC_MCR_MDIS_MASK

#define SEMC_MCR_MDIS_MASK (0x2U)

Definition at line 36416 of file MIMXRT1062.h.

## ◆ SEMC_MCR_MDIS_SHIFT

#define SEMC_MCR_MDIS_SHIFT (1U)

Definition at line 36417 of file MIMXRT1062.h.

## ◆ SEMC_MCR_SWRST

#define SEMC_MCR_SWRST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)

SWRST - Software Reset

Definition at line 36415 of file MIMXRT1062.h.

## ◆ SEMC_MCR_SWRST_MASK

#define SEMC_MCR_SWRST_MASK (0x1U)

Definition at line 36411 of file MIMXRT1062.h.

## ◆ SEMC_MCR_SWRST_SHIFT

#define SEMC_MCR_SWRST_SHIFT (0U)

Definition at line 36412 of file MIMXRT1062.h.

## ◆ SEMC_MCR_WPOL0

#define SEMC_MCR_WPOL0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)

WPOL0 - WAIT/RDY# polarity for NOR/PSRAM 0b0..Low active 0b1..High active

Definition at line 36436 of file MIMXRT1062.h.

## ◆ SEMC_MCR_WPOL0_MASK

#define SEMC_MCR_WPOL0_MASK (0x40U)

Definition at line 36430 of file MIMXRT1062.h.

## ◆ SEMC_MCR_WPOL0_SHIFT

#define SEMC_MCR_WPOL0_SHIFT (6U)

Definition at line 36431 of file MIMXRT1062.h.

## ◆ SEMC_MCR_WPOL1

#define SEMC_MCR_WPOL1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)

WPOL1 - WAIT/RDY# polarity for NAND 0b0..Low active 0b1..High active

Definition at line 36443 of file MIMXRT1062.h.

## ◆ SEMC_MCR_WPOL1_MASK

#define SEMC_MCR_WPOL1_MASK (0x80U)

Definition at line 36437 of file MIMXRT1062.h.

## ◆ SEMC_MCR_WPOL1_SHIFT

#define SEMC_MCR_WPOL1_SHIFT (7U)

Definition at line 36438 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_BL

#define SEMC_NANDCR0_BL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64

Definition at line 36967 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_BL_MASK

#define SEMC_NANDCR0_BL_MASK (0x70U)

Definition at line 36955 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_BL_SHIFT

#define SEMC_NANDCR0_BL_SHIFT (4U)

Definition at line 36956 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_COL

#define SEMC_NANDCR0_COL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)

COL - Column address bit number 0b000..16 0b001..15 0b010..14 0b011..13 0b100..12 0b101..11 0b110..10 0b111..9

Definition at line 36987 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_COL_MASK

#define SEMC_NANDCR0_COL_MASK (0x700U)

Definition at line 36975 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_COL_SHIFT

#define SEMC_NANDCR0_COL_SHIFT (8U)

Definition at line 36976 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_EDO

#define SEMC_NANDCR0_EDO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)

EDO - EDO mode enabled 0b0..EDO mode disabled 0b1..EDO mode enabled

Definition at line 36974 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_EDO_MASK

#define SEMC_NANDCR0_EDO_MASK (0x80U)

Definition at line 36968 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_EDO_SHIFT

#define SEMC_NANDCR0_EDO_SHIFT (7U)

Definition at line 36969 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_PS

#define SEMC_NANDCR0_PS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 36947 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_PS_MASK

#define SEMC_NANDCR0_PS_MASK (0x1U)

Definition at line 36941 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_PS_SHIFT

#define SEMC_NANDCR0_PS_SHIFT (0U)

Definition at line 36942 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_SYNCEN

#define SEMC_NANDCR0_SYNCEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)

SYNCEN - Select NAND controller mode. 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled.

Definition at line 36954 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_SYNCEN_MASK

#define SEMC_NANDCR0_SYNCEN_MASK (0x2U)

Definition at line 36948 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR0_SYNCEN_SHIFT

#define SEMC_NANDCR0_SYNCEN_SHIFT (1U)

Definition at line 36949 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CEH

#define SEMC_NANDCR1_CEH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)

CEH - CE hold time

Definition at line 37001 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CEH_MASK

#define SEMC_NANDCR1_CEH_MASK (0xF0U)

Definition at line 36997 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CEH_SHIFT

#define SEMC_NANDCR1_CEH_SHIFT (4U)

Definition at line 36998 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CEITV

#define SEMC_NANDCR1_CEITV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)

CEITV - CE# interval time

Definition at line 37031 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CEITV_MASK

#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)

Definition at line 37027 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CEITV_SHIFT

#define SEMC_NANDCR1_CEITV_SHIFT (28U)

Definition at line 37028 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CES

#define SEMC_NANDCR1_CES | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)

CES - CE setup time

Definition at line 36996 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CES_MASK

#define SEMC_NANDCR1_CES_MASK (0xFU)

Definition at line 36992 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_CES_SHIFT

#define SEMC_NANDCR1_CES_SHIFT (0U)

Definition at line 36993 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_REH

#define SEMC_NANDCR1_REH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)

REH - RE# HIGH time

Definition at line 37021 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_REH_MASK

#define SEMC_NANDCR1_REH_MASK (0xF00000U)

Definition at line 37017 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_REH_SHIFT

#define SEMC_NANDCR1_REH_SHIFT (20U)

Definition at line 37018 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_REL

#define SEMC_NANDCR1_REL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)

REL - RE# LOW time

Definition at line 37016 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_REL_MASK

#define SEMC_NANDCR1_REL_MASK (0xF0000U)

Definition at line 37012 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_REL_SHIFT

#define SEMC_NANDCR1_REL_SHIFT (16U)

Definition at line 37013 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_TA

#define SEMC_NANDCR1_TA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)

TA - Turnaround time

Definition at line 37026 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_TA_MASK

#define SEMC_NANDCR1_TA_MASK (0xF000000U)

Definition at line 37022 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_TA_SHIFT

#define SEMC_NANDCR1_TA_SHIFT (24U)

Definition at line 37023 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_WEH

#define SEMC_NANDCR1_WEH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)

WEH - WE# HIGH time

Definition at line 37011 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_WEH_MASK

#define SEMC_NANDCR1_WEH_MASK (0xF000U)

Definition at line 37007 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_WEH_SHIFT

#define SEMC_NANDCR1_WEH_SHIFT (12U)

Definition at line 37008 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_WEL

#define SEMC_NANDCR1_WEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)

WEL - WE# LOW time

Definition at line 37006 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_WEL_MASK

#define SEMC_NANDCR1_WEL_MASK (0xF00U)

Definition at line 37002 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR1_WEL_SHIFT

#define SEMC_NANDCR1_WEL_SHIFT (8U)

Definition at line 37003 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TADL

#define SEMC_NANDCR2_TADL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)

TADL - ALE to WRITE Data start wait time

Definition at line 37050 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TADL_MASK

#define SEMC_NANDCR2_TADL_MASK (0x3F000U)

Definition at line 37046 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TADL_SHIFT

#define SEMC_NANDCR2_TADL_SHIFT (12U)

Definition at line 37047 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TRHW

#define SEMC_NANDCR2_TRHW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)

TRHW - RE# HIGH to WE# LOW wait time

Definition at line 37045 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TRHW_MASK

#define SEMC_NANDCR2_TRHW_MASK (0xFC0U)

Definition at line 37041 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TRHW_SHIFT

#define SEMC_NANDCR2_TRHW_SHIFT (6U)

Definition at line 37042 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TRR

#define SEMC_NANDCR2_TRR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)

TRR - Ready to RE# LOW min wait time

Definition at line 37055 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TRR_MASK

#define SEMC_NANDCR2_TRR_MASK (0xFC0000U)

Definition at line 37051 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TRR_SHIFT

#define SEMC_NANDCR2_TRR_SHIFT (18U)

Definition at line 37052 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TWB

#define SEMC_NANDCR2_TWB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)

TWB - WE# HIGH to busy wait time

Definition at line 37060 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TWB_MASK

#define SEMC_NANDCR2_TWB_MASK (0x3F000000U)

Definition at line 37056 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TWB_SHIFT

#define SEMC_NANDCR2_TWB_SHIFT (24U)

Definition at line 37057 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TWHR

#define SEMC_NANDCR2_TWHR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)

TWHR - WE# HIGH to RE# LOW wait time

Definition at line 37040 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TWHR_MASK

#define SEMC_NANDCR2_TWHR_MASK (0x3FU)

Definition at line 37036 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR2_TWHR_SHIFT

#define SEMC_NANDCR2_TWHR_SHIFT (0U)

Definition at line 37037 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_CLE

#define SEMC_NANDCR3_CLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)

CLE - NAND CLE Option

Definition at line 37084 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_CLE_MASK

#define SEMC_NANDCR3_CLE_MASK (0x8U)

Definition at line 37080 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_CLE_SHIFT

#define SEMC_NANDCR3_CLE_SHIFT (3U)

Definition at line 37081 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT1

#define SEMC_NANDCR3_NDOPT1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)

NDOPT1 - NAND option bit 1

Definition at line 37069 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT1_MASK

#define SEMC_NANDCR3_NDOPT1_MASK (0x1U)

Definition at line 37065 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT1_SHIFT

#define SEMC_NANDCR3_NDOPT1_SHIFT (0U)

Definition at line 37066 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT2

#define SEMC_NANDCR3_NDOPT2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)

NDOPT2 - NAND option bit 2

Definition at line 37074 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT2_MASK

#define SEMC_NANDCR3_NDOPT2_MASK (0x2U)

Definition at line 37070 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT2_SHIFT

#define SEMC_NANDCR3_NDOPT2_SHIFT (1U)

Definition at line 37071 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT3

#define SEMC_NANDCR3_NDOPT3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)

NDOPT3 - NAND option bit 3

Definition at line 37079 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT3_MASK

#define SEMC_NANDCR3_NDOPT3_MASK (0x4U)

Definition at line 37075 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_NDOPT3_SHIFT

#define SEMC_NANDCR3_NDOPT3_SHIFT (2U)

Definition at line 37076 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_RDH

#define SEMC_NANDCR3_RDH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)

RDH - Read Data Hold cycle time.

Definition at line 37094 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_RDH_MASK

#define SEMC_NANDCR3_RDH_MASK (0xF00000U)

Definition at line 37090 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_RDH_SHIFT

#define SEMC_NANDCR3_RDH_SHIFT (20U)

Definition at line 37091 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_RDS

#define SEMC_NANDCR3_RDS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)

RDS - Read Data Setup cycle time.

Definition at line 37089 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_RDS_MASK

#define SEMC_NANDCR3_RDS_MASK (0xF0000U)

Definition at line 37085 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_RDS_SHIFT

#define SEMC_NANDCR3_RDS_SHIFT (16U)

Definition at line 37086 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_WDH

#define SEMC_NANDCR3_WDH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)

WDH - Write Data Hold cycle time.

Definition at line 37104 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_WDH_MASK

#define SEMC_NANDCR3_WDH_MASK (0xF0000000U)

Definition at line 37100 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_WDH_SHIFT

#define SEMC_NANDCR3_WDH_SHIFT (28U)

Definition at line 37101 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_WDS

#define SEMC_NANDCR3_WDS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)

WDS - Write Data Setup cycle time.

Definition at line 37099 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_WDS_MASK

#define SEMC_NANDCR3_WDS_MASK (0xF000000U)

Definition at line 37095 of file MIMXRT1062.h.

## ◆ SEMC_NANDCR3_WDS_SHIFT

#define SEMC_NANDCR3_WDS_SHIFT (24U)

Definition at line 37096 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_ADVH

#define SEMC_NORCR0_ADVH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)

ADVH - ADV# level control during address hold state 0b0..ADV# is high during address hold state. 0b1..ADV# is low during address hold state.

Definition at line 37158 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_ADVH_MASK

#define SEMC_NORCR0_ADVH_MASK (0x800U)

Definition at line 37152 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_ADVH_SHIFT

#define SEMC_NORCR0_ADVH_SHIFT (11U)

Definition at line 37153 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_ADVP

#define SEMC_NORCR0_ADVP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)

ADVP - ADV# polarity 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.

Definition at line 37151 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_ADVP_MASK

#define SEMC_NORCR0_ADVP_MASK (0x400U)

Definition at line 37145 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_ADVP_SHIFT

#define SEMC_NORCR0_ADVP_SHIFT (10U)

Definition at line 37146 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_AM

#define SEMC_NORCR0_AM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)

AM - Address Mode 0b00..Address/Data MUX mode 0b01..Advanced Address/Data MUX mode 0b10..Address/Data non-MUX mode 0b11..Address/Data non-MUX mode

Definition at line 37144 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_AM_MASK

#define SEMC_NORCR0_AM_MASK (0x300U)

Definition at line 37136 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_AM_SHIFT

#define SEMC_NORCR0_AM_SHIFT (8U)

Definition at line 37137 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_BL

#define SEMC_NORCR0_BL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64

Definition at line 37135 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_BL_MASK

#define SEMC_NORCR0_BL_MASK (0x70U)

Definition at line 37123 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_BL_SHIFT

#define SEMC_NORCR0_BL_SHIFT (4U)

Definition at line 37124 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_COL

#define SEMC_NORCR0_COL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)

COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits

Definition at line 37179 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_COL_MASK

#define SEMC_NORCR0_COL_MASK (0xF000U)

Definition at line 37159 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_COL_SHIFT

#define SEMC_NORCR0_COL_SHIFT (12U)

Definition at line 37160 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_PS

#define SEMC_NORCR0_PS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 37115 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_PS_MASK

#define SEMC_NORCR0_PS_MASK (0x1U)

Definition at line 37109 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_PS_SHIFT

#define SEMC_NORCR0_PS_SHIFT (0U)

Definition at line 37110 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_SYNCEN

#define SEMC_NORCR0_SYNCEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)

SYNCEN - Select NOR controller mode. 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled.

Definition at line 37122 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_SYNCEN_MASK

#define SEMC_NORCR0_SYNCEN_MASK (0x2U)

Definition at line 37116 of file MIMXRT1062.h.

## ◆ SEMC_NORCR0_SYNCEN_SHIFT

#define SEMC_NORCR0_SYNCEN_SHIFT (1U)

Definition at line 37117 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_AH

#define SEMC_NORCR1_AH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)

AH - Address hold time

Definition at line 37203 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_AH_MASK

#define SEMC_NORCR1_AH_MASK (0xF000U)

Definition at line 37199 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_AH_SHIFT

#define SEMC_NORCR1_AH_SHIFT (12U)

Definition at line 37200 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_AS

#define SEMC_NORCR1_AS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)

AS - Address setup time

Definition at line 37198 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_AS_MASK

#define SEMC_NORCR1_AS_MASK (0xF00U)

Definition at line 37194 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_AS_SHIFT

#define SEMC_NORCR1_AS_SHIFT (8U)

Definition at line 37195 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_CEH

#define SEMC_NORCR1_CEH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)

CEH - CE hold min time (CEH+1) cycle

Definition at line 37193 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_CEH_MASK

#define SEMC_NORCR1_CEH_MASK (0xF0U)

Definition at line 37189 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_CEH_SHIFT

#define SEMC_NORCR1_CEH_SHIFT (4U)

Definition at line 37190 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_CES

#define SEMC_NORCR1_CES | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)

CES - CE setup time cycle

Definition at line 37188 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_CES_MASK

#define SEMC_NORCR1_CES_MASK (0xFU)

Definition at line 37184 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_CES_SHIFT

#define SEMC_NORCR1_CES_SHIFT (0U)

Definition at line 37185 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_REH

#define SEMC_NORCR1_REH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)

REH - RE HIGH time (REH+1) cycle

Definition at line 37223 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_REH_MASK

#define SEMC_NORCR1_REH_MASK (0xF0000000U)

Definition at line 37219 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_REH_SHIFT

#define SEMC_NORCR1_REH_SHIFT (28U)

Definition at line 37220 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_REL

#define SEMC_NORCR1_REL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)

REL - RE LOW time (REL+1) cycle

Definition at line 37218 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_REL_MASK

#define SEMC_NORCR1_REL_MASK (0xF000000U)

Definition at line 37214 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_REL_SHIFT

#define SEMC_NORCR1_REL_SHIFT (24U)

Definition at line 37215 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_WEH

#define SEMC_NORCR1_WEH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)

WEH - WE HIGH time (WEH+1) cycle

Definition at line 37213 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_WEH_MASK

#define SEMC_NORCR1_WEH_MASK (0xF00000U)

Definition at line 37209 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_WEH_SHIFT

#define SEMC_NORCR1_WEH_SHIFT (20U)

Definition at line 37210 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_WEL

#define SEMC_NORCR1_WEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)

WEL - WE LOW time (WEL+1) cycle

Definition at line 37208 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_WEL_MASK

#define SEMC_NORCR1_WEL_MASK (0xF0000U)

Definition at line 37204 of file MIMXRT1062.h.

## ◆ SEMC_NORCR1_WEL_SHIFT

#define SEMC_NORCR1_WEL_SHIFT (16U)

Definition at line 37205 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_AWDH

#define SEMC_NORCR2_AWDH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)

AWDH - Address to write data hold time cycle

Definition at line 37237 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_AWDH_MASK

#define SEMC_NORCR2_AWDH_MASK (0xF000U)

Definition at line 37233 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_AWDH_SHIFT

#define SEMC_NORCR2_AWDH_SHIFT (12U)

Definition at line 37234 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_CEITV

#define SEMC_NORCR2_CEITV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)

CEITV - CE# interval min time

Definition at line 37252 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_CEITV_MASK

#define SEMC_NORCR2_CEITV_MASK (0xF000000U)

Definition at line 37248 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_CEITV_SHIFT

#define SEMC_NORCR2_CEITV_SHIFT (24U)

Definition at line 37249 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_LC

#define SEMC_NORCR2_LC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)

LC - Latency count

Definition at line 37242 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_LC_MASK

#define SEMC_NORCR2_LC_MASK (0xF0000U)

Definition at line 37238 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_LC_SHIFT

#define SEMC_NORCR2_LC_SHIFT (16U)

Definition at line 37239 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_RD

#define SEMC_NORCR2_RD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)

RD - Read cycle time

Definition at line 37247 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_RD_MASK

#define SEMC_NORCR2_RD_MASK (0xF00000U)

Definition at line 37243 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_RD_SHIFT

#define SEMC_NORCR2_RD_SHIFT (20U)

Definition at line 37244 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_RDH

#define SEMC_NORCR2_RDH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)

RDH - Read cycle hold time

Definition at line 37257 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_RDH_MASK

#define SEMC_NORCR2_RDH_MASK (0xF0000000U)

Definition at line 37253 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_RDH_SHIFT

#define SEMC_NORCR2_RDH_SHIFT (28U)

Definition at line 37254 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_TA

#define SEMC_NORCR2_TA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)

TA - Turnaround time cycle

Definition at line 37232 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_TA_MASK

#define SEMC_NORCR2_TA_MASK (0xF00U)

Definition at line 37228 of file MIMXRT1062.h.

## ◆ SEMC_NORCR2_TA_SHIFT

#define SEMC_NORCR2_TA_SHIFT (8U)

Definition at line 37229 of file MIMXRT1062.h.

## ◆ SEMC_NORCR3_AHSR

#define SEMC_NORCR3_AHSR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)

AHSR - Address hold time for synchronous read

Definition at line 37271 of file MIMXRT1062.h.

## ◆ SEMC_NORCR3_AHSR_MASK

#define SEMC_NORCR3_AHSR_MASK (0xF0U)

Definition at line 37267 of file MIMXRT1062.h.

## ◆ SEMC_NORCR3_AHSR_SHIFT

#define SEMC_NORCR3_AHSR_SHIFT (4U)

Definition at line 37268 of file MIMXRT1062.h.

## ◆ SEMC_NORCR3_ASSR

#define SEMC_NORCR3_ASSR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)

ASSR - Address setup time for synchronous read

Definition at line 37266 of file MIMXRT1062.h.

## ◆ SEMC_NORCR3_ASSR_MASK

#define SEMC_NORCR3_ASSR_MASK (0xFU)

Definition at line 37262 of file MIMXRT1062.h.

## ◆ SEMC_NORCR3_ASSR_SHIFT

#define SEMC_NORCR3_ASSR_SHIFT (0U)

Definition at line 37263 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_BANK2

#define SEMC_SDRAMCR0_BANK2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)

BANK2 - 2 Bank selection bit 0b0..SDRAM device has 4 banks. 0b1..SDRAM device has 2 banks.

Definition at line 36833 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_BANK2_MASK

#define SEMC_SDRAMCR0_BANK2_MASK (0x4000U)

Definition at line 36827 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_BANK2_SHIFT

#define SEMC_SDRAMCR0_BANK2_SHIFT (14U)

Definition at line 36828 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_BL

#define SEMC_SDRAMCR0_BL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..8 0b101..8 0b110..8 0b111..8

Definition at line 36801 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_BL_MASK

#define SEMC_SDRAMCR0_BL_MASK (0x70U)

Definition at line 36789 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_BL_SHIFT

#define SEMC_SDRAMCR0_BL_SHIFT (4U)

Definition at line 36790 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_CL

#define SEMC_SDRAMCR0_CL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)

CL - CAS Latency 0b00..1 0b01..1 0b10..2 0b11..3

Definition at line 36826 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_CL_MASK

#define SEMC_SDRAMCR0_CL_MASK (0xC00U)

Definition at line 36818 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_CL_SHIFT

#define SEMC_SDRAMCR0_CL_SHIFT (10U)

Definition at line 36819 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_COL

#define SEMC_SDRAMCR0_COL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)

COL - Column address bit number 0b00..12 bit 0b01..11 bit 0b10..10 bit 0b11..9 bit

Definition at line 36817 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_COL8

#define SEMC_SDRAMCR0_COL8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)

COL8 - Column 8 selection bit 0b0..Column address bit number is decided by COL field. 0b1..Column address bit number is 8. COL field is ignored.

Definition at line 36808 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_COL8_MASK

#define SEMC_SDRAMCR0_COL8_MASK (0x80U)

Definition at line 36802 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_COL8_SHIFT

#define SEMC_SDRAMCR0_COL8_SHIFT (7U)

Definition at line 36803 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_COL_MASK

#define SEMC_SDRAMCR0_COL_MASK (0x300U)

Definition at line 36809 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_COL_SHIFT

#define SEMC_SDRAMCR0_COL_SHIFT (8U)

Definition at line 36810 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_PS

#define SEMC_SDRAMCR0_PS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 36788 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_PS_MASK

#define SEMC_SDRAMCR0_PS_MASK (0x1U)

Definition at line 36782 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR0_PS_SHIFT

#define SEMC_SDRAMCR0_PS_SHIFT (0U)

Definition at line 36783 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_ACT2PRE

#define SEMC_SDRAMCR1_ACT2PRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)

ACT2PRE - ACT to Precharge minimum time

Definition at line 36867 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_ACT2PRE_MASK

#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)

Definition at line 36863 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_ACT2PRE_SHIFT

#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)

Definition at line 36864 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_ACT2RW

#define SEMC_SDRAMCR1_ACT2RW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)

ACT2RW - ACT to Read/Write wait time

Definition at line 36847 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_ACT2RW_MASK

#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)

Definition at line 36843 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_ACT2RW_SHIFT

#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)

Definition at line 36844 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_CKEOFF

#define SEMC_SDRAMCR1_CKEOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)

CKEOFF - CKE OFF minimum time

Definition at line 36862 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_CKEOFF_MASK

#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)

Definition at line 36858 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_CKEOFF_SHIFT

#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)

Definition at line 36859 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_PRE2ACT

#define SEMC_SDRAMCR1_PRE2ACT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)

PRE2ACT - PRECHARGE to ACT/Refresh wait time

Definition at line 36842 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_PRE2ACT_MASK

#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)

Definition at line 36838 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_PRE2ACT_SHIFT

#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)

Definition at line 36839 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_RFRC

#define SEMC_SDRAMCR1_RFRC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)

RFRC - Refresh recovery time

Definition at line 36852 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_RFRC_MASK

#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)

Definition at line 36848 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_RFRC_SHIFT

#define SEMC_SDRAMCR1_RFRC_SHIFT (8U)

Definition at line 36849 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_WRC

#define SEMC_SDRAMCR1_WRC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)

WRC - Write recovery time

Definition at line 36857 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_WRC_MASK

#define SEMC_SDRAMCR1_WRC_MASK (0xE000U)

Definition at line 36853 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR1_WRC_SHIFT

#define SEMC_SDRAMCR1_WRC_SHIFT (13U)

Definition at line 36854 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_ACT2ACT

#define SEMC_SDRAMCR2_ACT2ACT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)

ACT2ACT - ACT to ACT wait time

Definition at line 36886 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_ACT2ACT_MASK

#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)

Definition at line 36882 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_ACT2ACT_SHIFT

#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)

Definition at line 36883 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_ITO

#define SEMC_SDRAMCR2_ITO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)

ITO - SDRAM Idle timeout 0b00000000..IDLE timeout period is 256*Prescale period. 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.

Definition at line 36893 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_ITO_MASK

#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)

Definition at line 36887 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_ITO_SHIFT

#define SEMC_SDRAMCR2_ITO_SHIFT (24U)

Definition at line 36888 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_REF2REF

#define SEMC_SDRAMCR2_REF2REF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)

REF2REF - Refresh to Refresh wait time

Definition at line 36881 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_REF2REF_MASK

#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)

Definition at line 36877 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_REF2REF_SHIFT

#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)

Definition at line 36878 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_SRRC

#define SEMC_SDRAMCR2_SRRC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)

SRRC - Self Refresh Recovery time

Definition at line 36876 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_SRRC_MASK

#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)

Definition at line 36872 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR2_SRRC_SHIFT

#define SEMC_SDRAMCR2_SRRC_SHIFT (0U)

Definition at line 36873 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_PRESCALE

#define SEMC_SDRAMCR3_PRESCALE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)

PRESCALE - Prescaler timer period 0b00000000..256*16 cycle 0b00000001-0b11111111..PRESCALE*16 cycle

Definition at line 36922 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_PRESCALE_MASK

#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)

Definition at line 36916 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_PRESCALE_SHIFT

#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)

Definition at line 36917 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_REBL

#define SEMC_SDRAMCR3_REBL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)

REBL - Refresh burst length 0b000..1 0b001..2 0b010..3 0b011..4 0b100..5 0b101..6 0b110..7 0b111..8

Definition at line 36915 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_REBL_MASK

#define SEMC_SDRAMCR3_REBL_MASK (0xEU)

Definition at line 36903 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_REBL_SHIFT

#define SEMC_SDRAMCR3_REBL_SHIFT (1U)

Definition at line 36904 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_REN

#define SEMC_SDRAMCR3_REN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)

REN - Refresh enable

Definition at line 36902 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_REN_MASK

#define SEMC_SDRAMCR3_REN_MASK (0x1U)

Definition at line 36898 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_REN_SHIFT

#define SEMC_SDRAMCR3_REN_SHIFT (0U)

Definition at line 36899 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_RT

#define SEMC_SDRAMCR3_RT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)

RT - Refresh timer period 0b00000000..256*Prescaler period 0b00000001-0b11111111..RT*Prescaler period

Definition at line 36929 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_RT_MASK

#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)

Definition at line 36923 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_RT_SHIFT

#define SEMC_SDRAMCR3_RT_SHIFT (16U)

Definition at line 36924 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_UT

#define SEMC_SDRAMCR3_UT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)

UT - Refresh urgent threshold 0b00000000..256*Prescaler period 0b00000001-0b11111111..UT*Prescaler period

Definition at line 36936 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_UT_MASK

#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)

Definition at line 36930 of file MIMXRT1062.h.

## ◆ SEMC_SDRAMCR3_UT_SHIFT

#define SEMC_SDRAMCR3_UT_SHIFT (24U)

Definition at line 36931 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_ADVH

#define SEMC_SRAMCR0_ADVH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)

ADVH - ADV# level control during address hold state 0b0..ADV# is high during address hold state. 0b1..ADV# is low during address hold state.

Definition at line 37325 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_ADVH_MASK

#define SEMC_SRAMCR0_ADVH_MASK (0x800U)

Definition at line 37319 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_ADVH_SHIFT

#define SEMC_SRAMCR0_ADVH_SHIFT (11U)

Definition at line 37320 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_ADVP

#define SEMC_SRAMCR0_ADVP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)

ADVP - ADV# polarity 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.

Definition at line 37318 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_ADVP_MASK

#define SEMC_SRAMCR0_ADVP_MASK (0x400U)

Definition at line 37312 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_ADVP_SHIFT

#define SEMC_SRAMCR0_ADVP_SHIFT (10U)

Definition at line 37313 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_AM

#define SEMC_SRAMCR0_AM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)

AM - Address Mode 0b00..Address/Data MUX mode 0b01..Advanced Address/Data MUX mode 0b10..Address/Data non-MUX mode 0b11..Address/Data non-MUX mode

Definition at line 37311 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_AM_MASK

#define SEMC_SRAMCR0_AM_MASK (0x300U)

Definition at line 37303 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_AM_SHIFT

#define SEMC_SRAMCR0_AM_SHIFT (8U)

Definition at line 37304 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_BL

#define SEMC_SRAMCR0_BL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)

BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64

Definition at line 37302 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_BL_MASK

#define SEMC_SRAMCR0_BL_MASK (0x70U)

Definition at line 37290 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_BL_SHIFT

#define SEMC_SRAMCR0_BL_SHIFT (4U)

Definition at line 37291 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_COL

#define SEMC_SRAMCR0_COL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)

COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits

Definition at line 37346 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_COL_MASK

#define SEMC_SRAMCR0_COL_MASK (0xF000U)

Definition at line 37326 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_COL_SHIFT

#define SEMC_SRAMCR0_COL_SHIFT (12U)

Definition at line 37327 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_PS

#define SEMC_SRAMCR0_PS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)

PS - Port Size 0b0..8bit 0b1..16bit

Definition at line 37282 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_PS_MASK

#define SEMC_SRAMCR0_PS_MASK (0x1U)

Definition at line 37276 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_PS_SHIFT

#define SEMC_SRAMCR0_PS_SHIFT (0U)

Definition at line 37277 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_SYNCEN

#define SEMC_SRAMCR0_SYNCEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)

SYNCEN - Select SRAM controller mode. 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled.

Definition at line 37289 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_SYNCEN_MASK

#define SEMC_SRAMCR0_SYNCEN_MASK (0x2U)

Definition at line 37283 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR0_SYNCEN_SHIFT

#define SEMC_SRAMCR0_SYNCEN_SHIFT (1U)

Definition at line 37284 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_AH

#define SEMC_SRAMCR1_AH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)

AH - Address hold time

Definition at line 37370 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_AH_MASK

#define SEMC_SRAMCR1_AH_MASK (0xF000U)

Definition at line 37366 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_AH_SHIFT

#define SEMC_SRAMCR1_AH_SHIFT (12U)

Definition at line 37367 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_AS

#define SEMC_SRAMCR1_AS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)

AS - Address setup time

Definition at line 37365 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_AS_MASK

#define SEMC_SRAMCR1_AS_MASK (0xF00U)

Definition at line 37361 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_AS_SHIFT

#define SEMC_SRAMCR1_AS_SHIFT (8U)

Definition at line 37362 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_CEH

#define SEMC_SRAMCR1_CEH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)

CEH - CE hold min time

Definition at line 37360 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_CEH_MASK

#define SEMC_SRAMCR1_CEH_MASK (0xF0U)

Definition at line 37356 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_CEH_SHIFT

#define SEMC_SRAMCR1_CEH_SHIFT (4U)

Definition at line 37357 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_CES

#define SEMC_SRAMCR1_CES | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)

CES - CE setup time cycle

Definition at line 37355 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_CES_MASK

#define SEMC_SRAMCR1_CES_MASK (0xFU)

Definition at line 37351 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_CES_SHIFT

#define SEMC_SRAMCR1_CES_SHIFT (0U)

Definition at line 37352 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_REH

#define SEMC_SRAMCR1_REH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)

REH - RE HIGH time (REH+1) cycle

Definition at line 37390 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_REH_MASK

#define SEMC_SRAMCR1_REH_MASK (0xF0000000U)

Definition at line 37386 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_REH_SHIFT

#define SEMC_SRAMCR1_REH_SHIFT (28U)

Definition at line 37387 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_REL

#define SEMC_SRAMCR1_REL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)

REL - RE LOW time (REL+1) cycle

Definition at line 37385 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_REL_MASK

#define SEMC_SRAMCR1_REL_MASK (0xF000000U)

Definition at line 37381 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_REL_SHIFT

#define SEMC_SRAMCR1_REL_SHIFT (24U)

Definition at line 37382 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_WEH

#define SEMC_SRAMCR1_WEH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)

WEH - WE HIGH time (WEH+1) cycle

Definition at line 37380 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_WEH_MASK

#define SEMC_SRAMCR1_WEH_MASK (0xF00000U)

Definition at line 37376 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_WEH_SHIFT

#define SEMC_SRAMCR1_WEH_SHIFT (20U)

Definition at line 37377 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_WEL

#define SEMC_SRAMCR1_WEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)

WEL - WE LOW time (WEL+1) cycle

Definition at line 37375 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_WEL_MASK

#define SEMC_SRAMCR1_WEL_MASK (0xF0000U)

Definition at line 37371 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR1_WEL_SHIFT

#define SEMC_SRAMCR1_WEL_SHIFT (16U)

Definition at line 37372 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_AWDH

#define SEMC_SRAMCR2_AWDH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)

AWDH - Address to write data hold time cycle

Definition at line 37414 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_AWDH_MASK

#define SEMC_SRAMCR2_AWDH_MASK (0xF000U)

Definition at line 37410 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_AWDH_SHIFT

#define SEMC_SRAMCR2_AWDH_SHIFT (12U)

Definition at line 37411 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_CEITV

#define SEMC_SRAMCR2_CEITV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)

CEITV - CE# interval min time

Definition at line 37429 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_CEITV_MASK

#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)

Definition at line 37425 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_CEITV_SHIFT

#define SEMC_SRAMCR2_CEITV_SHIFT (24U)

Definition at line 37426 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_LC

#define SEMC_SRAMCR2_LC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)

LC - Latency count

Definition at line 37419 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_LC_MASK

#define SEMC_SRAMCR2_LC_MASK (0xF0000U)

Definition at line 37415 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_LC_SHIFT

#define SEMC_SRAMCR2_LC_SHIFT (16U)

Definition at line 37416 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_RD

#define SEMC_SRAMCR2_RD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)

RD - Read cycle time

Definition at line 37424 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_RD_MASK

#define SEMC_SRAMCR2_RD_MASK (0xF00000U)

Definition at line 37420 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_RD_SHIFT

#define SEMC_SRAMCR2_RD_SHIFT (20U)

Definition at line 37421 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_RDH

#define SEMC_SRAMCR2_RDH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)

RDH - Read cycle hold time

Definition at line 37434 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_RDH_MASK

#define SEMC_SRAMCR2_RDH_MASK (0xF0000000U)

Definition at line 37430 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_RDH_SHIFT

#define SEMC_SRAMCR2_RDH_SHIFT (28U)

Definition at line 37431 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_TA

#define SEMC_SRAMCR2_TA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)

TA - Turnaround time cycle

Definition at line 37409 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_TA_MASK

#define SEMC_SRAMCR2_TA_MASK (0xF00U)

Definition at line 37405 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_TA_SHIFT

#define SEMC_SRAMCR2_TA_SHIFT (8U)

Definition at line 37406 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_WDH

#define SEMC_SRAMCR2_WDH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)

WDH - Write Data hold time WDH cycle

Definition at line 37404 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_WDH_MASK

#define SEMC_SRAMCR2_WDH_MASK (0xF0U)

Definition at line 37400 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_WDH_SHIFT

#define SEMC_SRAMCR2_WDH_SHIFT (4U)

Definition at line 37401 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_WDS

#define SEMC_SRAMCR2_WDS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)

WDS - Write Data setup time (WDS+1) cycle

Definition at line 37399 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_WDS_MASK

#define SEMC_SRAMCR2_WDS_MASK (0xFU)

Definition at line 37395 of file MIMXRT1062.h.

## ◆ SEMC_SRAMCR2_WDS_SHIFT

#define SEMC_SRAMCR2_WDS_SHIFT (0U)

Definition at line 37396 of file MIMXRT1062.h.

## ◆ SEMC_STS0_IDLE

#define SEMC_STS0_IDLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)

IDLE - Indicating whether SEMC is in IDLE state.

Definition at line 37614 of file MIMXRT1062.h.

## ◆ SEMC_STS0_IDLE_MASK

#define SEMC_STS0_IDLE_MASK (0x1U)

Definition at line 37610 of file MIMXRT1062.h.

## ◆ SEMC_STS0_IDLE_SHIFT

#define SEMC_STS0_IDLE_SHIFT (0U)

Definition at line 37611 of file MIMXRT1062.h.

## ◆ SEMC_STS0_NARDY

#define SEMC_STS0_NARDY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)

NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready

Definition at line 37621 of file MIMXRT1062.h.

## ◆ SEMC_STS0_NARDY_MASK

#define SEMC_STS0_NARDY_MASK (0x2U)

Definition at line 37615 of file MIMXRT1062.h.

## ◆ SEMC_STS0_NARDY_SHIFT

#define SEMC_STS0_NARDY_SHIFT (1U)

Definition at line 37616 of file MIMXRT1062.h.

## ◆ SEMC_STS12_NDADDR

#define SEMC_STS12_NDADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)

NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).

Definition at line 37641 of file MIMXRT1062.h.

## ◆ SEMC_STS12_NDADDR_MASK

#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)

Definition at line 37637 of file MIMXRT1062.h.

## ◆ SEMC_STS12_NDADDR_SHIFT

#define SEMC_STS12_NDADDR_SHIFT (0U)

Definition at line 37638 of file MIMXRT1062.h.

## ◆ SEMC_STS13_REFLOCK

#define SEMC_STS13_REFLOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)

REFLOCK - Sample clock reference delay line locked.

Definition at line 37655 of file MIMXRT1062.h.

## ◆ SEMC_STS13_REFLOCK_MASK

#define SEMC_STS13_REFLOCK_MASK (0x2U)

Definition at line 37651 of file MIMXRT1062.h.

## ◆ SEMC_STS13_REFLOCK_SHIFT

#define SEMC_STS13_REFLOCK_SHIFT (1U)

Definition at line 37652 of file MIMXRT1062.h.

## ◆ SEMC_STS13_REFSEL

#define SEMC_STS13_REFSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)

REFSEL - Sample clock reference delay line delay cell number selection.

Definition at line 37665 of file MIMXRT1062.h.

## ◆ SEMC_STS13_REFSEL_MASK

#define SEMC_STS13_REFSEL_MASK (0x3F00U)

Definition at line 37661 of file MIMXRT1062.h.

## ◆ SEMC_STS13_REFSEL_SHIFT

#define SEMC_STS13_REFSEL_SHIFT (8U)

Definition at line 37662 of file MIMXRT1062.h.

## ◆ SEMC_STS13_SLVLOCK

#define SEMC_STS13_SLVLOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)

SLVLOCK - Sample clock slave delay line locked.

Definition at line 37650 of file MIMXRT1062.h.

## ◆ SEMC_STS13_SLVLOCK_MASK

#define SEMC_STS13_SLVLOCK_MASK (0x1U)

Definition at line 37646 of file MIMXRT1062.h.

## ◆ SEMC_STS13_SLVLOCK_SHIFT

#define SEMC_STS13_SLVLOCK_SHIFT (0U)

Definition at line 37647 of file MIMXRT1062.h.

## ◆ SEMC_STS13_SLVSEL

#define SEMC_STS13_SLVSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)

SLVSEL - Sample clock slave delay line delay cell number selection .

Definition at line 37660 of file MIMXRT1062.h.

## ◆ SEMC_STS13_SLVSEL_MASK

#define SEMC_STS13_SLVSEL_MASK (0xFCU)

Definition at line 37656 of file MIMXRT1062.h.

## ◆ SEMC_STS13_SLVSEL_SHIFT

#define SEMC_STS13_SLVSEL_SHIFT (2U)

Definition at line 37657 of file MIMXRT1062.h.

## ◆ SEMC_STS2_NDWRPEND

#define SEMC_STS2_NDWRPEND | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)

NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending

Definition at line 37632 of file MIMXRT1062.h.

## ◆ SEMC_STS2_NDWRPEND_MASK

#define SEMC_STS2_NDWRPEND_MASK (0x8U)

Definition at line 37626 of file MIMXRT1062.h.

## ◆ SEMC_STS2_NDWRPEND_SHIFT

#define SEMC_STS2_NDWRPEND_SHIFT (3U)

Definition at line 37627 of file MIMXRT1062.h.