Callisto4Bootloader: ENC Peripheral Access Layer

Callisto4Bootloader

Modules | Data Structures | Macros
ENC Peripheral Access Layer
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer

## Modules

| ENC Register Masks

## Data Structures

struct | ENC_Type

## Macros

#define | ENC1_BASE (0x403C8000u)
#define | ENC1 ((ENC_Type *)ENC1_BASE)
#define | ENC2_BASE (0x403CC000u)
#define | ENC2 ((ENC_Type *)ENC2_BASE)
#define | ENC3_BASE (0x403D0000u)
#define | ENC3 ((ENC_Type *)ENC3_BASE)
#define | ENC4_BASE (0x403D4000u)
#define | ENC4 ((ENC_Type *)ENC4_BASE)
#define | ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
#define | ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
#define | ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

## Detailed Description

## Macro Definition Documentation

## ◆ ENC1

#define ENC1 ((ENC_Type *)ENC1_BASE)

Peripheral ENC1 base pointer

Definition at line 16749 of file MIMXRT1062.h.

## ◆ ENC1_BASE

#define ENC1_BASE (0x403C8000u)

Peripheral ENC1 base address

Definition at line 16747 of file MIMXRT1062.h.

## ◆ ENC2

#define ENC2 ((ENC_Type *)ENC2_BASE)

Peripheral ENC2 base pointer

Definition at line 16753 of file MIMXRT1062.h.

## ◆ ENC2_BASE

#define ENC2_BASE (0x403CC000u)

Peripheral ENC2 base address

Definition at line 16751 of file MIMXRT1062.h.

## ◆ ENC3

#define ENC3 ((ENC_Type *)ENC3_BASE)

Peripheral ENC3 base pointer

Definition at line 16757 of file MIMXRT1062.h.

## ◆ ENC3_BASE

#define ENC3_BASE (0x403D0000u)

Peripheral ENC3 base address

Definition at line 16755 of file MIMXRT1062.h.

## ◆ ENC4

#define ENC4 ((ENC_Type *)ENC4_BASE)

Peripheral ENC4 base pointer

Definition at line 16761 of file MIMXRT1062.h.

## ◆ ENC4_BASE

#define ENC4_BASE (0x403D4000u)

Peripheral ENC4 base address

Definition at line 16759 of file MIMXRT1062.h.

## ◆ ENC_BASE_ADDRS

#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }

Array initializer of ENC peripheral base addresses

Definition at line 16763 of file MIMXRT1062.h.

## ◆ ENC_BASE_PTRS

#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }

Array initializer of ENC peripheral base pointers

Definition at line 16765 of file MIMXRT1062.h.

## ◆ ENC_COMPARE_IRQS

#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Interrupt vectors for the ENC peripheral type

Definition at line 16767 of file MIMXRT1062.h.

## ◆ ENC_HOME_IRQS

#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Definition at line 16768 of file MIMXRT1062.h.

## ◆ ENC_INDEX_IRQS

#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Definition at line 16770 of file MIMXRT1062.h.

## ◆ ENC_INPUT_SWITCH_IRQS

#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Definition at line 16771 of file MIMXRT1062.h.

## ◆ ENC_WDOG_IRQS

#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Definition at line 16769 of file MIMXRT1062.h.