Callisto4Bootloader: CMSIS/cmsis_iccarm.h Source File

Callisto4Bootloader

cmsis_iccarm.h
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1 /**************************************************************************/
8 //------------------------------------------------------------------------------
9 //
10 // Copyright (c) 2017-2018 IAR Systems
11 //
12 // Licensed under the Apache License, Version 2.0 (the "License")
13 // you may not use this file except in compliance with the License.
14 // You may obtain a copy of the License at
15 // http://www.apache.org/licenses/LICENSE-2.0
16 //
17 // Unless required by applicable law or agreed to in writing, software
18 // distributed under the License is distributed on an "AS IS" BASIS,
19 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 // See the License for the specific language governing permissions and
21 // limitations under the License.
22 //
23 //------------------------------------------------------------------------------
24
25
26 #ifndef __CMSIS_ICCARM_H__
27 #define __CMSIS_ICCARM_H__
28
29 #ifndef __ICCARM__
30 #error This file should only be compiled by ICCARM
31 #endif
32
33 #pragma system_include
34
35 #define __IAR_FT _Pragma("inline=forced") __intrinsic
36
37 #if (__VER__ >= 8000000)
38 #define __ICCARM_V8 1
39 #else
40 #define __ICCARM_V8 0
41 #endif
42
43 #ifndef __ALIGNED
44 #if __ICCARM_V8
45 #define __ALIGNED(x) __attribute__((aligned(x)))
46 #elif (__VER__ >= 7080000)
47 /* Needs IAR language extensions */
48 #define __ALIGNED(x) __attribute__((aligned(x)))
49 #else
50 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
51 #define __ALIGNED(x)
52 #endif
53 #endif
54
55
56 /* Define compiler macros for CPU architecture, used in CMSIS 5.
57 */
58 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
59 /* Macros already defined */
60 #else
61 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
62 #define __ARM_ARCH_8M_MAIN__ 1
63 #elif defined(__ARM8M_BASELINE__)
64 #define __ARM_ARCH_8M_BASE__ 1
65 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
66 #if __ARM_ARCH == 6
67 #define __ARM_ARCH_6M__ 1
68 #elif __ARM_ARCH == 7
69 #if __ARM_FEATURE_DSP
70 #define __ARM_ARCH_7EM__ 1
71 #else
72 #define __ARM_ARCH_7M__ 1
73 #endif
74 #endif /* __ARM_ARCH */
75 #endif /* __ARM_ARCH_PROFILE == 'M' */
76 #endif
77
78 /* Alternativ core deduction for older ICCARM's */
79 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
80 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
81 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
82 #define __ARM_ARCH_6M__ 1
83 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
84 #define __ARM_ARCH_7M__ 1
85 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
86 #define __ARM_ARCH_7EM__ 1
87 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
88 #define __ARM_ARCH_8M_BASE__ 1
89 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
90 #define __ARM_ARCH_8M_MAIN__ 1
91 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
92 #define __ARM_ARCH_8M_MAIN__ 1
93 #else
94 #error "Unknown target."
95 #endif
96 #endif
97
98
99
100 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
101 #define __IAR_M0_FAMILY 1
102 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
103 #define __IAR_M0_FAMILY 1
104 #else
105 #define __IAR_M0_FAMILY 0
106 #endif
107
108
109 #ifndef __ASM
110 #define __ASM __asm
111 #endif
112
113 #ifndef __INLINE
114 #define __INLINE inline
115 #endif
116
117 #ifndef __NO_RETURN
118 #if __ICCARM_V8
119 #define __NO_RETURN __attribute__((__noreturn__))
120 #else
121 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
122 #endif
123 #endif
124
125 #ifndef __PACKED
126 #if __ICCARM_V8
127 #define __PACKED __attribute__((packed, aligned(1)))
128 #else
129 /* Needs IAR language extensions */
130 #define __PACKED __packed
131 #endif
132 #endif
133
134 #ifndef __PACKED_STRUCT
135 #if __ICCARM_V8
136 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
137 #else
138 /* Needs IAR language extensions */
139 #define __PACKED_STRUCT __packed struct
140 #endif
141 #endif
142
143 #ifndef __PACKED_UNION
144 #if __ICCARM_V8
145 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
146 #else
147 /* Needs IAR language extensions */
148 #define __PACKED_UNION __packed union
149 #endif
150 #endif
151
152 #ifndef __RESTRICT
153 #if __ICCARM_V8
154 #define __RESTRICT __restrict
155 #else
156 /* Needs IAR language extensions */
157 #define __RESTRICT restrict
158 #endif
159 #endif
160
161 #ifndef __STATIC_INLINE
162 #define __STATIC_INLINE static inline
163 #endif
164
165 #ifndef __FORCEINLINE
166 #define __FORCEINLINE _Pragma("inline=forced")
167 #endif
168
169 #ifndef __STATIC_FORCEINLINE
170 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
171 #endif
172
173 #ifndef __UNALIGNED_UINT16_READ
174 #pragma language=save
175 #pragma language=extended
176 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
177 {
178 return *(__packed uint16_t*)(ptr);
179 }
180 #pragma language=restore
181 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
182 #endif
183
184
185 #ifndef __UNALIGNED_UINT16_WRITE
186 #pragma language=save
187 #pragma language=extended
188 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
189 {
190 *(__packed uint16_t*)(ptr) = val;;
191 }
192 #pragma language=restore
193 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
194 #endif
195
196 #ifndef __UNALIGNED_UINT32_READ
197 #pragma language=save
198 #pragma language=extended
199 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
200 {
201 return *(__packed uint32_t*)(ptr);
202 }
203 #pragma language=restore
204 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
205 #endif
206
207 #ifndef __UNALIGNED_UINT32_WRITE
208 #pragma language=save
209 #pragma language=extended
210 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
211 {
212 *(__packed uint32_t*)(ptr) = val;;
213 }
214 #pragma language=restore
215 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
216 #endif
217
218 #ifndef __UNALIGNED_UINT32 /* deprecated */
219 #pragma language=save
220 #pragma language=extended
221 __packed struct __iar_u32 { uint32_t v; };
222 #pragma language=restore
223 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
224 #endif
225
226 #ifndef __USED
227 #if __ICCARM_V8
228 #define __USED __attribute__((used))
229 #else
230 #define __USED _Pragma("__root")
231 #endif
232 #endif
233
234 #ifndef __WEAK
235 #if __ICCARM_V8
236 #define __WEAK __attribute__((weak))
237 #else
238 #define __WEAK _Pragma("__weak")
239 #endif
240 #endif
241
242
243 #ifndef __ICCARM_INTRINSICS_VERSION__
244 #define __ICCARM_INTRINSICS_VERSION__ 0
245 #endif
246
247 #if __ICCARM_INTRINSICS_VERSION__ == 2
248
249 #if defined(__CLZ)
250 #undef __CLZ
251 #endif
252 #if defined(__REVSH)
253 #undef __REVSH
254 #endif
255 #if defined(__RBIT)
256 #undef __RBIT
257 #endif
258 #if defined(__SSAT)
259 #undef __SSAT
260 #endif
261 #if defined(__USAT)
262 #undef __USAT
263 #endif
264
265 #include "iccarm_builtin.h"
266
267 #define __disable_fault_irq __iar_builtin_disable_fiq
268 #define __disable_irq __iar_builtin_disable_interrupt
269 #define __enable_fault_irq __iar_builtin_enable_fiq
270 #define __enable_irq __iar_builtin_enable_interrupt
271 #define __arm_rsr __iar_builtin_rsr
272 #define __arm_wsr __iar_builtin_wsr
273
274
275 #define __get_APSR() (__arm_rsr("APSR"))
276 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
277 #define __get_CONTROL() (__arm_rsr("CONTROL"))
278 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
279
280 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
281 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
282 #define __get_FPSCR() (__arm_rsr("FPSCR"))
283 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
284 #else
285 #define __get_FPSCR() ( 0 )
286 #define __set_FPSCR(VALUE) ((void)VALUE)
287 #endif
288
289 #define __get_IPSR() (__arm_rsr("IPSR"))
290 #define __get_MSP() (__arm_rsr("MSP"))
291 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
292 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
293 // without main extensions, the non-secure MSPLIM is RAZ/WI
294 #define __get_MSPLIM() (0U)
295 #else
296 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
297 #endif
298 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
299 #define __get_PSP() (__arm_rsr("PSP"))
300
301 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
302 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
303 // without main extensions, the non-secure PSPLIM is RAZ/WI
304 #define __get_PSPLIM() (0U)
305 #else
306 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
307 #endif
308
309 #define __get_xPSR() (__arm_rsr("xPSR"))
310
311 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
312 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
313 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
314 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
315 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
316
317 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
318 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
319 // without main extensions, the non-secure MSPLIM is RAZ/WI
320 #define __set_MSPLIM(VALUE) ((void)(VALUE))
321 #else
322 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
323 #endif
324 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
325 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
326 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
327 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
328 // without main extensions, the non-secure PSPLIM is RAZ/WI
329 #define __set_PSPLIM(VALUE) ((void)(VALUE))
330 #else
331 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
332 #endif
333
334 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
335 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
336 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
337 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
338 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
339 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
340 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
341 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
342 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
343 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
344 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
345 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
346 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
347 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
348
349 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
350 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
351 // without main extensions, the non-secure PSPLIM is RAZ/WI
352 #define __TZ_get_PSPLIM_NS() (0U)
353 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
354 #else
355 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
356 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
357 #endif
358
359 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
360 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
361
362 #define __NOP __iar_builtin_no_operation
363
364 #define __CLZ __iar_builtin_CLZ
365 #define __CLREX __iar_builtin_CLREX
366
367 #define __DMB __iar_builtin_DMB
368 #define __DSB __iar_builtin_DSB
369 #define __ISB __iar_builtin_ISB
370
371 #define __LDREXB __iar_builtin_LDREXB
372 #define __LDREXH __iar_builtin_LDREXH
373 #define __LDREXW __iar_builtin_LDREX
374
375 #define __RBIT __iar_builtin_RBIT
376 #define __REV __iar_builtin_REV
377 #define __REV16 __iar_builtin_REV16
378
379 __IAR_FT int16_t __REVSH(int16_t val)
380 {
381 return (int16_t) __iar_builtin_REVSH(val);
382 }
383
384 #define __ROR __iar_builtin_ROR
385 #define __RRX __iar_builtin_RRX
386
387 #define __SEV __iar_builtin_SEV
388
389 #if !__IAR_M0_FAMILY
390 #define __SSAT __iar_builtin_SSAT
391 #endif
392
393 #define __STREXB __iar_builtin_STREXB
394 #define __STREXH __iar_builtin_STREXH
395 #define __STREXW __iar_builtin_STREX
396
397 #if !__IAR_M0_FAMILY
398 #define __USAT __iar_builtin_USAT
399 #endif
400
401 #define __WFE __iar_builtin_WFE
402 #define __WFI __iar_builtin_WFI
403
404 #if __ARM_MEDIA__
405 #define __SADD8 __iar_builtin_SADD8
406 #define __QADD8 __iar_builtin_QADD8
407 #define __SHADD8 __iar_builtin_SHADD8
408 #define __UADD8 __iar_builtin_UADD8
409 #define __UQADD8 __iar_builtin_UQADD8
410 #define __UHADD8 __iar_builtin_UHADD8
411 #define __SSUB8 __iar_builtin_SSUB8
412 #define __QSUB8 __iar_builtin_QSUB8
413 #define __SHSUB8 __iar_builtin_SHSUB8
414 #define __USUB8 __iar_builtin_USUB8
415 #define __UQSUB8 __iar_builtin_UQSUB8
416 #define __UHSUB8 __iar_builtin_UHSUB8
417 #define __SADD16 __iar_builtin_SADD16
418 #define __QADD16 __iar_builtin_QADD16
419 #define __SHADD16 __iar_builtin_SHADD16
420 #define __UADD16 __iar_builtin_UADD16
421 #define __UQADD16 __iar_builtin_UQADD16
422 #define __UHADD16 __iar_builtin_UHADD16
423 #define __SSUB16 __iar_builtin_SSUB16
424 #define __QSUB16 __iar_builtin_QSUB16
425 #define __SHSUB16 __iar_builtin_SHSUB16
426 #define __USUB16 __iar_builtin_USUB16
427 #define __UQSUB16 __iar_builtin_UQSUB16
428 #define __UHSUB16 __iar_builtin_UHSUB16
429 #define __SASX __iar_builtin_SASX
430 #define __QASX __iar_builtin_QASX
431 #define __SHASX __iar_builtin_SHASX
432 #define __UASX __iar_builtin_UASX
433 #define __UQASX __iar_builtin_UQASX
434 #define __UHASX __iar_builtin_UHASX
435 #define __SSAX __iar_builtin_SSAX
436 #define __QSAX __iar_builtin_QSAX
437 #define __SHSAX __iar_builtin_SHSAX
438 #define __USAX __iar_builtin_USAX
439 #define __UQSAX __iar_builtin_UQSAX
440 #define __UHSAX __iar_builtin_UHSAX
441 #define __USAD8 __iar_builtin_USAD8
442 #define __USADA8 __iar_builtin_USADA8
443 #define __SSAT16 __iar_builtin_SSAT16
444 #define __USAT16 __iar_builtin_USAT16
445 #define __UXTB16 __iar_builtin_UXTB16
446 #define __UXTAB16 __iar_builtin_UXTAB16
447 #define __SXTB16 __iar_builtin_SXTB16
448 #define __SXTAB16 __iar_builtin_SXTAB16
449 #define __SMUAD __iar_builtin_SMUAD
450 #define __SMUADX __iar_builtin_SMUADX
451 #define __SMMLA __iar_builtin_SMMLA
452 #define __SMLAD __iar_builtin_SMLAD
453 #define __SMLADX __iar_builtin_SMLADX
454 #define __SMLALD __iar_builtin_SMLALD
455 #define __SMLALDX __iar_builtin_SMLALDX
456 #define __SMUSD __iar_builtin_SMUSD
457 #define __SMUSDX __iar_builtin_SMUSDX
458 #define __SMLSD __iar_builtin_SMLSD
459 #define __SMLSDX __iar_builtin_SMLSDX
460 #define __SMLSLD __iar_builtin_SMLSLD
461 #define __SMLSLDX __iar_builtin_SMLSLDX
462 #define __SEL __iar_builtin_SEL
463 #define __QADD __iar_builtin_QADD
464 #define __QSUB __iar_builtin_QSUB
465 #define __PKHBT __iar_builtin_PKHBT
466 #define __PKHTB __iar_builtin_PKHTB
467 #endif
468
469 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
470
471 #if __IAR_M0_FAMILY
472 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
473 #define __CLZ __cmsis_iar_clz_not_active
474 #define __SSAT __cmsis_iar_ssat_not_active
475 #define __USAT __cmsis_iar_usat_not_active
476 #define __RBIT __cmsis_iar_rbit_not_active
477 #define __get_APSR __cmsis_iar_get_APSR_not_active
478 #endif
479
480
481 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
482 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
483 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
484 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
485 #endif
486
487 #ifdef __INTRINSICS_INCLUDED
488 #error intrinsics.h is already included previously!
489 #endif
490
491 #include <intrinsics.h>
492
493 #if __IAR_M0_FAMILY
494 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
495 #undef __CLZ
496 #undef __SSAT
497 #undef __USAT
498 #undef __RBIT
499 #undef __get_APSR
500
501 __STATIC_INLINE uint8_t __CLZ(uint32_t data)
502 {
503 if (data == 0U) { return 32U; }
504
505 uint32_t count = 0U;
506 uint32_t mask = 0x80000000U;
507
508 while ((data & mask) == 0U)
509 {
510 count += 1U;
511 mask = mask >> 1U;
512 }
513 return count;
514 }
515
516 __STATIC_INLINE uint32_t __RBIT(uint32_t v)
517 {
518 uint8_t sc = 31U;
519 uint32_t r = v;
520 for (v >>= 1U; v; v >>= 1U)
521 {
522 r <<= 1U;
523 r |= v & 1U;
524 sc--;
525 }
526 return (r << sc);
527 }
528
529 __STATIC_INLINE uint32_t __get_APSR(void)
530 {
531 uint32_t res;
532 __asm("MRS %0,APSR" : "=r" (res));
533 return res;
534 }
535
536 #endif
537
538 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
539 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
540 #undef __get_FPSCR
541 #undef __set_FPSCR
542 #define __get_FPSCR() (0)
543 #define __set_FPSCR(VALUE) ((void)VALUE)
544 #endif
545
546 #pragma diag_suppress=Pe940
547 #pragma diag_suppress=Pe177
548
549 #define __enable_irq __enable_interrupt
550 #define __disable_irq __disable_interrupt
551 #define __NOP __no_operation
552
553 #define __get_xPSR __get_PSR
554
555 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
556
557 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
558 {
559 return __LDREX((unsigned long *)ptr);
560 }
561
562 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
563 {
564 return __STREX(value, (unsigned long *)ptr);
565 }
566 #endif
567
568
569 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
570 #if (__CORTEX_M >= 0x03)
571
572 __IAR_FT uint32_t __RRX(uint32_t value)
573 {
574 uint32_t result;
575 __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
576 return(result);
577 }
578
579 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
580 {
581 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
582 }
583
584
585 #define __enable_fault_irq __enable_fiq
586 #define __disable_fault_irq __disable_fiq
587
588
589 #endif /* (__CORTEX_M >= 0x03) */
590
591 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
592 {
593 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
594 }
595
596 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
597 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
598
599 __IAR_FT uint32_t __get_MSPLIM(void)
600 {
601 uint32_t res;
602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
603 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
604 // without main extensions, the non-secure MSPLIM is RAZ/WI
605 res = 0U;
606 #else
607 __asm volatile("MRS %0,MSPLIM" : "=r" (res));
608 #endif
609 return res;
610 }
611
612 __IAR_FT void __set_MSPLIM(uint32_t value)
613 {
614 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
615 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
616 // without main extensions, the non-secure MSPLIM is RAZ/WI
617 (void)value;
618 #else
619 __asm volatile("MSR MSPLIM,%0" :: "r" (value));
620 #endif
621 }
622
623 __IAR_FT uint32_t __get_PSPLIM(void)
624 {
625 uint32_t res;
626 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
627 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
628 // without main extensions, the non-secure PSPLIM is RAZ/WI
629 res = 0U;
630 #else
631 __asm volatile("MRS %0,PSPLIM" : "=r" (res));
632 #endif
633 return res;
634 }
635
636 __IAR_FT void __set_PSPLIM(uint32_t value)
637 {
638 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
639 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
640 // without main extensions, the non-secure PSPLIM is RAZ/WI
641 (void)value;
642 #else
643 __asm volatile("MSR PSPLIM,%0" :: "r" (value));
644 #endif
645 }
646
647 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
648 {
649 uint32_t res;
650 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
651 return res;
652 }
653
654 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
655 {
656 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
657 }
658
659 __IAR_FT uint32_t __TZ_get_PSP_NS(void)
660 {
661 uint32_t res;
662 __asm volatile("MRS %0,PSP_NS" : "=r" (res));
663 return res;
664 }
665
666 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
667 {
668 __asm volatile("MSR PSP_NS,%0" :: "r" (value));
669 }
670
671 __IAR_FT uint32_t __TZ_get_MSP_NS(void)
672 {
673 uint32_t res;
674 __asm volatile("MRS %0,MSP_NS" : "=r" (res));
675 return res;
676 }
677
678 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
679 {
680 __asm volatile("MSR MSP_NS,%0" :: "r" (value));
681 }
682
683 __IAR_FT uint32_t __TZ_get_SP_NS(void)
684 {
685 uint32_t res;
686 __asm volatile("MRS %0,SP_NS" : "=r" (res));
687 return res;
688 }
689 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
690 {
691 __asm volatile("MSR SP_NS,%0" :: "r" (value));
692 }
693
694 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
695 {
696 uint32_t res;
697 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
698 return res;
699 }
700
701 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
702 {
703 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
704 }
705
706 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
707 {
708 uint32_t res;
709 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
710 return res;
711 }
712
713 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
714 {
715 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
716 }
717
718 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
719 {
720 uint32_t res;
721 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
722 return res;
723 }
724
725 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
726 {
727 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
728 }
729
730 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
731 {
732 uint32_t res;
733 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
734 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
735 // without main extensions, the non-secure PSPLIM is RAZ/WI
736 res = 0U;
737 #else
738 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
739 #endif
740 return res;
741 }
742
743 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
744 {
745 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
746 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
747 // without main extensions, the non-secure PSPLIM is RAZ/WI
748 (void)value;
749 #else
750 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
751 #endif
752 }
753
754 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
755 {
756 uint32_t res;
757 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
758 return res;
759 }
760
761 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
762 {
763 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
764 }
765
766 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
767
768 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
769
770 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
771
772 #if __IAR_M0_FAMILY
773 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
774 {
775 if ((sat >= 1U) && (sat <= 32U))
776 {
777 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
778 const int32_t min = -1 - max ;
779 if (val > max)
780 {
781 return max;
782 }
783 else if (val < min)
784 {
785 return min;
786 }
787 }
788 return val;
789 }
790
791 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
792 {
793 if (sat <= 31U)
794 {
795 const uint32_t max = ((1U << sat) - 1U);
796 if (val > (int32_t)max)
797 {
798 return max;
799 }
800 else if (val < 0)
801 {
802 return 0U;
803 }
804 }
805 return (uint32_t)val;
806 }
807 #endif
808
809 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
810
811 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
812 {
813 uint32_t res;
814 __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
815 return ((uint8_t)res);
816 }
817
818 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
819 {
820 uint32_t res;
821 __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
822 return ((uint16_t)res);
823 }
824
825 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
826 {
827 uint32_t res;
828 __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
829 return res;
830 }
831
832 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
833 {
834 __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
835 }
836
837 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
838 {
839 __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
840 }
841
842 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
843 {
844 __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
845 }
846
847 #endif /* (__CORTEX_M >= 0x03) */
848
849 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
850 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
851
852
853 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
854 {
855 uint32_t res;
856 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
857 return ((uint8_t)res);
858 }
859
860 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
861 {
862 uint32_t res;
863 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
864 return ((uint16_t)res);
865 }
866
867 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
868 {
869 uint32_t res;
870 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
871 return res;
872 }
873
874 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
875 {
876 __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
877 }
878
879 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
880 {
881 __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
882 }
883
884 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
885 {
886 __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
887 }
888
889 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
890 {
891 uint32_t res;
892 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
893 return ((uint8_t)res);
894 }
895
896 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
897 {
898 uint32_t res;
899 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
900 return ((uint16_t)res);
901 }
902
903 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
904 {
905 uint32_t res;
906 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
907 return res;
908 }
909
910 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
911 {
912 uint32_t res;
913 __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
914 return res;
915 }
916
917 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
918 {
919 uint32_t res;
920 __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
921 return res;
922 }
923
924 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
925 {
926 uint32_t res;
927 __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
928 return res;
929 }
930
931 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
932
933 #undef __IAR_FT
934 #undef __IAR_M0_FAMILY
935 #undef __ICCARM_V8
936
937 #pragma diag_default=Pe940
938 #pragma diag_default=Pe177
939
940 #endif /* __CMSIS_ICCARM_H__ */
__iar_uint16_read
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
Definition: cmsis_iccarm.h:176
__CLZ
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
Count leading zeros.
Definition: cmsis_armclang.h:913
__IAR_FT
#define __IAR_FT
Definition: cmsis_iccarm.h:35
__REVSH
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
Reverse byte order (16 bit)
Definition: cmsis_gcc.h:934
__get_APSR
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition: cmsis_armcc.h:170
__iar_u32
Definition: cmsis_iccarm.h:221
__ROR
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
Definition: cmsis_iccarm.h:591
__iar_u32::v
uint32_t v
Definition: cmsis_iccarm.h:221
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_iccarm.h:162
__USAT
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition: cmsis_armclang.h:1164
__ASM
#define __ASM
Definition: cmsis_iccarm.h:110
sat
uint32_t sat
Definition: cmsis_armcc.h:741
__SSAT
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition: cmsis_armclang.h:1139
__LDREXW
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
Definition: cmsis_iccarm.h:557
__iar_uint32_write
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
Definition: cmsis_iccarm.h:210
__RBIT
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
Reverse bit order of value.
Definition: cmsis_gcc.h:981
__iar_uint32_read
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
Definition: cmsis_iccarm.h:199
min
#define min(a, b)
Minimum.
Definition: c4_qspi.h:41
__iar_uint16_write
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
Definition: cmsis_iccarm.h:188
__STREXW
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
Definition: cmsis_iccarm.h:562
max
#define max(a, b)
Maximum.
Definition: c4_qspi.h:26