Callisto4Bootloader: DCP_Type Struct Reference

Callisto4Bootloader

Data Fields
DCP_Type Struct Reference
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » DCP Peripheral Access Layer

`#include <MIMXRT1062.h>`

## Data Fields

__IO uint32_t | CTRL
__IO uint32_t | CTRL_SET
__IO uint32_t | CTRL_CLR
__IO uint32_t | CTRL_TOG
__IO uint32_t | STAT
__IO uint32_t | STAT_SET
__IO uint32_t | STAT_CLR
__IO uint32_t | STAT_TOG
__IO uint32_t | CHANNELCTRL
__IO uint32_t | CHANNELCTRL_SET
__IO uint32_t | CHANNELCTRL_CLR
__IO uint32_t | CHANNELCTRL_TOG
__IO uint32_t | CAPABILITY0
uint8_t | RESERVED_0 [12]
__I uint32_t | CAPABILITY1
uint8_t | RESERVED_1 [12]
__IO uint32_t | CONTEXT
uint8_t | RESERVED_2 [12]
__IO uint32_t | KEY
uint8_t | RESERVED_3 [12]
__IO uint32_t | KEYDATA
uint8_t | RESERVED_4 [12]
__I uint32_t | PACKET0
uint8_t | RESERVED_5 [12]
__I uint32_t | PACKET1
uint8_t | RESERVED_6 [12]
__I uint32_t | PACKET2
uint8_t | RESERVED_7 [12]
__I uint32_t | PACKET3
uint8_t | RESERVED_8 [12]
__I uint32_t | PACKET4
uint8_t | RESERVED_9 [12]
__I uint32_t | PACKET5
uint8_t | RESERVED_10 [12]
__I uint32_t | PACKET6
uint8_t | RESERVED_11 [28]
__IO uint32_t | CH0CMDPTR
uint8_t | RESERVED_12 [12]
__IO uint32_t | CH0SEMA
uint8_t | RESERVED_13 [12]
__IO uint32_t | CH0STAT
__IO uint32_t | CH0STAT_SET
__IO uint32_t | CH0STAT_CLR
__IO uint32_t | CH0STAT_TOG
__IO uint32_t | CH0OPTS
__IO uint32_t | CH0OPTS_SET
__IO uint32_t | CH0OPTS_CLR
__IO uint32_t | CH0OPTS_TOG
__IO uint32_t | CH1CMDPTR
uint8_t | RESERVED_14 [12]
__IO uint32_t | CH1SEMA
uint8_t | RESERVED_15 [12]
__IO uint32_t | CH1STAT
__IO uint32_t | CH1STAT_SET
__IO uint32_t | CH1STAT_CLR
__IO uint32_t | CH1STAT_TOG
__IO uint32_t | CH1OPTS
__IO uint32_t | CH1OPTS_SET
__IO uint32_t | CH1OPTS_CLR
__IO uint32_t | CH1OPTS_TOG
__IO uint32_t | CH2CMDPTR
uint8_t | RESERVED_16 [12]
__IO uint32_t | CH2SEMA
uint8_t | RESERVED_17 [12]
__IO uint32_t | CH2STAT
__IO uint32_t | CH2STAT_SET
__IO uint32_t | CH2STAT_CLR
__IO uint32_t | CH2STAT_TOG
__IO uint32_t | CH2OPTS
__IO uint32_t | CH2OPTS_SET
__IO uint32_t | CH2OPTS_CLR
__IO uint32_t | CH2OPTS_TOG
__IO uint32_t | CH3CMDPTR
uint8_t | RESERVED_18 [12]
__IO uint32_t | CH3SEMA
uint8_t | RESERVED_19 [12]
__IO uint32_t | CH3STAT
__IO uint32_t | CH3STAT_SET
__IO uint32_t | CH3STAT_CLR
__IO uint32_t | CH3STAT_TOG
__IO uint32_t | CH3OPTS
__IO uint32_t | CH3OPTS_SET
__IO uint32_t | CH3OPTS_CLR
__IO uint32_t | CH3OPTS_TOG
uint8_t | RESERVED_20 [512]
__IO uint32_t | DBGSELECT
uint8_t | RESERVED_21 [12]
__I uint32_t | DBGDATA
uint8_t | RESERVED_22 [12]
__IO uint32_t | PAGETABLE
uint8_t | RESERVED_23 [12]
__I uint32_t | VERSION

## Detailed Description

DCP - Register Layout Typedef

Definition at line 11453 of file MIMXRT1062.h.

The documentation for this struct was generated from the following file:

- device/MIMXRT1062.h