Callisto4Bootloader: GPC Register Masks

Callisto4Bootloader

Macros
GPC Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » GPC Peripheral Access Layer

## Macros

#define | GPC_IMR_COUNT (4U)
#define | GPC_ISR_COUNT (4U)

## CNTR - GPC Interface control register

#define | GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
#define | GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
#define | GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
#define | GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
#define | GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
#define | GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
#define | GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
#define | GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
#define | GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)

## IMR - IRQ masking register 1..IRQ masking register 4

#define | GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
#define | GPC_IMR_IMR1_SHIFT (0U)
#define | GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
#define | GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
#define | GPC_IMR_IMR2_SHIFT (0U)
#define | GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
#define | GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
#define | GPC_IMR_IMR3_SHIFT (0U)
#define | GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
#define | GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
#define | GPC_IMR_IMR4_SHIFT (0U)
#define | GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)

## ISR - IRQ status resister 1..IRQ status resister 4

#define | GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
#define | GPC_ISR_ISR1_SHIFT (0U)
#define | GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
#define | GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
#define | GPC_ISR_ISR2_SHIFT (0U)
#define | GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
#define | GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
#define | GPC_ISR_ISR3_SHIFT (0U)
#define | GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
#define | GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
#define | GPC_ISR_ISR4_SHIFT (0U)
#define | GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)

## IMR5 - IRQ masking register 5

#define | GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
#define | GPC_IMR5_IMR5_SHIFT (0U)
#define | GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)

## ISR5 - IRQ status resister 5

#define | GPC_ISR5_ISR4_MASK (0xFFFFFFFFU)
#define | GPC_ISR5_ISR4_SHIFT (0U)
#define | GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ GPC_CNTR_MEGA_PDN_REQ

#define GPC_CNTR_MEGA_PDN_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)

MEGA_PDN_REQ 0b0..No Request 0b1..Request power down sequence

Definition at line 20227 of file MIMXRT1062.h.

## ◆ GPC_CNTR_MEGA_PDN_REQ_MASK

#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)

Definition at line 20221 of file MIMXRT1062.h.

## ◆ GPC_CNTR_MEGA_PDN_REQ_SHIFT

#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)

Definition at line 20222 of file MIMXRT1062.h.

## ◆ GPC_CNTR_MEGA_PUP_REQ

#define GPC_CNTR_MEGA_PUP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)

MEGA_PUP_REQ 0b0..No Request 0b1..Request power up sequence

Definition at line 20234 of file MIMXRT1062.h.

## ◆ GPC_CNTR_MEGA_PUP_REQ_MASK

#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)

Definition at line 20228 of file MIMXRT1062.h.

## ◆ GPC_CNTR_MEGA_PUP_REQ_SHIFT

#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)

Definition at line 20229 of file MIMXRT1062.h.

## ◆ GPC_CNTR_PDRAM0_PGE

#define GPC_CNTR_PDRAM0_PGE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)

PDRAM0_PGE 0b1..FlexRAM PDRAM0 domain will be power down once when CPU core is power down. 0b0..FlexRAM PDRAM0 domain will keep power on even if CPU core is power down.

Definition at line 20241 of file MIMXRT1062.h.

## ◆ GPC_CNTR_PDRAM0_PGE_MASK

#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)

Definition at line 20235 of file MIMXRT1062.h.

## ◆ GPC_CNTR_PDRAM0_PGE_SHIFT

#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U)

Definition at line 20236 of file MIMXRT1062.h.

## ◆ GPC_IMR5_IMR5

#define GPC_IMR5_IMR5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)

Definition at line 20286 of file MIMXRT1062.h.

## ◆ GPC_IMR5_IMR5_MASK

#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)

Definition at line 20284 of file MIMXRT1062.h.

## ◆ GPC_IMR5_IMR5_SHIFT

#define GPC_IMR5_IMR5_SHIFT (0U)

Definition at line 20285 of file MIMXRT1062.h.

## ◆ GPC_IMR_COUNT

#define GPC_IMR_COUNT (4U)

Definition at line 20261 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR1

#define GPC_IMR_IMR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)

Definition at line 20248 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR1_MASK

#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU)

Definition at line 20246 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR1_SHIFT

#define GPC_IMR_IMR1_SHIFT (0U)

Definition at line 20247 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR2

#define GPC_IMR_IMR2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)

Definition at line 20251 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR2_MASK

#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU)

Definition at line 20249 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR2_SHIFT

#define GPC_IMR_IMR2_SHIFT (0U)

Definition at line 20250 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR3

#define GPC_IMR_IMR3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)

Definition at line 20254 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR3_MASK

#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU)

Definition at line 20252 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR3_SHIFT

#define GPC_IMR_IMR3_SHIFT (0U)

Definition at line 20253 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR4

#define GPC_IMR_IMR4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)

Definition at line 20257 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR4_MASK

#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU)

Definition at line 20255 of file MIMXRT1062.h.

## ◆ GPC_IMR_IMR4_SHIFT

#define GPC_IMR_IMR4_SHIFT (0U)

Definition at line 20256 of file MIMXRT1062.h.

## ◆ GPC_ISR5_ISR4

#define GPC_ISR5_ISR4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)

Definition at line 20293 of file MIMXRT1062.h.

## ◆ GPC_ISR5_ISR4_MASK

#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU)

Definition at line 20291 of file MIMXRT1062.h.

## ◆ GPC_ISR5_ISR4_SHIFT

#define GPC_ISR5_ISR4_SHIFT (0U)

Definition at line 20292 of file MIMXRT1062.h.

## ◆ GPC_ISR_COUNT

#define GPC_ISR_COUNT (4U)

Definition at line 20280 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR1

#define GPC_ISR_ISR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)

Definition at line 20267 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR1_MASK

#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU)

Definition at line 20265 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR1_SHIFT

#define GPC_ISR_ISR1_SHIFT (0U)

Definition at line 20266 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR2

#define GPC_ISR_ISR2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)

Definition at line 20270 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR2_MASK

#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU)

Definition at line 20268 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR2_SHIFT

#define GPC_ISR_ISR2_SHIFT (0U)

Definition at line 20269 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR3

#define GPC_ISR_ISR3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)

Definition at line 20273 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR3_MASK

#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU)

Definition at line 20271 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR3_SHIFT

#define GPC_ISR_ISR3_SHIFT (0U)

Definition at line 20272 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR4

#define GPC_ISR_ISR4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)

Definition at line 20276 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR4_MASK

#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU)

Definition at line 20274 of file MIMXRT1062.h.

## ◆ GPC_ISR_ISR4_SHIFT

#define GPC_ISR_ISR4_SHIFT (0U)

Definition at line 20275 of file MIMXRT1062.h.