Callisto4Bootloader: IOMUXC_GPR Register Masks

Callisto4Bootloader

IOMUXC_GPR Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » IOMUXC_GPR Peripheral Access Layer

## GPR1 - GPR1 General Purpose Register

#define | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
#define | IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
#define | IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
#define | IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
#define | IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)
#define | IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)
#define | IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
#define | IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U)
#define | IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U)
#define | IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK)
#define | IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)
#define | IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)
#define | IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
#define | IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)
#define | IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)
#define | IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U)
#define | IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U)
#define | IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
#define | IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
#define | IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
#define | IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)
#define | IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)
#define | IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
#define | IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
#define | IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)

## GPR2 - GPR2 General Purpose Register

#define | IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK (0x1U)
#define | IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT (0U)
#define | IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK (0x2U)
#define | IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT (1U)
#define | IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK (0x4U)
#define | IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT (2U)
#define | IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK (0x8U)
#define | IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT (3U)
#define | IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK (0x10U)
#define | IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT (4U)
#define | IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK (0x20U)
#define | IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT (5U)
#define | IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK)
#define | IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK (0x40U)
#define | IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT (6U)
#define | IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK)
#define | IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
#define | IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
#define | IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
#define | IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U)
#define | IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U)
#define | IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK)
#define | IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
#define | IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
#define | IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
#define | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
#define | IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
#define | IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
#define | IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
#define | IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
#define | IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
#define | IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
#define | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
#define | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
#define | IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
#define | IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
#define | IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
#define | IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
#define | IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
#define | IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
#define | IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
#define | IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)

## GPR3 - GPR3 General Purpose Register

#define | IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)
#define | IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)
#define | IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
#define | IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
#define | IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
#define | IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
#define | IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK (0xF00U)
#define | IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT (8U)
#define | IOMUXC_GPR_GPR3_OCRAM2_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK (0x8000U)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT (15U)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK)
#define | IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)
#define | IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)
#define | IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
#define | IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK (0xF000000U)
#define | IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT (24U)
#define | IOMUXC_GPR_GPR3_OCRAM2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT (31U)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALTED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)

## GPR4 - GPR4 General Purpose Register

#define | IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
#define | IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
#define | IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x100U)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (8U)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
#define | IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
#define | IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK (0x4000U)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT (14U)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK (0x8000U)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT (15U)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
#define | IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
#define | IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (24U)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
#define | IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT (30U)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT (31U)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK)

## GPR5 - GPR5 General Purpose Register

#define | IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
#define | IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
#define | IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
#define | IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
#define | IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
#define | IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK)
#define | IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
#define | IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
#define | IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U)
#define | IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)

## GPR6 - GPR6 General Purpose Register

#define | IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)

## GPR7 - GPR7 General Purpose Register

#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)

## GPR8 - GPR8 General Purpose Register

#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)

## GPR10 - GPR10 General Purpose Register

#define | IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
#define | IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
#define | IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
#define | IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
#define | IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
#define | IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
#define | IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
#define | IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
#define | IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
#define | IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
#define | IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
#define | IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
#define | IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
#define | IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
#define | IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
#define | IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
#define | IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
#define | IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
#define | IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
#define | IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)

## GPR11 - GPR11 General Purpose Register

#define | IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
#define | IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
#define | IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
#define | IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)

## GPR12 - GPR12 General Purpose Register

#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
#define | IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
#define | IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK (0x20U)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT (5U)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK (0x40U)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT (6U)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK)

## GPR13 - GPR13 General Purpose Register

#define | IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
#define | IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
#define | IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
#define | IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
#define | IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
#define | IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK (0x10U)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT (4U)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
#define | IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
#define | IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
#define | IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
#define | IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
#define | IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK (0x100000U)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT (20U)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK)

## GPR14 - GPR14 General Purpose Register

#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
#define | IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
#define | IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
#define | IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
#define | IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
#define | IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
#define | IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
#define | IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
#define | IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
#define | IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
#define | IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)
#define | IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)
#define | IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
#define | IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)
#define | IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)
#define | IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)

## GPR16 - GPR16 General Purpose Register

#define | IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)
#define | IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)
#define | IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
#define | IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)
#define | IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)
#define | IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)

## GPR17 - GPR17 General Purpose Register

#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)

## GPR18 - GPR18 General Purpose Register

#define | IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
#define | IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
#define | IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
#define | IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
#define | IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)

## GPR19 - GPR19 General Purpose Register

#define | IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
#define | IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
#define | IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
#define | IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
#define | IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)

## GPR20 - GPR20 General Purpose Register

#define | IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
#define | IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
#define | IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
#define | IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
#define | IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)

## GPR21 - GPR21 General Purpose Register

#define | IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
#define | IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
#define | IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
#define | IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
#define | IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)

## GPR22 - GPR22 General Purpose Register

#define | IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
#define | IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
#define | IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
#define | IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
#define | IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)

## GPR23 - GPR23 General Purpose Register

#define | IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
#define | IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
#define | IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
#define | IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
#define | IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)

## GPR24 - GPR24 General Purpose Register

#define | IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
#define | IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
#define | IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
#define | IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)
#define | IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)

## GPR25 - GPR25 General Purpose Register

#define | IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
#define | IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
#define | IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
#define | IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
#define | IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)

## GPR26 - GPR26 General Purpose Register

#define | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)

## GPR27 - GPR27 General Purpose Register

#define | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)

## GPR28 - GPR28 General Purpose Register

#define | IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK)

## GPR29 - GPR29 General Purpose Register

#define | IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK)

## GPR30 - GPR30 General Purpose Register

#define | IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK (0xFFFFF000U)
#define | IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT (12U)
#define | IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT)) & IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK)

## GPR31 - GPR31 General Purpose Register

#define | IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK (0xFFFFF000U)
#define | IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT (12U)
#define | IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT)) & IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK)

## GPR32 - GPR32 General Purpose Register

#define | IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK (0xFFFFF000U)
#define | IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT (12U)
#define | IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT)) & IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK)

## GPR33 - GPR33 General Purpose Register

#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK (0x1U)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT (0U)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK (0xFEU)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT (1U)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK (0x10000U)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT (16U)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK (0xFE0000U)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT (17U)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK)

## GPR34 - GPR34 General Purpose Register

#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK (0xFFU)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK (0x100U)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT (8U)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ IOMUXC_GPR_GPR10_DBG_EN

#define IOMUXC_GPR_GPR10_DBG_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)

DBG_EN 0b0..Debug turned off. 0b1..Debug enabled (default).

Definition at line 23786 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_DBG_EN_MASK

#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)

Definition at line 23780 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_DBG_EN_SHIFT

#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)

Definition at line 23781 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX

#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)

DCPKEY_OCOTP_OR_KEYMUX 0b0..Select key from Key MUX (SNVS/OTPMK). 0b1..Select key from OCOTP (SW_GP2).

Definition at line 23800 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK

#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)

Definition at line 23794 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT

#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)

Definition at line 23795 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_DBG_EN

#define IOMUXC_GPR_GPR10_LOCK_DBG_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)

LOCK_DBG_EN 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 23825 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK

#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)

Definition at line 23819 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)

Definition at line 23820 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX

#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)

LOCK_DCPKEY_OCOTP_OR_KEYMUX 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 23839 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK

#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)

Definition at line 23833 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)

Definition at line 23834 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_NIDEN

#define IOMUXC_GPR_GPR10_LOCK_NIDEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)

LOCK_NIDEN 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 23818 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK

#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)

Definition at line 23812 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)

Definition at line 23813 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)

LOCK_OCRAM_TZ_ADDR 0b0000000..Field is not locked 0b0000001..Field is locked (read access only)

Definition at line 23853 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)

Definition at line 23847 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)

Definition at line 23848 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)

LOCK_OCRAM_TZ_EN 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 23846 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)

Definition at line 23840 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)

Definition at line 23841 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP

#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)

LOCK_SEC_ERR_RESP 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 23832 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK

#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)

Definition at line 23826 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT

#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)

Definition at line 23827 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_NIDEN

#define IOMUXC_GPR_GPR10_NIDEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)

NIDEN 0b0..Debug turned off. 0b1..Debug enabled (default).

Definition at line 23779 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_NIDEN_MASK

#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)

Definition at line 23773 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_NIDEN_SHIFT

#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)

Definition at line 23774 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR

#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)

Definition at line 23811 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK

#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)

Definition at line 23809 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT

#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)

Definition at line 23810 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_OCRAM_TZ_EN

#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)

OCRAM_TZ_EN 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.

Definition at line 23808 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK

#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)

Definition at line 23801 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT

#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)

Definition at line 23802 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_SEC_ERR_RESP

#define IOMUXC_GPR_GPR10_SEC_ERR_RESP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)

SEC_ERR_RESP 0b0..OKEY response 0b1..SLVError (default)

Definition at line 23793 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK

#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)

Definition at line 23787 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT

#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)

Definition at line 23788 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_BEE_DE_RX_EN

#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)

Definition at line 23896 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK

#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)

Definition at line 23894 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT

#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)

Definition at line 23895 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)

M7_APC_AC_R0_CTRL 0b00..No access protection 0b01..M7 debug protection enabled 0b10..FlexSPI access protection 0b11..Both M7 debug and FlexSPI access are protected

Definition at line 23866 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)

Definition at line 23858 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)

Definition at line 23859 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)

M7_APC_AC_R1_CTRL 0b00..No access protection 0b01..M7 debug protection enabled 0b10..FlexSPI access protection 0b11..Both M7 debug and FlexSPI access are protected

Definition at line 23875 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK

#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)

Definition at line 23867 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)

Definition at line 23868 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)

M7_APC_AC_R2_CTRL 0b00..No access protection 0b01..M7 debug protection enabled 0b10..FlexSPI access protection 0b11..Both M7 debug and FlexSPI access are protected

Definition at line 23884 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK

#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)

Definition at line 23876 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)

Definition at line 23877 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)

M7_APC_AC_R3_CTRL 0b00..No access protection 0b01..M7 debug protection enabled 0b10..FlexSPI access protection 0b11..Both M7 debug and FlexSPI access are protected

Definition at line 23893 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK

#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)

Definition at line 23885 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT

#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)

Definition at line 23886 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)

ACMP_IPG_STOP_MODE 0b0..ACMP is functional in Stop mode. 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode.

Definition at line 23935 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)

Definition at line 23929 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)

Definition at line 23930 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)

FLEXIO1_IPG_DOZE 0b0..FLEXIO1 is not in doze mode 0b1..FLEXIO1 is in doze mode

Definition at line 23914 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)

Definition at line 23908 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)

Definition at line 23909 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)

FLEXIO1_IPG_STOP_MODE 0b0..FlexIO1 is functional in Stop mode. 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode.

Definition at line 23907 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)

Definition at line 23901 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)

Definition at line 23902 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)

FLEXIO2_IPG_DOZE 0b0..FLEXIO2 is not in doze mode 0b1..FLEXIO2 is in doze mode

Definition at line 23928 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)

Definition at line 23922 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)

Definition at line 23923 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)

FLEXIO2_IPG_STOP_MODE 0b0..FlexIO2 is functional in Stop mode. 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode.

Definition at line 23921 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)

Definition at line 23915 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)

Definition at line 23916 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE

#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK)

FLEXIO3_IPG_DOZE 0b0..FLEXIO3 is not in doze mode 0b1..FLEXIO3 is in doze mode

Definition at line 23949 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK (0x40U)

Definition at line 23943 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT (6U)

Definition at line 23944 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK)

FLEXIO3_IPG_STOP_MODE 0b0..FlexIO3 is functional in Stop mode. 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO3 is not functional in Stop mode.

Definition at line 23942 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK (0x20U)

Definition at line 23936 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT (5U)

Definition at line 23937 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_ARCACHE_USDHC

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)

ARCACHE_USDHC 0b0..Cacheable attribute is off for read transactions. 0b1..Cacheable attribute is on for read transactions.

Definition at line 23960 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)

Definition at line 23954 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)

Definition at line 23955 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_AWCACHE_USDHC

#define IOMUXC_GPR_GPR13_AWCACHE_USDHC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)

AWCACHE_USDHC 0b0..Cacheable attribute is off for write transactions. 0b1..Cacheable attribute is on for write transactions.

Definition at line 23967 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK

#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)

Definition at line 23961 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT

#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)

Definition at line 23962 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CACHE_ENET

#define IOMUXC_GPR_GPR13_CACHE_ENET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)

CACHE_ENET 0b0..Cacheable attribute is off for read/write transactions. 0b1..Cacheable attribute is on for read/write transactions.

Definition at line 23981 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CACHE_ENET_MASK

#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)

Definition at line 23975 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT

#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)

Definition at line 23976 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CACHE_USB

#define IOMUXC_GPR_GPR13_CACHE_USB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)

CACHE_USB 0b0..Cacheable attribute is off for read/write transactions. 0b1..Cacheable attribute is on for read/write transactions.

Definition at line 23988 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CACHE_USB_MASK

#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)

Definition at line 23982 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CACHE_USB_SHIFT

#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)

Definition at line 23983 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CANFD_STOP_ACK

#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK)

CANFD_STOP_ACK 0b0..CANFD stop acknowledge is not asserted 0b1..CANFD stop acknowledge is asserted

Definition at line 23995 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK

#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK (0x100000U)

Definition at line 23989 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT (20U)

Definition at line 23990 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CANFD_STOP_REQ

#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK)

CANFD_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23974 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK

#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK (0x10U)

Definition at line 23968 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT (4U)

Definition at line 23969 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)

ACMP1_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

Definition at line 24006 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)

Definition at line 24000 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)

Definition at line 24001 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)

ACMP1_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

Definition at line 24034 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)

Definition at line 24028 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)

Definition at line 24029 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)

ACMP1_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

Definition at line 24062 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK

#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)

Definition at line 24056 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)

Definition at line 24057 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)

ACMP2_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

Definition at line 24013 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)

Definition at line 24007 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)

Definition at line 24008 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)

ACMP2_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

Definition at line 24041 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)

Definition at line 24035 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)

Definition at line 24036 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)

ACMP2_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

Definition at line 24069 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK

#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)

Definition at line 24063 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)

Definition at line 24064 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)

ACMP3_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

Definition at line 24020 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)

Definition at line 24014 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)

Definition at line 24015 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)

ACMP3_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

Definition at line 24048 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)

Definition at line 24042 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)

Definition at line 24043 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)

ACMP3_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

Definition at line 24076 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK

#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)

Definition at line 24070 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)

Definition at line 24071 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)

ACMP4_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

Definition at line 24027 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)

Definition at line 24021 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)

Definition at line 24022 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)

ACMP4_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

Definition at line 24055 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)

Definition at line 24049 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)

Definition at line 24050 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)

ACMP4_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

Definition at line 24083 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK

#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)

Definition at line 24077 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT

#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)

Definition at line 24078 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ

#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)

CM7_CFGDTCMSZ 0b0000..0 KB (No DTCM) 0b0011..4 KB 0b0100..8 KB 0b0101..16 KB 0b0110..32 KB 0b0111..64 KB 0b1000..128 KB 0b1001..256 KB 0b1010..512 KB

Definition at line 24111 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK

#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)

Definition at line 24098 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT

#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)

Definition at line 24099 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_CM7_CFGITCMSZ

#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)

CM7_CFGITCMSZ 0b0000..0 KB (No ITCM) 0b0011..4 KB 0b0100..8 KB 0b0101..16 KB 0b0110..32 KB 0b0111..64 KB 0b1000..128 KB 0b1001..256 KB 0b1010..512 KB

Definition at line 24097 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK

#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)

Definition at line 24084 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT

#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)

Definition at line 24085 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)

FLEXRAM_BANK_CFG_SEL 0b0..use fuse value to config 0b1..use FLEXRAM_BANK_CFG to config

Definition at line 24136 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)

Definition at line 24130 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)

Definition at line 24131 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_INIT_DTCM_EN

#define IOMUXC_GPR_GPR16_INIT_DTCM_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)

INIT_DTCM_EN 0b0..DTCM is disabled 0b1..DTCM is enabled

Definition at line 24129 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK

#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)

Definition at line 24123 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT

#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)

Definition at line 24124 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_INIT_ITCM_EN

#define IOMUXC_GPR_GPR16_INIT_ITCM_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)

INIT_ITCM_EN 0b0..ITCM is disabled 0b1..ITCM is enabled

Definition at line 24122 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK

#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)

Definition at line 24116 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT

#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)

Definition at line 24117 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)

FLEXRAM_BANK_CFG - FlexRAM bank config value

Definition at line 24145 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)

Definition at line 24141 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)

Definition at line 24142 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)

LOCK_M7_APC_AC_R0_BOT 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 24156 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)

Definition at line 24150 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)

Definition at line 24151 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT

#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)

Definition at line 24159 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK

#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)

Definition at line 24157 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT

#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)

Definition at line 24158 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)

LOCK_M7_APC_AC_R0_TOP 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 24170 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)

Definition at line 24164 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)

Definition at line 24165 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP

#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)

Definition at line 24173 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK

#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)

Definition at line 24171 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT

#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)

Definition at line 24172 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN

#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)

CM7_FORCE_HCLK_EN 0b0..AHB clock is not running (gated) 0b1..AHB clock is running (enabled)

Definition at line 22375 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK

#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)

Definition at line 22369 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT

#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)

Definition at line 22370 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET1_CLK_SEL

#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)

ENET1_CLK_SEL 0b0..ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller.

Definition at line 22304 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK

#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)

Definition at line 22297 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT

#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)

Definition at line 22298 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR

#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)

ENET1_TX_CLK_DIR 0b0..ENET1_TX_CLK output driver is disabled 0b1..ENET1_TX_CLK output driver is enabled

Definition at line 22326 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK

#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)

Definition at line 22320 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)

Definition at line 22321 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET2_CLK_SEL

#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK)

ENET2_CLK_SEL 0b0..ENET2 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET2_REF_CLK function. 0b1..Gets ENET2 TX reference clock from the ENET2_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller.

Definition at line 22312 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK

#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U)

Definition at line 22305 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT

#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U)

Definition at line 22306 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR

#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK)

ENET2_TX_CLK_DIR 0b0..ENET2_TX_CLK output driver is disabled 0b1..ENET2_TX_CLK output driver is enabled

Definition at line 22333 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK

#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U)

Definition at line 22327 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U)

Definition at line 22328 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN

#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)

ENET_IPG_CLK_S_EN 0b0..ipg_clk_s is gated when there is no IPS access 0b1..ipg_clk_s is always on

Definition at line 22368 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK

#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)

Definition at line 22362 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT

#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)

Definition at line 22363 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_EXC_MON

#define IOMUXC_GPR_GPR1_EXC_MON | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)

EXC_MON 0b0..OKAY response 0b1..SLVError response (default)

Definition at line 22361 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_EXC_MON_MASK

#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)

Definition at line 22355 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_EXC_MON_SHIFT

#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)

Definition at line 22356 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_GINT

#define IOMUXC_GPR_GPR1_GINT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)

GINT 0b0..Global interrupt request is not asserted. 0b1..Global interrupt request is asserted.

Definition at line 22296 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_GINT_MASK

#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)

Definition at line 22290 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_GINT_SHIFT

#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U)

Definition at line 22291 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)

SAI1_MCLK1_SEL 0b000..ccm.ssi1_clk_root 0b001..ccm.ssi2_clk_root 0b010..ccm.ssi3_clk_root 0b011..iomux.sai1_ipg_clk_sai_mclk 0b100..iomux.sai2_ipg_clk_sai_mclk 0b101..iomux.sai3_ipg_clk_sai_mclk 0b110..Reserved 0b111..Reserved

Definition at line 22249 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)

Definition at line 22237 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)

Definition at line 22238 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)

SAI1_MCLK2_SEL 0b000..ccm.ssi1_clk_root 0b001..ccm.ssi2_clk_root 0b010..ccm.ssi3_clk_root 0b011..iomux.sai1_ipg_clk_sai_mclk 0b100..iomux.sai2_ipg_clk_sai_mclk 0b101..iomux.sai3_ipg_clk_sai_mclk 0b110..Reserved 0b111..Reserved

Definition at line 22262 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)

Definition at line 22250 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)

Definition at line 22251 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)

SAI1_MCLK3_SEL 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

Definition at line 22271 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)

Definition at line 22263 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)

Definition at line 22264 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK_DIR

#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)

SAI1_MCLK_DIR 0b0..sai1.MCLK is input signal 0b1..sai1.MCLK is output signal

Definition at line 22340 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK

#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)

Definition at line 22334 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)

Definition at line 22335 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)

SAI2_MCLK3_SEL 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

Definition at line 22280 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)

Definition at line 22272 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)

Definition at line 22273 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)

SAI2_MCLK_DIR 0b0..sai2.MCLK is input signal 0b1..sai2.MCLK is output signal

Definition at line 22347 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)

Definition at line 22341 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)

Definition at line 22342 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL

#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)

SAI3_MCLK3_SEL 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

Definition at line 22289 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK

#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)

Definition at line 22281 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT

#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)

Definition at line 22282 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI3_MCLK_DIR

#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)

SAI3_MCLK_DIR 0b0..sai3.MCLK is input signal 0b1..sai3.MCLK is output signal

Definition at line 22354 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK

#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)

Definition at line 22348 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT

#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)

Definition at line 22349 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_USB_EXP_MODE

#define IOMUXC_GPR_GPR1_USB_EXP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)

USB_EXP_MODE 0b0..Exposure mode is disabled. 0b1..Exposure mode is enabled.

Definition at line 22319 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK

#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)

Definition at line 22313 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT

#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)

Definition at line 22314 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)

LOCK_M7_APC_AC_R1_BOT 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 24184 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)

Definition at line 24178 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)

Definition at line 24179 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT

#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)

Definition at line 24187 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK

#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)

Definition at line 24185 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT

#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)

Definition at line 24186 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)

LOCK_M7_APC_AC_R1_TOP 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 24198 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)

Definition at line 24192 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)

Definition at line 24193 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP

#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)

Definition at line 24201 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK

#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)

Definition at line 24199 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT

#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)

Definition at line 24200 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)

LOCK_M7_APC_AC_R2_BOT 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 24212 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)

Definition at line 24206 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)

Definition at line 24207 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT

#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)

Definition at line 24215 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK

#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)

Definition at line 24213 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT

#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)

Definition at line 24214 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)

LOCK_M7_APC_AC_R2_TOP 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 24226 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)

Definition at line 24220 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)

Definition at line 24221 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP

#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)

Definition at line 24229 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK

#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)

Definition at line 24227 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT

#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)

Definition at line 24228 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)

LOCK_M7_APC_AC_R3_BOT 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 24240 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)

Definition at line 24234 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)

Definition at line 24235 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT

#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)

Definition at line 24243 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK

#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)

Definition at line 24241 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT

#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)

Definition at line 24242 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)

LOCK_M7_APC_AC_R3_TOP 0b0..Register field [31:1] is not locked 0b1..Register field [31:1] is locked (read access only)

Definition at line 24254 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)

Definition at line 24248 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)

Definition at line 24249 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP

#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)

Definition at line 24257 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK

#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)

Definition at line 24255 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT

#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)

Definition at line 24256 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL

#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)

GPIO_MUX1_GPIO_SEL - GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function.

Definition at line 24266 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK

#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK (0xFFFFFFFFU)

Definition at line 24262 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT

#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT (0U)

Definition at line 24263 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL

#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)

GPIO_MUX2_GPIO_SEL - GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function.

Definition at line 24275 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK

#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK (0xFFFFFFFFU)

Definition at line 24271 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT

#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT (0U)

Definition at line 24272 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL

#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK)

GPIO_MUX3_GPIO_SEL - GPIO3 and GPIO8 share same IO MUX function, GPIO_MUX3 selects one GPIO function.

Definition at line 24284 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK

#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK (0xFFFFFFFFU)

Definition at line 24280 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT

#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT (0U)

Definition at line 24281 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL

#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK)

GPIO_MUX4_GPIO_SEL - GPIO4 and GPIO9 share same IO MUX function, GPIO_MUX4 selects one GPIO function.

Definition at line 24293 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK

#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK (0xFFFFFFFFU)

Definition at line 24289 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT

#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT (0U)

Definition at line 24290 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY

#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK)

AXBS_L_AHBXL_HIGH_PRIORITY 0b0..AXBS_L AHBXL master does not have high priority 0b1..AXBS_P AHBXL master has high priority

Definition at line 22386 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK

#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK (0x1U)

Definition at line 22380 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT

#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT (0U)

Definition at line 22381 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY

#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK)

AXBS_L_DMA_HIGH_PRIORITY 0b0..AXBS_L DMA master does not have high priority 0b1..AXBS_L DMA master has high priority

Definition at line 22393 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK

#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK (0x2U)

Definition at line 22387 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT

#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT (1U)

Definition at line 22388 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN

#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK)

AXBS_L_FORCE_ROUND_ROBIN 0b0..AXBS_L masters are not arbitored in round robin, depending on DMA and AHBXL master priority settings. 0b1..AXBS_L masters are arbitored in round robin

Definition at line 22400 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK

#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK (0x4U)

Definition at line 22394 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT

#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT (2U)

Definition at line 22395 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN

#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK)

AXBS_P_FORCE_ROUND_ROBIN 0b0..AXBS_P masters are not arbitored in round robin, depending on M0/M1 master priority settings. 0b1..AXBS_P masters are arbitored in round robin

Definition at line 22421 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK

#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK (0x20U)

Definition at line 22415 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT

#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT (5U)

Definition at line 22416 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY

#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK)

AXBS_P_M0_HIGH_PRIORITY 0b0..AXBS_P M0 master doesn't have high priority 0b1..AXBS_P M0 master has high priority

Definition at line 22407 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK

#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK (0x8U)

Definition at line 22401 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT

#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT (3U)

Definition at line 22402 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY

#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK)

AXBS_P_M1_HIGH_PRIORITY 0b0..AXBS_P M1 master does not have high priority 0b1..AXBS_P M1 master has high priority

Definition at line 22414 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK

#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK (0x10U)

Definition at line 22408 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT

#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT (4U)

Definition at line 22409 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS

#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK)

CANFD_FILTER_BYPASS 0b0..enable CANFD filter 0b1..disable CANFD filter

Definition at line 22428 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK

#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK (0x40U)

Definition at line 22422 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT

#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT (6U)

Definition at line 22423 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP

#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)

L2_MEM_DEEPSLEEP 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode 0b1..force memory into deep sleep mode

Definition at line 22449 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK

#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)

Definition at line 22443 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT

#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)

Definition at line 22444 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)

L2_MEM_EN_POWERSAVING 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP (priority high to low) to enable power saving levels

Definition at line 22435 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)

Definition at line 22429 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)

Definition at line 22430 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_CLK_DIV

#define IOMUXC_GPR_GPR2_MQS_CLK_DIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)

MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. 0b00000000..mclk frequency = 1/1 * hmclk frequency 0b00000001..mclk frequency = 1/2 * hmclk frequency 0b00000010..mclk frequency = 1/3 * hmclk frequency 0b00000011..mclk frequency = 1/4 * hmclk frequency 0b00000100..mclk frequency = 1/5 * hmclk frequency 0b00000101..mclk frequency = 1/6 * hmclk frequency 0b00000110..mclk frequency = 1/7 * hmclk frequency 0b00000111..mclk frequency = 1/8 * hmclk frequency 0b00001000..mclk frequency = 1/9 * hmclk frequency 0b00001001..mclk frequency = 1/10 * hmclk frequency 0b00001010..mclk frequency = 1/11 * hmclk frequency 0b00001011..mclk frequency = 1/12 * hmclk frequency 0b00001100..mclk frequency = 1/13 * hmclk frequency 0b00001101..mclk frequency = 1/14 * hmclk frequency 0b00001110..mclk frequency = 1/15 * hmclk frequency 0b00001111..mclk frequency = 1/16 * hmclk frequency 0b00010000..mclk frequency = 1/17 * hmclk frequency 0b00010001..mclk frequency = 1/18 * hmclk frequency 0b00010010..mclk frequency = 1/19 * hmclk frequency 0b00010011..mclk frequency = 1/20 * hmclk frequency 0b00010100..mclk frequency = 1/21 * hmclk frequency 0b00010101..mclk frequency = 1/22 * hmclk frequency 0b00010110..mclk frequency = 1/23 * hmclk frequency 0b00010111..mclk frequency = 1/24 * hmclk frequency 0b00011000..mclk frequency = 1/25 * hmclk frequency 0b00011001..mclk frequency = 1/26 * hmclk frequency 0b00011010..mclk frequency = 1/27 * hmclk frequency 0b00011011..mclk frequency = 1/28 * hmclk frequency 0b00011100..mclk frequency = 1/29 * hmclk frequency 0b00011101..mclk frequency = 1/30 * hmclk frequency 0b00011110..mclk frequency = 1/31 * hmclk frequency 0b00011111..mclk frequency = 1/32 * hmclk frequency 0b00100000..mclk frequency = 1/33 * hmclk frequency 0b00100001..mclk frequency = 1/34 * hmclk frequency 0b00100010..mclk frequency = 1/35 * hmclk frequency 0b00100011..mclk frequency = 1/36 * hmclk frequency 0b00100100..mclk frequency = 1/37 * hmclk frequency 0b00100101..mclk frequency = 1/38 * hmclk frequency 0b00100110..mclk frequency = 1/39 * hmclk frequency 0b00100111..mclk frequency = 1/40 * hmclk frequency 0b00101000..mclk frequency = 1/41 * hmclk frequency 0b00101001..mclk frequency = 1/42 * hmclk frequency 0b00101010..mclk frequency = 1/43 * hmclk frequency 0b00101011..mclk frequency = 1/44 * hmclk frequency 0b00101100..mclk frequency = 1/45 * hmclk frequency 0b00101101..mclk frequency = 1/46 * hmclk frequency 0b00101110..mclk frequency = 1/47 * hmclk frequency 0b00101111..mclk frequency = 1/48 * hmclk frequency 0b00110000..mclk frequency = 1/49 * hmclk frequency 0b00110001..mclk frequency = 1/50 * hmclk frequency 0b00110010..mclk frequency = 1/51 * hmclk frequency 0b00110011..mclk frequency = 1/52 * hmclk frequency 0b00110100..mclk frequency = 1/53 * hmclk frequency 0b00110101..mclk frequency = 1/54 * hmclk frequency 0b00110110..mclk frequency = 1/55 * hmclk frequency 0b00110111..mclk frequency = 1/56 * hmclk frequency 0b00111000..mclk frequency = 1/57 * hmclk frequency 0b00111001..mclk frequency = 1/58 * hmclk frequency 0b00111010..mclk frequency = 1/59 * hmclk frequency 0b00111011..mclk frequency = 1/60 * hmclk frequency 0b00111100..mclk frequency = 1/61 * hmclk frequency 0b00111101..mclk frequency = 1/62 * hmclk frequency 0b00111110..mclk frequency = 1/63 * hmclk frequency 0b00111111..mclk frequency = 1/64 * hmclk frequency 0b01000000..mclk frequency = 1/65 * hmclk frequency 0b01000001..mclk frequency = 1/66 * hmclk frequency 0b01000010..mclk frequency = 1/67 * hmclk frequency 0b01000011..mclk frequency = 1/68 * hmclk frequency 0b01000100..mclk frequency = 1/69 * hmclk frequency 0b01000101..mclk frequency = 1/70 * hmclk frequency 0b01000110..mclk frequency = 1/71 * hmclk frequency 0b01000111..mclk frequency = 1/72 * hmclk frequency 0b01001000..mclk frequency = 1/73 * hmclk frequency 0b01001001..mclk frequency = 1/74 * hmclk frequency 0b01001010..mclk frequency = 1/75 * hmclk frequency 0b01001011..mclk frequency = 1/76 * hmclk frequency 0b01001100..mclk frequency = 1/77 * hmclk frequency 0b01001101..mclk frequency = 1/78 * hmclk frequency 0b01001110..mclk frequency = 1/79 * hmclk frequency 0b01001111..mclk frequency = 1/80 * hmclk frequency 0b01010000..mclk frequency = 1/81 * hmclk frequency 0b01010001..mclk frequency = 1/82 * hmclk frequency 0b01010010..mclk frequency = 1/83 * hmclk frequency 0b01010011..mclk frequency = 1/84 * hmclk frequency 0b01010100..mclk frequency = 1/85 * hmclk frequency 0b01010101..mclk frequency = 1/86 * hmclk frequency 0b01010110..mclk frequency = 1/87 * hmclk frequency 0b01010111..mclk frequency = 1/88 * hmclk frequency 0b01011000..mclk frequency = 1/89 * hmclk frequency 0b01011001..mclk frequency = 1/90 * hmclk frequency 0b01011010..mclk frequency = 1/91 * hmclk frequency 0b01011011..mclk frequency = 1/92 * hmclk frequency 0b01011100..mclk frequency = 1/93 * hmclk frequency 0b01011101..mclk frequency = 1/94 * hmclk frequency 0b01011110..mclk frequency = 1/95 * hmclk frequency 0b01011111..mclk frequency = 1/96 * hmclk frequency 0b01100000..mclk frequency = 1/97 * hmclk frequency 0b01100001..mclk frequency = 1/98 * hmclk frequency 0b01100010..mclk frequency = 1/99 * hmclk frequency 0b01100011..mclk frequency = 1/100 * hmclk frequency 0b01100100..mclk frequency = 1/101 * hmclk frequency 0b01100101..mclk frequency = 1/102 * hmclk frequency 0b01100110..mclk frequency = 1/103 * hmclk frequency 0b01100111..mclk frequency = 1/104 * hmclk frequency 0b01101000..mclk frequency = 1/105 * hmclk frequency 0b01101001..mclk frequency = 1/106 * hmclk frequency 0b01101010..mclk frequency = 1/107 * hmclk frequency 0b01101011..mclk frequency = 1/108 * hmclk frequency 0b01101100..mclk frequency = 1/109 * hmclk frequency 0b01101101..mclk frequency = 1/110 * hmclk frequency 0b01101110..mclk frequency = 1/111 * hmclk frequency 0b01101111..mclk frequency = 1/112 * hmclk frequency 0b01110000..mclk frequency = 1/113 * hmclk frequency 0b01110001..mclk frequency = 1/114 * hmclk frequency 0b01110010..mclk frequency = 1/115 * hmclk frequency 0b01110011..mclk frequency = 1/116 * hmclk frequency 0b01110100..mclk frequency = 1/117 * hmclk frequency 0b01110101..mclk frequency = 1/118 * hmclk frequency 0b01110110..mclk frequency = 1/119 * hmclk frequency 0b01110111..mclk frequency = 1/120 * hmclk frequency 0b01111000..mclk frequency = 1/121 * hmclk frequency 0b01111001..mclk frequency = 1/122 * hmclk frequency 0b01111010..mclk frequency = 1/123 * hmclk frequency 0b01111011..mclk frequency = 1/124 * hmclk frequency 0b01111100..mclk frequency = 1/125 * hmclk frequency 0b01111101..mclk frequency = 1/126 * hmclk frequency 0b01111110..mclk frequency = 1/127 * hmclk frequency 0b01111111..mclk frequency = 1/128 * hmclk frequency 0b10000000..mclk frequency = 1/129 * hmclk frequency 0b10000001..mclk frequency = 1/130 * hmclk frequency 0b10000010..mclk frequency = 1/131 * hmclk frequency 0b10000011..mclk frequency = 1/132 * hmclk frequency 0b10000100..mclk frequency = 1/133 * hmclk frequency 0b10000101..mclk frequency = 1/134 * hmclk frequency 0b10000110..mclk frequency = 1/135 * hmclk frequency 0b10000111..mclk frequency = 1/136 * hmclk frequency 0b10001000..mclk frequency = 1/137 * hmclk frequency 0b10001001..mclk frequency = 1/138 * hmclk frequency 0b10001010..mclk frequency = 1/139 * hmclk frequency 0b10001011..mclk frequency = 1/140 * hmclk frequency 0b10001100..mclk frequency = 1/141 * hmclk frequency 0b10001101..mclk frequency = 1/142 * hmclk frequency 0b10001110..mclk frequency = 1/143 * hmclk frequency 0b10001111..mclk frequency = 1/144 * hmclk frequency 0b10010000..mclk frequency = 1/145 * hmclk frequency 0b10010001..mclk frequency = 1/146 * hmclk frequency 0b10010010..mclk frequency = 1/147 * hmclk frequency 0b10010011..mclk frequency = 1/148 * hmclk frequency 0b10010100..mclk frequency = 1/149 * hmclk frequency 0b10010101..mclk frequency = 1/150 * hmclk frequency 0b10010110..mclk frequency = 1/151 * hmclk frequency 0b10010111..mclk frequency = 1/152 * hmclk frequency 0b10011000..mclk frequency = 1/153 * hmclk frequency 0b10011001..mclk frequency = 1/154 * hmclk frequency 0b10011010..mclk frequency = 1/155 * hmclk frequency 0b10011011..mclk frequency = 1/156 * hmclk frequency 0b10011100..mclk frequency = 1/157 * hmclk frequency 0b10011101..mclk frequency = 1/158 * hmclk frequency 0b10011110..mclk frequency = 1/159 * hmclk frequency 0b10011111..mclk frequency = 1/160 * hmclk frequency 0b10100000..mclk frequency = 1/161 * hmclk frequency 0b10100001..mclk frequency = 1/162 * hmclk frequency 0b10100010..mclk frequency = 1/163 * hmclk frequency 0b10100011..mclk frequency = 1/164 * hmclk frequency 0b10100100..mclk frequency = 1/165 * hmclk frequency 0b10100101..mclk frequency = 1/166 * hmclk frequency 0b10100110..mclk frequency = 1/167 * hmclk frequency 0b10100111..mclk frequency = 1/168 * hmclk frequency 0b10101000..mclk frequency = 1/169 * hmclk frequency 0b10101001..mclk frequency = 1/170 * hmclk frequency 0b10101010..mclk frequency = 1/171 * hmclk frequency 0b10101011..mclk frequency = 1/172 * hmclk frequency 0b10101100..mclk frequency = 1/173 * hmclk frequency 0b10101101..mclk frequency = 1/174 * hmclk frequency 0b10101110..mclk frequency = 1/175 * hmclk frequency 0b10101111..mclk frequency = 1/176 * hmclk frequency 0b10110000..mclk frequency = 1/177 * hmclk frequency 0b10110001..mclk frequency = 1/178 * hmclk frequency 0b10110010..mclk frequency = 1/179 * hmclk frequency 0b10110011..mclk frequency = 1/180 * hmclk frequency 0b10110100..mclk frequency = 1/181 * hmclk frequency 0b10110101..mclk frequency = 1/182 * hmclk frequency 0b10110110..mclk frequency = 1/183 * hmclk frequency 0b10110111..mclk frequency = 1/184 * hmclk frequency 0b10111000..mclk frequency = 1/185 * hmclk frequency 0b10111001..mclk frequency = 1/186 * hmclk frequency 0b10111010..mclk frequency = 1/187 * hmclk frequency 0b10111011..mclk frequency = 1/188 * hmclk frequency 0b10111100..mclk frequency = 1/189 * hmclk frequency 0b10111101..mclk frequency = 1/190 * hmclk frequency 0b10111110..mclk frequency = 1/191 * hmclk frequency 0b10111111..mclk frequency = 1/192 * hmclk frequency 0b11000000..mclk frequency = 1/193 * hmclk frequency 0b11000001..mclk frequency = 1/194 * hmclk frequency 0b11000010..mclk frequency = 1/195 * hmclk frequency 0b11000011..mclk frequency = 1/196 * hmclk frequency 0b11000100..mclk frequency = 1/197 * hmclk frequency 0b11000101..mclk frequency = 1/198 * hmclk frequency 0b11000110..mclk frequency = 1/199 * hmclk frequency 0b11000111..mclk frequency = 1/200 * hmclk frequency 0b11001000..mclk frequency = 1/201 * hmclk frequency 0b11001001..mclk frequency = 1/202 * hmclk frequency 0b11001010..mclk frequency = 1/203 * hmclk frequency 0b11001011..mclk frequency = 1/204 * hmclk frequency 0b11001100..mclk frequency = 1/205 * hmclk frequency 0b11001101..mclk frequency = 1/206 * hmclk frequency 0b11001110..mclk frequency = 1/207 * hmclk frequency 0b11001111..mclk frequency = 1/208 * hmclk frequency 0b11010000..mclk frequency = 1/209 * hmclk frequency 0b11010001..mclk frequency = 1/210 * hmclk frequency 0b11010010..mclk frequency = 1/211 * hmclk frequency 0b11010011..mclk frequency = 1/212 * hmclk frequency 0b11010100..mclk frequency = 1/213 * hmclk frequency 0b11010101..mclk frequency = 1/214 * hmclk frequency 0b11010110..mclk frequency = 1/215 * hmclk frequency 0b11010111..mclk frequency = 1/216 * hmclk frequency 0b11011000..mclk frequency = 1/217 * hmclk frequency 0b11011001..mclk frequency = 1/218 * hmclk frequency 0b11011010..mclk frequency = 1/219 * hmclk frequency 0b11011011..mclk frequency = 1/220 * hmclk frequency 0b11011100..mclk frequency = 1/221 * hmclk frequency 0b11011101..mclk frequency = 1/222 * hmclk frequency 0b11011110..mclk frequency = 1/223 * hmclk frequency 0b11011111..mclk frequency = 1/224 * hmclk frequency 0b11100000..mclk frequency = 1/225 * hmclk frequency 0b11100001..mclk frequency = 1/226 * hmclk frequency 0b11100010..mclk frequency = 1/227 * hmclk frequency 0b11100011..mclk frequency = 1/228 * hmclk frequency 0b11100100..mclk frequency = 1/229 * hmclk frequency 0b11100101..mclk frequency = 1/230 * hmclk frequency 0b11100110..mclk frequency = 1/231 * hmclk frequency 0b11100111..mclk frequency = 1/232 * hmclk frequency 0b11101000..mclk frequency = 1/233 * hmclk frequency 0b11101001..mclk frequency = 1/234 * hmclk frequency 0b11101010..mclk frequency = 1/235 * hmclk frequency 0b11101011..mclk frequency = 1/236 * hmclk frequency 0b11101100..mclk frequency = 1/237 * hmclk frequency 0b11101101..mclk frequency = 1/238 * hmclk frequency 0b11101110..mclk frequency = 1/239 * hmclk frequency 0b11101111..mclk frequency = 1/240 * hmclk frequency 0b11110000..mclk frequency = 1/241 * hmclk frequency 0b11110001..mclk frequency = 1/242 * hmclk frequency 0b11110010..mclk frequency = 1/243 * hmclk frequency 0b11110011..mclk frequency = 1/244 * hmclk frequency 0b11110100..mclk frequency = 1/245 * hmclk frequency 0b11110101..mclk frequency = 1/246 * hmclk frequency 0b11110110..mclk frequency = 1/247 * hmclk frequency 0b11110111..mclk frequency = 1/248 * hmclk frequency 0b11111000..mclk frequency = 1/249 * hmclk frequency 0b11111001..mclk frequency = 1/250 * hmclk frequency 0b11111010..mclk frequency = 1/251 * hmclk frequency 0b11111011..mclk frequency = 1/252 * hmclk frequency 0b11111100..mclk frequency = 1/253 * hmclk frequency 0b11111101..mclk frequency = 1/254 * hmclk frequency 0b11111110..mclk frequency = 1/255 * hmclk frequency 0b11111111..mclk frequency = 1/256 * hmclk frequency

Definition at line 22710 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK

#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)

Definition at line 22450 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT

#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)

Definition at line 22451 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_EN

#define IOMUXC_GPR_GPR2_MQS_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)

MQS_EN 0b0..Disable MQS 0b1..Enable MQS

Definition at line 22724 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_EN_MASK

#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)

Definition at line 22718 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_EN_SHIFT

#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)

Definition at line 22719 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_OVERSAMPLE

#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)

MQS_OVERSAMPLE 0b0..32 0b1..64

Definition at line 22731 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK

#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)

Definition at line 22725 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT

#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)

Definition at line 22726 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_SW_RST

#define IOMUXC_GPR_GPR2_MQS_SW_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)

MQS_SW_RST 0b0..Exit software reset for MQS 0b1..Enable software reset for MQS

Definition at line 22717 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_SW_RST_MASK

#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)

Definition at line 22711 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT

#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)

Definition at line 22712 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)

QTIMER1_TMR_CNTS_FREEZE 0b0..timer counter work normally 0b1..reset counter and ouput flags

Definition at line 22738 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK

#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)

Definition at line 22732 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT

#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)

Definition at line 22733 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)

QTIMER2_TMR_CNTS_FREEZE 0b0..timer counter work normally 0b1..reset counter and ouput flags

Definition at line 22745 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK

#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)

Definition at line 22739 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT

#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)

Definition at line 22740 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)

QTIMER3_TMR_CNTS_FREEZE 0b0..timer counter work normally 0b1..reset counter and ouput flags

Definition at line 22752 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK

#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)

Definition at line 22746 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT

#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)

Definition at line 22747 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)

QTIMER4_TMR_CNTS_FREEZE 0b0..timer counter work normally 0b1..reset counter and ouput flags

Definition at line 22759 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK

#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)

Definition at line 22753 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT

#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)

Definition at line 22754 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN

#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK)

RAM_AUTO_CLK_GATING_EN 0b0..disable automatically gate off RAM clock 0b1..enable automatically gate off RAM clock

Definition at line 22442 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK

#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U)

Definition at line 22436 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT

#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U)

Definition at line 22437 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START

#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT)) & IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK)

Definition at line 24300 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK

#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK (0xFFFFF000U)

Definition at line 24298 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT

#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT (12U)

Definition at line 24299 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END

#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT)) & IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK)

Definition at line 24307 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK

#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK (0xFFFFF000U)

Definition at line 24305 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT

#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT (12U)

Definition at line 24306 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET

#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT)) & IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK)

Definition at line 24314 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK

#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK (0xFFFFF000U)

Definition at line 24312 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT

#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT (12U)

Definition at line 24313 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR

#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK)

LOCK_OCRAM2_TZ_ADDR 0b0000000..Field is not locked 0b0000001..Field is locked (read access only)

Definition at line 24343 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK

#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK (0xFE0000U)

Definition at line 24337 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT

#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT (17U)

Definition at line 24338 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN

#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK)

LOCK_OCRAM2_TZ_EN 0b0..Field is not locked 0b1..Field is locked (read access only)

Definition at line 24336 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK

#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK (0x10000U)

Definition at line 24330 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT

#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT (16U)

Definition at line 24331 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR

#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK)

Definition at line 24329 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK

#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK (0xFEU)

Definition at line 24327 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT

#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT (1U)

Definition at line 24328 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_OCRAM2_TZ_EN

#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK)

OCRAM2_TZ_EN 0b0..The TrustZone feature is disabled. Entire OCRAM2 space is available for all access types (secure/non-secure/user/supervisor). 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.

Definition at line 24326 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK

#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK (0x1U)

Definition at line 24319 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT

#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT (0U)

Definition at line 24320 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL

#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK)

SIP_TEST_MUX_BOOT_PIN_SEL - Boot Pin select in SIP_TEST_MUX

Definition at line 24352 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK

#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK (0xFFU)

Definition at line 24348 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT

#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT (0U)

Definition at line 24349 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN

#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK)

SIP_TEST_MUX_QSPI_SIP_EN 0b0..SIP_TEST_MUX is disabled 0b1..SIP_TEST_MUX is enabled

Definition at line 24359 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK

#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK (0x100U)

Definition at line 24353 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT

#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT (8U)

Definition at line 24354 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ

#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK)

AXBS_L_HALT_REQ 0b0..axbs_l normal run 0b1..request to halt axbs_l

Definition at line 22783 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK

#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK (0x8000U)

Definition at line 22777 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT

#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT (15U)

Definition at line 22778 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_AXBS_L_HALTED

#define IOMUXC_GPR_GPR3_AXBS_L_HALTED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK)

AXBS_L_HALTED 0b0..axbs_l is not halted 0b1..axbs_l is in halted status

Definition at line 22796 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK

#define IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK (0x80000000U)

Definition at line 22790 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT

#define IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT (31U)

Definition at line 22791 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_DCP_KEY_SEL

#define IOMUXC_GPR_GPR3_DCP_KEY_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)

DCP_KEY_SEL 0b0..Select [127:0] from snvs/ocotp key as dcp key 0b1..Select [255:128] from snvs/ocotp key as dcp key

Definition at line 22773 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK

#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)

Definition at line 22767 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT

#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)

Definition at line 22768 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM2_CTL

#define IOMUXC_GPR_GPR3_OCRAM2_CTL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK)

Definition at line 22776 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK

#define IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK (0xF00U)

Definition at line 22774 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT

#define IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT (8U)

Definition at line 22775 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM2_STATUS

#define IOMUXC_GPR_GPR3_OCRAM2_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK)

Definition at line 22789 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK

#define IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK (0xF000000U)

Definition at line 22787 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT

#define IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT (24U)

Definition at line 22788 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM_CTL

#define IOMUXC_GPR_GPR3_OCRAM_CTL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)

Definition at line 22766 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM_CTL_MASK

#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)

Definition at line 22764 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT

#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)

Definition at line 22765 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM_STATUS

#define IOMUXC_GPR_GPR3_OCRAM_STATUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)

Definition at line 22786 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK

#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)

Definition at line 22784 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT

#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)

Definition at line 22785 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN1_STOP_ACK

#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)

CAN1_STOP_ACK 0b0..CAN1 stop acknowledge is not asserted 0b1..CAN1 stop acknowledge is asserted

Definition at line 22926 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)

Definition at line 22920 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)

Definition at line 22921 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN1_STOP_REQ

#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)

CAN1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22814 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)

Definition at line 22808 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)

Definition at line 22809 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN2_STOP_ACK

#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)

CAN2_STOP_ACK 0b0..CAN2 stop acknowledge is not asserted 0b1..CAN2 stop acknowledge is asserted

Definition at line 22933 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)

Definition at line 22927 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)

Definition at line 22928 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN2_STOP_REQ

#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)

CAN2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22821 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)

Definition at line 22815 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)

Definition at line 22816 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_EDMA_STOP_ACK

#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)

EDMA_STOP_ACK 0b0..EDMA stop acknowledge is not asserted 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode).

Definition at line 22919 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)

Definition at line 22913 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)

Definition at line 22914 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_EDMA_STOP_REQ

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)

EDMA_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22807 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)

Definition at line 22801 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)

Definition at line 22802 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET2_STOP_ACK

#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK)

ENET2_STOP_ACK 0b0..ENET2 stop acknowledge is not asserted 0b1..ENET2 stop acknowledge is asserted

Definition at line 22975 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x1000000U)

Definition at line 22969 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (24U)

Definition at line 22970 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET2_STOP_REQ

#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK)

ENET2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22863 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x100U)

Definition at line 22857 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (8U)

Definition at line 22858 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET_STOP_ACK

#define IOMUXC_GPR_GPR4_ENET_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)

ENET_STOP_ACK 0b0..ENET1 stop acknowledge is not asserted 0b1..ENET1 stop acknowledge is asserted

Definition at line 22947 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)

Definition at line 22941 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)

Definition at line 22942 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET_STOP_REQ

#define IOMUXC_GPR_GPR4_ENET_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)

ENET_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22835 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)

Definition at line 22829 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)

Definition at line 22830 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)

FLEXIO1_STOP_ACK 0b0..FLEXIO1 stop acknowledge is not asserted 0b1..FLEXIO1 stop acknowledge is asserted

Definition at line 23003 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)

Definition at line 22997 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)

Definition at line 22998 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)

FLEXIO1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22891 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)

Definition at line 22885 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)

Definition at line 22886 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)

FLEXIO2_STOP_ACK 0b0..FLEXIO2 stop acknowledge is not asserted 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode)

Definition at line 23010 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)

Definition at line 23004 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)

Definition at line 23005 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)

FLEXIO2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22898 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)

Definition at line 22892 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)

Definition at line 22893 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK)

FLEXIO3_STOP_ACK 0b0..FLEXIO3 stop acknowledge is not asserted 0b1..FLEXIO3 stop acknowledge is asserted

Definition at line 23017 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK (0x40000000U)

Definition at line 23011 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT (30U)

Definition at line 23012 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK)

FLEXIO3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22905 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK (0x4000U)

Definition at line 22899 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT (14U)

Definition at line 22900 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK)

FLEXSPI2_STOP_ACK 0b0..FLEXSPI2 stop acknowledge is not asserted 0b1..FLEXSPI2 stop acknowledge is asserted

Definition at line 23024 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK (0x80000000U)

Definition at line 23018 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT (31U)

Definition at line 23019 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK)

FLEXSPI2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22912 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK (0x8000U)

Definition at line 22906 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT (15U)

Definition at line 22907 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)

FLEXSPI_STOP_ACK 0b0..FLEXSPI stop acknowledge is not asserted 0b1..FLEXSPI stop acknowledge is asserted

Definition at line 22996 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)

Definition at line 22990 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)

Definition at line 22991 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)

FLEXSPI_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22884 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)

Definition at line 22878 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)

Definition at line 22879 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_PIT_STOP_ACK

#define IOMUXC_GPR_GPR4_PIT_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)

PIT_STOP_ACK 0b0..PIT stop acknowledge is not asserted 0b1..PIT stop acknowledge is asserted

Definition at line 22989 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)

Definition at line 22983 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)

Definition at line 22984 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_PIT_STOP_REQ

#define IOMUXC_GPR_GPR4_PIT_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)

PIT_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22877 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)

Definition at line 22871 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)

Definition at line 22872 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI1_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)

SAI1_STOP_ACK 0b0..SAI1 stop acknowledge is not asserted 0b1..SAI1 stop acknowledge is asserted

Definition at line 22954 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)

Definition at line 22948 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)

Definition at line 22949 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI1_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)

SAI1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22842 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)

Definition at line 22836 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)

Definition at line 22837 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI2_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)

SAI2_STOP_ACK 0b0..SAI2 stop acknowledge is not asserted 0b1..SAI2 stop acknowledge is asserted

Definition at line 22961 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)

Definition at line 22955 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)

Definition at line 22956 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI2_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)

SAI2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22849 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)

Definition at line 22843 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)

Definition at line 22844 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI3_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)

SAI3_STOP_ACK 0b0..SAI3 stop acknowledge is not asserted 0b1..SAI3 stop acknowledge is asserted

Definition at line 22968 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)

Definition at line 22962 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)

Definition at line 22963 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI3_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)

SAI3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22856 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)

Definition at line 22850 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)

Definition at line 22851 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SEMC_STOP_ACK

#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)

SEMC_STOP_ACK 0b0..SEMC stop acknowledge is not asserted 0b1..SEMC stop acknowledge is asserted

Definition at line 22982 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)

Definition at line 22976 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)

Definition at line 22977 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SEMC_STOP_REQ

#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)

SEMC_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22870 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)

Definition at line 22864 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)

Definition at line 22865 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_TRNG_STOP_ACK

#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)

TRNG_STOP_ACK 0b0..TRNG stop acknowledge is not asserted 0b1..TRNG stop acknowledge is asserted

Definition at line 22940 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK

#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)

Definition at line 22934 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)

Definition at line 22935 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_TRNG_STOP_REQ

#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)

TRNG_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 22828 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK

#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)

Definition at line 22822 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)

Definition at line 22823 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL

#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK)

ENET2_EVENT3IN_SEL 0b0..event3 source input from ENET2_1588_EVENT3_IN 0b1..event3 source input from GPT2.GPT_COMPARE2

Definition at line 23070 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK

#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U)

Definition at line 23064 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT

#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U)

Definition at line 23065 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL

#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)

ENET_EVENT3IN_SEL 0b0..event3 source input from ENET_1588_EVENT3_IN 0b1..event3 source input from GPT2.GPT_COMPARE1

Definition at line 23063 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK

#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)

Definition at line 23057 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT

#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)

Definition at line 23058 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL

#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)

GPT2_CAPIN1_SEL 0b0..source from GPT2_CAPTURE1 0b1..source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)

Definition at line 23049 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK

#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)

Definition at line 23043 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT

#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)

Definition at line 23044 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL

#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK)

GPT2_CAPIN2_SEL 0b0..source from GPT2_CAPTURE2 0b1..source from ENET2_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)

Definition at line 23056 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK

#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U)

Definition at line 23050 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT

#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U)

Definition at line 23051 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)

VREF_1M_CLK_GPT1 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock

Definition at line 23077 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)

Definition at line 23071 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)

Definition at line 23072 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)

VREF_1M_CLK_GPT2 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock

Definition at line 23084 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)

Definition at line 23078 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)

Definition at line 23079 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_WDOG1_MASK

#define IOMUXC_GPR_GPR5_WDOG1_MASK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)

WDOG1_MASK 0b0..WDOG1 Timeout behaves normally 0b1..WDOG1 Timeout is masked

Definition at line 23035 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_WDOG1_MASK_MASK

#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)

Definition at line 23029 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT

#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)

Definition at line 23030 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_WDOG2_MASK

#define IOMUXC_GPR_GPR5_WDOG2_MASK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)

WDOG2_MASK 0b0..WDOG2 Timeout behaves normally 0b1..WDOG2 Timeout is masked

Definition at line 23042 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_WDOG2_MASK_MASK

#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)

Definition at line 23036 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT

#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)

Definition at line 23037 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)

IOMUXC_XBAR_DIR_SEL_10 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23249 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)

Definition at line 23243 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)

Definition at line 23244 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)

IOMUXC_XBAR_DIR_SEL_11 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23256 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)

Definition at line 23250 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)

Definition at line 23251 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)

IOMUXC_XBAR_DIR_SEL_12 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23263 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)

Definition at line 23257 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)

Definition at line 23258 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)

IOMUXC_XBAR_DIR_SEL_13 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23270 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)

Definition at line 23264 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)

Definition at line 23265 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)

IOMUXC_XBAR_DIR_SEL_14 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23277 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)

Definition at line 23271 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)

Definition at line 23272 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)

IOMUXC_XBAR_DIR_SEL_15 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23284 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)

Definition at line 23278 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)

Definition at line 23279 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)

IOMUXC_XBAR_DIR_SEL_16 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23291 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)

Definition at line 23285 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)

Definition at line 23286 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)

IOMUXC_XBAR_DIR_SEL_17 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23298 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)

Definition at line 23292 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)

Definition at line 23293 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)

IOMUXC_XBAR_DIR_SEL_18 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23305 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)

Definition at line 23299 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)

Definition at line 23300 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)

IOMUXC_XBAR_DIR_SEL_19 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23312 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)

Definition at line 23306 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)

Definition at line 23307 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)

IOMUXC_XBAR_DIR_SEL_4 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23207 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)

Definition at line 23201 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)

Definition at line 23202 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)

IOMUXC_XBAR_DIR_SEL_5 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23214 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)

Definition at line 23208 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)

Definition at line 23209 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)

IOMUXC_XBAR_DIR_SEL_6 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23221 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)

Definition at line 23215 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)

Definition at line 23216 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)

IOMUXC_XBAR_DIR_SEL_7 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23228 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)

Definition at line 23222 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)

Definition at line 23223 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)

IOMUXC_XBAR_DIR_SEL_8 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23235 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)

Definition at line 23229 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)

Definition at line 23230 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)

IOMUXC_XBAR_DIR_SEL_9 0b0..XBAR_INOUT as input 0b1..XBAR_INOUT as output

Definition at line 23242 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)

Definition at line 23236 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)

Definition at line 23237 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)

QTIMER1_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23095 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)

Definition at line 23089 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)

Definition at line 23090 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)

QTIMER1_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23102 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)

Definition at line 23096 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)

Definition at line 23097 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)

QTIMER1_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23109 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)

Definition at line 23103 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)

Definition at line 23104 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)

QTIMER1_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23116 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)

Definition at line 23110 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)

Definition at line 23111 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)

QTIMER2_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23123 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)

Definition at line 23117 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)

Definition at line 23118 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)

QTIMER2_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23130 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)

Definition at line 23124 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)

Definition at line 23125 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)

QTIMER2_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23137 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)

Definition at line 23131 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)

Definition at line 23132 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)

QTIMER2_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23144 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)

Definition at line 23138 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)

Definition at line 23139 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)

QTIMER3_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23151 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)

Definition at line 23145 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)

Definition at line 23146 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)

QTIMER3_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23158 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)

Definition at line 23152 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)

Definition at line 23153 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)

QTIMER3_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23165 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)

Definition at line 23159 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)

Definition at line 23160 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)

QTIMER3_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23172 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)

Definition at line 23166 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)

Definition at line 23167 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)

QTIMER4_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23179 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)

Definition at line 23173 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)

Definition at line 23174 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)

QTIMER4_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23186 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)

Definition at line 23180 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)

Definition at line 23181 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)

QTIMER4_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23193 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)

Definition at line 23187 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)

Definition at line 23188 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)

QTIMER4_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

Definition at line 23200 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK

#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)

Definition at line 23194 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT

#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)

Definition at line 23195 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)

LPI2C1_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted (the module is in Stop mode)

Definition at line 23435 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)

Definition at line 23429 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)

Definition at line 23430 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)

LPI2C1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23323 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)

Definition at line 23317 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)

Definition at line 23318 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)

LPI2C2_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23442 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)

Definition at line 23436 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)

Definition at line 23437 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)

LPI2C2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23330 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)

Definition at line 23324 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)

Definition at line 23325 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)

LPI2C3_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23449 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)

Definition at line 23443 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)

Definition at line 23444 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)

LPI2C3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23337 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)

Definition at line 23331 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)

Definition at line 23332 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)

LPI2C4_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23456 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)

Definition at line 23450 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)

Definition at line 23451 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)

LPI2C4_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23344 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)

Definition at line 23338 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)

Definition at line 23339 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)

LPSPI1_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23463 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)

Definition at line 23457 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)

Definition at line 23458 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)

LPSPI1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23351 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)

Definition at line 23345 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)

Definition at line 23346 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)

LPSPI2_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23470 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)

Definition at line 23464 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)

Definition at line 23465 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)

LPSPI2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23358 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)

Definition at line 23352 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)

Definition at line 23353 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)

LPSPI3_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23477 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)

Definition at line 23471 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)

Definition at line 23472 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)

LPSPI3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23365 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)

Definition at line 23359 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)

Definition at line 23360 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)

LPSPI4_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23484 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)

Definition at line 23478 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)

Definition at line 23479 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)

LPSPI4_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23372 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)

Definition at line 23366 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)

Definition at line 23367 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)

LPUART1_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23491 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)

Definition at line 23485 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)

Definition at line 23486 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)

LPUART1_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23379 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)

Definition at line 23373 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)

Definition at line 23374 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)

LPUART2_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23498 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)

Definition at line 23492 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)

Definition at line 23493 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)

LPUART2_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23386 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)

Definition at line 23380 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)

Definition at line 23381 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)

LPUART3_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23505 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)

Definition at line 23499 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)

Definition at line 23500 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)

LPUART3_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23393 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)

Definition at line 23387 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)

Definition at line 23388 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)

LPUART4_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23512 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)

Definition at line 23506 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)

Definition at line 23507 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)

LPUART4_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23400 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)

Definition at line 23394 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)

Definition at line 23395 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART5_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)

LPUART5_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23519 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)

Definition at line 23513 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)

Definition at line 23514 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART5_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)

LPUART5_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23407 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)

Definition at line 23401 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)

Definition at line 23402 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART6_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)

LPUART6_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23526 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)

Definition at line 23520 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)

Definition at line 23521 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART6_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)

LPUART6_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23414 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)

Definition at line 23408 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)

Definition at line 23409 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART7_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)

LPUART7_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

Definition at line 23533 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)

Definition at line 23527 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)

Definition at line 23528 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART7_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)

LPUART7_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23421 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)

Definition at line 23415 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)

Definition at line 23416 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART8_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)

LPUART8_STOP_ACK 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted (the module is in Stop mode)

Definition at line 23540 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK

#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)

Definition at line 23534 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT

#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)

Definition at line 23535 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART8_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)

LPUART8_STOP_REQ 0b0..stop request off 0b1..stop request on

Definition at line 23428 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK

#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)

Definition at line 23422 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT

#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)

Definition at line 23423 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)

LPI2C1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23558 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)

Definition at line 23552 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)

Definition at line 23553 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)

LPI2C1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23551 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)

Definition at line 23545 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)

Definition at line 23546 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)

LPI2C2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23572 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)

Definition at line 23566 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)

Definition at line 23567 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)

LPI2C2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23565 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)

Definition at line 23559 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)

Definition at line 23560 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)

LPI2C3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23586 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)

Definition at line 23580 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)

Definition at line 23581 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)

LPI2C3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23579 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)

Definition at line 23573 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)

Definition at line 23574 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)

LPI2C4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23600 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)

Definition at line 23594 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)

Definition at line 23595 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)

LPI2C4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23593 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)

Definition at line 23587 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)

Definition at line 23588 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)

LPSPI1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23614 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)

Definition at line 23608 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)

Definition at line 23609 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)

LPSPI1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23607 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)

Definition at line 23601 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)

Definition at line 23602 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)

LPSPI2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23628 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)

Definition at line 23622 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)

Definition at line 23623 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)

LPSPI2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23621 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)

Definition at line 23615 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)

Definition at line 23616 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)

LPSPI3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23642 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)

Definition at line 23636 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)

Definition at line 23637 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)

LPSPI3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23635 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)

Definition at line 23629 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)

Definition at line 23630 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)

LPSPI4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23656 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)

Definition at line 23650 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)

Definition at line 23651 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)

LPSPI4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23649 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)

Definition at line 23643 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)

Definition at line 23644 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)

LPUART1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23670 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)

Definition at line 23664 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)

Definition at line 23665 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)

LPUART1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23663 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)

Definition at line 23657 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)

Definition at line 23658 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)

LPUART2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23684 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)

Definition at line 23678 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)

Definition at line 23679 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)

LPUART2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23677 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)

Definition at line 23671 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)

Definition at line 23672 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)

LPUART3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23698 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)

Definition at line 23692 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)

Definition at line 23693 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)

LPUART3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23691 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)

Definition at line 23685 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)

Definition at line 23686 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)

LPUART4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23712 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)

Definition at line 23706 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)

Definition at line 23707 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)

LPUART4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23705 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)

Definition at line 23699 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)

Definition at line 23700 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)

LPUART5_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23726 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)

Definition at line 23720 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)

Definition at line 23721 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)

LPUART5_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23719 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)

Definition at line 23713 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)

Definition at line 23714 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)

LPUART6_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23740 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)

Definition at line 23734 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)

Definition at line 23735 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)

LPUART6_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23733 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)

Definition at line 23727 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)

Definition at line 23728 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)

LPUART7_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23754 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)

Definition at line 23748 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)

Definition at line 23749 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)

LPUART7_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23747 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)

Definition at line 23741 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)

Definition at line 23742 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)

LPUART8_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

Definition at line 23768 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK

#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)

Definition at line 23762 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)

Definition at line 23763 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)

LPUART8_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

Definition at line 23761 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK

#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)

Definition at line 23755 of file MIMXRT1062.h.

## ◆ IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT

#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)

Definition at line 23756 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL

#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)

Definition at line 24932 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)

Definition at line 24930 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)

Definition at line 24931 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)

Definition at line 24935 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)

Definition at line 24933 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)

Definition at line 24934 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)

Definition at line 24938 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)

Definition at line 24936 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)

Definition at line 24937 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)

DCDC_STATUS_CAPT_CLR - DCDC captured status clear

Definition at line 24926 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)

Definition at line 24922 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)

Definition at line 24923 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)

Definition at line 24941 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)

Definition at line 24939 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)

Definition at line 24940 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE

#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)

Definition at line 24921 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK

#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)

Definition at line 24919 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)

Definition at line 24920 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE

#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)

Definition at line 24929 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK

#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)

Definition at line 24927 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT

#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)

Definition at line 24928 of file MIMXRT1062.h.