Callisto4Bootloader: Globals

Callisto4Bootloader

### - t -

- TABLE_SPACING_Q15 : arm_math.h
- TABLE_SPACING_Q31 : arm_math.h
- TEMPMON : MIMXRT1062.h
- TEMPMON_BASE : MIMXRT1062.h
- TEMPMON_BASE_ADDRS : MIMXRT1062.h
- TEMPMON_BASE_PTRS : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_FINISHED : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_POWER_DOWN : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_TEMP_CNT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_FINISHED : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_FINISHED_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_FINISHED_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_MEASURE_TEMP : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_POWER_DOWN : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_POWER_DOWN_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_FINISHED : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_FINISHED_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_POWER_DOWN : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_TEMP_CNT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TEMP_CNT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TEMP_CNT_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_FINISHED : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_POWER_DOWN : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_TEMP_CNT : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_MEASURE_FREQ : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK : MIMXRT1062.h
- TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT : MIMXRT1062.h
- TEST_IF : watchdog_test.c
- TESTCASE : excep_test_configuration.h
- TMR1 : MIMXRT1062.h
- TMR1_BASE : MIMXRT1062.h
- TMR2 : MIMXRT1062.h
- TMR2_BASE : MIMXRT1062.h
- TMR3 : MIMXRT1062.h
- TMR3_BASE : MIMXRT1062.h
- TMR4 : MIMXRT1062.h
- TMR4_BASE : MIMXRT1062.h
- TMR_BASE_ADDRS : MIMXRT1062.h
- TMR_BASE_PTRS : MIMXRT1062.h
- TMR_CAPT_CAPTURE : MIMXRT1062.h
- TMR_CAPT_CAPTURE_MASK : MIMXRT1062.h
- TMR_CAPT_CAPTURE_SHIFT : MIMXRT1062.h
- TMR_CAPT_COUNT : MIMXRT1062.h
- TMR_CMPLD1_COMPARATOR_LOAD_1 : MIMXRT1062.h
- TMR_CMPLD1_COMPARATOR_LOAD_1_MASK : MIMXRT1062.h
- TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT : MIMXRT1062.h
- TMR_CMPLD1_COUNT : MIMXRT1062.h
- TMR_CMPLD2_COMPARATOR_LOAD_2 : MIMXRT1062.h
- TMR_CMPLD2_COMPARATOR_LOAD_2_MASK : MIMXRT1062.h
- TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT : MIMXRT1062.h
- TMR_CMPLD2_COUNT : MIMXRT1062.h
- TMR_CNTR_COUNT : MIMXRT1062.h
- TMR_CNTR_COUNTER : MIMXRT1062.h
- TMR_CNTR_COUNTER_MASK : MIMXRT1062.h
- TMR_CNTR_COUNTER_SHIFT : MIMXRT1062.h
- TMR_COMP1_COMPARISON_1 : MIMXRT1062.h
- TMR_COMP1_COMPARISON_1_MASK : MIMXRT1062.h
- TMR_COMP1_COMPARISON_1_SHIFT : MIMXRT1062.h
- TMR_COMP1_COUNT : MIMXRT1062.h
- TMR_COMP2_COMPARISON_2 : MIMXRT1062.h
- TMR_COMP2_COMPARISON_2_MASK : MIMXRT1062.h
- TMR_COMP2_COMPARISON_2_SHIFT : MIMXRT1062.h
- TMR_COMP2_COUNT : MIMXRT1062.h
- TMR_CSCTRL_ALT_LOAD : MIMXRT1062.h
- TMR_CSCTRL_ALT_LOAD_MASK : MIMXRT1062.h
- TMR_CSCTRL_ALT_LOAD_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_CL1 : MIMXRT1062.h
- TMR_CSCTRL_CL1_MASK : MIMXRT1062.h
- TMR_CSCTRL_CL1_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_CL2 : MIMXRT1062.h
- TMR_CSCTRL_CL2_MASK : MIMXRT1062.h
- TMR_CSCTRL_CL2_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_COUNT : MIMXRT1062.h
- TMR_CSCTRL_DBG_EN : MIMXRT1062.h
- TMR_CSCTRL_DBG_EN_MASK : MIMXRT1062.h
- TMR_CSCTRL_DBG_EN_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_FAULT : MIMXRT1062.h
- TMR_CSCTRL_FAULT_MASK : MIMXRT1062.h
- TMR_CSCTRL_FAULT_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_ROC : MIMXRT1062.h
- TMR_CSCTRL_ROC_MASK : MIMXRT1062.h
- TMR_CSCTRL_ROC_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_TCF1 : MIMXRT1062.h
- TMR_CSCTRL_TCF1_MASK : MIMXRT1062.h
- TMR_CSCTRL_TCF1_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_TCF1EN : MIMXRT1062.h
- TMR_CSCTRL_TCF1EN_MASK : MIMXRT1062.h
- TMR_CSCTRL_TCF1EN_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_TCF2 : MIMXRT1062.h
- TMR_CSCTRL_TCF2_MASK : MIMXRT1062.h
- TMR_CSCTRL_TCF2_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_TCF2EN : MIMXRT1062.h
- TMR_CSCTRL_TCF2EN_MASK : MIMXRT1062.h
- TMR_CSCTRL_TCF2EN_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_TCI : MIMXRT1062.h
- TMR_CSCTRL_TCI_MASK : MIMXRT1062.h
- TMR_CSCTRL_TCI_SHIFT : MIMXRT1062.h
- TMR_CSCTRL_UP : MIMXRT1062.h
- TMR_CSCTRL_UP_MASK : MIMXRT1062.h
- TMR_CSCTRL_UP_SHIFT : MIMXRT1062.h
- TMR_CTRL_CM : MIMXRT1062.h
- TMR_CTRL_CM_MASK : MIMXRT1062.h
- TMR_CTRL_CM_SHIFT : MIMXRT1062.h
- TMR_CTRL_COINIT : MIMXRT1062.h
- TMR_CTRL_COINIT_MASK : MIMXRT1062.h
- TMR_CTRL_COINIT_SHIFT : MIMXRT1062.h
- TMR_CTRL_COUNT : MIMXRT1062.h
- TMR_CTRL_DIR : MIMXRT1062.h
- TMR_CTRL_DIR_MASK : MIMXRT1062.h
- TMR_CTRL_DIR_SHIFT : MIMXRT1062.h
- TMR_CTRL_LENGTH : MIMXRT1062.h
- TMR_CTRL_LENGTH_MASK : MIMXRT1062.h
- TMR_CTRL_LENGTH_SHIFT : MIMXRT1062.h
- TMR_CTRL_ONCE : MIMXRT1062.h
- TMR_CTRL_ONCE_MASK : MIMXRT1062.h
- TMR_CTRL_ONCE_SHIFT : MIMXRT1062.h
- TMR_CTRL_OUTMODE : MIMXRT1062.h
- TMR_CTRL_OUTMODE_MASK : MIMXRT1062.h
- TMR_CTRL_OUTMODE_SHIFT : MIMXRT1062.h
- TMR_CTRL_PCS : MIMXRT1062.h
- TMR_CTRL_PCS_MASK : MIMXRT1062.h
- TMR_CTRL_PCS_SHIFT : MIMXRT1062.h
- TMR_CTRL_SCS : MIMXRT1062.h
- TMR_CTRL_SCS_MASK : MIMXRT1062.h
- TMR_CTRL_SCS_SHIFT : MIMXRT1062.h
- TMR_DMA_CMPLD1DE : MIMXRT1062.h
- TMR_DMA_CMPLD1DE_MASK : MIMXRT1062.h
- TMR_DMA_CMPLD1DE_SHIFT : MIMXRT1062.h
- TMR_DMA_CMPLD2DE : MIMXRT1062.h
- TMR_DMA_CMPLD2DE_MASK : MIMXRT1062.h
- TMR_DMA_CMPLD2DE_SHIFT : MIMXRT1062.h
- TMR_DMA_COUNT : MIMXRT1062.h
- TMR_DMA_IEFDE : MIMXRT1062.h
- TMR_DMA_IEFDE_MASK : MIMXRT1062.h
- TMR_DMA_IEFDE_SHIFT : MIMXRT1062.h
- TMR_ENBL_COUNT : MIMXRT1062.h
- TMR_ENBL_ENBL : MIMXRT1062.h
- TMR_ENBL_ENBL_MASK : MIMXRT1062.h
- TMR_ENBL_ENBL_SHIFT : MIMXRT1062.h
- TMR_FILT_COUNT : MIMXRT1062.h
- TMR_FILT_FILT_CNT : MIMXRT1062.h
- TMR_FILT_FILT_CNT_MASK : MIMXRT1062.h
- TMR_FILT_FILT_CNT_SHIFT : MIMXRT1062.h
- TMR_FILT_FILT_PER : MIMXRT1062.h
- TMR_FILT_FILT_PER_MASK : MIMXRT1062.h
- TMR_FILT_FILT_PER_SHIFT : MIMXRT1062.h
- TMR_HOLD_COUNT : MIMXRT1062.h
- TMR_HOLD_HOLD : MIMXRT1062.h
- TMR_HOLD_HOLD_MASK : MIMXRT1062.h
- TMR_HOLD_HOLD_SHIFT : MIMXRT1062.h
- TMR_IRQS : MIMXRT1062.h
- TMR_LOAD_COUNT : MIMXRT1062.h
- TMR_LOAD_LOAD : MIMXRT1062.h
- TMR_LOAD_LOAD_MASK : MIMXRT1062.h
- TMR_LOAD_LOAD_SHIFT : MIMXRT1062.h
- TMR_SCTRL_CAPTURE_MODE : MIMXRT1062.h
- TMR_SCTRL_CAPTURE_MODE_MASK : MIMXRT1062.h
- TMR_SCTRL_CAPTURE_MODE_SHIFT : MIMXRT1062.h
- TMR_SCTRL_COUNT : MIMXRT1062.h
- TMR_SCTRL_EEOF : MIMXRT1062.h
- TMR_SCTRL_EEOF_MASK : MIMXRT1062.h
- TMR_SCTRL_EEOF_SHIFT : MIMXRT1062.h
- TMR_SCTRL_FORCE : MIMXRT1062.h
- TMR_SCTRL_FORCE_MASK : MIMXRT1062.h
- TMR_SCTRL_FORCE_SHIFT : MIMXRT1062.h
- TMR_SCTRL_IEF : MIMXRT1062.h
- TMR_SCTRL_IEF_MASK : MIMXRT1062.h
- TMR_SCTRL_IEF_SHIFT : MIMXRT1062.h
- TMR_SCTRL_IEFIE : MIMXRT1062.h
- TMR_SCTRL_IEFIE_MASK : MIMXRT1062.h
- TMR_SCTRL_IEFIE_SHIFT : MIMXRT1062.h
- TMR_SCTRL_INPUT : MIMXRT1062.h
- TMR_SCTRL_INPUT_MASK : MIMXRT1062.h
- TMR_SCTRL_INPUT_SHIFT : MIMXRT1062.h
- TMR_SCTRL_IPS : MIMXRT1062.h
- TMR_SCTRL_IPS_MASK : MIMXRT1062.h
- TMR_SCTRL_IPS_SHIFT : MIMXRT1062.h
- TMR_SCTRL_MSTR : MIMXRT1062.h
- TMR_SCTRL_MSTR_MASK : MIMXRT1062.h
- TMR_SCTRL_MSTR_SHIFT : MIMXRT1062.h
- TMR_SCTRL_OEN : MIMXRT1062.h
- TMR_SCTRL_OEN_MASK : MIMXRT1062.h
- TMR_SCTRL_OEN_SHIFT : MIMXRT1062.h
- TMR_SCTRL_OPS : MIMXRT1062.h
- TMR_SCTRL_OPS_MASK : MIMXRT1062.h
- TMR_SCTRL_OPS_SHIFT : MIMXRT1062.h
- TMR_SCTRL_TCF : MIMXRT1062.h
- TMR_SCTRL_TCF_MASK : MIMXRT1062.h
- TMR_SCTRL_TCF_SHIFT : MIMXRT1062.h
- TMR_SCTRL_TCFIE : MIMXRT1062.h
- TMR_SCTRL_TCFIE_MASK : MIMXRT1062.h
- TMR_SCTRL_TCFIE_SHIFT : MIMXRT1062.h
- TMR_SCTRL_TOF : MIMXRT1062.h
- TMR_SCTRL_TOF_MASK : MIMXRT1062.h
- TMR_SCTRL_TOF_SHIFT : MIMXRT1062.h
- TMR_SCTRL_TOFIE : MIMXRT1062.h
- TMR_SCTRL_TOFIE_MASK : MIMXRT1062.h
- TMR_SCTRL_TOFIE_SHIFT : MIMXRT1062.h
- TMR_SCTRL_VAL : MIMXRT1062.h
- TMR_SCTRL_VAL_MASK : MIMXRT1062.h
- TMR_SCTRL_VAL_SHIFT : MIMXRT1062.h
- TPI : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_ACPR_PRESCALER_Msk : core_armv81mml.h , core_cm7.h
- TPI_ACPR_PRESCALER_Pos : core_armv81mml.h , core_cm7.h
- TPI_ACPR_SWOSCALER_Msk : core_armv8mbl.h , core_armv8mml.h
- TPI_ACPR_SWOSCALER_Pos : core_armv8mbl.h , core_armv8mml.h
- TPI_BASE : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVID_AsynClkIn_Msk : core_armv81mml.h , core_cm7.h
- TPI_DEVID_AsynClkIn_Pos : core_armv81mml.h , core_cm7.h
- TPI_DEVID_FIFOSZ_Msk : core_armv8mbl.h , core_armv8mml.h
- TPI_DEVID_FIFOSZ_Pos : core_armv8mbl.h , core_armv8mml.h
- TPI_DEVID_MANCVALID_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVID_MANCVALID_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVID_MinBufSz_Msk : core_armv81mml.h , core_cm7.h
- TPI_DEVID_MinBufSz_Pos : core_armv81mml.h , core_cm7.h
- TPI_DEVID_NrTraceInput_Msk : core_armv81mml.h , core_cm7.h
- TPI_DEVID_NrTraceInput_Pos : core_armv81mml.h , core_cm7.h
- TPI_DEVID_NRZVALID_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVID_NRZVALID_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVID_PTINVALID_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVID_PTINVALID_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVTYPE_MajorType_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVTYPE_MajorType_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVTYPE_SubType_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_DEVTYPE_SubType_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFCR_EnFCont_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFCR_EnFCont_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFCR_FOnMan_Msk : core_armv8mbl.h , core_armv8mml.h
- TPI_FFCR_FOnMan_Pos : core_armv8mbl.h , core_armv8mml.h
- TPI_FFCR_TrigIn_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFCR_TrigIn_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFSR_FlInProg_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFSR_FlInProg_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFSR_FtNonStop_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFSR_FtNonStop_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFSR_FtStopped_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFSR_FtStopped_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFSR_TCPresent_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FFSR_TCPresent_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_FIFO0_ETM0_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM0_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM1_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM1_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM2_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM2_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM_ATVALID_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM_ATVALID_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM_bytecount_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ETM_bytecount_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ITM_ATVALID_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ITM_ATVALID_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ITM_bytecount_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO0_ITM_bytecount_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ETM_ATVALID_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ETM_ATVALID_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ETM_bytecount_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ETM_bytecount_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM0_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM0_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM1_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM1_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM2_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM2_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM_ATVALID_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM_ATVALID_Pos : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM_bytecount_Msk : core_armv81mml.h , core_cm7.h
- TPI_FIFO1_ITM_bytecount_Pos : core_armv81mml.h , core_cm7.h
- TPI_ITATBCTR0_ATREADY1_Msk : core_cm7.h
- TPI_ITATBCTR0_ATREADY1_Pos : core_cm7.h
- TPI_ITATBCTR0_ATREADY2_Msk : core_cm7.h
- TPI_ITATBCTR0_ATREADY2_Pos : core_cm7.h
- TPI_ITATBCTR0_ATREADY_Msk : core_armv81mml.h
- TPI_ITATBCTR0_ATREADY_Pos : core_armv81mml.h
- TPI_ITATBCTR2_ATREADY1_Msk : core_cm7.h
- TPI_ITATBCTR2_ATREADY1_Pos : core_cm7.h
- TPI_ITATBCTR2_ATREADY2_Msk : core_cm7.h
- TPI_ITATBCTR2_ATREADY2_Pos : core_cm7.h
- TPI_ITATBCTR2_ATREADY_Msk : core_armv81mml.h
- TPI_ITATBCTR2_ATREADY_Pos : core_armv81mml.h
- TPI_ITCTRL_Mode_Msk : core_armv81mml.h , core_cm7.h
- TPI_ITCTRL_Mode_Pos : core_armv81mml.h , core_cm7.h
- TPI_LSR_nTT_Msk : core_armv8mbl.h , core_armv8mml.h
- TPI_LSR_nTT_Pos : core_armv8mbl.h , core_armv8mml.h
- TPI_LSR_SLI_Msk : core_armv8mbl.h , core_armv8mml.h
- TPI_LSR_SLI_Pos : core_armv8mbl.h , core_armv8mml.h
- TPI_LSR_SLK_Msk : core_armv8mbl.h , core_armv8mml.h
- TPI_LSR_SLK_Pos : core_armv8mbl.h , core_armv8mml.h
- TPI_PSCR_PSCount_Msk : core_armv8mbl.h , core_armv8mml.h
- TPI_PSCR_PSCount_Pos : core_armv8mbl.h , core_armv8mml.h
- TPI_SPPR_TXMODE_Msk : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_SPPR_TXMODE_Pos : core_armv81mml.h , core_armv8mbl.h , core_armv8mml.h , core_cm7.h
- TPI_TRIGGER_TRIGGER_Msk : core_armv81mml.h , core_cm7.h
- TPI_TRIGGER_TRIGGER_Pos : core_armv81mml.h , core_cm7.h
- TRNG : MIMXRT1062.h
- TRNG_BASE : MIMXRT1062.h
- TRNG_BASE_ADDRS : MIMXRT1062.h
- TRNG_BASE_PTRS : MIMXRT1062.h
- TRNG_ENT_COUNT : MIMXRT1062.h
- TRNG_ENT_ENT : MIMXRT1062.h
- TRNG_ENT_ENT_MASK : MIMXRT1062.h
- TRNG_ENT_ENT_SHIFT : MIMXRT1062.h
- TRNG_FRQCNT_FRQ_CT : MIMXRT1062.h
- TRNG_FRQCNT_FRQ_CT_MASK : MIMXRT1062.h
- TRNG_FRQCNT_FRQ_CT_SHIFT : MIMXRT1062.h
- TRNG_FRQMAX_FRQ_MAX : MIMXRT1062.h
- TRNG_FRQMAX_FRQ_MAX_MASK : MIMXRT1062.h
- TRNG_FRQMAX_FRQ_MAX_SHIFT : MIMXRT1062.h
- TRNG_FRQMIN_FRQ_MIN : MIMXRT1062.h
- TRNG_FRQMIN_FRQ_MIN_MASK : MIMXRT1062.h
- TRNG_FRQMIN_FRQ_MIN_SHIFT : MIMXRT1062.h
- TRNG_INT_CTRL_ENT_VAL : MIMXRT1062.h
- TRNG_INT_CTRL_ENT_VAL_MASK : MIMXRT1062.h
- TRNG_INT_CTRL_ENT_VAL_SHIFT : MIMXRT1062.h
- TRNG_INT_CTRL_FRQ_CT_FAIL : MIMXRT1062.h
- TRNG_INT_CTRL_FRQ_CT_FAIL_MASK : MIMXRT1062.h
- TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT : MIMXRT1062.h
- TRNG_INT_CTRL_HW_ERR : MIMXRT1062.h
- TRNG_INT_CTRL_HW_ERR_MASK : MIMXRT1062.h
- TRNG_INT_CTRL_HW_ERR_SHIFT : MIMXRT1062.h
- TRNG_INT_CTRL_UNUSED : MIMXRT1062.h
- TRNG_INT_CTRL_UNUSED_MASK : MIMXRT1062.h
- TRNG_INT_CTRL_UNUSED_SHIFT : MIMXRT1062.h
- TRNG_INT_MASK_ENT_VAL : MIMXRT1062.h
- TRNG_INT_MASK_ENT_VAL_MASK : MIMXRT1062.h
- TRNG_INT_MASK_ENT_VAL_SHIFT : MIMXRT1062.h
- TRNG_INT_MASK_FRQ_CT_FAIL : MIMXRT1062.h
- TRNG_INT_MASK_FRQ_CT_FAIL_MASK : MIMXRT1062.h
- TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT : MIMXRT1062.h
- TRNG_INT_MASK_HW_ERR : MIMXRT1062.h
- TRNG_INT_MASK_HW_ERR_MASK : MIMXRT1062.h
- TRNG_INT_MASK_HW_ERR_SHIFT : MIMXRT1062.h
- TRNG_INT_STATUS_ENT_VAL : MIMXRT1062.h
- TRNG_INT_STATUS_ENT_VAL_MASK : MIMXRT1062.h
- TRNG_INT_STATUS_ENT_VAL_SHIFT : MIMXRT1062.h
- TRNG_INT_STATUS_FRQ_CT_FAIL : MIMXRT1062.h
- TRNG_INT_STATUS_FRQ_CT_FAIL_MASK : MIMXRT1062.h
- TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT : MIMXRT1062.h
- TRNG_INT_STATUS_HW_ERR : MIMXRT1062.h
- TRNG_INT_STATUS_HW_ERR_MASK : MIMXRT1062.h
- TRNG_INT_STATUS_HW_ERR_SHIFT : MIMXRT1062.h
- TRNG_IRQS : MIMXRT1062.h
- TRNG_MCTL_ENT_VAL : MIMXRT1062.h
- TRNG_MCTL_ENT_VAL_MASK : MIMXRT1062.h
- TRNG_MCTL_ENT_VAL_SHIFT : MIMXRT1062.h
- TRNG_MCTL_ERR : MIMXRT1062.h
- TRNG_MCTL_ERR_MASK : MIMXRT1062.h
- TRNG_MCTL_ERR_SHIFT : MIMXRT1062.h
- TRNG_MCTL_FCT_FAIL : MIMXRT1062.h
- TRNG_MCTL_FCT_FAIL_MASK : MIMXRT1062.h
- TRNG_MCTL_FCT_FAIL_SHIFT : MIMXRT1062.h
- TRNG_MCTL_FCT_VAL : MIMXRT1062.h
- TRNG_MCTL_FCT_VAL_MASK : MIMXRT1062.h
- TRNG_MCTL_FCT_VAL_SHIFT : MIMXRT1062.h
- TRNG_MCTL_FOR_SCLK : MIMXRT1062.h
- TRNG_MCTL_FOR_SCLK_MASK : MIMXRT1062.h
- TRNG_MCTL_FOR_SCLK_SHIFT : MIMXRT1062.h
- TRNG_MCTL_LRUN_CONT : MIMXRT1062.h
- TRNG_MCTL_LRUN_CONT_MASK : MIMXRT1062.h
- TRNG_MCTL_LRUN_CONT_SHIFT : MIMXRT1062.h
- TRNG_MCTL_OSC_DIV : MIMXRT1062.h
- TRNG_MCTL_OSC_DIV_MASK : MIMXRT1062.h
- TRNG_MCTL_OSC_DIV_SHIFT : MIMXRT1062.h
- TRNG_MCTL_PRGM : MIMXRT1062.h
- TRNG_MCTL_PRGM_MASK : MIMXRT1062.h
- TRNG_MCTL_PRGM_SHIFT : MIMXRT1062.h
- TRNG_MCTL_RST_DEF : MIMXRT1062.h
- TRNG_MCTL_RST_DEF_MASK : MIMXRT1062.h
- TRNG_MCTL_RST_DEF_SHIFT : MIMXRT1062.h
- TRNG_MCTL_SAMP_MODE : MIMXRT1062.h
- TRNG_MCTL_SAMP_MODE_MASK : MIMXRT1062.h
- TRNG_MCTL_SAMP_MODE_SHIFT : MIMXRT1062.h
- TRNG_MCTL_TST_OUT : MIMXRT1062.h
- TRNG_MCTL_TST_OUT_MASK : MIMXRT1062.h
- TRNG_MCTL_TST_OUT_SHIFT : MIMXRT1062.h
- TRNG_MCTL_TSTOP_OK : MIMXRT1062.h
- TRNG_MCTL_TSTOP_OK_MASK : MIMXRT1062.h
- TRNG_MCTL_TSTOP_OK_SHIFT : MIMXRT1062.h
- TRNG_MCTL_UNUSED4 : MIMXRT1062.h
- TRNG_MCTL_UNUSED4_MASK : MIMXRT1062.h
- TRNG_MCTL_UNUSED4_SHIFT : MIMXRT1062.h
- TRNG_MCTL_UNUSED5 : MIMXRT1062.h
- TRNG_MCTL_UNUSED5_MASK : MIMXRT1062.h
- TRNG_MCTL_UNUSED5_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT10_PKR_0_CT : MIMXRT1062.h
- TRNG_PKRCNT10_PKR_0_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT10_PKR_0_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT10_PKR_1_CT : MIMXRT1062.h
- TRNG_PKRCNT10_PKR_1_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT10_PKR_1_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT32_PKR_2_CT : MIMXRT1062.h
- TRNG_PKRCNT32_PKR_2_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT32_PKR_2_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT32_PKR_3_CT : MIMXRT1062.h
- TRNG_PKRCNT32_PKR_3_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT32_PKR_3_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT54_PKR_4_CT : MIMXRT1062.h
- TRNG_PKRCNT54_PKR_4_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT54_PKR_4_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT54_PKR_5_CT : MIMXRT1062.h
- TRNG_PKRCNT54_PKR_5_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT54_PKR_5_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT76_PKR_6_CT : MIMXRT1062.h
- TRNG_PKRCNT76_PKR_6_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT76_PKR_6_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT76_PKR_7_CT : MIMXRT1062.h
- TRNG_PKRCNT76_PKR_7_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT76_PKR_7_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT98_PKR_8_CT : MIMXRT1062.h
- TRNG_PKRCNT98_PKR_8_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT98_PKR_8_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNT98_PKR_9_CT : MIMXRT1062.h
- TRNG_PKRCNT98_PKR_9_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNT98_PKR_9_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNTBA_PKR_A_CT : MIMXRT1062.h
- TRNG_PKRCNTBA_PKR_A_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNTBA_PKR_A_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNTBA_PKR_B_CT : MIMXRT1062.h
- TRNG_PKRCNTBA_PKR_B_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNTBA_PKR_B_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNTDC_PKR_C_CT : MIMXRT1062.h
- TRNG_PKRCNTDC_PKR_C_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNTDC_PKR_C_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNTDC_PKR_D_CT : MIMXRT1062.h
- TRNG_PKRCNTDC_PKR_D_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNTDC_PKR_D_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNTFE_PKR_E_CT : MIMXRT1062.h
- TRNG_PKRCNTFE_PKR_E_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNTFE_PKR_E_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRCNTFE_PKR_F_CT : MIMXRT1062.h
- TRNG_PKRCNTFE_PKR_F_CT_MASK : MIMXRT1062.h
- TRNG_PKRCNTFE_PKR_F_CT_SHIFT : MIMXRT1062.h
- TRNG_PKRMAX_PKR_MAX : MIMXRT1062.h
- TRNG_PKRMAX_PKR_MAX_MASK : MIMXRT1062.h
- TRNG_PKRMAX_PKR_MAX_SHIFT : MIMXRT1062.h
- TRNG_PKRRNG_PKR_RNG : MIMXRT1062.h
- TRNG_PKRRNG_PKR_RNG_MASK : MIMXRT1062.h
- TRNG_PKRRNG_PKR_RNG_SHIFT : MIMXRT1062.h
- TRNG_PKRSQ_PKR_SQ : MIMXRT1062.h
- TRNG_PKRSQ_PKR_SQ_MASK : MIMXRT1062.h
- TRNG_PKRSQ_PKR_SQ_SHIFT : MIMXRT1062.h
- TRNG_SBLIM_SB_LIM : MIMXRT1062.h
- TRNG_SBLIM_SB_LIM_MASK : MIMXRT1062.h
- TRNG_SBLIM_SB_LIM_SHIFT : MIMXRT1062.h
- TRNG_SCMC_MONO_CT : MIMXRT1062.h
- TRNG_SCMC_MONO_CT_MASK : MIMXRT1062.h
- TRNG_SCMC_MONO_CT_SHIFT : MIMXRT1062.h
- TRNG_SCMISC_LRUN_MAX : MIMXRT1062.h
- TRNG_SCMISC_LRUN_MAX_MASK : MIMXRT1062.h
- TRNG_SCMISC_LRUN_MAX_SHIFT : MIMXRT1062.h
- TRNG_SCMISC_RTY_CT : MIMXRT1062.h
- TRNG_SCMISC_RTY_CT_MASK : MIMXRT1062.h
- TRNG_SCMISC_RTY_CT_SHIFT : MIMXRT1062.h
- TRNG_SCML_MONO_MAX : MIMXRT1062.h
- TRNG_SCML_MONO_MAX_MASK : MIMXRT1062.h
- TRNG_SCML_MONO_MAX_SHIFT : MIMXRT1062.h
- TRNG_SCML_MONO_RNG : MIMXRT1062.h
- TRNG_SCML_MONO_RNG_MASK : MIMXRT1062.h
- TRNG_SCML_MONO_RNG_SHIFT : MIMXRT1062.h
- TRNG_SCR1C_R1_0_CT : MIMXRT1062.h
- TRNG_SCR1C_R1_0_CT_MASK : MIMXRT1062.h
- TRNG_SCR1C_R1_0_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR1C_R1_1_CT : MIMXRT1062.h
- TRNG_SCR1C_R1_1_CT_MASK : MIMXRT1062.h
- TRNG_SCR1C_R1_1_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR1L_RUN1_MAX : MIMXRT1062.h
- TRNG_SCR1L_RUN1_MAX_MASK : MIMXRT1062.h
- TRNG_SCR1L_RUN1_MAX_SHIFT : MIMXRT1062.h
- TRNG_SCR1L_RUN1_RNG : MIMXRT1062.h
- TRNG_SCR1L_RUN1_RNG_MASK : MIMXRT1062.h
- TRNG_SCR1L_RUN1_RNG_SHIFT : MIMXRT1062.h
- TRNG_SCR2C_R2_0_CT : MIMXRT1062.h
- TRNG_SCR2C_R2_0_CT_MASK : MIMXRT1062.h
- TRNG_SCR2C_R2_0_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR2C_R2_1_CT : MIMXRT1062.h
- TRNG_SCR2C_R2_1_CT_MASK : MIMXRT1062.h
- TRNG_SCR2C_R2_1_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR2L_RUN2_MAX : MIMXRT1062.h
- TRNG_SCR2L_RUN2_MAX_MASK : MIMXRT1062.h
- TRNG_SCR2L_RUN2_MAX_SHIFT : MIMXRT1062.h
- TRNG_SCR2L_RUN2_RNG : MIMXRT1062.h
- TRNG_SCR2L_RUN2_RNG_MASK : MIMXRT1062.h
- TRNG_SCR2L_RUN2_RNG_SHIFT : MIMXRT1062.h
- TRNG_SCR3C_R3_0_CT : MIMXRT1062.h
- TRNG_SCR3C_R3_0_CT_MASK : MIMXRT1062.h
- TRNG_SCR3C_R3_0_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR3C_R3_1_CT : MIMXRT1062.h
- TRNG_SCR3C_R3_1_CT_MASK : MIMXRT1062.h
- TRNG_SCR3C_R3_1_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR3L_RUN3_MAX : MIMXRT1062.h
- TRNG_SCR3L_RUN3_MAX_MASK : MIMXRT1062.h
- TRNG_SCR3L_RUN3_MAX_SHIFT : MIMXRT1062.h
- TRNG_SCR3L_RUN3_RNG : MIMXRT1062.h
- TRNG_SCR3L_RUN3_RNG_MASK : MIMXRT1062.h
- TRNG_SCR3L_RUN3_RNG_SHIFT : MIMXRT1062.h
- TRNG_SCR4C_R4_0_CT : MIMXRT1062.h
- TRNG_SCR4C_R4_0_CT_MASK : MIMXRT1062.h
- TRNG_SCR4C_R4_0_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR4C_R4_1_CT : MIMXRT1062.h
- TRNG_SCR4C_R4_1_CT_MASK : MIMXRT1062.h
- TRNG_SCR4C_R4_1_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR4L_RUN4_MAX : MIMXRT1062.h
- TRNG_SCR4L_RUN4_MAX_MASK : MIMXRT1062.h
- TRNG_SCR4L_RUN4_MAX_SHIFT : MIMXRT1062.h
- TRNG_SCR4L_RUN4_RNG : MIMXRT1062.h
- TRNG_SCR4L_RUN4_RNG_MASK : MIMXRT1062.h
- TRNG_SCR4L_RUN4_RNG_SHIFT : MIMXRT1062.h
- TRNG_SCR5C_R5_0_CT : MIMXRT1062.h
- TRNG_SCR5C_R5_0_CT_MASK : MIMXRT1062.h
- TRNG_SCR5C_R5_0_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR5C_R5_1_CT : MIMXRT1062.h
- TRNG_SCR5C_R5_1_CT_MASK : MIMXRT1062.h
- TRNG_SCR5C_R5_1_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR5L_RUN5_MAX : MIMXRT1062.h
- TRNG_SCR5L_RUN5_MAX_MASK : MIMXRT1062.h
- TRNG_SCR5L_RUN5_MAX_SHIFT : MIMXRT1062.h
- TRNG_SCR5L_RUN5_RNG : MIMXRT1062.h
- TRNG_SCR5L_RUN5_RNG_MASK : MIMXRT1062.h
- TRNG_SCR5L_RUN5_RNG_SHIFT : MIMXRT1062.h
- TRNG_SCR6PC_R6P_0_CT : MIMXRT1062.h
- TRNG_SCR6PC_R6P_0_CT_MASK : MIMXRT1062.h
- TRNG_SCR6PC_R6P_0_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR6PC_R6P_1_CT : MIMXRT1062.h
- TRNG_SCR6PC_R6P_1_CT_MASK : MIMXRT1062.h
- TRNG_SCR6PC_R6P_1_CT_SHIFT : MIMXRT1062.h
- TRNG_SCR6PL_RUN6P_MAX : MIMXRT1062.h
- TRNG_SCR6PL_RUN6P_MAX_MASK : MIMXRT1062.h
- TRNG_SCR6PL_RUN6P_MAX_SHIFT : MIMXRT1062.h
- TRNG_SCR6PL_RUN6P_RNG : MIMXRT1062.h
- TRNG_SCR6PL_RUN6P_RNG_MASK : MIMXRT1062.h
- TRNG_SCR6PL_RUN6P_RNG_SHIFT : MIMXRT1062.h
- TRNG_SDCTL_ENT_DLY : MIMXRT1062.h
- TRNG_SDCTL_ENT_DLY_MASK : MIMXRT1062.h
- TRNG_SDCTL_ENT_DLY_SHIFT : MIMXRT1062.h
- TRNG_SDCTL_SAMP_SIZE : MIMXRT1062.h
- TRNG_SDCTL_SAMP_SIZE_MASK : MIMXRT1062.h
- TRNG_SDCTL_SAMP_SIZE_SHIFT : MIMXRT1062.h
- TRNG_SEC_CFG_NO_PRGM : MIMXRT1062.h
- TRNG_SEC_CFG_NO_PRGM_MASK : MIMXRT1062.h
- TRNG_SEC_CFG_NO_PRGM_SHIFT : MIMXRT1062.h
- TRNG_SEC_CFG_UNUSED0 : MIMXRT1062.h
- TRNG_SEC_CFG_UNUSED0_MASK : MIMXRT1062.h
- TRNG_SEC_CFG_UNUSED0_SHIFT : MIMXRT1062.h
- TRNG_SEC_CFG_UNUSED2 : MIMXRT1062.h
- TRNG_SEC_CFG_UNUSED2_MASK : MIMXRT1062.h
- TRNG_SEC_CFG_UNUSED2_SHIFT : MIMXRT1062.h
- TRNG_STATUS_RETRY_CT : MIMXRT1062.h
- TRNG_STATUS_RETRY_CT_MASK : MIMXRT1062.h
- TRNG_STATUS_RETRY_CT_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF1BR0 : MIMXRT1062.h
- TRNG_STATUS_TF1BR0_MASK : MIMXRT1062.h
- TRNG_STATUS_TF1BR0_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF1BR1 : MIMXRT1062.h
- TRNG_STATUS_TF1BR1_MASK : MIMXRT1062.h
- TRNG_STATUS_TF1BR1_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF2BR0 : MIMXRT1062.h
- TRNG_STATUS_TF2BR0_MASK : MIMXRT1062.h
- TRNG_STATUS_TF2BR0_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF2BR1 : MIMXRT1062.h
- TRNG_STATUS_TF2BR1_MASK : MIMXRT1062.h
- TRNG_STATUS_TF2BR1_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF3BR0 : MIMXRT1062.h
- TRNG_STATUS_TF3BR0_MASK : MIMXRT1062.h
- TRNG_STATUS_TF3BR0_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF3BR1 : MIMXRT1062.h
- TRNG_STATUS_TF3BR1_MASK : MIMXRT1062.h
- TRNG_STATUS_TF3BR1_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF4BR0 : MIMXRT1062.h
- TRNG_STATUS_TF4BR0_MASK : MIMXRT1062.h
- TRNG_STATUS_TF4BR0_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF4BR1 : MIMXRT1062.h
- TRNG_STATUS_TF4BR1_MASK : MIMXRT1062.h
- TRNG_STATUS_TF4BR1_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF5BR0 : MIMXRT1062.h
- TRNG_STATUS_TF5BR0_MASK : MIMXRT1062.h
- TRNG_STATUS_TF5BR0_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF5BR1 : MIMXRT1062.h
- TRNG_STATUS_TF5BR1_MASK : MIMXRT1062.h
- TRNG_STATUS_TF5BR1_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF6PBR0 : MIMXRT1062.h
- TRNG_STATUS_TF6PBR0_MASK : MIMXRT1062.h
- TRNG_STATUS_TF6PBR0_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TF6PBR1 : MIMXRT1062.h
- TRNG_STATUS_TF6PBR1_MASK : MIMXRT1062.h
- TRNG_STATUS_TF6PBR1_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TFLR : MIMXRT1062.h
- TRNG_STATUS_TFLR_MASK : MIMXRT1062.h
- TRNG_STATUS_TFLR_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TFMB : MIMXRT1062.h
- TRNG_STATUS_TFMB_MASK : MIMXRT1062.h
- TRNG_STATUS_TFMB_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TFP : MIMXRT1062.h
- TRNG_STATUS_TFP_MASK : MIMXRT1062.h
- TRNG_STATUS_TFP_SHIFT : MIMXRT1062.h
- TRNG_STATUS_TFSB : MIMXRT1062.h
- TRNG_STATUS_TFSB_MASK : MIMXRT1062.h
- TRNG_STATUS_TFSB_SHIFT : MIMXRT1062.h
- TRNG_TOTSAM_TOT_SAM : MIMXRT1062.h
- TRNG_TOTSAM_TOT_SAM_MASK : MIMXRT1062.h
- TRNG_TOTSAM_TOT_SAM_SHIFT : MIMXRT1062.h
- TRNG_VID1_IP_ID : MIMXRT1062.h
- TRNG_VID1_IP_ID_MASK : MIMXRT1062.h
- TRNG_VID1_IP_ID_SHIFT : MIMXRT1062.h
- TRNG_VID1_MAJ_REV : MIMXRT1062.h
- TRNG_VID1_MAJ_REV_MASK : MIMXRT1062.h
- TRNG_VID1_MAJ_REV_SHIFT : MIMXRT1062.h
- TRNG_VID1_MIN_REV : MIMXRT1062.h
- TRNG_VID1_MIN_REV_MASK : MIMXRT1062.h
- TRNG_VID1_MIN_REV_SHIFT : MIMXRT1062.h
- TRNG_VID2_CONFIG_OPT : MIMXRT1062.h
- TRNG_VID2_CONFIG_OPT_MASK : MIMXRT1062.h
- TRNG_VID2_CONFIG_OPT_SHIFT : MIMXRT1062.h
- TRNG_VID2_ECO_REV : MIMXRT1062.h
- TRNG_VID2_ECO_REV_MASK : MIMXRT1062.h
- TRNG_VID2_ECO_REV_SHIFT : MIMXRT1062.h
- TRNG_VID2_ERA : MIMXRT1062.h
- TRNG_VID2_ERA_MASK : MIMXRT1062.h
- TRNG_VID2_ERA_SHIFT : MIMXRT1062.h
- TRNG_VID2_INTG_OPT : MIMXRT1062.h
- TRNG_VID2_INTG_OPT_MASK : MIMXRT1062.h
- TRNG_VID2_INTG_OPT_SHIFT : MIMXRT1062.h
- TSC : MIMXRT1062.h
- TSC_BASE : MIMXRT1062.h
- TSC_BASE_ADDRS : MIMXRT1062.h
- TSC_BASE_PTRS : MIMXRT1062.h
- TSC_BASIC_SETTING__4_5_WIRE : MIMXRT1062.h
- TSC_BASIC_SETTING__4_5_WIRE_MASK : MIMXRT1062.h
- TSC_BASIC_SETTING__4_5_WIRE_SHIFT : MIMXRT1062.h
- TSC_BASIC_SETTING_AUTO_MEASURE : MIMXRT1062.h
- TSC_BASIC_SETTING_AUTO_MEASURE_MASK : MIMXRT1062.h
- TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT : MIMXRT1062.h
- TSC_BASIC_SETTING_MEASURE_DELAY_TIME : MIMXRT1062.h
- TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK : MIMXRT1062.h
- TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT : MIMXRT1062.h
- TSC_BASIC_SETTING_WIRE_4_5 : MIMXRT1062.h
- TSC_BASIC_SETTING_WIRE_4_5_MASK : MIMXRT1062.h
- TSC_BASIC_SETTING_WIRE_4_5_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_DE_GLITCH : MIMXRT1062.h
- TSC_DEBUG_MODE2_DE_GLITCH_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_DE_GLITCH_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_FIVE_WIRE : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_FOUR_WIRE : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_INTERMEDIATE : MIMXRT1062.h
- TSC_DEBUG_MODE2_INTERMEDIATE_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_STATE_MACHINE : MIMXRT1062.h
- TSC_DEBUG_MODE2_STATE_MACHINE_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_200K_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_PULL_DOWN : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_200K_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_PULL_DOWN : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_200K_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_PULL_DOWN : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_200K_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_PULL_DOWN : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_200K_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_PULL_DOWN : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_PULL_UP : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO_CLEAR : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_COCO_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_CONV_VALUE : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE_DEBUG_EN : MIMXRT1062.h
- TSC_DEBUG_MODE_DEBUG_EN_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE_DEBUG_EN_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE_EXT_HWTS : MIMXRT1062.h
- TSC_DEBUG_MODE_EXT_HWTS_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE_EXT_HWTS_SHIFT : MIMXRT1062.h
- TSC_DEBUG_MODE_TRIGGER : MIMXRT1062.h
- TSC_DEBUG_MODE_TRIGGER_MASK : MIMXRT1062.h
- TSC_DEBUG_MODE_TRIGGER_SHIFT : MIMXRT1062.h
- TSC_FLOW_CONTROL_DISABLE : MIMXRT1062.h
- TSC_FLOW_CONTROL_DISABLE_MASK : MIMXRT1062.h
- TSC_FLOW_CONTROL_DISABLE_SHIFT : MIMXRT1062.h
- TSC_FLOW_CONTROL_DROP_MEASURE : MIMXRT1062.h
- TSC_FLOW_CONTROL_DROP_MEASURE_MASK : MIMXRT1062.h
- TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT : MIMXRT1062.h
- TSC_FLOW_CONTROL_START_MEASURE : MIMXRT1062.h
- TSC_FLOW_CONTROL_START_MEASURE_MASK : MIMXRT1062.h
- TSC_FLOW_CONTROL_START_MEASURE_SHIFT : MIMXRT1062.h
- TSC_FLOW_CONTROL_START_SENSE : MIMXRT1062.h
- TSC_FLOW_CONTROL_START_SENSE_MASK : MIMXRT1062.h
- TSC_FLOW_CONTROL_START_SENSE_SHIFT : MIMXRT1062.h
- TSC_FLOW_CONTROL_SW_RST : MIMXRT1062.h
- TSC_FLOW_CONTROL_SW_RST_MASK : MIMXRT1062.h
- TSC_FLOW_CONTROL_SW_RST_SHIFT : MIMXRT1062.h
- TSC_INT_EN_DETECT_INT_EN : MIMXRT1062.h
- TSC_INT_EN_DETECT_INT_EN_MASK : MIMXRT1062.h
- TSC_INT_EN_DETECT_INT_EN_SHIFT : MIMXRT1062.h
- TSC_INT_EN_IDLE_SW_INT_EN : MIMXRT1062.h
- TSC_INT_EN_IDLE_SW_INT_EN_MASK : MIMXRT1062.h
- TSC_INT_EN_IDLE_SW_INT_EN_SHIFT : MIMXRT1062.h
- TSC_INT_EN_MEASURE_INT_EN : MIMXRT1062.h
- TSC_INT_EN_MEASURE_INT_EN_MASK : MIMXRT1062.h
- TSC_INT_EN_MEASURE_INT_EN_SHIFT : MIMXRT1062.h
- TSC_INT_SIG_EN_DETECT_SIG_EN : MIMXRT1062.h
- TSC_INT_SIG_EN_DETECT_SIG_EN_MASK : MIMXRT1062.h
- TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT : MIMXRT1062.h
- TSC_INT_SIG_EN_IDLE_SW_SIG_EN : MIMXRT1062.h
- TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK : MIMXRT1062.h
- TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT : MIMXRT1062.h
- TSC_INT_SIG_EN_MEASURE_SIG_EN : MIMXRT1062.h
- TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK : MIMXRT1062.h
- TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT : MIMXRT1062.h
- TSC_INT_SIG_EN_VALID_SIG_EN : MIMXRT1062.h
- TSC_INT_SIG_EN_VALID_SIG_EN_MASK : MIMXRT1062.h
- TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT : MIMXRT1062.h
- TSC_INT_STATUS_DETECT : MIMXRT1062.h
- TSC_INT_STATUS_DETECT_MASK : MIMXRT1062.h
- TSC_INT_STATUS_DETECT_SHIFT : MIMXRT1062.h
- TSC_INT_STATUS_IDLE_SW : MIMXRT1062.h
- TSC_INT_STATUS_IDLE_SW_MASK : MIMXRT1062.h
- TSC_INT_STATUS_IDLE_SW_SHIFT : MIMXRT1062.h
- TSC_INT_STATUS_MEASURE : MIMXRT1062.h
- TSC_INT_STATUS_MEASURE_MASK : MIMXRT1062.h
- TSC_INT_STATUS_MEASURE_SHIFT : MIMXRT1062.h
- TSC_INT_STATUS_VALID : MIMXRT1062.h
- TSC_INT_STATUS_VALID_MASK : MIMXRT1062.h
- TSC_INT_STATUS_VALID_SHIFT : MIMXRT1062.h
- TSC_IRQS : MIMXRT1062.h
- TSC_MEASEURE_VALUE_X_VALUE : MIMXRT1062.h
- TSC_MEASEURE_VALUE_X_VALUE_MASK : MIMXRT1062.h
- TSC_MEASEURE_VALUE_X_VALUE_SHIFT : MIMXRT1062.h
- TSC_MEASEURE_VALUE_Y_VALUE : MIMXRT1062.h
- TSC_MEASEURE_VALUE_Y_VALUE_MASK : MIMXRT1062.h
- TSC_MEASEURE_VALUE_Y_VALUE_SHIFT : MIMXRT1062.h
- TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME : MIMXRT1062.h
- TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK : MIMXRT1062.h
- TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT : MIMXRT1062.h
- twiddleCoef : arm_common_tables.h