Callisto4Bootloader: ADC Register Masks

Callisto4Bootloader

Macros
ADC Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » ADC Peripheral Access Layer

## Macros

#define | ADC_HC_COUNT (8U)
#define | ADC_R_COUNT (8U)

## HC - Control register for hardware triggers

#define | ADC_HC_ADCH_MASK (0x1FU)
#define | ADC_HC_ADCH_SHIFT (0U)
#define | ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
#define | ADC_HC_AIEN_MASK (0x80U)
#define | ADC_HC_AIEN_SHIFT (7U)
#define | ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)

## HS - Status register for HW triggers

#define | ADC_HS_COCO0_MASK (0x1U)
#define | ADC_HS_COCO0_SHIFT (0U)
#define | ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)

## R - Data result register for HW triggers

#define | ADC_R_CDATA_MASK (0xFFFU)
#define | ADC_R_CDATA_SHIFT (0U)
#define | ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)

## CFG - Configuration register

#define | ADC_CFG_ADICLK_MASK (0x3U)
#define | ADC_CFG_ADICLK_SHIFT (0U)
#define | ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
#define | ADC_CFG_MODE_MASK (0xCU)
#define | ADC_CFG_MODE_SHIFT (2U)
#define | ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
#define | ADC_CFG_ADLSMP_MASK (0x10U)
#define | ADC_CFG_ADLSMP_SHIFT (4U)
#define | ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
#define | ADC_CFG_ADIV_MASK (0x60U)
#define | ADC_CFG_ADIV_SHIFT (5U)
#define | ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
#define | ADC_CFG_ADLPC_MASK (0x80U)
#define | ADC_CFG_ADLPC_SHIFT (7U)
#define | ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
#define | ADC_CFG_ADSTS_MASK (0x300U)
#define | ADC_CFG_ADSTS_SHIFT (8U)
#define | ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
#define | ADC_CFG_ADHSC_MASK (0x400U)
#define | ADC_CFG_ADHSC_SHIFT (10U)
#define | ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
#define | ADC_CFG_REFSEL_MASK (0x1800U)
#define | ADC_CFG_REFSEL_SHIFT (11U)
#define | ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define | ADC_CFG_ADTRG_MASK (0x2000U)
#define | ADC_CFG_ADTRG_SHIFT (13U)
#define | ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
#define | ADC_CFG_AVGS_MASK (0xC000U)
#define | ADC_CFG_AVGS_SHIFT (14U)
#define | ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
#define | ADC_CFG_OVWREN_MASK (0x10000U)
#define | ADC_CFG_OVWREN_SHIFT (16U)
#define | ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)

## GC - General control register

#define | ADC_GC_ADACKEN_MASK (0x1U)
#define | ADC_GC_ADACKEN_SHIFT (0U)
#define | ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
#define | ADC_GC_DMAEN_MASK (0x2U)
#define | ADC_GC_DMAEN_SHIFT (1U)
#define | ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
#define | ADC_GC_ACREN_MASK (0x4U)
#define | ADC_GC_ACREN_SHIFT (2U)
#define | ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
#define | ADC_GC_ACFGT_MASK (0x8U)
#define | ADC_GC_ACFGT_SHIFT (3U)
#define | ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
#define | ADC_GC_ACFE_MASK (0x10U)
#define | ADC_GC_ACFE_SHIFT (4U)
#define | ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
#define | ADC_GC_AVGE_MASK (0x20U)
#define | ADC_GC_AVGE_SHIFT (5U)
#define | ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
#define | ADC_GC_ADCO_MASK (0x40U)
#define | ADC_GC_ADCO_SHIFT (6U)
#define | ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
#define | ADC_GC_CAL_MASK (0x80U)
#define | ADC_GC_CAL_SHIFT (7U)
#define | ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)

## GS - General status register

#define | ADC_GS_ADACT_MASK (0x1U)
#define | ADC_GS_ADACT_SHIFT (0U)
#define | ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
#define | ADC_GS_CALF_MASK (0x2U)
#define | ADC_GS_CALF_SHIFT (1U)
#define | ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
#define | ADC_GS_AWKST_MASK (0x4U)
#define | ADC_GS_AWKST_SHIFT (2U)
#define | ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)

## CV - Compare value register

#define | ADC_CV_CV1_MASK (0xFFFU)
#define | ADC_CV_CV1_SHIFT (0U)
#define | ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
#define | ADC_CV_CV2_MASK (0xFFF0000U)
#define | ADC_CV_CV2_SHIFT (16U)
#define | ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)

## OFS - Offset correction value register

#define | ADC_OFS_OFS_MASK (0xFFFU)
#define | ADC_OFS_OFS_SHIFT (0U)
#define | ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
#define | ADC_OFS_SIGN_MASK (0x1000U)
#define | ADC_OFS_SIGN_SHIFT (12U)
#define | ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)

## CAL - Calibration value register

#define | ADC_CAL_CAL_CODE_MASK (0xFU)
#define | ADC_CAL_CAL_CODE_SHIFT (0U)
#define | ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ ADC_CAL_CAL_CODE

#define ADC_CAL_CAL_CODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)

CAL_CODE - Calibration Result Value

Definition at line 1703 of file MIMXRT1062.h.

## ◆ ADC_CAL_CAL_CODE_MASK

#define ADC_CAL_CAL_CODE_MASK (0xFU)

Definition at line 1699 of file MIMXRT1062.h.

## ◆ ADC_CAL_CAL_CODE_SHIFT

#define ADC_CAL_CAL_CODE_SHIFT (0U)

Definition at line 1700 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADHSC

#define ADC_CFG_ADHSC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)

ADHSC - High Speed Configuration 0b0..Normal conversion selected. 0b1..High speed conversion selected.

Definition at line 1547 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADHSC_MASK

#define ADC_CFG_ADHSC_MASK (0x400U)

Definition at line 1541 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADHSC_SHIFT

#define ADC_CFG_ADHSC_SHIFT (10U)

Definition at line 1542 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADICLK

#define ADC_CFG_ADICLK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)

ADICLK - Input Clock Select 0b00..IPG clock 0b01..IPG clock divided by 2 0b10..Reserved 0b11..Asynchronous clock (ADACK)

Definition at line 1499 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADICLK_MASK

#define ADC_CFG_ADICLK_MASK (0x3U)

Definition at line 1491 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADICLK_SHIFT

#define ADC_CFG_ADICLK_SHIFT (0U)

Definition at line 1492 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADIV

#define ADC_CFG_ADIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)

ADIV - Clock Divide Select 0b00..Input clock 0b01..Input clock / 2 0b10..Input clock / 4 0b11..Input clock / 8

Definition at line 1524 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADIV_MASK

#define ADC_CFG_ADIV_MASK (0x60U)

Definition at line 1516 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADIV_SHIFT

#define ADC_CFG_ADIV_SHIFT (5U)

Definition at line 1517 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADLPC

#define ADC_CFG_ADLPC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)

ADLPC - Low-Power Configuration 0b0..ADC hard block not in low power mode. 0b1..ADC hard block in low power mode.

Definition at line 1531 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADLPC_MASK

#define ADC_CFG_ADLPC_MASK (0x80U)

Definition at line 1525 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADLPC_SHIFT

#define ADC_CFG_ADLPC_SHIFT (7U)

Definition at line 1526 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADLSMP

#define ADC_CFG_ADLSMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)

ADLSMP - Long Sample Time Configuration 0b0..Short sample mode. 0b1..Long sample mode.

Definition at line 1515 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADLSMP_MASK

#define ADC_CFG_ADLSMP_MASK (0x10U)

Definition at line 1509 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADLSMP_SHIFT

#define ADC_CFG_ADLSMP_SHIFT (4U)

Definition at line 1510 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADSTS

#define ADC_CFG_ADSTS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)

ADSTS 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b

Definition at line 1540 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADSTS_MASK

#define ADC_CFG_ADSTS_MASK (0x300U)

Definition at line 1532 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADSTS_SHIFT

#define ADC_CFG_ADSTS_SHIFT (8U)

Definition at line 1533 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADTRG

#define ADC_CFG_ADTRG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)

ADTRG - Conversion Trigger Select 0b0..Software trigger selected 0b1..Hardware trigger selected

Definition at line 1563 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADTRG_MASK

#define ADC_CFG_ADTRG_MASK (0x2000U)

Definition at line 1557 of file MIMXRT1062.h.

## ◆ ADC_CFG_ADTRG_SHIFT

#define ADC_CFG_ADTRG_SHIFT (13U)

Definition at line 1558 of file MIMXRT1062.h.

## ◆ ADC_CFG_AVGS

#define ADC_CFG_AVGS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)

AVGS - Hardware Average select 0b00..4 samples averaged 0b01..8 samples averaged 0b10..16 samples averaged 0b11..32 samples averaged

Definition at line 1572 of file MIMXRT1062.h.

## ◆ ADC_CFG_AVGS_MASK

#define ADC_CFG_AVGS_MASK (0xC000U)

Definition at line 1564 of file MIMXRT1062.h.

## ◆ ADC_CFG_AVGS_SHIFT

#define ADC_CFG_AVGS_SHIFT (14U)

Definition at line 1565 of file MIMXRT1062.h.

## ◆ ADC_CFG_MODE

#define ADC_CFG_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)

MODE - Conversion Mode Selection 0b00..8-bit conversion 0b01..10-bit conversion 0b10..12-bit conversion 0b11..Reserved

Definition at line 1508 of file MIMXRT1062.h.

## ◆ ADC_CFG_MODE_MASK

#define ADC_CFG_MODE_MASK (0xCU)

Definition at line 1500 of file MIMXRT1062.h.

## ◆ ADC_CFG_MODE_SHIFT

#define ADC_CFG_MODE_SHIFT (2U)

Definition at line 1501 of file MIMXRT1062.h.

## ◆ ADC_CFG_OVWREN

#define ADC_CFG_OVWREN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)

OVWREN - Data Overwrite Enable 0b1..Enable the overwriting. 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.

Definition at line 1579 of file MIMXRT1062.h.

## ◆ ADC_CFG_OVWREN_MASK

#define ADC_CFG_OVWREN_MASK (0x10000U)

Definition at line 1573 of file MIMXRT1062.h.

## ◆ ADC_CFG_OVWREN_SHIFT

#define ADC_CFG_OVWREN_SHIFT (16U)

Definition at line 1574 of file MIMXRT1062.h.

## ◆ ADC_CFG_REFSEL

#define ADC_CFG_REFSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..Selects VREFH/VREFL as reference voltage. 0b01..Reserved 0b10..Reserved 0b11..Reserved

Definition at line 1556 of file MIMXRT1062.h.

## ◆ ADC_CFG_REFSEL_MASK

#define ADC_CFG_REFSEL_MASK (0x1800U)

Definition at line 1548 of file MIMXRT1062.h.

## ◆ ADC_CFG_REFSEL_SHIFT

#define ADC_CFG_REFSEL_SHIFT (11U)

Definition at line 1549 of file MIMXRT1062.h.

## ◆ ADC_CV_CV1

#define ADC_CV_CV1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)

CV1 - Compare Value 1

Definition at line 1673 of file MIMXRT1062.h.

## ◆ ADC_CV_CV1_MASK

#define ADC_CV_CV1_MASK (0xFFFU)

Definition at line 1669 of file MIMXRT1062.h.

## ◆ ADC_CV_CV1_SHIFT

#define ADC_CV_CV1_SHIFT (0U)

Definition at line 1670 of file MIMXRT1062.h.

## ◆ ADC_CV_CV2

#define ADC_CV_CV2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)

CV2 - Compare Value 2

Definition at line 1678 of file MIMXRT1062.h.

## ◆ ADC_CV_CV2_MASK

#define ADC_CV_CV2_MASK (0xFFF0000U)

Definition at line 1674 of file MIMXRT1062.h.

## ◆ ADC_CV_CV2_SHIFT

#define ADC_CV_CV2_SHIFT (16U)

Definition at line 1675 of file MIMXRT1062.h.

## ◆ ADC_GC_ACFE

#define ADC_GC_ACFE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)

ACFE - Compare Function Enable 0b0..Compare function disabled 0b1..Compare function enabled

Definition at line 1620 of file MIMXRT1062.h.

## ◆ ADC_GC_ACFE_MASK

#define ADC_GC_ACFE_MASK (0x10U)

Definition at line 1614 of file MIMXRT1062.h.

## ◆ ADC_GC_ACFE_SHIFT

#define ADC_GC_ACFE_SHIFT (4U)

Definition at line 1615 of file MIMXRT1062.h.

## ◆ ADC_GC_ACFGT

#define ADC_GC_ACFGT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)

ACFGT - Compare Function Greater Than Enable 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers.

Definition at line 1613 of file MIMXRT1062.h.

## ◆ ADC_GC_ACFGT_MASK

#define ADC_GC_ACFGT_MASK (0x8U)

Definition at line 1605 of file MIMXRT1062.h.

## ◆ ADC_GC_ACFGT_SHIFT

#define ADC_GC_ACFGT_SHIFT (3U)

Definition at line 1606 of file MIMXRT1062.h.

## ◆ ADC_GC_ACREN

#define ADC_GC_ACREN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)

ACREN - Compare Function Range Enable 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.

Definition at line 1604 of file MIMXRT1062.h.

## ◆ ADC_GC_ACREN_MASK

#define ADC_GC_ACREN_MASK (0x4U)

Definition at line 1598 of file MIMXRT1062.h.

## ◆ ADC_GC_ACREN_SHIFT

#define ADC_GC_ACREN_SHIFT (2U)

Definition at line 1599 of file MIMXRT1062.h.

## ◆ ADC_GC_ADACKEN

#define ADC_GC_ADACKEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)

ADACKEN - Asynchronous clock output enable 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC

Definition at line 1590 of file MIMXRT1062.h.

## ◆ ADC_GC_ADACKEN_MASK

#define ADC_GC_ADACKEN_MASK (0x1U)

Definition at line 1584 of file MIMXRT1062.h.

## ◆ ADC_GC_ADACKEN_SHIFT

#define ADC_GC_ADACKEN_SHIFT (0U)

Definition at line 1585 of file MIMXRT1062.h.

## ◆ ADC_GC_ADCO

#define ADC_GC_ADCO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)

ADCO - Continuous Conversion Enable 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.

Definition at line 1634 of file MIMXRT1062.h.

## ◆ ADC_GC_ADCO_MASK

#define ADC_GC_ADCO_MASK (0x40U)

Definition at line 1628 of file MIMXRT1062.h.

## ◆ ADC_GC_ADCO_SHIFT

#define ADC_GC_ADCO_SHIFT (6U)

Definition at line 1629 of file MIMXRT1062.h.

## ◆ ADC_GC_AVGE

#define ADC_GC_AVGE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)

AVGE - Hardware average enable 0b0..Hardware average function disabled 0b1..Hardware average function enabled

Definition at line 1627 of file MIMXRT1062.h.

## ◆ ADC_GC_AVGE_MASK

#define ADC_GC_AVGE_MASK (0x20U)

Definition at line 1621 of file MIMXRT1062.h.

## ◆ ADC_GC_AVGE_SHIFT

#define ADC_GC_AVGE_SHIFT (5U)

Definition at line 1622 of file MIMXRT1062.h.

## ◆ ADC_GC_CAL

#define ADC_GC_CAL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)

CAL - Calibration

Definition at line 1639 of file MIMXRT1062.h.

## ◆ ADC_GC_CAL_MASK

#define ADC_GC_CAL_MASK (0x80U)

Definition at line 1635 of file MIMXRT1062.h.

## ◆ ADC_GC_CAL_SHIFT

#define ADC_GC_CAL_SHIFT (7U)

Definition at line 1636 of file MIMXRT1062.h.

## ◆ ADC_GC_DMAEN

#define ADC_GC_DMAEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA disabled (default) 0b1..DMA enabled

Definition at line 1597 of file MIMXRT1062.h.

## ◆ ADC_GC_DMAEN_MASK

#define ADC_GC_DMAEN_MASK (0x2U)

Definition at line 1591 of file MIMXRT1062.h.

## ◆ ADC_GC_DMAEN_SHIFT

#define ADC_GC_DMAEN_SHIFT (1U)

Definition at line 1592 of file MIMXRT1062.h.

## ◆ ADC_GS_ADACT

#define ADC_GS_ADACT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)

ADACT - Conversion Active 0b0..Conversion not in progress. 0b1..Conversion in progress.

Definition at line 1650 of file MIMXRT1062.h.

## ◆ ADC_GS_ADACT_MASK

#define ADC_GS_ADACT_MASK (0x1U)

Definition at line 1644 of file MIMXRT1062.h.

## ◆ ADC_GS_ADACT_SHIFT

#define ADC_GS_ADACT_SHIFT (0U)

Definition at line 1645 of file MIMXRT1062.h.

## ◆ ADC_GS_AWKST

#define ADC_GS_AWKST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)

AWKST - Asynchronous wakeup interrupt status 0b1..Asynchronous wake up interrupt occurred in stop mode. 0b0..No asynchronous interrupt.

Definition at line 1664 of file MIMXRT1062.h.

## ◆ ADC_GS_AWKST_MASK

#define ADC_GS_AWKST_MASK (0x4U)

Definition at line 1658 of file MIMXRT1062.h.

## ◆ ADC_GS_AWKST_SHIFT

#define ADC_GS_AWKST_SHIFT (2U)

Definition at line 1659 of file MIMXRT1062.h.

## ◆ ADC_GS_CALF

#define ADC_GS_CALF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)

CALF - Calibration Failed Flag 0b0..Calibration completed normally. 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.

Definition at line 1657 of file MIMXRT1062.h.

## ◆ ADC_GS_CALF_MASK

#define ADC_GS_CALF_MASK (0x2U)

Definition at line 1651 of file MIMXRT1062.h.

## ◆ ADC_GS_CALF_SHIFT

#define ADC_GS_CALF_SHIFT (1U)

Definition at line 1652 of file MIMXRT1062.h.

## ◆ ADC_HC_ADCH

#define ADC_HC_ADCH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)

ADCH - Input Channel Select 0b10000..External channel selection from ADC_ETC 0b11000..Reserved. 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally 0b11010..Reserved. 0b11011..Reserved. 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.

Definition at line 1455 of file MIMXRT1062.h.

## ◆ ADC_HC_ADCH_MASK

#define ADC_HC_ADCH_MASK (0x1FU)

Definition at line 1445 of file MIMXRT1062.h.

## ◆ ADC_HC_ADCH_SHIFT

#define ADC_HC_ADCH_SHIFT (0U)

Definition at line 1446 of file MIMXRT1062.h.

## ◆ ADC_HC_AIEN

#define ADC_HC_AIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)

AIEN - Conversion Complete Interrupt Enable/Disable Control 0b1..Conversion complete interrupt enabled 0b0..Conversion complete interrupt disabled

Definition at line 1462 of file MIMXRT1062.h.

## ◆ ADC_HC_AIEN_MASK

#define ADC_HC_AIEN_MASK (0x80U)

Definition at line 1456 of file MIMXRT1062.h.

## ◆ ADC_HC_AIEN_SHIFT

#define ADC_HC_AIEN_SHIFT (7U)

Definition at line 1457 of file MIMXRT1062.h.

## ◆ ADC_HC_COUNT

#define ADC_HC_COUNT (8U)

Definition at line 1466 of file MIMXRT1062.h.

## ◆ ADC_HS_COCO0

#define ADC_HS_COCO0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)

COCO0 - Conversion Complete Flag

Definition at line 1474 of file MIMXRT1062.h.

## ◆ ADC_HS_COCO0_MASK

#define ADC_HS_COCO0_MASK (0x1U)

Definition at line 1470 of file MIMXRT1062.h.

## ◆ ADC_HS_COCO0_SHIFT

#define ADC_HS_COCO0_SHIFT (0U)

Definition at line 1471 of file MIMXRT1062.h.

## ◆ ADC_OFS_OFS

#define ADC_OFS_OFS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)

OFS - Offset value

Definition at line 1687 of file MIMXRT1062.h.

## ◆ ADC_OFS_OFS_MASK

#define ADC_OFS_OFS_MASK (0xFFFU)

Definition at line 1683 of file MIMXRT1062.h.

## ◆ ADC_OFS_OFS_SHIFT

#define ADC_OFS_OFS_SHIFT (0U)

Definition at line 1684 of file MIMXRT1062.h.

## ◆ ADC_OFS_SIGN

#define ADC_OFS_SIGN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)

SIGN - Sign bit 0b0..The offset value is added with the raw result 0b1..The offset value is subtracted from the raw converted value

Definition at line 1694 of file MIMXRT1062.h.

## ◆ ADC_OFS_SIGN_MASK

#define ADC_OFS_SIGN_MASK (0x1000U)

Definition at line 1688 of file MIMXRT1062.h.

## ◆ ADC_OFS_SIGN_SHIFT

#define ADC_OFS_SIGN_SHIFT (12U)

Definition at line 1689 of file MIMXRT1062.h.

## ◆ ADC_R_CDATA

#define ADC_R_CDATA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)

CDATA - Data (result of an ADC conversion)

Definition at line 1483 of file MIMXRT1062.h.

## ◆ ADC_R_CDATA_MASK

#define ADC_R_CDATA_MASK (0xFFFU)

Definition at line 1479 of file MIMXRT1062.h.

## ◆ ADC_R_CDATA_SHIFT

#define ADC_R_CDATA_SHIFT (0U)

Definition at line 1480 of file MIMXRT1062.h.

## ◆ ADC_R_COUNT

#define ADC_R_COUNT (8U)

Definition at line 1487 of file MIMXRT1062.h.