Callisto4Bootloader: USDHC Register Masks

Callisto4Bootloader

USDHC Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » USDHC Peripheral Access Layer

## DS_ADDR - DMA System Address

#define | USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
#define | USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
#define | USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)

## BLK_ATT - Block Attributes

#define | USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
#define | USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
#define | USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
#define | USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
#define | USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
#define | USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)

## CMD_ARG - Command Argument

#define | USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_ARG_CMDARG_SHIFT (0U)
#define | USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)

## CMD_XFR_TYP - Command Transfer Type

#define | USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
#define | USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
#define | USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
#define | USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
#define | USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
#define | USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
#define | USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
#define | USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
#define | USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
#define | USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
#define | USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
#define | USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
#define | USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
#define | USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
#define | USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
#define | USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
#define | USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
#define | USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)

## CMD_RSP0 - Command Response0

#define | USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
#define | USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)

## CMD_RSP1 - Command Response1

#define | USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
#define | USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

## CMD_RSP2 - Command Response2

#define | USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
#define | USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

## CMD_RSP3 - Command Response3

#define | USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
#define | USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)

## DATA_BUFF_ACC_PORT - Data Buffer Access Port

#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)

## PRES_STATE - Present State

#define | USDHC_PRES_STATE_CIHB_MASK (0x1U)
#define | USDHC_PRES_STATE_CIHB_SHIFT (0U)
#define | USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
#define | USDHC_PRES_STATE_CDIHB_MASK (0x2U)
#define | USDHC_PRES_STATE_CDIHB_SHIFT (1U)
#define | USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
#define | USDHC_PRES_STATE_DLA_MASK (0x4U)
#define | USDHC_PRES_STATE_DLA_SHIFT (2U)
#define | USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
#define | USDHC_PRES_STATE_SDSTB_MASK (0x8U)
#define | USDHC_PRES_STATE_SDSTB_SHIFT (3U)
#define | USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
#define | USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
#define | USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
#define | USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
#define | USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
#define | USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
#define | USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
#define | USDHC_PRES_STATE_PEROFF_MASK (0x40U)
#define | USDHC_PRES_STATE_PEROFF_SHIFT (6U)
#define | USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
#define | USDHC_PRES_STATE_SDOFF_MASK (0x80U)
#define | USDHC_PRES_STATE_SDOFF_SHIFT (7U)
#define | USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
#define | USDHC_PRES_STATE_WTA_MASK (0x100U)
#define | USDHC_PRES_STATE_WTA_SHIFT (8U)
#define | USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
#define | USDHC_PRES_STATE_RTA_MASK (0x200U)
#define | USDHC_PRES_STATE_RTA_SHIFT (9U)
#define | USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
#define | USDHC_PRES_STATE_BWEN_MASK (0x400U)
#define | USDHC_PRES_STATE_BWEN_SHIFT (10U)
#define | USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
#define | USDHC_PRES_STATE_BREN_MASK (0x800U)
#define | USDHC_PRES_STATE_BREN_SHIFT (11U)
#define | USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
#define | USDHC_PRES_STATE_RTR_MASK (0x1000U)
#define | USDHC_PRES_STATE_RTR_SHIFT (12U)
#define | USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
#define | USDHC_PRES_STATE_TSCD_MASK (0x8000U)
#define | USDHC_PRES_STATE_TSCD_SHIFT (15U)
#define | USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
#define | USDHC_PRES_STATE_CINST_MASK (0x10000U)
#define | USDHC_PRES_STATE_CINST_SHIFT (16U)
#define | USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
#define | USDHC_PRES_STATE_CDPL_MASK (0x40000U)
#define | USDHC_PRES_STATE_CDPL_SHIFT (18U)
#define | USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
#define | USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
#define | USDHC_PRES_STATE_WPSPL_SHIFT (19U)
#define | USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
#define | USDHC_PRES_STATE_CLSL_MASK (0x800000U)
#define | USDHC_PRES_STATE_CLSL_SHIFT (23U)
#define | USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
#define | USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
#define | USDHC_PRES_STATE_DLSL_SHIFT (24U)
#define | USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)

## PROT_CTRL - Protocol Control

#define | USDHC_PROT_CTRL_LCTL_MASK (0x1U)
#define | USDHC_PROT_CTRL_LCTL_SHIFT (0U)
#define | USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
#define | USDHC_PROT_CTRL_DTW_MASK (0x6U)
#define | USDHC_PROT_CTRL_DTW_SHIFT (1U)
#define | USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
#define | USDHC_PROT_CTRL_D3CD_MASK (0x8U)
#define | USDHC_PROT_CTRL_D3CD_SHIFT (3U)
#define | USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
#define | USDHC_PROT_CTRL_EMODE_MASK (0x30U)
#define | USDHC_PROT_CTRL_EMODE_SHIFT (4U)
#define | USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
#define | USDHC_PROT_CTRL_CDTL_MASK (0x40U)
#define | USDHC_PROT_CTRL_CDTL_SHIFT (6U)
#define | USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
#define | USDHC_PROT_CTRL_CDSS_MASK (0x80U)
#define | USDHC_PROT_CTRL_CDSS_SHIFT (7U)
#define | USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
#define | USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
#define | USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
#define | USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
#define | USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
#define | USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
#define | USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
#define | USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
#define | USDHC_PROT_CTRL_CREQ_SHIFT (17U)
#define | USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
#define | USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
#define | USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
#define | USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
#define | USDHC_PROT_CTRL_IABG_MASK (0x80000U)
#define | USDHC_PROT_CTRL_IABG_SHIFT (19U)
#define | USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
#define | USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
#define | USDHC_PROT_CTRL_WECINT_SHIFT (24U)
#define | USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
#define | USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
#define | USDHC_PROT_CTRL_WECINS_SHIFT (25U)
#define | USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
#define | USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
#define | USDHC_PROT_CTRL_WECRM_SHIFT (26U)
#define | USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
#define | USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
#define | USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
#define | USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)

## SYS_CTRL - System Control

#define | USDHC_SYS_CTRL_DVS_MASK (0xF0U)
#define | USDHC_SYS_CTRL_DVS_SHIFT (4U)
#define | USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
#define | USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
#define | USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
#define | USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
#define | USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
#define | USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
#define | USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
#define | USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
#define | USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
#define | USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
#define | USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
#define | USDHC_SYS_CTRL_RSTA_SHIFT (24U)
#define | USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
#define | USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
#define | USDHC_SYS_CTRL_RSTC_SHIFT (25U)
#define | USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
#define | USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
#define | USDHC_SYS_CTRL_RSTD_SHIFT (26U)
#define | USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
#define | USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
#define | USDHC_SYS_CTRL_INITA_SHIFT (27U)
#define | USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
#define | USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
#define | USDHC_SYS_CTRL_RSTT_SHIFT (28U)
#define | USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)

## INT_STATUS - Interrupt Status

#define | USDHC_INT_STATUS_CC_MASK (0x1U)
#define | USDHC_INT_STATUS_CC_SHIFT (0U)
#define | USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
#define | USDHC_INT_STATUS_TC_MASK (0x2U)
#define | USDHC_INT_STATUS_TC_SHIFT (1U)
#define | USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
#define | USDHC_INT_STATUS_BGE_MASK (0x4U)
#define | USDHC_INT_STATUS_BGE_SHIFT (2U)
#define | USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
#define | USDHC_INT_STATUS_DINT_MASK (0x8U)
#define | USDHC_INT_STATUS_DINT_SHIFT (3U)
#define | USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
#define | USDHC_INT_STATUS_BWR_MASK (0x10U)
#define | USDHC_INT_STATUS_BWR_SHIFT (4U)
#define | USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
#define | USDHC_INT_STATUS_BRR_MASK (0x20U)
#define | USDHC_INT_STATUS_BRR_SHIFT (5U)
#define | USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
#define | USDHC_INT_STATUS_CINS_MASK (0x40U)
#define | USDHC_INT_STATUS_CINS_SHIFT (6U)
#define | USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
#define | USDHC_INT_STATUS_CRM_MASK (0x80U)
#define | USDHC_INT_STATUS_CRM_SHIFT (7U)
#define | USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
#define | USDHC_INT_STATUS_CINT_MASK (0x100U)
#define | USDHC_INT_STATUS_CINT_SHIFT (8U)
#define | USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
#define | USDHC_INT_STATUS_RTE_MASK (0x1000U)
#define | USDHC_INT_STATUS_RTE_SHIFT (12U)
#define | USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
#define | USDHC_INT_STATUS_TP_MASK (0x4000U)
#define | USDHC_INT_STATUS_TP_SHIFT (14U)
#define | USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
#define | USDHC_INT_STATUS_CTOE_MASK (0x10000U)
#define | USDHC_INT_STATUS_CTOE_SHIFT (16U)
#define | USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
#define | USDHC_INT_STATUS_CCE_MASK (0x20000U)
#define | USDHC_INT_STATUS_CCE_SHIFT (17U)
#define | USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
#define | USDHC_INT_STATUS_CEBE_MASK (0x40000U)
#define | USDHC_INT_STATUS_CEBE_SHIFT (18U)
#define | USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
#define | USDHC_INT_STATUS_CIE_MASK (0x80000U)
#define | USDHC_INT_STATUS_CIE_SHIFT (19U)
#define | USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
#define | USDHC_INT_STATUS_DTOE_MASK (0x100000U)
#define | USDHC_INT_STATUS_DTOE_SHIFT (20U)
#define | USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
#define | USDHC_INT_STATUS_DCE_MASK (0x200000U)
#define | USDHC_INT_STATUS_DCE_SHIFT (21U)
#define | USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
#define | USDHC_INT_STATUS_DEBE_MASK (0x400000U)
#define | USDHC_INT_STATUS_DEBE_SHIFT (22U)
#define | USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
#define | USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
#define | USDHC_INT_STATUS_AC12E_SHIFT (24U)
#define | USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
#define | USDHC_INT_STATUS_TNE_MASK (0x4000000U)
#define | USDHC_INT_STATUS_TNE_SHIFT (26U)
#define | USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
#define | USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
#define | USDHC_INT_STATUS_DMAE_SHIFT (28U)
#define | USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)

## INT_STATUS_EN - Interrupt Status Enable

#define | USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
#define | USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
#define | USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
#define | USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
#define | USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
#define | USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
#define | USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
#define | USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
#define | USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
#define | USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
#define | USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
#define | USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
#define | USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
#define | USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
#define | USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
#define | USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
#define | USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
#define | USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
#define | USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
#define | USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
#define | USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
#define | USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
#define | USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
#define | USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
#define | USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
#define | USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
#define | USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
#define | USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
#define | USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
#define | USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
#define | USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
#define | USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
#define | USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
#define | USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
#define | USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
#define | USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
#define | USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
#define | USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
#define | USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
#define | USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
#define | USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
#define | USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
#define | USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
#define | USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
#define | USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
#define | USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
#define | USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
#define | USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
#define | USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
#define | USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
#define | USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
#define | USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
#define | USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
#define | USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
#define | USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
#define | USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
#define | USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
#define | USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
#define | USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
#define | USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
#define | USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
#define | USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
#define | USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)

## INT_SIGNAL_EN - Interrupt Signal Enable

#define | USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
#define | USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
#define | USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
#define | USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
#define | USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
#define | USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
#define | USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
#define | USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
#define | USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
#define | USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
#define | USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
#define | USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
#define | USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
#define | USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
#define | USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
#define | USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
#define | USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
#define | USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
#define | USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
#define | USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
#define | USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
#define | USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
#define | USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
#define | USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
#define | USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
#define | USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
#define | USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
#define | USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
#define | USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
#define | USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
#define | USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
#define | USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
#define | USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
#define | USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
#define | USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
#define | USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
#define | USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
#define | USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
#define | USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
#define | USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
#define | USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
#define | USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
#define | USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)

## AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status

#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)

## HOST_CTRL_CAP - Host Controller Capabilities

#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
#define | USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
#define | USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
#define | USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
#define | USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
#define | USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
#define | USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
#define | USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
#define | USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
#define | USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
#define | USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
#define | USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
#define | USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
#define | USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
#define | USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
#define | USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
#define | USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
#define | USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
#define | USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
#define | USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
#define | USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
#define | USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
#define | USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
#define | USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
#define | USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
#define | USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
#define | USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
#define | USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
#define | USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
#define | USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
#define | USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)

## WTMK_LVL - Watermark Level

#define | USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
#define | USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
#define | USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
#define | USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
#define | USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
#define | USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
#define | USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
#define | USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
#define | USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
#define | USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
#define | USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
#define | USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)

## MIX_CTRL - Mixer Control

#define | USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
#define | USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
#define | USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
#define | USDHC_MIX_CTRL_BCEN_MASK (0x2U)
#define | USDHC_MIX_CTRL_BCEN_SHIFT (1U)
#define | USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
#define | USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
#define | USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
#define | USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
#define | USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
#define | USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
#define | USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
#define | USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
#define | USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
#define | USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
#define | USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
#define | USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
#define | USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
#define | USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
#define | USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
#define | USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
#define | USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
#define | USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
#define | USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
#define | USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
#define | USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
#define | USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
#define | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
#define | USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
#define | USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
#define | USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
#define | USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
#define | USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

## FORCE_EVENT - Force Event

#define | USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
#define | USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
#define | USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
#define | USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
#define | USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
#define | USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
#define | USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
#define | USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
#define | USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
#define | USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
#define | USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
#define | USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
#define | USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
#define | USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
#define | USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
#define | USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
#define | USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
#define | USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
#define | USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
#define | USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
#define | USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
#define | USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
#define | USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
#define | USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
#define | USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
#define | USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
#define | USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
#define | USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
#define | USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
#define | USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
#define | USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
#define | USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
#define | USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
#define | USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
#define | USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
#define | USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
#define | USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
#define | USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
#define | USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)

## ADMA_ERR_STATUS - ADMA Error Status Register

#define | USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
#define | USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
#define | USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
#define | USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
#define | USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
#define | USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
#define | USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
#define | USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
#define | USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)

## ADMA_SYS_ADDR - ADMA System Address

#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)

## DLL_CTRL - DLL (Delay Line) Control

#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)

## DLL_STATUS - DLL Status

#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)

## CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status

#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)

## VEND_SPEC - Vendor Specific Register

#define | USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
#define | USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
#define | USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
#define | USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
#define | USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
#define | USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
#define | USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
#define | USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
#define | USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)

## MMC_BOOT - MMC Boot Register

#define | USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
#define | USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
#define | USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
#define | USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
#define | USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
#define | USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
#define | USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
#define | USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
#define | USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
#define | USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
#define | USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
#define | USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
#define | USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
#define | USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
#define | USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)

## VEND_SPEC2 - Vendor Specific 2 Register

#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
#define | USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U)
#define | USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U)
#define | USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
#define | USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U)
#define | USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U)
#define | USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)

## TUNING_CTRL - Tuning Control Register

#define | USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
#define | USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
#define | USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
#define | USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
#define | USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
#define | USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
#define | USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
#define | USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
#define | USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
#define | USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
#define | USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
#define | USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
#define | USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
#define | USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
#define | USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ USDHC_ADMA_ERR_STATUS_ADMADCE

#define USDHC_ADMA_ERR_STATUS_ADMADCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)

ADMADCE - ADMA Descriptor Error 0b1..Error 0b0..No Error

Definition at line 45973 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_ERR_STATUS_ADMADCE_MASK

#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)

Definition at line 45967 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT

#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)

Definition at line 45968 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_ERR_STATUS_ADMAES

#define USDHC_ADMA_ERR_STATUS_ADMAES | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

ADMAES - ADMA Error State (when ADMA Error is occurred)

Definition at line 45959 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_ERR_STATUS_ADMAES_MASK

#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)

Definition at line 45955 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT

#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)

Definition at line 45956 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_ERR_STATUS_ADMALME

#define USDHC_ADMA_ERR_STATUS_ADMALME | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

ADMALME - ADMA Length Mismatch Error 0b1..Error 0b0..No Error

Definition at line 45966 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_ERR_STATUS_ADMALME_MASK

#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)

Definition at line 45960 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT

#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)

Definition at line 45961 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_SYS_ADDR_ADS_ADDR

#define USDHC_ADMA_SYS_ADDR_ADS_ADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)

ADS_ADDR - ADMA System Address

Definition at line 45982 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK

#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)

Definition at line 45978 of file MIMXRT1062.h.

## ◆ USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT

#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)

Definition at line 45979 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12CE

#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

AC12CE - Auto CMD12 / 23 CRC Error 0b1..CRC Error Met in Auto CMD12/23 Response 0b0..No CRC error

Definition at line 45631 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK

#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)

Definition at line 45625 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT

#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)

Definition at line 45626 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12EBE

#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

AC12EBE - Auto CMD12 / 23 End Bit Error 0b1..End Bit Error Generated 0b0..No error

Definition at line 45624 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK

#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)

Definition at line 45618 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT

#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)

Definition at line 45619 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12IE

#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

AC12IE - Auto CMD12 / 23 Index Error 0b1..Error, the CMD index in response is not CMD12/23 0b0..No error

Definition at line 45638 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK

#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)

Definition at line 45632 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT

#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)

Definition at line 45633 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12NE

#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

AC12NE - Auto CMD12 Not Executed 0b1..Not executed 0b0..Executed

Definition at line 45610 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK

#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)

Definition at line 45604 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT

#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)

Definition at line 45605 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12TOE

#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

AC12TOE - Auto CMD12 / 23 Timeout Error 0b1..Time out 0b0..No error

Definition at line 45617 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK

#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)

Definition at line 45611 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT

#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)

Definition at line 45612 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E

#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

CNIBAC12E - Command Not Issued By Auto CMD12 Error 0b1..Not Issued 0b0..No error

Definition at line 45645 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK

#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)

Definition at line 45639 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT

#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)

Definition at line 45640 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING

#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

EXECUTE_TUNING - Execute Tuning

Definition at line 45650 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK

#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)

Definition at line 45646 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT

#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)

Definition at line 45647 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL

#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)

SMP_CLK_SEL - Sample Clock Select 0b1..Tuned clock is used to sample data 0b0..Fixed clock is used to sample data

Definition at line 45657 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK

#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)

Definition at line 45651 of file MIMXRT1062.h.

## ◆ USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT

#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)

Definition at line 45652 of file MIMXRT1062.h.

## ◆ USDHC_BLK_ATT_BLKCNT

#define USDHC_BLK_ATT_BLKCNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)

BLKCNT - Block Count 0b1111111111111111..65535 blocks 0b0000000000000010..2 blocks 0b0000000000000001..1 block 0b0000000000000000..Stop Count

Definition at line 44715 of file MIMXRT1062.h.

## ◆ USDHC_BLK_ATT_BLKCNT_MASK

#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)

Definition at line 44707 of file MIMXRT1062.h.

## ◆ USDHC_BLK_ATT_BLKCNT_SHIFT

#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)

Definition at line 44708 of file MIMXRT1062.h.

## ◆ USDHC_BLK_ATT_BLKSIZE

#define USDHC_BLK_ATT_BLKSIZE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

BLKSIZE - Block Size 0b1000000000000..4096 Bytes 0b0100000000000..2048 Bytes 0b0001000000000..512 Bytes 0b0000111111111..511 Bytes 0b0000000000100..4 Bytes 0b0000000000011..3 Bytes 0b0000000000010..2 Bytes 0b0000000000001..1 Byte 0b0000000000000..No data transfer

Definition at line 44706 of file MIMXRT1062.h.

## ◆ USDHC_BLK_ATT_BLKSIZE_MASK

#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)

Definition at line 44693 of file MIMXRT1062.h.

## ◆ USDHC_BLK_ATT_BLKSIZE_SHIFT

#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)

Definition at line 44694 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

DLY_CELL_SET_OUT - DLY_CELL_SET_OUT

Definition at line 46074 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)

Definition at line 46070 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)

Definition at line 46071 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

DLY_CELL_SET_POST - DLY_CELL_SET_POST

Definition at line 46069 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)

Definition at line 46065 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)

Definition at line 46066 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

DLY_CELL_SET_PRE - DLY_CELL_SET_PRE

Definition at line 46079 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)

Definition at line 46075 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)

Definition at line 46076 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR

#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

NXT_ERR - NXT_ERR

Definition at line 46084 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK

#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)

Definition at line 46080 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT

#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)

Definition at line 46081 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR

#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)

PRE_ERR - PRE_ERR

Definition at line 46104 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK

#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)

Definition at line 46100 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT

#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)

Definition at line 46101 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

TAP_SEL_OUT - TAP_SEL_OUT

Definition at line 46094 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)

Definition at line 46090 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)

Definition at line 46091 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

TAP_SEL_POST - TAP_SEL_POST

Definition at line 46089 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)

Definition at line 46085 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)

Definition at line 46086 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

TAP_SEL_PRE - TAP_SEL_PRE

Definition at line 46099 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)

Definition at line 46095 of file MIMXRT1062.h.

## ◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)

Definition at line 46096 of file MIMXRT1062.h.

## ◆ USDHC_CMD_ARG_CMDARG

#define USDHC_CMD_ARG_CMDARG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)

CMDARG - Command Argument

Definition at line 44724 of file MIMXRT1062.h.

## ◆ USDHC_CMD_ARG_CMDARG_MASK

#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)

Definition at line 44720 of file MIMXRT1062.h.

## ◆ USDHC_CMD_ARG_CMDARG_SHIFT

#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)

Definition at line 44721 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP0_CMDRSP0

#define USDHC_CMD_RSP0_CMDRSP0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)

CMDRSP0 - Command Response 0

Definition at line 44781 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP0_CMDRSP0_MASK

#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)

Definition at line 44777 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP0_CMDRSP0_SHIFT

#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)

Definition at line 44778 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP1_CMDRSP1

#define USDHC_CMD_RSP1_CMDRSP1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

CMDRSP1 - Command Response 1

Definition at line 44790 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP1_CMDRSP1_MASK

#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)

Definition at line 44786 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP1_CMDRSP1_SHIFT

#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)

Definition at line 44787 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP2_CMDRSP2

#define USDHC_CMD_RSP2_CMDRSP2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

CMDRSP2 - Command Response 2

Definition at line 44799 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP2_CMDRSP2_MASK

#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)

Definition at line 44795 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP2_CMDRSP2_SHIFT

#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)

Definition at line 44796 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP3_CMDRSP3

#define USDHC_CMD_RSP3_CMDRSP3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)

CMDRSP3 - Command Response 3

Definition at line 44808 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP3_CMDRSP3_MASK

#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)

Definition at line 44804 of file MIMXRT1062.h.

## ◆ USDHC_CMD_RSP3_CMDRSP3_SHIFT

#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)

Definition at line 44805 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CCCEN

#define USDHC_CMD_XFR_TYP_CCCEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

CCCEN - Command CRC Check Enable 0b1..Enable 0b0..Disable

Definition at line 44744 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CCCEN_MASK

#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)

Definition at line 44738 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CCCEN_SHIFT

#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)

Definition at line 44739 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CICEN

#define USDHC_CMD_XFR_TYP_CICEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

CICEN - Command Index Check Enable 0b1..Enable 0b0..Disable

Definition at line 44751 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CICEN_MASK

#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)

Definition at line 44745 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CICEN_SHIFT

#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)

Definition at line 44746 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CMDINX

#define USDHC_CMD_XFR_TYP_CMDINX | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)

CMDINX - Command Index

Definition at line 44772 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CMDINX_MASK

#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)

Definition at line 44768 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CMDINX_SHIFT

#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)

Definition at line 44769 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CMDTYP

#define USDHC_CMD_XFR_TYP_CMDTYP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

CMDTYP - Command Type 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR 0b10..Resume CMD52 for writing Function Select in CCCR 0b01..Suspend CMD52 for writing Bus Suspend in CCCR 0b00..Normal Other commands

Definition at line 44767 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CMDTYP_MASK

#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)

Definition at line 44759 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_CMDTYP_SHIFT

#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)

Definition at line 44760 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_DPSEL

#define USDHC_CMD_XFR_TYP_DPSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

DPSEL - Data Present Select 0b1..Data Present 0b0..No Data Present

Definition at line 44758 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_DPSEL_MASK

#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)

Definition at line 44752 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_DPSEL_SHIFT

#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)

Definition at line 44753 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_RSPTYP

#define USDHC_CMD_XFR_TYP_RSPTYP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

RSPTYP - Response Type Select 0b00..No Response 0b01..Response Length 136 0b10..Response Length 48 0b11..Response Length 48, check Busy after response

Definition at line 44737 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_RSPTYP_MASK

#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)

Definition at line 44729 of file MIMXRT1062.h.

## ◆ USDHC_CMD_XFR_TYP_RSPTYP_SHIFT

#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)

Definition at line 44730 of file MIMXRT1062.h.

## ◆ USDHC_DATA_BUFF_ACC_PORT_DATCONT

#define USDHC_DATA_BUFF_ACC_PORT_DATCONT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)

DATCONT - Data Content

Definition at line 44817 of file MIMXRT1062.h.

## ◆ USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK

#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)

Definition at line 44813 of file MIMXRT1062.h.

## ◆ USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT

#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)

Definition at line 44814 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_ENABLE

#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

DLL_CTRL_ENABLE - DLL_CTRL_ENABLE

Definition at line 45991 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)

Definition at line 45987 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)

Definition at line 45988 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE

#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

DLL_CTRL_GATE_UPDATE - DLL_CTRL_GATE_UPDATE

Definition at line 46011 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)

Definition at line 46007 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)

Definition at line 46008 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT

#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)

DLL_CTRL_REF_UPDATE_INT - DLL_CTRL_REF_UPDATE_INT

Definition at line 46036 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)

Definition at line 46032 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)

Definition at line 46033 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_RESET

#define USDHC_DLL_CTRL_DLL_CTRL_RESET | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

DLL_CTRL_RESET - DLL_CTRL_RESET

Definition at line 45996 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)

Definition at line 45992 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)

Definition at line 45993 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

DLL_CTRL_SLV_DLY_TARGET0 - DLL_CTRL_SLV_DLY_TARGET0

Definition at line 46006 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)

Definition at line 46002 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)

Definition at line 46003 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

DLL_CTRL_SLV_DLY_TARGET1 - DLL_CTRL_SLV_DLY_TARGET1

Definition at line 46026 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)

Definition at line 46022 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)

Definition at line 46023 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

DLL_CTRL_SLV_FORCE_UPD - DLL_CTRL_SLV_FORCE_UPD

Definition at line 46001 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)

Definition at line 45997 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)

Definition at line 45998 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

DLL_CTRL_SLV_OVERRIDE - DLL_CTRL_SLV_OVERRIDE

Definition at line 46016 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)

Definition at line 46012 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)

Definition at line 46013 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

DLL_CTRL_SLV_OVERRIDE_VAL - DLL_CTRL_SLV_OVERRIDE_VAL

Definition at line 46021 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)

Definition at line 46017 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)

Definition at line 46018 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

DLL_CTRL_SLV_UPDATE_INT - DLL_CTRL_SLV_UPDATE_INT

Definition at line 46031 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)

Definition at line 46027 of file MIMXRT1062.h.

## ◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)

Definition at line 46028 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_REF_LOCK

#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

DLL_STS_REF_LOCK - DLL_STS_REF_LOCK

Definition at line 46050 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK

#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)

Definition at line 46046 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT

#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)

Definition at line 46047 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_REF_SEL

#define USDHC_DLL_STATUS_DLL_STS_REF_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)

DLL_STS_REF_SEL - DLL_STS_REF_SEL

Definition at line 46060 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK

#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)

Definition at line 46056 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT

#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)

Definition at line 46057 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_SLV_LOCK

#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

DLL_STS_SLV_LOCK - DLL_STS_SLV_LOCK

Definition at line 46045 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK

#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)

Definition at line 46041 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT

#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)

Definition at line 46042 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_SLV_SEL

#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

DLL_STS_SLV_SEL - DLL_STS_SLV_SEL

Definition at line 46055 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK

#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)

Definition at line 46051 of file MIMXRT1062.h.

## ◆ USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT

#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)

Definition at line 46052 of file MIMXRT1062.h.

## ◆ USDHC_DS_ADDR_DS_ADDR

#define USDHC_DS_ADDR_DS_ADDR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)

DS_ADDR - DS_ADDR

Definition at line 44688 of file MIMXRT1062.h.

## ◆ USDHC_DS_ADDR_DS_ADDR_MASK

#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)

Definition at line 44684 of file MIMXRT1062.h.

## ◆ USDHC_DS_ADDR_DS_ADDR_SHIFT

#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)

Definition at line 44685 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12CE

#define USDHC_FORCE_EVENT_FEVTAC12CE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

FEVTAC12CE - Force Event Auto Command 12 CRC Error

Definition at line 45880 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12CE_MASK

#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)

Definition at line 45876 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT

#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)

Definition at line 45877 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12E

#define USDHC_FORCE_EVENT_FEVTAC12E | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

FEVTAC12E - Force Event Auto Command 12 Error

Definition at line 45935 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12E_MASK

#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)

Definition at line 45931 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12E_SHIFT

#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)

Definition at line 45932 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12EBE

#define USDHC_FORCE_EVENT_FEVTAC12EBE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

FEVTAC12EBE - Force Event Auto Command 12 End Bit Error

Definition at line 45885 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12EBE_MASK

#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)

Definition at line 45881 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT

#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)

Definition at line 45882 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12IE

#define USDHC_FORCE_EVENT_FEVTAC12IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

FEVTAC12IE - Force Event Auto Command 12 Index Error

Definition at line 45890 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12IE_MASK

#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)

Definition at line 45886 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT

#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)

Definition at line 45887 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12NE

#define USDHC_FORCE_EVENT_FEVTAC12NE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

FEVTAC12NE - Force Event Auto Command 12 Not Executed

Definition at line 45870 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12NE_MASK

#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)

Definition at line 45866 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT

#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)

Definition at line 45867 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12TOE

#define USDHC_FORCE_EVENT_FEVTAC12TOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

FEVTAC12TOE - Force Event Auto Command 12 Time Out Error

Definition at line 45875 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12TOE_MASK

#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)

Definition at line 45871 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT

#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)

Definition at line 45872 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCCE

#define USDHC_FORCE_EVENT_FEVTCCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

FEVTCCE - Force Event Command CRC Error

Definition at line 45905 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCCE_MASK

#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)

Definition at line 45901 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCCE_SHIFT

#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)

Definition at line 45902 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCEBE

#define USDHC_FORCE_EVENT_FEVTCEBE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

FEVTCEBE - Force Event Command End Bit Error

Definition at line 45910 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCEBE_MASK

#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)

Definition at line 45906 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCEBE_SHIFT

#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)

Definition at line 45907 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCIE

#define USDHC_FORCE_EVENT_FEVTCIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

FEVTCIE - Force Event Command Index Error

Definition at line 45915 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCIE_MASK

#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)

Definition at line 45911 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCIE_SHIFT

#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)

Definition at line 45912 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCINT

#define USDHC_FORCE_EVENT_FEVTCINT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)

FEVTCINT - Force Event Card Interrupt

Definition at line 45950 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCINT_MASK

#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)

Definition at line 45946 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCINT_SHIFT

#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)

Definition at line 45947 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCNIBAC12E

#define USDHC_FORCE_EVENT_FEVTCNIBAC12E | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

FEVTCNIBAC12E - Force Event Command Not Executed By Auto Command 12 Error

Definition at line 45895 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK

#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)

Definition at line 45891 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT

#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)

Definition at line 45892 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCTOE

#define USDHC_FORCE_EVENT_FEVTCTOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

FEVTCTOE - Force Event Command Time Out Error

Definition at line 45900 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCTOE_MASK

#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)

Definition at line 45896 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTCTOE_SHIFT

#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)

Definition at line 45897 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDCE

#define USDHC_FORCE_EVENT_FEVTDCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

FEVTDCE - Force Event Data CRC Error

Definition at line 45925 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDCE_MASK

#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)

Definition at line 45921 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDCE_SHIFT

#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)

Definition at line 45922 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDEBE

#define USDHC_FORCE_EVENT_FEVTDEBE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

FEVTDEBE - Force Event Data End Bit Error

Definition at line 45930 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDEBE_MASK

#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)

Definition at line 45926 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDEBE_SHIFT

#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)

Definition at line 45927 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDMAE

#define USDHC_FORCE_EVENT_FEVTDMAE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

FEVTDMAE - Force Event DMA Error

Definition at line 45945 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDMAE_MASK

#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)

Definition at line 45941 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDMAE_SHIFT

#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)

Definition at line 45942 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDTOE

#define USDHC_FORCE_EVENT_FEVTDTOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

FEVTDTOE - Force Event Data Time Out Error

Definition at line 45920 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDTOE_MASK

#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)

Definition at line 45916 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTDTOE_SHIFT

#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)

Definition at line 45917 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTTNE

#define USDHC_FORCE_EVENT_FEVTTNE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

FEVTTNE - Force Tuning Error

Definition at line 45940 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTTNE_MASK

#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)

Definition at line 45936 of file MIMXRT1062.h.

## ◆ USDHC_FORCE_EVENT_FEVTTNE_SHIFT

#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)

Definition at line 45937 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_ADMAS

#define USDHC_HOST_CTRL_CAP_ADMAS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

ADMAS - ADMA Support 0b1..Advanced DMA Supported 0b0..Advanced DMA Not supported

Definition at line 45713 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_ADMAS_MASK

#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)

Definition at line 45707 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_ADMAS_SHIFT

#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)

Definition at line 45708 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_DDR50_SUPPORT

#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

DDR50_SUPPORT - DDR50 support

Definition at line 45676 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK

#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)

Definition at line 45672 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT

#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)

Definition at line 45673 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_DMAS

#define USDHC_HOST_CTRL_CAP_DMAS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

DMAS - DMA Support 0b1..DMA Supported 0b0..DMA not supported

Definition at line 45727 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_DMAS_MASK

#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)

Definition at line 45721 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_DMAS_SHIFT

#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)

Definition at line 45722 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_HSS

#define USDHC_HOST_CTRL_CAP_HSS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

HSS - High Speed Support 0b1..High Speed Supported 0b0..High Speed Not Supported

Definition at line 45720 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_HSS_MASK

#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)

Definition at line 45714 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_HSS_SHIFT

#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)

Definition at line 45715 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_MBL

#define USDHC_HOST_CTRL_CAP_MBL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

MBL - Max Block Length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

Definition at line 45706 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_MBL_MASK

#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)

Definition at line 45698 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_MBL_SHIFT

#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)

Definition at line 45699 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_RETUNING_MODE

#define USDHC_HOST_CTRL_CAP_RETUNING_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)

RETUNING_MODE - Retuning Mode 0b00..Mode 1 0b01..Mode 2 0b10..Mode 3 0b11..Reserved

Definition at line 45697 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK

#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)

Definition at line 45689 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT

#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)

Definition at line 45690 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SDR104_SUPPORT

#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

SDR104_SUPPORT - SDR104 support

Definition at line 45671 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK

#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)

Definition at line 45667 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT

#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)

Definition at line 45668 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SDR50_SUPPORT

#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

SDR50_SUPPORT - SDR50 support

Definition at line 45666 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK

#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)

Definition at line 45662 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT

#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)

Definition at line 45663 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SRS

#define USDHC_HOST_CTRL_CAP_SRS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

SRS - Suspend / Resume Support 0b1..Supported 0b0..Not supported

Definition at line 45734 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SRS_MASK

#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)

Definition at line 45728 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_SRS_SHIFT

#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)

Definition at line 45729 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING

#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)

TIME_COUNT_RETUNING - Time Counter for Retuning

Definition at line 45681 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK

#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)

Definition at line 45677 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT

#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)

Definition at line 45678 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50

#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

USE_TUNING_SDR50 - Use Tuning for SDR50 0b1..SDR50 requires tuning 0b0..SDR does not require tuning

Definition at line 45688 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK

#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)

Definition at line 45682 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT

#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)

Definition at line 45683 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS18

#define USDHC_HOST_CTRL_CAP_VS18 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)

VS18 - Voltage Support 1.8 V 0b1..1.8V supported 0b0..1.8V not supported

Definition at line 45755 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS18_MASK

#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)

Definition at line 45749 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS18_SHIFT

#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)

Definition at line 45750 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS30

#define USDHC_HOST_CTRL_CAP_VS30 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

VS30 - Voltage Support 3.0 V 0b1..3.0V supported 0b0..3.0V not supported

Definition at line 45748 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS30_MASK

#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)

Definition at line 45742 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS30_SHIFT

#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)

Definition at line 45743 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS33

#define USDHC_HOST_CTRL_CAP_VS33 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

VS33 - Voltage Support 3.3V 0b1..3.3V supported 0b0..3.3V not supported

Definition at line 45741 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS33_MASK

#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)

Definition at line 45735 of file MIMXRT1062.h.

## ◆ USDHC_HOST_CTRL_CAP_VS33_SHIFT

#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)

Definition at line 45736 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_AC12EIEN

#define USDHC_INT_SIGNAL_EN_AC12EIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

AC12EIEN - Auto CMD12 Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45585 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_AC12EIEN_MASK

#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)

Definition at line 45579 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)

Definition at line 45580 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BGEIEN

#define USDHC_INT_SIGNAL_EN_BGEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

BGEIEN - Block Gap Event Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45473 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BGEIEN_MASK

#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)

Definition at line 45467 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)

Definition at line 45468 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BRRIEN

#define USDHC_INT_SIGNAL_EN_BRRIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

BRRIEN - Buffer Read Ready Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45494 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BRRIEN_MASK

#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)

Definition at line 45488 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)

Definition at line 45489 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BWRIEN

#define USDHC_INT_SIGNAL_EN_BWRIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

BWRIEN - Buffer Write Ready Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45487 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BWRIEN_MASK

#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)

Definition at line 45481 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)

Definition at line 45482 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CCEIEN

#define USDHC_INT_SIGNAL_EN_CCEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

CCEIEN - Command CRC Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45543 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CCEIEN_MASK

#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)

Definition at line 45537 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)

Definition at line 45538 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CCIEN

#define USDHC_INT_SIGNAL_EN_CCIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

CCIEN - Command Complete Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45459 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CCIEN_MASK

#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)

Definition at line 45453 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CCIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)

Definition at line 45454 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CEBEIEN

#define USDHC_INT_SIGNAL_EN_CEBEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

CEBEIEN - Command End Bit Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45550 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CEBEIEN_MASK

#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)

Definition at line 45544 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)

Definition at line 45545 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CIEIEN

#define USDHC_INT_SIGNAL_EN_CIEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

CIEIEN - Command Index Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45557 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CIEIEN_MASK

#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)

Definition at line 45551 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)

Definition at line 45552 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CINSIEN

#define USDHC_INT_SIGNAL_EN_CINSIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

CINSIEN - Card Insertion Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45501 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CINSIEN_MASK

#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)

Definition at line 45495 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)

Definition at line 45496 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CINTIEN

#define USDHC_INT_SIGNAL_EN_CINTIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

CINTIEN - Card Interrupt Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45515 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CINTIEN_MASK

#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)

Definition at line 45509 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)

Definition at line 45510 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CRMIEN

#define USDHC_INT_SIGNAL_EN_CRMIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

CRMIEN - Card Removal Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45508 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CRMIEN_MASK

#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)

Definition at line 45502 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)

Definition at line 45503 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CTOEIEN

#define USDHC_INT_SIGNAL_EN_CTOEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

CTOEIEN - Command Timeout Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45536 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CTOEIEN_MASK

#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)

Definition at line 45530 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)

Definition at line 45531 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DCEIEN

#define USDHC_INT_SIGNAL_EN_DCEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

DCEIEN - Data CRC Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45571 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DCEIEN_MASK

#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)

Definition at line 45565 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)

Definition at line 45566 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DEBEIEN

#define USDHC_INT_SIGNAL_EN_DEBEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

DEBEIEN - Data End Bit Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45578 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DEBEIEN_MASK

#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)

Definition at line 45572 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)

Definition at line 45573 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DINTIEN

#define USDHC_INT_SIGNAL_EN_DINTIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

DINTIEN - DMA Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45480 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DINTIEN_MASK

#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)

Definition at line 45474 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)

Definition at line 45475 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DMAEIEN

#define USDHC_INT_SIGNAL_EN_DMAEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)

DMAEIEN - DMA Error Interrupt Enable 0b1..Enable 0b0..Masked

Definition at line 45599 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DMAEIEN_MASK

#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)

Definition at line 45593 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)

Definition at line 45594 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DTOEIEN

#define USDHC_INT_SIGNAL_EN_DTOEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

DTOEIEN - Data Timeout Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45564 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DTOEIEN_MASK

#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)

Definition at line 45558 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)

Definition at line 45559 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_RTEIEN

#define USDHC_INT_SIGNAL_EN_RTEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

RTEIEN - Re-Tuning Event Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45522 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_RTEIEN_MASK

#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)

Definition at line 45516 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)

Definition at line 45517 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TCIEN

#define USDHC_INT_SIGNAL_EN_TCIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

TCIEN - Transfer Complete Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45466 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TCIEN_MASK

#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)

Definition at line 45460 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TCIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)

Definition at line 45461 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TNEIEN

#define USDHC_INT_SIGNAL_EN_TNEIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

TNEIEN - Tuning Error Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45592 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TNEIEN_MASK

#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)

Definition at line 45586 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)

Definition at line 45587 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TPIEN

#define USDHC_INT_SIGNAL_EN_TPIEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

TPIEN - Tuning Pass Interrupt Enable 0b1..Enabled 0b0..Masked

Definition at line 45529 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TPIEN_MASK

#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)

Definition at line 45523 of file MIMXRT1062.h.

## ◆ USDHC_INT_SIGNAL_EN_TPIEN_SHIFT

#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)

Definition at line 45524 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_AC12E

#define USDHC_INT_STATUS_AC12E | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

AC12E - Auto CMD12 Error 0b1..Error 0b0..No Error

Definition at line 45285 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_AC12E_MASK

#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)

Definition at line 45279 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_AC12E_SHIFT

#define USDHC_INT_STATUS_AC12E_SHIFT (24U)

Definition at line 45280 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BGE

#define USDHC_INT_STATUS_BGE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

BGE - Block Gap Event 0b1..Transaction stopped at block gap 0b0..No block gap event

Definition at line 45175 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BGE_MASK

#define USDHC_INT_STATUS_BGE_MASK (0x4U)

Definition at line 45169 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BGE_SHIFT

#define USDHC_INT_STATUS_BGE_SHIFT (2U)

Definition at line 45170 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BRR

#define USDHC_INT_STATUS_BRR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

BRR - Buffer Read Ready 0b1..Ready to read buffer 0b0..Not ready to read buffer

Definition at line 45196 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BRR_MASK

#define USDHC_INT_STATUS_BRR_MASK (0x20U)

Definition at line 45190 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BRR_SHIFT

#define USDHC_INT_STATUS_BRR_SHIFT (5U)

Definition at line 45191 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BWR

#define USDHC_INT_STATUS_BWR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

BWR - Buffer Write Ready 0b1..Ready to write buffer: 0b0..Not ready to write buffer

Definition at line 45189 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BWR_MASK

#define USDHC_INT_STATUS_BWR_MASK (0x10U)

Definition at line 45183 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_BWR_SHIFT

#define USDHC_INT_STATUS_BWR_SHIFT (4U)

Definition at line 45184 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CC

#define USDHC_INT_STATUS_CC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

CC - Command Complete 0b1..Command complete 0b0..Command not complete

Definition at line 45161 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CC_MASK

#define USDHC_INT_STATUS_CC_MASK (0x1U)

Definition at line 45155 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CC_SHIFT

#define USDHC_INT_STATUS_CC_SHIFT (0U)

Definition at line 45156 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CCE

#define USDHC_INT_STATUS_CCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

CCE - Command CRC Error 0b1..CRC Error Generated. 0b0..No Error

Definition at line 45243 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CCE_MASK

#define USDHC_INT_STATUS_CCE_MASK (0x20000U)

Definition at line 45237 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CCE_SHIFT

#define USDHC_INT_STATUS_CCE_SHIFT (17U)

Definition at line 45238 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CEBE

#define USDHC_INT_STATUS_CEBE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

CEBE - Command End Bit Error 0b1..End Bit Error Generated 0b0..No Error

Definition at line 45250 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CEBE_MASK

#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)

Definition at line 45244 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CEBE_SHIFT

#define USDHC_INT_STATUS_CEBE_SHIFT (18U)

Definition at line 45245 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CIE

#define USDHC_INT_STATUS_CIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

CIE - Command Index Error 0b1..Error 0b0..No Error

Definition at line 45257 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CIE_MASK

#define USDHC_INT_STATUS_CIE_MASK (0x80000U)

Definition at line 45251 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CIE_SHIFT

#define USDHC_INT_STATUS_CIE_SHIFT (19U)

Definition at line 45252 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CINS

#define USDHC_INT_STATUS_CINS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

CINS - Card Insertion 0b1..Card inserted 0b0..Card state unstable or removed

Definition at line 45203 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CINS_MASK

#define USDHC_INT_STATUS_CINS_MASK (0x40U)

Definition at line 45197 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CINS_SHIFT

#define USDHC_INT_STATUS_CINS_SHIFT (6U)

Definition at line 45198 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CINT

#define USDHC_INT_STATUS_CINT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

CINT - Card Interrupt 0b1..Generate Card Interrupt 0b0..No Card Interrupt

Definition at line 45217 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CINT_MASK

#define USDHC_INT_STATUS_CINT_MASK (0x100U)

Definition at line 45211 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CINT_SHIFT

#define USDHC_INT_STATUS_CINT_SHIFT (8U)

Definition at line 45212 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CRM

#define USDHC_INT_STATUS_CRM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

CRM - Card Removal 0b1..Card removed 0b0..Card state unstable or inserted

Definition at line 45210 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CRM_MASK

#define USDHC_INT_STATUS_CRM_MASK (0x80U)

Definition at line 45204 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CRM_SHIFT

#define USDHC_INT_STATUS_CRM_SHIFT (7U)

Definition at line 45205 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CTOE

#define USDHC_INT_STATUS_CTOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

CTOE - Command Timeout Error 0b1..Time out 0b0..No Error

Definition at line 45236 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CTOE_MASK

#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)

Definition at line 45230 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_CTOE_SHIFT

#define USDHC_INT_STATUS_CTOE_SHIFT (16U)

Definition at line 45231 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DCE

#define USDHC_INT_STATUS_DCE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

DCE - Data CRC Error 0b1..Error 0b0..No Error

Definition at line 45271 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DCE_MASK

#define USDHC_INT_STATUS_DCE_MASK (0x200000U)

Definition at line 45265 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DCE_SHIFT

#define USDHC_INT_STATUS_DCE_SHIFT (21U)

Definition at line 45266 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DEBE

#define USDHC_INT_STATUS_DEBE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

DEBE - Data End Bit Error 0b1..Error 0b0..No Error

Definition at line 45278 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DEBE_MASK

#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)

Definition at line 45272 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DEBE_SHIFT

#define USDHC_INT_STATUS_DEBE_SHIFT (22U)

Definition at line 45273 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DINT

#define USDHC_INT_STATUS_DINT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

DINT - DMA Interrupt 0b1..DMA Interrupt is generated 0b0..No DMA Interrupt

Definition at line 45182 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DINT_MASK

#define USDHC_INT_STATUS_DINT_MASK (0x8U)

Definition at line 45176 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DINT_SHIFT

#define USDHC_INT_STATUS_DINT_SHIFT (3U)

Definition at line 45177 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DMAE

#define USDHC_INT_STATUS_DMAE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)

DMAE - DMA Error 0b1..Error 0b0..No Error

Definition at line 45297 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DMAE_MASK

#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)

Definition at line 45291 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DMAE_SHIFT

#define USDHC_INT_STATUS_DMAE_SHIFT (28U)

Definition at line 45292 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DTOE

#define USDHC_INT_STATUS_DTOE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

DTOE - Data Timeout Error 0b1..Time out 0b0..No Error

Definition at line 45264 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DTOE_MASK

#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)

Definition at line 45258 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_DTOE_SHIFT

#define USDHC_INT_STATUS_DTOE_SHIFT (20U)

Definition at line 45259 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_AC12ESEN

#define USDHC_INT_STATUS_EN_AC12ESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

AC12ESEN - Auto CMD12 Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45434 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_AC12ESEN_MASK

#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)

Definition at line 45428 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_AC12ESEN_SHIFT

#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)

Definition at line 45429 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BGESEN

#define USDHC_INT_STATUS_EN_BGESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

BGESEN - Block Gap Event Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45322 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BGESEN_MASK

#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)

Definition at line 45316 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BGESEN_SHIFT

#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)

Definition at line 45317 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BRRSEN

#define USDHC_INT_STATUS_EN_BRRSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

BRRSEN - Buffer Read Ready Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45343 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BRRSEN_MASK

#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)

Definition at line 45337 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BRRSEN_SHIFT

#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)

Definition at line 45338 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BWRSEN

#define USDHC_INT_STATUS_EN_BWRSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

BWRSEN - Buffer Write Ready Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45336 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BWRSEN_MASK

#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)

Definition at line 45330 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_BWRSEN_SHIFT

#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)

Definition at line 45331 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CCESEN

#define USDHC_INT_STATUS_EN_CCESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

CCESEN - Command CRC Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45392 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CCESEN_MASK

#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)

Definition at line 45386 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CCESEN_SHIFT

#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)

Definition at line 45387 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CCSEN

#define USDHC_INT_STATUS_EN_CCSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

CCSEN - Command Complete Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45308 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CCSEN_MASK

#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)

Definition at line 45302 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CCSEN_SHIFT

#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)

Definition at line 45303 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CEBESEN

#define USDHC_INT_STATUS_EN_CEBESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

CEBESEN - Command End Bit Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45399 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CEBESEN_MASK

#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)

Definition at line 45393 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CEBESEN_SHIFT

#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)

Definition at line 45394 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CIESEN

#define USDHC_INT_STATUS_EN_CIESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

CIESEN - Command Index Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45406 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CIESEN_MASK

#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)

Definition at line 45400 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CIESEN_SHIFT

#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)

Definition at line 45401 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CINSSEN

#define USDHC_INT_STATUS_EN_CINSSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

CINSSEN - Card Insertion Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45350 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CINSSEN_MASK

#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)

Definition at line 45344 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CINSSEN_SHIFT

#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)

Definition at line 45345 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CINTSEN

#define USDHC_INT_STATUS_EN_CINTSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

CINTSEN - Card Interrupt Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45364 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CINTSEN_MASK

#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)

Definition at line 45358 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CINTSEN_SHIFT

#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)

Definition at line 45359 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CRMSEN

#define USDHC_INT_STATUS_EN_CRMSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

CRMSEN - Card Removal Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45357 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CRMSEN_MASK

#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)

Definition at line 45351 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CRMSEN_SHIFT

#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)

Definition at line 45352 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CTOESEN

#define USDHC_INT_STATUS_EN_CTOESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

CTOESEN - Command Timeout Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45385 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CTOESEN_MASK

#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)

Definition at line 45379 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_CTOESEN_SHIFT

#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)

Definition at line 45380 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DCESEN

#define USDHC_INT_STATUS_EN_DCESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

DCESEN - Data CRC Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45420 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DCESEN_MASK

#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)

Definition at line 45414 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DCESEN_SHIFT

#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)

Definition at line 45415 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DEBESEN

#define USDHC_INT_STATUS_EN_DEBESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

DEBESEN - Data End Bit Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45427 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DEBESEN_MASK

#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)

Definition at line 45421 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DEBESEN_SHIFT

#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)

Definition at line 45422 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DINTSEN

#define USDHC_INT_STATUS_EN_DINTSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

DINTSEN - DMA Interrupt Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45329 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DINTSEN_MASK

#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)

Definition at line 45323 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DINTSEN_SHIFT

#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)

Definition at line 45324 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DMAESEN

#define USDHC_INT_STATUS_EN_DMAESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)

DMAESEN - DMA Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45448 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DMAESEN_MASK

#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)

Definition at line 45442 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DMAESEN_SHIFT

#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)

Definition at line 45443 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DTOESEN

#define USDHC_INT_STATUS_EN_DTOESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

DTOESEN - Data Timeout Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45413 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DTOESEN_MASK

#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)

Definition at line 45407 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_DTOESEN_SHIFT

#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)

Definition at line 45408 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_RTESEN

#define USDHC_INT_STATUS_EN_RTESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

RTESEN - Re-Tuning Event Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45371 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_RTESEN_MASK

#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)

Definition at line 45365 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_RTESEN_SHIFT

#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)

Definition at line 45366 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TCSEN

#define USDHC_INT_STATUS_EN_TCSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

TCSEN - Transfer Complete Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45315 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TCSEN_MASK

#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)

Definition at line 45309 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TCSEN_SHIFT

#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)

Definition at line 45310 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TNESEN

#define USDHC_INT_STATUS_EN_TNESEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

TNESEN - Tuning Error Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45441 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TNESEN_MASK

#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)

Definition at line 45435 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TNESEN_SHIFT

#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)

Definition at line 45436 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TPSEN

#define USDHC_INT_STATUS_EN_TPSEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

TPSEN - Tuning Pass Status Enable 0b1..Enabled 0b0..Masked

Definition at line 45378 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TPSEN_MASK

#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)

Definition at line 45372 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_EN_TPSEN_SHIFT

#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)

Definition at line 45373 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_RTE

#define USDHC_INT_STATUS_RTE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) 0b1..Re-Tuning should be performed 0b0..Re-Tuning is not required

Definition at line 45224 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_RTE_MASK

#define USDHC_INT_STATUS_RTE_MASK (0x1000U)

Definition at line 45218 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_RTE_SHIFT

#define USDHC_INT_STATUS_RTE_SHIFT (12U)

Definition at line 45219 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TC

#define USDHC_INT_STATUS_TC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

TC - Transfer Complete 0b1..Transfer complete 0b0..Transfer not complete

Definition at line 45168 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TC_MASK

#define USDHC_INT_STATUS_TC_MASK (0x2U)

Definition at line 45162 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TC_SHIFT

#define USDHC_INT_STATUS_TC_SHIFT (1U)

Definition at line 45163 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TNE

#define USDHC_INT_STATUS_TNE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

TNE - Tuning Error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)

Definition at line 45290 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TNE_MASK

#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)

Definition at line 45286 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TNE_SHIFT

#define USDHC_INT_STATUS_TNE_SHIFT (26U)

Definition at line 45287 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TP

#define USDHC_INT_STATUS_TP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

TP - Tuning Pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)

Definition at line 45229 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TP_MASK

#define USDHC_INT_STATUS_TP_MASK (0x4000U)

Definition at line 45225 of file MIMXRT1062.h.

## ◆ USDHC_INT_STATUS_TP_SHIFT

#define USDHC_INT_STATUS_TP_SHIFT (14U)

Definition at line 45226 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AC12EN

#define USDHC_MIX_CTRL_AC12EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

AC12EN - Auto CMD12 Enable 0b1..Enable 0b0..Disable

Definition at line 45804 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AC12EN_MASK

#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)

Definition at line 45798 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AC12EN_SHIFT

#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)

Definition at line 45799 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AC23EN

#define USDHC_MIX_CTRL_AC23EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

AC23EN - Auto CMD23 Enable

Definition at line 45833 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AC23EN_MASK

#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)

Definition at line 45829 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AC23EN_SHIFT

#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)

Definition at line 45830 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AUTO_TUNE_EN

#define USDHC_MIX_CTRL_AUTO_TUNE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) 0b1..Enable auto tuning 0b0..Disable auto tuning

Definition at line 45854 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK

#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)

Definition at line 45848 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT

#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)

Definition at line 45849 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_BCEN

#define USDHC_MIX_CTRL_BCEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

BCEN - Block Count Enable 0b1..Enable 0b0..Disable

Definition at line 45797 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_BCEN_MASK

#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)

Definition at line 45791 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_BCEN_SHIFT

#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)

Definition at line 45792 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DDR_EN

#define USDHC_MIX_CTRL_DDR_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

DDR_EN - Dual Data Rate mode selection

Definition at line 45809 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DDR_EN_MASK

#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)

Definition at line 45805 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DDR_EN_SHIFT

#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)

Definition at line 45806 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DMAEN

#define USDHC_MIX_CTRL_DMAEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

DMAEN - DMA Enable 0b1..Enable 0b0..Disable

Definition at line 45790 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DMAEN_MASK

#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)

Definition at line 45784 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DMAEN_SHIFT

#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)

Definition at line 45785 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DTDSEL

#define USDHC_MIX_CTRL_DTDSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

DTDSEL - Data Transfer Direction Select 0b1..Read (Card to Host) 0b0..Write (Host to Card)

Definition at line 45816 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DTDSEL_MASK

#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)

Definition at line 45810 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_DTDSEL_SHIFT

#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)

Definition at line 45811 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_EXE_TUNE

#define USDHC_MIX_CTRL_EXE_TUNE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 0b1..Execute Tuning 0b0..Not Tuned or Tuning Completed

Definition at line 45840 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_EXE_TUNE_MASK

#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)

Definition at line 45834 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_EXE_TUNE_SHIFT

#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)

Definition at line 45835 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_FBCLK_SEL

#define USDHC_MIX_CTRL_FBCLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 0b1..Feedback clock comes from the ipp_card_clk_out 0b0..Feedback clock comes from the loopback CLK

Definition at line 45861 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_FBCLK_SEL_MASK

#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)

Definition at line 45855 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_FBCLK_SEL_SHIFT

#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)

Definition at line 45856 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_MSBSEL

#define USDHC_MIX_CTRL_MSBSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

MSBSEL - Multi / Single Block Select 0b1..Multiple Blocks 0b0..Single Block

Definition at line 45823 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_MSBSEL_MASK

#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)

Definition at line 45817 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_MSBSEL_SHIFT

#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)

Definition at line 45818 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_NIBBLE_POS

#define USDHC_MIX_CTRL_NIBBLE_POS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

NIBBLE_POS - NIBBLE_POS

Definition at line 45828 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_NIBBLE_POS_MASK

#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)

Definition at line 45824 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_NIBBLE_POS_SHIFT

#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)

Definition at line 45825 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_SMP_CLK_SEL

#define USDHC_MIX_CTRL_SMP_CLK_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

SMP_CLK_SEL - SMP_CLK_SEL 0b1..Tuned clock is used to sample data / cmd 0b0..Fixed clock is used to sample data / cmd

Definition at line 45847 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_SMP_CLK_SEL_MASK

#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)

Definition at line 45841 of file MIMXRT1062.h.

## ◆ USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT

#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)

Definition at line 45842 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_AUTO_SABG_EN

#define USDHC_MMC_BOOT_AUTO_SABG_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

AUTO_SABG_EN - AUTO_SABG_EN

Definition at line 46195 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_AUTO_SABG_EN_MASK

#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)

Definition at line 46191 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT

#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)

Definition at line 46192 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_ACK

#define USDHC_MMC_BOOT_BOOT_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

BOOT_ACK - BOOT_ACK 0b0..No ack 0b1..Ack

Definition at line 46176 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_ACK_MASK

#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)

Definition at line 46170 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_ACK_SHIFT

#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)

Definition at line 46171 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_BLK_CNT

#define USDHC_MMC_BOOT_BOOT_BLK_CNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)

BOOT_BLK_CNT - BOOT_BLK_CNT

Definition at line 46207 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK

#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)

Definition at line 46203 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT

#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)

Definition at line 46204 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_EN

#define USDHC_MMC_BOOT_BOOT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

BOOT_EN - BOOT_EN 0b0..Fast boot disable 0b1..Fast boot enable

Definition at line 46190 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_EN_MASK

#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)

Definition at line 46184 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_EN_SHIFT

#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)

Definition at line 46185 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_MODE

#define USDHC_MMC_BOOT_BOOT_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

BOOT_MODE - BOOT_MODE 0b0..Normal boot 0b1..Alternative boot

Definition at line 46183 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_MODE_MASK

#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)

Definition at line 46177 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_BOOT_MODE_SHIFT

#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)

Definition at line 46178 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_DISABLE_TIME_OUT

#define USDHC_MMC_BOOT_DISABLE_TIME_OUT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

DISABLE_TIME_OUT - Disable Time Out 0b0..Enable time out 0b1..Disable time out

Definition at line 46202 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK

#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)

Definition at line 46196 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT

#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)

Definition at line 46197 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_DTOCV_ACK

#define USDHC_MMC_BOOT_DTOCV_ACK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

DTOCV_ACK - DTOCV_ACK 0b0000..SDCLK x 2^14 0b0001..SDCLK x 2^15 0b0010..SDCLK x 2^16 0b0011..SDCLK x 2^17 0b0100..SDCLK x 2^18 0b0101..SDCLK x 2^19 0b0110..SDCLK x 2^20 0b0111..SDCLK x 2^21 0b1110..SDCLK x 2^28 0b1111..SDCLK x 2^29

Definition at line 46169 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_DTOCV_ACK_MASK

#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)

Definition at line 46155 of file MIMXRT1062.h.

## ◆ USDHC_MMC_BOOT_DTOCV_ACK_SHIFT

#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)

Definition at line 46156 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_BREN

#define USDHC_PRES_STATE_BREN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

BREN - Buffer Read Enable 0b1..Read enable 0b0..Read disable

Definition at line 44905 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_BREN_MASK

#define USDHC_PRES_STATE_BREN_MASK (0x800U)

Definition at line 44899 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_BREN_SHIFT

#define USDHC_PRES_STATE_BREN_SHIFT (11U)

Definition at line 44900 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_BWEN

#define USDHC_PRES_STATE_BWEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

BWEN - Buffer Write Enable 0b1..Write enable 0b0..Write disable

Definition at line 44898 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_BWEN_MASK

#define USDHC_PRES_STATE_BWEN_MASK (0x400U)

Definition at line 44892 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_BWEN_SHIFT

#define USDHC_PRES_STATE_BWEN_SHIFT (10U)

Definition at line 44893 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CDIHB

#define USDHC_PRES_STATE_CDIHB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

CDIHB - Command Inhibit (DATA) 0b1..Cannot issue command which uses the DATA line 0b0..Can issue command which uses the DATA line

Definition at line 44835 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CDIHB_MASK

#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)

Definition at line 44829 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CDIHB_SHIFT

#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)

Definition at line 44830 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CDPL

#define USDHC_PRES_STATE_CDPL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

CDPL - Card Detect Pin Level 0b1..Card present (CD_B = 0) 0b0..No card present (CD_B = 1)

Definition at line 44933 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CDPL_MASK

#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)

Definition at line 44927 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CDPL_SHIFT

#define USDHC_PRES_STATE_CDPL_SHIFT (18U)

Definition at line 44928 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CIHB

#define USDHC_PRES_STATE_CIHB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

CIHB - Command Inhibit (CMD) 0b1..Cannot issue command 0b0..Can issue command using only CMD line

Definition at line 44828 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CIHB_MASK

#define USDHC_PRES_STATE_CIHB_MASK (0x1U)

Definition at line 44822 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CIHB_SHIFT

#define USDHC_PRES_STATE_CIHB_SHIFT (0U)

Definition at line 44823 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CINST

#define USDHC_PRES_STATE_CINST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

CINST - Card Inserted 0b1..Card Inserted 0b0..Power on Reset or No Card

Definition at line 44926 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CINST_MASK

#define USDHC_PRES_STATE_CINST_MASK (0x10000U)

Definition at line 44920 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CINST_SHIFT

#define USDHC_PRES_STATE_CINST_SHIFT (16U)

Definition at line 44921 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CLSL

#define USDHC_PRES_STATE_CLSL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

CLSL - CMD Line Signal Level

Definition at line 44945 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CLSL_MASK

#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)

Definition at line 44941 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_CLSL_SHIFT

#define USDHC_PRES_STATE_CLSL_SHIFT (23U)

Definition at line 44942 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_DLA

#define USDHC_PRES_STATE_DLA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

DLA - Data Line Active 0b1..DATA Line Active 0b0..DATA Line Inactive

Definition at line 44842 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_DLA_MASK

#define USDHC_PRES_STATE_DLA_MASK (0x4U)

Definition at line 44836 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_DLA_SHIFT

#define USDHC_PRES_STATE_DLA_SHIFT (2U)

Definition at line 44837 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_DLSL

#define USDHC_PRES_STATE_DLSL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)

DLSL - DATA[7:0] Line Signal Level 0b00000111..Data 7 line signal level 0b00000110..Data 6 line signal level 0b00000101..Data 5 line signal level 0b00000100..Data 4 line signal level 0b00000011..Data 3 line signal level 0b00000010..Data 2 line signal level 0b00000001..Data 1 line signal level 0b00000000..Data 0 line signal level

Definition at line 44958 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_DLSL_MASK

#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)

Definition at line 44946 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_DLSL_SHIFT

#define USDHC_PRES_STATE_DLSL_SHIFT (24U)

Definition at line 44947 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_HCKOFF

#define USDHC_PRES_STATE_HCKOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)

HCKOFF - HCLK Gated Off Internally 0b1..HCLK is gated off. 0b0..HCLK is active.

Definition at line 44863 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_HCKOFF_MASK

#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)

Definition at line 44857 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_HCKOFF_SHIFT

#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)

Definition at line 44858 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_IPGOFF

#define USDHC_PRES_STATE_IPGOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)

IPGOFF - IPG_CLK Gated Off Internally 0b1..IPG_CLK is gated off. 0b0..IPG_CLK is active.

Definition at line 44856 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_IPGOFF_MASK

#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)

Definition at line 44850 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_IPGOFF_SHIFT

#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)

Definition at line 44851 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_PEROFF

#define USDHC_PRES_STATE_PEROFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)

PEROFF - IPG_PERCLK Gated Off Internally 0b1..IPG_PERCLK is gated off. 0b0..IPG_PERCLK is active.

Definition at line 44870 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_PEROFF_MASK

#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)

Definition at line 44864 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_PEROFF_SHIFT

#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)

Definition at line 44865 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_RTA

#define USDHC_PRES_STATE_RTA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

RTA - Read Transfer Active 0b1..Transferring data 0b0..No valid data

Definition at line 44891 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_RTA_MASK

#define USDHC_PRES_STATE_RTA_MASK (0x200U)

Definition at line 44885 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_RTA_SHIFT

#define USDHC_PRES_STATE_RTA_SHIFT (9U)

Definition at line 44886 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_RTR

#define USDHC_PRES_STATE_RTR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) 0b1..Sampling clock needs re-tuning 0b0..Fixed or well tuned sampling clock

Definition at line 44912 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_RTR_MASK

#define USDHC_PRES_STATE_RTR_MASK (0x1000U)

Definition at line 44906 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_RTR_SHIFT

#define USDHC_PRES_STATE_RTR_SHIFT (12U)

Definition at line 44907 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_SDOFF

#define USDHC_PRES_STATE_SDOFF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)

SDOFF - SD Clock Gated Off Internally 0b1..SD Clock is gated off. 0b0..SD Clock is active.

Definition at line 44877 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_SDOFF_MASK

#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)

Definition at line 44871 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_SDOFF_SHIFT

#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)

Definition at line 44872 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_SDSTB

#define USDHC_PRES_STATE_SDSTB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

SDSTB - SD Clock Stable 0b1..Clock is stable. 0b0..Clock is changing frequency and not stable.

Definition at line 44849 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_SDSTB_MASK

#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)

Definition at line 44843 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_SDSTB_SHIFT

#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)

Definition at line 44844 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_TSCD

#define USDHC_PRES_STATE_TSCD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

TSCD - Tape Select Change Done 0b1..Delay cell select change is finished. 0b0..Delay cell select change is not finished.

Definition at line 44919 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_TSCD_MASK

#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)

Definition at line 44913 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_TSCD_SHIFT

#define USDHC_PRES_STATE_TSCD_SHIFT (15U)

Definition at line 44914 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_WPSPL

#define USDHC_PRES_STATE_WPSPL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

WPSPL - Write Protect Switch Pin Level 0b1..Write enabled (WP = 0) 0b0..Write protected (WP = 1)

Definition at line 44940 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_WPSPL_MASK

#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)

Definition at line 44934 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_WPSPL_SHIFT

#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)

Definition at line 44935 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_WTA

#define USDHC_PRES_STATE_WTA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

WTA - Write Transfer Active 0b1..Transferring data 0b0..No valid data

Definition at line 44884 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_WTA_MASK

#define USDHC_PRES_STATE_WTA_MASK (0x100U)

Definition at line 44878 of file MIMXRT1062.h.

## ◆ USDHC_PRES_STATE_WTA_SHIFT

#define USDHC_PRES_STATE_WTA_SHIFT (8U)

Definition at line 44879 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_BURST_LEN_EN

#define USDHC_PROT_CTRL_BURST_LEN_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)

BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP 0bxx1..Burst length is enabled for INCR 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP

Definition at line 45079 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_BURST_LEN_EN_MASK

#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)

Definition at line 45072 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT

#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)

Definition at line 45073 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CDSS

#define USDHC_PROT_CTRL_CDSS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)

CDSS - Card Detect Signal Selection 0b1..Card Detection Test Level is selected (for test purpose). 0b0..Card Detection Level is selected (for normal purpose).

Definition at line 45008 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CDSS_MASK

#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)

Definition at line 45002 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CDSS_SHIFT

#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)

Definition at line 45003 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CDTL

#define USDHC_PROT_CTRL_CDTL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)

CDTL - Card Detect Test Level 0b1..Card Detect Test Level is 1, card inserted 0b0..Card Detect Test Level is 0, no card inserted

Definition at line 45001 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CDTL_MASK

#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)

Definition at line 44995 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CDTL_SHIFT

#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)

Definition at line 44996 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CREQ

#define USDHC_PROT_CTRL_CREQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

CREQ - Continue Request 0b1..Restart 0b0..No effect

Definition at line 45031 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CREQ_MASK

#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)

Definition at line 45025 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_CREQ_SHIFT

#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)

Definition at line 45026 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_D3CD

#define USDHC_PROT_CTRL_D3CD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

D3CD - DATA3 as Card Detection Pin 0b1..DATA3 as Card Detection Pin 0b0..DATA3 does not monitor Card Insertion

Definition at line 44985 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_D3CD_MASK

#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)

Definition at line 44979 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_D3CD_SHIFT

#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)

Definition at line 44980 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_DMASEL

#define USDHC_PROT_CTRL_DMASEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

DMASEL - DMA Select 0b00..No DMA or Simple DMA is selected 0b01..ADMA1 is selected 0b10..ADMA2 is selected 0b11..reserved

Definition at line 45017 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_DMASEL_MASK

#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)

Definition at line 45009 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_DMASEL_SHIFT

#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)

Definition at line 45010 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_DTW

#define USDHC_PROT_CTRL_DTW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

DTW - Data Transfer Width 0b10..8-bit mode 0b01..4-bit mode 0b00..1-bit mode 0b11..Reserved

Definition at line 44978 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_DTW_MASK

#define USDHC_PROT_CTRL_DTW_MASK (0x6U)

Definition at line 44970 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_DTW_SHIFT

#define USDHC_PROT_CTRL_DTW_SHIFT (1U)

Definition at line 44971 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_EMODE

#define USDHC_PROT_CTRL_EMODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

EMODE - Endian Mode 0b00..Big Endian Mode 0b01..Half Word Big Endian Mode 0b10..Little Endian Mode 0b11..Reserved

Definition at line 44994 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_EMODE_MASK

#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)

Definition at line 44986 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_EMODE_SHIFT

#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)

Definition at line 44987 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_IABG

#define USDHC_PROT_CTRL_IABG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

IABG - Interrupt At Block Gap 0b1..Enabled 0b0..Disabled

Definition at line 45045 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_IABG_MASK

#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)

Definition at line 45039 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_IABG_SHIFT

#define USDHC_PROT_CTRL_IABG_SHIFT (19U)

Definition at line 45040 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_LCTL

#define USDHC_PROT_CTRL_LCTL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)

LCTL - LED Control 0b1..LED on 0b0..LED off

Definition at line 44969 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_LCTL_MASK

#define USDHC_PROT_CTRL_LCTL_MASK (0x1U)

Definition at line 44963 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_LCTL_SHIFT

#define USDHC_PROT_CTRL_LCTL_SHIFT (0U)

Definition at line 44964 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_NON_EXACT_BLK_RD

#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)

NON_EXACT_BLK_RD - NON_EXACT_BLK_RD 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.

Definition at line 45086 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK

#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)

Definition at line 45080 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT

#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)

Definition at line 45081 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_RD_DONE_NO_8CLK

#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

RD_DONE_NO_8CLK - RD_DONE_NO_8CLK

Definition at line 45050 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK

#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)

Definition at line 45046 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT

#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)

Definition at line 45047 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_RWCTL

#define USDHC_PROT_CTRL_RWCTL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

RWCTL - Read Wait Control 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set

Definition at line 45038 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_RWCTL_MASK

#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)

Definition at line 45032 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_RWCTL_SHIFT

#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)

Definition at line 45033 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_SABGREQ

#define USDHC_PROT_CTRL_SABGREQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

SABGREQ - Stop At Block Gap Request 0b1..Stop 0b0..Transfer

Definition at line 45024 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_SABGREQ_MASK

#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)

Definition at line 45018 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_SABGREQ_SHIFT

#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)

Definition at line 45019 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECINS

#define USDHC_PROT_CTRL_WECINS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

WECINS - Wakeup Event Enable On SD Card Insertion 0b1..Enable 0b0..Disable

Definition at line 45064 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECINS_MASK

#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)

Definition at line 45058 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECINS_SHIFT

#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)

Definition at line 45059 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECINT

#define USDHC_PROT_CTRL_WECINT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

WECINT - Wakeup Event Enable On Card Interrupt 0b1..Enable 0b0..Disable

Definition at line 45057 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECINT_MASK

#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)

Definition at line 45051 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECINT_SHIFT

#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)

Definition at line 45052 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECRM

#define USDHC_PROT_CTRL_WECRM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

WECRM - Wakeup Event Enable On SD Card Removal 0b1..Enable 0b0..Disable

Definition at line 45071 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECRM_MASK

#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)

Definition at line 45065 of file MIMXRT1062.h.

## ◆ USDHC_PROT_CTRL_WECRM_SHIFT

#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)

Definition at line 45066 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_DTOCV

#define USDHC_SYS_CTRL_DTOCV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

DTOCV - Data Timeout Counter Value 0b1111..SDCLK x 2 29 0b1110..SDCLK x 2 28 0b1101..SDCLK x 2 27 0b0001..SDCLK x 2 15 0b0000..SDCLK x 2 14

Definition at line 45114 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_DTOCV_MASK

#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)

Definition at line 45105 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_DTOCV_SHIFT

#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)

Definition at line 45106 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_DVS

#define USDHC_SYS_CTRL_DVS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

DVS - Divisor 0b0000..Divide-by-1 0b0001..Divide-by-2 0b1110..Divide-by-15 0b1111..Divide-by-16

Definition at line 45099 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_DVS_MASK

#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)

Definition at line 45091 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_DVS_SHIFT

#define USDHC_SYS_CTRL_DVS_SHIFT (4U)

Definition at line 45092 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_INITA

#define USDHC_SYS_CTRL_INITA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

INITA - Initialization Active

Definition at line 45145 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_INITA_MASK

#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)

Definition at line 45141 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_INITA_SHIFT

#define USDHC_SYS_CTRL_INITA_SHIFT (27U)

Definition at line 45142 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_IPP_RST_N

#define USDHC_SYS_CTRL_IPP_RST_N | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

IPP_RST_N - IPP_RST_N

Definition at line 45119 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_IPP_RST_N_MASK

#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)

Definition at line 45115 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_IPP_RST_N_SHIFT

#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)

Definition at line 45116 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTA

#define USDHC_SYS_CTRL_RSTA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

RSTA - Software Reset For ALL 0b1..Reset 0b0..No Reset

Definition at line 45126 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTA_MASK

#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)

Definition at line 45120 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTA_SHIFT

#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)

Definition at line 45121 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTC

#define USDHC_SYS_CTRL_RSTC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

RSTC - Software Reset For CMD Line 0b1..Reset 0b0..No Reset

Definition at line 45133 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTC_MASK

#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)

Definition at line 45127 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTC_SHIFT

#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)

Definition at line 45128 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTD

#define USDHC_SYS_CTRL_RSTD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

RSTD - Software Reset For DATA Line 0b1..Reset 0b0..No Reset

Definition at line 45140 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTD_MASK

#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)

Definition at line 45134 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTD_SHIFT

#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)

Definition at line 45135 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTT

#define USDHC_SYS_CTRL_RSTT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)

RSTT - Reset Tuning

Definition at line 45150 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTT_MASK

#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)

Definition at line 45146 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_RSTT_SHIFT

#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)

Definition at line 45147 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_SDCLKFS

#define USDHC_SYS_CTRL_SDCLKFS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

SDCLKFS - SDCLK Frequency Select

Definition at line 45104 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_SDCLKFS_MASK

#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)

Definition at line 45100 of file MIMXRT1062.h.

## ◆ USDHC_SYS_CTRL_SDCLKFS_SHIFT

#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)

Definition at line 45101 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_STD_TUNING_EN

#define USDHC_TUNING_CTRL_STD_TUNING_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)

STD_TUNING_EN - STD_TUNING_EN

Definition at line 46281 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_STD_TUNING_EN_MASK

#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)

Definition at line 46277 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT

#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)

Definition at line 46278 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_COUNTER

#define USDHC_TUNING_CTRL_TUNING_COUNTER | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

TUNING_COUNTER - TUNING_COUNTER

Definition at line 46266 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_COUNTER_MASK

#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)

Definition at line 46262 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT

#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)

Definition at line 46263 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_START_TAP

#define USDHC_TUNING_CTRL_TUNING_START_TAP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

TUNING_START_TAP - TUNING_START_TAP

Definition at line 46261 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_START_TAP_MASK

#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)

Definition at line 46257 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT

#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)

Definition at line 46258 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_STEP

#define USDHC_TUNING_CTRL_TUNING_STEP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

TUNING_STEP - TUNING_STEP

Definition at line 46271 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_STEP_MASK

#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)

Definition at line 46267 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_STEP_SHIFT

#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)

Definition at line 46268 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_WINDOW

#define USDHC_TUNING_CTRL_TUNING_WINDOW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

TUNING_WINDOW - TUNING_WINDOW

Definition at line 46276 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_WINDOW_MASK

#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)

Definition at line 46272 of file MIMXRT1062.h.

## ◆ USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT

#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)

Definition at line 46273 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_ACMD23_ARGU2_EN

#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. 0b0..Disable

Definition at line 46242 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK

#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)

Definition at line 46236 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT

#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)

Definition at line 46237 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_BUS_RST

#define USDHC_VEND_SPEC2_BUS_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)

BUS_RST - BUS reset

Definition at line 46252 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_BUS_RST_MASK

#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U)

Definition at line 46248 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_BUS_RST_SHIFT

#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U)

Definition at line 46249 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_CARD_INT_D3_TEST

#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

CARD_INT_D3_TEST - Card Interrupt Detection Test 0b0..Check the card interrupt only when DATA3 is high. 0b1..Check the card interrupt by ignoring the status of DATA3.

Definition at line 46218 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK

#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)

Definition at line 46212 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT

#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)

Definition at line 46213 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_PART_DLL_DEBUG

#define USDHC_VEND_SPEC2_PART_DLL_DEBUG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)

PART_DLL_DEBUG - debug for part dll

Definition at line 46247 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK

#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U)

Definition at line 46243 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT

#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U)

Definition at line 46244 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_1bit_EN

#define USDHC_VEND_SPEC2_TUNING_1bit_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)

TUNING_1bit_EN - TUNING_1bit_EN

Definition at line 46228 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK

#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)

Definition at line 46224 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT

#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)

Definition at line 46225 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_8bit_EN

#define USDHC_VEND_SPEC2_TUNING_8bit_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)

TUNING_8bit_EN - TUNING_8bit_EN

Definition at line 46223 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK

#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)

Definition at line 46219 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT

#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)

Definition at line 46220 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_CMD_EN

#define USDHC_VEND_SPEC2_TUNING_CMD_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

TUNING_CMD_EN - TUNING_CMD_EN 0b0..Auto tuning circuit does not check the CMD line. 0b1..Auto tuning circuit checks the CMD line.

Definition at line 46235 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK

#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)

Definition at line 46229 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT

#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)

Definition at line 46230 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN

#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN 0b0..Do not check busy after auto CMD12 for write data packet 0b1..Check busy after auto CMD12 for write data packet

Definition at line 46129 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK

#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)

Definition at line 46123 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT

#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)

Definition at line 46124 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CMD_BYTE_EN

#define USDHC_VEND_SPEC_CMD_BYTE_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)

CMD_BYTE_EN - CMD_BYTE_EN 0b0..Disable 0b1..Enable

Definition at line 46150 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CMD_BYTE_EN_MASK

#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)

Definition at line 46144 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT

#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)

Definition at line 46145 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CONFLICT_CHK_EN

#define USDHC_VEND_SPEC_CONFLICT_CHK_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)

CONFLICT_CHK_EN - Conflict check enable. 0b0..Conflict check disable 0b1..Conflict check enable

Definition at line 46122 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK

#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)

Definition at line 46116 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT

#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)

Definition at line 46117 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CRC_CHK_DIS

#define USDHC_VEND_SPEC_CRC_CHK_DIS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

CRC_CHK_DIS - CRC Check Disable 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet

Definition at line 46143 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CRC_CHK_DIS_MASK

#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)

Definition at line 46137 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT

#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)

Definition at line 46138 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_FRC_SDCLK_ON

#define USDHC_VEND_SPEC_FRC_SDCLK_ON | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

FRC_SDCLK_ON - FRC_SDCLK_ON 0b0..CLK active or inactive is fully controlled by the hardware. 0b1..Force CLK active.

Definition at line 46136 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK

#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)

Definition at line 46130 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT

#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)

Definition at line 46131 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_VSELECT

#define USDHC_VEND_SPEC_VSELECT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

VSELECT - Voltage Selection 0b1..Change the voltage to low voltage range, around 1.8 V 0b0..Change the voltage to high voltage range, around 3.0 V

Definition at line 46115 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_VSELECT_MASK

#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)

Definition at line 46109 of file MIMXRT1062.h.

## ◆ USDHC_VEND_SPEC_VSELECT_SHIFT

#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)

Definition at line 46110 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_RD_BRST_LEN

#define USDHC_WTMK_LVL_RD_BRST_LEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)

RD_BRST_LEN - Read Burst Length Due to system restriction, the actual burst length may not exceed 16.

Definition at line 45769 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_RD_BRST_LEN_MASK

#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)

Definition at line 45765 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT

#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)

Definition at line 45766 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_RD_WML

#define USDHC_WTMK_LVL_RD_WML | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

RD_WML - Read Watermark Level

Definition at line 45764 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_RD_WML_MASK

#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)

Definition at line 45760 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_RD_WML_SHIFT

#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)

Definition at line 45761 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_WR_BRST_LEN

#define USDHC_WTMK_LVL_WR_BRST_LEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)

WR_BRST_LEN - Write Burst Length Due to system restriction, the actual burst length may not exceed 16.

Definition at line 45779 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_WR_BRST_LEN_MASK

#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)

Definition at line 45775 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT

#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)

Definition at line 45776 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_WR_WML

#define USDHC_WTMK_LVL_WR_WML | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)

WR_WML - Write Watermark Level

Definition at line 45774 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_WR_WML_MASK

#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)

Definition at line 45770 of file MIMXRT1062.h.

## ◆ USDHC_WTMK_LVL_WR_WML_SHIFT

#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)

Definition at line 45771 of file MIMXRT1062.h.