Callisto4Bootloader: GPIO Peripheral Access Layer

Callisto4Bootloader

Modules | Data Structures | Macros
GPIO Peripheral Access Layer
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer

## Modules

| GPIO Register Masks

## Data Structures

struct | GPIO_Type

## Macros

#define | GPIO1_BASE (0x401B8000u)
#define | GPIO1 ((GPIO_Type *)GPIO1_BASE)
#define | GPIO2_BASE (0x401BC000u)
#define | GPIO2 ((GPIO_Type *)GPIO2_BASE)
#define | GPIO3_BASE (0x401C0000u)
#define | GPIO3 ((GPIO_Type *)GPIO3_BASE)
#define | GPIO4_BASE (0x401C4000u)
#define | GPIO4 ((GPIO_Type *)GPIO4_BASE)
#define | GPIO5_BASE (0x400C0000u)
#define | GPIO5 ((GPIO_Type *)GPIO5_BASE)
#define | GPIO6_BASE (0x42000000u)
#define | GPIO6 ((GPIO_Type *)GPIO6_BASE)
#define | GPIO7_BASE (0x42004000u)
#define | GPIO7 ((GPIO_Type *)GPIO7_BASE)
#define | GPIO8_BASE (0x42008000u)
#define | GPIO8 ((GPIO_Type *)GPIO8_BASE)
#define | GPIO9_BASE (0x4200C000u)
#define | GPIO9 ((GPIO_Type *)GPIO9_BASE)
#define | GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE }
#define | GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 }
#define | GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
#define | GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }
#define | GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }

## Detailed Description

## Macro Definition Documentation

## ◆ GPIO1

#define GPIO1 ((GPIO_Type *)GPIO1_BASE)

Peripheral GPIO1 base pointer

Definition at line 20740 of file MIMXRT1062.h.

## ◆ GPIO1_BASE

#define GPIO1_BASE (0x401B8000u)

Peripheral GPIO1 base address

Definition at line 20738 of file MIMXRT1062.h.

## ◆ GPIO2

#define GPIO2 ((GPIO_Type *)GPIO2_BASE)

Peripheral GPIO2 base pointer

Definition at line 20744 of file MIMXRT1062.h.

## ◆ GPIO2_BASE

#define GPIO2_BASE (0x401BC000u)

Peripheral GPIO2 base address

Definition at line 20742 of file MIMXRT1062.h.

## ◆ GPIO3

#define GPIO3 ((GPIO_Type *)GPIO3_BASE)

Peripheral GPIO3 base pointer

Definition at line 20748 of file MIMXRT1062.h.

## ◆ GPIO3_BASE

#define GPIO3_BASE (0x401C0000u)

Peripheral GPIO3 base address

Definition at line 20746 of file MIMXRT1062.h.

## ◆ GPIO4

#define GPIO4 ((GPIO_Type *)GPIO4_BASE)

Peripheral GPIO4 base pointer

Definition at line 20752 of file MIMXRT1062.h.

## ◆ GPIO4_BASE

#define GPIO4_BASE (0x401C4000u)

Peripheral GPIO4 base address

Definition at line 20750 of file MIMXRT1062.h.

## ◆ GPIO5

#define GPIO5 ((GPIO_Type *)GPIO5_BASE)

Peripheral GPIO5 base pointer

Definition at line 20756 of file MIMXRT1062.h.

## ◆ GPIO5_BASE

#define GPIO5_BASE (0x400C0000u)

Peripheral GPIO5 base address

Definition at line 20754 of file MIMXRT1062.h.

## ◆ GPIO6

#define GPIO6 ((GPIO_Type *)GPIO6_BASE)

Peripheral GPIO6 base pointer

Definition at line 20760 of file MIMXRT1062.h.

## ◆ GPIO6_BASE

#define GPIO6_BASE (0x42000000u)

Peripheral GPIO6 base address

Definition at line 20758 of file MIMXRT1062.h.

## ◆ GPIO7

#define GPIO7 ((GPIO_Type *)GPIO7_BASE)

Peripheral GPIO7 base pointer

Definition at line 20764 of file MIMXRT1062.h.

## ◆ GPIO7_BASE

#define GPIO7_BASE (0x42004000u)

Peripheral GPIO7 base address

Definition at line 20762 of file MIMXRT1062.h.

## ◆ GPIO8

#define GPIO8 ((GPIO_Type *)GPIO8_BASE)

Peripheral GPIO8 base pointer

Definition at line 20768 of file MIMXRT1062.h.

## ◆ GPIO8_BASE

#define GPIO8_BASE (0x42008000u)

Peripheral GPIO8 base address

Definition at line 20766 of file MIMXRT1062.h.

## ◆ GPIO9

#define GPIO9 ((GPIO_Type *)GPIO9_BASE)

Peripheral GPIO9 base pointer

Definition at line 20772 of file MIMXRT1062.h.

## ◆ GPIO9_BASE

#define GPIO9_BASE (0x4200C000u)

Peripheral GPIO9 base address

Definition at line 20770 of file MIMXRT1062.h.

## ◆ GPIO_BASE_ADDRS

#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE }

Array initializer of GPIO peripheral base addresses

Definition at line 20774 of file MIMXRT1062.h.

## ◆ GPIO_BASE_PTRS

#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 }

Array initializer of GPIO peripheral base pointers

Definition at line 20776 of file MIMXRT1062.h.

## ◆ GPIO_COMBINED_HIGH_IRQS

#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }

Definition at line 20780 of file MIMXRT1062.h.

## ◆ GPIO_COMBINED_LOW_IRQS

#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }

Definition at line 20779 of file MIMXRT1062.h.

## ◆ GPIO_IRQS

#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

Interrupt vectors for the GPIO peripheral type

Definition at line 20778 of file MIMXRT1062.h.