Callisto4Bootloader: device/system_MIMXRT1062.c Source File

Callisto4Bootloader

system_MIMXRT1062.c
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1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1062CVJ5A
4 ** MIMXRT1062CVL5A
5 ** MIMXRT1062DVJ6A
6 ** MIMXRT1062DVL6A
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
15 ** Version: rev. 1.2, 2019-04-29
16 ** Build: b191113
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2019 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 0.1 (2017-01-10)
34 ** Initial version.
35 ** - rev. 1.0 (2018-11-16)
36 ** Update header files to align with IMXRT1060RM Rev.0.
37 ** - rev. 1.1 (2018-11-27)
38 ** Update header files to align with IMXRT1060RM Rev.1.
39 ** - rev. 1.2 (2019-04-29)
40 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
41 **
42 ** ###################################################################
43 */
44
56 #include <stdint.h>
57 #include "fsl_device_registers.h"
58
59
60
61 /* ----------------------------------------------------------------------------
62 -- Core clock
63 ---------------------------------------------------------------------------- */
64
65 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
66
67 /* ----------------------------------------------------------------------------
68 -- SystemInit()
69 ---------------------------------------------------------------------------- */
70
71 void SystemInit (void) {
72 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
73 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
74 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
75
76 #if defined(__MCUXPRESSO)
77 extern void (* const g_pfnVectors[])(void); // Vector table defined in startup code
78 SCB->VTOR = (uint32_t)(void *)g_pfnVectors;
79 #endif
80
81 /* Disable Watchdog Power Down Counter */
82 WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
83 WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
84
85 /* Watchdog disable */
86
87 #if (DISABLE_WDOG)
88 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
89 {
90 WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
91 }
92 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
93 {
94 WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
95 }
96 if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
97 {
98 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
99 }
100 else
101 {
102 RTWDOG->CNT = 0xC520U;
103 RTWDOG->CNT = 0xD928U;
104 }
105 RTWDOG->TOVAL = 0xFFFF;
106 RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
107 #endif /* (DISABLE_WDOG) */
108
109 /* Disable Systick which might be enabled by bootrom */
110 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
111 {
112 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
113 }
114
115 /* Enable instruction and data caches */
116 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
117 if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
118 SCB_EnableICache();
119 }
120 #endif
121 #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
122 if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
123 SCB_EnableDCache();
124 }
125 #endif
126
127 SystemInitHook();
128 }
129
130 /* ----------------------------------------------------------------------------
131 -- SystemCoreClockUpdate()
132 ---------------------------------------------------------------------------- */
133
134 void SystemCoreClockUpdate (void) {
135
136 uint32_t freq;
137 uint32_t PLL1MainClock;
138 uint32_t PLL2MainClock;
139
140 /* Periph_clk2_clk ---> Periph_clk */
141 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
142 {
143 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
144 {
145 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
146 case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
147 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
148 {
149 freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
150 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
151 }
152 else
153 {
154 freq = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
155 }
156 break;
157
158 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
159 case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
160 freq = CPU_XTAL_CLK_HZ;
161 break;
162
163 case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
164 freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
165 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
166 break;
167
168 case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
169 default:
170 freq = 0U;
171 break;
172 }
173
174 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
175 }
176 /* Pre_Periph_clk ---> Periph_clk */
177 else
178 {
179 /* check if pll is bypassed */
180 if((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) != 0U)
181 {
182 PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
183 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
184 }
185 else
186 {
187 PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
188 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
189 }
190
191 /* check if pll is bypassed */
192 if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
193 {
194 PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
195 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
196 }
197 else
198 {
199 PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
200 }
201 PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
202
203
204 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
205 {
206 /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
207 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
208 freq = PLL2MainClock;
209 break;
210
211 /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
212 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
213 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
214 break;
215
216 /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
217 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
218 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
219 break;
220
221 /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
222 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
223 freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
224 break;
225
226 default:
227 freq = 0U;
228 break;
229 }
230 }
231
232 SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
233
234 }
235
236 /* ----------------------------------------------------------------------------
237 -- SystemInitHook()
238 ---------------------------------------------------------------------------- */
239
240 __attribute__ ((weak)) void SystemInitHook (void) {
241 /* Void implementation of the weak function. */
242 }
CCM_CBCDR_PERIPH_CLK2_PODF_MASK
#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK
Definition: MIMXRT1062.h:5470
SCB_EnableDCache
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: core_cm7.h:2288
CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
Definition: MIMXRT1062.h:5523
CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT
#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT
Definition: MIMXRT1062.h:7330
CCM_CBCDR_PERIPH_CLK_SEL_MASK
#define CCM_CBCDR_PERIPH_CLK_SEL_MASK
Definition: MIMXRT1062.h:5463
SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition: core_armv81mml.h:660
__attribute__
__attribute__((weak))
Definition: system_MIMXRT1062.c:240
CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK
Definition: MIMXRT1062.h:7338
CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT
#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT
Definition: MIMXRT1062.h:8501
CCM_ANALOG_PLL_ARM_BYPASS_MASK
#define CCM_ANALOG_PLL_ARM_BYPASS_MASK
Definition: MIMXRT1062.h:7347
CCM_CBCDR_AHB_PODF_SHIFT
#define CCM_CBCDR_AHB_PODF_SHIFT
Definition: MIMXRT1062.h:5438
CPU_CLK1_HZ
#define CPU_CLK1_HZ
Definition: system_MIMXRT1062.h:74
WDOG_WCR_WDE_MASK
#define WDOG_WCR_WDE_MASK
Definition: MIMXRT1062.h:46354
CCM_CBCDR_AHB_PODF_MASK
#define CCM_CBCDR_AHB_PODF_MASK
Definition: MIMXRT1062.h:5437
CCM_ANALOG_PFD_528_PFD0_FRAC_MASK
#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK
Definition: MIMXRT1062.h:8500
SysTick
#define SysTick
Definition: core_armv81mml.h:2044
SystemCoreClock
uint32_t SystemCoreClock
System clock frequency (core clock)
Definition: system_MIMXRT1062.c:65
CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK
#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK
Definition: MIMXRT1062.h:7453
CCM_CACRR_ARM_PODF_MASK
#define CCM_CACRR_ARM_PODF_MASK
Definition: MIMXRT1062.h:5397
fsl_device_registers.h
CCM_CBCMR_PRE_PERIPH_CLK_SEL
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x)
Definition: MIMXRT1062.h:5531
CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK
#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK
Definition: MIMXRT1062.h:7329
CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT
#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT
Definition: MIMXRT1062.h:7719
CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK
#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK
Definition: MIMXRT1062.h:7718
WDOG1
#define WDOG1
Definition: MIMXRT1062.h:46492
SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition: core_armv81mml.h:657
CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT
#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT
Definition: MIMXRT1062.h:5471
CCM_ANALOG
#define CCM_ANALOG
Definition: MIMXRT1062.h:9704
RTWDOG_CS_CMD32EN_MASK
#define RTWDOG_CS_CMD32EN_MASK
Definition: MIMXRT1062.h:36244
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock variable.
Definition: system_MIMXRT1062.c:134
CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT
#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT
Definition: MIMXRT1062.h:8519
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv81mml.h:1053
RTWDOG_CS_UPDATE_MASK
#define RTWDOG_CS_UPDATE_MASK
Definition: MIMXRT1062.h:36193
CCM
#define CCM
Definition: MIMXRT1062.h:7229
CCM_ANALOG_PLL_USB1_BYPASS_MASK
#define CCM_ANALOG_PLL_USB1_BYPASS_MASK
Definition: MIMXRT1062.h:7476
WDOG2
#define WDOG2
Definition: MIMXRT1062.h:46496
SystemInit
void SystemInit(void)
Setup the microcontroller system.
Definition: system_MIMXRT1062.c:71
RTWDOG_CS_EN_MASK
#define RTWDOG_CS_EN_MASK
Definition: MIMXRT1062.h:36207
CCM_CBCMR_PERIPH_CLK2_SEL_MASK
#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK
Definition: MIMXRT1062.h:5505
CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK
#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK
Definition: MIMXRT1062.h:7469
RTWDOG
#define RTWDOG
Definition: MIMXRT1062.h:36319
CCM_CBCMR_PERIPH_CLK2_SEL
#define CCM_CBCMR_PERIPH_CLK2_SEL(x)
Definition: MIMXRT1062.h:5513
CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT
#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT
Definition: MIMXRT1062.h:7470
CCM_ANALOG_PFD_528_PFD2_FRAC_MASK
#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK
Definition: MIMXRT1062.h:8518
SCB
#define SCB
Definition: core_armv81mml.h:2043
SystemInitHook
void SystemInitHook(void)
SystemInit function hook.
CCM_ANALOG_PLL_SYS_BYPASS_MASK
#define CCM_ANALOG_PLL_SYS_BYPASS_MASK
Definition: MIMXRT1062.h:7725
SCB_EnableICache
__STATIC_FORCEINLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: core_cm7.h:2234
CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT
Definition: MIMXRT1062.h:7339
CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK
#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK
Definition: MIMXRT1062.h:7709
DEFAULT_SYSTEM_CLOCK
#define DEFAULT_SYSTEM_CLOCK
Definition: system_MIMXRT1062.h:77
CCM_CACRR_ARM_PODF_SHIFT
#define CCM_CACRR_ARM_PODF_SHIFT
Definition: MIMXRT1062.h:5398
CPU_XTAL_CLK_HZ
#define CPU_XTAL_CLK_HZ
Definition: system_MIMXRT1062.h:72
WDOG_WMCR_PDE_MASK
#define WDOG_WMCR_PDE_MASK
Definition: MIMXRT1062.h:46473