Callisto4Bootloader: LPSPI_Type Struct Reference

Callisto4Bootloader

Data Fields
LPSPI_Type Struct Reference
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » LPSPI Peripheral Access Layer

`#include <MIMXRT1062.h>`

## Data Fields

__I uint32_t | VERID
__I uint32_t | PARAM
uint8_t | RESERVED_0 [8]
__IO uint32_t | CR
__IO uint32_t | SR
__IO uint32_t | IER
__IO uint32_t | DER
__IO uint32_t | CFGR0
__IO uint32_t | CFGR1
uint8_t | RESERVED_1 [8]
__IO uint32_t | DMR0
__IO uint32_t | DMR1
uint8_t | RESERVED_2 [8]
__IO uint32_t | CCR
uint8_t | RESERVED_3 [20]
__IO uint32_t | FCR
__I uint32_t | FSR
__IO uint32_t | TCR
__O uint32_t | TDR
uint8_t | RESERVED_4 [8]
__I uint32_t | RSR
__I uint32_t | RDR

## Detailed Description

LPSPI - Register Layout Typedef

Definition at line 27724 of file MIMXRT1062.h.

The documentation for this struct was generated from the following file:

- device/MIMXRT1062.h