Callisto4Bootloader: Floating Point Unit (FPU)

Callisto4Bootloader

Modules | Data Structures
Floating Point Unit (FPU)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI)

Type definitions for the Floating Point Unit (FPU) More...

## Modules

| Core Debug Registers (CoreDebug)
| Type definitions for the Core Debug Registers.

## Data Structures

struct | FPU_Type
| Structure type to access the Floating Point Unit (FPU). More...
#define | FPU_FPCCR_ASPEN_Pos 31U
#define | FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
#define | FPU_FPCCR_LSPEN_Pos 30U
#define | FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
#define | FPU_FPCCR_LSPENS_Pos 29U
#define | FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
#define | FPU_FPCCR_CLRONRET_Pos 28U
#define | FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
#define | FPU_FPCCR_CLRONRETS_Pos 27U
#define | FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
#define | FPU_FPCCR_TS_Pos 26U
#define | FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
#define | FPU_FPCCR_UFRDY_Pos 10U
#define | FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
#define | FPU_FPCCR_SPLIMVIOL_Pos 9U
#define | FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
#define | FPU_FPCCR_MONRDY_Pos 8U
#define | FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
#define | FPU_FPCCR_SFRDY_Pos 7U
#define | FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
#define | FPU_FPCCR_BFRDY_Pos 6U
#define | FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
#define | FPU_FPCCR_MMRDY_Pos 5U
#define | FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
#define | FPU_FPCCR_HFRDY_Pos 4U
#define | FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
#define | FPU_FPCCR_THREAD_Pos 3U
#define | FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
#define | FPU_FPCCR_S_Pos 2U
#define | FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
#define | FPU_FPCCR_USER_Pos 1U
#define | FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
#define | FPU_FPCCR_LSPACT_Pos 0U
#define | FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
#define | FPU_FPCAR_ADDRESS_Pos 3U
#define | FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
#define | FPU_FPDSCR_AHP_Pos 26U
#define | FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
#define | FPU_FPDSCR_DN_Pos 25U
#define | FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
#define | FPU_FPDSCR_FZ_Pos 24U
#define | FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
#define | FPU_FPDSCR_RMode_Pos 22U
#define | FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
#define | FPU_MVFR0_FP_rounding_modes_Pos 28U
#define | FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
#define | FPU_MVFR0_Short_vectors_Pos 24U
#define | FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
#define | FPU_MVFR0_Square_root_Pos 20U
#define | FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
#define | FPU_MVFR0_Divide_Pos 16U
#define | FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
#define | FPU_MVFR0_FP_excep_trapping_Pos 12U
#define | FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
#define | FPU_MVFR0_Double_precision_Pos 8U
#define | FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
#define | FPU_MVFR0_Single_precision_Pos 4U
#define | FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
#define | FPU_MVFR0_A_SIMD_registers_Pos 0U
#define | FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
#define | FPU_MVFR1_FP_fused_MAC_Pos 28U
#define | FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
#define | FPU_MVFR1_FP_HPFP_Pos 24U
#define | FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
#define | FPU_MVFR1_D_NaN_mode_Pos 4U
#define | FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
#define | FPU_MVFR1_FtZ_mode_Pos 0U
#define | FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
#define | FPU_FPCCR_ASPEN_Pos 31U
#define | FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
#define | FPU_FPCCR_LSPEN_Pos 30U
#define | FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
#define | FPU_FPCCR_LSPENS_Pos 29U
#define | FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
#define | FPU_FPCCR_CLRONRET_Pos 28U
#define | FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
#define | FPU_FPCCR_CLRONRETS_Pos 27U
#define | FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
#define | FPU_FPCCR_TS_Pos 26U
#define | FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
#define | FPU_FPCCR_UFRDY_Pos 10U
#define | FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
#define | FPU_FPCCR_SPLIMVIOL_Pos 9U
#define | FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
#define | FPU_FPCCR_MONRDY_Pos 8U
#define | FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
#define | FPU_FPCCR_SFRDY_Pos 7U
#define | FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
#define | FPU_FPCCR_BFRDY_Pos 6U
#define | FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
#define | FPU_FPCCR_MMRDY_Pos 5U
#define | FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
#define | FPU_FPCCR_HFRDY_Pos 4U
#define | FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
#define | FPU_FPCCR_THREAD_Pos 3U
#define | FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
#define | FPU_FPCCR_S_Pos 2U
#define | FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
#define | FPU_FPCCR_USER_Pos 1U
#define | FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
#define | FPU_FPCCR_LSPACT_Pos 0U
#define | FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
#define | FPU_FPCAR_ADDRESS_Pos 3U
#define | FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
#define | FPU_FPDSCR_AHP_Pos 26U
#define | FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
#define | FPU_FPDSCR_DN_Pos 25U
#define | FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
#define | FPU_FPDSCR_FZ_Pos 24U
#define | FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
#define | FPU_FPDSCR_RMode_Pos 22U
#define | FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
#define | FPU_MVFR0_FP_rounding_modes_Pos 28U
#define | FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
#define | FPU_MVFR0_Short_vectors_Pos 24U
#define | FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
#define | FPU_MVFR0_Square_root_Pos 20U
#define | FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
#define | FPU_MVFR0_Divide_Pos 16U
#define | FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
#define | FPU_MVFR0_FP_excep_trapping_Pos 12U
#define | FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
#define | FPU_MVFR0_Double_precision_Pos 8U
#define | FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
#define | FPU_MVFR0_Single_precision_Pos 4U
#define | FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
#define | FPU_MVFR0_A_SIMD_registers_Pos 0U
#define | FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
#define | FPU_MVFR1_FP_fused_MAC_Pos 28U
#define | FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
#define | FPU_MVFR1_FP_HPFP_Pos 24U
#define | FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
#define | FPU_MVFR1_D_NaN_mode_Pos 4U
#define | FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
#define | FPU_MVFR1_FtZ_mode_Pos 0U
#define | FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
#define | FPU_FPCCR_ASPEN_Pos 31U
#define | FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
#define | FPU_FPCCR_LSPEN_Pos 30U
#define | FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
#define | FPU_FPCCR_MONRDY_Pos 8U
#define | FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
#define | FPU_FPCCR_BFRDY_Pos 6U
#define | FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
#define | FPU_FPCCR_MMRDY_Pos 5U
#define | FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
#define | FPU_FPCCR_HFRDY_Pos 4U
#define | FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
#define | FPU_FPCCR_THREAD_Pos 3U
#define | FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
#define | FPU_FPCCR_USER_Pos 1U
#define | FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
#define | FPU_FPCCR_LSPACT_Pos 0U
#define | FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
#define | FPU_FPCAR_ADDRESS_Pos 3U
#define | FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
#define | FPU_FPDSCR_AHP_Pos 26U
#define | FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
#define | FPU_FPDSCR_DN_Pos 25U
#define | FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
#define | FPU_FPDSCR_FZ_Pos 24U
#define | FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
#define | FPU_FPDSCR_RMode_Pos 22U
#define | FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
#define | FPU_MVFR0_FP_rounding_modes_Pos 28U
#define | FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
#define | FPU_MVFR0_Short_vectors_Pos 24U
#define | FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
#define | FPU_MVFR0_Square_root_Pos 20U
#define | FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
#define | FPU_MVFR0_Divide_Pos 16U
#define | FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
#define | FPU_MVFR0_FP_excep_trapping_Pos 12U
#define | FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
#define | FPU_MVFR0_Double_precision_Pos 8U
#define | FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
#define | FPU_MVFR0_Single_precision_Pos 4U
#define | FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
#define | FPU_MVFR0_A_SIMD_registers_Pos 0U
#define | FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
#define | FPU_MVFR1_FP_fused_MAC_Pos 28U
#define | FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
#define | FPU_MVFR1_FP_HPFP_Pos 24U
#define | FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
#define | FPU_MVFR1_D_NaN_mode_Pos 4U
#define | FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
#define | FPU_MVFR1_FtZ_mode_Pos 0U
#define | FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
#define | FPU_MVFR2_VFP_Misc_Pos 4U
#define | FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

## Detailed Description

Type definitions for the Floating Point Unit (FPU)

## Macro Definition Documentation

## ◆ FPU_FPCAR_ADDRESS_Msk [1/3]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1566 of file core_cm7.h.

## ◆ FPU_FPCAR_ADDRESS_Msk [2/3]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1652 of file core_armv8mml.h.

## ◆ FPU_FPCAR_ADDRESS_Msk [3/3]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1809 of file core_armv81mml.h.

## ◆ FPU_FPCAR_ADDRESS_Pos [1/3]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1565 of file core_cm7.h.

## ◆ FPU_FPCAR_ADDRESS_Pos [2/3]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1651 of file core_armv8mml.h.

## ◆ FPU_FPCAR_ADDRESS_Pos [3/3]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1808 of file core_armv81mml.h.

## ◆ FPU_FPCCR_ASPEN_Msk [1/3]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1538 of file core_cm7.h.

## ◆ FPU_FPCCR_ASPEN_Msk [2/3]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1600 of file core_armv8mml.h.

## ◆ FPU_FPCCR_ASPEN_Msk [3/3]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1757 of file core_armv81mml.h.

## ◆ FPU_FPCCR_ASPEN_Pos [1/3]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1537 of file core_cm7.h.

## ◆ FPU_FPCCR_ASPEN_Pos [2/3]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1599 of file core_armv8mml.h.

## ◆ FPU_FPCCR_ASPEN_Pos [3/3]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1756 of file core_armv81mml.h.

## ◆ FPU_FPCCR_BFRDY_Msk [1/3]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1547 of file core_cm7.h.

## ◆ FPU_FPCCR_BFRDY_Msk [2/3]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1630 of file core_armv8mml.h.

## ◆ FPU_FPCCR_BFRDY_Msk [3/3]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1787 of file core_armv81mml.h.

## ◆ FPU_FPCCR_BFRDY_Pos [1/3]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1546 of file core_cm7.h.

## ◆ FPU_FPCCR_BFRDY_Pos [2/3]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1629 of file core_armv8mml.h.

## ◆ FPU_FPCCR_BFRDY_Pos [3/3]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1786 of file core_armv81mml.h.

## ◆ FPU_FPCCR_CLRONRET_Msk [1/2]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1609 of file core_armv8mml.h.

## ◆ FPU_FPCCR_CLRONRET_Msk [2/2]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1766 of file core_armv81mml.h.

## ◆ FPU_FPCCR_CLRONRET_Pos [1/2]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1608 of file core_armv8mml.h.

## ◆ FPU_FPCCR_CLRONRET_Pos [2/2]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1765 of file core_armv81mml.h.

## ◆ FPU_FPCCR_CLRONRETS_Msk [1/2]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1612 of file core_armv8mml.h.

## ◆ FPU_FPCCR_CLRONRETS_Msk [2/2]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1769 of file core_armv81mml.h.

## ◆ FPU_FPCCR_CLRONRETS_Pos [1/2]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1611 of file core_armv8mml.h.

## ◆ FPU_FPCCR_CLRONRETS_Pos [2/2]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1768 of file core_armv81mml.h.

## ◆ FPU_FPCCR_HFRDY_Msk [1/3]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1553 of file core_cm7.h.

## ◆ FPU_FPCCR_HFRDY_Msk [2/3]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1636 of file core_armv8mml.h.

## ◆ FPU_FPCCR_HFRDY_Msk [3/3]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1793 of file core_armv81mml.h.

## ◆ FPU_FPCCR_HFRDY_Pos [1/3]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1552 of file core_cm7.h.

## ◆ FPU_FPCCR_HFRDY_Pos [2/3]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1635 of file core_armv8mml.h.

## ◆ FPU_FPCCR_HFRDY_Pos [3/3]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1792 of file core_armv81mml.h.

## ◆ FPU_FPCCR_LSPACT_Msk [1/3]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1562 of file core_cm7.h.

## ◆ FPU_FPCCR_LSPACT_Msk [2/3]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1648 of file core_armv8mml.h.

## ◆ FPU_FPCCR_LSPACT_Msk [3/3]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1805 of file core_armv81mml.h.

## ◆ FPU_FPCCR_LSPACT_Pos [1/3]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1561 of file core_cm7.h.

## ◆ FPU_FPCCR_LSPACT_Pos [2/3]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1647 of file core_armv8mml.h.

## ◆ FPU_FPCCR_LSPACT_Pos [3/3]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1804 of file core_armv81mml.h.

## ◆ FPU_FPCCR_LSPEN_Msk [1/3]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1541 of file core_cm7.h.

## ◆ FPU_FPCCR_LSPEN_Msk [2/3]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1603 of file core_armv8mml.h.

## ◆ FPU_FPCCR_LSPEN_Msk [3/3]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1760 of file core_armv81mml.h.

## ◆ FPU_FPCCR_LSPEN_Pos [1/3]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1540 of file core_cm7.h.

## ◆ FPU_FPCCR_LSPEN_Pos [2/3]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1602 of file core_armv8mml.h.

## ◆ FPU_FPCCR_LSPEN_Pos [3/3]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1759 of file core_armv81mml.h.

## ◆ FPU_FPCCR_LSPENS_Msk [1/2]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1606 of file core_armv8mml.h.

## ◆ FPU_FPCCR_LSPENS_Msk [2/2]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1763 of file core_armv81mml.h.

## ◆ FPU_FPCCR_LSPENS_Pos [1/2]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1605 of file core_armv8mml.h.

## ◆ FPU_FPCCR_LSPENS_Pos [2/2]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1762 of file core_armv81mml.h.

## ◆ FPU_FPCCR_MMRDY_Msk [1/3]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1550 of file core_cm7.h.

## ◆ FPU_FPCCR_MMRDY_Msk [2/3]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1633 of file core_armv8mml.h.

## ◆ FPU_FPCCR_MMRDY_Msk [3/3]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1790 of file core_armv81mml.h.

## ◆ FPU_FPCCR_MMRDY_Pos [1/3]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1549 of file core_cm7.h.

## ◆ FPU_FPCCR_MMRDY_Pos [2/3]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1632 of file core_armv8mml.h.

## ◆ FPU_FPCCR_MMRDY_Pos [3/3]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1789 of file core_armv81mml.h.

## ◆ FPU_FPCCR_MONRDY_Msk [1/3]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1544 of file core_cm7.h.

## ◆ FPU_FPCCR_MONRDY_Msk [2/3]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1624 of file core_armv8mml.h.

## ◆ FPU_FPCCR_MONRDY_Msk [3/3]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1781 of file core_armv81mml.h.

## ◆ FPU_FPCCR_MONRDY_Pos [1/3]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1543 of file core_cm7.h.

## ◆ FPU_FPCCR_MONRDY_Pos [2/3]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1623 of file core_armv8mml.h.

## ◆ FPU_FPCCR_MONRDY_Pos [3/3]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1780 of file core_armv81mml.h.

## ◆ FPU_FPCCR_S_Msk [1/2]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1642 of file core_armv8mml.h.

## ◆ FPU_FPCCR_S_Msk [2/2]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1799 of file core_armv81mml.h.

## ◆ FPU_FPCCR_S_Pos [1/2]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1641 of file core_armv8mml.h.

## ◆ FPU_FPCCR_S_Pos [2/2]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1798 of file core_armv81mml.h.

## ◆ FPU_FPCCR_SFRDY_Msk [1/2]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1627 of file core_armv8mml.h.

## ◆ FPU_FPCCR_SFRDY_Msk [2/2]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1784 of file core_armv81mml.h.

## ◆ FPU_FPCCR_SFRDY_Pos [1/2]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1626 of file core_armv8mml.h.

## ◆ FPU_FPCCR_SFRDY_Pos [2/2]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1783 of file core_armv81mml.h.

## ◆ FPU_FPCCR_SPLIMVIOL_Msk [1/2]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1621 of file core_armv8mml.h.

## ◆ FPU_FPCCR_SPLIMVIOL_Msk [2/2]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1778 of file core_armv81mml.h.

## ◆ FPU_FPCCR_SPLIMVIOL_Pos [1/2]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1620 of file core_armv8mml.h.

## ◆ FPU_FPCCR_SPLIMVIOL_Pos [2/2]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1777 of file core_armv81mml.h.

## ◆ FPU_FPCCR_THREAD_Msk [1/3]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1556 of file core_cm7.h.

## ◆ FPU_FPCCR_THREAD_Msk [2/3]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1639 of file core_armv8mml.h.

## ◆ FPU_FPCCR_THREAD_Msk [3/3]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1796 of file core_armv81mml.h.

## ◆ FPU_FPCCR_THREAD_Pos [1/3]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1555 of file core_cm7.h.

## ◆ FPU_FPCCR_THREAD_Pos [2/3]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1638 of file core_armv8mml.h.

## ◆ FPU_FPCCR_THREAD_Pos [3/3]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1795 of file core_armv81mml.h.

## ◆ FPU_FPCCR_TS_Msk [1/2]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1615 of file core_armv8mml.h.

## ◆ FPU_FPCCR_TS_Msk [2/2]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1772 of file core_armv81mml.h.

## ◆ FPU_FPCCR_TS_Pos [1/2]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1614 of file core_armv8mml.h.

## ◆ FPU_FPCCR_TS_Pos [2/2]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1771 of file core_armv81mml.h.

## ◆ FPU_FPCCR_UFRDY_Msk [1/2]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1618 of file core_armv8mml.h.

## ◆ FPU_FPCCR_UFRDY_Msk [2/2]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1775 of file core_armv81mml.h.

## ◆ FPU_FPCCR_UFRDY_Pos [1/2]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1617 of file core_armv8mml.h.

## ◆ FPU_FPCCR_UFRDY_Pos [2/2]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1774 of file core_armv81mml.h.

## ◆ FPU_FPCCR_USER_Msk [1/3]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1559 of file core_cm7.h.

## ◆ FPU_FPCCR_USER_Msk [2/3]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1645 of file core_armv8mml.h.

## ◆ FPU_FPCCR_USER_Msk [3/3]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1802 of file core_armv81mml.h.

## ◆ FPU_FPCCR_USER_Pos [1/3]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1558 of file core_cm7.h.

## ◆ FPU_FPCCR_USER_Pos [2/3]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1644 of file core_armv8mml.h.

## ◆ FPU_FPCCR_USER_Pos [3/3]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1801 of file core_armv81mml.h.

## ◆ FPU_FPDSCR_AHP_Msk [1/3]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1570 of file core_cm7.h.

## ◆ FPU_FPDSCR_AHP_Msk [2/3]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1656 of file core_armv8mml.h.

## ◆ FPU_FPDSCR_AHP_Msk [3/3]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1813 of file core_armv81mml.h.

## ◆ FPU_FPDSCR_AHP_Pos [1/3]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1569 of file core_cm7.h.

## ◆ FPU_FPDSCR_AHP_Pos [2/3]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1655 of file core_armv8mml.h.

## ◆ FPU_FPDSCR_AHP_Pos [3/3]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1812 of file core_armv81mml.h.

## ◆ FPU_FPDSCR_DN_Msk [1/3]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1573 of file core_cm7.h.

## ◆ FPU_FPDSCR_DN_Msk [2/3]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1659 of file core_armv8mml.h.

## ◆ FPU_FPDSCR_DN_Msk [3/3]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1816 of file core_armv81mml.h.

## ◆ FPU_FPDSCR_DN_Pos [1/3]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1572 of file core_cm7.h.

## ◆ FPU_FPDSCR_DN_Pos [2/3]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1658 of file core_armv8mml.h.

## ◆ FPU_FPDSCR_DN_Pos [3/3]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1815 of file core_armv81mml.h.

## ◆ FPU_FPDSCR_FZ_Msk [1/3]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1576 of file core_cm7.h.

## ◆ FPU_FPDSCR_FZ_Msk [2/3]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1662 of file core_armv8mml.h.

## ◆ FPU_FPDSCR_FZ_Msk [3/3]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1819 of file core_armv81mml.h.

## ◆ FPU_FPDSCR_FZ_Pos [1/3]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1575 of file core_cm7.h.

## ◆ FPU_FPDSCR_FZ_Pos [2/3]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1661 of file core_armv8mml.h.

## ◆ FPU_FPDSCR_FZ_Pos [3/3]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1818 of file core_armv81mml.h.

## ◆ FPU_FPDSCR_RMode_Msk [1/3]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1579 of file core_cm7.h.

## ◆ FPU_FPDSCR_RMode_Msk [2/3]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1665 of file core_armv8mml.h.

## ◆ FPU_FPDSCR_RMode_Msk [3/3]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1822 of file core_armv81mml.h.

## ◆ FPU_FPDSCR_RMode_Pos [1/3]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1578 of file core_cm7.h.

## ◆ FPU_FPDSCR_RMode_Pos [2/3]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1664 of file core_armv8mml.h.

## ◆ FPU_FPDSCR_RMode_Pos [3/3]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1821 of file core_armv81mml.h.

## ◆ FPU_MVFR0_A_SIMD_registers_Msk [1/3]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1604 of file core_cm7.h.

## ◆ FPU_MVFR0_A_SIMD_registers_Msk [2/3]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1690 of file core_armv8mml.h.

## ◆ FPU_MVFR0_A_SIMD_registers_Msk [3/3]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1847 of file core_armv81mml.h.

## ◆ FPU_MVFR0_A_SIMD_registers_Pos [1/3]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1603 of file core_cm7.h.

## ◆ FPU_MVFR0_A_SIMD_registers_Pos [2/3]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1689 of file core_armv8mml.h.

## ◆ FPU_MVFR0_A_SIMD_registers_Pos [3/3]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1846 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Divide_Msk [1/3]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1592 of file core_cm7.h.

## ◆ FPU_MVFR0_Divide_Msk [2/3]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1678 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Divide_Msk [3/3]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1835 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Divide_Pos [1/3]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1591 of file core_cm7.h.

## ◆ FPU_MVFR0_Divide_Pos [2/3]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1677 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Divide_Pos [3/3]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1834 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Double_precision_Msk [1/3]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1598 of file core_cm7.h.

## ◆ FPU_MVFR0_Double_precision_Msk [2/3]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1684 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Double_precision_Msk [3/3]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1841 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Double_precision_Pos [1/3]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1597 of file core_cm7.h.

## ◆ FPU_MVFR0_Double_precision_Pos [2/3]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1683 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Double_precision_Pos [3/3]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1840 of file core_armv81mml.h.

## ◆ FPU_MVFR0_FP_excep_trapping_Msk [1/3]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1595 of file core_cm7.h.

## ◆ FPU_MVFR0_FP_excep_trapping_Msk [2/3]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1681 of file core_armv8mml.h.

## ◆ FPU_MVFR0_FP_excep_trapping_Msk [3/3]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1838 of file core_armv81mml.h.

## ◆ FPU_MVFR0_FP_excep_trapping_Pos [1/3]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1594 of file core_cm7.h.

## ◆ FPU_MVFR0_FP_excep_trapping_Pos [2/3]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1680 of file core_armv8mml.h.

## ◆ FPU_MVFR0_FP_excep_trapping_Pos [3/3]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1837 of file core_armv81mml.h.

## ◆ FPU_MVFR0_FP_rounding_modes_Msk [1/3]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1583 of file core_cm7.h.

## ◆ FPU_MVFR0_FP_rounding_modes_Msk [2/3]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1669 of file core_armv8mml.h.

## ◆ FPU_MVFR0_FP_rounding_modes_Msk [3/3]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1826 of file core_armv81mml.h.

## ◆ FPU_MVFR0_FP_rounding_modes_Pos [1/3]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1582 of file core_cm7.h.

## ◆ FPU_MVFR0_FP_rounding_modes_Pos [2/3]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1668 of file core_armv8mml.h.

## ◆ FPU_MVFR0_FP_rounding_modes_Pos [3/3]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1825 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Short_vectors_Msk [1/3]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1586 of file core_cm7.h.

## ◆ FPU_MVFR0_Short_vectors_Msk [2/3]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1672 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Short_vectors_Msk [3/3]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1829 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Short_vectors_Pos [1/3]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1585 of file core_cm7.h.

## ◆ FPU_MVFR0_Short_vectors_Pos [2/3]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1671 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Short_vectors_Pos [3/3]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1828 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Single_precision_Msk [1/3]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1601 of file core_cm7.h.

## ◆ FPU_MVFR0_Single_precision_Msk [2/3]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1687 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Single_precision_Msk [3/3]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1844 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Single_precision_Pos [1/3]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1600 of file core_cm7.h.

## ◆ FPU_MVFR0_Single_precision_Pos [2/3]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1686 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Single_precision_Pos [3/3]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1843 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Square_root_Msk [1/3]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1589 of file core_cm7.h.

## ◆ FPU_MVFR0_Square_root_Msk [2/3]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1675 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Square_root_Msk [3/3]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1832 of file core_armv81mml.h.

## ◆ FPU_MVFR0_Square_root_Pos [1/3]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1588 of file core_cm7.h.

## ◆ FPU_MVFR0_Square_root_Pos [2/3]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1674 of file core_armv8mml.h.

## ◆ FPU_MVFR0_Square_root_Pos [3/3]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1831 of file core_armv81mml.h.

## ◆ FPU_MVFR1_D_NaN_mode_Msk [1/3]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1614 of file core_cm7.h.

## ◆ FPU_MVFR1_D_NaN_mode_Msk [2/3]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1700 of file core_armv8mml.h.

## ◆ FPU_MVFR1_D_NaN_mode_Msk [3/3]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1857 of file core_armv81mml.h.

## ◆ FPU_MVFR1_D_NaN_mode_Pos [1/3]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1613 of file core_cm7.h.

## ◆ FPU_MVFR1_D_NaN_mode_Pos [2/3]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1699 of file core_armv8mml.h.

## ◆ FPU_MVFR1_D_NaN_mode_Pos [3/3]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1856 of file core_armv81mml.h.

## ◆ FPU_MVFR1_FP_fused_MAC_Msk [1/3]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1608 of file core_cm7.h.

## ◆ FPU_MVFR1_FP_fused_MAC_Msk [2/3]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1694 of file core_armv8mml.h.

## ◆ FPU_MVFR1_FP_fused_MAC_Msk [3/3]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1851 of file core_armv81mml.h.

## ◆ FPU_MVFR1_FP_fused_MAC_Pos [1/3]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1607 of file core_cm7.h.

## ◆ FPU_MVFR1_FP_fused_MAC_Pos [2/3]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1693 of file core_armv8mml.h.

## ◆ FPU_MVFR1_FP_fused_MAC_Pos [3/3]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1850 of file core_armv81mml.h.

## ◆ FPU_MVFR1_FP_HPFP_Msk [1/3]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1611 of file core_cm7.h.

## ◆ FPU_MVFR1_FP_HPFP_Msk [2/3]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1697 of file core_armv8mml.h.

## ◆ FPU_MVFR1_FP_HPFP_Msk [3/3]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1854 of file core_armv81mml.h.

## ◆ FPU_MVFR1_FP_HPFP_Pos [1/3]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1610 of file core_cm7.h.

## ◆ FPU_MVFR1_FP_HPFP_Pos [2/3]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1696 of file core_armv8mml.h.

## ◆ FPU_MVFR1_FP_HPFP_Pos [3/3]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1853 of file core_armv81mml.h.

## ◆ FPU_MVFR1_FtZ_mode_Msk [1/3]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1617 of file core_cm7.h.

## ◆ FPU_MVFR1_FtZ_mode_Msk [2/3]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1703 of file core_armv8mml.h.

## ◆ FPU_MVFR1_FtZ_mode_Msk [3/3]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1860 of file core_armv81mml.h.

## ◆ FPU_MVFR1_FtZ_mode_Pos [1/3]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1616 of file core_cm7.h.

## ◆ FPU_MVFR1_FtZ_mode_Pos [2/3]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1702 of file core_armv8mml.h.

## ◆ FPU_MVFR1_FtZ_mode_Pos [3/3]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1859 of file core_armv81mml.h.

## ◆ FPU_MVFR2_VFP_Misc_Msk

#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

MVFR2: VFP Misc bits Mask

Definition at line 1622 of file core_cm7.h.

## ◆ FPU_MVFR2_VFP_Misc_Pos

#define FPU_MVFR2_VFP_Misc_Pos 4U

MVFR2: VFP Misc bits Position

Definition at line 1621 of file core_cm7.h.