Callisto4Bootloader: LPSPI Register Masks

Callisto4Bootloader

LPSPI Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » LPSPI Peripheral Access Layer

## CR - Control Register

#define | LPSPI_CR_MEN_MASK (0x1U)
#define | LPSPI_CR_MEN_SHIFT (0U)
#define | LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
#define | LPSPI_CR_RST_MASK (0x2U)
#define | LPSPI_CR_RST_SHIFT (1U)
#define | LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
#define | LPSPI_CR_DOZEN_MASK (0x4U)
#define | LPSPI_CR_DOZEN_SHIFT (2U)
#define | LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
#define | LPSPI_CR_DBGEN_MASK (0x8U)
#define | LPSPI_CR_DBGEN_SHIFT (3U)
#define | LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
#define | LPSPI_CR_RTF_MASK (0x100U)
#define | LPSPI_CR_RTF_SHIFT (8U)
#define | LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
#define | LPSPI_CR_RRF_MASK (0x200U)
#define | LPSPI_CR_RRF_SHIFT (9U)
#define | LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

## VERID - Version ID Register

#define | LPSPI_VERID_FEATURE_MASK (0xFFFFU)
#define | LPSPI_VERID_FEATURE_SHIFT (0U)
#define | LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define | LPSPI_VERID_MINOR_MASK (0xFF0000U)
#define | LPSPI_VERID_MINOR_SHIFT (16U)
#define | LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define | LPSPI_VERID_MAJOR_MASK (0xFF000000U)
#define | LPSPI_VERID_MAJOR_SHIFT (24U)
#define | LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)

## PARAM - Parameter Register

#define | LPSPI_PARAM_TXFIFO_MASK (0xFFU)
#define | LPSPI_PARAM_TXFIFO_SHIFT (0U)
#define | LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define | LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
#define | LPSPI_PARAM_RXFIFO_SHIFT (8U)
#define | LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
#define | LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
#define | LPSPI_PARAM_PCSNUM_SHIFT (16U)
#define | LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)

## SR - Status Register

#define | LPSPI_SR_TDF_MASK (0x1U)
#define | LPSPI_SR_TDF_SHIFT (0U)
#define | LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
#define | LPSPI_SR_RDF_MASK (0x2U)
#define | LPSPI_SR_RDF_SHIFT (1U)
#define | LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
#define | LPSPI_SR_WCF_MASK (0x100U)
#define | LPSPI_SR_WCF_SHIFT (8U)
#define | LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
#define | LPSPI_SR_FCF_MASK (0x200U)
#define | LPSPI_SR_FCF_SHIFT (9U)
#define | LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
#define | LPSPI_SR_TCF_MASK (0x400U)
#define | LPSPI_SR_TCF_SHIFT (10U)
#define | LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
#define | LPSPI_SR_TEF_MASK (0x800U)
#define | LPSPI_SR_TEF_SHIFT (11U)
#define | LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
#define | LPSPI_SR_REF_MASK (0x1000U)
#define | LPSPI_SR_REF_SHIFT (12U)
#define | LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
#define | LPSPI_SR_DMF_MASK (0x2000U)
#define | LPSPI_SR_DMF_SHIFT (13U)
#define | LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
#define | LPSPI_SR_MBF_MASK (0x1000000U)
#define | LPSPI_SR_MBF_SHIFT (24U)
#define | LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)

## IER - Interrupt Enable Register

#define | LPSPI_IER_TDIE_MASK (0x1U)
#define | LPSPI_IER_TDIE_SHIFT (0U)
#define | LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
#define | LPSPI_IER_RDIE_MASK (0x2U)
#define | LPSPI_IER_RDIE_SHIFT (1U)
#define | LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
#define | LPSPI_IER_WCIE_MASK (0x100U)
#define | LPSPI_IER_WCIE_SHIFT (8U)
#define | LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
#define | LPSPI_IER_FCIE_MASK (0x200U)
#define | LPSPI_IER_FCIE_SHIFT (9U)
#define | LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
#define | LPSPI_IER_TCIE_MASK (0x400U)
#define | LPSPI_IER_TCIE_SHIFT (10U)
#define | LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
#define | LPSPI_IER_TEIE_MASK (0x800U)
#define | LPSPI_IER_TEIE_SHIFT (11U)
#define | LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
#define | LPSPI_IER_REIE_MASK (0x1000U)
#define | LPSPI_IER_REIE_SHIFT (12U)
#define | LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
#define | LPSPI_IER_DMIE_MASK (0x2000U)
#define | LPSPI_IER_DMIE_SHIFT (13U)
#define | LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)

## DER - DMA Enable Register

#define | LPSPI_DER_TDDE_MASK (0x1U)
#define | LPSPI_DER_TDDE_SHIFT (0U)
#define | LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
#define | LPSPI_DER_RDDE_MASK (0x2U)
#define | LPSPI_DER_RDDE_SHIFT (1U)
#define | LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)

## CFGR0 - Configuration Register 0

#define | LPSPI_CFGR0_HREN_MASK (0x1U)
#define | LPSPI_CFGR0_HREN_SHIFT (0U)
#define | LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
#define | LPSPI_CFGR0_HRPOL_MASK (0x2U)
#define | LPSPI_CFGR0_HRPOL_SHIFT (1U)
#define | LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
#define | LPSPI_CFGR0_HRSEL_MASK (0x4U)
#define | LPSPI_CFGR0_HRSEL_SHIFT (2U)
#define | LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
#define | LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
#define | LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
#define | LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
#define | LPSPI_CFGR0_RDMO_MASK (0x200U)
#define | LPSPI_CFGR0_RDMO_SHIFT (9U)
#define | LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)

## CFGR1 - Configuration Register 1

#define | LPSPI_CFGR1_MASTER_MASK (0x1U)
#define | LPSPI_CFGR1_MASTER_SHIFT (0U)
#define | LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
#define | LPSPI_CFGR1_SAMPLE_MASK (0x2U)
#define | LPSPI_CFGR1_SAMPLE_SHIFT (1U)
#define | LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
#define | LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
#define | LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
#define | LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
#define | LPSPI_CFGR1_NOSTALL_MASK (0x8U)
#define | LPSPI_CFGR1_NOSTALL_SHIFT (3U)
#define | LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
#define | LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
#define | LPSPI_CFGR1_PCSPOL_SHIFT (8U)
#define | LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
#define | LPSPI_CFGR1_MATCFG_MASK (0x70000U)
#define | LPSPI_CFGR1_MATCFG_SHIFT (16U)
#define | LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
#define | LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
#define | LPSPI_CFGR1_PINCFG_SHIFT (24U)
#define | LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
#define | LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
#define | LPSPI_CFGR1_OUTCFG_SHIFT (26U)
#define | LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
#define | LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
#define | LPSPI_CFGR1_PCSCFG_SHIFT (27U)
#define | LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)

## DMR0 - Data Match Register 0

#define | LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
#define | LPSPI_DMR0_MATCH0_SHIFT (0U)
#define | LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)

## DMR1 - Data Match Register 1

#define | LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
#define | LPSPI_DMR1_MATCH1_SHIFT (0U)
#define | LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)

## CCR - Clock Configuration Register

#define | LPSPI_CCR_SCKDIV_MASK (0xFFU)
#define | LPSPI_CCR_SCKDIV_SHIFT (0U)
#define | LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
#define | LPSPI_CCR_DBT_MASK (0xFF00U)
#define | LPSPI_CCR_DBT_SHIFT (8U)
#define | LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
#define | LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
#define | LPSPI_CCR_PCSSCK_SHIFT (16U)
#define | LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
#define | LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
#define | LPSPI_CCR_SCKPCS_SHIFT (24U)
#define | LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)

## FCR - FIFO Control Register

#define | LPSPI_FCR_TXWATER_MASK (0xFU)
#define | LPSPI_FCR_TXWATER_SHIFT (0U)
#define | LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
#define | LPSPI_FCR_RXWATER_MASK (0xF0000U)
#define | LPSPI_FCR_RXWATER_SHIFT (16U)
#define | LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)

## FSR - FIFO Status Register

#define | LPSPI_FSR_TXCOUNT_MASK (0x1FU)
#define | LPSPI_FSR_TXCOUNT_SHIFT (0U)
#define | LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
#define | LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
#define | LPSPI_FSR_RXCOUNT_SHIFT (16U)
#define | LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)

## TCR - Transmit Command Register

#define | LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
#define | LPSPI_TCR_FRAMESZ_SHIFT (0U)
#define | LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
#define | LPSPI_TCR_WIDTH_MASK (0x30000U)
#define | LPSPI_TCR_WIDTH_SHIFT (16U)
#define | LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
#define | LPSPI_TCR_TXMSK_MASK (0x40000U)
#define | LPSPI_TCR_TXMSK_SHIFT (18U)
#define | LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
#define | LPSPI_TCR_RXMSK_MASK (0x80000U)
#define | LPSPI_TCR_RXMSK_SHIFT (19U)
#define | LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
#define | LPSPI_TCR_CONTC_MASK (0x100000U)
#define | LPSPI_TCR_CONTC_SHIFT (20U)
#define | LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
#define | LPSPI_TCR_CONT_MASK (0x200000U)
#define | LPSPI_TCR_CONT_SHIFT (21U)
#define | LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
#define | LPSPI_TCR_BYSW_MASK (0x400000U)
#define | LPSPI_TCR_BYSW_SHIFT (22U)
#define | LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
#define | LPSPI_TCR_LSBF_MASK (0x800000U)
#define | LPSPI_TCR_LSBF_SHIFT (23U)
#define | LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
#define | LPSPI_TCR_PCS_MASK (0x3000000U)
#define | LPSPI_TCR_PCS_SHIFT (24U)
#define | LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
#define | LPSPI_TCR_PRESCALE_MASK (0x38000000U)
#define | LPSPI_TCR_PRESCALE_SHIFT (27U)
#define | LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
#define | LPSPI_TCR_CPHA_MASK (0x40000000U)
#define | LPSPI_TCR_CPHA_SHIFT (30U)
#define | LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
#define | LPSPI_TCR_CPOL_MASK (0x80000000U)
#define | LPSPI_TCR_CPOL_SHIFT (31U)
#define | LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)

## TDR - Transmit Data Register

#define | LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
#define | LPSPI_TDR_DATA_SHIFT (0U)
#define | LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)

## RSR - Receive Status Register

#define | LPSPI_RSR_SOF_MASK (0x1U)
#define | LPSPI_RSR_SOF_SHIFT (0U)
#define | LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
#define | LPSPI_RSR_RXEMPTY_MASK (0x2U)
#define | LPSPI_RSR_RXEMPTY_SHIFT (1U)
#define | LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)

## RDR - Receive Data Register

#define | LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
#define | LPSPI_RDR_DATA_SHIFT (0U)
#define | LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ LPSPI_CCR_DBT

#define LPSPI_CCR_DBT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)

DBT - Delay Between Transfers

Definition at line 28133 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_DBT_MASK

#define LPSPI_CCR_DBT_MASK (0xFF00U)

Definition at line 28129 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_DBT_SHIFT

#define LPSPI_CCR_DBT_SHIFT (8U)

Definition at line 28130 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_PCSSCK

#define LPSPI_CCR_PCSSCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)

PCSSCK - PCS-to-SCK Delay

Definition at line 28138 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_PCSSCK_MASK

#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)

Definition at line 28134 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_PCSSCK_SHIFT

#define LPSPI_CCR_PCSSCK_SHIFT (16U)

Definition at line 28135 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_SCKDIV

#define LPSPI_CCR_SCKDIV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)

SCKDIV - SCK Divider

Definition at line 28128 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_SCKDIV_MASK

#define LPSPI_CCR_SCKDIV_MASK (0xFFU)

Definition at line 28124 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_SCKDIV_SHIFT

#define LPSPI_CCR_SCKDIV_SHIFT (0U)

Definition at line 28125 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_SCKPCS

#define LPSPI_CCR_SCKPCS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)

SCKPCS - SCK-to-PCS Delay

Definition at line 28143 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_SCKPCS_MASK

#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)

Definition at line 28139 of file MIMXRT1062.h.

## ◆ LPSPI_CCR_SCKPCS_SHIFT

#define LPSPI_CCR_SCKPCS_SHIFT (24U)

Definition at line 28140 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_CIRFIFO

#define LPSPI_CFGR0_CIRFIFO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)

CIRFIFO - Circular FIFO Enable 0b0..Circular FIFO is disabled 0b1..Circular FIFO is enabled

Definition at line 28017 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_CIRFIFO_MASK

#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)

Definition at line 28011 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_CIRFIFO_SHIFT

#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)

Definition at line 28012 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HREN

#define LPSPI_CFGR0_HREN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)

HREN - Host Request Enable 0b0..Host request is disabled 0b1..Host request is enabled

Definition at line 27996 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HREN_MASK

#define LPSPI_CFGR0_HREN_MASK (0x1U)

Definition at line 27990 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HREN_SHIFT

#define LPSPI_CFGR0_HREN_SHIFT (0U)

Definition at line 27991 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HRPOL

#define LPSPI_CFGR0_HRPOL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)

HRPOL - Host Request Polarity 0b0..Active low 0b1..Active high

Definition at line 28003 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HRPOL_MASK

#define LPSPI_CFGR0_HRPOL_MASK (0x2U)

Definition at line 27997 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HRPOL_SHIFT

#define LPSPI_CFGR0_HRPOL_SHIFT (1U)

Definition at line 27998 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HRSEL

#define LPSPI_CFGR0_HRSEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)

HRSEL - Host Request Select 0b0..Host request input is the LPSPI_HREQ pin 0b1..Host request input is the input trigger

Definition at line 28010 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HRSEL_MASK

#define LPSPI_CFGR0_HRSEL_MASK (0x4U)

Definition at line 28004 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_HRSEL_SHIFT

#define LPSPI_CFGR0_HRSEL_SHIFT (2U)

Definition at line 28005 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_RDMO

#define LPSPI_CFGR0_RDMO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)

RDMO - Receive Data Match Only 0b0..Received data is stored in the receive FIFO as in normal operations 0b1..Received data is discarded unless the Data Match Flag (DMF) is set

Definition at line 28024 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_RDMO_MASK

#define LPSPI_CFGR0_RDMO_MASK (0x200U)

Definition at line 28018 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR0_RDMO_SHIFT

#define LPSPI_CFGR0_RDMO_SHIFT (9U)

Definition at line 28019 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_AUTOPCS

#define LPSPI_CFGR1_AUTOPCS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)

AUTOPCS - Automatic PCS 0b0..Automatic PCS generation is disabled 0b1..Automatic PCS generation is enabled

Definition at line 28049 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_AUTOPCS_MASK

#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)

Definition at line 28043 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_AUTOPCS_SHIFT

#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)

Definition at line 28044 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_MASTER

#define LPSPI_CFGR1_MASTER | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)

MASTER - Master Mode 0b0..Slave mode 0b1..Master mode

Definition at line 28035 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_MASTER_MASK

#define LPSPI_CFGR1_MASTER_MASK (0x1U)

Definition at line 28029 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_MASTER_SHIFT

#define LPSPI_CFGR1_MASTER_SHIFT (0U)

Definition at line 28030 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_MATCFG

#define LPSPI_CFGR1_MATCFG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)

MATCFG - Match Configuration 0b000..Match is disabled 0b001..Reserved 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]

Definition at line 28078 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_MATCFG_MASK

#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)

Definition at line 28064 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_MATCFG_SHIFT

#define LPSPI_CFGR1_MATCFG_SHIFT (16U)

Definition at line 28065 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_NOSTALL

#define LPSPI_CFGR1_NOSTALL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)

NOSTALL - No Stall 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur

Definition at line 28056 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_NOSTALL_MASK

#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)

Definition at line 28050 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_NOSTALL_SHIFT

#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)

Definition at line 28051 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_OUTCFG

#define LPSPI_CFGR1_OUTCFG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)

OUTCFG - Output Config 0b0..Output data retains last value when chip select is negated 0b1..Output data is tristated when chip select is negated

Definition at line 28094 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_OUTCFG_MASK

#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)

Definition at line 28088 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_OUTCFG_SHIFT

#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)

Definition at line 28089 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PCSCFG

#define LPSPI_CFGR1_PCSCFG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)

PCSCFG - Peripheral Chip Select Configuration 0b0..PCS[3:2] are enabled 0b1..PCS[3:2] are disabled

Definition at line 28101 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PCSCFG_MASK

#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)

Definition at line 28095 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PCSCFG_SHIFT

#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)

Definition at line 28096 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PCSPOL

#define LPSPI_CFGR1_PCSPOL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)

PCSPOL - Peripheral Chip Select Polarity 0b0000..The Peripheral Chip Select pin PCSx is active low 0b0001..The Peripheral Chip Select pin PCSx is active high

Definition at line 28063 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PCSPOL_MASK

#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)

Definition at line 28057 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PCSPOL_SHIFT

#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)

Definition at line 28058 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PINCFG

#define LPSPI_CFGR1_PINCFG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)

PINCFG - Pin Configuration 0b00..SIN is used for input data and SOUT is used for output data 0b01..SIN is used for both input and output data 0b10..SOUT is used for both input and output data 0b11..SOUT is used for input data and SIN is used for output data

Definition at line 28087 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PINCFG_MASK

#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)

Definition at line 28079 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_PINCFG_SHIFT

#define LPSPI_CFGR1_PINCFG_SHIFT (24U)

Definition at line 28080 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_SAMPLE

#define LPSPI_CFGR1_SAMPLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)

SAMPLE - Sample Point 0b0..Input data is sampled on SCK edge 0b1..Input data is sampled on delayed SCK edge

Definition at line 28042 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_SAMPLE_MASK

#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)

Definition at line 28036 of file MIMXRT1062.h.

## ◆ LPSPI_CFGR1_SAMPLE_SHIFT

#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)

Definition at line 28037 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DBGEN

#define LPSPI_CR_DBGEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..Module is disabled in debug mode 0b1..Module is enabled in debug mode

Definition at line 27826 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DBGEN_MASK

#define LPSPI_CR_DBGEN_MASK (0x8U)

Definition at line 27820 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DBGEN_SHIFT

#define LPSPI_CR_DBGEN_SHIFT (3U)

Definition at line 27821 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DOZEN

#define LPSPI_CR_DOZEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

DOZEN - Doze mode enable 0b0..Module is enabled in Doze mode 0b1..Module is disabled in Doze mode

Definition at line 27819 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DOZEN_MASK

#define LPSPI_CR_DOZEN_MASK (0x4U)

Definition at line 27813 of file MIMXRT1062.h.

## ◆ LPSPI_CR_DOZEN_SHIFT

#define LPSPI_CR_DOZEN_SHIFT (2U)

Definition at line 27814 of file MIMXRT1062.h.

## ◆ LPSPI_CR_MEN

#define LPSPI_CR_MEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

MEN - Module Enable 0b0..Module is disabled 0b1..Module is enabled

Definition at line 27805 of file MIMXRT1062.h.

## ◆ LPSPI_CR_MEN_MASK

#define LPSPI_CR_MEN_MASK (0x1U)

Definition at line 27799 of file MIMXRT1062.h.

## ◆ LPSPI_CR_MEN_SHIFT

#define LPSPI_CR_MEN_SHIFT (0U)

Definition at line 27800 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RRF

#define LPSPI_CR_RRF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive FIFO is reset

Definition at line 27840 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RRF_MASK

#define LPSPI_CR_RRF_MASK (0x200U)

Definition at line 27834 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RRF_SHIFT

#define LPSPI_CR_RRF_SHIFT (9U)

Definition at line 27835 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RST

#define LPSPI_CR_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

RST - Software Reset 0b0..Module is not reset 0b1..Module is reset

Definition at line 27812 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RST_MASK

#define LPSPI_CR_RST_MASK (0x2U)

Definition at line 27806 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RST_SHIFT

#define LPSPI_CR_RST_SHIFT (1U)

Definition at line 27807 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RTF

#define LPSPI_CR_RTF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit FIFO is reset

Definition at line 27833 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RTF_MASK

#define LPSPI_CR_RTF_MASK (0x100U)

Definition at line 27827 of file MIMXRT1062.h.

## ◆ LPSPI_CR_RTF_SHIFT

#define LPSPI_CR_RTF_SHIFT (8U)

Definition at line 27828 of file MIMXRT1062.h.

## ◆ LPSPI_DER_RDDE

#define LPSPI_DER_RDDE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)

RDDE - Receive Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

Definition at line 27985 of file MIMXRT1062.h.

## ◆ LPSPI_DER_RDDE_MASK

#define LPSPI_DER_RDDE_MASK (0x2U)

Definition at line 27979 of file MIMXRT1062.h.

## ◆ LPSPI_DER_RDDE_SHIFT

#define LPSPI_DER_RDDE_SHIFT (1U)

Definition at line 27980 of file MIMXRT1062.h.

## ◆ LPSPI_DER_TDDE

#define LPSPI_DER_TDDE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)

TDDE - Transmit Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

Definition at line 27978 of file MIMXRT1062.h.

## ◆ LPSPI_DER_TDDE_MASK

#define LPSPI_DER_TDDE_MASK (0x1U)

Definition at line 27972 of file MIMXRT1062.h.

## ◆ LPSPI_DER_TDDE_SHIFT

#define LPSPI_DER_TDDE_SHIFT (0U)

Definition at line 27973 of file MIMXRT1062.h.

## ◆ LPSPI_DMR0_MATCH0

#define LPSPI_DMR0_MATCH0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)

MATCH0 - Match 0 Value

Definition at line 28110 of file MIMXRT1062.h.

## ◆ LPSPI_DMR0_MATCH0_MASK

#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)

Definition at line 28106 of file MIMXRT1062.h.

## ◆ LPSPI_DMR0_MATCH0_SHIFT

#define LPSPI_DMR0_MATCH0_SHIFT (0U)

Definition at line 28107 of file MIMXRT1062.h.

## ◆ LPSPI_DMR1_MATCH1

#define LPSPI_DMR1_MATCH1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)

MATCH1 - Match 1 Value

Definition at line 28119 of file MIMXRT1062.h.

## ◆ LPSPI_DMR1_MATCH1_MASK

#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)

Definition at line 28115 of file MIMXRT1062.h.

## ◆ LPSPI_DMR1_MATCH1_SHIFT

#define LPSPI_DMR1_MATCH1_SHIFT (0U)

Definition at line 28116 of file MIMXRT1062.h.

## ◆ LPSPI_FCR_RXWATER

#define LPSPI_FCR_RXWATER | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)

RXWATER - Receive FIFO Watermark

Definition at line 28157 of file MIMXRT1062.h.

## ◆ LPSPI_FCR_RXWATER_MASK

#define LPSPI_FCR_RXWATER_MASK (0xF0000U)

Definition at line 28153 of file MIMXRT1062.h.

## ◆ LPSPI_FCR_RXWATER_SHIFT

#define LPSPI_FCR_RXWATER_SHIFT (16U)

Definition at line 28154 of file MIMXRT1062.h.

## ◆ LPSPI_FCR_TXWATER

#define LPSPI_FCR_TXWATER | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)

TXWATER - Transmit FIFO Watermark

Definition at line 28152 of file MIMXRT1062.h.

## ◆ LPSPI_FCR_TXWATER_MASK

#define LPSPI_FCR_TXWATER_MASK (0xFU)

Definition at line 28148 of file MIMXRT1062.h.

## ◆ LPSPI_FCR_TXWATER_SHIFT

#define LPSPI_FCR_TXWATER_SHIFT (0U)

Definition at line 28149 of file MIMXRT1062.h.

## ◆ LPSPI_FSR_RXCOUNT

#define LPSPI_FSR_RXCOUNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)

RXCOUNT - Receive FIFO Count

Definition at line 28171 of file MIMXRT1062.h.

## ◆ LPSPI_FSR_RXCOUNT_MASK

#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)

Definition at line 28167 of file MIMXRT1062.h.

## ◆ LPSPI_FSR_RXCOUNT_SHIFT

#define LPSPI_FSR_RXCOUNT_SHIFT (16U)

Definition at line 28168 of file MIMXRT1062.h.

## ◆ LPSPI_FSR_TXCOUNT

#define LPSPI_FSR_TXCOUNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)

TXCOUNT - Transmit FIFO Count

Definition at line 28166 of file MIMXRT1062.h.

## ◆ LPSPI_FSR_TXCOUNT_MASK

#define LPSPI_FSR_TXCOUNT_MASK (0x1FU)

Definition at line 28162 of file MIMXRT1062.h.

## ◆ LPSPI_FSR_TXCOUNT_SHIFT

#define LPSPI_FSR_TXCOUNT_SHIFT (0U)

Definition at line 28163 of file MIMXRT1062.h.

## ◆ LPSPI_IER_DMIE

#define LPSPI_IER_DMIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)

DMIE - Data Match Interrupt Enable 0b0..Disabled 0b1..Enabled

Definition at line 27967 of file MIMXRT1062.h.

## ◆ LPSPI_IER_DMIE_MASK

#define LPSPI_IER_DMIE_MASK (0x2000U)

Definition at line 27961 of file MIMXRT1062.h.

## ◆ LPSPI_IER_DMIE_SHIFT

#define LPSPI_IER_DMIE_SHIFT (13U)

Definition at line 27962 of file MIMXRT1062.h.

## ◆ LPSPI_IER_FCIE

#define LPSPI_IER_FCIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)

FCIE - Frame Complete Interrupt Enable 0b0..Disabled 0b1..Enabled

Definition at line 27939 of file MIMXRT1062.h.

## ◆ LPSPI_IER_FCIE_MASK

#define LPSPI_IER_FCIE_MASK (0x200U)

Definition at line 27933 of file MIMXRT1062.h.

## ◆ LPSPI_IER_FCIE_SHIFT

#define LPSPI_IER_FCIE_SHIFT (9U)

Definition at line 27934 of file MIMXRT1062.h.

## ◆ LPSPI_IER_RDIE

#define LPSPI_IER_RDIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)

RDIE - Receive Data Interrupt Enable 0b0..Disabled 0b1..Enabled

Definition at line 27925 of file MIMXRT1062.h.

## ◆ LPSPI_IER_RDIE_MASK

#define LPSPI_IER_RDIE_MASK (0x2U)

Definition at line 27919 of file MIMXRT1062.h.

## ◆ LPSPI_IER_RDIE_SHIFT

#define LPSPI_IER_RDIE_SHIFT (1U)

Definition at line 27920 of file MIMXRT1062.h.

## ◆ LPSPI_IER_REIE

#define LPSPI_IER_REIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)

REIE - Receive Error Interrupt Enable 0b0..Disabled 0b1..Enabled

Definition at line 27960 of file MIMXRT1062.h.

## ◆ LPSPI_IER_REIE_MASK

#define LPSPI_IER_REIE_MASK (0x1000U)

Definition at line 27954 of file MIMXRT1062.h.

## ◆ LPSPI_IER_REIE_SHIFT

#define LPSPI_IER_REIE_SHIFT (12U)

Definition at line 27955 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TCIE

#define LPSPI_IER_TCIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)

TCIE - Transfer Complete Interrupt Enable 0b0..Disabled 0b1..Enabled

Definition at line 27946 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TCIE_MASK

#define LPSPI_IER_TCIE_MASK (0x400U)

Definition at line 27940 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TCIE_SHIFT

#define LPSPI_IER_TCIE_SHIFT (10U)

Definition at line 27941 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TDIE

#define LPSPI_IER_TDIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)

TDIE - Transmit Data Interrupt Enable 0b0..Disabled 0b1..Enabled

Definition at line 27918 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TDIE_MASK

#define LPSPI_IER_TDIE_MASK (0x1U)

Definition at line 27912 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TDIE_SHIFT

#define LPSPI_IER_TDIE_SHIFT (0U)

Definition at line 27913 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TEIE

#define LPSPI_IER_TEIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)

TEIE - Transmit Error Interrupt Enable 0b0..Disabled 0b1..Enabled

Definition at line 27953 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TEIE_MASK

#define LPSPI_IER_TEIE_MASK (0x800U)

Definition at line 27947 of file MIMXRT1062.h.

## ◆ LPSPI_IER_TEIE_SHIFT

#define LPSPI_IER_TEIE_SHIFT (11U)

Definition at line 27948 of file MIMXRT1062.h.

## ◆ LPSPI_IER_WCIE

#define LPSPI_IER_WCIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)

WCIE - Word Complete Interrupt Enable 0b0..Disabled 0b1..Enabled

Definition at line 27932 of file MIMXRT1062.h.

## ◆ LPSPI_IER_WCIE_MASK

#define LPSPI_IER_WCIE_MASK (0x100U)

Definition at line 27926 of file MIMXRT1062.h.

## ◆ LPSPI_IER_WCIE_SHIFT

#define LPSPI_IER_WCIE_SHIFT (8U)

Definition at line 27927 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_PCSNUM

#define LPSPI_PARAM_PCSNUM | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)

PCSNUM - PCS Number

Definition at line 27794 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_PCSNUM_MASK

#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)

Definition at line 27790 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_PCSNUM_SHIFT

#define LPSPI_PARAM_PCSNUM_SHIFT (16U)

Definition at line 27791 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_RXFIFO

#define LPSPI_PARAM_RXFIFO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

Definition at line 27789 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_RXFIFO_MASK

#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)

Definition at line 27785 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_RXFIFO_SHIFT

#define LPSPI_PARAM_RXFIFO_SHIFT (8U)

Definition at line 27786 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_TXFIFO

#define LPSPI_PARAM_TXFIFO | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

Definition at line 27784 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_TXFIFO_MASK

#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)

Definition at line 27780 of file MIMXRT1062.h.

## ◆ LPSPI_PARAM_TXFIFO_SHIFT

#define LPSPI_PARAM_TXFIFO_SHIFT (0U)

Definition at line 27781 of file MIMXRT1062.h.

## ◆ LPSPI_RDR_DATA

#define LPSPI_RDR_DATA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)

DATA - Receive Data

Definition at line 28303 of file MIMXRT1062.h.

## ◆ LPSPI_RDR_DATA_MASK

#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)

Definition at line 28299 of file MIMXRT1062.h.

## ◆ LPSPI_RDR_DATA_SHIFT

#define LPSPI_RDR_DATA_SHIFT (0U)

Definition at line 28300 of file MIMXRT1062.h.

## ◆ LPSPI_RSR_RXEMPTY

#define LPSPI_RSR_RXEMPTY | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)

RXEMPTY - RX FIFO Empty 0b0..RX FIFO is not empty 0b1..RX FIFO is empty

Definition at line 28294 of file MIMXRT1062.h.

## ◆ LPSPI_RSR_RXEMPTY_MASK

#define LPSPI_RSR_RXEMPTY_MASK (0x2U)

Definition at line 28288 of file MIMXRT1062.h.

## ◆ LPSPI_RSR_RXEMPTY_SHIFT

#define LPSPI_RSR_RXEMPTY_SHIFT (1U)

Definition at line 28289 of file MIMXRT1062.h.

## ◆ LPSPI_RSR_SOF

#define LPSPI_RSR_SOF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)

SOF - Start Of Frame 0b0..Subsequent data word received after LPSPI_PCS assertion 0b1..First data word received after LPSPI_PCS assertion

Definition at line 28287 of file MIMXRT1062.h.

## ◆ LPSPI_RSR_SOF_MASK

#define LPSPI_RSR_SOF_MASK (0x1U)

Definition at line 28281 of file MIMXRT1062.h.

## ◆ LPSPI_RSR_SOF_SHIFT

#define LPSPI_RSR_SOF_SHIFT (0U)

Definition at line 28282 of file MIMXRT1062.h.

## ◆ LPSPI_SR_DMF

#define LPSPI_SR_DMF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)

DMF - Data Match Flag 0b0..Have not received matching data 0b1..Have received matching data

Definition at line 27900 of file MIMXRT1062.h.

## ◆ LPSPI_SR_DMF_MASK

#define LPSPI_SR_DMF_MASK (0x2000U)

Definition at line 27894 of file MIMXRT1062.h.

## ◆ LPSPI_SR_DMF_SHIFT

#define LPSPI_SR_DMF_SHIFT (13U)

Definition at line 27895 of file MIMXRT1062.h.

## ◆ LPSPI_SR_FCF

#define LPSPI_SR_FCF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)

FCF - Frame Complete Flag 0b0..Frame transfer has not completed 0b1..Frame transfer has completed

Definition at line 27872 of file MIMXRT1062.h.

## ◆ LPSPI_SR_FCF_MASK

#define LPSPI_SR_FCF_MASK (0x200U)

Definition at line 27866 of file MIMXRT1062.h.

## ◆ LPSPI_SR_FCF_SHIFT

#define LPSPI_SR_FCF_SHIFT (9U)

Definition at line 27867 of file MIMXRT1062.h.

## ◆ LPSPI_SR_MBF

#define LPSPI_SR_MBF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)

MBF - Module Busy Flag 0b0..LPSPI is idle 0b1..LPSPI is busy

Definition at line 27907 of file MIMXRT1062.h.

## ◆ LPSPI_SR_MBF_MASK

#define LPSPI_SR_MBF_MASK (0x1000000U)

Definition at line 27901 of file MIMXRT1062.h.

## ◆ LPSPI_SR_MBF_SHIFT

#define LPSPI_SR_MBF_SHIFT (24U)

Definition at line 27902 of file MIMXRT1062.h.

## ◆ LPSPI_SR_RDF

#define LPSPI_SR_RDF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)

RDF - Receive Data Flag 0b0..Receive Data is not ready 0b1..Receive data is ready

Definition at line 27858 of file MIMXRT1062.h.

## ◆ LPSPI_SR_RDF_MASK

#define LPSPI_SR_RDF_MASK (0x2U)

Definition at line 27852 of file MIMXRT1062.h.

## ◆ LPSPI_SR_RDF_SHIFT

#define LPSPI_SR_RDF_SHIFT (1U)

Definition at line 27853 of file MIMXRT1062.h.

## ◆ LPSPI_SR_REF

#define LPSPI_SR_REF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)

REF - Receive Error Flag 0b0..Receive FIFO has not overflowed 0b1..Receive FIFO has overflowed

Definition at line 27893 of file MIMXRT1062.h.

## ◆ LPSPI_SR_REF_MASK

#define LPSPI_SR_REF_MASK (0x1000U)

Definition at line 27887 of file MIMXRT1062.h.

## ◆ LPSPI_SR_REF_SHIFT

#define LPSPI_SR_REF_SHIFT (12U)

Definition at line 27888 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TCF

#define LPSPI_SR_TCF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)

TCF - Transfer Complete Flag 0b0..All transfers have not completed 0b1..All transfers have completed

Definition at line 27879 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TCF_MASK

#define LPSPI_SR_TCF_MASK (0x400U)

Definition at line 27873 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TCF_SHIFT

#define LPSPI_SR_TCF_SHIFT (10U)

Definition at line 27874 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TDF

#define LPSPI_SR_TDF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)

TDF - Transmit Data Flag 0b0..Transmit data not requested 0b1..Transmit data is requested

Definition at line 27851 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TDF_MASK

#define LPSPI_SR_TDF_MASK (0x1U)

Definition at line 27845 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TDF_SHIFT

#define LPSPI_SR_TDF_SHIFT (0U)

Definition at line 27846 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TEF

#define LPSPI_SR_TEF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)

TEF - Transmit Error Flag 0b0..Transmit FIFO underrun has not occurred 0b1..Transmit FIFO underrun has occurred

Definition at line 27886 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TEF_MASK

#define LPSPI_SR_TEF_MASK (0x800U)

Definition at line 27880 of file MIMXRT1062.h.

## ◆ LPSPI_SR_TEF_SHIFT

#define LPSPI_SR_TEF_SHIFT (11U)

Definition at line 27881 of file MIMXRT1062.h.

## ◆ LPSPI_SR_WCF

#define LPSPI_SR_WCF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)

WCF - Word Complete Flag 0b0..Transfer of a received word has not yet completed 0b1..Transfer of a received word has completed

Definition at line 27865 of file MIMXRT1062.h.

## ◆ LPSPI_SR_WCF_MASK

#define LPSPI_SR_WCF_MASK (0x100U)

Definition at line 27859 of file MIMXRT1062.h.

## ◆ LPSPI_SR_WCF_SHIFT

#define LPSPI_SR_WCF_SHIFT (8U)

Definition at line 27860 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_BYSW

#define LPSPI_TCR_BYSW | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)

BYSW - Byte Swap 0b0..Byte swap is disabled 0b1..Byte swap is enabled

Definition at line 28224 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_BYSW_MASK

#define LPSPI_TCR_BYSW_MASK (0x400000U)

Definition at line 28218 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_BYSW_SHIFT

#define LPSPI_TCR_BYSW_SHIFT (22U)

Definition at line 28219 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CONT

#define LPSPI_TCR_CONT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)

CONT - Continuous Transfer 0b0..Continuous transfer is disabled 0b1..Continuous transfer is enabled

Definition at line 28217 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CONT_MASK

#define LPSPI_TCR_CONT_MASK (0x200000U)

Definition at line 28211 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CONT_SHIFT

#define LPSPI_TCR_CONT_SHIFT (21U)

Definition at line 28212 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CONTC

#define LPSPI_TCR_CONTC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)

CONTC - Continuing Command 0b0..Command word for start of new transfer 0b1..Command word for continuing transfer

Definition at line 28210 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CONTC_MASK

#define LPSPI_TCR_CONTC_MASK (0x100000U)

Definition at line 28204 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CONTC_SHIFT

#define LPSPI_TCR_CONTC_SHIFT (20U)

Definition at line 28205 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CPHA

#define LPSPI_TCR_CPHA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)

CPHA - Clock Phase 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK

Definition at line 28260 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CPHA_MASK

#define LPSPI_TCR_CPHA_MASK (0x40000000U)

Definition at line 28254 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CPHA_SHIFT

#define LPSPI_TCR_CPHA_SHIFT (30U)

Definition at line 28255 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CPOL

#define LPSPI_TCR_CPOL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)

CPOL - Clock Polarity 0b0..The inactive state value of SCK is low 0b1..The inactive state value of SCK is high

Definition at line 28267 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CPOL_MASK

#define LPSPI_TCR_CPOL_MASK (0x80000000U)

Definition at line 28261 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_CPOL_SHIFT

#define LPSPI_TCR_CPOL_SHIFT (31U)

Definition at line 28262 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_FRAMESZ

#define LPSPI_TCR_FRAMESZ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)

FRAMESZ - Frame Size

Definition at line 28180 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_FRAMESZ_MASK

#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)

Definition at line 28176 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_FRAMESZ_SHIFT

#define LPSPI_TCR_FRAMESZ_SHIFT (0U)

Definition at line 28177 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_LSBF

#define LPSPI_TCR_LSBF | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)

LSBF - LSB First 0b0..Data is transferred MSB first 0b1..Data is transferred LSB first

Definition at line 28231 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_LSBF_MASK

#define LPSPI_TCR_LSBF_MASK (0x800000U)

Definition at line 28225 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_LSBF_SHIFT

#define LPSPI_TCR_LSBF_SHIFT (23U)

Definition at line 28226 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_PCS

#define LPSPI_TCR_PCS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)

PCS - Peripheral Chip Select 0b00..Transfer using LPSPI_PCS[0] 0b01..Transfer using LPSPI_PCS[1] 0b10..Transfer using LPSPI_PCS[2] 0b11..Transfer using LPSPI_PCS[3]

Definition at line 28240 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_PCS_MASK

#define LPSPI_TCR_PCS_MASK (0x3000000U)

Definition at line 28232 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_PCS_SHIFT

#define LPSPI_TCR_PCS_SHIFT (24U)

Definition at line 28233 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_PRESCALE

#define LPSPI_TCR_PRESCALE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)

PRESCALE - Prescaler Value 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

Definition at line 28253 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_PRESCALE_MASK

#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)

Definition at line 28241 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_PRESCALE_SHIFT

#define LPSPI_TCR_PRESCALE_SHIFT (27U)

Definition at line 28242 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_RXMSK

#define LPSPI_TCR_RXMSK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)

RXMSK - Receive Data Mask 0b0..Normal transfer 0b1..Receive data is masked

Definition at line 28203 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_RXMSK_MASK

#define LPSPI_TCR_RXMSK_MASK (0x80000U)

Definition at line 28197 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_RXMSK_SHIFT

#define LPSPI_TCR_RXMSK_SHIFT (19U)

Definition at line 28198 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_TXMSK

#define LPSPI_TCR_TXMSK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)

TXMSK - Transmit Data Mask 0b0..Normal transfer 0b1..Mask transmit data

Definition at line 28196 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_TXMSK_MASK

#define LPSPI_TCR_TXMSK_MASK (0x40000U)

Definition at line 28190 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_TXMSK_SHIFT

#define LPSPI_TCR_TXMSK_SHIFT (18U)

Definition at line 28191 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_WIDTH

#define LPSPI_TCR_WIDTH | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)

WIDTH - Transfer Width 0b00..1 bit transfer 0b01..2 bit transfer 0b10..4 bit transfer 0b11..Reserved

Definition at line 28189 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_WIDTH_MASK

#define LPSPI_TCR_WIDTH_MASK (0x30000U)

Definition at line 28181 of file MIMXRT1062.h.

## ◆ LPSPI_TCR_WIDTH_SHIFT

#define LPSPI_TCR_WIDTH_SHIFT (16U)

Definition at line 28182 of file MIMXRT1062.h.

## ◆ LPSPI_TDR_DATA

#define LPSPI_TDR_DATA | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)

DATA - Transmit Data

Definition at line 28276 of file MIMXRT1062.h.

## ◆ LPSPI_TDR_DATA_MASK

#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)

Definition at line 28272 of file MIMXRT1062.h.

## ◆ LPSPI_TDR_DATA_SHIFT

#define LPSPI_TDR_DATA_SHIFT (0U)

Definition at line 28273 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_FEATURE

#define LPSPI_VERID_FEATURE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)

FEATURE - Module Identification Number 0b0000000000000100..Standard feature set supporting a 32-bit shift register.

Definition at line 27765 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_FEATURE_MASK

#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)

Definition at line 27760 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_FEATURE_SHIFT

#define LPSPI_VERID_FEATURE_SHIFT (0U)

Definition at line 27761 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_MAJOR

#define LPSPI_VERID_MAJOR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)

MAJOR - Major Version Number

Definition at line 27775 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_MAJOR_MASK

#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)

Definition at line 27771 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_MAJOR_SHIFT

#define LPSPI_VERID_MAJOR_SHIFT (24U)

Definition at line 27772 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_MINOR

#define LPSPI_VERID_MINOR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)

MINOR - Minor Version Number

Definition at line 27770 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_MINOR_MASK

#define LPSPI_VERID_MINOR_MASK (0xFF0000U)

Definition at line 27766 of file MIMXRT1062.h.

## ◆ LPSPI_VERID_MINOR_SHIFT

#define LPSPI_VERID_MINOR_SHIFT (16U)

Definition at line 27767 of file MIMXRT1062.h.