Callisto4Bootloader: CMSIS/mpu_armv8.h Source File

Callisto4Bootloader

mpu_armv8.h
Go to the documentation of this file.
1 /******************************************************************************
2 * @file mpu_armv8.h
3 * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
4 * @version V5.1.0
5 * @date 08. March 2019
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef ARM_MPU_ARMV8_H
32 #define ARM_MPU_ARMV8_H
33
35 #define ARM_MPU_ATTR_DEVICE ( 0U )
36
38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39
46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
48
50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51
53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54
56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57
59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60
65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
66
68 #define ARM_MPU_SH_NON (0U)
69
71 #define ARM_MPU_SH_OUTER (2U)
72
74 #define ARM_MPU_SH_INNER (3U)
75
80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
81
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90 ((BASE & MPU_RBAR_BASE_Msk) | \
91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94
99 #define ARM_MPU_RLAR(LIMIT, IDX) \
100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102 (MPU_RLAR_EN_Msk))
103
104 #if defined(MPU_RLAR_PXN_Pos)
105
111 #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
112 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
113 ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
114 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
115 (MPU_RLAR_EN_Msk))
116
117 #endif
118
122 typedef struct {
123 uint32_t RBAR;
124 uint32_t RLAR;
125 } ARM_MPU_Region_t;
126
130 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
131 {
132 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
133 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
134 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
135 #endif
136 __DSB();
137 __ISB();
138 }
139
142 __STATIC_INLINE void ARM_MPU_Disable(void)
143 {
144 __DMB();
145 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
146 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
147 #endif
148 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
149 }
150
151 #ifdef MPU_NS
152
155 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
156 {
157 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
158 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
159 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
160 #endif
161 __DSB();
162 __ISB();
163 }
164
167 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
168 {
169 __DMB();
170 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
171 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
172 #endif
173 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
174 }
175 #endif
176
182 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
183 {
184 const uint8_t reg = idx / 4U;
185 const uint32_t pos = ((idx % 4U) * 8U);
186 const uint32_t mask = 0xFFU << pos;
187
188 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
189 return; // invalid index
190 }
191
192 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
193 }
194
199 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
200 {
201 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
202 }
203
204 #ifdef MPU_NS
205
209 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
210 {
211 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
212 }
213 #endif
214
219 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
220 {
221 mpu->RNR = rnr;
222 mpu->RLAR = 0U;
223 }
224
228 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
229 {
230 ARM_MPU_ClrRegionEx(MPU, rnr);
231 }
232
233 #ifdef MPU_NS
234
237 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
238 {
239 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
240 }
241 #endif
242
249 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
250 {
251 mpu->RNR = rnr;
252 mpu->RBAR = rbar;
253 mpu->RLAR = rlar;
254 }
255
261 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
262 {
263 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
264 }
265
266 #ifdef MPU_NS
267
272 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
273 {
274 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
275 }
276 #endif
277
283 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
284 {
285 uint32_t i;
286 for (i = 0U; i < len; ++i)
287 {
288 dst[i] = src[i];
289 }
290 }
291
298 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
299 {
300 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
301 if (cnt == 1U) {
302 mpu->RNR = rnr;
303 ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
304 } else {
305 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
306 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
307
308 mpu->RNR = rnrBase;
309 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
310 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
311 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
312 table += c;
313 cnt -= c;
314 rnrOffset = 0U;
315 rnrBase += MPU_TYPE_RALIASES;
316 mpu->RNR = rnrBase;
317 }
318
319 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
320 }
321 }
322
328 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
329 {
330 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
331 }
332
333 #ifdef MPU_NS
334
339 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
340 {
341 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
342 }
343 #endif
344
345 #endif
346
ARM_MPU_SetRegion
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
Definition: mpu_armv8.h:260
__RESTRICT
#define __RESTRICT
Definition: cmsis_armcc.h:105
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866
ARM_MPU_ClrRegionEx
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type *mpu, uint32_t rnr)
Definition: mpu_armv8.h:218
ARM_MPU_Region_t
Definition: mpu_armv7.h:182
SCB_SHCSR_MEMFAULTENA_Msk
#define SCB_SHCSR_MEMFAULTENA_Msk
Definition: core_armv81mml.h:694
i
volatile int i
Definition: excep_test.c:17
ARM_MPU_OrderedMemcpy
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
Definition: mpu_armv8.h:282
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
__DMB
__STATIC_FORCEINLINE void __DMB(void)
Data Memory Barrier.
Definition: cmsis_gcc.h:888
ARM_MPU_ClrRegion
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Definition: mpu_armv8.h:227
ARM_MPU_Region_t::RBAR
uint32_t RBAR
The region base address register value (RBAR)
Definition: mpu_armv7.h:183
ARM_MPU_SetMemAttr
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
Definition: mpu_armv8.h:198
ARM_MPU_LoadEx
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
Definition: mpu_armv8.h:297
ARM_MPU_SetMemAttrEx
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type *mpu, uint8_t idx, uint8_t attr)
Definition: mpu_armv8.h:181
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:63
ARM_MPU_Enable
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Definition: mpu_armv8.h:129
ARM_MPU_Disable
__STATIC_INLINE void ARM_MPU_Disable(void)
Definition: mpu_armv8.h:141
ARM_MPU_Load
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
Definition: mpu_armv8.h:327
SCB
#define SCB
Definition: core_armv81mml.h:2043
ARM_MPU_SetRegionEx
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
Definition: mpu_armv8.h:248