Callisto4Bootloader: device/MIMXRT1062.h Source File

Callisto4Bootloader

MIMXRT1062.h
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1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1062CVJ5A
4 ** MIMXRT1062CVL5A
5 ** MIMXRT1062DVJ6A
6 ** MIMXRT1062DVL6A
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
15 ** Version: rev. 1.2, 2019-04-29
16 ** Build: b191115
17 **
18 ** Abstract:
19 ** CMSIS Peripheral Access Layer for MIMXRT1062
20 **
21 ** Copyright 1997-2016 Freescale Semiconductor, Inc.
22 ** Copyright 2016-2019 NXP
23 ** All rights reserved.
24 **
25 ** SPDX-License-Identifier: BSD-3-Clause
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 0.1 (2017-01-10)
32 ** Initial version.
33 ** - rev. 1.0 (2018-11-16)
34 ** Update header files to align with IMXRT1060RM Rev.0.
35 ** - rev. 1.1 (2018-11-27)
36 ** Update header files to align with IMXRT1060RM Rev.1.
37 ** - rev. 1.2 (2019-04-29)
38 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
39 **
40 ** ###################################################################
41 */
42
52 #ifndef _MIMXRT1062_H_
53 #define _MIMXRT1062_H_
57 #define MCU_MEM_MAP_VERSION 0x0100U
58
59 #define MCU_MEM_MAP_VERSION_MINOR 0x0002U
60
61
62 /* ----------------------------------------------------------------------------
63 -- Interrupt vector numbers
64 ---------------------------------------------------------------------------- */
65
72 #define NUMBER_OF_INT_VECTORS 174
74 typedef enum IRQn {
75 /* Auxiliary constants */
76 NotAvail_IRQn = -128,
78 /* Core interrupts */
79 NonMaskableInt_IRQn = -14,
80 HardFault_IRQn = -13,
81 MemoryManagement_IRQn = -12,
82 BusFault_IRQn = -11,
83 UsageFault_IRQn = -10,
84 SVCall_IRQn = -5,
85 DebugMonitor_IRQn = -4,
86 PendSV_IRQn = -2,
87 SysTick_IRQn = -1,
89 /* Device specific interrupts */
90 DMA0_DMA16_IRQn = 0,
91 DMA1_DMA17_IRQn = 1,
92 DMA2_DMA18_IRQn = 2,
93 DMA3_DMA19_IRQn = 3,
94 DMA4_DMA20_IRQn = 4,
95 DMA5_DMA21_IRQn = 5,
96 DMA6_DMA22_IRQn = 6,
97 DMA7_DMA23_IRQn = 7,
98 DMA8_DMA24_IRQn = 8,
99 DMA9_DMA25_IRQn = 9,
100 DMA10_DMA26_IRQn = 10,
101 DMA11_DMA27_IRQn = 11,
102 DMA12_DMA28_IRQn = 12,
103 DMA13_DMA29_IRQn = 13,
104 DMA14_DMA30_IRQn = 14,
105 DMA15_DMA31_IRQn = 15,
106 DMA_ERROR_IRQn = 16,
107 CTI0_ERROR_IRQn = 17,
108 CTI1_ERROR_IRQn = 18,
109 CORE_IRQn = 19,
110 LPUART1_IRQn = 20,
111 LPUART2_IRQn = 21,
112 LPUART3_IRQn = 22,
113 LPUART4_IRQn = 23,
114 LPUART5_IRQn = 24,
115 LPUART6_IRQn = 25,
116 LPUART7_IRQn = 26,
117 LPUART8_IRQn = 27,
118 LPI2C1_IRQn = 28,
119 LPI2C2_IRQn = 29,
120 LPI2C3_IRQn = 30,
121 LPI2C4_IRQn = 31,
122 LPSPI1_IRQn = 32,
123 LPSPI2_IRQn = 33,
124 LPSPI3_IRQn = 34,
125 LPSPI4_IRQn = 35,
126 CAN1_IRQn = 36,
127 CAN2_IRQn = 37,
128 FLEXRAM_IRQn = 38,
129 KPP_IRQn = 39,
130 TSC_DIG_IRQn = 40,
131 GPR_IRQ_IRQn = 41,
132 LCDIF_IRQn = 42,
133 CSI_IRQn = 43,
134 PXP_IRQn = 44,
135 WDOG2_IRQn = 45,
136 SNVS_HP_WRAPPER_IRQn = 46,
137 SNVS_HP_WRAPPER_TZ_IRQn = 47,
138 SNVS_LP_WRAPPER_IRQn = 48,
139 CSU_IRQn = 49,
140 DCP_IRQn = 50,
141 DCP_VMI_IRQn = 51,
142 Reserved68_IRQn = 52,
143 TRNG_IRQn = 53,
144 SJC_IRQn = 54,
145 BEE_IRQn = 55,
146 SAI1_IRQn = 56,
147 SAI2_IRQn = 57,
148 SAI3_RX_IRQn = 58,
149 SAI3_TX_IRQn = 59,
150 SPDIF_IRQn = 60,
151 PMU_EVENT_IRQn = 61,
152 Reserved78_IRQn = 62,
153 TEMP_LOW_HIGH_IRQn = 63,
154 TEMP_PANIC_IRQn = 64,
155 USB_PHY1_IRQn = 65,
156 USB_PHY2_IRQn = 66,
157 ADC1_IRQn = 67,
158 ADC2_IRQn = 68,
159 DCDC_IRQn = 69,
160 Reserved86_IRQn = 70,
161 Reserved87_IRQn = 71,
162 GPIO1_INT0_IRQn = 72,
163 GPIO1_INT1_IRQn = 73,
164 GPIO1_INT2_IRQn = 74,
165 GPIO1_INT3_IRQn = 75,
166 GPIO1_INT4_IRQn = 76,
167 GPIO1_INT5_IRQn = 77,
168 GPIO1_INT6_IRQn = 78,
169 GPIO1_INT7_IRQn = 79,
170 GPIO1_Combined_0_15_IRQn = 80,
171 GPIO1_Combined_16_31_IRQn = 81,
172 GPIO2_Combined_0_15_IRQn = 82,
173 GPIO2_Combined_16_31_IRQn = 83,
174 GPIO3_Combined_0_15_IRQn = 84,
175 GPIO3_Combined_16_31_IRQn = 85,
176 GPIO4_Combined_0_15_IRQn = 86,
177 GPIO4_Combined_16_31_IRQn = 87,
178 GPIO5_Combined_0_15_IRQn = 88,
179 GPIO5_Combined_16_31_IRQn = 89,
180 FLEXIO1_IRQn = 90,
181 FLEXIO2_IRQn = 91,
182 WDOG1_IRQn = 92,
183 RTWDOG_IRQn = 93,
184 EWM_IRQn = 94,
185 CCM_1_IRQn = 95,
186 CCM_2_IRQn = 96,
187 GPC_IRQn = 97,
188 SRC_IRQn = 98,
189 Reserved115_IRQn = 99,
190 GPT1_IRQn = 100,
191 GPT2_IRQn = 101,
192 PWM1_0_IRQn = 102,
193 PWM1_1_IRQn = 103,
194 PWM1_2_IRQn = 104,
195 PWM1_3_IRQn = 105,
196 PWM1_FAULT_IRQn = 106,
197 FLEXSPI2_IRQn = 107,
198 FLEXSPI_IRQn = 108,
199 SEMC_IRQn = 109,
200 USDHC1_IRQn = 110,
201 USDHC2_IRQn = 111,
202 USB_OTG2_IRQn = 112,
203 USB_OTG1_IRQn = 113,
204 ENET_IRQn = 114,
205 ENET_1588_Timer_IRQn = 115,
206 XBAR1_IRQ_0_1_IRQn = 116,
207 XBAR1_IRQ_2_3_IRQn = 117,
208 ADC_ETC_IRQ0_IRQn = 118,
209 ADC_ETC_IRQ1_IRQn = 119,
210 ADC_ETC_IRQ2_IRQn = 120,
211 ADC_ETC_ERROR_IRQ_IRQn = 121,
212 PIT_IRQn = 122,
213 ACMP1_IRQn = 123,
214 ACMP2_IRQn = 124,
215 ACMP3_IRQn = 125,
216 ACMP4_IRQn = 126,
217 Reserved143_IRQn = 127,
218 Reserved144_IRQn = 128,
219 ENC1_IRQn = 129,
220 ENC2_IRQn = 130,
221 ENC3_IRQn = 131,
222 ENC4_IRQn = 132,
223 TMR1_IRQn = 133,
224 TMR2_IRQn = 134,
225 TMR3_IRQn = 135,
226 TMR4_IRQn = 136,
227 PWM2_0_IRQn = 137,
228 PWM2_1_IRQn = 138,
229 PWM2_2_IRQn = 139,
230 PWM2_3_IRQn = 140,
231 PWM2_FAULT_IRQn = 141,
232 PWM3_0_IRQn = 142,
233 PWM3_1_IRQn = 143,
234 PWM3_2_IRQn = 144,
235 PWM3_3_IRQn = 145,
236 PWM3_FAULT_IRQn = 146,
237 PWM4_0_IRQn = 147,
238 PWM4_1_IRQn = 148,
239 PWM4_2_IRQn = 149,
240 PWM4_3_IRQn = 150,
241 PWM4_FAULT_IRQn = 151,
242 ENET2_IRQn = 152,
243 ENET2_1588_Timer_IRQn = 153,
244 CAN3_IRQn = 154,
245 Reserved171_IRQn = 155,
246 FLEXIO3_IRQn = 156,
247 GPIO6_7_8_9_IRQn = 157
248 } IRQn_Type;
249 /* end of group Interrupt_vector_numbers */
253
254
255 /* ----------------------------------------------------------------------------
256 -- Cortex M7 Core Configuration
257 ---------------------------------------------------------------------------- */
258
264 #define __MPU_PRESENT 1
265 #define __ICACHE_PRESENT 1
266 #define __DCACHE_PRESENT 1
267 #define __DTCM_PRESENT 1
268 #define __NVIC_PRIO_BITS 4
269 #define __Vendor_SysTickConfig 0
270 #define __FPU_PRESENT 1
272 #include "core_cm7.h" /* Core Peripheral Access Layer */
273 #include "system_MIMXRT1062.h" /* Device specific configuration file */
274 /* end of group Cortex_Core_Configuration */
278
279
280 /* ----------------------------------------------------------------------------
281 -- Mapping Information
282 ---------------------------------------------------------------------------- */
283
295 /*******************************************************************************
296 * Definitions
297 ******************************************************************************/
298
306 typedef enum _dma_request_source
307 {
308 kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U,
309 kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U,
310 kDmaRequestMuxLPUART1Tx = 2|0x100U,
311 kDmaRequestMuxLPUART1Rx = 3|0x100U,
312 kDmaRequestMuxLPUART3Tx = 4|0x100U,
313 kDmaRequestMuxLPUART3Rx = 5|0x100U,
314 kDmaRequestMuxLPUART5Tx = 6|0x100U,
315 kDmaRequestMuxLPUART5Rx = 7|0x100U,
316 kDmaRequestMuxLPUART7Tx = 8|0x100U,
317 kDmaRequestMuxLPUART7Rx = 9|0x100U,
318 kDmaRequestMuxCAN3 = 11|0x100U,
319 kDmaRequestMuxCSI = 12|0x100U,
320 kDmaRequestMuxLPSPI1Rx = 13|0x100U,
321 kDmaRequestMuxLPSPI1Tx = 14|0x100U,
322 kDmaRequestMuxLPSPI3Rx = 15|0x100U,
323 kDmaRequestMuxLPSPI3Tx = 16|0x100U,
324 kDmaRequestMuxLPI2C1 = 17|0x100U,
325 kDmaRequestMuxLPI2C3 = 18|0x100U,
326 kDmaRequestMuxSai1Rx = 19|0x100U,
327 kDmaRequestMuxSai1Tx = 20|0x100U,
328 kDmaRequestMuxSai2Rx = 21|0x100U,
329 kDmaRequestMuxSai2Tx = 22|0x100U,
330 kDmaRequestMuxADC_ETC = 23|0x100U,
331 kDmaRequestMuxADC1 = 24|0x100U,
332 kDmaRequestMuxACMP1 = 25|0x100U,
333 kDmaRequestMuxACMP3 = 26|0x100U,
334 kDmaRequestMuxFlexSPIRx = 28|0x100U,
335 kDmaRequestMuxFlexSPITx = 29|0x100U,
336 kDmaRequestMuxXBAR1Request0 = 30|0x100U,
337 kDmaRequestMuxXBAR1Request1 = 31|0x100U,
338 kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U,
339 kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U,
340 kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U,
341 kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U,
342 kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U,
343 kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U,
344 kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U,
345 kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U,
346 kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U,
347 kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U,
348 kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U,
349 kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U,
350 kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U,
351 kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U,
352 kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U,
353 kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U,
354 kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U,
355 kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,
356 kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U,
357 kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U,
358 kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U,
359 kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U,
360 kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U,
361 kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U,
362 kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U,
363 kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U,
364 kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U,
365 kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U,
366 kDmaRequestMuxFlexSPI2Rx = 60|0x100U,
367 kDmaRequestMuxFlexSPI2Tx = 61|0x100U,
368 kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U,
369 kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U,
370 kDmaRequestMuxLPUART2Tx = 66|0x100U,
371 kDmaRequestMuxLPUART2Rx = 67|0x100U,
372 kDmaRequestMuxLPUART4Tx = 68|0x100U,
373 kDmaRequestMuxLPUART4Rx = 69|0x100U,
374 kDmaRequestMuxLPUART6Tx = 70|0x100U,
375 kDmaRequestMuxLPUART6Rx = 71|0x100U,
376 kDmaRequestMuxLPUART8Tx = 72|0x100U,
377 kDmaRequestMuxLPUART8Rx = 73|0x100U,
378 kDmaRequestMuxPxp = 75|0x100U,
379 kDmaRequestMuxLCDIF = 76|0x100U,
380 kDmaRequestMuxLPSPI2Rx = 77|0x100U,
381 kDmaRequestMuxLPSPI2Tx = 78|0x100U,
382 kDmaRequestMuxLPSPI4Rx = 79|0x100U,
383 kDmaRequestMuxLPSPI4Tx = 80|0x100U,
384 kDmaRequestMuxLPI2C2 = 81|0x100U,
385 kDmaRequestMuxLPI2C4 = 82|0x100U,
386 kDmaRequestMuxSai3Rx = 83|0x100U,
387 kDmaRequestMuxSai3Tx = 84|0x100U,
388 kDmaRequestMuxSpdifRx = 85|0x100U,
389 kDmaRequestMuxSpdifTx = 86|0x100U,
390 kDmaRequestMuxADC2 = 88|0x100U,
391 kDmaRequestMuxACMP2 = 89|0x100U,
392 kDmaRequestMuxACMP4 = 90|0x100U,
393 kDmaRequestMuxEnetTimer0 = 92|0x100U,
394 kDmaRequestMuxEnetTimer1 = 93|0x100U,
395 kDmaRequestMuxXBAR1Request2 = 94|0x100U,
396 kDmaRequestMuxXBAR1Request3 = 95|0x100U,
397 kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U,
398 kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U,
399 kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U,
400 kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U,
401 kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U,
402 kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U,
403 kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U,
404 kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U,
405 kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U,
406 kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U,
407 kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U,
408 kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U,
409 kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U,
410 kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U,
411 kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U,
412 kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U,
413 kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U,
414 kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U,
415 kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,
416 kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U,
417 kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U,
418 kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U,
419 kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U,
420 kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U,
421 kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U,
422 kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U,
423 kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U,
424 kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U,
425 kDmaRequestMuxEnet2Timer0 = 124|0x100U,
426 kDmaRequestMuxEnet2Timer1 = 125|0x100U,
427 } dma_request_source_t;
428
429 /* @} */
430
435 /*******************************************************************************
436 * Definitions
437 *******************************************************************************/
438
444 typedef enum _iomuxc_sw_mux_ctl_pad
445 {
446 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U,
447 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U,
448 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U,
449 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U,
450 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U,
451 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U,
452 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U,
453 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U,
454 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U,
455 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U,
456 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U,
457 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U,
458 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U,
459 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U,
460 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U,
461 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U,
462 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U,
463 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U,
464 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U,
465 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U,
466 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U,
467 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U,
468 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U,
469 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U,
470 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U,
471 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U,
472 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U,
473 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U,
474 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U,
475 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U,
476 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U,
477 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U,
478 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U,
479 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U,
480 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U,
481 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U,
482 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U,
483 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U,
484 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U,
485 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U,
486 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U,
487 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U,
488 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U,
489 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U,
490 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U,
491 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U,
492 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U,
493 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U,
494 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U,
495 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U,
496 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U,
497 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U,
498 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U,
499 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U,
500 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U,
501 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U,
502 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U,
503 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U,
504 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U,
505 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U,
506 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U,
507 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U,
508 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U,
509 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U,
510 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U,
511 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U,
512 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U,
513 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U,
514 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U,
515 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U,
516 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U,
517 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U,
518 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U,
519 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U,
520 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U,
521 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U,
522 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U,
523 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U,
524 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U,
525 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U,
526 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U,
527 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U,
528 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U,
529 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U,
530 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U,
531 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U,
532 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U,
533 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U,
534 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U,
535 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U,
536 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U,
537 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U,
538 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U,
539 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U,
540 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U,
541 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U,
542 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U,
543 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U,
544 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U,
545 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U,
546 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U,
547 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U,
548 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U,
549 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U,
550 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U,
551 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U,
552 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U,
553 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U,
554 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U,
555 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U,
556 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U,
557 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U,
558 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U,
559 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U,
560 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U,
561 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U,
562 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U,
563 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U,
564 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U,
565 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U,
566 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U,
567 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U,
568 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U,
569 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U,
570 } iomuxc_sw_mux_ctl_pad_t;
571
572 /* @} */
573
578 /*******************************************************************************
579 * Definitions
580 *******************************************************************************/
581
587 typedef enum _iomuxc_sw_mux_ctl_pad_1
588 {
589 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00 = 0U,
590 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01 = 1U,
591 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02 = 2U,
592 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03 = 3U,
593 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04 = 4U,
594 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05 = 5U,
595 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06 = 6U,
596 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07 = 7U,
597 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08 = 8U,
598 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09 = 9U,
599 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10 = 10U,
600 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11 = 11U,
601 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12 = 12U,
602 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13 = 13U,
603 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00 = 14U,
604 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01 = 15U,
605 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02 = 16U,
606 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03 = 17U,
607 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04 = 18U,
608 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05 = 19U,
609 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06 = 20U,
610 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07 = 21U,
611 } iomuxc_sw_mux_ctl_pad_1_t;
612
613 /* @} */
614
619 /*******************************************************************************
620 * Definitions
621 *******************************************************************************/
622
628 typedef enum _iomuxc_sw_pad_ctl_pad
629 {
630 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U,
631 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U,
632 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U,
633 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U,
634 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U,
635 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U,
636 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U,
637 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U,
638 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U,
639 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U,
640 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U,
641 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U,
642 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U,
643 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U,
644 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U,
645 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U,
646 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U,
647 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U,
648 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U,
649 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U,
650 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U,
651 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U,
652 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U,
653 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U,
654 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U,
655 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U,
656 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U,
657 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U,
658 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U,
659 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U,
660 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U,
661 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U,
662 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U,
663 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U,
664 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U,
665 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U,
666 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U,
667 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U,
668 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U,
669 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U,
670 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U,
671 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U,
672 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U,
673 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U,
674 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U,
675 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U,
676 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U,
677 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U,
678 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U,
679 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U,
680 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U,
681 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U,
682 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U,
683 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U,
684 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U,
685 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U,
686 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U,
687 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U,
688 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U,
689 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U,
690 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U,
691 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U,
692 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U,
693 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U,
694 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U,
695 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U,
696 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U,
697 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U,
698 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U,
699 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U,
700 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U,
701 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U,
702 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U,
703 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U,
704 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U,
705 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U,
706 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U,
707 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U,
708 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U,
709 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U,
710 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U,
711 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U,
712 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U,
713 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U,
714 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U,
715 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U,
716 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U,
717 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U,
718 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U,
719 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U,
720 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U,
721 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U,
722 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U,
723 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U,
724 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U,
725 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U,
726 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U,
727 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U,
728 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U,
729 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U,
730 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U,
731 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U,
732 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U,
733 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U,
734 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U,
735 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U,
736 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U,
737 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U,
738 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U,
739 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U,
740 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U,
741 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U,
742 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U,
743 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U,
744 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U,
745 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U,
746 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U,
747 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U,
748 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U,
749 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U,
750 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U,
751 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U,
752 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U,
753 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U,
754 } iomuxc_sw_pad_ctl_pad_t;
755
756 /* @} */
757
762 /*******************************************************************************
763 * Definitions
764 *******************************************************************************/
765
771 typedef enum _iomuxc_sw_pad_ctl_pad_1
772 {
773 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00 = 0U,
774 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01 = 1U,
775 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02 = 2U,
776 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03 = 3U,
777 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04 = 4U,
778 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05 = 5U,
779 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06 = 6U,
780 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07 = 7U,
781 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08 = 8U,
782 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09 = 9U,
783 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10 = 10U,
784 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11 = 11U,
785 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12 = 12U,
786 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13 = 13U,
787 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00 = 14U,
788 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01 = 15U,
789 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02 = 16U,
790 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03 = 17U,
791 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04 = 18U,
792 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05 = 19U,
793 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06 = 20U,
794 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07 = 21U,
795 } iomuxc_sw_pad_ctl_pad_1_t;
796
797 /* @} */
798
804 typedef enum _iomuxc_select_input
805 {
806 kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U,
807 kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U,
808 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U,
809 kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U,
810 kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U,
811 kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U,
812 kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U,
813 kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U,
814 kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U,
815 kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U,
816 kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U,
817 kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U,
818 kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U,
819 kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U,
820 kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U,
821 kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U,
822 kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U,
823 kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U,
824 kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U,
825 kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U,
826 kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U,
827 kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U,
828 kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U,
829 kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U,
830 kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U,
831 kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U,
832 kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U,
833 kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U,
834 kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U,
835 kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U,
836 kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U,
837 kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U,
838 kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U,
839 kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U,
840 kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U,
841 kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U,
842 kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U,
843 kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U,
844 kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U,
845 kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U,
846 kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U,
847 kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U,
848 kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U,
849 kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U,
850 kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U,
851 kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U,
852 kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U,
853 kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U,
854 kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U,
855 kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U,
856 kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U,
857 kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U,
858 kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U,
859 kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U,
860 kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U,
861 kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U,
862 kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U,
863 kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U,
864 kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U,
865 kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U,
866 kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U,
867 kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U,
868 kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U,
869 kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U,
870 kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U,
871 kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U,
872 kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U,
873 kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U,
874 kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U,
875 kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U,
876 kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U,
877 kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U,
878 kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U,
879 kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U,
880 kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U,
881 kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U,
882 kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U,
883 kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U,
884 kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U,
885 kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U,
886 kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U,
887 kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U,
888 kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U,
889 kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U,
890 kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U,
891 kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U,
892 kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U,
893 kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U,
894 kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U,
895 kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U,
896 kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U,
897 kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U,
898 kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U,
899 kIOMUXC_NMI_SELECT_INPUT = 93U,
900 kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U,
901 kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U,
902 kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U,
903 kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U,
904 kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U,
905 kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U,
906 kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U,
907 kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U,
908 kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U,
909 kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U,
910 kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U,
911 kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U,
912 kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U,
913 kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U,
914 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U,
915 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U,
916 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U,
917 kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U,
918 kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U,
919 kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U,
920 kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U,
921 kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U,
922 kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U,
923 kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U,
924 kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U,
925 kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U,
926 kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U,
927 kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U,
928 kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U,
929 kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U,
930 kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U,
931 kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U,
932 kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U,
933 kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U,
934 kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U,
935 kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U,
936 kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U,
937 kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U,
938 kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U,
939 kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U,
940 kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U,
941 kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U,
942 kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U,
943 kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U,
944 kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U,
945 kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U,
946 kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U,
947 kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U,
948 kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U,
949 kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U,
950 kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U,
951 kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U,
952 kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U,
953 kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U,
954 kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U,
955 kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U,
956 kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U,
957 kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U,
958 kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U,
959 kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U,
960 } iomuxc_select_input_t;
961
967 typedef enum _iomuxc_select_input_1
968 {
969 kIOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT = 0U,
970 kIOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT = 1U,
971 kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 = 2U,
972 kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 = 3U,
973 kIOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT = 4U,
974 kIOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT = 5U,
975 kIOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 = 6U,
976 kIOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT = 7U,
977 kIOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT = 8U,
978 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 9U,
979 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 10U,
980 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 11U,
981 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 12U,
982 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT = 13U,
983 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT = 14U,
984 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT = 15U,
985 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT = 16U,
986 kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT = 17U,
987 kIOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT = 18U,
988 kIOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT = 19U,
989 kIOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT = 20U,
990 kIOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT = 21U,
991 kIOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT = 22U,
992 kIOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT = 23U,
993 kIOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT = 24U,
994 kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 25U,
995 kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 26U,
996 kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 27U,
997 kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 28U,
998 kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 29U,
999 kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 30U,
1000 kIOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT = 31U,
1001 kIOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT = 32U,
1002 } iomuxc_select_input_1_t;
1003
1004 typedef enum _xbar_input_signal
1005 {
1006 kXBARA1_InputLogicLow = 0|0x100U,
1007 kXBARA1_InputLogicHigh = 1|0x100U,
1008 kXBARA1_InputIomuxXbarIn02 = 2|0x100U,
1009 kXBARA1_InputIomuxXbarIn03 = 3|0x100U,
1010 kXBARA1_InputIomuxXbarInout04 = 4|0x100U,
1011 kXBARA1_InputIomuxXbarInout05 = 5|0x100U,
1012 kXBARA1_InputIomuxXbarInout06 = 6|0x100U,
1013 kXBARA1_InputIomuxXbarInout07 = 7|0x100U,
1014 kXBARA1_InputIomuxXbarInout08 = 8|0x100U,
1015 kXBARA1_InputIomuxXbarInout09 = 9|0x100U,
1016 kXBARA1_InputIomuxXbarInout10 = 10|0x100U,
1017 kXBARA1_InputIomuxXbarInout11 = 11|0x100U,
1018 kXBARA1_InputIomuxXbarInout12 = 12|0x100U,
1019 kXBARA1_InputIomuxXbarInout13 = 13|0x100U,
1020 kXBARA1_InputIomuxXbarInout14 = 14|0x100U,
1021 kXBARA1_InputIomuxXbarInout15 = 15|0x100U,
1022 kXBARA1_InputIomuxXbarInout16 = 16|0x100U,
1023 kXBARA1_InputIomuxXbarInout17 = 17|0x100U,
1024 kXBARA1_InputIomuxXbarInout18 = 18|0x100U,
1025 kXBARA1_InputIomuxXbarInout19 = 19|0x100U,
1026 kXBARA1_InputIomuxXbarIn20 = 20|0x100U,
1027 kXBARA1_InputIomuxXbarIn21 = 21|0x100U,
1028 kXBARA1_InputIomuxXbarIn22 = 22|0x100U,
1029 kXBARA1_InputIomuxXbarIn23 = 23|0x100U,
1030 kXBARA1_InputIomuxXbarIn24 = 24|0x100U,
1031 kXBARA1_InputIomuxXbarIn25 = 25|0x100U,
1032 kXBARA1_InputAcmp1Out = 26|0x100U,
1033 kXBARA1_InputAcmp2Out = 27|0x100U,
1034 kXBARA1_InputAcmp3Out = 28|0x100U,
1035 kXBARA1_InputAcmp4Out = 29|0x100U,
1036 kXBARA1_InputRESERVED30 = 30|0x100U,
1037 kXBARA1_InputRESERVED31 = 31|0x100U,
1038 kXBARA1_InputQtimer3Tmr0Output = 32|0x100U,
1039 kXBARA1_InputQtimer3Tmr1Output = 33|0x100U,
1040 kXBARA1_InputQtimer3Tmr2Output = 34|0x100U,
1041 kXBARA1_InputQtimer3Tmr3Output = 35|0x100U,
1042 kXBARA1_InputQtimer4Tmr0Output = 36|0x100U,
1043 kXBARA1_InputQtimer4Tmr1Output = 37|0x100U,
1044 kXBARA1_InputQtimer4Tmr2Output = 38|0x100U,
1045 kXBARA1_InputQtimer4Tmr3Output = 39|0x100U,
1046 kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U,
1047 kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U,
1048 kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U,
1049 kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U,
1050 kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U,
1051 kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U,
1052 kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U,
1053 kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U,
1054 kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U,
1055 kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U,
1056 kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U,
1057 kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U,
1058 kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U,
1059 kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U,
1060 kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U,
1061 kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U,
1062 kXBARA1_InputPitTrigger0 = 56|0x100U,
1063 kXBARA1_InputPitTrigger1 = 57|0x100U,
1064 kXBARA1_InputPitTrigger2 = 58|0x100U,
1065 kXBARA1_InputPitTrigger3 = 59|0x100U,
1066 kXBARA1_InputEnc1PosMatch = 60|0x100U,
1067 kXBARA1_InputEnc2PosMatch = 61|0x100U,
1068 kXBARA1_InputEnc3PosMatch = 62|0x100U,
1069 kXBARA1_InputEnc4PosMatch = 63|0x100U,
1070 kXBARA1_InputDmaDone0 = 64|0x100U,
1071 kXBARA1_InputDmaDone1 = 65|0x100U,
1072 kXBARA1_InputDmaDone2 = 66|0x100U,
1073 kXBARA1_InputDmaDone3 = 67|0x100U,
1074 kXBARA1_InputDmaDone4 = 68|0x100U,
1075 kXBARA1_InputDmaDone5 = 69|0x100U,
1076 kXBARA1_InputDmaDone6 = 70|0x100U,
1077 kXBARA1_InputDmaDone7 = 71|0x100U,
1078 kXBARA1_InputAoi1Out0 = 72|0x100U,
1079 kXBARA1_InputAoi1Out1 = 73|0x100U,
1080 kXBARA1_InputAoi1Out2 = 74|0x100U,
1081 kXBARA1_InputAoi1Out3 = 75|0x100U,
1082 kXBARA1_InputAoi2Out0 = 76|0x100U,
1083 kXBARA1_InputAoi2Out1 = 77|0x100U,
1084 kXBARA1_InputAoi2Out2 = 78|0x100U,
1085 kXBARA1_InputAoi2Out3 = 79|0x100U,
1086 kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U,
1087 kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U,
1088 kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U,
1089 kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U,
1090 kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U,
1091 kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U,
1092 kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U,
1093 kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U,
1094 kXBARB2_InputLogicLow = 0|0x200U,
1095 kXBARB2_InputLogicHigh = 1|0x200U,
1096 kXBARB2_InputRESERVED2 = 2|0x200U,
1097 kXBARB2_InputRESERVED3 = 3|0x200U,
1098 kXBARB2_InputRESERVED4 = 4|0x200U,
1099 kXBARB2_InputRESERVED5 = 5|0x200U,
1100 kXBARB2_InputAcmp1Out = 6|0x200U,
1101 kXBARB2_InputAcmp2Out = 7|0x200U,
1102 kXBARB2_InputAcmp3Out = 8|0x200U,
1103 kXBARB2_InputAcmp4Out = 9|0x200U,
1104 kXBARB2_InputRESERVED10 = 10|0x200U,
1105 kXBARB2_InputRESERVED11 = 11|0x200U,
1106 kXBARB2_InputQtimer3Tmr0Output = 12|0x200U,
1107 kXBARB2_InputQtimer3Tmr1Output = 13|0x200U,
1108 kXBARB2_InputQtimer3Tmr2Output = 14|0x200U,
1109 kXBARB2_InputQtimer3Tmr3Output = 15|0x200U,
1110 kXBARB2_InputQtimer4Tmr0Output = 16|0x200U,
1111 kXBARB2_InputQtimer4Tmr1Output = 17|0x200U,
1112 kXBARB2_InputQtimer4Tmr2Output = 18|0x200U,
1113 kXBARB2_InputQtimer4Tmr3Output = 19|0x200U,
1114 kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U,
1115 kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U,
1116 kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U,
1117 kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U,
1118 kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U,
1119 kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U,
1120 kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U,
1121 kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U,
1122 kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U,
1123 kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U,
1124 kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U,
1125 kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U,
1126 kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U,
1127 kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U,
1128 kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U,
1129 kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U,
1130 kXBARB2_InputPitTrigger0 = 36|0x200U,
1131 kXBARB2_InputPitTrigger1 = 37|0x200U,
1132 kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U,
1133 kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U,
1134 kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U,
1135 kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U,
1136 kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U,
1137 kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U,
1138 kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U,
1139 kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U,
1140 kXBARB2_InputEnc1PosMatch = 46|0x200U,
1141 kXBARB2_InputEnc2PosMatch = 47|0x200U,
1142 kXBARB2_InputEnc3PosMatch = 48|0x200U,
1143 kXBARB2_InputEnc4PosMatch = 49|0x200U,
1144 kXBARB2_InputDmaDone0 = 50|0x200U,
1145 kXBARB2_InputDmaDone1 = 51|0x200U,
1146 kXBARB2_InputDmaDone2 = 52|0x200U,
1147 kXBARB2_InputDmaDone3 = 53|0x200U,
1148 kXBARB2_InputDmaDone4 = 54|0x200U,
1149 kXBARB2_InputDmaDone5 = 55|0x200U,
1150 kXBARB2_InputDmaDone6 = 56|0x200U,
1151 kXBARB2_InputDmaDone7 = 57|0x200U,
1152 kXBARB3_InputLogicLow = 0|0x300U,
1153 kXBARB3_InputLogicHigh = 1|0x300U,
1154 kXBARB3_InputRESERVED2 = 2|0x300U,
1155 kXBARB3_InputRESERVED3 = 3|0x300U,
1156 kXBARB3_InputRESERVED4 = 4|0x300U,
1157 kXBARB3_InputRESERVED5 = 5|0x300U,
1158 kXBARB3_InputAcmp1Out = 6|0x300U,
1159 kXBARB3_InputAcmp2Out = 7|0x300U,
1160 kXBARB3_InputAcmp3Out = 8|0x300U,
1161 kXBARB3_InputAcmp4Out = 9|0x300U,
1162 kXBARB3_InputRESERVED10 = 10|0x300U,
1163 kXBARB3_InputRESERVED11 = 11|0x300U,
1164 kXBARB3_InputQtimer3Tmr0Output = 12|0x300U,
1165 kXBARB3_InputQtimer3Tmr1Output = 13|0x300U,
1166 kXBARB3_InputQtimer3Tmr2Output = 14|0x300U,
1167 kXBARB3_InputQtimer3Tmr3Output = 15|0x300U,
1168 kXBARB3_InputQtimer4Tmr0Output = 16|0x300U,
1169 kXBARB3_InputQtimer4Tmr1Output = 17|0x300U,
1170 kXBARB3_InputQtimer4Tmr2Output = 18|0x300U,
1171 kXBARB3_InputQtimer4Tmr3Output = 19|0x300U,
1172 kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U,
1173 kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U,
1174 kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U,
1175 kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U,
1176 kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U,
1177 kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U,
1178 kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U,
1179 kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U,
1180 kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U,
1181 kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U,
1182 kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U,
1183 kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U,
1184 kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U,
1185 kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U,
1186 kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U,
1187 kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U,
1188 kXBARB3_InputPitTrigger0 = 36|0x300U,
1189 kXBARB3_InputPitTrigger1 = 37|0x300U,
1190 kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U,
1191 kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U,
1192 kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U,
1193 kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U,
1194 kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U,
1195 kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U,
1196 kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U,
1197 kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U,
1198 kXBARB3_InputEnc1PosMatch = 46|0x300U,
1199 kXBARB3_InputEnc2PosMatch = 47|0x300U,
1200 kXBARB3_InputEnc3PosMatch = 48|0x300U,
1201 kXBARB3_InputEnc4PosMatch = 49|0x300U,
1202 kXBARB3_InputDmaDone0 = 50|0x300U,
1203 kXBARB3_InputDmaDone1 = 51|0x300U,
1204 kXBARB3_InputDmaDone2 = 52|0x300U,
1205 kXBARB3_InputDmaDone3 = 53|0x300U,
1206 kXBARB3_InputDmaDone4 = 54|0x300U,
1207 kXBARB3_InputDmaDone5 = 55|0x300U,
1208 kXBARB3_InputDmaDone6 = 56|0x300U,
1209 kXBARB3_InputDmaDone7 = 57|0x300U,
1210 } xbar_input_signal_t;
1211
1212 typedef enum _xbar_output_signal
1213 {
1214 kXBARA1_OutputDmaChMuxReq30 = 0|0x100U,
1215 kXBARA1_OutputDmaChMuxReq31 = 1|0x100U,
1216 kXBARA1_OutputDmaChMuxReq94 = 2|0x100U,
1217 kXBARA1_OutputDmaChMuxReq95 = 3|0x100U,
1218 kXBARA1_OutputIomuxXbarInout04 = 4|0x100U,
1219 kXBARA1_OutputIomuxXbarInout05 = 5|0x100U,
1220 kXBARA1_OutputIomuxXbarInout06 = 6|0x100U,
1221 kXBARA1_OutputIomuxXbarInout07 = 7|0x100U,
1222 kXBARA1_OutputIomuxXbarInout08 = 8|0x100U,
1223 kXBARA1_OutputIomuxXbarInout09 = 9|0x100U,
1224 kXBARA1_OutputIomuxXbarInout10 = 10|0x100U,
1225 kXBARA1_OutputIomuxXbarInout11 = 11|0x100U,
1226 kXBARA1_OutputIomuxXbarInout12 = 12|0x100U,
1227 kXBARA1_OutputIomuxXbarInout13 = 13|0x100U,
1228 kXBARA1_OutputIomuxXbarInout14 = 14|0x100U,
1229 kXBARA1_OutputIomuxXbarInout15 = 15|0x100U,
1230 kXBARA1_OutputIomuxXbarInout16 = 16|0x100U,
1231 kXBARA1_OutputIomuxXbarInout17 = 17|0x100U,
1232 kXBARA1_OutputIomuxXbarInout18 = 18|0x100U,
1233 kXBARA1_OutputIomuxXbarInout19 = 19|0x100U,
1234 kXBARA1_OutputAcmp1Sample = 20|0x100U,
1235 kXBARA1_OutputAcmp2Sample = 21|0x100U,
1236 kXBARA1_OutputAcmp3Sample = 22|0x100U,
1237 kXBARA1_OutputAcmp4Sample = 23|0x100U,
1238 kXBARA1_OutputRESERVED24 = 24|0x100U,
1239 kXBARA1_OutputRESERVED25 = 25|0x100U,
1240 kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U,
1241 kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U,
1242 kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U,
1243 kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U,
1244 kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U,
1245 kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U,
1246 kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U,
1247 kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U,
1248 kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U,
1249 kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U,
1250 kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U,
1251 kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U,
1252 kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U,
1253 kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U,
1254 kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U,
1255 kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U,
1256 kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U,
1257 kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U,
1258 kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U,
1259 kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U,
1260 kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U,
1261 kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U,
1262 kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U,
1263 kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U,
1264 kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U,
1265 kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U,
1266 kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U,
1267 kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U,
1268 kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U,
1269 kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U,
1270 kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U,
1271 kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U,
1272 kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U,
1273 kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U,
1274 kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U,
1275 kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U,
1276 kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U,
1277 kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U,
1278 kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U,
1279 kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U,
1280 kXBARA1_OutputEnc1PhaseAInput = 66|0x100U,
1281 kXBARA1_OutputEnc1PhaseBInput = 67|0x100U,
1282 kXBARA1_OutputEnc1Index = 68|0x100U,
1283 kXBARA1_OutputEnc1Home = 69|0x100U,
1284 kXBARA1_OutputEnc1Trigger = 70|0x100U,
1285 kXBARA1_OutputEnc2PhaseAInput = 71|0x100U,
1286 kXBARA1_OutputEnc2PhaseBInput = 72|0x100U,
1287 kXBARA1_OutputEnc2Index = 73|0x100U,
1288 kXBARA1_OutputEnc2Home = 74|0x100U,
1289 kXBARA1_OutputEnc2Trigger = 75|0x100U,
1290 kXBARA1_OutputEnc3PhaseAInput = 76|0x100U,
1291 kXBARA1_OutputEnc3PhaseBInput = 77|0x100U,
1292 kXBARA1_OutputEnc3Index = 78|0x100U,
1293 kXBARA1_OutputEnc3Home = 79|0x100U,
1294 kXBARA1_OutputEnc3Trigger = 80|0x100U,
1295 kXBARA1_OutputEnc4PhaseAInput = 81|0x100U,
1296 kXBARA1_OutputEnc4PhaseBInput = 82|0x100U,
1297 kXBARA1_OutputEnc4Index = 83|0x100U,
1298 kXBARA1_OutputEnc4Home = 84|0x100U,
1299 kXBARA1_OutputEnc4Trigger = 85|0x100U,
1300 kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U,
1301 kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U,
1302 kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U,
1303 kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U,
1304 kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U,
1305 kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U,
1306 kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U,
1307 kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U,
1308 kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U,
1309 kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U,
1310 kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U,
1311 kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U,
1312 kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U,
1313 kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U,
1314 kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U,
1315 kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U,
1316 kXBARA1_OutputEwmEwmIn = 102|0x100U,
1317 kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U,
1318 kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U,
1319 kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U,
1320 kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U,
1321 kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U,
1322 kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U,
1323 kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U,
1324 kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U,
1325 kXBARA1_OutputLpi2c1TrgInput = 111|0x100U,
1326 kXBARA1_OutputLpi2c2TrgInput = 112|0x100U,
1327 kXBARA1_OutputLpi2c3TrgInput = 113|0x100U,
1328 kXBARA1_OutputLpi2c4TrgInput = 114|0x100U,
1329 kXBARA1_OutputLpspi1TrgInput = 115|0x100U,
1330 kXBARA1_OutputLpspi2TrgInput = 116|0x100U,
1331 kXBARA1_OutputLpspi3TrgInput = 117|0x100U,
1332 kXBARA1_OutputLpspi4TrgInput = 118|0x100U,
1333 kXBARA1_OutputLpuart1TrgInput = 119|0x100U,
1334 kXBARA1_OutputLpuart2TrgInput = 120|0x100U,
1335 kXBARA1_OutputLpuart3TrgInput = 121|0x100U,
1336 kXBARA1_OutputLpuart4TrgInput = 122|0x100U,
1337 kXBARA1_OutputLpuart5TrgInput = 123|0x100U,
1338 kXBARA1_OutputLpuart6TrgInput = 124|0x100U,
1339 kXBARA1_OutputLpuart7TrgInput = 125|0x100U,
1340 kXBARA1_OutputLpuart8TrgInput = 126|0x100U,
1341 kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U,
1342 kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U,
1343 kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U,
1344 kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U,
1345 kXBARB2_OutputAoi1In00 = 0|0x200U,
1346 kXBARB2_OutputAoi1In01 = 1|0x200U,
1347 kXBARB2_OutputAoi1In02 = 2|0x200U,
1348 kXBARB2_OutputAoi1In03 = 3|0x200U,
1349 kXBARB2_OutputAoi1In04 = 4|0x200U,
1350 kXBARB2_OutputAoi1In05 = 5|0x200U,
1351 kXBARB2_OutputAoi1In06 = 6|0x200U,
1352 kXBARB2_OutputAoi1In07 = 7|0x200U,
1353 kXBARB2_OutputAoi1In08 = 8|0x200U,
1354 kXBARB2_OutputAoi1In09 = 9|0x200U,
1355 kXBARB2_OutputAoi1In10 = 10|0x200U,
1356 kXBARB2_OutputAoi1In11 = 11|0x200U,
1357 kXBARB2_OutputAoi1In12 = 12|0x200U,
1358 kXBARB2_OutputAoi1In13 = 13|0x200U,
1359 kXBARB2_OutputAoi1In14 = 14|0x200U,
1360 kXBARB2_OutputAoi1In15 = 15|0x200U,
1361 kXBARB3_OutputAoi2In00 = 0|0x300U,
1362 kXBARB3_OutputAoi2In01 = 1|0x300U,
1363 kXBARB3_OutputAoi2In02 = 2|0x300U,
1364 kXBARB3_OutputAoi2In03 = 3|0x300U,
1365 kXBARB3_OutputAoi2In04 = 4|0x300U,
1366 kXBARB3_OutputAoi2In05 = 5|0x300U,
1367 kXBARB3_OutputAoi2In06 = 6|0x300U,
1368 kXBARB3_OutputAoi2In07 = 7|0x300U,
1369 kXBARB3_OutputAoi2In08 = 8|0x300U,
1370 kXBARB3_OutputAoi2In09 = 9|0x300U,
1371 kXBARB3_OutputAoi2In10 = 10|0x300U,
1372 kXBARB3_OutputAoi2In11 = 11|0x300U,
1373 kXBARB3_OutputAoi2In12 = 12|0x300U,
1374 kXBARB3_OutputAoi2In13 = 13|0x300U,
1375 kXBARB3_OutputAoi2In14 = 14|0x300U,
1376 kXBARB3_OutputAoi2In15 = 15|0x300U,
1377 } xbar_output_signal_t;
1378
1379 /* end of group Mapping_Information */
1383
1384
1385 /* ----------------------------------------------------------------------------
1386 -- Device Peripheral Access Layer
1387 ---------------------------------------------------------------------------- */
1388
1395 /*
1396 ** Start of section using anonymous unions
1397 */
1398
1399 #if defined(__ARMCC_VERSION)
1400 #if (__ARMCC_VERSION >= 6010050)
1401 #pragma clang diagnostic push
1402 #else
1403 #pragma push
1404 #pragma anon_unions
1405 #endif
1406 #elif defined(__CWCC__)
1407 #pragma push
1408 #pragma cpp_extensions on
1409 #elif defined(__GNUC__)
1410 /* anonymous unions are enabled by default */
1411 #elif defined(__IAR_SYSTEMS_ICC__)
1412 #pragma language=extended
1413 #else
1414 #error Not supported compiler type
1415 #endif
1416
1417 /* ----------------------------------------------------------------------------
1418 -- ADC Peripheral Access Layer
1419 ---------------------------------------------------------------------------- */
1420
1427 typedef struct {
1428 __IO uint32_t HC[8];
1429 __I uint32_t HS;
1430 __I uint32_t R[8];
1431 __IO uint32_t CFG;
1432 __IO uint32_t GC;
1433 __IO uint32_t GS;
1434 __IO uint32_t CV;
1435 __IO uint32_t OFS;
1436 __IO uint32_t CAL;
1437 } ADC_Type;
1438
1439 /* ----------------------------------------------------------------------------
1440 -- ADC Register Masks
1441 ---------------------------------------------------------------------------- */
1442
1450 #define ADC_HC_ADCH_MASK (0x1FU)
1451 #define ADC_HC_ADCH_SHIFT (0U)
1452
1460 #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1461 #define ADC_HC_AIEN_MASK (0x80U)
1462 #define ADC_HC_AIEN_SHIFT (7U)
1463
1467 #define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1468
1470 /* The count of ADC_HC */
1471 #define ADC_HC_COUNT (8U)
1472
1475 #define ADC_HS_COCO0_MASK (0x1U)
1476 #define ADC_HS_COCO0_SHIFT (0U)
1477
1479 #define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1480
1484 #define ADC_R_CDATA_MASK (0xFFFU)
1485 #define ADC_R_CDATA_SHIFT (0U)
1486
1488 #define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1489
1491 /* The count of ADC_R */
1492 #define ADC_R_COUNT (8U)
1493
1496 #define ADC_CFG_ADICLK_MASK (0x3U)
1497 #define ADC_CFG_ADICLK_SHIFT (0U)
1498
1504 #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1505 #define ADC_CFG_MODE_MASK (0xCU)
1506 #define ADC_CFG_MODE_SHIFT (2U)
1507
1513 #define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1514 #define ADC_CFG_ADLSMP_MASK (0x10U)
1515 #define ADC_CFG_ADLSMP_SHIFT (4U)
1516
1520 #define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1521 #define ADC_CFG_ADIV_MASK (0x60U)
1522 #define ADC_CFG_ADIV_SHIFT (5U)
1523
1529 #define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1530 #define ADC_CFG_ADLPC_MASK (0x80U)
1531 #define ADC_CFG_ADLPC_SHIFT (7U)
1532
1536 #define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1537 #define ADC_CFG_ADSTS_MASK (0x300U)
1538 #define ADC_CFG_ADSTS_SHIFT (8U)
1539
1545 #define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1546 #define ADC_CFG_ADHSC_MASK (0x400U)
1547 #define ADC_CFG_ADHSC_SHIFT (10U)
1548
1552 #define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1553 #define ADC_CFG_REFSEL_MASK (0x1800U)
1554 #define ADC_CFG_REFSEL_SHIFT (11U)
1555
1561 #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1562 #define ADC_CFG_ADTRG_MASK (0x2000U)
1563 #define ADC_CFG_ADTRG_SHIFT (13U)
1564
1568 #define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1569 #define ADC_CFG_AVGS_MASK (0xC000U)
1570 #define ADC_CFG_AVGS_SHIFT (14U)
1571
1577 #define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1578 #define ADC_CFG_OVWREN_MASK (0x10000U)
1579 #define ADC_CFG_OVWREN_SHIFT (16U)
1580
1584 #define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1585
1589 #define ADC_GC_ADACKEN_MASK (0x1U)
1590 #define ADC_GC_ADACKEN_SHIFT (0U)
1591
1595 #define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1596 #define ADC_GC_DMAEN_MASK (0x2U)
1597 #define ADC_GC_DMAEN_SHIFT (1U)
1598
1602 #define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1603 #define ADC_GC_ACREN_MASK (0x4U)
1604 #define ADC_GC_ACREN_SHIFT (2U)
1605
1609 #define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1610 #define ADC_GC_ACFGT_MASK (0x8U)
1611 #define ADC_GC_ACFGT_SHIFT (3U)
1612
1618 #define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1619 #define ADC_GC_ACFE_MASK (0x10U)
1620 #define ADC_GC_ACFE_SHIFT (4U)
1621
1625 #define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1626 #define ADC_GC_AVGE_MASK (0x20U)
1627 #define ADC_GC_AVGE_SHIFT (5U)
1628
1632 #define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1633 #define ADC_GC_ADCO_MASK (0x40U)
1634 #define ADC_GC_ADCO_SHIFT (6U)
1635
1639 #define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1640 #define ADC_GC_CAL_MASK (0x80U)
1641 #define ADC_GC_CAL_SHIFT (7U)
1642
1644 #define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1645
1649 #define ADC_GS_ADACT_MASK (0x1U)
1650 #define ADC_GS_ADACT_SHIFT (0U)
1651
1655 #define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1656 #define ADC_GS_CALF_MASK (0x2U)
1657 #define ADC_GS_CALF_SHIFT (1U)
1658
1662 #define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1663 #define ADC_GS_AWKST_MASK (0x4U)
1664 #define ADC_GS_AWKST_SHIFT (2U)
1665
1669 #define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1670
1674 #define ADC_CV_CV1_MASK (0xFFFU)
1675 #define ADC_CV_CV1_SHIFT (0U)
1676
1678 #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1679 #define ADC_CV_CV2_MASK (0xFFF0000U)
1680 #define ADC_CV_CV2_SHIFT (16U)
1681
1683 #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1684
1688 #define ADC_OFS_OFS_MASK (0xFFFU)
1689 #define ADC_OFS_OFS_SHIFT (0U)
1690
1692 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1693 #define ADC_OFS_SIGN_MASK (0x1000U)
1694 #define ADC_OFS_SIGN_SHIFT (12U)
1695
1699 #define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1700
1704 #define ADC_CAL_CAL_CODE_MASK (0xFU)
1705 #define ADC_CAL_CAL_CODE_SHIFT (0U)
1706
1708 #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
1709 /* end of group ADC_Register_Masks */
1715
1716
1717 /* ADC - Peripheral instance base addresses */
1719 #define ADC1_BASE (0x400C4000u)
1720
1721 #define ADC1 ((ADC_Type *)ADC1_BASE)
1722
1723 #define ADC2_BASE (0x400C8000u)
1724
1725 #define ADC2 ((ADC_Type *)ADC2_BASE)
1726
1727 #define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
1728
1729 #define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
1730
1731 #define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1732 /* end of group ADC_Peripheral_Access_Layer */
1736
1737
1738 /* ----------------------------------------------------------------------------
1739 -- ADC_ETC Peripheral Access Layer
1740 ---------------------------------------------------------------------------- */
1741
1748 typedef struct {
1749 __IO uint32_t CTRL;
1750 __IO uint32_t DONE0_1_IRQ;
1751 __IO uint32_t DONE2_ERR_IRQ;
1752 __IO uint32_t DMA_CTRL;
1753 struct { /* offset: 0x10, array step: 0x28 */
1754 __IO uint32_t TRIGn_CTRL;
1755 __IO uint32_t TRIGn_COUNTER;
1756 __IO uint32_t TRIGn_CHAIN_1_0;
1757 __IO uint32_t TRIGn_CHAIN_3_2;
1758 __IO uint32_t TRIGn_CHAIN_5_4;
1759 __IO uint32_t TRIGn_CHAIN_7_6;
1760 __I uint32_t TRIGn_RESULT_1_0;
1761 __I uint32_t TRIGn_RESULT_3_2;
1762 __I uint32_t TRIGn_RESULT_5_4;
1763 __I uint32_t TRIGn_RESULT_7_6;
1764 } TRIG[8];
1765 } ADC_ETC_Type;
1766
1767 /* ----------------------------------------------------------------------------
1768 -- ADC_ETC Register Masks
1769 ---------------------------------------------------------------------------- */
1770
1778 #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1779 #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1780 #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1781 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1782 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1783 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1784 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1785 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1786 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1787 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1788 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1789 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1790 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1791 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1792 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1793 #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1794 #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1795 #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1796 #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1797 #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1798 #define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1799 #define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1800 #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1801 #define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1802 #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1803 #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1804 #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1805
1809 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1810 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1811 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1812 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1813 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1814 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1815 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1816 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1817 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1818 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1819 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1820 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1821 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1822 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1823 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1824 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1825 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1826 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1827 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1828 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1829 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1830 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1831 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1832 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1833 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1834 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1835 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1836 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1837 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1838 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1839 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1840 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1841 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1842 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1843 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1844 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1845 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1846 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1847 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1848 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1849 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1850 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1851 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1852 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1853 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1854 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1855 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1856 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1857
1861 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1862 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1863 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
1864 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1865 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1866 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1867 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1868 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1869 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1870 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1871 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1872 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1873 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1874 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1875 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1876 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1877 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1878 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1879 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1880 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1881 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1882 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1883 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1884 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1885 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1886 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1887 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1888 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1889 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1890 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1891 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1892 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1893 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1894 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1895 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1896 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1897 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1898 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1899 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1900 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1901 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1902 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1903 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1904 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1905 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1906 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1907 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1908 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1909
1913 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1914 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1915 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1916 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1917 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1918 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1919 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1920 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1921 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1922 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1923 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1924 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1925 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1926 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1927 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1928 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1929 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1930 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1931 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1932 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1933 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1934 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1935 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1936 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1937 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1938 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1939 #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1940 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1941 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1942 #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1943 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1944 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1945 #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1946 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1947 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1948 #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1949 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1950 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1951 #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1952 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1953 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1954 #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1955 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1956 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1957 #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1958 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1959 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1960 #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1961
1965 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1966 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1967 #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1968 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1969 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1970 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1971 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1972 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1973 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1974 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1975 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1976 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1977 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1978 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1979 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1980
1982 /* The count of ADC_ETC_TRIGn_CTRL */
1983 #define ADC_ETC_TRIGn_CTRL_COUNT (8U)
1984
1987 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1988 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1989 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1990 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1991 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1992 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1993
1995 /* The count of ADC_ETC_TRIGn_COUNTER */
1996 #define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
1997
2000 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
2001 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
2002 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
2003 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
2004 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
2005 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
2006 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
2007 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
2008 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
2009 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
2010 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
2011 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
2012 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
2013 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
2014 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
2015 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
2016 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
2017 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
2018 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
2019 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
2020 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
2021 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
2022 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
2023 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
2024
2026 /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
2027 #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
2028
2031 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
2032 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
2033 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
2034 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
2035 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
2036 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
2037 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
2038 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
2039 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
2040 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
2041 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
2042 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
2043 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
2044 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
2045 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
2046 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
2047 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
2048 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
2049 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
2050 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
2051 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
2052 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
2053 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
2054 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
2055
2057 /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
2058 #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
2059
2062 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
2063 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
2064 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
2065 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
2066 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
2067 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
2068 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
2069 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
2070 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
2071 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
2072 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
2073 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
2074 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
2075 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
2076 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
2077 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
2078 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
2079 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
2080 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
2081 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
2082 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
2083 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
2084 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
2085 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
2086
2088 /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
2089 #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
2090
2093 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
2094 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
2095 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
2096 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
2097 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
2098 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
2099 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
2100 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
2101 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
2102 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
2103 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
2104 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
2105 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
2106 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
2107 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
2108 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
2109 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
2110 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
2111 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
2112 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
2113 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
2114 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
2115 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
2116 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
2117
2119 /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
2120 #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
2121
2124 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
2125 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
2126 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
2127 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
2128 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
2129 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
2130
2132 /* The count of ADC_ETC_TRIGn_RESULT_1_0 */
2133 #define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
2134
2137 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
2138 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
2139 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
2140 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
2141 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
2142 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
2143
2145 /* The count of ADC_ETC_TRIGn_RESULT_3_2 */
2146 #define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
2147
2150 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
2151 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
2152 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
2153 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
2154 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
2155 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
2156
2158 /* The count of ADC_ETC_TRIGn_RESULT_5_4 */
2159 #define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
2160
2163 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
2164 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
2165 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
2166 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
2167 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
2168 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
2169
2171 /* The count of ADC_ETC_TRIGn_RESULT_7_6 */
2172 #define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
2173
2174 /* end of group ADC_ETC_Register_Masks */
2178
2179
2180 /* ADC_ETC - Peripheral instance base addresses */
2182 #define ADC_ETC_BASE (0x403B0000u)
2183
2184 #define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
2185
2186 #define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
2187
2188 #define ADC_ETC_BASE_PTRS { ADC_ETC }
2189
2190 #define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
2191 #define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
2192 /* end of group ADC_ETC_Peripheral_Access_Layer */
2196
2197
2198 /* ----------------------------------------------------------------------------
2199 -- AIPSTZ Peripheral Access Layer
2200 ---------------------------------------------------------------------------- */
2201
2208 typedef struct {
2209 __IO uint32_t MPR;
2210 uint8_t RESERVED_0[60];
2211 __IO uint32_t OPACR;
2212 __IO uint32_t OPACR1;
2213 __IO uint32_t OPACR2;
2214 __IO uint32_t OPACR3;
2215 __IO uint32_t OPACR4;
2216 } AIPSTZ_Type;
2217
2218 /* ----------------------------------------------------------------------------
2219 -- AIPSTZ Register Masks
2220 ---------------------------------------------------------------------------- */
2221
2229 #define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
2230 #define AIPSTZ_MPR_MPROT5_SHIFT (8U)
2231
2240 #define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
2241 #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
2242 #define AIPSTZ_MPR_MPROT3_SHIFT (16U)
2243
2252 #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
2253 #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
2254 #define AIPSTZ_MPR_MPROT2_SHIFT (20U)
2255
2264 #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
2265 #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
2266 #define AIPSTZ_MPR_MPROT1_SHIFT (24U)
2267
2276 #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
2277 #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
2278 #define AIPSTZ_MPR_MPROT0_SHIFT (28U)
2279
2288 #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
2289
2293 #define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
2294 #define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
2295
2309 #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
2310 #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
2311 #define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
2312
2326 #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
2327 #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
2328 #define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
2329
2343 #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2344 #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
2345 #define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
2346
2360 #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2361 #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
2362 #define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
2363
2377 #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2378 #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
2379 #define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
2380
2394 #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2395 #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
2396 #define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
2397
2411 #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
2412 #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
2413 #define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
2414
2428 #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
2429
2433 #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
2434 #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
2435
2449 #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
2450 #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
2451 #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
2452
2466 #define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
2467 #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
2468 #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
2469
2483 #define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
2484 #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
2485 #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
2486
2500 #define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
2501 #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
2502 #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
2503
2517 #define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
2518 #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
2519 #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
2520
2534 #define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
2535 #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
2536 #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
2537
2551 #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
2552 #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
2553 #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
2554
2568 #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
2569
2573 #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
2574 #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
2575
2589 #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
2590 #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
2591 #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
2592
2606 #define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
2607 #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
2608 #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
2609
2623 #define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
2624 #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
2625 #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
2626
2640 #define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
2641 #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
2642 #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
2643
2657 #define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
2658 #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
2659 #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
2660
2674 #define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
2675 #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
2676 #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
2677
2691 #define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
2692 #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
2693 #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
2694
2708 #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
2709
2713 #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
2714 #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
2715
2729 #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
2730 #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
2731 #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
2732
2746 #define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
2747 #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
2748 #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
2749
2763 #define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
2764 #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
2765 #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
2766
2780 #define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
2781 #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
2782 #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
2783
2797 #define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
2798 #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
2799 #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
2800
2814 #define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2815 #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2816 #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2817
2831 #define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2832 #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2833 #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2834
2848 #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2849
2853 #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2854 #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2855
2869 #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2870 #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2871 #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2872
2886 #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
2887 /* end of group AIPSTZ_Register_Masks */
2893
2894
2895 /* AIPSTZ - Peripheral instance base addresses */
2897 #define AIPSTZ1_BASE (0x4007C000u)
2898
2899 #define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2900
2901 #define AIPSTZ2_BASE (0x4017C000u)
2902
2903 #define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2904
2905 #define AIPSTZ3_BASE (0x4027C000u)
2906
2907 #define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
2908
2909 #define AIPSTZ4_BASE (0x4037C000u)
2910
2911 #define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
2912
2913 #define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
2914
2915 #define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
2916 /* end of group AIPSTZ_Peripheral_Access_Layer */
2920
2921
2922 /* ----------------------------------------------------------------------------
2923 -- AOI Peripheral Access Layer
2924 ---------------------------------------------------------------------------- */
2925
2932 typedef struct {
2933 struct { /* offset: 0x0, array step: 0x4 */
2934 __IO uint16_t BFCRT01;
2935 __IO uint16_t BFCRT23;
2936 } BFCRT[4];
2937 } AOI_Type;
2938
2939 /* ----------------------------------------------------------------------------
2940 -- AOI Register Masks
2941 ---------------------------------------------------------------------------- */
2942
2950 #define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2951 #define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2952
2958 #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2959 #define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2960 #define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2961
2967 #define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2968 #define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2969 #define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2970
2976 #define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2977 #define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2978 #define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2979
2985 #define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2986 #define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2987 #define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2988
2994 #define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2995 #define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2996 #define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2997
3003 #define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
3004 #define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
3005 #define AOI_BFCRT01_PT0_BC_SHIFT (12U)
3006
3012 #define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
3013 #define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
3014 #define AOI_BFCRT01_PT0_AC_SHIFT (14U)
3015
3021 #define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
3022
3024 /* The count of AOI_BFCRT01 */
3025 #define AOI_BFCRT01_COUNT (4U)
3026
3029 #define AOI_BFCRT23_PT3_DC_MASK (0x3U)
3030 #define AOI_BFCRT23_PT3_DC_SHIFT (0U)
3031
3037 #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
3038 #define AOI_BFCRT23_PT3_CC_MASK (0xCU)
3039 #define AOI_BFCRT23_PT3_CC_SHIFT (2U)
3040
3046 #define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
3047 #define AOI_BFCRT23_PT3_BC_MASK (0x30U)
3048 #define AOI_BFCRT23_PT3_BC_SHIFT (4U)
3049
3055 #define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
3056 #define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
3057 #define AOI_BFCRT23_PT3_AC_SHIFT (6U)
3058
3064 #define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
3065 #define AOI_BFCRT23_PT2_DC_MASK (0x300U)
3066 #define AOI_BFCRT23_PT2_DC_SHIFT (8U)
3067
3073 #define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
3074 #define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
3075 #define AOI_BFCRT23_PT2_CC_SHIFT (10U)
3076
3082 #define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
3083 #define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
3084 #define AOI_BFCRT23_PT2_BC_SHIFT (12U)
3085
3091 #define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
3092 #define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
3093 #define AOI_BFCRT23_PT2_AC_SHIFT (14U)
3094
3100 #define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
3101
3103 /* The count of AOI_BFCRT23 */
3104 #define AOI_BFCRT23_COUNT (4U)
3105
3106 /* end of group AOI_Register_Masks */
3110
3111
3112 /* AOI - Peripheral instance base addresses */
3114 #define AOI1_BASE (0x403B4000u)
3115
3116 #define AOI1 ((AOI_Type *)AOI1_BASE)
3117
3118 #define AOI2_BASE (0x403B8000u)
3119
3120 #define AOI2 ((AOI_Type *)AOI2_BASE)
3121
3122 #define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
3123
3124 #define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
3125 /* end of group AOI_Peripheral_Access_Layer */
3129
3130
3131 /* ----------------------------------------------------------------------------
3132 -- BEE Peripheral Access Layer
3133 ---------------------------------------------------------------------------- */
3134
3141 typedef struct {
3142 __IO uint32_t CTRL;
3143 __IO uint32_t ADDR_OFFSET0;
3144 __IO uint32_t ADDR_OFFSET1;
3145 __IO uint32_t AES_KEY0_W0;
3146 __IO uint32_t AES_KEY0_W1;
3147 __IO uint32_t AES_KEY0_W2;
3148 __IO uint32_t AES_KEY0_W3;
3149 __IO uint32_t STATUS;
3150 __O uint32_t CTR_NONCE0_W0;
3151 __O uint32_t CTR_NONCE0_W1;
3152 __O uint32_t CTR_NONCE0_W2;
3153 __O uint32_t CTR_NONCE0_W3;
3154 __O uint32_t CTR_NONCE1_W0;
3155 __O uint32_t CTR_NONCE1_W1;
3156 __O uint32_t CTR_NONCE1_W2;
3157 __O uint32_t CTR_NONCE1_W3;
3158 __IO uint32_t REGION1_TOP;
3159 __IO uint32_t REGION1_BOT;
3160 } BEE_Type;
3161
3162 /* ----------------------------------------------------------------------------
3163 -- BEE Register Masks
3164 ---------------------------------------------------------------------------- */
3165
3173 #define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
3174 #define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
3175
3179 #define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
3180 #define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
3181 #define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
3182 #define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
3183 #define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
3184 #define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
3185 #define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
3186 #define BEE_CTRL_KEY_VALID_MASK (0x10U)
3187 #define BEE_CTRL_KEY_VALID_SHIFT (4U)
3188 #define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
3189 #define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
3190 #define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
3191
3195 #define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
3196 #define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
3197 #define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
3198 #define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
3199 #define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
3200 #define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
3201
3207 #define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
3208 #define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
3209 #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
3210 #define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
3211 #define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
3212 #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
3213
3217 #define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
3218 #define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
3219 #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
3220 #define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
3221 #define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
3222 #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
3223
3227 #define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
3228 #define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
3229 #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
3230 #define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
3231 #define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
3232 #define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
3233 #define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
3234 #define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
3235 #define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
3236 #define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
3237 #define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
3238 #define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
3239 #define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
3240 #define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
3241 #define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
3242 #define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
3243 #define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
3244 #define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
3245 #define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
3246 #define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
3247 #define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
3248 #define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
3249 #define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
3250 #define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
3251 #define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
3252 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
3253 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
3254 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
3255 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
3256 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
3257 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
3258 #define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
3259 #define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
3260 #define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
3261 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
3262 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
3263 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
3264 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
3265 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
3266 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
3267 #define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
3268 #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
3269 #define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
3270
3274 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
3275 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
3276 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
3277 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
3278 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
3279 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
3280
3284 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
3285 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
3286 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
3287 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
3288 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
3289 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
3290
3294 #define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
3295 #define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
3296
3298 #define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
3299
3303 #define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
3304 #define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
3305
3307 #define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
3308
3312 #define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
3313 #define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
3314
3316 #define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
3317
3321 #define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
3322 #define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
3323
3325 #define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
3326
3330 #define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
3331 #define BEE_STATUS_IRQ_VEC_SHIFT (0U)
3332 #define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
3333 #define BEE_STATUS_BEE_IDLE_MASK (0x100U)
3334 #define BEE_STATUS_BEE_IDLE_SHIFT (8U)
3335 #define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
3336
3340 #define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
3341 #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
3342 #define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
3343
3347 #define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
3348 #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
3349 #define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
3350
3354 #define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
3355 #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
3356 #define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
3357
3361 #define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
3362 #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
3363 #define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
3364
3368 #define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
3369 #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
3370 #define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
3371
3375 #define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
3376 #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
3377 #define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
3378
3382 #define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
3383 #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
3384 #define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
3385
3389 #define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
3390 #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
3391 #define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
3392
3396 #define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
3397 #define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
3398
3400 #define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
3401
3405 #define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
3406 #define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
3407
3409 #define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
3410 /* end of group BEE_Register_Masks */
3416
3417
3418 /* BEE - Peripheral instance base addresses */
3420 #define BEE_BASE (0x403EC000u)
3421
3422 #define BEE ((BEE_Type *)BEE_BASE)
3423
3424 #define BEE_BASE_ADDRS { BEE_BASE }
3425
3426 #define BEE_BASE_PTRS { BEE }
3427 /* end of group BEE_Peripheral_Access_Layer */
3431
3432
3433 /* ----------------------------------------------------------------------------
3434 -- CAN Peripheral Access Layer
3435 ---------------------------------------------------------------------------- */
3436
3443 typedef struct {
3444 __IO uint32_t MCR;
3445 __IO uint32_t CTRL1;
3446 __IO uint32_t TIMER;
3447 uint8_t RESERVED_0[4];
3448 __IO uint32_t RXMGMASK;
3449 __IO uint32_t RX14MASK;
3450 __IO uint32_t RX15MASK;
3451 __IO uint32_t ECR;
3452 __IO uint32_t ESR1;
3453 __IO uint32_t IMASK2;
3454 __IO uint32_t IMASK1;
3455 __IO uint32_t IFLAG2;
3456 __IO uint32_t IFLAG1;
3457 __IO uint32_t CTRL2;
3458 __I uint32_t ESR2;
3459 uint8_t RESERVED_1[8];
3460 __I uint32_t CRCR;
3461 __IO uint32_t RXFGMASK;
3462 __I uint32_t RXFIR;
3463 __IO uint32_t CBT;
3464 uint8_t RESERVED_2[4];
3465 __I uint32_t DBG1;
3466 __I uint32_t DBG2;
3467 uint8_t RESERVED_3[32];
3468 union { /* offset: 0x80 */
3469 struct { /* offset: 0x80, array step: 0x10 */
3470 __IO uint32_t CS;
3471 __IO uint32_t ID;
3472 __IO uint32_t WORD[2];
3473 } MB_8B[64];
3474 struct { /* offset: 0x80, array step: 0x18 */
3475 __IO uint32_t CS;
3476 __IO uint32_t ID;
3477 __IO uint32_t WORD[4];
3478 } MB_16B[42];
3479 struct { /* offset: 0x80, array step: 0x28 */
3480 __IO uint32_t CS;
3481 __IO uint32_t ID;
3482 __IO uint32_t WORD[8];
3483 } MB_32B[24];
3484 struct { /* offset: 0x80, array step: 0x48 */
3485 __IO uint32_t CS;
3486 __IO uint32_t ID;
3487 __IO uint32_t WORD[16];
3488 } MB_64B[14];
3489 struct { /* offset: 0x80, array step: 0x10 */
3490 __IO uint32_t CS;
3491 __IO uint32_t ID;
3492 __IO uint32_t WORD0;
3493 __IO uint32_t WORD1;
3494 } MB[64];
3495 };
3496 uint8_t RESERVED_4[1024];
3497 __IO uint32_t RXIMR[64];
3498 uint8_t RESERVED_5[96];
3499 __IO uint32_t GFWR;
3500 uint8_t RESERVED_6[524];
3501 __IO uint32_t EPRS;
3502 __IO uint32_t ENCBT;
3503 __IO uint32_t EDCBT;
3504 __IO uint32_t ETDC;
3505 __IO uint32_t FDCTRL;
3506 __IO uint32_t FDCBT;
3507 __I uint32_t FDCRC;
3508 __IO uint32_t ERFCR;
3509 __IO uint32_t ERFIER;
3510 __IO uint32_t ERFSR;
3511 uint8_t RESERVED_7[24];
3512 __I uint32_t HR_TIME_STAMP[64];
3513 uint8_t RESERVED_8[8912];
3514 __IO uint32_t ERFFEL[128];
3515 } CAN_Type;
3516
3517 /* ----------------------------------------------------------------------------
3518 -- CAN Register Masks
3519 ---------------------------------------------------------------------------- */
3520
3528 #define CAN_MCR_MAXMB_MASK (0x7FU)
3529 #define CAN_MCR_MAXMB_SHIFT (0U)
3530
3532 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
3533 #define CAN_MCR_IDAM_MASK (0x300U)
3534 #define CAN_MCR_IDAM_SHIFT (8U)
3535
3541 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
3542 #define CAN_MCR_FDEN_MASK (0x800U)
3543 #define CAN_MCR_FDEN_SHIFT (11U)
3544
3548 #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
3549 #define CAN_MCR_AEN_MASK (0x1000U)
3550 #define CAN_MCR_AEN_SHIFT (12U)
3551
3555 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
3556 #define CAN_MCR_LPRIOEN_MASK (0x2000U)
3557 #define CAN_MCR_LPRIOEN_SHIFT (13U)
3558
3562 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
3563 #define CAN_MCR_DMA_MASK (0x8000U)
3564 #define CAN_MCR_DMA_SHIFT (15U)
3565
3569 #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
3570 #define CAN_MCR_IRMQ_MASK (0x10000U)
3571 #define CAN_MCR_IRMQ_SHIFT (16U)
3572
3576 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
3577 #define CAN_MCR_SRXDIS_MASK (0x20000U)
3578 #define CAN_MCR_SRXDIS_SHIFT (17U)
3579
3583 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
3584 #define CAN_MCR_DOZE_MASK (0x40000U)
3585 #define CAN_MCR_DOZE_SHIFT (18U)
3586
3590 #define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
3591 #define CAN_MCR_WAKSRC_MASK (0x80000U)
3592 #define CAN_MCR_WAKSRC_SHIFT (19U)
3593
3597 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
3598 #define CAN_MCR_LPMACK_MASK (0x100000U)
3599 #define CAN_MCR_LPMACK_SHIFT (20U)
3600
3604 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
3605 #define CAN_MCR_WRNEN_MASK (0x200000U)
3606 #define CAN_MCR_WRNEN_SHIFT (21U)
3607
3611 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
3612 #define CAN_MCR_SLFWAK_MASK (0x400000U)
3613 #define CAN_MCR_SLFWAK_SHIFT (22U)
3614
3618 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
3619 #define CAN_MCR_SUPV_MASK (0x800000U)
3620 #define CAN_MCR_SUPV_SHIFT (23U)
3621
3626 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
3627 #define CAN_MCR_FRZACK_MASK (0x1000000U)
3628 #define CAN_MCR_FRZACK_SHIFT (24U)
3629
3633 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
3634 #define CAN_MCR_SOFTRST_MASK (0x2000000U)
3635 #define CAN_MCR_SOFTRST_SHIFT (25U)
3636
3640 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
3641 #define CAN_MCR_WAKMSK_MASK (0x4000000U)
3642 #define CAN_MCR_WAKMSK_SHIFT (26U)
3643
3647 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
3648 #define CAN_MCR_NOTRDY_MASK (0x8000000U)
3649 #define CAN_MCR_NOTRDY_SHIFT (27U)
3650
3654 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
3655 #define CAN_MCR_HALT_MASK (0x10000000U)
3656 #define CAN_MCR_HALT_SHIFT (28U)
3657
3661 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
3662 #define CAN_MCR_RFEN_MASK (0x20000000U)
3663 #define CAN_MCR_RFEN_SHIFT (29U)
3664
3668 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
3669 #define CAN_MCR_FRZ_MASK (0x40000000U)
3670 #define CAN_MCR_FRZ_SHIFT (30U)
3671
3675 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
3676 #define CAN_MCR_MDIS_MASK (0x80000000U)
3677 #define CAN_MCR_MDIS_SHIFT (31U)
3678
3682 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
3683
3687 #define CAN_CTRL1_PROPSEG_MASK (0x7U)
3688 #define CAN_CTRL1_PROPSEG_SHIFT (0U)
3689
3691 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
3692 #define CAN_CTRL1_LOM_MASK (0x8U)
3693 #define CAN_CTRL1_LOM_SHIFT (3U)
3694
3698 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
3699 #define CAN_CTRL1_LBUF_MASK (0x10U)
3700 #define CAN_CTRL1_LBUF_SHIFT (4U)
3701
3705 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
3706 #define CAN_CTRL1_TSYN_MASK (0x20U)
3707 #define CAN_CTRL1_TSYN_SHIFT (5U)
3708
3712 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
3713 #define CAN_CTRL1_BOFFREC_MASK (0x40U)
3714 #define CAN_CTRL1_BOFFREC_SHIFT (6U)
3715
3719 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
3720 #define CAN_CTRL1_SMP_MASK (0x80U)
3721 #define CAN_CTRL1_SMP_SHIFT (7U)
3722
3727 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
3728 #define CAN_CTRL1_RWRNMSK_MASK (0x400U)
3729 #define CAN_CTRL1_RWRNMSK_SHIFT (10U)
3730
3734 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
3735 #define CAN_CTRL1_TWRNMSK_MASK (0x800U)
3736 #define CAN_CTRL1_TWRNMSK_SHIFT (11U)
3737
3741 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
3742 #define CAN_CTRL1_LPB_MASK (0x1000U)
3743 #define CAN_CTRL1_LPB_SHIFT (12U)
3744
3748 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
3749 #define CAN_CTRL1_CLKSRC_MASK (0x2000U)
3750 #define CAN_CTRL1_CLKSRC_SHIFT (13U)
3751
3755 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
3756 #define CAN_CTRL1_ERRMSK_MASK (0x4000U)
3757 #define CAN_CTRL1_ERRMSK_SHIFT (14U)
3758
3762 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
3763 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
3764 #define CAN_CTRL1_BOFFMSK_SHIFT (15U)
3765
3769 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
3770 #define CAN_CTRL1_PSEG2_MASK (0x70000U)
3771 #define CAN_CTRL1_PSEG2_SHIFT (16U)
3772
3774 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
3775 #define CAN_CTRL1_PSEG1_MASK (0x380000U)
3776 #define CAN_CTRL1_PSEG1_SHIFT (19U)
3777
3779 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
3780 #define CAN_CTRL1_RJW_MASK (0xC00000U)
3781 #define CAN_CTRL1_RJW_SHIFT (22U)
3782
3784 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
3785 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
3786 #define CAN_CTRL1_PRESDIV_SHIFT (24U)
3787
3789 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
3790
3794 #define CAN_TIMER_TIMER_MASK (0xFFFFU)
3795 #define CAN_TIMER_TIMER_SHIFT (0U)
3796
3798 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
3799
3803 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
3804 #define CAN_RXMGMASK_MG_SHIFT (0U)
3805
3809 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
3810
3814 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
3815 #define CAN_RX14MASK_RX14M_SHIFT (0U)
3816
3820 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
3821
3825 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
3826 #define CAN_RX15MASK_RX15M_SHIFT (0U)
3827
3831 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
3832
3836 #define CAN_ECR_TXERRCNT_MASK (0xFFU)
3837 #define CAN_ECR_TXERRCNT_SHIFT (0U)
3838
3840 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
3841 #define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
3842 #define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
3843 #define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
3844 #define CAN_ECR_RXERRCNT_MASK (0xFF00U)
3845 #define CAN_ECR_RXERRCNT_SHIFT (8U)
3846
3848 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
3849 #define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
3850 #define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
3851 #define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
3852 #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
3853 #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
3854
3856 #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
3857 #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
3858 #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
3859
3861 #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
3862
3866 #define CAN_ESR1_WAKINT_MASK (0x1U)
3867 #define CAN_ESR1_WAKINT_SHIFT (0U)
3868
3872 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
3873 #define CAN_ESR1_ERRINT_MASK (0x2U)
3874 #define CAN_ESR1_ERRINT_SHIFT (1U)
3875
3879 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
3880 #define CAN_ESR1_BOFFINT_MASK (0x4U)
3881 #define CAN_ESR1_BOFFINT_SHIFT (2U)
3882
3886 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
3887 #define CAN_ESR1_RX_MASK (0x8U)
3888 #define CAN_ESR1_RX_SHIFT (3U)
3889
3893 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
3894 #define CAN_ESR1_FLTCONF_MASK (0x30U)
3895 #define CAN_ESR1_FLTCONF_SHIFT (4U)
3896
3901 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
3902 #define CAN_ESR1_TX_MASK (0x40U)
3903 #define CAN_ESR1_TX_SHIFT (6U)
3904
3908 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
3909 #define CAN_ESR1_IDLE_MASK (0x80U)
3910 #define CAN_ESR1_IDLE_SHIFT (7U)
3911
3915 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
3916 #define CAN_ESR1_RXWRN_MASK (0x100U)
3917 #define CAN_ESR1_RXWRN_SHIFT (8U)
3918
3922 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
3923 #define CAN_ESR1_TXWRN_MASK (0x200U)
3924 #define CAN_ESR1_TXWRN_SHIFT (9U)
3925
3929 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
3930 #define CAN_ESR1_STFERR_MASK (0x400U)
3931 #define CAN_ESR1_STFERR_SHIFT (10U)
3932
3936 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
3937 #define CAN_ESR1_FRMERR_MASK (0x800U)
3938 #define CAN_ESR1_FRMERR_SHIFT (11U)
3939
3943 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
3944 #define CAN_ESR1_CRCERR_MASK (0x1000U)
3945 #define CAN_ESR1_CRCERR_SHIFT (12U)
3946
3950 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
3951 #define CAN_ESR1_ACKERR_MASK (0x2000U)
3952 #define CAN_ESR1_ACKERR_SHIFT (13U)
3953
3957 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
3958 #define CAN_ESR1_BIT0ERR_MASK (0x4000U)
3959 #define CAN_ESR1_BIT0ERR_SHIFT (14U)
3960
3964 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
3965 #define CAN_ESR1_BIT1ERR_MASK (0x8000U)
3966 #define CAN_ESR1_BIT1ERR_SHIFT (15U)
3967
3971 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
3972 #define CAN_ESR1_RWRNINT_MASK (0x10000U)
3973 #define CAN_ESR1_RWRNINT_SHIFT (16U)
3974
3978 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
3979 #define CAN_ESR1_TWRNINT_MASK (0x20000U)
3980 #define CAN_ESR1_TWRNINT_SHIFT (17U)
3981
3985 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
3986 #define CAN_ESR1_SYNCH_MASK (0x40000U)
3987 #define CAN_ESR1_SYNCH_SHIFT (18U)
3988
3992 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
3993 #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
3994 #define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
3995
3999 #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
4000 #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
4001 #define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
4002
4006 #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
4007 #define CAN_ESR1_ERROVR_MASK (0x200000U)
4008 #define CAN_ESR1_ERROVR_SHIFT (21U)
4009
4013 #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
4014 #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
4015 #define CAN_ESR1_STFERR_FAST_SHIFT (26U)
4016
4020 #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
4021 #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
4022 #define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
4023
4027 #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
4028 #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
4029 #define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
4030
4034 #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
4035 #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
4036 #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
4037
4041 #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
4042 #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
4043 #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
4044
4048 #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
4049
4053 #define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
4054 #define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
4055
4057 #define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
4058 #define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
4059 #define CAN_IMASK2_BUFHM_SHIFT (0U)
4060
4064 #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
4065
4069 #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
4070 #define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
4071
4073 #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
4074 #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
4075 #define CAN_IMASK1_BUFLM_SHIFT (0U)
4076
4080 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
4081
4085 #define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
4086 #define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
4087
4089 #define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
4090 #define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
4091 #define CAN_IFLAG2_BUFHI_SHIFT (0U)
4092
4096 #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
4097
4101 #define CAN_IFLAG1_BUF0I_MASK (0x1U)
4102 #define CAN_IFLAG1_BUF0I_SHIFT (0U)
4103
4107 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4108 #define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
4109 #define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
4110
4114 #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
4115 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4116 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4117
4119 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4120 #define CAN_IFLAG1_BUF5I_MASK (0x20U)
4121 #define CAN_IFLAG1_BUF5I_SHIFT (5U)
4122
4126 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4127 #define CAN_IFLAG1_BUF6I_MASK (0x40U)
4128 #define CAN_IFLAG1_BUF6I_SHIFT (6U)
4129
4133 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4134 #define CAN_IFLAG1_BUF7I_MASK (0x80U)
4135 #define CAN_IFLAG1_BUF7I_SHIFT (7U)
4136
4140 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4141 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4142 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4143
4147 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4148
4152 #define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U)
4153 #define CAN_CTRL2_TSTAMPCAP_SHIFT (6U)
4154
4160 #define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK)
4161 #define CAN_CTRL2_MBTSBASE_MASK (0x300U)
4162 #define CAN_CTRL2_MBTSBASE_SHIFT (8U)
4163
4169 #define CAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK)
4170 #define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
4171 #define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
4172
4176 #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
4177 #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
4178 #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
4179
4183 #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
4184 #define CAN_CTRL2_BTE_MASK (0x2000U)
4185 #define CAN_CTRL2_BTE_SHIFT (13U)
4186
4190 #define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)
4191 #define CAN_CTRL2_PREXCEN_MASK (0x4000U)
4192 #define CAN_CTRL2_PREXCEN_SHIFT (14U)
4193
4197 #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
4198 #define CAN_CTRL2_TIMER_SRC_MASK (0x8000U)
4199 #define CAN_CTRL2_TIMER_SRC_SHIFT (15U)
4200
4206 #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
4207 #define CAN_CTRL2_EACEN_MASK (0x10000U)
4208 #define CAN_CTRL2_EACEN_SHIFT (16U)
4209
4214 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4215 #define CAN_CTRL2_RRS_MASK (0x20000U)
4216 #define CAN_CTRL2_RRS_SHIFT (17U)
4217
4221 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4222 #define CAN_CTRL2_MRP_MASK (0x40000U)
4223 #define CAN_CTRL2_MRP_SHIFT (18U)
4224
4228 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
4229 #define CAN_CTRL2_TASD_MASK (0xF80000U)
4230 #define CAN_CTRL2_TASD_SHIFT (19U)
4231
4233 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
4234 #define CAN_CTRL2_RFFN_MASK (0xF000000U)
4235 #define CAN_CTRL2_RFFN_SHIFT (24U)
4236
4238 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
4239 #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
4240 #define CAN_CTRL2_WRMFRZ_SHIFT (28U)
4241
4245 #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
4246 #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
4247 #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
4248
4252 #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
4253 #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
4254 #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
4255
4259 #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
4260
4264 #define CAN_ESR2_IMB_MASK (0x2000U)
4265 #define CAN_ESR2_IMB_SHIFT (13U)
4266
4270 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4271 #define CAN_ESR2_VPS_MASK (0x4000U)
4272 #define CAN_ESR2_VPS_SHIFT (14U)
4273
4277 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4278 #define CAN_ESR2_LPTM_MASK (0x7F0000U)
4279 #define CAN_ESR2_LPTM_SHIFT (16U)
4280
4282 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4283
4287 #define CAN_CRCR_TXCRC_MASK (0x7FFFU)
4288 #define CAN_CRCR_TXCRC_SHIFT (0U)
4289
4291 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4292 #define CAN_CRCR_MBCRC_MASK (0x7F0000U)
4293 #define CAN_CRCR_MBCRC_SHIFT (16U)
4294
4296 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4297
4301 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
4302 #define CAN_RXFGMASK_FGM_SHIFT (0U)
4303
4307 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4308
4312 #define CAN_RXFIR_IDHIT_MASK (0x1FFU)
4313 #define CAN_RXFIR_IDHIT_SHIFT (0U)
4314
4316 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4317
4321 #define CAN_CBT_EPSEG2_MASK (0x1FU)
4322 #define CAN_CBT_EPSEG2_SHIFT (0U)
4323
4325 #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
4326 #define CAN_CBT_EPSEG1_MASK (0x3E0U)
4327 #define CAN_CBT_EPSEG1_SHIFT (5U)
4328
4330 #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
4331 #define CAN_CBT_EPROPSEG_MASK (0xFC00U)
4332 #define CAN_CBT_EPROPSEG_SHIFT (10U)
4333
4335 #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
4336 #define CAN_CBT_ERJW_MASK (0x1F0000U)
4337 #define CAN_CBT_ERJW_SHIFT (16U)
4338
4340 #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
4341 #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
4342 #define CAN_CBT_EPRESDIV_SHIFT (21U)
4343
4345 #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
4346 #define CAN_CBT_BTF_MASK (0x80000000U)
4347 #define CAN_CBT_BTF_SHIFT (31U)
4348
4352 #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
4353
4357 #define CAN_DBG1_CFSM_MASK (0x3FU)
4358 #define CAN_DBG1_CFSM_SHIFT (0U)
4359
4361 #define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
4362 #define CAN_DBG1_CBN_MASK (0x1F000000U)
4363 #define CAN_DBG1_CBN_SHIFT (24U)
4364
4366 #define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
4367
4371 #define CAN_DBG2_RMP_MASK (0x7FU)
4372 #define CAN_DBG2_RMP_SHIFT (0U)
4373
4375 #define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
4376 #define CAN_DBG2_MPP_MASK (0x80U)
4377 #define CAN_DBG2_MPP_SHIFT (7U)
4378
4382 #define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
4383 #define CAN_DBG2_TAP_MASK (0x7F00U)
4384 #define CAN_DBG2_TAP_SHIFT (8U)
4385
4387 #define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
4388 #define CAN_DBG2_APP_MASK (0x8000U)
4389 #define CAN_DBG2_APP_SHIFT (15U)
4390
4394 #define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
4395
4397 /* The count of CAN_CS */
4398 #define CAN_CS_COUNT_MB8B (64U)
4399
4400 /* The count of CAN_ID */
4401 #define CAN_ID_COUNT_MB8B (64U)
4402
4403 /* The count of CAN_WORD */
4404 #define CAN_WORD_COUNT_MB8B (64U)
4405
4406 /* The count of CAN_WORD */
4407 #define CAN_WORD_COUNT_MB8B2 (2U)
4408
4409 /* The count of CAN_CS */
4410 #define CAN_CS_COUNT_MB16B (42U)
4411
4412 /* The count of CAN_ID */
4413 #define CAN_ID_COUNT_MB16B (42U)
4414
4415 /* The count of CAN_WORD */
4416 #define CAN_WORD_COUNT_MB16B (42U)
4417
4418 /* The count of CAN_WORD */
4419 #define CAN_WORD_COUNT_MB16B2 (4U)
4420
4421 /* The count of CAN_CS */
4422 #define CAN_CS_COUNT_MB32B (24U)
4423
4424 /* The count of CAN_ID */
4425 #define CAN_ID_COUNT_MB32B (24U)
4426
4427 /* The count of CAN_WORD */
4428 #define CAN_WORD_COUNT_MB32B (24U)
4429
4430 /* The count of CAN_WORD */
4431 #define CAN_WORD_COUNT_MB32B2 (8U)
4432
4435 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
4436 #define CAN_CS_TIME_STAMP_SHIFT (0U)
4437
4441 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4442 #define CAN_CS_DLC_MASK (0xF0000U)
4443 #define CAN_CS_DLC_SHIFT (16U)
4444
4446 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4447 #define CAN_CS_RTR_MASK (0x100000U)
4448 #define CAN_CS_RTR_SHIFT (20U)
4449
4451 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4452 #define CAN_CS_IDE_MASK (0x200000U)
4453 #define CAN_CS_IDE_SHIFT (21U)
4454
4456 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4457 #define CAN_CS_SRR_MASK (0x400000U)
4458 #define CAN_CS_SRR_SHIFT (22U)
4459
4461 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4462 #define CAN_CS_CODE_MASK (0xF000000U)
4463 #define CAN_CS_CODE_SHIFT (24U)
4464
4467 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4468 #define CAN_CS_ESI_MASK (0x20000000U)
4469 #define CAN_CS_ESI_SHIFT (29U)
4470
4472 #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
4473 #define CAN_CS_BRS_MASK (0x40000000U)
4474 #define CAN_CS_BRS_SHIFT (30U)
4475
4477 #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
4478 #define CAN_CS_EDL_MASK (0x80000000U)
4479 #define CAN_CS_EDL_SHIFT (31U)
4480
4483 #define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
4484
4486 /* The count of CAN_CS */
4487 #define CAN_CS_COUNT_MB64B (14U)
4488
4491 #define CAN_ID_EXT_MASK (0x3FFFFU)
4492 #define CAN_ID_EXT_SHIFT (0U)
4493
4495 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4496 #define CAN_ID_STD_MASK (0x1FFC0000U)
4497 #define CAN_ID_STD_SHIFT (18U)
4498
4500 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4501 #define CAN_ID_PRIO_MASK (0xE0000000U)
4502 #define CAN_ID_PRIO_SHIFT (29U)
4503
4507 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4508
4510 /* The count of CAN_ID */
4511 #define CAN_ID_COUNT_MB64B (14U)
4512
4515 #define CAN_WORD_DATA_BYTE_3_MASK (0xFFU)
4516 #define CAN_WORD_DATA_BYTE_3_SHIFT (0U)
4517
4519 #define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
4520 #define CAN_WORD_DATA_BYTE_7_MASK (0xFFU)
4521 #define CAN_WORD_DATA_BYTE_7_SHIFT (0U)
4522
4524 #define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
4525 #define CAN_WORD_DATA_BYTE_11_MASK (0xFFU)
4526 #define CAN_WORD_DATA_BYTE_11_SHIFT (0U)
4527
4529 #define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
4530 #define CAN_WORD_DATA_BYTE_15_MASK (0xFFU)
4531 #define CAN_WORD_DATA_BYTE_15_SHIFT (0U)
4532
4534 #define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
4535 #define CAN_WORD_DATA_BYTE_19_MASK (0xFFU)
4536 #define CAN_WORD_DATA_BYTE_19_SHIFT (0U)
4537
4539 #define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
4540 #define CAN_WORD_DATA_BYTE_23_MASK (0xFFU)
4541 #define CAN_WORD_DATA_BYTE_23_SHIFT (0U)
4542
4544 #define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
4545 #define CAN_WORD_DATA_BYTE_27_MASK (0xFFU)
4546 #define CAN_WORD_DATA_BYTE_27_SHIFT (0U)
4547
4549 #define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
4550 #define CAN_WORD_DATA_BYTE_31_MASK (0xFFU)
4551 #define CAN_WORD_DATA_BYTE_31_SHIFT (0U)
4552
4554 #define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
4555 #define CAN_WORD_DATA_BYTE_35_MASK (0xFFU)
4556 #define CAN_WORD_DATA_BYTE_35_SHIFT (0U)
4557
4559 #define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
4560 #define CAN_WORD_DATA_BYTE_39_MASK (0xFFU)
4561 #define CAN_WORD_DATA_BYTE_39_SHIFT (0U)
4562
4564 #define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
4565 #define CAN_WORD_DATA_BYTE_43_MASK (0xFFU)
4566 #define CAN_WORD_DATA_BYTE_43_SHIFT (0U)
4567
4569 #define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
4570 #define CAN_WORD_DATA_BYTE_47_MASK (0xFFU)
4571 #define CAN_WORD_DATA_BYTE_47_SHIFT (0U)
4572
4574 #define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
4575 #define CAN_WORD_DATA_BYTE_51_MASK (0xFFU)
4576 #define CAN_WORD_DATA_BYTE_51_SHIFT (0U)
4577
4579 #define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
4580 #define CAN_WORD_DATA_BYTE_55_MASK (0xFFU)
4581 #define CAN_WORD_DATA_BYTE_55_SHIFT (0U)
4582
4584 #define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
4585 #define CAN_WORD_DATA_BYTE_59_MASK (0xFFU)
4586 #define CAN_WORD_DATA_BYTE_59_SHIFT (0U)
4587
4589 #define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
4590 #define CAN_WORD_DATA_BYTE_63_MASK (0xFFU)
4591 #define CAN_WORD_DATA_BYTE_63_SHIFT (0U)
4592
4594 #define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
4595 #define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)
4596 #define CAN_WORD_DATA_BYTE_2_SHIFT (8U)
4597
4599 #define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
4600 #define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)
4601 #define CAN_WORD_DATA_BYTE_6_SHIFT (8U)
4602
4604 #define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
4605 #define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)
4606 #define CAN_WORD_DATA_BYTE_10_SHIFT (8U)
4607
4609 #define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
4610 #define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)
4611 #define CAN_WORD_DATA_BYTE_14_SHIFT (8U)
4612
4614 #define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
4615 #define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)
4616 #define CAN_WORD_DATA_BYTE_18_SHIFT (8U)
4617
4619 #define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
4620 #define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)
4621 #define CAN_WORD_DATA_BYTE_22_SHIFT (8U)
4622
4624 #define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
4625 #define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)
4626 #define CAN_WORD_DATA_BYTE_26_SHIFT (8U)
4627
4629 #define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
4630 #define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)
4631 #define CAN_WORD_DATA_BYTE_30_SHIFT (8U)
4632
4634 #define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
4635 #define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)
4636 #define CAN_WORD_DATA_BYTE_34_SHIFT (8U)
4637
4639 #define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
4640 #define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)
4641 #define CAN_WORD_DATA_BYTE_38_SHIFT (8U)
4642
4644 #define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
4645 #define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)
4646 #define CAN_WORD_DATA_BYTE_42_SHIFT (8U)
4647
4649 #define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
4650 #define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)
4651 #define CAN_WORD_DATA_BYTE_46_SHIFT (8U)
4652
4654 #define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
4655 #define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)
4656 #define CAN_WORD_DATA_BYTE_50_SHIFT (8U)
4657
4659 #define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
4660 #define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)
4661 #define CAN_WORD_DATA_BYTE_54_SHIFT (8U)
4662
4664 #define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
4665 #define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)
4666 #define CAN_WORD_DATA_BYTE_58_SHIFT (8U)
4667
4669 #define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
4670 #define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)
4671 #define CAN_WORD_DATA_BYTE_62_SHIFT (8U)
4672
4674 #define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
4675 #define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)
4676 #define CAN_WORD_DATA_BYTE_1_SHIFT (16U)
4677
4679 #define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
4680 #define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)
4681 #define CAN_WORD_DATA_BYTE_5_SHIFT (16U)
4682
4684 #define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
4685 #define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)
4686 #define CAN_WORD_DATA_BYTE_9_SHIFT (16U)
4687
4689 #define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
4690 #define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)
4691 #define CAN_WORD_DATA_BYTE_13_SHIFT (16U)
4692
4694 #define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
4695 #define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)
4696 #define CAN_WORD_DATA_BYTE_17_SHIFT (16U)
4697
4699 #define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
4700 #define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)
4701 #define CAN_WORD_DATA_BYTE_21_SHIFT (16U)
4702
4704 #define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
4705 #define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)
4706 #define CAN_WORD_DATA_BYTE_25_SHIFT (16U)
4707
4709 #define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
4710 #define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)
4711 #define CAN_WORD_DATA_BYTE_29_SHIFT (16U)
4712
4714 #define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
4715 #define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)
4716 #define CAN_WORD_DATA_BYTE_33_SHIFT (16U)
4717
4719 #define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
4720 #define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)
4721 #define CAN_WORD_DATA_BYTE_37_SHIFT (16U)
4722
4724 #define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
4725 #define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)
4726 #define CAN_WORD_DATA_BYTE_41_SHIFT (16U)
4727
4729 #define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
4730 #define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)
4731 #define CAN_WORD_DATA_BYTE_45_SHIFT (16U)
4732
4734 #define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
4735 #define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)
4736 #define CAN_WORD_DATA_BYTE_49_SHIFT (16U)
4737
4739 #define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
4740 #define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)
4741 #define CAN_WORD_DATA_BYTE_53_SHIFT (16U)
4742
4744 #define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
4745 #define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)
4746 #define CAN_WORD_DATA_BYTE_57_SHIFT (16U)
4747
4749 #define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
4750 #define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)
4751 #define CAN_WORD_DATA_BYTE_61_SHIFT (16U)
4752
4754 #define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
4755 #define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)
4756 #define CAN_WORD_DATA_BYTE_0_SHIFT (24U)
4757
4759 #define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
4760 #define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)
4761 #define CAN_WORD_DATA_BYTE_4_SHIFT (24U)
4762
4764 #define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
4765 #define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)
4766 #define CAN_WORD_DATA_BYTE_8_SHIFT (24U)
4767
4769 #define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
4770 #define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)
4771 #define CAN_WORD_DATA_BYTE_12_SHIFT (24U)
4772
4774 #define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
4775 #define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)
4776 #define CAN_WORD_DATA_BYTE_16_SHIFT (24U)
4777
4779 #define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
4780 #define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)
4781 #define CAN_WORD_DATA_BYTE_20_SHIFT (24U)
4782
4784 #define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
4785 #define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)
4786 #define CAN_WORD_DATA_BYTE_24_SHIFT (24U)
4787
4789 #define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
4790 #define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)
4791 #define CAN_WORD_DATA_BYTE_28_SHIFT (24U)
4792
4794 #define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
4795 #define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)
4796 #define CAN_WORD_DATA_BYTE_32_SHIFT (24U)
4797
4799 #define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
4800 #define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)
4801 #define CAN_WORD_DATA_BYTE_36_SHIFT (24U)
4802
4804 #define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
4805 #define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)
4806 #define CAN_WORD_DATA_BYTE_40_SHIFT (24U)
4807
4809 #define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
4810 #define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)
4811 #define CAN_WORD_DATA_BYTE_44_SHIFT (24U)
4812
4814 #define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
4815 #define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)
4816 #define CAN_WORD_DATA_BYTE_48_SHIFT (24U)
4817
4819 #define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
4820 #define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)
4821 #define CAN_WORD_DATA_BYTE_52_SHIFT (24U)
4822
4824 #define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
4825 #define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)
4826 #define CAN_WORD_DATA_BYTE_56_SHIFT (24U)
4827
4829 #define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
4830 #define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)
4831 #define CAN_WORD_DATA_BYTE_60_SHIFT (24U)
4832
4834 #define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
4835
4837 /* The count of CAN_WORD */
4838 #define CAN_WORD_COUNT_MB64B (14U)
4839
4840 /* The count of CAN_WORD */
4841 #define CAN_WORD_COUNT_MB64B2 (16U)
4842
4843 /* The count of CAN_CS */
4844 #define CAN_CS_COUNT (64U)
4845
4846 /* The count of CAN_ID */
4847 #define CAN_ID_COUNT (64U)
4848
4851 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4852 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4853
4855 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4856 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4857 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4858
4860 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4861 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4862 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4863
4865 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4866 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4867 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4868
4870 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4871
4873 /* The count of CAN_WORD0 */
4874 #define CAN_WORD0_COUNT (64U)
4875
4878 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4879 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4880
4882 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4883 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4884 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4885
4887 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4888 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4889 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4890
4892 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4893 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4894 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4895
4897 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4898
4900 /* The count of CAN_WORD1 */
4901 #define CAN_WORD1_COUNT (64U)
4902
4905 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4906 #define CAN_RXIMR_MI_SHIFT (0U)
4907
4911 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
4912
4914 /* The count of CAN_RXIMR */
4915 #define CAN_RXIMR_COUNT (64U)
4916
4919 #define CAN_GFWR_GFWR_MASK (0xFFU)
4920 #define CAN_GFWR_GFWR_SHIFT (0U)
4921 #define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
4922
4926 #define CAN_EPRS_ENPRESDIV_MASK (0x3FFU)
4927 #define CAN_EPRS_ENPRESDIV_SHIFT (0U)
4928
4930 #define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)
4931 #define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U)
4932 #define CAN_EPRS_EDPRESDIV_SHIFT (16U)
4933
4935 #define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
4936
4940 #define CAN_ENCBT_NTSEG1_MASK (0xFFU)
4941 #define CAN_ENCBT_NTSEG1_SHIFT (0U)
4942
4944 #define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)
4945 #define CAN_ENCBT_NTSEG2_MASK (0x7F000U)
4946 #define CAN_ENCBT_NTSEG2_SHIFT (12U)
4947
4949 #define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)
4950 #define CAN_ENCBT_NRJW_MASK (0x1FC00000U)
4951 #define CAN_ENCBT_NRJW_SHIFT (22U)
4952
4954 #define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
4955
4959 #define CAN_EDCBT_DTSEG1_MASK (0x1FU)
4960 #define CAN_EDCBT_DTSEG1_SHIFT (0U)
4961
4963 #define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)
4964 #define CAN_EDCBT_DTSEG2_MASK (0xF000U)
4965 #define CAN_EDCBT_DTSEG2_SHIFT (12U)
4966
4968 #define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)
4969 #define CAN_EDCBT_DRJW_MASK (0x3C00000U)
4970 #define CAN_EDCBT_DRJW_SHIFT (22U)
4971
4973 #define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
4974
4978 #define CAN_ETDC_ETDCVAL_MASK (0xFFU)
4979 #define CAN_ETDC_ETDCVAL_SHIFT (0U)
4980
4982 #define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)
4983 #define CAN_ETDC_ETDCOFF_MASK (0x7F0000U)
4984 #define CAN_ETDC_ETDCOFF_SHIFT (16U)
4985
4987 #define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)
4988 #define CAN_ETDC_TDMDIS_MASK (0x80000000U)
4989 #define CAN_ETDC_TDMDIS_SHIFT (31U)
4990
4994 #define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)
4995
4999 #define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
5000 #define CAN_FDCTRL_TDCVAL_SHIFT (0U)
5001
5003 #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
5004 #define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
5005 #define CAN_FDCTRL_TDCOFF_SHIFT (8U)
5006
5008 #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
5009 #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
5010 #define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
5011
5015 #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
5016 #define CAN_FDCTRL_TDCEN_MASK (0x8000U)
5017 #define CAN_FDCTRL_TDCEN_SHIFT (15U)
5018
5022 #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
5023 #define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
5024 #define CAN_FDCTRL_MBDSR0_SHIFT (16U)
5025
5031 #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
5032 #define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
5033 #define CAN_FDCTRL_MBDSR1_SHIFT (19U)
5034
5040 #define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
5041 #define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
5042 #define CAN_FDCTRL_FDRATE_SHIFT (31U)
5043
5047 #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
5048
5052 #define CAN_FDCBT_FPSEG2_MASK (0x7U)
5053 #define CAN_FDCBT_FPSEG2_SHIFT (0U)
5054
5056 #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
5057 #define CAN_FDCBT_FPSEG1_MASK (0xE0U)
5058 #define CAN_FDCBT_FPSEG1_SHIFT (5U)
5059
5061 #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
5062 #define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
5063 #define CAN_FDCBT_FPROPSEG_SHIFT (10U)
5064
5066 #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
5067 #define CAN_FDCBT_FRJW_MASK (0x70000U)
5068 #define CAN_FDCBT_FRJW_SHIFT (16U)
5069
5071 #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
5072 #define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
5073 #define CAN_FDCBT_FPRESDIV_SHIFT (20U)
5074
5076 #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
5077
5081 #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
5082 #define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
5083
5085 #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
5086 #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
5087 #define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
5088
5090 #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
5091
5095 #define CAN_ERFCR_ERFWM_MASK (0x1FU)
5096 #define CAN_ERFCR_ERFWM_SHIFT (0U)
5097
5099 #define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)
5100 #define CAN_ERFCR_NFE_MASK (0x3F00U)
5101 #define CAN_ERFCR_NFE_SHIFT (8U)
5102
5104 #define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)
5105 #define CAN_ERFCR_NEXIF_MASK (0x7F0000U)
5106 #define CAN_ERFCR_NEXIF_SHIFT (16U)
5107
5109 #define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)
5110 #define CAN_ERFCR_DMALW_MASK (0x7C000000U)
5111 #define CAN_ERFCR_DMALW_SHIFT (26U)
5112
5114 #define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)
5115 #define CAN_ERFCR_ERFEN_MASK (0x80000000U)
5116 #define CAN_ERFCR_ERFEN_SHIFT (31U)
5117
5121 #define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
5122
5126 #define CAN_ERFIER_ERFDAIE_MASK (0x10000000U)
5127 #define CAN_ERFIER_ERFDAIE_SHIFT (28U)
5128
5132 #define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)
5133 #define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U)
5134 #define CAN_ERFIER_ERFWMIIE_SHIFT (29U)
5135
5139 #define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)
5140 #define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U)
5141 #define CAN_ERFIER_ERFOVFIE_SHIFT (30U)
5142
5146 #define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)
5147 #define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U)
5148 #define CAN_ERFIER_ERFUFWIE_SHIFT (31U)
5149
5153 #define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
5154
5158 #define CAN_ERFSR_ERFEL_MASK (0x3FU)
5159 #define CAN_ERFSR_ERFEL_SHIFT (0U)
5160
5162 #define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)
5163 #define CAN_ERFSR_ERFF_MASK (0x10000U)
5164 #define CAN_ERFSR_ERFF_SHIFT (16U)
5165
5169 #define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)
5170 #define CAN_ERFSR_ERFE_MASK (0x20000U)
5171 #define CAN_ERFSR_ERFE_SHIFT (17U)
5172
5176 #define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)
5177 #define CAN_ERFSR_ERFCLR_MASK (0x8000000U)
5178 #define CAN_ERFSR_ERFCLR_SHIFT (27U)
5179
5183 #define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)
5184 #define CAN_ERFSR_ERFDA_MASK (0x10000000U)
5185 #define CAN_ERFSR_ERFDA_SHIFT (28U)
5186
5190 #define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)
5191 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U)
5192 #define CAN_ERFSR_ERFWMI_SHIFT (29U)
5193
5197 #define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
5198 #define CAN_ERFSR_ERFOVF_MASK (0x40000000U)
5199 #define CAN_ERFSR_ERFOVF_SHIFT (30U)
5200
5204 #define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)
5205 #define CAN_ERFSR_ERFUFW_MASK (0x80000000U)
5206 #define CAN_ERFSR_ERFUFW_SHIFT (31U)
5207
5211 #define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
5212
5216 #define CAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU)
5217 #define CAN_HR_TIME_STAMP_TS_SHIFT (0U)
5218
5220 #define CAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK)
5221
5223 /* The count of CAN_HR_TIME_STAMP */
5224 #define CAN_HR_TIME_STAMP_COUNT (64U)
5225
5228 #define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU)
5229 #define CAN_ERFFEL_FEL_SHIFT (0U)
5230
5232 #define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
5233
5235 /* The count of CAN_ERFFEL */
5236 #define CAN_ERFFEL_COUNT (128U)
5237
5238 /* end of group CAN_Register_Masks */
5242
5243
5244 /* CAN - Peripheral instance base addresses */
5246 #define CAN1_BASE (0x401D0000u)
5247
5248 #define CAN1 ((CAN_Type *)CAN1_BASE)
5249
5250 #define CAN2_BASE (0x401D4000u)
5251
5252 #define CAN2 ((CAN_Type *)CAN2_BASE)
5253
5254 #define CAN3_BASE (0x401D8000u)
5255
5256 #define CAN3 ((CAN_Type *)CAN3_BASE)
5257
5258 #define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
5259
5260 #define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
5261
5262 #define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5263 #define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5264 #define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5265 #define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5266 #define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5267 #define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5268 /* end of group CAN_Peripheral_Access_Layer */
5272
5273
5274 /* ----------------------------------------------------------------------------
5275 -- CCM Peripheral Access Layer
5276 ---------------------------------------------------------------------------- */
5277
5284 typedef struct {
5285 __IO uint32_t CCR;
5286 uint8_t RESERVED_0[4];
5287 __I uint32_t CSR;
5288 __IO uint32_t CCSR;
5289 __IO uint32_t CACRR;
5290 __IO uint32_t CBCDR;
5291 __IO uint32_t CBCMR;
5292 __IO uint32_t CSCMR1;
5293 __IO uint32_t CSCMR2;
5294 __IO uint32_t CSCDR1;
5295 __IO uint32_t CS1CDR;
5296 __IO uint32_t CS2CDR;
5297 __IO uint32_t CDCDR;
5298 uint8_t RESERVED_1[4];
5299 __IO uint32_t CSCDR2;
5300 __IO uint32_t CSCDR3;
5301 uint8_t RESERVED_2[8];
5302 __I uint32_t CDHIPR;
5303 uint8_t RESERVED_3[8];
5304 __IO uint32_t CLPCR;
5305 __IO uint32_t CISR;
5306 __IO uint32_t CIMR;
5307 __IO uint32_t CCOSR;
5308 __IO uint32_t CGPR;
5309 __IO uint32_t CCGR0;
5310 __IO uint32_t CCGR1;
5311 __IO uint32_t CCGR2;
5312 __IO uint32_t CCGR3;
5313 __IO uint32_t CCGR4;
5314 __IO uint32_t CCGR5;
5315 __IO uint32_t CCGR6;
5316 __IO uint32_t CCGR7;
5317 __IO uint32_t CMEOR;
5318 } CCM_Type;
5319
5320 /* ----------------------------------------------------------------------------
5321 -- CCM Register Masks
5322 ---------------------------------------------------------------------------- */
5323
5331 #define CCM_CCR_OSCNT_MASK (0xFFU)
5332 #define CCM_CCR_OSCNT_SHIFT (0U)
5333
5339 #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
5340 #define CCM_CCR_COSC_EN_MASK (0x1000U)
5341 #define CCM_CCR_COSC_EN_SHIFT (12U)
5342
5346 #define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
5347 #define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
5348 #define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
5349
5354 #define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
5355 #define CCM_CCR_RBC_EN_MASK (0x8000000U)
5356 #define CCM_CCR_RBC_EN_SHIFT (27U)
5357
5361 #define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
5362
5366 #define CCM_CSR_REF_EN_B_MASK (0x1U)
5367 #define CCM_CSR_REF_EN_B_SHIFT (0U)
5368
5372 #define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
5373 #define CCM_CSR_CAMP2_READY_MASK (0x8U)
5374 #define CCM_CSR_CAMP2_READY_SHIFT (3U)
5375
5379 #define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
5380 #define CCM_CSR_COSC_READY_MASK (0x20U)
5381 #define CCM_CSR_COSC_READY_SHIFT (5U)
5382
5386 #define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
5387
5391 #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
5392 #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
5393
5397 #define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
5398
5402 #define CCM_CACRR_ARM_PODF_MASK (0x7U)
5403 #define CCM_CACRR_ARM_PODF_SHIFT (0U)
5404
5414 #define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
5415
5419 #define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
5420 #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
5421
5425 #define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
5426 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
5427 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
5428
5432 #define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
5433 #define CCM_CBCDR_IPG_PODF_MASK (0x300U)
5434 #define CCM_CBCDR_IPG_PODF_SHIFT (8U)
5435
5441 #define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
5442 #define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
5443 #define CCM_CBCDR_AHB_PODF_SHIFT (10U)
5444
5454 #define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
5455 #define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
5456 #define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
5457
5467 #define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
5468 #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
5469 #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
5470
5474 #define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
5475 #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
5476 #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
5477
5487 #define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
5488
5492 #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
5493 #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
5494
5500 #define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
5501 #define CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK (0x300U)
5502 #define CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT (8U)
5503
5509 #define CCM_CBCMR_FLEXSPI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT)) & CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK)
5510 #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
5511 #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
5512
5518 #define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
5519 #define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
5520 #define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
5521
5527 #define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
5528 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
5529 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
5530
5536 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
5537 #define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
5538 #define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
5539
5549 #define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
5550 #define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
5551 #define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
5552
5562 #define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
5563 #define CCM_CBCMR_FLEXSPI2_PODF_MASK (0xE0000000U)
5564 #define CCM_CBCMR_FLEXSPI2_PODF_SHIFT (29U)
5565
5575 #define CCM_CBCMR_FLEXSPI2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_PODF_SHIFT)) & CCM_CBCMR_FLEXSPI2_PODF_MASK)
5576
5580 #define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
5581 #define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
5582
5648 #define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
5649 #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
5650 #define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
5651
5655 #define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
5656 #define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
5657 #define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
5658
5664 #define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
5665 #define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
5666 #define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
5667
5673 #define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
5674 #define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
5675 #define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
5676
5682 #define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
5683 #define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
5684 #define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
5685
5689 #define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
5690 #define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
5691 #define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
5692
5696 #define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
5697 #define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
5698 #define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
5699
5709 #define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
5710 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
5711 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
5712
5718 #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
5719
5723 #define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
5724 #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
5725
5791 #define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
5792 #define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
5793 #define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
5794
5800 #define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
5801 #define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
5802 #define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
5803
5809 #define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
5810
5814 #define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
5815 #define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
5816
5882 #define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
5883 #define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
5884 #define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
5885
5889 #define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
5890 #define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
5891 #define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
5892
5902 #define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
5903 #define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
5904 #define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
5905
5915 #define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
5916 #define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
5917 #define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
5918
5924 #define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
5925
5929 #define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
5930 #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
5931
5998 #define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
5999 #define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
6000 #define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
6001
6011 #define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
6012 #define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
6013 #define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
6014
6024 #define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
6025 #define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
6026 #define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
6027
6094 #define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
6095 #define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
6096 #define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
6097
6107 #define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
6108 #define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
6109 #define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
6110
6120 #define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
6121
6125 #define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
6126 #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
6127
6194 #define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
6195 #define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
6196 #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
6197
6207 #define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
6208
6212 #define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
6213 #define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
6214
6220 #define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
6221 #define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
6222 #define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
6223
6233 #define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
6234 #define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
6235 #define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
6236
6246 #define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
6247 #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
6248 #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
6249
6255 #define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
6256 #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
6257 #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
6258
6268 #define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
6269 #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
6270 #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
6271
6281 #define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
6282
6286 #define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
6287 #define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
6288
6298 #define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
6299 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
6300 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
6301
6309 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
6310 #define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
6311 #define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
6312
6316 #define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
6317 #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
6318 #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
6319
6387 #define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
6388
6392 #define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
6393 #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
6394
6400 #define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
6401 #define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
6402 #define CCM_CSCDR3_CSI_PODF_SHIFT (11U)
6403
6413 #define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
6414
6418 #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
6419 #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
6420
6425 #define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
6426 #define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
6427 #define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
6428
6433 #define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
6434 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
6435 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
6436
6441 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
6442 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
6443 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
6444
6449 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
6450 #define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
6451 #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
6452
6457 #define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
6458
6462 #define CCM_CLPCR_LPM_MASK (0x3U)
6463 #define CCM_CLPCR_LPM_SHIFT (0U)
6464
6470 #define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
6471 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
6472 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
6473
6477 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
6478 #define CCM_CLPCR_SBYOS_MASK (0x40U)
6479 #define CCM_CLPCR_SBYOS_SHIFT (6U)
6480
6488 #define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
6489 #define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
6490 #define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
6491
6495 #define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
6496 #define CCM_CLPCR_VSTBY_MASK (0x100U)
6497 #define CCM_CLPCR_VSTBY_SHIFT (8U)
6498
6502 #define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
6503 #define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
6504 #define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
6505
6511 #define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
6512 #define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
6513 #define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
6514
6518 #define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
6519 #define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
6520 #define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
6521 #define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
6522 #define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
6523 #define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
6524 #define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
6525 #define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
6526 #define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
6527
6531 #define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
6532 #define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
6533 #define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
6534
6538 #define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
6539 #define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
6540 #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
6541
6545 #define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
6546
6550 #define CCM_CISR_LRF_PLL_MASK (0x1U)
6551 #define CCM_CISR_LRF_PLL_SHIFT (0U)
6552
6556 #define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
6557 #define CCM_CISR_COSC_READY_MASK (0x40U)
6558 #define CCM_CISR_COSC_READY_SHIFT (6U)
6559
6563 #define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
6564 #define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
6565 #define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
6566
6570 #define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
6571 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6572 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6573
6577 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
6578 #define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
6579 #define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
6580
6584 #define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
6585 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6586 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6587
6591 #define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
6592 #define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
6593 #define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
6594
6598 #define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
6599
6603 #define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
6604 #define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
6605
6609 #define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
6610 #define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
6611 #define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
6612
6616 #define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
6617 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
6618 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
6619
6623 #define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
6624 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6625 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6626
6630 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
6631 #define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
6632 #define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
6633
6637 #define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
6638 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6639 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6640
6644 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
6645 #define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
6646 #define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
6647
6651 #define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
6652
6656 #define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
6657 #define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
6658
6671 #define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
6672 #define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
6673 #define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
6674
6684 #define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
6685 #define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
6686 #define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
6687
6691 #define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
6692 #define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
6693 #define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
6694
6698 #define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
6699 #define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
6700 #define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
6701
6716 #define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
6717 #define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
6718 #define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
6719
6729 #define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
6730 #define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
6731 #define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
6732
6736 #define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
6737
6741 #define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
6742 #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
6743
6747 #define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
6748 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
6749 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
6750
6754 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
6755 #define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
6756 #define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
6757
6762 #define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
6763 #define CCM_CGPR_FPL_MASK (0x10000U)
6764 #define CCM_CGPR_FPL_SHIFT (16U)
6765
6769 #define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
6770 #define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
6771 #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
6772
6777 #define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
6778
6782 #define CCM_CCGR0_CG0_MASK (0x3U)
6783 #define CCM_CCGR0_CG0_SHIFT (0U)
6784 #define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
6785 #define CCM_CCGR0_CG1_MASK (0xCU)
6786 #define CCM_CCGR0_CG1_SHIFT (2U)
6787 #define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
6788 #define CCM_CCGR0_CG2_MASK (0x30U)
6789 #define CCM_CCGR0_CG2_SHIFT (4U)
6790 #define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
6791 #define CCM_CCGR0_CG3_MASK (0xC0U)
6792 #define CCM_CCGR0_CG3_SHIFT (6U)
6793 #define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
6794 #define CCM_CCGR0_CG4_MASK (0x300U)
6795 #define CCM_CCGR0_CG4_SHIFT (8U)
6796 #define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
6797 #define CCM_CCGR0_CG5_MASK (0xC00U)
6798 #define CCM_CCGR0_CG5_SHIFT (10U)
6799 #define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
6800 #define CCM_CCGR0_CG6_MASK (0x3000U)
6801 #define CCM_CCGR0_CG6_SHIFT (12U)
6802 #define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
6803 #define CCM_CCGR0_CG7_MASK (0xC000U)
6804 #define CCM_CCGR0_CG7_SHIFT (14U)
6805 #define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
6806 #define CCM_CCGR0_CG8_MASK (0x30000U)
6807 #define CCM_CCGR0_CG8_SHIFT (16U)
6808 #define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
6809 #define CCM_CCGR0_CG9_MASK (0xC0000U)
6810 #define CCM_CCGR0_CG9_SHIFT (18U)
6811 #define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
6812 #define CCM_CCGR0_CG10_MASK (0x300000U)
6813 #define CCM_CCGR0_CG10_SHIFT (20U)
6814 #define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
6815 #define CCM_CCGR0_CG11_MASK (0xC00000U)
6816 #define CCM_CCGR0_CG11_SHIFT (22U)
6817 #define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
6818 #define CCM_CCGR0_CG12_MASK (0x3000000U)
6819 #define CCM_CCGR0_CG12_SHIFT (24U)
6820 #define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
6821 #define CCM_CCGR0_CG13_MASK (0xC000000U)
6822 #define CCM_CCGR0_CG13_SHIFT (26U)
6823 #define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
6824 #define CCM_CCGR0_CG14_MASK (0x30000000U)
6825 #define CCM_CCGR0_CG14_SHIFT (28U)
6826 #define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
6827 #define CCM_CCGR0_CG15_MASK (0xC0000000U)
6828 #define CCM_CCGR0_CG15_SHIFT (30U)
6829 #define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
6830
6834 #define CCM_CCGR1_CG0_MASK (0x3U)
6835 #define CCM_CCGR1_CG0_SHIFT (0U)
6836 #define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
6837 #define CCM_CCGR1_CG1_MASK (0xCU)
6838 #define CCM_CCGR1_CG1_SHIFT (2U)
6839 #define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
6840 #define CCM_CCGR1_CG2_MASK (0x30U)
6841 #define CCM_CCGR1_CG2_SHIFT (4U)
6842 #define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
6843 #define CCM_CCGR1_CG3_MASK (0xC0U)
6844 #define CCM_CCGR1_CG3_SHIFT (6U)
6845 #define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
6846 #define CCM_CCGR1_CG4_MASK (0x300U)
6847 #define CCM_CCGR1_CG4_SHIFT (8U)
6848 #define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
6849 #define CCM_CCGR1_CG5_MASK (0xC00U)
6850 #define CCM_CCGR1_CG5_SHIFT (10U)
6851 #define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
6852 #define CCM_CCGR1_CG6_MASK (0x3000U)
6853 #define CCM_CCGR1_CG6_SHIFT (12U)
6854 #define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
6855 #define CCM_CCGR1_CG7_MASK (0xC000U)
6856 #define CCM_CCGR1_CG7_SHIFT (14U)
6857 #define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
6858 #define CCM_CCGR1_CG8_MASK (0x30000U)
6859 #define CCM_CCGR1_CG8_SHIFT (16U)
6860 #define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
6861 #define CCM_CCGR1_CG9_MASK (0xC0000U)
6862 #define CCM_CCGR1_CG9_SHIFT (18U)
6863 #define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
6864 #define CCM_CCGR1_CG10_MASK (0x300000U)
6865 #define CCM_CCGR1_CG10_SHIFT (20U)
6866 #define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
6867 #define CCM_CCGR1_CG11_MASK (0xC00000U)
6868 #define CCM_CCGR1_CG11_SHIFT (22U)
6869 #define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
6870 #define CCM_CCGR1_CG12_MASK (0x3000000U)
6871 #define CCM_CCGR1_CG12_SHIFT (24U)
6872 #define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
6873 #define CCM_CCGR1_CG13_MASK (0xC000000U)
6874 #define CCM_CCGR1_CG13_SHIFT (26U)
6875 #define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
6876 #define CCM_CCGR1_CG14_MASK (0x30000000U)
6877 #define CCM_CCGR1_CG14_SHIFT (28U)
6878 #define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
6879 #define CCM_CCGR1_CG15_MASK (0xC0000000U)
6880 #define CCM_CCGR1_CG15_SHIFT (30U)
6881 #define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
6882
6886 #define CCM_CCGR2_CG0_MASK (0x3U)
6887 #define CCM_CCGR2_CG0_SHIFT (0U)
6888 #define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
6889 #define CCM_CCGR2_CG1_MASK (0xCU)
6890 #define CCM_CCGR2_CG1_SHIFT (2U)
6891 #define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
6892 #define CCM_CCGR2_CG2_MASK (0x30U)
6893 #define CCM_CCGR2_CG2_SHIFT (4U)
6894 #define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
6895 #define CCM_CCGR2_CG3_MASK (0xC0U)
6896 #define CCM_CCGR2_CG3_SHIFT (6U)
6897 #define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
6898 #define CCM_CCGR2_CG4_MASK (0x300U)
6899 #define CCM_CCGR2_CG4_SHIFT (8U)
6900 #define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
6901 #define CCM_CCGR2_CG5_MASK (0xC00U)
6902 #define CCM_CCGR2_CG5_SHIFT (10U)
6903 #define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
6904 #define CCM_CCGR2_CG6_MASK (0x3000U)
6905 #define CCM_CCGR2_CG6_SHIFT (12U)
6906 #define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
6907 #define CCM_CCGR2_CG7_MASK (0xC000U)
6908 #define CCM_CCGR2_CG7_SHIFT (14U)
6909 #define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
6910 #define CCM_CCGR2_CG8_MASK (0x30000U)
6911 #define CCM_CCGR2_CG8_SHIFT (16U)
6912 #define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
6913 #define CCM_CCGR2_CG9_MASK (0xC0000U)
6914 #define CCM_CCGR2_CG9_SHIFT (18U)
6915 #define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
6916 #define CCM_CCGR2_CG10_MASK (0x300000U)
6917 #define CCM_CCGR2_CG10_SHIFT (20U)
6918 #define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
6919 #define CCM_CCGR2_CG11_MASK (0xC00000U)
6920 #define CCM_CCGR2_CG11_SHIFT (22U)
6921 #define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
6922 #define CCM_CCGR2_CG12_MASK (0x3000000U)
6923 #define CCM_CCGR2_CG12_SHIFT (24U)
6924 #define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
6925 #define CCM_CCGR2_CG13_MASK (0xC000000U)
6926 #define CCM_CCGR2_CG13_SHIFT (26U)
6927 #define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
6928 #define CCM_CCGR2_CG14_MASK (0x30000000U)
6929 #define CCM_CCGR2_CG14_SHIFT (28U)
6930 #define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
6931 #define CCM_CCGR2_CG15_MASK (0xC0000000U)
6932 #define CCM_CCGR2_CG15_SHIFT (30U)
6933 #define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
6934
6938 #define CCM_CCGR3_CG0_MASK (0x3U)
6939 #define CCM_CCGR3_CG0_SHIFT (0U)
6940 #define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
6941 #define CCM_CCGR3_CG1_MASK (0xCU)
6942 #define CCM_CCGR3_CG1_SHIFT (2U)
6943 #define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
6944 #define CCM_CCGR3_CG2_MASK (0x30U)
6945 #define CCM_CCGR3_CG2_SHIFT (4U)
6946 #define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
6947 #define CCM_CCGR3_CG3_MASK (0xC0U)
6948 #define CCM_CCGR3_CG3_SHIFT (6U)
6949 #define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
6950 #define CCM_CCGR3_CG4_MASK (0x300U)
6951 #define CCM_CCGR3_CG4_SHIFT (8U)
6952 #define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
6953 #define CCM_CCGR3_CG5_MASK (0xC00U)
6954 #define CCM_CCGR3_CG5_SHIFT (10U)
6955 #define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
6956 #define CCM_CCGR3_CG6_MASK (0x3000U)
6957 #define CCM_CCGR3_CG6_SHIFT (12U)
6958 #define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
6959 #define CCM_CCGR3_CG7_MASK (0xC000U)
6960 #define CCM_CCGR3_CG7_SHIFT (14U)
6961 #define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
6962 #define CCM_CCGR3_CG8_MASK (0x30000U)
6963 #define CCM_CCGR3_CG8_SHIFT (16U)
6964 #define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
6965 #define CCM_CCGR3_CG9_MASK (0xC0000U)
6966 #define CCM_CCGR3_CG9_SHIFT (18U)
6967 #define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
6968 #define CCM_CCGR3_CG10_MASK (0x300000U)
6969 #define CCM_CCGR3_CG10_SHIFT (20U)
6970 #define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
6971 #define CCM_CCGR3_CG11_MASK (0xC00000U)
6972 #define CCM_CCGR3_CG11_SHIFT (22U)
6973 #define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
6974 #define CCM_CCGR3_CG12_MASK (0x3000000U)
6975 #define CCM_CCGR3_CG12_SHIFT (24U)
6976 #define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
6977 #define CCM_CCGR3_CG13_MASK (0xC000000U)
6978 #define CCM_CCGR3_CG13_SHIFT (26U)
6979 #define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
6980 #define CCM_CCGR3_CG14_MASK (0x30000000U)
6981 #define CCM_CCGR3_CG14_SHIFT (28U)
6982
6984 #define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
6985 #define CCM_CCGR3_CG15_MASK (0xC0000000U)
6986 #define CCM_CCGR3_CG15_SHIFT (30U)
6987 #define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
6988
6992 #define CCM_CCGR4_CG0_MASK (0x3U)
6993 #define CCM_CCGR4_CG0_SHIFT (0U)
6994 #define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
6995 #define CCM_CCGR4_CG1_MASK (0xCU)
6996 #define CCM_CCGR4_CG1_SHIFT (2U)
6997 #define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
6998 #define CCM_CCGR4_CG2_MASK (0x30U)
6999 #define CCM_CCGR4_CG2_SHIFT (4U)
7000 #define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
7001 #define CCM_CCGR4_CG3_MASK (0xC0U)
7002 #define CCM_CCGR4_CG3_SHIFT (6U)
7003 #define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
7004 #define CCM_CCGR4_CG4_MASK (0x300U)
7005 #define CCM_CCGR4_CG4_SHIFT (8U)
7006 #define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
7007 #define CCM_CCGR4_CG5_MASK (0xC00U)
7008 #define CCM_CCGR4_CG5_SHIFT (10U)
7009 #define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
7010 #define CCM_CCGR4_CG6_MASK (0x3000U)
7011 #define CCM_CCGR4_CG6_SHIFT (12U)
7012 #define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
7013 #define CCM_CCGR4_CG7_MASK (0xC000U)
7014 #define CCM_CCGR4_CG7_SHIFT (14U)
7015 #define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
7016 #define CCM_CCGR4_CG8_MASK (0x30000U)
7017 #define CCM_CCGR4_CG8_SHIFT (16U)
7018 #define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
7019 #define CCM_CCGR4_CG9_MASK (0xC0000U)
7020 #define CCM_CCGR4_CG9_SHIFT (18U)
7021 #define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
7022 #define CCM_CCGR4_CG10_MASK (0x300000U)
7023 #define CCM_CCGR4_CG10_SHIFT (20U)
7024 #define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
7025 #define CCM_CCGR4_CG11_MASK (0xC00000U)
7026 #define CCM_CCGR4_CG11_SHIFT (22U)
7027 #define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
7028 #define CCM_CCGR4_CG12_MASK (0x3000000U)
7029 #define CCM_CCGR4_CG12_SHIFT (24U)
7030 #define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
7031 #define CCM_CCGR4_CG13_MASK (0xC000000U)
7032 #define CCM_CCGR4_CG13_SHIFT (26U)
7033 #define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
7034 #define CCM_CCGR4_CG14_MASK (0x30000000U)
7035 #define CCM_CCGR4_CG14_SHIFT (28U)
7036 #define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
7037 #define CCM_CCGR4_CG15_MASK (0xC0000000U)
7038 #define CCM_CCGR4_CG15_SHIFT (30U)
7039 #define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
7040
7044 #define CCM_CCGR5_CG0_MASK (0x3U)
7045 #define CCM_CCGR5_CG0_SHIFT (0U)
7046 #define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
7047 #define CCM_CCGR5_CG1_MASK (0xCU)
7048 #define CCM_CCGR5_CG1_SHIFT (2U)
7049 #define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
7050 #define CCM_CCGR5_CG2_MASK (0x30U)
7051 #define CCM_CCGR5_CG2_SHIFT (4U)
7052 #define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
7053 #define CCM_CCGR5_CG3_MASK (0xC0U)
7054 #define CCM_CCGR5_CG3_SHIFT (6U)
7055 #define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
7056 #define CCM_CCGR5_CG4_MASK (0x300U)
7057 #define CCM_CCGR5_CG4_SHIFT (8U)
7058 #define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
7059 #define CCM_CCGR5_CG5_MASK (0xC00U)
7060 #define CCM_CCGR5_CG5_SHIFT (10U)
7061 #define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
7062 #define CCM_CCGR5_CG6_MASK (0x3000U)
7063 #define CCM_CCGR5_CG6_SHIFT (12U)
7064 #define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
7065 #define CCM_CCGR5_CG7_MASK (0xC000U)
7066 #define CCM_CCGR5_CG7_SHIFT (14U)
7067 #define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
7068 #define CCM_CCGR5_CG8_MASK (0x30000U)
7069 #define CCM_CCGR5_CG8_SHIFT (16U)
7070 #define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
7071 #define CCM_CCGR5_CG9_MASK (0xC0000U)
7072 #define CCM_CCGR5_CG9_SHIFT (18U)
7073 #define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
7074 #define CCM_CCGR5_CG10_MASK (0x300000U)
7075 #define CCM_CCGR5_CG10_SHIFT (20U)
7076 #define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
7077 #define CCM_CCGR5_CG11_MASK (0xC00000U)
7078 #define CCM_CCGR5_CG11_SHIFT (22U)
7079 #define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
7080 #define CCM_CCGR5_CG12_MASK (0x3000000U)
7081 #define CCM_CCGR5_CG12_SHIFT (24U)
7082 #define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
7083 #define CCM_CCGR5_CG13_MASK (0xC000000U)
7084 #define CCM_CCGR5_CG13_SHIFT (26U)
7085 #define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
7086 #define CCM_CCGR5_CG14_MASK (0x30000000U)
7087 #define CCM_CCGR5_CG14_SHIFT (28U)
7088 #define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
7089 #define CCM_CCGR5_CG15_MASK (0xC0000000U)
7090 #define CCM_CCGR5_CG15_SHIFT (30U)
7091 #define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
7092
7096 #define CCM_CCGR6_CG0_MASK (0x3U)
7097 #define CCM_CCGR6_CG0_SHIFT (0U)
7098 #define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
7099 #define CCM_CCGR6_CG1_MASK (0xCU)
7100 #define CCM_CCGR6_CG1_SHIFT (2U)
7101 #define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
7102 #define CCM_CCGR6_CG2_MASK (0x30U)
7103 #define CCM_CCGR6_CG2_SHIFT (4U)
7104 #define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
7105 #define CCM_CCGR6_CG3_MASK (0xC0U)
7106 #define CCM_CCGR6_CG3_SHIFT (6U)
7107 #define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
7108 #define CCM_CCGR6_CG4_MASK (0x300U)
7109 #define CCM_CCGR6_CG4_SHIFT (8U)
7110 #define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
7111 #define CCM_CCGR6_CG5_MASK (0xC00U)
7112 #define CCM_CCGR6_CG5_SHIFT (10U)
7113 #define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
7114 #define CCM_CCGR6_CG6_MASK (0x3000U)
7115 #define CCM_CCGR6_CG6_SHIFT (12U)
7116 #define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
7117 #define CCM_CCGR6_CG7_MASK (0xC000U)
7118 #define CCM_CCGR6_CG7_SHIFT (14U)
7119 #define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
7120 #define CCM_CCGR6_CG8_MASK (0x30000U)
7121 #define CCM_CCGR6_CG8_SHIFT (16U)
7122 #define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
7123 #define CCM_CCGR6_CG9_MASK (0xC0000U)
7124 #define CCM_CCGR6_CG9_SHIFT (18U)
7125 #define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
7126 #define CCM_CCGR6_CG10_MASK (0x300000U)
7127 #define CCM_CCGR6_CG10_SHIFT (20U)
7128 #define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
7129 #define CCM_CCGR6_CG11_MASK (0xC00000U)
7130 #define CCM_CCGR6_CG11_SHIFT (22U)
7131 #define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
7132 #define CCM_CCGR6_CG12_MASK (0x3000000U)
7133 #define CCM_CCGR6_CG12_SHIFT (24U)
7134 #define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
7135 #define CCM_CCGR6_CG13_MASK (0xC000000U)
7136 #define CCM_CCGR6_CG13_SHIFT (26U)
7137 #define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
7138 #define CCM_CCGR6_CG14_MASK (0x30000000U)
7139 #define CCM_CCGR6_CG14_SHIFT (28U)
7140 #define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
7141 #define CCM_CCGR6_CG15_MASK (0xC0000000U)
7142 #define CCM_CCGR6_CG15_SHIFT (30U)
7143 #define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
7144
7148 #define CCM_CCGR7_CG0_MASK (0x3U)
7149 #define CCM_CCGR7_CG0_SHIFT (0U)
7150 #define CCM_CCGR7_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG0_SHIFT)) & CCM_CCGR7_CG0_MASK)
7151 #define CCM_CCGR7_CG1_MASK (0xCU)
7152 #define CCM_CCGR7_CG1_SHIFT (2U)
7153 #define CCM_CCGR7_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG1_SHIFT)) & CCM_CCGR7_CG1_MASK)
7154 #define CCM_CCGR7_CG2_MASK (0x30U)
7155 #define CCM_CCGR7_CG2_SHIFT (4U)
7156 #define CCM_CCGR7_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG2_SHIFT)) & CCM_CCGR7_CG2_MASK)
7157 #define CCM_CCGR7_CG3_MASK (0xC0U)
7158 #define CCM_CCGR7_CG3_SHIFT (6U)
7159 #define CCM_CCGR7_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG3_SHIFT)) & CCM_CCGR7_CG3_MASK)
7160 #define CCM_CCGR7_CG4_MASK (0x300U)
7161 #define CCM_CCGR7_CG4_SHIFT (8U)
7162 #define CCM_CCGR7_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG4_SHIFT)) & CCM_CCGR7_CG4_MASK)
7163 #define CCM_CCGR7_CG5_MASK (0xC00U)
7164 #define CCM_CCGR7_CG5_SHIFT (10U)
7165 #define CCM_CCGR7_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG5_SHIFT)) & CCM_CCGR7_CG5_MASK)
7166 #define CCM_CCGR7_CG6_MASK (0x3000U)
7167 #define CCM_CCGR7_CG6_SHIFT (12U)
7168 #define CCM_CCGR7_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG6_SHIFT)) & CCM_CCGR7_CG6_MASK)
7169
7173 #define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
7174 #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
7175
7179 #define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
7180 #define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
7181 #define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
7182
7186 #define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
7187 #define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
7188 #define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
7189
7193 #define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
7194 #define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
7195 #define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
7196
7200 #define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
7201 #define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK (0x400U)
7202 #define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT (10U)
7203
7207 #define CCM_CMEOR_MOD_EN_OV_CANFD_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK)
7208 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
7209 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
7210
7214 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
7215 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
7216 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
7217
7221 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
7222 /* end of group CCM_Register_Masks */
7228
7229
7230 /* CCM - Peripheral instance base addresses */
7232 #define CCM_BASE (0x400FC000u)
7233
7234 #define CCM ((CCM_Type *)CCM_BASE)
7235
7236 #define CCM_BASE_ADDRS { CCM_BASE }
7237
7238 #define CCM_BASE_PTRS { CCM }
7239
7240 #define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
7241 /* end of group CCM_Peripheral_Access_Layer */
7245
7246
7247 /* ----------------------------------------------------------------------------
7248 -- CCM_ANALOG Peripheral Access Layer
7249 ---------------------------------------------------------------------------- */
7250
7257 typedef struct {
7258 __IO uint32_t PLL_ARM;
7259 __IO uint32_t PLL_ARM_SET;
7260 __IO uint32_t PLL_ARM_CLR;
7261 __IO uint32_t PLL_ARM_TOG;
7262 __IO uint32_t PLL_USB1;
7263 __IO uint32_t PLL_USB1_SET;
7264 __IO uint32_t PLL_USB1_CLR;
7265 __IO uint32_t PLL_USB1_TOG;
7266 __IO uint32_t PLL_USB2;
7267 __IO uint32_t PLL_USB2_SET;
7268 __IO uint32_t PLL_USB2_CLR;
7269 __IO uint32_t PLL_USB2_TOG;
7270 __IO uint32_t PLL_SYS;
7271 __IO uint32_t PLL_SYS_SET;
7272 __IO uint32_t PLL_SYS_CLR;
7273 __IO uint32_t PLL_SYS_TOG;
7274 __IO uint32_t PLL_SYS_SS;
7275 uint8_t RESERVED_0[12];
7276 __IO uint32_t PLL_SYS_NUM;
7277 uint8_t RESERVED_1[12];
7278 __IO uint32_t PLL_SYS_DENOM;
7279 uint8_t RESERVED_2[12];
7280 __IO uint32_t PLL_AUDIO;
7281 __IO uint32_t PLL_AUDIO_SET;
7282 __IO uint32_t PLL_AUDIO_CLR;
7283 __IO uint32_t PLL_AUDIO_TOG;
7284 __IO uint32_t PLL_AUDIO_NUM;
7285 uint8_t RESERVED_3[12];
7286 __IO uint32_t PLL_AUDIO_DENOM;
7287 uint8_t RESERVED_4[12];
7288 __IO uint32_t PLL_VIDEO;
7289 __IO uint32_t PLL_VIDEO_SET;
7290 __IO uint32_t PLL_VIDEO_CLR;
7291 __IO uint32_t PLL_VIDEO_TOG;
7292 __IO uint32_t PLL_VIDEO_NUM;
7293 uint8_t RESERVED_5[12];
7294 __IO uint32_t PLL_VIDEO_DENOM;
7295 uint8_t RESERVED_6[28];
7296 __IO uint32_t PLL_ENET;
7297 __IO uint32_t PLL_ENET_SET;
7298 __IO uint32_t PLL_ENET_CLR;
7299 __IO uint32_t PLL_ENET_TOG;
7300 __IO uint32_t PFD_480;
7301 __IO uint32_t PFD_480_SET;
7302 __IO uint32_t PFD_480_CLR;
7303 __IO uint32_t PFD_480_TOG;
7304 __IO uint32_t PFD_528;
7305 __IO uint32_t PFD_528_SET;
7306 __IO uint32_t PFD_528_CLR;
7307 __IO uint32_t PFD_528_TOG;
7308 uint8_t RESERVED_7[64];
7309 __IO uint32_t MISC0;
7310 __IO uint32_t MISC0_SET;
7311 __IO uint32_t MISC0_CLR;
7312 __IO uint32_t MISC0_TOG;
7313 __IO uint32_t MISC1;
7314 __IO uint32_t MISC1_SET;
7315 __IO uint32_t MISC1_CLR;
7316 __IO uint32_t MISC1_TOG;
7317 __IO uint32_t MISC2;
7318 __IO uint32_t MISC2_SET;
7319 __IO uint32_t MISC2_CLR;
7320 __IO uint32_t MISC2_TOG;
7321 } CCM_ANALOG_Type;
7322
7323 /* ----------------------------------------------------------------------------
7324 -- CCM_ANALOG Register Masks
7325 ---------------------------------------------------------------------------- */
7326
7334 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
7335 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
7336 #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
7337 #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
7338 #define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
7339 #define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
7340 #define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
7341 #define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
7342 #define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
7343 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
7344 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
7345
7351 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
7352 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
7353 #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
7354 #define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
7355 #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
7356 #define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
7357 #define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
7358 #define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
7359 #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
7360 #define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
7361
7365 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
7366 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
7367 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
7368 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
7369 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
7370 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
7371 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
7372 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
7373 #define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
7374 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7375 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
7376
7382 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
7383 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
7384 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
7385 #define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
7386 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
7387 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
7388 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
7389 #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
7390 #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
7391 #define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
7392
7396 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
7397 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
7398 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
7399 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
7400 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
7401 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
7402 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
7403 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
7404 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
7405 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7406 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7407
7413 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
7414 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
7415 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
7416 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
7417 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
7418 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
7419 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
7420 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
7421 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
7422 #define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
7423
7427 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
7428 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
7429 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
7430 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
7431 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
7432 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
7433 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
7434 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
7435 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
7436 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7437 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7438
7444 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
7445 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
7446 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
7447 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
7448 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
7449 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
7450 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
7451 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
7452 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
7453 #define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
7454
7458 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
7459 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
7460 #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
7461 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
7462 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
7463
7467 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
7468 #define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
7469 #define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
7470 #define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
7471 #define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
7472 #define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
7473 #define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
7474 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
7475 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
7476
7480 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
7481 #define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
7482 #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
7483 #define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
7484 #define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
7485 #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
7486 #define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
7487
7491 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
7492 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
7493 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
7494 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
7495 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
7496
7500 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
7501 #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
7502 #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
7503 #define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
7504 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
7505 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
7506 #define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
7507 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7508 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
7509
7513 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
7514 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
7515 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
7516 #define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
7517 #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
7518 #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
7519 #define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
7520
7524 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
7525 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
7526 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
7527 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
7528 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
7529
7533 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
7534 #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
7535 #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
7536 #define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
7537 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
7538 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
7539 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
7540 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7541 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7542
7546 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
7547 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
7548 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
7549 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
7550 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
7551 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
7552 #define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
7553
7557 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
7558 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
7559 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
7560 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
7561 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
7562
7566 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
7567 #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
7568 #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
7569 #define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
7570 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
7571 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
7572 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
7573 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7574 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7575
7579 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
7580 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
7581 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
7582 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
7583 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
7584 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
7585 #define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
7586
7590 #define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
7591 #define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
7592 #define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
7593 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
7594 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
7595 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
7596 #define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
7597 #define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
7598 #define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
7599 #define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
7600 #define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
7601 #define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
7602 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
7603 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
7604
7610 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
7611 #define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
7612 #define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
7613 #define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
7614 #define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
7615 #define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
7616 #define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
7617
7621 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
7622 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
7623 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
7624 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
7625 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
7626 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
7627 #define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
7628 #define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
7629 #define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
7630 #define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
7631 #define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
7632 #define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
7633 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7634 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
7635
7641 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
7642 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
7643 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
7644 #define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
7645 #define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
7646 #define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
7647 #define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
7648
7652 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
7653 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
7654 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
7655 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
7656 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
7657 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
7658 #define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
7659 #define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
7660 #define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
7661 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
7662 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
7663 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
7664 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7665 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7666
7672 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
7673 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
7674 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
7675 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
7676 #define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
7677 #define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
7678 #define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
7679
7683 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
7684 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
7685 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
7686 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
7687 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
7688 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
7689 #define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
7690 #define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
7691 #define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
7692 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
7693 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
7694 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
7695 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7696 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7697
7703 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
7704 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
7705 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
7706 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
7707 #define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
7708 #define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
7709 #define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
7710
7714 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
7715 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
7716 #define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
7717 #define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
7718 #define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
7719 #define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
7720 #define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
7721 #define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
7722 #define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
7723 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
7724 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
7725
7729 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
7730 #define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
7731 #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
7732 #define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
7733 #define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
7734 #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
7735 #define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
7736
7740 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
7741 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
7742 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
7743 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
7744 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
7745 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
7746 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
7747 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
7748 #define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
7749 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7750 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
7751
7755 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
7756 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
7757 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
7758 #define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
7759 #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
7760 #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
7761 #define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
7762
7766 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
7767 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
7768 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
7769 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
7770 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
7771 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
7772 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
7773 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
7774 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
7775 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7776 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7777
7781 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
7782 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
7783 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
7784 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
7785 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
7786 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
7787 #define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
7788
7792 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
7793 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
7794 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
7795 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
7796 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
7797 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
7798 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
7799 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
7800 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
7801 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7802 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7803
7807 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
7808 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
7809 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
7810 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
7811 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
7812 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
7813 #define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
7814
7818 #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
7819 #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
7820 #define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
7821 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
7822 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
7823
7827 #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
7828 #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
7829 #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
7830 #define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
7831
7835 #define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
7836 #define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
7837 #define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
7838
7842 #define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
7843 #define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
7844 #define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
7845
7849 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
7850 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
7851 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
7852 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
7853 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
7854 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
7855 #define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
7856 #define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
7857 #define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
7858 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
7859 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
7860
7866 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
7867 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
7868 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
7869 #define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
7870 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
7871 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
7872
7878 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
7879 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
7880 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
7881 #define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
7882
7886 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
7887 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
7888 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
7889 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
7890 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
7891 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
7892 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
7893 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
7894 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
7895 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7896 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
7897
7903 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
7904 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
7905 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
7906 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
7907 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
7908 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
7909
7915 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
7916 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
7917 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
7918 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
7919
7923 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
7924 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
7925 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
7926 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
7927 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
7928 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
7929 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
7930 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
7931 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
7932 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7933 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7934
7940 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
7941 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
7942 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
7943 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
7944 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
7945 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
7946
7952 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
7953 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
7954 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
7955 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
7956
7960 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
7961 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
7962 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
7963 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
7964 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
7965 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
7966 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
7967 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
7968 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
7969 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7970 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7971
7977 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
7978 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
7979 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
7980 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
7981 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
7982 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
7983
7989 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
7990 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
7991 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
7992 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
7993
7997 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
7998 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
7999 #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
8000
8004 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
8005 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
8006 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
8007
8011 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
8012 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
8013 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
8014 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
8015 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
8016 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
8017 #define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
8018 #define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
8019 #define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
8020 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
8021 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
8022
8028 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
8029 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
8030 #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
8031 #define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
8032 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
8033 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
8034
8040 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
8041 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
8042 #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
8043 #define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
8044
8048 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
8049 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
8050 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
8051 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
8052 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
8053 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
8054 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
8055 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
8056 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
8057 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
8058 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
8059
8065 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
8066 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
8067 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
8068 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
8069 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
8070 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
8071
8077 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
8078 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
8079 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
8080 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
8081
8085 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
8086 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
8087 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
8088 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
8089 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
8090 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
8091 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
8092 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
8093 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
8094 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8095 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8096
8102 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
8103 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
8104 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
8105 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
8106 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
8107 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
8108
8114 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
8115 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
8116 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
8117 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
8118
8122 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
8123 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
8124 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
8125 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
8126 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
8127 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
8128 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
8129 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
8130 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
8131 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8132 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8133
8139 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
8140 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
8141 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
8142 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
8143 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
8144 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
8145
8151 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
8152 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
8153 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
8154 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
8155
8159 #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
8160 #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
8161 #define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
8162
8166 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
8167 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
8168 #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
8169
8173 #define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
8174 #define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
8175 #define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
8176 #define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK (0xCU)
8177 #define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT (2U)
8178
8184 #define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)
8185 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
8186 #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
8187 #define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
8188 #define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
8189 #define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
8190 #define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
8191 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
8192 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
8193
8199 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
8200 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
8201 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
8202 #define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
8203 #define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK (0x100000U)
8204 #define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT (20U)
8205 #define CCM_ANALOG_PLL_ENET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK)
8206 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
8207 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
8208 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
8209 #define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
8210 #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
8211 #define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
8212
8216 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
8217 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
8218 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
8219 #define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK (0xCU)
8220 #define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT (2U)
8221
8227 #define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK)
8228 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
8229 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
8230 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
8231 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
8232 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
8233 #define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
8234 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
8235 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
8236
8242 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
8243 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
8244 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
8245 #define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
8246 #define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK (0x100000U)
8247 #define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT (20U)
8248 #define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK)
8249 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
8250 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
8251 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
8252 #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
8253 #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
8254 #define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
8255
8259 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
8260 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
8261 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
8262 #define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK (0xCU)
8263 #define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT (2U)
8264
8270 #define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK)
8271 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
8272 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
8273 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
8274 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
8275 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
8276 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
8277 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8278 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8279
8285 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
8286 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
8287 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
8288 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
8289 #define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK (0x100000U)
8290 #define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT (20U)
8291 #define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK)
8292 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
8293 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
8294 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
8295 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
8296 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
8297 #define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
8298
8302 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
8303 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
8304 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
8305 #define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK (0xCU)
8306 #define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT (2U)
8307
8313 #define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK)
8314 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
8315 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
8316 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
8317 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
8318 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
8319 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
8320 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8321 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8322
8328 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
8329 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
8330 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
8331 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
8332 #define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK (0x100000U)
8333 #define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT (20U)
8334 #define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK)
8335 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
8336 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
8337 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
8338 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
8339 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
8340 #define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
8341
8345 #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
8346 #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
8347 #define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
8348 #define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
8349 #define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
8350 #define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
8351 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
8352 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
8353 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
8354 #define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
8355 #define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
8356 #define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
8357 #define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
8358 #define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
8359 #define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
8360 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
8361 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
8362 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
8363 #define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
8364 #define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
8365 #define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
8366 #define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
8367 #define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
8368 #define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
8369 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
8370 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
8371 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
8372 #define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
8373 #define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
8374 #define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
8375 #define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
8376 #define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
8377 #define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
8378 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
8379 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
8380 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
8381
8385 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
8386 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
8387 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
8388 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
8389 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
8390 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
8391 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
8392 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
8393 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
8394 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
8395 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
8396 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
8397 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
8398 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
8399 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
8400 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
8401 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
8402 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
8403 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
8404 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
8405 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
8406 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
8407 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
8408 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
8409 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
8410 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
8411 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
8412 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
8413 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
8414 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
8415 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
8416 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
8417 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
8418 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
8419 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
8420 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
8421
8425 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
8426 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
8427 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
8428 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
8429 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
8430 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
8431 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
8432 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
8433 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
8434 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
8435 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
8436 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
8437 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
8438 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
8439 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
8440 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
8441 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
8442 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
8443 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
8444 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
8445 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
8446 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
8447 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
8448 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
8449 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
8450 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
8451 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
8452 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
8453 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
8454 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
8455 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
8456 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
8457 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
8458 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8459 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
8460 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
8461
8465 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
8466 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
8467 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
8468 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
8469 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
8470 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
8471 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
8472 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
8473 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
8474 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
8475 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
8476 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
8477 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
8478 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
8479 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
8480 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
8481 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
8482 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
8483 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
8484 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
8485 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
8486 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
8487 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
8488 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
8489 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
8490 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
8491 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
8492 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
8493 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
8494 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
8495 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
8496 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
8497 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
8498 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8499 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
8500 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
8501
8505 #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
8506 #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
8507 #define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
8508 #define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
8509 #define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
8510 #define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
8511 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
8512 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
8513 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
8514 #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
8515 #define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
8516 #define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
8517 #define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
8518 #define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
8519 #define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
8520 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
8521 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
8522 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
8523 #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
8524 #define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
8525 #define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
8526 #define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
8527 #define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
8528 #define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
8529 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
8530 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
8531 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
8532 #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
8533 #define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
8534 #define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
8535 #define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
8536 #define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
8537 #define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
8538 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
8539 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
8540 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
8541
8545 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
8546 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
8547 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
8548 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
8549 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
8550 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
8551 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
8552 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
8553 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
8554 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
8555 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
8556 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
8557 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
8558 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
8559 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
8560 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
8561 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
8562 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
8563 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
8564 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
8565 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
8566 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
8567 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
8568 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
8569 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
8570 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
8571 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
8572 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
8573 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
8574 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
8575 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
8576 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
8577 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
8578 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
8579 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
8580 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
8581
8585 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
8586 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
8587 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
8588 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
8589 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
8590 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
8591 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
8592 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
8593 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
8594 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
8595 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
8596 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
8597 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
8598 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
8599 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
8600 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
8601 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
8602 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
8603 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
8604 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
8605 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
8606 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
8607 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
8608 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
8609 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
8610 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
8611 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
8612 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
8613 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
8614 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
8615 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
8616 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
8617 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
8618 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8619 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
8620 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
8621
8625 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
8626 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
8627 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
8628 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
8629 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
8630 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
8631 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
8632 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
8633 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
8634 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
8635 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
8636 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
8637 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
8638 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
8639 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
8640 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
8641 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
8642 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
8643 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
8644 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
8645 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
8646 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
8647 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
8648 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
8649 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
8650 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
8651 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
8652 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
8653 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
8654 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
8655 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
8656 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
8657 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
8658 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8659 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
8660 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
8661
8665 #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
8666 #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
8667 #define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
8668 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
8669 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
8670
8674 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
8675 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
8676 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
8677
8687 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
8688 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
8689 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
8690 #define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
8691 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
8692 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
8693
8700 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
8701 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
8702 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
8703
8707 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
8708 #define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
8709 #define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
8710
8716 #define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
8717 #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
8718 #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
8719 #define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
8720 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
8721 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
8722 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
8723 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
8724 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
8725
8729 #define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
8730 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
8731 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
8732
8742 #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
8743 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
8744 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
8745
8749 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
8750 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
8751 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
8752 #define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
8753
8757 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
8758 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
8759 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
8760 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
8761 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
8762
8766 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
8767 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
8768 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
8769
8779 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
8780 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
8781 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
8782 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
8783 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
8784 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
8785
8792 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
8793 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
8794 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
8795
8799 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
8800 #define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
8801 #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
8802
8808 #define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
8809 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
8810 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
8811 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
8812 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
8813 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
8814 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
8815 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
8816 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
8817
8821 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
8822 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
8823 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
8824
8834 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
8835 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
8836 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
8837
8841 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
8842 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
8843 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
8844 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
8845
8849 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
8850 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
8851 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
8852 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
8853 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
8854
8858 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
8859 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
8860 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
8861
8871 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
8872 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
8873 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
8874 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
8875 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
8876 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
8877
8884 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
8885 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
8886 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
8887
8891 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
8892 #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
8893 #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
8894
8900 #define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
8901 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
8902 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
8903 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
8904 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
8905 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
8906 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
8907 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
8908 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
8909
8913 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
8914 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
8915 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
8916
8926 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
8927 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
8928 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
8929
8933 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
8934 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
8935 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
8936 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
8937
8941 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
8942 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
8943 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
8944 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
8945 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
8946
8950 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
8951 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
8952 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
8953
8963 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
8964 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
8965 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
8966 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
8967 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
8968 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
8969
8976 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
8977 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
8978 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
8979
8983 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
8984 #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
8985 #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
8986
8992 #define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
8993 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
8994 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
8995 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
8996 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
8997 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
8998 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
8999 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
9000 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
9001
9005 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
9006 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
9007 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
9008
9018 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
9019 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
9020 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
9021
9025 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
9026 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
9027 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
9028 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
9029
9033 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
9034 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
9035
9053 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
9054 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
9055 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
9056 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
9057 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
9058 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
9059 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
9060 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9061 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
9062 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
9063 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9064 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
9065 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
9066 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
9067 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
9068 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
9069 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
9070 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
9071 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
9072 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
9073 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
9074 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
9075 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
9076 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
9077 #define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
9078 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
9079 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
9080 #define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
9081
9085 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
9086 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
9087
9105 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
9106 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
9107 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
9108 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
9109 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
9110 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
9111 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
9112 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9113 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
9114 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
9115 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9116 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
9117 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
9118 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
9119 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
9120 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
9121 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
9122 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
9123 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
9124 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
9125 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
9126 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
9127 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
9128 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
9129 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
9130 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
9131 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
9132 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
9133
9137 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
9138 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
9139
9157 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
9158 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
9159 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
9160 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
9161 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
9162 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
9163 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
9164 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9165 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
9166 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
9167 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9168 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
9169 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
9170 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
9171 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
9172 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
9173 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
9174 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
9175 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
9176 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
9177 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
9178 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
9179 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
9180 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
9181 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
9182 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
9183 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
9184 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
9185
9189 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
9190 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
9191
9209 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
9210 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
9211 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
9212 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
9213 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
9214 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
9215 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
9216 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9217 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
9218 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
9219 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9220 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
9221 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
9222 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
9223 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
9224 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
9225 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
9226 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
9227 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
9228 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
9229 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
9230 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
9231 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
9232 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
9233 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
9234 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
9235 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
9236 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
9237
9241 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
9242 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
9243
9247 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
9248 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
9249 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
9250
9253 #define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
9254 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
9255 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
9256 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
9257 #define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
9258 #define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
9259 #define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
9260 #define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U)
9261 #define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U)
9262
9266 #define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)
9267 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
9268 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
9269
9273 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
9274 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
9275 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
9276
9279 #define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
9280 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
9281 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
9282 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
9283 #define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
9284 #define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
9285 #define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
9286 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
9287 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
9288
9292 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
9293 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
9294 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
9295
9299 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
9300 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
9301 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
9302 #define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
9303 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
9304 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
9305 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
9306 #define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
9307 #define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
9308 #define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
9309 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
9310 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
9311
9315 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
9316 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
9317 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
9318
9324 #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
9325 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
9326 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
9327
9333 #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
9334 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
9335 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
9336
9342 #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
9343 #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
9344 #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
9345
9351 #define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
9352
9356 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
9357 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
9358
9362 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
9363 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
9364 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
9365
9368 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
9369 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
9370 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
9371 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
9372 #define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
9373 #define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
9374 #define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
9375 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)
9376 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)
9377
9381 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)
9382 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
9383 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
9384
9388 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
9389 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
9390 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
9391
9394 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
9395 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
9396 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
9397 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
9398 #define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
9399 #define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
9400 #define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
9401 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
9402 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
9403
9407 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
9408 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
9409 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
9410
9414 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
9415 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
9416 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
9417 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
9418 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
9419 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
9420 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
9421 #define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
9422 #define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
9423 #define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
9424 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
9425 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
9426
9430 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
9431 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
9432 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
9433
9439 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
9440 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
9441 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
9442
9448 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
9449 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
9450 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
9451
9457 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
9458 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
9459 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
9460
9466 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
9467
9471 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
9472 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
9473
9477 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
9478 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
9479 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
9480
9483 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
9484 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
9485 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
9486 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
9487 #define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
9488 #define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
9489 #define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
9490 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)
9491 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)
9492
9496 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)
9497 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
9498 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
9499
9503 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
9504 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
9505 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
9506
9509 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
9510 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
9511 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
9512 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
9513 #define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
9514 #define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
9515 #define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
9516 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
9517 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
9518
9522 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
9523 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
9524 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
9525
9529 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
9530 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
9531 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
9532 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
9533 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
9534 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
9535 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
9536 #define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
9537 #define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
9538 #define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
9539 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
9540 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
9541
9545 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
9546 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
9547 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
9548
9554 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
9555 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
9556 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
9557
9563 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
9564 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
9565 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
9566
9572 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
9573 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
9574 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
9575
9581 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
9582
9586 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
9587 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
9588
9592 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
9593 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
9594 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
9595
9598 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
9599 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
9600 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
9601 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
9602 #define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
9603 #define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
9604 #define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
9605 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)
9606 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)
9607
9611 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)
9612 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
9613 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
9614
9618 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
9619 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
9620 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
9621
9624 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
9625 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
9626 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
9627 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
9628 #define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
9629 #define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
9630 #define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
9631 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
9632 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
9633
9637 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
9638 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
9639 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
9640
9644 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
9645 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
9646 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
9647 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
9648 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
9649 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
9650 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
9651 #define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
9652 #define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
9653 #define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
9654 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
9655 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
9656
9660 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
9661 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
9662 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
9663
9669 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
9670 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
9671 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
9672
9678 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
9679 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
9680 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
9681
9687 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
9688 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
9689 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
9690
9696 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
9697 /* end of group CCM_ANALOG_Register_Masks */
9703
9704
9705 /* CCM_ANALOG - Peripheral instance base addresses */
9707 #define CCM_ANALOG_BASE (0x400D8000u)
9708
9709 #define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
9710
9711 #define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
9712
9713 #define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
9714 /* end of group CCM_ANALOG_Peripheral_Access_Layer */
9718
9719
9720 /* ----------------------------------------------------------------------------
9721 -- CMP Peripheral Access Layer
9722 ---------------------------------------------------------------------------- */
9723
9730 typedef struct {
9731 __IO uint8_t CR0;
9732 __IO uint8_t CR1;
9733 __IO uint8_t FPR;
9734 __IO uint8_t SCR;
9735 __IO uint8_t DACCR;
9736 __IO uint8_t MUXCR;
9737 } CMP_Type;
9738
9739 /* ----------------------------------------------------------------------------
9740 -- CMP Register Masks
9741 ---------------------------------------------------------------------------- */
9742
9750 #define CMP_CR0_HYSTCTR_MASK (0x3U)
9751 #define CMP_CR0_HYSTCTR_SHIFT (0U)
9752
9758 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
9759 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
9760 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
9761
9771 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
9772
9776 #define CMP_CR1_EN_MASK (0x1U)
9777 #define CMP_CR1_EN_SHIFT (0U)
9778
9782 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
9783 #define CMP_CR1_OPE_MASK (0x2U)
9784 #define CMP_CR1_OPE_SHIFT (1U)
9785
9791 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
9792 #define CMP_CR1_COS_MASK (0x4U)
9793 #define CMP_CR1_COS_SHIFT (2U)
9794
9798 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
9799 #define CMP_CR1_INV_MASK (0x8U)
9800 #define CMP_CR1_INV_SHIFT (3U)
9801
9805 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
9806 #define CMP_CR1_PMODE_MASK (0x10U)
9807 #define CMP_CR1_PMODE_SHIFT (4U)
9808
9812 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
9813 #define CMP_CR1_WE_MASK (0x40U)
9814 #define CMP_CR1_WE_SHIFT (6U)
9815
9819 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
9820 #define CMP_CR1_SE_MASK (0x80U)
9821 #define CMP_CR1_SE_SHIFT (7U)
9822
9826 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
9827
9831 #define CMP_FPR_FILT_PER_MASK (0xFFU)
9832 #define CMP_FPR_FILT_PER_SHIFT (0U)
9833
9835 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
9836
9840 #define CMP_SCR_COUT_MASK (0x1U)
9841 #define CMP_SCR_COUT_SHIFT (0U)
9842
9844 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
9845 #define CMP_SCR_CFF_MASK (0x2U)
9846 #define CMP_SCR_CFF_SHIFT (1U)
9847
9851 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
9852 #define CMP_SCR_CFR_MASK (0x4U)
9853 #define CMP_SCR_CFR_SHIFT (2U)
9854
9858 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
9859 #define CMP_SCR_IEF_MASK (0x8U)
9860 #define CMP_SCR_IEF_SHIFT (3U)
9861
9865 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
9866 #define CMP_SCR_IER_MASK (0x10U)
9867 #define CMP_SCR_IER_SHIFT (4U)
9868
9872 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
9873 #define CMP_SCR_DMAEN_MASK (0x40U)
9874 #define CMP_SCR_DMAEN_SHIFT (6U)
9875
9879 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
9880
9884 #define CMP_DACCR_VOSEL_MASK (0x3FU)
9885 #define CMP_DACCR_VOSEL_SHIFT (0U)
9886
9888 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
9889 #define CMP_DACCR_VRSEL_MASK (0x40U)
9890 #define CMP_DACCR_VRSEL_SHIFT (6U)
9891
9895 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
9896 #define CMP_DACCR_DACEN_MASK (0x80U)
9897 #define CMP_DACCR_DACEN_SHIFT (7U)
9898
9902 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
9903
9907 #define CMP_MUXCR_MSEL_MASK (0x7U)
9908 #define CMP_MUXCR_MSEL_SHIFT (0U)
9909
9919 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
9920 #define CMP_MUXCR_PSEL_MASK (0x38U)
9921 #define CMP_MUXCR_PSEL_SHIFT (3U)
9922
9932 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
9933 /* end of group CMP_Register_Masks */
9939
9940
9941 /* CMP - Peripheral instance base addresses */
9943 #define CMP1_BASE (0x40094000u)
9944
9945 #define CMP1 ((CMP_Type *)CMP1_BASE)
9946
9947 #define CMP2_BASE (0x40094008u)
9948
9949 #define CMP2 ((CMP_Type *)CMP2_BASE)
9950
9951 #define CMP3_BASE (0x40094010u)
9952
9953 #define CMP3 ((CMP_Type *)CMP3_BASE)
9954
9955 #define CMP4_BASE (0x40094018u)
9956
9957 #define CMP4 ((CMP_Type *)CMP4_BASE)
9958
9959 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
9960
9961 #define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
9962
9963 #define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
9964 /* end of group CMP_Peripheral_Access_Layer */
9968
9969
9970 /* ----------------------------------------------------------------------------
9971 -- CSI Peripheral Access Layer
9972 ---------------------------------------------------------------------------- */
9973
9980 typedef struct {
9981 __IO uint32_t CSICR1;
9982 __IO uint32_t CSICR2;
9983 __IO uint32_t CSICR3;
9984 __I uint32_t CSISTATFIFO;
9985 __I uint32_t CSIRFIFO;
9986 __IO uint32_t CSIRXCNT;
9987 __IO uint32_t CSISR;
9988 uint8_t RESERVED_0[4];
9989 __IO uint32_t CSIDMASA_STATFIFO;
9990 __IO uint32_t CSIDMATS_STATFIFO;
9991 __IO uint32_t CSIDMASA_FB1;
9992 __IO uint32_t CSIDMASA_FB2;
9993 __IO uint32_t CSIFBUF_PARA;
9994 __IO uint32_t CSIIMAG_PARA;
9995 uint8_t RESERVED_1[16];
9996 __IO uint32_t CSICR18;
9997 __IO uint32_t CSICR19;
9998 } CSI_Type;
9999
10000 /* ----------------------------------------------------------------------------
10001 -- CSI Register Masks
10002 ---------------------------------------------------------------------------- */
10003
10011 #define CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
10012 #define CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
10013
10017 #define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
10018 #define CSI_CSICR1_REDGE_MASK (0x2U)
10019 #define CSI_CSICR1_REDGE_SHIFT (1U)
10020
10024 #define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
10025 #define CSI_CSICR1_INV_PCLK_MASK (0x4U)
10026 #define CSI_CSICR1_INV_PCLK_SHIFT (2U)
10027
10031 #define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
10032 #define CSI_CSICR1_INV_DATA_MASK (0x8U)
10033 #define CSI_CSICR1_INV_DATA_SHIFT (3U)
10034
10038 #define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
10039 #define CSI_CSICR1_GCLK_MODE_MASK (0x10U)
10040 #define CSI_CSICR1_GCLK_MODE_SHIFT (4U)
10041
10045 #define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
10046 #define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
10047 #define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
10048 #define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
10049 #define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
10050 #define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
10051 #define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
10052 #define CSI_CSICR1_PACK_DIR_MASK (0x80U)
10053 #define CSI_CSICR1_PACK_DIR_SHIFT (7U)
10054
10060 #define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
10061 #define CSI_CSICR1_FCC_MASK (0x100U)
10062 #define CSI_CSICR1_FCC_SHIFT (8U)
10063
10067 #define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
10068 #define CSI_CSICR1_CCIR_EN_MASK (0x400U)
10069 #define CSI_CSICR1_CCIR_EN_SHIFT (10U)
10070
10074 #define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
10075 #define CSI_CSICR1_HSYNC_POL_MASK (0x800U)
10076 #define CSI_CSICR1_HSYNC_POL_SHIFT (11U)
10077
10081 #define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
10082 #define CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
10083 #define CSI_CSICR1_SOF_INTEN_SHIFT (16U)
10084
10088 #define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
10089 #define CSI_CSICR1_SOF_POL_MASK (0x20000U)
10090 #define CSI_CSICR1_SOF_POL_SHIFT (17U)
10091
10095 #define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
10096 #define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
10097 #define CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
10098
10102 #define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
10103 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
10104 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
10105
10109 #define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
10110 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
10111 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
10112
10116 #define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
10117 #define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
10118 #define CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
10119
10123 #define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
10124 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
10125 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
10126
10130 #define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
10131 #define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
10132 #define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
10133
10137 #define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
10138 #define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
10139 #define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
10140
10144 #define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
10145 #define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
10146 #define CSI_CSICR1_COF_INT_EN_SHIFT (26U)
10147
10151 #define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
10152 #define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)
10153 #define CSI_CSICR1_CCIR_MODE_SHIFT (27U)
10154
10158 #define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
10159 #define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
10160 #define CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
10161
10165 #define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
10166 #define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
10167 #define CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
10168
10172 #define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
10173 #define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
10174 #define CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
10175
10179 #define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
10180 #define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
10181 #define CSI_CSICR1_SWAP16_EN_SHIFT (31U)
10182
10186 #define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
10187
10191 #define CSI_CSICR2_HSC_MASK (0xFFU)
10192 #define CSI_CSICR2_HSC_SHIFT (0U)
10193 #define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
10194 #define CSI_CSICR2_VSC_MASK (0xFF00U)
10195 #define CSI_CSICR2_VSC_SHIFT (8U)
10196 #define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
10197 #define CSI_CSICR2_LVRM_MASK (0x70000U)
10198 #define CSI_CSICR2_LVRM_SHIFT (16U)
10199
10208 #define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
10209 #define CSI_CSICR2_BTS_MASK (0x180000U)
10210 #define CSI_CSICR2_BTS_SHIFT (19U)
10211
10217 #define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
10218 #define CSI_CSICR2_SCE_MASK (0x800000U)
10219 #define CSI_CSICR2_SCE_SHIFT (23U)
10220
10224 #define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
10225 #define CSI_CSICR2_AFS_MASK (0x3000000U)
10226 #define CSI_CSICR2_AFS_SHIFT (24U)
10227
10232 #define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
10233 #define CSI_CSICR2_DRM_MASK (0x4000000U)
10234 #define CSI_CSICR2_DRM_SHIFT (26U)
10235
10239 #define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
10240 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
10241 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
10242
10247 #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
10248 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
10249 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
10250
10255 #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
10256
10260 #define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
10261 #define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
10262
10266 #define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
10267 #define CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
10268 #define CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
10269
10273 #define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
10274 #define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
10275 #define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
10276
10280 #define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
10281 #define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
10282 #define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
10283
10287 #define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
10288 #define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
10289 #define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
10290
10300 #define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
10301 #define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
10302 #define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
10303
10307 #define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
10308 #define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
10309 #define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
10310
10320 #define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
10321 #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
10322 #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
10323
10327 #define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
10328 #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
10329 #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
10330
10334 #define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
10335 #define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
10336 #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
10337
10341 #define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
10342 #define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
10343 #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
10344
10348 #define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
10349 #define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
10350 #define CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
10351
10355 #define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
10356 #define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
10357 #define CSI_CSICR3_FRMCNT_SHIFT (16U)
10358 #define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
10359
10363 #define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
10364 #define CSI_CSISTATFIFO_STAT_SHIFT (0U)
10365 #define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
10366
10370 #define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
10371 #define CSI_CSIRFIFO_IMAGE_SHIFT (0U)
10372 #define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
10373
10377 #define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
10378 #define CSI_CSIRXCNT_RXCNT_SHIFT (0U)
10379 #define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
10380
10384 #define CSI_CSISR_DRDY_MASK (0x1U)
10385 #define CSI_CSISR_DRDY_SHIFT (0U)
10386
10390 #define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
10391 #define CSI_CSISR_ECC_INT_MASK (0x2U)
10392 #define CSI_CSISR_ECC_INT_SHIFT (1U)
10393
10397 #define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
10398 #define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
10399 #define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
10400
10404 #define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
10405 #define CSI_CSISR_COF_INT_MASK (0x2000U)
10406 #define CSI_CSISR_COF_INT_SHIFT (13U)
10407
10411 #define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
10412 #define CSI_CSISR_F1_INT_MASK (0x4000U)
10413 #define CSI_CSISR_F1_INT_SHIFT (14U)
10414
10418 #define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
10419 #define CSI_CSISR_F2_INT_MASK (0x8000U)
10420 #define CSI_CSISR_F2_INT_SHIFT (15U)
10421
10425 #define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
10426 #define CSI_CSISR_SOF_INT_MASK (0x10000U)
10427 #define CSI_CSISR_SOF_INT_SHIFT (16U)
10428
10432 #define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
10433 #define CSI_CSISR_EOF_INT_MASK (0x20000U)
10434 #define CSI_CSISR_EOF_INT_SHIFT (17U)
10435
10439 #define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
10440 #define CSI_CSISR_RxFF_INT_MASK (0x40000U)
10441 #define CSI_CSISR_RxFF_INT_SHIFT (18U)
10442
10446 #define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
10447 #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
10448 #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
10449
10453 #define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
10454 #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
10455 #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
10456
10460 #define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
10461 #define CSI_CSISR_STATFF_INT_MASK (0x200000U)
10462 #define CSI_CSISR_STATFF_INT_SHIFT (21U)
10463
10467 #define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
10468 #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
10469 #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
10470
10474 #define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
10475 #define CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
10476 #define CSI_CSISR_RF_OR_INT_SHIFT (24U)
10477
10481 #define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
10482 #define CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
10483 #define CSI_CSISR_SF_OR_INT_SHIFT (25U)
10484
10488 #define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
10489 #define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
10490 #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
10491 #define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
10492 #define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
10493 #define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
10494 #define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
10495 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
10496 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
10497 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
10498
10502 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
10503 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
10504 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
10505
10509 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
10510 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
10511 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
10512
10516 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
10517 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
10518 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
10519
10523 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
10524 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
10525 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
10526
10530 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
10531 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
10532 #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
10533 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
10534 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
10535 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
10536
10540 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
10541 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
10542 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
10543 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
10544 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
10545 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
10546
10550 #define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
10551 #define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
10552
10556 #define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
10557 #define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
10558 #define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
10559 #define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
10560 #define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
10561 #define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
10562 #define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
10563 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
10564 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
10565
10569 #define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
10570 #define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
10571 #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
10572
10576 #define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
10577 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
10578 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
10579
10583 #define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
10584 #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
10585 #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
10586
10590 #define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
10591 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
10592 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
10593 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
10594 #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
10595 #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
10596
10600 #define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
10601 #define CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
10602 #define CSI_CSICR18_AHB_HPROT_SHIFT (12U)
10603 #define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
10604 #define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
10605 #define CSI_CSICR18_MASK_OPTION_SHIFT (18U)
10606
10612 #define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
10613 #define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
10614 #define CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
10615 #define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
10616
10620 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
10621 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
10622 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
10623 /* end of group CSI_Register_Masks */
10629
10630
10631 /* CSI - Peripheral instance base addresses */
10633 #define CSI_BASE (0x402BC000u)
10634
10635 #define CSI ((CSI_Type *)CSI_BASE)
10636
10637 #define CSI_BASE_ADDRS { CSI_BASE }
10638
10639 #define CSI_BASE_PTRS { CSI }
10640
10641 #define CSI_IRQS { CSI_IRQn }
10642 /* end of group CSI_Peripheral_Access_Layer */
10646
10647
10648 /* ----------------------------------------------------------------------------
10649 -- CSU Peripheral Access Layer
10650 ---------------------------------------------------------------------------- */
10651
10658 typedef struct {
10659 __IO uint32_t CSL[32];
10660 uint8_t RESERVED_0[384];
10661 __IO uint32_t HP0;
10662 uint8_t RESERVED_1[20];
10663 __IO uint32_t SA;
10664 uint8_t RESERVED_2[316];
10665 __IO uint32_t HPCONTROL0;
10666 } CSU_Type;
10667
10668 /* ----------------------------------------------------------------------------
10669 -- CSU Register Masks
10670 ---------------------------------------------------------------------------- */
10671
10679 #define CSU_CSL_SUR_S2_MASK (0x1U)
10680 #define CSU_CSL_SUR_S2_SHIFT (0U)
10681
10685 #define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
10686 #define CSU_CSL_SSR_S2_MASK (0x2U)
10687 #define CSU_CSL_SSR_S2_SHIFT (1U)
10688
10692 #define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
10693 #define CSU_CSL_NUR_S2_MASK (0x4U)
10694 #define CSU_CSL_NUR_S2_SHIFT (2U)
10695
10699 #define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
10700 #define CSU_CSL_NSR_S2_MASK (0x8U)
10701 #define CSU_CSL_NSR_S2_SHIFT (3U)
10702
10706 #define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
10707 #define CSU_CSL_SUW_S2_MASK (0x10U)
10708 #define CSU_CSL_SUW_S2_SHIFT (4U)
10709
10713 #define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
10714 #define CSU_CSL_SSW_S2_MASK (0x20U)
10715 #define CSU_CSL_SSW_S2_SHIFT (5U)
10716
10720 #define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
10721 #define CSU_CSL_NUW_S2_MASK (0x40U)
10722 #define CSU_CSL_NUW_S2_SHIFT (6U)
10723
10727 #define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
10728 #define CSU_CSL_NSW_S2_MASK (0x80U)
10729 #define CSU_CSL_NSW_S2_SHIFT (7U)
10730
10734 #define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
10735 #define CSU_CSL_LOCK_S2_MASK (0x100U)
10736 #define CSU_CSL_LOCK_S2_SHIFT (8U)
10737
10741 #define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
10742 #define CSU_CSL_SUR_S1_MASK (0x10000U)
10743 #define CSU_CSL_SUR_S1_SHIFT (16U)
10744
10748 #define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
10749 #define CSU_CSL_SSR_S1_MASK (0x20000U)
10750 #define CSU_CSL_SSR_S1_SHIFT (17U)
10751
10755 #define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
10756 #define CSU_CSL_NUR_S1_MASK (0x40000U)
10757 #define CSU_CSL_NUR_S1_SHIFT (18U)
10758
10762 #define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
10763 #define CSU_CSL_NSR_S1_MASK (0x80000U)
10764 #define CSU_CSL_NSR_S1_SHIFT (19U)
10765
10769 #define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
10770 #define CSU_CSL_SUW_S1_MASK (0x100000U)
10771 #define CSU_CSL_SUW_S1_SHIFT (20U)
10772
10776 #define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
10777 #define CSU_CSL_SSW_S1_MASK (0x200000U)
10778 #define CSU_CSL_SSW_S1_SHIFT (21U)
10779
10783 #define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
10784 #define CSU_CSL_NUW_S1_MASK (0x400000U)
10785 #define CSU_CSL_NUW_S1_SHIFT (22U)
10786
10790 #define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
10791 #define CSU_CSL_NSW_S1_MASK (0x800000U)
10792 #define CSU_CSL_NSW_S1_SHIFT (23U)
10793
10797 #define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
10798 #define CSU_CSL_LOCK_S1_MASK (0x1000000U)
10799 #define CSU_CSL_LOCK_S1_SHIFT (24U)
10800
10804 #define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
10805
10807 /* The count of CSU_CSL */
10808 #define CSU_CSL_COUNT (32U)
10809
10812 #define CSU_HP0_HP_DMA_MASK (0x4U)
10813 #define CSU_HP0_HP_DMA_SHIFT (2U)
10814
10818 #define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
10819 #define CSU_HP0_L_DMA_MASK (0x8U)
10820 #define CSU_HP0_L_DMA_SHIFT (3U)
10821
10825 #define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
10826 #define CSU_HP0_HP_LCDIF_MASK (0x10U)
10827 #define CSU_HP0_HP_LCDIF_SHIFT (4U)
10828
10832 #define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
10833 #define CSU_HP0_L_LCDIF_MASK (0x20U)
10834 #define CSU_HP0_L_LCDIF_SHIFT (5U)
10835
10839 #define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
10840 #define CSU_HP0_HP_CSI_MASK (0x40U)
10841 #define CSU_HP0_HP_CSI_SHIFT (6U)
10842
10846 #define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
10847 #define CSU_HP0_L_CSI_MASK (0x80U)
10848 #define CSU_HP0_L_CSI_SHIFT (7U)
10849
10853 #define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
10854 #define CSU_HP0_HP_PXP_MASK (0x100U)
10855 #define CSU_HP0_HP_PXP_SHIFT (8U)
10856
10860 #define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
10861 #define CSU_HP0_L_PXP_MASK (0x200U)
10862 #define CSU_HP0_L_PXP_SHIFT (9U)
10863
10867 #define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
10868 #define CSU_HP0_HP_DCP_MASK (0x400U)
10869 #define CSU_HP0_HP_DCP_SHIFT (10U)
10870
10874 #define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
10875 #define CSU_HP0_L_DCP_MASK (0x800U)
10876 #define CSU_HP0_L_DCP_SHIFT (11U)
10877
10881 #define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
10882 #define CSU_HP0_HP_ENET_MASK (0x4000U)
10883 #define CSU_HP0_HP_ENET_SHIFT (14U)
10884
10888 #define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
10889 #define CSU_HP0_L_ENET_MASK (0x8000U)
10890 #define CSU_HP0_L_ENET_SHIFT (15U)
10891
10895 #define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
10896 #define CSU_HP0_HP_USDHC1_MASK (0x10000U)
10897 #define CSU_HP0_HP_USDHC1_SHIFT (16U)
10898
10902 #define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
10903 #define CSU_HP0_L_USDHC1_MASK (0x20000U)
10904 #define CSU_HP0_L_USDHC1_SHIFT (17U)
10905
10909 #define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
10910 #define CSU_HP0_HP_USDHC2_MASK (0x40000U)
10911 #define CSU_HP0_HP_USDHC2_SHIFT (18U)
10912
10916 #define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
10917 #define CSU_HP0_L_USDHC2_MASK (0x80000U)
10918 #define CSU_HP0_L_USDHC2_SHIFT (19U)
10919
10923 #define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
10924 #define CSU_HP0_HP_TPSMP_MASK (0x100000U)
10925 #define CSU_HP0_HP_TPSMP_SHIFT (20U)
10926
10930 #define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
10931 #define CSU_HP0_L_TPSMP_MASK (0x200000U)
10932 #define CSU_HP0_L_TPSMP_SHIFT (21U)
10933
10937 #define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
10938 #define CSU_HP0_HP_USB_MASK (0x400000U)
10939 #define CSU_HP0_HP_USB_SHIFT (22U)
10940
10944 #define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
10945 #define CSU_HP0_L_USB_MASK (0x800000U)
10946 #define CSU_HP0_L_USB_SHIFT (23U)
10947
10951 #define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
10952
10956 #define CSU_SA_NSA_DMA_MASK (0x4U)
10957 #define CSU_SA_NSA_DMA_SHIFT (2U)
10958
10962 #define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
10963 #define CSU_SA_L_DMA_MASK (0x8U)
10964 #define CSU_SA_L_DMA_SHIFT (3U)
10965
10969 #define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
10970 #define CSU_SA_NSA_LCDIF_MASK (0x10U)
10971 #define CSU_SA_NSA_LCDIF_SHIFT (4U)
10972
10976 #define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
10977 #define CSU_SA_L_LCDIF_MASK (0x20U)
10978 #define CSU_SA_L_LCDIF_SHIFT (5U)
10979
10983 #define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
10984 #define CSU_SA_NSA_CSI_MASK (0x40U)
10985 #define CSU_SA_NSA_CSI_SHIFT (6U)
10986
10990 #define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
10991 #define CSU_SA_L_CSI_MASK (0x80U)
10992 #define CSU_SA_L_CSI_SHIFT (7U)
10993
10997 #define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
10998 #define CSU_SA_NSA_PXP_MASK (0x100U)
10999 #define CSU_SA_NSA_PXP_SHIFT (8U)
11000
11004 #define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
11005 #define CSU_SA_L_PXP_MASK (0x200U)
11006 #define CSU_SA_L_PXP_SHIFT (9U)
11007
11011 #define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
11012 #define CSU_SA_NSA_DCP_MASK (0x400U)
11013 #define CSU_SA_NSA_DCP_SHIFT (10U)
11014
11018 #define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
11019 #define CSU_SA_L_DCP_MASK (0x800U)
11020 #define CSU_SA_L_DCP_SHIFT (11U)
11021
11025 #define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
11026 #define CSU_SA_NSA_ENET_MASK (0x4000U)
11027 #define CSU_SA_NSA_ENET_SHIFT (14U)
11028
11032 #define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
11033 #define CSU_SA_L_ENET_MASK (0x8000U)
11034 #define CSU_SA_L_ENET_SHIFT (15U)
11035
11039 #define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
11040 #define CSU_SA_NSA_USDHC1_MASK (0x10000U)
11041 #define CSU_SA_NSA_USDHC1_SHIFT (16U)
11042
11046 #define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
11047 #define CSU_SA_L_USDHC1_MASK (0x20000U)
11048 #define CSU_SA_L_USDHC1_SHIFT (17U)
11049
11053 #define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
11054 #define CSU_SA_NSA_USDHC2_MASK (0x40000U)
11055 #define CSU_SA_NSA_USDHC2_SHIFT (18U)
11056
11060 #define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
11061 #define CSU_SA_L_USDHC2_MASK (0x80000U)
11062 #define CSU_SA_L_USDHC2_SHIFT (19U)
11063
11067 #define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
11068 #define CSU_SA_NSA_TPSMP_MASK (0x100000U)
11069 #define CSU_SA_NSA_TPSMP_SHIFT (20U)
11070
11074 #define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
11075 #define CSU_SA_L_TPSMP_MASK (0x200000U)
11076 #define CSU_SA_L_TPSMP_SHIFT (21U)
11077
11081 #define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
11082 #define CSU_SA_NSA_USB_MASK (0x400000U)
11083 #define CSU_SA_NSA_USB_SHIFT (22U)
11084
11088 #define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
11089 #define CSU_SA_L_USB_MASK (0x800000U)
11090 #define CSU_SA_L_USB_SHIFT (23U)
11091
11095 #define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
11096
11100 #define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
11101 #define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
11102
11106 #define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
11107 #define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
11108 #define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
11109
11113 #define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
11114 #define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
11115 #define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
11116
11120 #define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
11121 #define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
11122 #define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
11123
11127 #define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
11128 #define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
11129 #define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
11130
11134 #define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
11135 #define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
11136 #define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
11137
11141 #define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
11142 #define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
11143 #define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
11144
11148 #define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
11149 #define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
11150 #define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
11151
11155 #define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
11156 #define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
11157 #define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
11158
11162 #define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
11163 #define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
11164 #define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
11165
11169 #define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
11170 #define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
11171 #define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
11172
11176 #define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
11177 #define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
11178 #define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
11179
11183 #define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
11184 #define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
11185 #define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
11186
11190 #define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
11191 #define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
11192 #define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
11193
11197 #define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
11198 #define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
11199 #define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
11200
11204 #define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
11205 #define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
11206 #define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
11207
11211 #define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
11212 #define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
11213 #define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
11214
11218 #define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
11219 #define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
11220 #define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
11221
11225 #define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
11226 #define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
11227 #define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
11228
11232 #define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
11233 #define CSU_HPCONTROL0_L_USB_MASK (0x800000U)
11234 #define CSU_HPCONTROL0_L_USB_SHIFT (23U)
11235
11239 #define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
11240 /* end of group CSU_Register_Masks */
11246
11247
11248 /* CSU - Peripheral instance base addresses */
11250 #define CSU_BASE (0x400DC000u)
11251
11252 #define CSU ((CSU_Type *)CSU_BASE)
11253
11254 #define CSU_BASE_ADDRS { CSU_BASE }
11255
11256 #define CSU_BASE_PTRS { CSU }
11257 /* end of group CSU_Peripheral_Access_Layer */
11261
11262
11263 /* ----------------------------------------------------------------------------
11264 -- DCDC Peripheral Access Layer
11265 ---------------------------------------------------------------------------- */
11266
11273 typedef struct {
11274 __IO uint32_t REG0;
11275 __IO uint32_t REG1;
11276 __IO uint32_t REG2;
11277 __IO uint32_t REG3;
11278 } DCDC_Type;
11279
11280 /* ----------------------------------------------------------------------------
11281 -- DCDC Register Masks
11282 ---------------------------------------------------------------------------- */
11283
11291 #define DCDC_REG0_PWD_ZCD_MASK (0x1U)
11292 #define DCDC_REG0_PWD_ZCD_SHIFT (0U)
11293 #define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
11294 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
11295 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
11296 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
11297 #define DCDC_REG0_SEL_CLK_MASK (0x4U)
11298 #define DCDC_REG0_SEL_CLK_SHIFT (2U)
11299 #define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
11300 #define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
11301 #define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
11302 #define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
11303 #define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
11304 #define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
11305 #define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
11306 #define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
11307 #define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
11308 #define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
11309 #define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
11310 #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
11311 #define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
11312 #define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
11313 #define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
11314 #define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
11315 #define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
11316 #define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
11317 #define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
11318 #define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)
11319 #define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)
11320 #define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)
11321 #define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
11322 #define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
11323 #define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
11324 #define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
11325 #define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
11326 #define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
11327 #define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
11328 #define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
11329 #define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
11330 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
11331 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
11332 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
11333 #define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
11334 #define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
11335 #define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
11336 #define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
11337 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
11338 #define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
11339 #define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
11340 #define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
11341 #define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
11342 #define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
11343 #define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
11344 #define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
11345 #define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
11346 #define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
11347 #define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
11348 #define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
11349 #define DCDC_REG0_STS_DC_OK_SHIFT (31U)
11350 #define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
11351
11355 #define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
11356 #define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
11357 #define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
11358 #define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
11359 #define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
11360 #define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
11361 #define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
11362 #define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
11363 #define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
11364 #define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
11365 #define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
11366 #define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
11367 #define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
11368 #define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
11369 #define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
11370 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
11371 #define DCDC_REG1_VBG_TRIM_SHIFT (24U)
11372 #define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
11373
11377 #define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
11378 #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
11379 #define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
11380 #define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
11381 #define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
11382 #define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
11383 #define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
11384 #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
11385 #define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
11386 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
11387 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
11388 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
11389 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
11390 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
11391 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
11392 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
11393 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
11394 #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
11395 #define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
11396 #define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
11397 #define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
11398 #define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
11399 #define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
11400 #define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
11401
11405 #define DCDC_REG3_TRG_MASK (0x1FU)
11406 #define DCDC_REG3_TRG_SHIFT (0U)
11407 #define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
11408 #define DCDC_REG3_TARGET_LP_MASK (0x700U)
11409 #define DCDC_REG3_TARGET_LP_SHIFT (8U)
11410 #define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
11411 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
11412 #define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
11413 #define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
11414 #define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
11415 #define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
11416 #define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
11417 #define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)
11418 #define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)
11419 #define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)
11420 #define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
11421 #define DCDC_REG3_DISABLE_STEP_SHIFT (30U)
11422 #define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)
11423 /* end of group DCDC_Register_Masks */
11429
11430
11431 /* DCDC - Peripheral instance base addresses */
11433 #define DCDC_BASE (0x40080000u)
11434
11435 #define DCDC ((DCDC_Type *)DCDC_BASE)
11436
11437 #define DCDC_BASE_ADDRS { DCDC_BASE }
11438
11439 #define DCDC_BASE_PTRS { DCDC }
11440
11441 #define DCDC_IRQS { DCDC_IRQn }
11442 /* end of group DCDC_Peripheral_Access_Layer */
11446
11447
11448 /* ----------------------------------------------------------------------------
11449 -- DCP Peripheral Access Layer
11450 ---------------------------------------------------------------------------- */
11451
11458 typedef struct {
11459 __IO uint32_t CTRL;
11460 __IO uint32_t CTRL_SET;
11461 __IO uint32_t CTRL_CLR;
11462 __IO uint32_t CTRL_TOG;
11463 __IO uint32_t STAT;
11464 __IO uint32_t STAT_SET;
11465 __IO uint32_t STAT_CLR;
11466 __IO uint32_t STAT_TOG;
11467 __IO uint32_t CHANNELCTRL;
11468 __IO uint32_t CHANNELCTRL_SET;
11469 __IO uint32_t CHANNELCTRL_CLR;
11470 __IO uint32_t CHANNELCTRL_TOG;
11471 __IO uint32_t CAPABILITY0;
11472 uint8_t RESERVED_0[12];
11473 __I uint32_t CAPABILITY1;
11474 uint8_t RESERVED_1[12];
11475 __IO uint32_t CONTEXT;
11476 uint8_t RESERVED_2[12];
11477 __IO uint32_t KEY;
11478 uint8_t RESERVED_3[12];
11479 __IO uint32_t KEYDATA;
11480 uint8_t RESERVED_4[12];
11481 __I uint32_t PACKET0;
11482 uint8_t RESERVED_5[12];
11483 __I uint32_t PACKET1;
11484 uint8_t RESERVED_6[12];
11485 __I uint32_t PACKET2;
11486 uint8_t RESERVED_7[12];
11487 __I uint32_t PACKET3;
11488 uint8_t RESERVED_8[12];
11489 __I uint32_t PACKET4;
11490 uint8_t RESERVED_9[12];
11491 __I uint32_t PACKET5;
11492 uint8_t RESERVED_10[12];
11493 __I uint32_t PACKET6;
11494 uint8_t RESERVED_11[28];
11495 __IO uint32_t CH0CMDPTR;
11496 uint8_t RESERVED_12[12];
11497 __IO uint32_t CH0SEMA;
11498 uint8_t RESERVED_13[12];
11499 __IO uint32_t CH0STAT;
11500 __IO uint32_t CH0STAT_SET;
11501 __IO uint32_t CH0STAT_CLR;
11502 __IO uint32_t CH0STAT_TOG;
11503 __IO uint32_t CH0OPTS;
11504 __IO uint32_t CH0OPTS_SET;
11505 __IO uint32_t CH0OPTS_CLR;
11506 __IO uint32_t CH0OPTS_TOG;
11507 __IO uint32_t CH1CMDPTR;
11508 uint8_t RESERVED_14[12];
11509 __IO uint32_t CH1SEMA;
11510 uint8_t RESERVED_15[12];
11511 __IO uint32_t CH1STAT;
11512 __IO uint32_t CH1STAT_SET;
11513 __IO uint32_t CH1STAT_CLR;
11514 __IO uint32_t CH1STAT_TOG;
11515 __IO uint32_t CH1OPTS;
11516 __IO uint32_t CH1OPTS_SET;
11517 __IO uint32_t CH1OPTS_CLR;
11518 __IO uint32_t CH1OPTS_TOG;
11519 __IO uint32_t CH2CMDPTR;
11520 uint8_t RESERVED_16[12];
11521 __IO uint32_t CH2SEMA;
11522 uint8_t RESERVED_17[12];
11523 __IO uint32_t CH2STAT;
11524 __IO uint32_t CH2STAT_SET;
11525 __IO uint32_t CH2STAT_CLR;
11526 __IO uint32_t CH2STAT_TOG;
11527 __IO uint32_t CH2OPTS;
11528 __IO uint32_t CH2OPTS_SET;
11529 __IO uint32_t CH2OPTS_CLR;
11530 __IO uint32_t CH2OPTS_TOG;
11531 __IO uint32_t CH3CMDPTR;
11532 uint8_t RESERVED_18[12];
11533 __IO uint32_t CH3SEMA;
11534 uint8_t RESERVED_19[12];
11535 __IO uint32_t CH3STAT;
11536 __IO uint32_t CH3STAT_SET;
11537 __IO uint32_t CH3STAT_CLR;
11538 __IO uint32_t CH3STAT_TOG;
11539 __IO uint32_t CH3OPTS;
11540 __IO uint32_t CH3OPTS_SET;
11541 __IO uint32_t CH3OPTS_CLR;
11542 __IO uint32_t CH3OPTS_TOG;
11543 uint8_t RESERVED_20[512];
11544 __IO uint32_t DBGSELECT;
11545 uint8_t RESERVED_21[12];
11546 __I uint32_t DBGDATA;
11547 uint8_t RESERVED_22[12];
11548 __IO uint32_t PAGETABLE;
11549 uint8_t RESERVED_23[12];
11550 __I uint32_t VERSION;
11551 } DCP_Type;
11552
11553 /* ----------------------------------------------------------------------------
11554 -- DCP Register Masks
11555 ---------------------------------------------------------------------------- */
11556
11564 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
11565 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
11566
11572 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
11573 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
11574 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
11575 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
11576 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
11577 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
11578 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
11579 #define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
11580 #define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
11581 #define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
11582 #define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
11583 #define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
11584 #define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
11585 #define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
11586 #define DCP_CTRL_PRESENT_SHA_SHIFT (28U)
11587
11591 #define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
11592 #define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
11593 #define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
11594
11598 #define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
11599 #define DCP_CTRL_CLKGATE_MASK (0x40000000U)
11600 #define DCP_CTRL_CLKGATE_SHIFT (30U)
11601 #define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
11602 #define DCP_CTRL_SFTRST_MASK (0x80000000U)
11603 #define DCP_CTRL_SFTRST_SHIFT (31U)
11604 #define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
11605
11609 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
11610 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
11611
11617 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
11618 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
11619 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
11620 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
11621 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
11622 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
11623 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
11624 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
11625 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
11626 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
11627 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
11628 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
11629 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
11630 #define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U)
11631 #define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U)
11632
11636 #define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
11637 #define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U)
11638 #define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U)
11639
11643 #define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
11644 #define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U)
11645 #define DCP_CTRL_SET_CLKGATE_SHIFT (30U)
11646 #define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
11647 #define DCP_CTRL_SET_SFTRST_MASK (0x80000000U)
11648 #define DCP_CTRL_SET_SFTRST_SHIFT (31U)
11649 #define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
11650
11654 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
11655 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
11656
11662 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
11663 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
11664 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
11665 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
11666 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
11667 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
11668 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
11669 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
11670 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
11671 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
11672 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
11673 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
11674 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
11675 #define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U)
11676 #define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U)
11677
11681 #define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
11682 #define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U)
11683 #define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U)
11684
11688 #define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
11689 #define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
11690 #define DCP_CTRL_CLR_CLKGATE_SHIFT (30U)
11691 #define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
11692 #define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U)
11693 #define DCP_CTRL_CLR_SFTRST_SHIFT (31U)
11694 #define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
11695
11699 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
11700 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
11701
11707 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
11708 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
11709 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
11710 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
11711 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
11712 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
11713 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
11714 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
11715 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
11716 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
11717 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
11718 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
11719 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
11720 #define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U)
11721 #define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U)
11722
11726 #define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
11727 #define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U)
11728 #define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U)
11729
11733 #define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
11734 #define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
11735 #define DCP_CTRL_TOG_CLKGATE_SHIFT (30U)
11736 #define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
11737 #define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U)
11738 #define DCP_CTRL_TOG_SFTRST_SHIFT (31U)
11739 #define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
11740
11744 #define DCP_STAT_IRQ_MASK (0xFU)
11745 #define DCP_STAT_IRQ_SHIFT (0U)
11746 #define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
11747 #define DCP_STAT_RSVD_IRQ_MASK (0x100U)
11748 #define DCP_STAT_RSVD_IRQ_SHIFT (8U)
11749 #define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
11750 #define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
11751 #define DCP_STAT_READY_CHANNELS_SHIFT (16U)
11752
11758 #define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
11759 #define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
11760 #define DCP_STAT_CUR_CHANNEL_SHIFT (24U)
11761
11768 #define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
11769 #define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
11770 #define DCP_STAT_OTP_KEY_READY_SHIFT (28U)
11771 #define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
11772
11776 #define DCP_STAT_SET_IRQ_MASK (0xFU)
11777 #define DCP_STAT_SET_IRQ_SHIFT (0U)
11778 #define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
11779 #define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U)
11780 #define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U)
11781 #define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
11782 #define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U)
11783 #define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U)
11784
11790 #define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
11791 #define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U)
11792 #define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U)
11793
11800 #define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
11801 #define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U)
11802 #define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U)
11803 #define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
11804
11808 #define DCP_STAT_CLR_IRQ_MASK (0xFU)
11809 #define DCP_STAT_CLR_IRQ_SHIFT (0U)
11810 #define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
11811 #define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U)
11812 #define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U)
11813 #define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
11814 #define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U)
11815 #define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U)
11816
11822 #define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
11823 #define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U)
11824 #define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U)
11825
11832 #define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
11833 #define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U)
11834 #define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U)
11835 #define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
11836
11840 #define DCP_STAT_TOG_IRQ_MASK (0xFU)
11841 #define DCP_STAT_TOG_IRQ_SHIFT (0U)
11842 #define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
11843 #define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U)
11844 #define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U)
11845 #define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
11846 #define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U)
11847 #define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U)
11848
11854 #define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
11855 #define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U)
11856 #define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U)
11857
11864 #define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
11865 #define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U)
11866 #define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U)
11867 #define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
11868
11872 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
11873 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
11874
11880 #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
11881 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
11882 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
11883
11889 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
11890 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
11891 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
11892 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
11893 #define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
11894 #define DCP_CHANNELCTRL_RSVD_SHIFT (17U)
11895 #define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
11896
11900 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU)
11901 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
11902
11908 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
11909 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
11910 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
11911
11917 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
11918 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U)
11919 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
11920 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
11921 #define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U)
11922 #define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U)
11923 #define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
11924
11928 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU)
11929 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
11930
11936 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
11937 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
11938 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
11939
11945 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
11946 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U)
11947 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
11948 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
11949 #define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U)
11950 #define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U)
11951 #define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
11952
11956 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU)
11957 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
11958
11964 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
11965 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
11966 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
11967
11973 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
11974 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U)
11975 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
11976 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
11977 #define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U)
11978 #define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U)
11979 #define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
11980
11984 #define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
11985 #define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
11986 #define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
11987 #define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
11988 #define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
11989 #define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
11990 #define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
11991 #define DCP_CAPABILITY0_RSVD_SHIFT (12U)
11992 #define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
11993 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
11994 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
11995 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
11996 #define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
11997 #define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
11998 #define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
11999
12003 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
12004 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
12005
12008 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
12009 #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
12010 #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
12011
12016 #define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
12017
12021 #define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
12022 #define DCP_CONTEXT_ADDR_SHIFT (0U)
12023 #define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
12024
12028 #define DCP_KEY_SUBWORD_MASK (0x3U)
12029 #define DCP_KEY_SUBWORD_SHIFT (0U)
12030 #define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
12031 #define DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
12032 #define DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
12033 #define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
12034 #define DCP_KEY_INDEX_MASK (0x30U)
12035 #define DCP_KEY_INDEX_SHIFT (4U)
12036 #define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
12037 #define DCP_KEY_RSVD_INDEX_MASK (0xC0U)
12038 #define DCP_KEY_RSVD_INDEX_SHIFT (6U)
12039 #define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
12040 #define DCP_KEY_RSVD_MASK (0xFFFFFF00U)
12041 #define DCP_KEY_RSVD_SHIFT (8U)
12042 #define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
12043
12047 #define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
12048 #define DCP_KEYDATA_DATA_SHIFT (0U)
12049 #define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
12050
12054 #define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
12055 #define DCP_PACKET0_ADDR_SHIFT (0U)
12056 #define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
12057
12061 #define DCP_PACKET1_INTERRUPT_MASK (0x1U)
12062 #define DCP_PACKET1_INTERRUPT_SHIFT (0U)
12063 #define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
12064 #define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
12065 #define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
12066 #define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
12067 #define DCP_PACKET1_CHAIN_MASK (0x4U)
12068 #define DCP_PACKET1_CHAIN_SHIFT (2U)
12069 #define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
12070 #define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
12071 #define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
12072 #define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
12073 #define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
12074 #define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
12075 #define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
12076 #define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
12077 #define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
12078 #define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
12079 #define DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
12080 #define DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
12081 #define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
12082 #define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
12083 #define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
12084 #define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
12085 #define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
12086 #define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
12087
12091 #define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
12092 #define DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
12093 #define DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
12094 #define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
12095 #define DCP_PACKET1_OTP_KEY_MASK (0x400U)
12096 #define DCP_PACKET1_OTP_KEY_SHIFT (10U)
12097 #define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
12098 #define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
12099 #define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
12100 #define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
12101 #define DCP_PACKET1_HASH_INIT_MASK (0x1000U)
12102 #define DCP_PACKET1_HASH_INIT_SHIFT (12U)
12103 #define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
12104 #define DCP_PACKET1_HASH_TERM_MASK (0x2000U)
12105 #define DCP_PACKET1_HASH_TERM_SHIFT (13U)
12106 #define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
12107 #define DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
12108 #define DCP_PACKET1_CHECK_HASH_SHIFT (14U)
12109 #define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
12110 #define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
12111 #define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
12112
12116 #define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
12117 #define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
12118 #define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
12119 #define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
12120 #define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
12121 #define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
12122 #define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
12123 #define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
12124 #define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
12125 #define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
12126 #define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
12127 #define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
12128 #define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
12129 #define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
12130 #define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
12131 #define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
12132 #define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
12133 #define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
12134 #define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
12135 #define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
12136 #define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
12137 #define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
12138 #define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
12139 #define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
12140 #define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
12141 #define DCP_PACKET1_TAG_MASK (0xFF000000U)
12142 #define DCP_PACKET1_TAG_SHIFT (24U)
12143 #define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
12144
12148 #define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
12149 #define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
12150
12153 #define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
12154 #define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
12155 #define DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
12156
12160 #define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
12161 #define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
12162 #define DCP_PACKET2_KEY_SELECT_SHIFT (8U)
12163
12171 #define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
12172 #define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
12173 #define DCP_PACKET2_HASH_SELECT_SHIFT (16U)
12174
12179 #define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
12180 #define DCP_PACKET2_RSVD_MASK (0xF00000U)
12181 #define DCP_PACKET2_RSVD_SHIFT (20U)
12182 #define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
12183 #define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
12184 #define DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
12185 #define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
12186
12190 #define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
12191 #define DCP_PACKET3_ADDR_SHIFT (0U)
12192 #define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
12193
12197 #define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
12198 #define DCP_PACKET4_ADDR_SHIFT (0U)
12199 #define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
12200
12204 #define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
12205 #define DCP_PACKET5_COUNT_SHIFT (0U)
12206 #define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
12207
12211 #define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
12212 #define DCP_PACKET6_ADDR_SHIFT (0U)
12213 #define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
12214
12218 #define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
12219 #define DCP_CH0CMDPTR_ADDR_SHIFT (0U)
12220 #define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
12221
12225 #define DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
12226 #define DCP_CH0SEMA_INCREMENT_SHIFT (0U)
12227 #define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
12228 #define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
12229 #define DCP_CH0SEMA_VALUE_SHIFT (16U)
12230 #define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
12231
12235 #define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
12236 #define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
12237 #define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
12238 #define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
12239 #define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
12240 #define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
12241 #define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
12242 #define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
12243 #define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
12244 #define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
12245 #define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
12246 #define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
12247 #define DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
12248 #define DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
12249 #define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
12250 #define DCP_CH0STAT_ERROR_DST_MASK (0x20U)
12251 #define DCP_CH0STAT_ERROR_DST_SHIFT (5U)
12252 #define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
12253 #define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
12254 #define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
12255 #define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
12256 #define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
12257 #define DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
12258
12265 #define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
12266 #define DCP_CH0STAT_TAG_MASK (0xFF000000U)
12267 #define DCP_CH0STAT_TAG_SHIFT (24U)
12268 #define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
12269
12273 #define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U)
12274 #define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U)
12275 #define DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
12276 #define DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U)
12277 #define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U)
12278 #define DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
12279 #define DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U)
12280 #define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U)
12281 #define DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
12282 #define DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U)
12283 #define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U)
12284 #define DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
12285 #define DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U)
12286 #define DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U)
12287 #define DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
12288 #define DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U)
12289 #define DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U)
12290 #define DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
12291 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
12292 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
12293 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
12294 #define DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U)
12295 #define DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U)
12296
12303 #define DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
12304 #define DCP_CH0STAT_SET_TAG_MASK (0xFF000000U)
12305 #define DCP_CH0STAT_SET_TAG_SHIFT (24U)
12306 #define DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
12307
12311 #define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
12312 #define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
12313 #define DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
12314 #define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U)
12315 #define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U)
12316 #define DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
12317 #define DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U)
12318 #define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U)
12319 #define DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
12320 #define DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U)
12321 #define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U)
12322 #define DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
12323 #define DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U)
12324 #define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U)
12325 #define DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
12326 #define DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U)
12327 #define DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U)
12328 #define DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
12329 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
12330 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
12331 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
12332 #define DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
12333 #define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U)
12334
12341 #define DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
12342 #define DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U)
12343 #define DCP_CH0STAT_CLR_TAG_SHIFT (24U)
12344 #define DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
12345
12349 #define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
12350 #define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
12351 #define DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
12352 #define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U)
12353 #define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U)
12354 #define DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
12355 #define DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U)
12356 #define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U)
12357 #define DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
12358 #define DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U)
12359 #define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U)
12360 #define DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
12361 #define DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U)
12362 #define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U)
12363 #define DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
12364 #define DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U)
12365 #define DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U)
12366 #define DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
12367 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
12368 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
12369 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
12370 #define DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
12371 #define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U)
12372
12379 #define DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
12380 #define DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U)
12381 #define DCP_CH0STAT_TOG_TAG_SHIFT (24U)
12382 #define DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
12383
12387 #define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
12388 #define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
12389 #define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
12390 #define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
12391 #define DCP_CH0OPTS_RSVD_SHIFT (16U)
12392 #define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
12393
12397 #define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
12398 #define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
12399 #define DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
12400 #define DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U)
12401 #define DCP_CH0OPTS_SET_RSVD_SHIFT (16U)
12402 #define DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
12403
12407 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
12408 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
12409 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
12410 #define DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U)
12411 #define DCP_CH0OPTS_CLR_RSVD_SHIFT (16U)
12412 #define DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
12413
12417 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
12418 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
12419 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
12420 #define DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U)
12421 #define DCP_CH0OPTS_TOG_RSVD_SHIFT (16U)
12422 #define DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
12423
12427 #define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
12428 #define DCP_CH1CMDPTR_ADDR_SHIFT (0U)
12429 #define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
12430
12434 #define DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
12435 #define DCP_CH1SEMA_INCREMENT_SHIFT (0U)
12436 #define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
12437 #define DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
12438 #define DCP_CH1SEMA_VALUE_SHIFT (16U)
12439 #define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
12440
12444 #define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
12445 #define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
12446 #define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
12447 #define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
12448 #define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
12449 #define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
12450 #define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
12451 #define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
12452 #define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
12453 #define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
12454 #define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
12455 #define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
12456 #define DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
12457 #define DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
12458 #define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
12459 #define DCP_CH1STAT_ERROR_DST_MASK (0x20U)
12460 #define DCP_CH1STAT_ERROR_DST_SHIFT (5U)
12461 #define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
12462 #define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
12463 #define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
12464 #define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
12465 #define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
12466 #define DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
12467
12474 #define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
12475 #define DCP_CH1STAT_TAG_MASK (0xFF000000U)
12476 #define DCP_CH1STAT_TAG_SHIFT (24U)
12477 #define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
12478
12482 #define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U)
12483 #define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U)
12484 #define DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
12485 #define DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U)
12486 #define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U)
12487 #define DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
12488 #define DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U)
12489 #define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U)
12490 #define DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
12491 #define DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U)
12492 #define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U)
12493 #define DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
12494 #define DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U)
12495 #define DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U)
12496 #define DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
12497 #define DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U)
12498 #define DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U)
12499 #define DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
12500 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
12501 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
12502 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
12503 #define DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U)
12504 #define DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U)
12505
12512 #define DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
12513 #define DCP_CH1STAT_SET_TAG_MASK (0xFF000000U)
12514 #define DCP_CH1STAT_SET_TAG_SHIFT (24U)
12515 #define DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
12516
12520 #define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
12521 #define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
12522 #define DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
12523 #define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U)
12524 #define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U)
12525 #define DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
12526 #define DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U)
12527 #define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U)
12528 #define DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
12529 #define DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U)
12530 #define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U)
12531 #define DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
12532 #define DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U)
12533 #define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U)
12534 #define DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
12535 #define DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U)
12536 #define DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U)
12537 #define DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
12538 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
12539 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
12540 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
12541 #define DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
12542 #define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U)
12543
12550 #define DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
12551 #define DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U)
12552 #define DCP_CH1STAT_CLR_TAG_SHIFT (24U)
12553 #define DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
12554
12558 #define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
12559 #define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
12560 #define DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
12561 #define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U)
12562 #define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U)
12563 #define DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
12564 #define DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U)
12565 #define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U)
12566 #define DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
12567 #define DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U)
12568 #define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U)
12569 #define DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
12570 #define DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U)
12571 #define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U)
12572 #define DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
12573 #define DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U)
12574 #define DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U)
12575 #define DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
12576 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
12577 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
12578 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
12579 #define DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
12580 #define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U)
12581
12588 #define DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
12589 #define DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U)
12590 #define DCP_CH1STAT_TOG_TAG_SHIFT (24U)
12591 #define DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
12592
12596 #define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
12597 #define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
12598 #define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
12599 #define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
12600 #define DCP_CH1OPTS_RSVD_SHIFT (16U)
12601 #define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
12602
12606 #define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
12607 #define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
12608 #define DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
12609 #define DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U)
12610 #define DCP_CH1OPTS_SET_RSVD_SHIFT (16U)
12611 #define DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
12612
12616 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
12617 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
12618 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
12619 #define DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U)
12620 #define DCP_CH1OPTS_CLR_RSVD_SHIFT (16U)
12621 #define DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
12622
12626 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
12627 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
12628 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
12629 #define DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U)
12630 #define DCP_CH1OPTS_TOG_RSVD_SHIFT (16U)
12631 #define DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
12632
12636 #define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
12637 #define DCP_CH2CMDPTR_ADDR_SHIFT (0U)
12638 #define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
12639
12643 #define DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
12644 #define DCP_CH2SEMA_INCREMENT_SHIFT (0U)
12645 #define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
12646 #define DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
12647 #define DCP_CH2SEMA_VALUE_SHIFT (16U)
12648 #define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
12649
12653 #define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
12654 #define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
12655 #define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
12656 #define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
12657 #define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
12658 #define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
12659 #define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
12660 #define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
12661 #define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
12662 #define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
12663 #define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
12664 #define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
12665 #define DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
12666 #define DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
12667 #define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
12668 #define DCP_CH2STAT_ERROR_DST_MASK (0x20U)
12669 #define DCP_CH2STAT_ERROR_DST_SHIFT (5U)
12670 #define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
12671 #define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
12672 #define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
12673 #define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
12674 #define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
12675 #define DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
12676
12683 #define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
12684 #define DCP_CH2STAT_TAG_MASK (0xFF000000U)
12685 #define DCP_CH2STAT_TAG_SHIFT (24U)
12686 #define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
12687
12691 #define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U)
12692 #define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U)
12693 #define DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
12694 #define DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U)
12695 #define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U)
12696 #define DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
12697 #define DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U)
12698 #define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U)
12699 #define DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
12700 #define DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U)
12701 #define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U)
12702 #define DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
12703 #define DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U)
12704 #define DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U)
12705 #define DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
12706 #define DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U)
12707 #define DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U)
12708 #define DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
12709 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
12710 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
12711 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
12712 #define DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U)
12713 #define DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U)
12714
12721 #define DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
12722 #define DCP_CH2STAT_SET_TAG_MASK (0xFF000000U)
12723 #define DCP_CH2STAT_SET_TAG_SHIFT (24U)
12724 #define DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
12725
12729 #define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
12730 #define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
12731 #define DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
12732 #define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U)
12733 #define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U)
12734 #define DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
12735 #define DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U)
12736 #define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U)
12737 #define DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
12738 #define DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U)
12739 #define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U)
12740 #define DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
12741 #define DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U)
12742 #define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U)
12743 #define DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
12744 #define DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U)
12745 #define DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U)
12746 #define DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
12747 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
12748 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
12749 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
12750 #define DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
12751 #define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U)
12752
12759 #define DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
12760 #define DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U)
12761 #define DCP_CH2STAT_CLR_TAG_SHIFT (24U)
12762 #define DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
12763
12767 #define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
12768 #define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
12769 #define DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
12770 #define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U)
12771 #define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U)
12772 #define DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
12773 #define DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U)
12774 #define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U)
12775 #define DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
12776 #define DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U)
12777 #define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U)
12778 #define DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
12779 #define DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U)
12780 #define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U)
12781 #define DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
12782 #define DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U)
12783 #define DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U)
12784 #define DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
12785 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
12786 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
12787 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
12788 #define DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
12789 #define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U)
12790
12797 #define DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
12798 #define DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U)
12799 #define DCP_CH2STAT_TOG_TAG_SHIFT (24U)
12800 #define DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
12801
12805 #define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
12806 #define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
12807 #define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
12808 #define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
12809 #define DCP_CH2OPTS_RSVD_SHIFT (16U)
12810 #define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
12811
12815 #define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
12816 #define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
12817 #define DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
12818 #define DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U)
12819 #define DCP_CH2OPTS_SET_RSVD_SHIFT (16U)
12820 #define DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
12821
12825 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
12826 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
12827 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
12828 #define DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U)
12829 #define DCP_CH2OPTS_CLR_RSVD_SHIFT (16U)
12830 #define DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
12831
12835 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
12836 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
12837 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
12838 #define DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U)
12839 #define DCP_CH2OPTS_TOG_RSVD_SHIFT (16U)
12840 #define DCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)
12841
12845 #define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)
12846 #define DCP_CH3CMDPTR_ADDR_SHIFT (0U)
12847 #define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
12848
12852 #define DCP_CH3SEMA_INCREMENT_MASK (0xFFU)
12853 #define DCP_CH3SEMA_INCREMENT_SHIFT (0U)
12854 #define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
12855 #define DCP_CH3SEMA_VALUE_MASK (0xFF0000U)
12856 #define DCP_CH3SEMA_VALUE_SHIFT (16U)
12857 #define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
12858
12862 #define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)
12863 #define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)
12864 #define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
12865 #define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)
12866 #define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)
12867 #define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
12868 #define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)
12869 #define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)
12870 #define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
12871 #define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)
12872 #define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)
12873 #define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
12874 #define DCP_CH3STAT_ERROR_SRC_MASK (0x10U)
12875 #define DCP_CH3STAT_ERROR_SRC_SHIFT (4U)
12876 #define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
12877 #define DCP_CH3STAT_ERROR_DST_MASK (0x20U)
12878 #define DCP_CH3STAT_ERROR_DST_SHIFT (5U)
12879 #define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
12880 #define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)
12881 #define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)
12882 #define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
12883 #define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)
12884 #define DCP_CH3STAT_ERROR_CODE_SHIFT (16U)
12885
12892 #define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
12893 #define DCP_CH3STAT_TAG_MASK (0xFF000000U)
12894 #define DCP_CH3STAT_TAG_SHIFT (24U)
12895 #define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
12896
12900 #define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U)
12901 #define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U)
12902 #define DCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)
12903 #define DCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U)
12904 #define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U)
12905 #define DCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)
12906 #define DCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U)
12907 #define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U)
12908 #define DCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)
12909 #define DCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U)
12910 #define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U)
12911 #define DCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)
12912 #define DCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U)
12913 #define DCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U)
12914 #define DCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)
12915 #define DCP_CH3STAT_SET_ERROR_DST_MASK (0x20U)
12916 #define DCP_CH3STAT_SET_ERROR_DST_SHIFT (5U)
12917 #define DCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)
12918 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
12919 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
12920 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)
12921 #define DCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U)
12922 #define DCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U)
12923
12930 #define DCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)
12931 #define DCP_CH3STAT_SET_TAG_MASK (0xFF000000U)
12932 #define DCP_CH3STAT_SET_TAG_SHIFT (24U)
12933 #define DCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)
12934
12938 #define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
12939 #define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
12940 #define DCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)
12941 #define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U)
12942 #define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U)
12943 #define DCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)
12944 #define DCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U)
12945 #define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U)
12946 #define DCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)
12947 #define DCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U)
12948 #define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U)
12949 #define DCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)
12950 #define DCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U)
12951 #define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U)
12952 #define DCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)
12953 #define DCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U)
12954 #define DCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U)
12955 #define DCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)
12956 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
12957 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
12958 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)
12959 #define DCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
12960 #define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U)
12961
12968 #define DCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)
12969 #define DCP_CH3STAT_CLR_TAG_MASK (0xFF000000U)
12970 #define DCP_CH3STAT_CLR_TAG_SHIFT (24U)
12971 #define DCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)
12972
12976 #define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
12977 #define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
12978 #define DCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)
12979 #define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U)
12980 #define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U)
12981 #define DCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)
12982 #define DCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U)
12983 #define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U)
12984 #define DCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)
12985 #define DCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U)
12986 #define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U)
12987 #define DCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)
12988 #define DCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U)
12989 #define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U)
12990 #define DCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)
12991 #define DCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U)
12992 #define DCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U)
12993 #define DCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)
12994 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
12995 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
12996 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)
12997 #define DCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
12998 #define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U)
12999
13006 #define DCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)
13007 #define DCP_CH3STAT_TOG_TAG_MASK (0xFF000000U)
13008 #define DCP_CH3STAT_TOG_TAG_SHIFT (24U)
13009 #define DCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)
13010
13014 #define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
13015 #define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)
13016 #define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
13017 #define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)
13018 #define DCP_CH3OPTS_RSVD_SHIFT (16U)
13019 #define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
13020
13024 #define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
13025 #define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
13026 #define DCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)
13027 #define DCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U)
13028 #define DCP_CH3OPTS_SET_RSVD_SHIFT (16U)
13029 #define DCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)
13030
13034 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
13035 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
13036 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)
13037 #define DCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U)
13038 #define DCP_CH3OPTS_CLR_RSVD_SHIFT (16U)
13039 #define DCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)
13040
13044 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
13045 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
13046 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)
13047 #define DCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U)
13048 #define DCP_CH3OPTS_TOG_RSVD_SHIFT (16U)
13049 #define DCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)
13050
13054 #define DCP_DBGSELECT_INDEX_MASK (0xFFU)
13055 #define DCP_DBGSELECT_INDEX_SHIFT (0U)
13056
13063 #define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
13064 #define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)
13065 #define DCP_DBGSELECT_RSVD_SHIFT (8U)
13066 #define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
13067
13071 #define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)
13072 #define DCP_DBGDATA_DATA_SHIFT (0U)
13073 #define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
13074
13078 #define DCP_PAGETABLE_ENABLE_MASK (0x1U)
13079 #define DCP_PAGETABLE_ENABLE_SHIFT (0U)
13080 #define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
13081 #define DCP_PAGETABLE_FLUSH_MASK (0x2U)
13082 #define DCP_PAGETABLE_FLUSH_SHIFT (1U)
13083 #define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
13084 #define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)
13085 #define DCP_PAGETABLE_BASE_SHIFT (2U)
13086 #define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
13087
13091 #define DCP_VERSION_STEP_MASK (0xFFFFU)
13092 #define DCP_VERSION_STEP_SHIFT (0U)
13093 #define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
13094 #define DCP_VERSION_MINOR_MASK (0xFF0000U)
13095 #define DCP_VERSION_MINOR_SHIFT (16U)
13096 #define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
13097 #define DCP_VERSION_MAJOR_MASK (0xFF000000U)
13098 #define DCP_VERSION_MAJOR_SHIFT (24U)
13099 #define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)
13100 /* end of group DCP_Register_Masks */
13106
13107
13108 /* DCP - Peripheral instance base addresses */
13110 #define DCP_BASE (0x402FC000u)
13111
13112 #define DCP ((DCP_Type *)DCP_BASE)
13113
13114 #define DCP_BASE_ADDRS { DCP_BASE }
13115
13116 #define DCP_BASE_PTRS { DCP }
13117
13118 #define DCP_IRQS { DCP_IRQn }
13119 #define DCP_VMI_IRQS { DCP_VMI_IRQn }
13120 /* end of group DCP_Peripheral_Access_Layer */
13124
13125
13126 /* ----------------------------------------------------------------------------
13127 -- DMA Peripheral Access Layer
13128 ---------------------------------------------------------------------------- */
13129
13136 typedef struct {
13137 __IO uint32_t CR;
13138 __I uint32_t ES;
13139 uint8_t RESERVED_0[4];
13140 __IO uint32_t ERQ;
13141 uint8_t RESERVED_1[4];
13142 __IO uint32_t EEI;
13143 __O uint8_t CEEI;
13144 __O uint8_t SEEI;
13145 __O uint8_t CERQ;
13146 __O uint8_t SERQ;
13147 __O uint8_t CDNE;
13148 __O uint8_t SSRT;
13149 __O uint8_t CERR;
13150 __O uint8_t CINT;
13151 uint8_t RESERVED_2[4];
13152 __IO uint32_t INT;
13153 uint8_t RESERVED_3[4];
13154 __IO uint32_t ERR;
13155 uint8_t RESERVED_4[4];
13156 __I uint32_t HRS;
13157 uint8_t RESERVED_5[12];
13158 __IO uint32_t EARS;
13159 uint8_t RESERVED_6[184];
13160 __IO uint8_t DCHPRI3;
13161 __IO uint8_t DCHPRI2;
13162 __IO uint8_t DCHPRI1;
13163 __IO uint8_t DCHPRI0;
13164 __IO uint8_t DCHPRI7;
13165 __IO uint8_t DCHPRI6;
13166 __IO uint8_t DCHPRI5;
13167 __IO uint8_t DCHPRI4;
13168 __IO uint8_t DCHPRI11;
13169 __IO uint8_t DCHPRI10;
13170 __IO uint8_t DCHPRI9;
13171 __IO uint8_t DCHPRI8;
13172 __IO uint8_t DCHPRI15;
13173 __IO uint8_t DCHPRI14;
13174 __IO uint8_t DCHPRI13;
13175 __IO uint8_t DCHPRI12;
13176 __IO uint8_t DCHPRI19;
13177 __IO uint8_t DCHPRI18;
13178 __IO uint8_t DCHPRI17;
13179 __IO uint8_t DCHPRI16;
13180 __IO uint8_t DCHPRI23;
13181 __IO uint8_t DCHPRI22;
13182 __IO uint8_t DCHPRI21;
13183 __IO uint8_t DCHPRI20;
13184 __IO uint8_t DCHPRI27;
13185 __IO uint8_t DCHPRI26;
13186 __IO uint8_t DCHPRI25;
13187 __IO uint8_t DCHPRI24;
13188 __IO uint8_t DCHPRI31;
13189 __IO uint8_t DCHPRI30;
13190 __IO uint8_t DCHPRI29;
13191 __IO uint8_t DCHPRI28;
13192 uint8_t RESERVED_7[3808];
13193 struct { /* offset: 0x1000, array step: 0x20 */
13194 __IO uint32_t SADDR;
13195 __IO uint16_t SOFF;
13196 __IO uint16_t ATTR;
13197 union { /* offset: 0x1008, array step: 0x20 */
13198 __IO uint32_t NBYTES_MLNO;
13199 __IO uint32_t NBYTES_MLOFFNO;
13200 __IO uint32_t NBYTES_MLOFFYES;
13201 };
13202 __IO uint32_t SLAST;
13203 __IO uint32_t DADDR;
13204 __IO uint16_t DOFF;
13205 union { /* offset: 0x1016, array step: 0x20 */
13206 __IO uint16_t CITER_ELINKNO;
13207 __IO uint16_t CITER_ELINKYES;
13208 };
13209 __IO uint32_t DLAST_SGA;
13210 __IO uint16_t CSR;
13211 union { /* offset: 0x101E, array step: 0x20 */
13212 __IO uint16_t BITER_ELINKNO;
13213 __IO uint16_t BITER_ELINKYES;
13214 };
13215 } TCD[32];
13216 } DMA_Type;
13217
13218 /* ----------------------------------------------------------------------------
13219 -- DMA Register Masks
13220 ---------------------------------------------------------------------------- */
13221
13229 #define DMA_CR_EDBG_MASK (0x2U)
13230 #define DMA_CR_EDBG_SHIFT (1U)
13231
13236 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
13237 #define DMA_CR_ERCA_MASK (0x4U)
13238 #define DMA_CR_ERCA_SHIFT (2U)
13239
13243 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
13244 #define DMA_CR_ERGA_MASK (0x8U)
13245 #define DMA_CR_ERGA_SHIFT (3U)
13246
13250 #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
13251 #define DMA_CR_HOE_MASK (0x10U)
13252 #define DMA_CR_HOE_SHIFT (4U)
13253
13257 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
13258 #define DMA_CR_HALT_MASK (0x20U)
13259 #define DMA_CR_HALT_SHIFT (5U)
13260
13264 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
13265 #define DMA_CR_CLM_MASK (0x40U)
13266 #define DMA_CR_CLM_SHIFT (6U)
13267
13274 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
13275 #define DMA_CR_EMLM_MASK (0x80U)
13276 #define DMA_CR_EMLM_SHIFT (7U)
13277
13283 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
13284 #define DMA_CR_GRP0PRI_MASK (0x100U)
13285 #define DMA_CR_GRP0PRI_SHIFT (8U)
13286
13288 #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
13289 #define DMA_CR_GRP1PRI_MASK (0x400U)
13290 #define DMA_CR_GRP1PRI_SHIFT (10U)
13291
13293 #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
13294 #define DMA_CR_ECX_MASK (0x10000U)
13295 #define DMA_CR_ECX_SHIFT (16U)
13296
13304 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
13305 #define DMA_CR_CX_MASK (0x20000U)
13306 #define DMA_CR_CX_SHIFT (17U)
13307
13313 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
13314 #define DMA_CR_ACTIVE_MASK (0x80000000U)
13315 #define DMA_CR_ACTIVE_SHIFT (31U)
13316
13320 #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
13321
13325 #define DMA_ES_DBE_MASK (0x1U)
13326 #define DMA_ES_DBE_SHIFT (0U)
13327
13331 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
13332 #define DMA_ES_SBE_MASK (0x2U)
13333 #define DMA_ES_SBE_SHIFT (1U)
13334
13338 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
13339 #define DMA_ES_SGE_MASK (0x4U)
13340 #define DMA_ES_SGE_SHIFT (2U)
13341
13347 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
13348 #define DMA_ES_NCE_MASK (0x8U)
13349 #define DMA_ES_NCE_SHIFT (3U)
13350
13356 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
13357 #define DMA_ES_DOE_MASK (0x10U)
13358 #define DMA_ES_DOE_SHIFT (4U)
13359
13363 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
13364 #define DMA_ES_DAE_MASK (0x20U)
13365 #define DMA_ES_DAE_SHIFT (5U)
13366
13370 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
13371 #define DMA_ES_SOE_MASK (0x40U)
13372 #define DMA_ES_SOE_SHIFT (6U)
13373
13377 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
13378 #define DMA_ES_SAE_MASK (0x80U)
13379 #define DMA_ES_SAE_SHIFT (7U)
13380
13384 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
13385 #define DMA_ES_ERRCHN_MASK (0x1F00U)
13386 #define DMA_ES_ERRCHN_SHIFT (8U)
13387
13389 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
13390 #define DMA_ES_CPE_MASK (0x4000U)
13391 #define DMA_ES_CPE_SHIFT (14U)
13392
13397 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
13398 #define DMA_ES_GPE_MASK (0x8000U)
13399 #define DMA_ES_GPE_SHIFT (15U)
13400
13404 #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
13405 #define DMA_ES_ECX_MASK (0x10000U)
13406 #define DMA_ES_ECX_SHIFT (16U)
13407
13411 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
13412 #define DMA_ES_VLD_MASK (0x80000000U)
13413 #define DMA_ES_VLD_SHIFT (31U)
13414
13418 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
13419
13423 #define DMA_ERQ_ERQ0_MASK (0x1U)
13424 #define DMA_ERQ_ERQ0_SHIFT (0U)
13425
13429 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
13430 #define DMA_ERQ_ERQ1_MASK (0x2U)
13431 #define DMA_ERQ_ERQ1_SHIFT (1U)
13432
13436 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
13437 #define DMA_ERQ_ERQ2_MASK (0x4U)
13438 #define DMA_ERQ_ERQ2_SHIFT (2U)
13439
13443 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
13444 #define DMA_ERQ_ERQ3_MASK (0x8U)
13445 #define DMA_ERQ_ERQ3_SHIFT (3U)
13446
13450 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
13451 #define DMA_ERQ_ERQ4_MASK (0x10U)
13452 #define DMA_ERQ_ERQ4_SHIFT (4U)
13453
13457 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
13458 #define DMA_ERQ_ERQ5_MASK (0x20U)
13459 #define DMA_ERQ_ERQ5_SHIFT (5U)
13460
13464 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
13465 #define DMA_ERQ_ERQ6_MASK (0x40U)
13466 #define DMA_ERQ_ERQ6_SHIFT (6U)
13467
13471 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
13472 #define DMA_ERQ_ERQ7_MASK (0x80U)
13473 #define DMA_ERQ_ERQ7_SHIFT (7U)
13474
13478 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
13479 #define DMA_ERQ_ERQ8_MASK (0x100U)
13480 #define DMA_ERQ_ERQ8_SHIFT (8U)
13481
13485 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
13486 #define DMA_ERQ_ERQ9_MASK (0x200U)
13487 #define DMA_ERQ_ERQ9_SHIFT (9U)
13488
13492 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
13493 #define DMA_ERQ_ERQ10_MASK (0x400U)
13494 #define DMA_ERQ_ERQ10_SHIFT (10U)
13495
13499 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
13500 #define DMA_ERQ_ERQ11_MASK (0x800U)
13501 #define DMA_ERQ_ERQ11_SHIFT (11U)
13502
13506 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
13507 #define DMA_ERQ_ERQ12_MASK (0x1000U)
13508 #define DMA_ERQ_ERQ12_SHIFT (12U)
13509
13513 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
13514 #define DMA_ERQ_ERQ13_MASK (0x2000U)
13515 #define DMA_ERQ_ERQ13_SHIFT (13U)
13516
13520 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
13521 #define DMA_ERQ_ERQ14_MASK (0x4000U)
13522 #define DMA_ERQ_ERQ14_SHIFT (14U)
13523
13527 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
13528 #define DMA_ERQ_ERQ15_MASK (0x8000U)
13529 #define DMA_ERQ_ERQ15_SHIFT (15U)
13530
13534 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
13535 #define DMA_ERQ_ERQ16_MASK (0x10000U)
13536 #define DMA_ERQ_ERQ16_SHIFT (16U)
13537
13541 #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
13542 #define DMA_ERQ_ERQ17_MASK (0x20000U)
13543 #define DMA_ERQ_ERQ17_SHIFT (17U)
13544
13548 #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
13549 #define DMA_ERQ_ERQ18_MASK (0x40000U)
13550 #define DMA_ERQ_ERQ18_SHIFT (18U)
13551
13555 #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
13556 #define DMA_ERQ_ERQ19_MASK (0x80000U)
13557 #define DMA_ERQ_ERQ19_SHIFT (19U)
13558
13562 #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
13563 #define DMA_ERQ_ERQ20_MASK (0x100000U)
13564 #define DMA_ERQ_ERQ20_SHIFT (20U)
13565
13569 #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
13570 #define DMA_ERQ_ERQ21_MASK (0x200000U)
13571 #define DMA_ERQ_ERQ21_SHIFT (21U)
13572
13576 #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
13577 #define DMA_ERQ_ERQ22_MASK (0x400000U)
13578 #define DMA_ERQ_ERQ22_SHIFT (22U)
13579
13583 #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
13584 #define DMA_ERQ_ERQ23_MASK (0x800000U)
13585 #define DMA_ERQ_ERQ23_SHIFT (23U)
13586
13590 #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
13591 #define DMA_ERQ_ERQ24_MASK (0x1000000U)
13592 #define DMA_ERQ_ERQ24_SHIFT (24U)
13593
13597 #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
13598 #define DMA_ERQ_ERQ25_MASK (0x2000000U)
13599 #define DMA_ERQ_ERQ25_SHIFT (25U)
13600
13604 #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
13605 #define DMA_ERQ_ERQ26_MASK (0x4000000U)
13606 #define DMA_ERQ_ERQ26_SHIFT (26U)
13607
13611 #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
13612 #define DMA_ERQ_ERQ27_MASK (0x8000000U)
13613 #define DMA_ERQ_ERQ27_SHIFT (27U)
13614
13618 #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
13619 #define DMA_ERQ_ERQ28_MASK (0x10000000U)
13620 #define DMA_ERQ_ERQ28_SHIFT (28U)
13621
13625 #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
13626 #define DMA_ERQ_ERQ29_MASK (0x20000000U)
13627 #define DMA_ERQ_ERQ29_SHIFT (29U)
13628
13632 #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
13633 #define DMA_ERQ_ERQ30_MASK (0x40000000U)
13634 #define DMA_ERQ_ERQ30_SHIFT (30U)
13635
13639 #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
13640 #define DMA_ERQ_ERQ31_MASK (0x80000000U)
13641 #define DMA_ERQ_ERQ31_SHIFT (31U)
13642
13646 #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
13647
13651 #define DMA_EEI_EEI0_MASK (0x1U)
13652 #define DMA_EEI_EEI0_SHIFT (0U)
13653
13657 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
13658 #define DMA_EEI_EEI1_MASK (0x2U)
13659 #define DMA_EEI_EEI1_SHIFT (1U)
13660
13664 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
13665 #define DMA_EEI_EEI2_MASK (0x4U)
13666 #define DMA_EEI_EEI2_SHIFT (2U)
13667
13671 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
13672 #define DMA_EEI_EEI3_MASK (0x8U)
13673 #define DMA_EEI_EEI3_SHIFT (3U)
13674
13678 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
13679 #define DMA_EEI_EEI4_MASK (0x10U)
13680 #define DMA_EEI_EEI4_SHIFT (4U)
13681
13685 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
13686 #define DMA_EEI_EEI5_MASK (0x20U)
13687 #define DMA_EEI_EEI5_SHIFT (5U)
13688
13692 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
13693 #define DMA_EEI_EEI6_MASK (0x40U)
13694 #define DMA_EEI_EEI6_SHIFT (6U)
13695
13699 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
13700 #define DMA_EEI_EEI7_MASK (0x80U)
13701 #define DMA_EEI_EEI7_SHIFT (7U)
13702
13706 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
13707 #define DMA_EEI_EEI8_MASK (0x100U)
13708 #define DMA_EEI_EEI8_SHIFT (8U)
13709
13713 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
13714 #define DMA_EEI_EEI9_MASK (0x200U)
13715 #define DMA_EEI_EEI9_SHIFT (9U)
13716
13720 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
13721 #define DMA_EEI_EEI10_MASK (0x400U)
13722 #define DMA_EEI_EEI10_SHIFT (10U)
13723
13727 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
13728 #define DMA_EEI_EEI11_MASK (0x800U)
13729 #define DMA_EEI_EEI11_SHIFT (11U)
13730
13734 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
13735 #define DMA_EEI_EEI12_MASK (0x1000U)
13736 #define DMA_EEI_EEI12_SHIFT (12U)
13737
13741 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
13742 #define DMA_EEI_EEI13_MASK (0x2000U)
13743 #define DMA_EEI_EEI13_SHIFT (13U)
13744
13748 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
13749 #define DMA_EEI_EEI14_MASK (0x4000U)
13750 #define DMA_EEI_EEI14_SHIFT (14U)
13751
13755 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
13756 #define DMA_EEI_EEI15_MASK (0x8000U)
13757 #define DMA_EEI_EEI15_SHIFT (15U)
13758
13762 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
13763 #define DMA_EEI_EEI16_MASK (0x10000U)
13764 #define DMA_EEI_EEI16_SHIFT (16U)
13765
13769 #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
13770 #define DMA_EEI_EEI17_MASK (0x20000U)
13771 #define DMA_EEI_EEI17_SHIFT (17U)
13772
13776 #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
13777 #define DMA_EEI_EEI18_MASK (0x40000U)
13778 #define DMA_EEI_EEI18_SHIFT (18U)
13779
13783 #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
13784 #define DMA_EEI_EEI19_MASK (0x80000U)
13785 #define DMA_EEI_EEI19_SHIFT (19U)
13786
13790 #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
13791 #define DMA_EEI_EEI20_MASK (0x100000U)
13792 #define DMA_EEI_EEI20_SHIFT (20U)
13793
13797 #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
13798 #define DMA_EEI_EEI21_MASK (0x200000U)
13799 #define DMA_EEI_EEI21_SHIFT (21U)
13800
13804 #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
13805 #define DMA_EEI_EEI22_MASK (0x400000U)
13806 #define DMA_EEI_EEI22_SHIFT (22U)
13807
13811 #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
13812 #define DMA_EEI_EEI23_MASK (0x800000U)
13813 #define DMA_EEI_EEI23_SHIFT (23U)
13814
13818 #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
13819 #define DMA_EEI_EEI24_MASK (0x1000000U)
13820 #define DMA_EEI_EEI24_SHIFT (24U)
13821
13825 #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
13826 #define DMA_EEI_EEI25_MASK (0x2000000U)
13827 #define DMA_EEI_EEI25_SHIFT (25U)
13828
13832 #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
13833 #define DMA_EEI_EEI26_MASK (0x4000000U)
13834 #define DMA_EEI_EEI26_SHIFT (26U)
13835
13839 #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
13840 #define DMA_EEI_EEI27_MASK (0x8000000U)
13841 #define DMA_EEI_EEI27_SHIFT (27U)
13842
13846 #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
13847 #define DMA_EEI_EEI28_MASK (0x10000000U)
13848 #define DMA_EEI_EEI28_SHIFT (28U)
13849
13853 #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
13854 #define DMA_EEI_EEI29_MASK (0x20000000U)
13855 #define DMA_EEI_EEI29_SHIFT (29U)
13856
13860 #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
13861 #define DMA_EEI_EEI30_MASK (0x40000000U)
13862 #define DMA_EEI_EEI30_SHIFT (30U)
13863
13867 #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
13868 #define DMA_EEI_EEI31_MASK (0x80000000U)
13869 #define DMA_EEI_EEI31_SHIFT (31U)
13870
13874 #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
13875
13879 #define DMA_CEEI_CEEI_MASK (0x1FU)
13880 #define DMA_CEEI_CEEI_SHIFT (0U)
13881
13883 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
13884 #define DMA_CEEI_CAEE_MASK (0x40U)
13885 #define DMA_CEEI_CAEE_SHIFT (6U)
13886
13890 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
13891 #define DMA_CEEI_NOP_MASK (0x80U)
13892 #define DMA_CEEI_NOP_SHIFT (7U)
13893
13897 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
13898
13902 #define DMA_SEEI_SEEI_MASK (0x1FU)
13903 #define DMA_SEEI_SEEI_SHIFT (0U)
13904
13906 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
13907 #define DMA_SEEI_SAEE_MASK (0x40U)
13908 #define DMA_SEEI_SAEE_SHIFT (6U)
13909
13913 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
13914 #define DMA_SEEI_NOP_MASK (0x80U)
13915 #define DMA_SEEI_NOP_SHIFT (7U)
13916
13920 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
13921
13925 #define DMA_CERQ_CERQ_MASK (0x1FU)
13926 #define DMA_CERQ_CERQ_SHIFT (0U)
13927
13929 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
13930 #define DMA_CERQ_CAER_MASK (0x40U)
13931 #define DMA_CERQ_CAER_SHIFT (6U)
13932
13936 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
13937 #define DMA_CERQ_NOP_MASK (0x80U)
13938 #define DMA_CERQ_NOP_SHIFT (7U)
13939
13943 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
13944
13948 #define DMA_SERQ_SERQ_MASK (0x1FU)
13949 #define DMA_SERQ_SERQ_SHIFT (0U)
13950
13952 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
13953 #define DMA_SERQ_SAER_MASK (0x40U)
13954 #define DMA_SERQ_SAER_SHIFT (6U)
13955
13959 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
13960 #define DMA_SERQ_NOP_MASK (0x80U)
13961 #define DMA_SERQ_NOP_SHIFT (7U)
13962
13966 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
13967
13971 #define DMA_CDNE_CDNE_MASK (0x1FU)
13972 #define DMA_CDNE_CDNE_SHIFT (0U)
13973
13975 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
13976 #define DMA_CDNE_CADN_MASK (0x40U)
13977 #define DMA_CDNE_CADN_SHIFT (6U)
13978
13982 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
13983 #define DMA_CDNE_NOP_MASK (0x80U)
13984 #define DMA_CDNE_NOP_SHIFT (7U)
13985
13989 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
13990
13994 #define DMA_SSRT_SSRT_MASK (0x1FU)
13995 #define DMA_SSRT_SSRT_SHIFT (0U)
13996
13998 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
13999 #define DMA_SSRT_SAST_MASK (0x40U)
14000 #define DMA_SSRT_SAST_SHIFT (6U)
14001
14005 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
14006 #define DMA_SSRT_NOP_MASK (0x80U)
14007 #define DMA_SSRT_NOP_SHIFT (7U)
14008
14012 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
14013
14017 #define DMA_CERR_CERR_MASK (0x1FU)
14018 #define DMA_CERR_CERR_SHIFT (0U)
14019
14021 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
14022 #define DMA_CERR_CAEI_MASK (0x40U)
14023 #define DMA_CERR_CAEI_SHIFT (6U)
14024
14028 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
14029 #define DMA_CERR_NOP_MASK (0x80U)
14030 #define DMA_CERR_NOP_SHIFT (7U)
14031
14035 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
14036
14040 #define DMA_CINT_CINT_MASK (0x1FU)
14041 #define DMA_CINT_CINT_SHIFT (0U)
14042
14044 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
14045 #define DMA_CINT_CAIR_MASK (0x40U)
14046 #define DMA_CINT_CAIR_SHIFT (6U)
14047
14051 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
14052 #define DMA_CINT_NOP_MASK (0x80U)
14053 #define DMA_CINT_NOP_SHIFT (7U)
14054
14058 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
14059
14063 #define DMA_INT_INT0_MASK (0x1U)
14064 #define DMA_INT_INT0_SHIFT (0U)
14065
14069 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
14070 #define DMA_INT_INT1_MASK (0x2U)
14071 #define DMA_INT_INT1_SHIFT (1U)
14072
14076 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
14077 #define DMA_INT_INT2_MASK (0x4U)
14078 #define DMA_INT_INT2_SHIFT (2U)
14079
14083 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
14084 #define DMA_INT_INT3_MASK (0x8U)
14085 #define DMA_INT_INT3_SHIFT (3U)
14086
14090 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
14091 #define DMA_INT_INT4_MASK (0x10U)
14092 #define DMA_INT_INT4_SHIFT (4U)
14093
14097 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
14098 #define DMA_INT_INT5_MASK (0x20U)
14099 #define DMA_INT_INT5_SHIFT (5U)
14100
14104 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
14105 #define DMA_INT_INT6_MASK (0x40U)
14106 #define DMA_INT_INT6_SHIFT (6U)
14107
14111 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
14112 #define DMA_INT_INT7_MASK (0x80U)
14113 #define DMA_INT_INT7_SHIFT (7U)
14114
14118 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
14119 #define DMA_INT_INT8_MASK (0x100U)
14120 #define DMA_INT_INT8_SHIFT (8U)
14121
14125 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
14126 #define DMA_INT_INT9_MASK (0x200U)
14127 #define DMA_INT_INT9_SHIFT (9U)
14128
14132 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
14133 #define DMA_INT_INT10_MASK (0x400U)
14134 #define DMA_INT_INT10_SHIFT (10U)
14135
14139 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
14140 #define DMA_INT_INT11_MASK (0x800U)
14141 #define DMA_INT_INT11_SHIFT (11U)
14142
14146 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
14147 #define DMA_INT_INT12_MASK (0x1000U)
14148 #define DMA_INT_INT12_SHIFT (12U)
14149
14153 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
14154 #define DMA_INT_INT13_MASK (0x2000U)
14155 #define DMA_INT_INT13_SHIFT (13U)
14156
14160 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
14161 #define DMA_INT_INT14_MASK (0x4000U)
14162 #define DMA_INT_INT14_SHIFT (14U)
14163
14167 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
14168 #define DMA_INT_INT15_MASK (0x8000U)
14169 #define DMA_INT_INT15_SHIFT (15U)
14170
14174 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
14175 #define DMA_INT_INT16_MASK (0x10000U)
14176 #define DMA_INT_INT16_SHIFT (16U)
14177
14181 #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
14182 #define DMA_INT_INT17_MASK (0x20000U)
14183 #define DMA_INT_INT17_SHIFT (17U)
14184
14188 #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
14189 #define DMA_INT_INT18_MASK (0x40000U)
14190 #define DMA_INT_INT18_SHIFT (18U)
14191
14195 #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
14196 #define DMA_INT_INT19_MASK (0x80000U)
14197 #define DMA_INT_INT19_SHIFT (19U)
14198
14202 #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
14203 #define DMA_INT_INT20_MASK (0x100000U)
14204 #define DMA_INT_INT20_SHIFT (20U)
14205
14209 #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
14210 #define DMA_INT_INT21_MASK (0x200000U)
14211 #define DMA_INT_INT21_SHIFT (21U)
14212
14216 #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
14217 #define DMA_INT_INT22_MASK (0x400000U)
14218 #define DMA_INT_INT22_SHIFT (22U)
14219
14223 #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
14224 #define DMA_INT_INT23_MASK (0x800000U)
14225 #define DMA_INT_INT23_SHIFT (23U)
14226
14230 #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
14231 #define DMA_INT_INT24_MASK (0x1000000U)
14232 #define DMA_INT_INT24_SHIFT (24U)
14233
14237 #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
14238 #define DMA_INT_INT25_MASK (0x2000000U)
14239 #define DMA_INT_INT25_SHIFT (25U)
14240
14244 #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
14245 #define DMA_INT_INT26_MASK (0x4000000U)
14246 #define DMA_INT_INT26_SHIFT (26U)
14247
14251 #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
14252 #define DMA_INT_INT27_MASK (0x8000000U)
14253 #define DMA_INT_INT27_SHIFT (27U)
14254
14258 #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
14259 #define DMA_INT_INT28_MASK (0x10000000U)
14260 #define DMA_INT_INT28_SHIFT (28U)
14261
14265 #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
14266 #define DMA_INT_INT29_MASK (0x20000000U)
14267 #define DMA_INT_INT29_SHIFT (29U)
14268
14272 #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
14273 #define DMA_INT_INT30_MASK (0x40000000U)
14274 #define DMA_INT_INT30_SHIFT (30U)
14275
14279 #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
14280 #define DMA_INT_INT31_MASK (0x80000000U)
14281 #define DMA_INT_INT31_SHIFT (31U)
14282
14286 #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
14287
14291 #define DMA_ERR_ERR0_MASK (0x1U)
14292 #define DMA_ERR_ERR0_SHIFT (0U)
14293
14297 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
14298 #define DMA_ERR_ERR1_MASK (0x2U)
14299 #define DMA_ERR_ERR1_SHIFT (1U)
14300
14304 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
14305 #define DMA_ERR_ERR2_MASK (0x4U)
14306 #define DMA_ERR_ERR2_SHIFT (2U)
14307
14311 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
14312 #define DMA_ERR_ERR3_MASK (0x8U)
14313 #define DMA_ERR_ERR3_SHIFT (3U)
14314
14318 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
14319 #define DMA_ERR_ERR4_MASK (0x10U)
14320 #define DMA_ERR_ERR4_SHIFT (4U)
14321
14325 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
14326 #define DMA_ERR_ERR5_MASK (0x20U)
14327 #define DMA_ERR_ERR5_SHIFT (5U)
14328
14332 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
14333 #define DMA_ERR_ERR6_MASK (0x40U)
14334 #define DMA_ERR_ERR6_SHIFT (6U)
14335
14339 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
14340 #define DMA_ERR_ERR7_MASK (0x80U)
14341 #define DMA_ERR_ERR7_SHIFT (7U)
14342
14346 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
14347 #define DMA_ERR_ERR8_MASK (0x100U)
14348 #define DMA_ERR_ERR8_SHIFT (8U)
14349
14353 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
14354 #define DMA_ERR_ERR9_MASK (0x200U)
14355 #define DMA_ERR_ERR9_SHIFT (9U)
14356
14360 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
14361 #define DMA_ERR_ERR10_MASK (0x400U)
14362 #define DMA_ERR_ERR10_SHIFT (10U)
14363
14367 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
14368 #define DMA_ERR_ERR11_MASK (0x800U)
14369 #define DMA_ERR_ERR11_SHIFT (11U)
14370
14374 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
14375 #define DMA_ERR_ERR12_MASK (0x1000U)
14376 #define DMA_ERR_ERR12_SHIFT (12U)
14377
14381 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
14382 #define DMA_ERR_ERR13_MASK (0x2000U)
14383 #define DMA_ERR_ERR13_SHIFT (13U)
14384
14388 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
14389 #define DMA_ERR_ERR14_MASK (0x4000U)
14390 #define DMA_ERR_ERR14_SHIFT (14U)
14391
14395 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
14396 #define DMA_ERR_ERR15_MASK (0x8000U)
14397 #define DMA_ERR_ERR15_SHIFT (15U)
14398
14402 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
14403 #define DMA_ERR_ERR16_MASK (0x10000U)
14404 #define DMA_ERR_ERR16_SHIFT (16U)
14405
14409 #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
14410 #define DMA_ERR_ERR17_MASK (0x20000U)
14411 #define DMA_ERR_ERR17_SHIFT (17U)
14412
14416 #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
14417 #define DMA_ERR_ERR18_MASK (0x40000U)
14418 #define DMA_ERR_ERR18_SHIFT (18U)
14419
14423 #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
14424 #define DMA_ERR_ERR19_MASK (0x80000U)
14425 #define DMA_ERR_ERR19_SHIFT (19U)
14426
14430 #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
14431 #define DMA_ERR_ERR20_MASK (0x100000U)
14432 #define DMA_ERR_ERR20_SHIFT (20U)
14433
14437 #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
14438 #define DMA_ERR_ERR21_MASK (0x200000U)
14439 #define DMA_ERR_ERR21_SHIFT (21U)
14440
14444 #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
14445 #define DMA_ERR_ERR22_MASK (0x400000U)
14446 #define DMA_ERR_ERR22_SHIFT (22U)
14447
14451 #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
14452 #define DMA_ERR_ERR23_MASK (0x800000U)
14453 #define DMA_ERR_ERR23_SHIFT (23U)
14454
14458 #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
14459 #define DMA_ERR_ERR24_MASK (0x1000000U)
14460 #define DMA_ERR_ERR24_SHIFT (24U)
14461
14465 #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
14466 #define DMA_ERR_ERR25_MASK (0x2000000U)
14467 #define DMA_ERR_ERR25_SHIFT (25U)
14468
14472 #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
14473 #define DMA_ERR_ERR26_MASK (0x4000000U)
14474 #define DMA_ERR_ERR26_SHIFT (26U)
14475
14479 #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
14480 #define DMA_ERR_ERR27_MASK (0x8000000U)
14481 #define DMA_ERR_ERR27_SHIFT (27U)
14482
14486 #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
14487 #define DMA_ERR_ERR28_MASK (0x10000000U)
14488 #define DMA_ERR_ERR28_SHIFT (28U)
14489
14493 #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
14494 #define DMA_ERR_ERR29_MASK (0x20000000U)
14495 #define DMA_ERR_ERR29_SHIFT (29U)
14496
14500 #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
14501 #define DMA_ERR_ERR30_MASK (0x40000000U)
14502 #define DMA_ERR_ERR30_SHIFT (30U)
14503
14507 #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
14508 #define DMA_ERR_ERR31_MASK (0x80000000U)
14509 #define DMA_ERR_ERR31_SHIFT (31U)
14510
14514 #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
14515
14519 #define DMA_HRS_HRS0_MASK (0x1U)
14520 #define DMA_HRS_HRS0_SHIFT (0U)
14521
14525 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
14526 #define DMA_HRS_HRS1_MASK (0x2U)
14527 #define DMA_HRS_HRS1_SHIFT (1U)
14528
14532 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
14533 #define DMA_HRS_HRS2_MASK (0x4U)
14534 #define DMA_HRS_HRS2_SHIFT (2U)
14535
14539 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
14540 #define DMA_HRS_HRS3_MASK (0x8U)
14541 #define DMA_HRS_HRS3_SHIFT (3U)
14542
14546 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
14547 #define DMA_HRS_HRS4_MASK (0x10U)
14548 #define DMA_HRS_HRS4_SHIFT (4U)
14549
14553 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
14554 #define DMA_HRS_HRS5_MASK (0x20U)
14555 #define DMA_HRS_HRS5_SHIFT (5U)
14556
14560 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
14561 #define DMA_HRS_HRS6_MASK (0x40U)
14562 #define DMA_HRS_HRS6_SHIFT (6U)
14563
14567 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
14568 #define DMA_HRS_HRS7_MASK (0x80U)
14569 #define DMA_HRS_HRS7_SHIFT (7U)
14570
14574 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
14575 #define DMA_HRS_HRS8_MASK (0x100U)
14576 #define DMA_HRS_HRS8_SHIFT (8U)
14577
14581 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
14582 #define DMA_HRS_HRS9_MASK (0x200U)
14583 #define DMA_HRS_HRS9_SHIFT (9U)
14584
14588 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
14589 #define DMA_HRS_HRS10_MASK (0x400U)
14590 #define DMA_HRS_HRS10_SHIFT (10U)
14591
14595 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
14596 #define DMA_HRS_HRS11_MASK (0x800U)
14597 #define DMA_HRS_HRS11_SHIFT (11U)
14598
14602 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
14603 #define DMA_HRS_HRS12_MASK (0x1000U)
14604 #define DMA_HRS_HRS12_SHIFT (12U)
14605
14609 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
14610 #define DMA_HRS_HRS13_MASK (0x2000U)
14611 #define DMA_HRS_HRS13_SHIFT (13U)
14612
14616 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
14617 #define DMA_HRS_HRS14_MASK (0x4000U)
14618 #define DMA_HRS_HRS14_SHIFT (14U)
14619
14623 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
14624 #define DMA_HRS_HRS15_MASK (0x8000U)
14625 #define DMA_HRS_HRS15_SHIFT (15U)
14626
14630 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
14631 #define DMA_HRS_HRS16_MASK (0x10000U)
14632 #define DMA_HRS_HRS16_SHIFT (16U)
14633
14637 #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
14638 #define DMA_HRS_HRS17_MASK (0x20000U)
14639 #define DMA_HRS_HRS17_SHIFT (17U)
14640
14644 #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
14645 #define DMA_HRS_HRS18_MASK (0x40000U)
14646 #define DMA_HRS_HRS18_SHIFT (18U)
14647
14651 #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
14652 #define DMA_HRS_HRS19_MASK (0x80000U)
14653 #define DMA_HRS_HRS19_SHIFT (19U)
14654
14658 #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
14659 #define DMA_HRS_HRS20_MASK (0x100000U)
14660 #define DMA_HRS_HRS20_SHIFT (20U)
14661
14665 #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
14666 #define DMA_HRS_HRS21_MASK (0x200000U)
14667 #define DMA_HRS_HRS21_SHIFT (21U)
14668
14672 #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
14673 #define DMA_HRS_HRS22_MASK (0x400000U)
14674 #define DMA_HRS_HRS22_SHIFT (22U)
14675
14679 #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
14680 #define DMA_HRS_HRS23_MASK (0x800000U)
14681 #define DMA_HRS_HRS23_SHIFT (23U)
14682
14686 #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
14687 #define DMA_HRS_HRS24_MASK (0x1000000U)
14688 #define DMA_HRS_HRS24_SHIFT (24U)
14689
14693 #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
14694 #define DMA_HRS_HRS25_MASK (0x2000000U)
14695 #define DMA_HRS_HRS25_SHIFT (25U)
14696
14700 #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
14701 #define DMA_HRS_HRS26_MASK (0x4000000U)
14702 #define DMA_HRS_HRS26_SHIFT (26U)
14703
14707 #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
14708 #define DMA_HRS_HRS27_MASK (0x8000000U)
14709 #define DMA_HRS_HRS27_SHIFT (27U)
14710
14714 #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
14715 #define DMA_HRS_HRS28_MASK (0x10000000U)
14716 #define DMA_HRS_HRS28_SHIFT (28U)
14717
14721 #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
14722 #define DMA_HRS_HRS29_MASK (0x20000000U)
14723 #define DMA_HRS_HRS29_SHIFT (29U)
14724
14728 #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
14729 #define DMA_HRS_HRS30_MASK (0x40000000U)
14730 #define DMA_HRS_HRS30_SHIFT (30U)
14731
14735 #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
14736 #define DMA_HRS_HRS31_MASK (0x80000000U)
14737 #define DMA_HRS_HRS31_SHIFT (31U)
14738
14742 #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
14743
14747 #define DMA_EARS_EDREQ_0_MASK (0x1U)
14748 #define DMA_EARS_EDREQ_0_SHIFT (0U)
14749
14753 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
14754 #define DMA_EARS_EDREQ_1_MASK (0x2U)
14755 #define DMA_EARS_EDREQ_1_SHIFT (1U)
14756
14760 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
14761 #define DMA_EARS_EDREQ_2_MASK (0x4U)
14762 #define DMA_EARS_EDREQ_2_SHIFT (2U)
14763
14767 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
14768 #define DMA_EARS_EDREQ_3_MASK (0x8U)
14769 #define DMA_EARS_EDREQ_3_SHIFT (3U)
14770
14774 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
14775 #define DMA_EARS_EDREQ_4_MASK (0x10U)
14776 #define DMA_EARS_EDREQ_4_SHIFT (4U)
14777
14781 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
14782 #define DMA_EARS_EDREQ_5_MASK (0x20U)
14783 #define DMA_EARS_EDREQ_5_SHIFT (5U)
14784
14788 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
14789 #define DMA_EARS_EDREQ_6_MASK (0x40U)
14790 #define DMA_EARS_EDREQ_6_SHIFT (6U)
14791
14795 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
14796 #define DMA_EARS_EDREQ_7_MASK (0x80U)
14797 #define DMA_EARS_EDREQ_7_SHIFT (7U)
14798
14802 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
14803 #define DMA_EARS_EDREQ_8_MASK (0x100U)
14804 #define DMA_EARS_EDREQ_8_SHIFT (8U)
14805
14809 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
14810 #define DMA_EARS_EDREQ_9_MASK (0x200U)
14811 #define DMA_EARS_EDREQ_9_SHIFT (9U)
14812
14816 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
14817 #define DMA_EARS_EDREQ_10_MASK (0x400U)
14818 #define DMA_EARS_EDREQ_10_SHIFT (10U)
14819
14823 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
14824 #define DMA_EARS_EDREQ_11_MASK (0x800U)
14825 #define DMA_EARS_EDREQ_11_SHIFT (11U)
14826
14830 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
14831 #define DMA_EARS_EDREQ_12_MASK (0x1000U)
14832 #define DMA_EARS_EDREQ_12_SHIFT (12U)
14833
14837 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
14838 #define DMA_EARS_EDREQ_13_MASK (0x2000U)
14839 #define DMA_EARS_EDREQ_13_SHIFT (13U)
14840
14844 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
14845 #define DMA_EARS_EDREQ_14_MASK (0x4000U)
14846 #define DMA_EARS_EDREQ_14_SHIFT (14U)
14847
14851 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
14852 #define DMA_EARS_EDREQ_15_MASK (0x8000U)
14853 #define DMA_EARS_EDREQ_15_SHIFT (15U)
14854
14858 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
14859 #define DMA_EARS_EDREQ_16_MASK (0x10000U)
14860 #define DMA_EARS_EDREQ_16_SHIFT (16U)
14861
14865 #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
14866 #define DMA_EARS_EDREQ_17_MASK (0x20000U)
14867 #define DMA_EARS_EDREQ_17_SHIFT (17U)
14868
14872 #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
14873 #define DMA_EARS_EDREQ_18_MASK (0x40000U)
14874 #define DMA_EARS_EDREQ_18_SHIFT (18U)
14875
14879 #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
14880 #define DMA_EARS_EDREQ_19_MASK (0x80000U)
14881 #define DMA_EARS_EDREQ_19_SHIFT (19U)
14882
14886 #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
14887 #define DMA_EARS_EDREQ_20_MASK (0x100000U)
14888 #define DMA_EARS_EDREQ_20_SHIFT (20U)
14889
14893 #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
14894 #define DMA_EARS_EDREQ_21_MASK (0x200000U)
14895 #define DMA_EARS_EDREQ_21_SHIFT (21U)
14896
14900 #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
14901 #define DMA_EARS_EDREQ_22_MASK (0x400000U)
14902 #define DMA_EARS_EDREQ_22_SHIFT (22U)
14903
14907 #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
14908 #define DMA_EARS_EDREQ_23_MASK (0x800000U)
14909 #define DMA_EARS_EDREQ_23_SHIFT (23U)
14910
14914 #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
14915 #define DMA_EARS_EDREQ_24_MASK (0x1000000U)
14916 #define DMA_EARS_EDREQ_24_SHIFT (24U)
14917
14921 #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
14922 #define DMA_EARS_EDREQ_25_MASK (0x2000000U)
14923 #define DMA_EARS_EDREQ_25_SHIFT (25U)
14924
14928 #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
14929 #define DMA_EARS_EDREQ_26_MASK (0x4000000U)
14930 #define DMA_EARS_EDREQ_26_SHIFT (26U)
14931
14935 #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
14936 #define DMA_EARS_EDREQ_27_MASK (0x8000000U)
14937 #define DMA_EARS_EDREQ_27_SHIFT (27U)
14938
14942 #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
14943 #define DMA_EARS_EDREQ_28_MASK (0x10000000U)
14944 #define DMA_EARS_EDREQ_28_SHIFT (28U)
14945
14949 #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
14950 #define DMA_EARS_EDREQ_29_MASK (0x20000000U)
14951 #define DMA_EARS_EDREQ_29_SHIFT (29U)
14952
14956 #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
14957 #define DMA_EARS_EDREQ_30_MASK (0x40000000U)
14958 #define DMA_EARS_EDREQ_30_SHIFT (30U)
14959
14963 #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
14964 #define DMA_EARS_EDREQ_31_MASK (0x80000000U)
14965 #define DMA_EARS_EDREQ_31_SHIFT (31U)
14966
14970 #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
14971
14975 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
14976 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
14977
14979 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
14980 #define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
14981 #define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
14982
14984 #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
14985 #define DMA_DCHPRI3_DPA_MASK (0x40U)
14986 #define DMA_DCHPRI3_DPA_SHIFT (6U)
14987
14991 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
14992 #define DMA_DCHPRI3_ECP_MASK (0x80U)
14993 #define DMA_DCHPRI3_ECP_SHIFT (7U)
14994
14998 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
14999
15003 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
15004 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
15005
15007 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
15008 #define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
15009 #define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
15010
15012 #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
15013 #define DMA_DCHPRI2_DPA_MASK (0x40U)
15014 #define DMA_DCHPRI2_DPA_SHIFT (6U)
15015
15019 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
15020 #define DMA_DCHPRI2_ECP_MASK (0x80U)
15021 #define DMA_DCHPRI2_ECP_SHIFT (7U)
15022
15026 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
15027
15031 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
15032 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
15033
15035 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
15036 #define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
15037 #define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
15038
15040 #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
15041 #define DMA_DCHPRI1_DPA_MASK (0x40U)
15042 #define DMA_DCHPRI1_DPA_SHIFT (6U)
15043
15047 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
15048 #define DMA_DCHPRI1_ECP_MASK (0x80U)
15049 #define DMA_DCHPRI1_ECP_SHIFT (7U)
15050
15054 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
15055
15059 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
15060 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
15061
15063 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
15064 #define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
15065 #define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
15066
15068 #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
15069 #define DMA_DCHPRI0_DPA_MASK (0x40U)
15070 #define DMA_DCHPRI0_DPA_SHIFT (6U)
15071
15075 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
15076 #define DMA_DCHPRI0_ECP_MASK (0x80U)
15077 #define DMA_DCHPRI0_ECP_SHIFT (7U)
15078
15082 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
15083
15087 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
15088 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
15089
15091 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
15092 #define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
15093 #define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
15094
15096 #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
15097 #define DMA_DCHPRI7_DPA_MASK (0x40U)
15098 #define DMA_DCHPRI7_DPA_SHIFT (6U)
15099
15103 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
15104 #define DMA_DCHPRI7_ECP_MASK (0x80U)
15105 #define DMA_DCHPRI7_ECP_SHIFT (7U)
15106
15110 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
15111
15115 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
15116 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
15117
15119 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
15120 #define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
15121 #define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
15122
15124 #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
15125 #define DMA_DCHPRI6_DPA_MASK (0x40U)
15126 #define DMA_DCHPRI6_DPA_SHIFT (6U)
15127
15131 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
15132 #define DMA_DCHPRI6_ECP_MASK (0x80U)
15133 #define DMA_DCHPRI6_ECP_SHIFT (7U)
15134
15138 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
15139
15143 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
15144 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
15145
15147 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
15148 #define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
15149 #define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
15150
15152 #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
15153 #define DMA_DCHPRI5_DPA_MASK (0x40U)
15154 #define DMA_DCHPRI5_DPA_SHIFT (6U)
15155
15159 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
15160 #define DMA_DCHPRI5_ECP_MASK (0x80U)
15161 #define DMA_DCHPRI5_ECP_SHIFT (7U)
15162
15166 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
15167
15171 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
15172 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
15173
15175 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
15176 #define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
15177 #define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
15178
15180 #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
15181 #define DMA_DCHPRI4_DPA_MASK (0x40U)
15182 #define DMA_DCHPRI4_DPA_SHIFT (6U)
15183
15187 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
15188 #define DMA_DCHPRI4_ECP_MASK (0x80U)
15189 #define DMA_DCHPRI4_ECP_SHIFT (7U)
15190
15194 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
15195
15199 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
15200 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
15201
15203 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
15204 #define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
15205 #define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
15206
15208 #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
15209 #define DMA_DCHPRI11_DPA_MASK (0x40U)
15210 #define DMA_DCHPRI11_DPA_SHIFT (6U)
15211
15215 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
15216 #define DMA_DCHPRI11_ECP_MASK (0x80U)
15217 #define DMA_DCHPRI11_ECP_SHIFT (7U)
15218
15222 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
15223
15227 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
15228 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
15229
15231 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
15232 #define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
15233 #define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
15234
15236 #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
15237 #define DMA_DCHPRI10_DPA_MASK (0x40U)
15238 #define DMA_DCHPRI10_DPA_SHIFT (6U)
15239
15243 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
15244 #define DMA_DCHPRI10_ECP_MASK (0x80U)
15245 #define DMA_DCHPRI10_ECP_SHIFT (7U)
15246
15250 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
15251
15255 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
15256 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
15257
15259 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
15260 #define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
15261 #define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
15262
15264 #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
15265 #define DMA_DCHPRI9_DPA_MASK (0x40U)
15266 #define DMA_DCHPRI9_DPA_SHIFT (6U)
15267
15271 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
15272 #define DMA_DCHPRI9_ECP_MASK (0x80U)
15273 #define DMA_DCHPRI9_ECP_SHIFT (7U)
15274
15278 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
15279
15283 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
15284 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
15285
15287 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
15288 #define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
15289 #define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
15290
15292 #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
15293 #define DMA_DCHPRI8_DPA_MASK (0x40U)
15294 #define DMA_DCHPRI8_DPA_SHIFT (6U)
15295
15299 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
15300 #define DMA_DCHPRI8_ECP_MASK (0x80U)
15301 #define DMA_DCHPRI8_ECP_SHIFT (7U)
15302
15306 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
15307
15311 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
15312 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
15313
15315 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
15316 #define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
15317 #define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
15318
15320 #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
15321 #define DMA_DCHPRI15_DPA_MASK (0x40U)
15322 #define DMA_DCHPRI15_DPA_SHIFT (6U)
15323
15327 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
15328 #define DMA_DCHPRI15_ECP_MASK (0x80U)
15329 #define DMA_DCHPRI15_ECP_SHIFT (7U)
15330
15334 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
15335
15339 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
15340 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
15341
15343 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
15344 #define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
15345 #define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
15346
15348 #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
15349 #define DMA_DCHPRI14_DPA_MASK (0x40U)
15350 #define DMA_DCHPRI14_DPA_SHIFT (6U)
15351
15355 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
15356 #define DMA_DCHPRI14_ECP_MASK (0x80U)
15357 #define DMA_DCHPRI14_ECP_SHIFT (7U)
15358
15362 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
15363
15367 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
15368 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
15369
15371 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
15372 #define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
15373 #define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
15374
15376 #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
15377 #define DMA_DCHPRI13_DPA_MASK (0x40U)
15378 #define DMA_DCHPRI13_DPA_SHIFT (6U)
15379
15383 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
15384 #define DMA_DCHPRI13_ECP_MASK (0x80U)
15385 #define DMA_DCHPRI13_ECP_SHIFT (7U)
15386
15390 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
15391
15395 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
15396 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
15397
15399 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
15400 #define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
15401 #define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
15402
15404 #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
15405 #define DMA_DCHPRI12_DPA_MASK (0x40U)
15406 #define DMA_DCHPRI12_DPA_SHIFT (6U)
15407
15411 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
15412 #define DMA_DCHPRI12_ECP_MASK (0x80U)
15413 #define DMA_DCHPRI12_ECP_SHIFT (7U)
15414
15418 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
15419
15423 #define DMA_DCHPRI19_CHPRI_MASK (0xFU)
15424 #define DMA_DCHPRI19_CHPRI_SHIFT (0U)
15425
15427 #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
15428 #define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
15429 #define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
15430
15432 #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
15433 #define DMA_DCHPRI19_DPA_MASK (0x40U)
15434 #define DMA_DCHPRI19_DPA_SHIFT (6U)
15435
15439 #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
15440 #define DMA_DCHPRI19_ECP_MASK (0x80U)
15441 #define DMA_DCHPRI19_ECP_SHIFT (7U)
15442
15446 #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
15447
15451 #define DMA_DCHPRI18_CHPRI_MASK (0xFU)
15452 #define DMA_DCHPRI18_CHPRI_SHIFT (0U)
15453
15455 #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
15456 #define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
15457 #define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
15458
15460 #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
15461 #define DMA_DCHPRI18_DPA_MASK (0x40U)
15462 #define DMA_DCHPRI18_DPA_SHIFT (6U)
15463
15467 #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
15468 #define DMA_DCHPRI18_ECP_MASK (0x80U)
15469 #define DMA_DCHPRI18_ECP_SHIFT (7U)
15470
15474 #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
15475
15479 #define DMA_DCHPRI17_CHPRI_MASK (0xFU)
15480 #define DMA_DCHPRI17_CHPRI_SHIFT (0U)
15481
15483 #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
15484 #define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
15485 #define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
15486
15488 #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
15489 #define DMA_DCHPRI17_DPA_MASK (0x40U)
15490 #define DMA_DCHPRI17_DPA_SHIFT (6U)
15491
15495 #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
15496 #define DMA_DCHPRI17_ECP_MASK (0x80U)
15497 #define DMA_DCHPRI17_ECP_SHIFT (7U)
15498
15502 #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
15503
15507 #define DMA_DCHPRI16_CHPRI_MASK (0xFU)
15508 #define DMA_DCHPRI16_CHPRI_SHIFT (0U)
15509
15511 #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
15512 #define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
15513 #define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
15514
15516 #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
15517 #define DMA_DCHPRI16_DPA_MASK (0x40U)
15518 #define DMA_DCHPRI16_DPA_SHIFT (6U)
15519
15523 #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
15524 #define DMA_DCHPRI16_ECP_MASK (0x80U)
15525 #define DMA_DCHPRI16_ECP_SHIFT (7U)
15526
15530 #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
15531
15535 #define DMA_DCHPRI23_CHPRI_MASK (0xFU)
15536 #define DMA_DCHPRI23_CHPRI_SHIFT (0U)
15537
15539 #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
15540 #define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
15541 #define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
15542
15544 #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
15545 #define DMA_DCHPRI23_DPA_MASK (0x40U)
15546 #define DMA_DCHPRI23_DPA_SHIFT (6U)
15547
15551 #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
15552 #define DMA_DCHPRI23_ECP_MASK (0x80U)
15553 #define DMA_DCHPRI23_ECP_SHIFT (7U)
15554
15558 #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
15559
15563 #define DMA_DCHPRI22_CHPRI_MASK (0xFU)
15564 #define DMA_DCHPRI22_CHPRI_SHIFT (0U)
15565
15567 #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
15568 #define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
15569 #define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
15570
15572 #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
15573 #define DMA_DCHPRI22_DPA_MASK (0x40U)
15574 #define DMA_DCHPRI22_DPA_SHIFT (6U)
15575
15579 #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
15580 #define DMA_DCHPRI22_ECP_MASK (0x80U)
15581 #define DMA_DCHPRI22_ECP_SHIFT (7U)
15582
15586 #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
15587
15591 #define DMA_DCHPRI21_CHPRI_MASK (0xFU)
15592 #define DMA_DCHPRI21_CHPRI_SHIFT (0U)
15593
15595 #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
15596 #define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
15597 #define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
15598
15600 #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
15601 #define DMA_DCHPRI21_DPA_MASK (0x40U)
15602 #define DMA_DCHPRI21_DPA_SHIFT (6U)
15603
15607 #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
15608 #define DMA_DCHPRI21_ECP_MASK (0x80U)
15609 #define DMA_DCHPRI21_ECP_SHIFT (7U)
15610
15614 #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
15615
15619 #define DMA_DCHPRI20_CHPRI_MASK (0xFU)
15620 #define DMA_DCHPRI20_CHPRI_SHIFT (0U)
15621
15623 #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
15624 #define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
15625 #define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
15626
15628 #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
15629 #define DMA_DCHPRI20_DPA_MASK (0x40U)
15630 #define DMA_DCHPRI20_DPA_SHIFT (6U)
15631
15635 #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
15636 #define DMA_DCHPRI20_ECP_MASK (0x80U)
15637 #define DMA_DCHPRI20_ECP_SHIFT (7U)
15638
15642 #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
15643
15647 #define DMA_DCHPRI27_CHPRI_MASK (0xFU)
15648 #define DMA_DCHPRI27_CHPRI_SHIFT (0U)
15649
15651 #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
15652 #define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
15653 #define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
15654
15656 #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
15657 #define DMA_DCHPRI27_DPA_MASK (0x40U)
15658 #define DMA_DCHPRI27_DPA_SHIFT (6U)
15659
15663 #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
15664 #define DMA_DCHPRI27_ECP_MASK (0x80U)
15665 #define DMA_DCHPRI27_ECP_SHIFT (7U)
15666
15670 #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
15671
15675 #define DMA_DCHPRI26_CHPRI_MASK (0xFU)
15676 #define DMA_DCHPRI26_CHPRI_SHIFT (0U)
15677
15679 #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
15680 #define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
15681 #define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
15682
15684 #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
15685 #define DMA_DCHPRI26_DPA_MASK (0x40U)
15686 #define DMA_DCHPRI26_DPA_SHIFT (6U)
15687
15691 #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
15692 #define DMA_DCHPRI26_ECP_MASK (0x80U)
15693 #define DMA_DCHPRI26_ECP_SHIFT (7U)
15694
15698 #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
15699
15703 #define DMA_DCHPRI25_CHPRI_MASK (0xFU)
15704 #define DMA_DCHPRI25_CHPRI_SHIFT (0U)
15705
15707 #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
15708 #define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
15709 #define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
15710
15712 #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
15713 #define DMA_DCHPRI25_DPA_MASK (0x40U)
15714 #define DMA_DCHPRI25_DPA_SHIFT (6U)
15715
15719 #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
15720 #define DMA_DCHPRI25_ECP_MASK (0x80U)
15721 #define DMA_DCHPRI25_ECP_SHIFT (7U)
15722
15726 #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
15727
15731 #define DMA_DCHPRI24_CHPRI_MASK (0xFU)
15732 #define DMA_DCHPRI24_CHPRI_SHIFT (0U)
15733
15735 #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
15736 #define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
15737 #define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
15738
15740 #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
15741 #define DMA_DCHPRI24_DPA_MASK (0x40U)
15742 #define DMA_DCHPRI24_DPA_SHIFT (6U)
15743
15747 #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
15748 #define DMA_DCHPRI24_ECP_MASK (0x80U)
15749 #define DMA_DCHPRI24_ECP_SHIFT (7U)
15750
15754 #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
15755
15759 #define DMA_DCHPRI31_CHPRI_MASK (0xFU)
15760 #define DMA_DCHPRI31_CHPRI_SHIFT (0U)
15761
15763 #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
15764 #define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
15765 #define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
15766
15768 #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
15769 #define DMA_DCHPRI31_DPA_MASK (0x40U)
15770 #define DMA_DCHPRI31_DPA_SHIFT (6U)
15771
15775 #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
15776 #define DMA_DCHPRI31_ECP_MASK (0x80U)
15777 #define DMA_DCHPRI31_ECP_SHIFT (7U)
15778
15782 #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
15783
15787 #define DMA_DCHPRI30_CHPRI_MASK (0xFU)
15788 #define DMA_DCHPRI30_CHPRI_SHIFT (0U)
15789
15791 #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
15792 #define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
15793 #define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
15794
15796 #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
15797 #define DMA_DCHPRI30_DPA_MASK (0x40U)
15798 #define DMA_DCHPRI30_DPA_SHIFT (6U)
15799
15803 #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
15804 #define DMA_DCHPRI30_ECP_MASK (0x80U)
15805 #define DMA_DCHPRI30_ECP_SHIFT (7U)
15806
15810 #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
15811
15815 #define DMA_DCHPRI29_CHPRI_MASK (0xFU)
15816 #define DMA_DCHPRI29_CHPRI_SHIFT (0U)
15817
15819 #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
15820 #define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
15821 #define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
15822
15824 #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
15825 #define DMA_DCHPRI29_DPA_MASK (0x40U)
15826 #define DMA_DCHPRI29_DPA_SHIFT (6U)
15827
15831 #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
15832 #define DMA_DCHPRI29_ECP_MASK (0x80U)
15833 #define DMA_DCHPRI29_ECP_SHIFT (7U)
15834
15838 #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
15839
15843 #define DMA_DCHPRI28_CHPRI_MASK (0xFU)
15844 #define DMA_DCHPRI28_CHPRI_SHIFT (0U)
15845
15847 #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
15848 #define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
15849 #define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
15850
15852 #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
15853 #define DMA_DCHPRI28_DPA_MASK (0x40U)
15854 #define DMA_DCHPRI28_DPA_SHIFT (6U)
15855
15859 #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
15860 #define DMA_DCHPRI28_ECP_MASK (0x80U)
15861 #define DMA_DCHPRI28_ECP_SHIFT (7U)
15862
15866 #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
15867
15871 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
15872 #define DMA_SADDR_SADDR_SHIFT (0U)
15873
15875 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
15876
15878 /* The count of DMA_SADDR */
15879 #define DMA_SADDR_COUNT (32U)
15880
15883 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
15884 #define DMA_SOFF_SOFF_SHIFT (0U)
15885
15887 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
15888
15890 /* The count of DMA_SOFF */
15891 #define DMA_SOFF_COUNT (32U)
15892
15895 #define DMA_ATTR_DSIZE_MASK (0x7U)
15896 #define DMA_ATTR_DSIZE_SHIFT (0U)
15897
15899 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
15900 #define DMA_ATTR_DMOD_MASK (0xF8U)
15901 #define DMA_ATTR_DMOD_SHIFT (3U)
15902
15904 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
15905 #define DMA_ATTR_SSIZE_MASK (0x700U)
15906 #define DMA_ATTR_SSIZE_SHIFT (8U)
15907
15917 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
15918 #define DMA_ATTR_SMOD_MASK (0xF800U)
15919 #define DMA_ATTR_SMOD_SHIFT (11U)
15920
15931 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
15932
15934 /* The count of DMA_ATTR */
15935 #define DMA_ATTR_COUNT (32U)
15936
15939 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
15940 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
15941
15943 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
15944
15946 /* The count of DMA_NBYTES_MLNO */
15947 #define DMA_NBYTES_MLNO_COUNT (32U)
15948
15951 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
15952 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
15953
15955 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
15956 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
15957 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
15958
15962 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
15963 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
15964 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
15965
15969 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
15970
15972 /* The count of DMA_NBYTES_MLOFFNO */
15973 #define DMA_NBYTES_MLOFFNO_COUNT (32U)
15974
15977 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
15978 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
15979
15981 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
15982 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
15983 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
15984
15987 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
15988 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
15989 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
15990
15994 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
15995 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
15996 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
15997
16001 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
16002
16004 /* The count of DMA_NBYTES_MLOFFYES */
16005 #define DMA_NBYTES_MLOFFYES_COUNT (32U)
16006
16009 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
16010 #define DMA_SLAST_SLAST_SHIFT (0U)
16011
16013 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
16014
16016 /* The count of DMA_SLAST */
16017 #define DMA_SLAST_COUNT (32U)
16018
16021 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
16022 #define DMA_DADDR_DADDR_SHIFT (0U)
16023
16025 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
16026
16028 /* The count of DMA_DADDR */
16029 #define DMA_DADDR_COUNT (32U)
16030
16033 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
16034 #define DMA_DOFF_DOFF_SHIFT (0U)
16035
16037 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
16038
16040 /* The count of DMA_DOFF */
16041 #define DMA_DOFF_COUNT (32U)
16042
16045 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
16046 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
16047
16049 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
16050 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
16051 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
16052
16056 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
16057
16059 /* The count of DMA_CITER_ELINKNO */
16060 #define DMA_CITER_ELINKNO_COUNT (32U)
16061
16064 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
16065 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
16066
16068 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
16069 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
16070 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
16071
16073 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
16074 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
16075 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
16076
16080 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
16081
16083 /* The count of DMA_CITER_ELINKYES */
16084 #define DMA_CITER_ELINKYES_COUNT (32U)
16085
16088 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
16089 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
16090
16092 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
16093
16095 /* The count of DMA_DLAST_SGA */
16096 #define DMA_DLAST_SGA_COUNT (32U)
16097
16100 #define DMA_CSR_START_MASK (0x1U)
16101 #define DMA_CSR_START_SHIFT (0U)
16102
16106 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
16107 #define DMA_CSR_INTMAJOR_MASK (0x2U)
16108 #define DMA_CSR_INTMAJOR_SHIFT (1U)
16109
16113 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
16114 #define DMA_CSR_INTHALF_MASK (0x4U)
16115 #define DMA_CSR_INTHALF_SHIFT (2U)
16116
16120 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
16121 #define DMA_CSR_DREQ_MASK (0x8U)
16122 #define DMA_CSR_DREQ_SHIFT (3U)
16123
16127 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
16128 #define DMA_CSR_ESG_MASK (0x10U)
16129 #define DMA_CSR_ESG_SHIFT (4U)
16130
16135 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
16136 #define DMA_CSR_MAJORELINK_MASK (0x20U)
16137 #define DMA_CSR_MAJORELINK_SHIFT (5U)
16138
16142 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
16143 #define DMA_CSR_ACTIVE_MASK (0x40U)
16144 #define DMA_CSR_ACTIVE_SHIFT (6U)
16145
16147 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
16148 #define DMA_CSR_DONE_MASK (0x80U)
16149 #define DMA_CSR_DONE_SHIFT (7U)
16150
16152 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
16153 #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
16154 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
16155
16157 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
16158 #define DMA_CSR_BWC_MASK (0xC000U)
16159 #define DMA_CSR_BWC_SHIFT (14U)
16160
16166 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
16167
16169 /* The count of DMA_CSR */
16170 #define DMA_CSR_COUNT (32U)
16171
16174 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
16175 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
16176
16178 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
16179 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
16180 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
16181
16185 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
16186
16188 /* The count of DMA_BITER_ELINKNO */
16189 #define DMA_BITER_ELINKNO_COUNT (32U)
16190
16193 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
16194 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
16195
16197 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
16198 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
16199 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
16200
16202 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
16203 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
16204 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
16205
16209 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
16210
16212 /* The count of DMA_BITER_ELINKYES */
16213 #define DMA_BITER_ELINKYES_COUNT (32U)
16214
16215 /* end of group DMA_Register_Masks */
16219
16220
16221 /* DMA - Peripheral instance base addresses */
16223 #define DMA0_BASE (0x400E8000u)
16224
16225 #define DMA0 ((DMA_Type *)DMA0_BASE)
16226
16227 #define DMA_BASE_ADDRS { DMA0_BASE }
16228
16229 #define DMA_BASE_PTRS { DMA0 }
16230
16231 #define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
16232 #define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
16233 /* end of group DMA_Peripheral_Access_Layer */
16237
16238
16239 /* ----------------------------------------------------------------------------
16240 -- DMAMUX Peripheral Access Layer
16241 ---------------------------------------------------------------------------- */
16242
16249 typedef struct {
16250 __IO uint32_t CHCFG[32];
16251 } DMAMUX_Type;
16252
16253 /* ----------------------------------------------------------------------------
16254 -- DMAMUX Register Masks
16255 ---------------------------------------------------------------------------- */
16256
16264 #define DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
16265 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
16266
16268 #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
16269 #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
16270 #define DMAMUX_CHCFG_A_ON_SHIFT (29U)
16271
16275 #define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
16276 #define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
16277 #define DMAMUX_CHCFG_TRIG_SHIFT (30U)
16278
16283 #define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
16284 #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
16285 #define DMAMUX_CHCFG_ENBL_SHIFT (31U)
16286
16290 #define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
16291
16293 /* The count of DMAMUX_CHCFG */
16294 #define DMAMUX_CHCFG_COUNT (32U)
16295
16296 /* end of group DMAMUX_Register_Masks */
16300
16301
16302 /* DMAMUX - Peripheral instance base addresses */
16304 #define DMAMUX_BASE (0x400EC000u)
16305
16306 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
16307
16308 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
16309
16310 #define DMAMUX_BASE_PTRS { DMAMUX }
16311 /* end of group DMAMUX_Peripheral_Access_Layer */
16315
16316
16317 /* ----------------------------------------------------------------------------
16318 -- ENC Peripheral Access Layer
16319 ---------------------------------------------------------------------------- */
16320
16327 typedef struct {
16328 __IO uint16_t CTRL;
16329 __IO uint16_t FILT;
16330 __IO uint16_t WTR;
16331 __IO uint16_t POSD;
16332 __I uint16_t POSDH;
16333 __IO uint16_t REV;
16334 __I uint16_t REVH;
16335 __IO uint16_t UPOS;
16336 __IO uint16_t LPOS;
16337 __I uint16_t UPOSH;
16338 __I uint16_t LPOSH;
16339 __IO uint16_t UINIT;
16340 __IO uint16_t LINIT;
16341 __I uint16_t IMR;
16342 __IO uint16_t TST;
16343 __IO uint16_t CTRL2;
16344 __IO uint16_t UMOD;
16345 __IO uint16_t LMOD;
16346 __IO uint16_t UCOMP;
16347 __IO uint16_t LCOMP;
16348 } ENC_Type;
16349
16350 /* ----------------------------------------------------------------------------
16351 -- ENC Register Masks
16352 ---------------------------------------------------------------------------- */
16353
16361 #define ENC_CTRL_CMPIE_MASK (0x1U)
16362 #define ENC_CTRL_CMPIE_SHIFT (0U)
16363
16367 #define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
16368 #define ENC_CTRL_CMPIRQ_MASK (0x2U)
16369 #define ENC_CTRL_CMPIRQ_SHIFT (1U)
16370
16374 #define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
16375 #define ENC_CTRL_WDE_MASK (0x4U)
16376 #define ENC_CTRL_WDE_SHIFT (2U)
16377
16381 #define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
16382 #define ENC_CTRL_DIE_MASK (0x8U)
16383 #define ENC_CTRL_DIE_SHIFT (3U)
16384
16388 #define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
16389 #define ENC_CTRL_DIRQ_MASK (0x10U)
16390 #define ENC_CTRL_DIRQ_SHIFT (4U)
16391
16395 #define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
16396 #define ENC_CTRL_XNE_MASK (0x20U)
16397 #define ENC_CTRL_XNE_SHIFT (5U)
16398
16402 #define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
16403 #define ENC_CTRL_XIP_MASK (0x40U)
16404 #define ENC_CTRL_XIP_SHIFT (6U)
16405
16409 #define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
16410 #define ENC_CTRL_XIE_MASK (0x80U)
16411 #define ENC_CTRL_XIE_SHIFT (7U)
16412
16416 #define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
16417 #define ENC_CTRL_XIRQ_MASK (0x100U)
16418 #define ENC_CTRL_XIRQ_SHIFT (8U)
16419
16423 #define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
16424 #define ENC_CTRL_PH1_MASK (0x200U)
16425 #define ENC_CTRL_PH1_SHIFT (9U)
16426
16433 #define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
16434 #define ENC_CTRL_REV_MASK (0x400U)
16435 #define ENC_CTRL_REV_SHIFT (10U)
16436
16440 #define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
16441 #define ENC_CTRL_SWIP_MASK (0x800U)
16442 #define ENC_CTRL_SWIP_SHIFT (11U)
16443
16447 #define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
16448 #define ENC_CTRL_HNE_MASK (0x1000U)
16449 #define ENC_CTRL_HNE_SHIFT (12U)
16450
16454 #define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
16455 #define ENC_CTRL_HIP_MASK (0x2000U)
16456 #define ENC_CTRL_HIP_SHIFT (13U)
16457
16461 #define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
16462 #define ENC_CTRL_HIE_MASK (0x4000U)
16463 #define ENC_CTRL_HIE_SHIFT (14U)
16464
16468 #define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
16469 #define ENC_CTRL_HIRQ_MASK (0x8000U)
16470 #define ENC_CTRL_HIRQ_SHIFT (15U)
16471
16475 #define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
16476
16480 #define ENC_FILT_FILT_PER_MASK (0xFFU)
16481 #define ENC_FILT_FILT_PER_SHIFT (0U)
16482
16484 #define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
16485 #define ENC_FILT_FILT_CNT_MASK (0x700U)
16486 #define ENC_FILT_FILT_CNT_SHIFT (8U)
16487
16489 #define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
16490
16494 #define ENC_WTR_WDOG_MASK (0xFFFFU)
16495 #define ENC_WTR_WDOG_SHIFT (0U)
16496 #define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
16497
16501 #define ENC_POSD_POSD_MASK (0xFFFFU)
16502 #define ENC_POSD_POSD_SHIFT (0U)
16503 #define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
16504
16508 #define ENC_POSDH_POSDH_MASK (0xFFFFU)
16509 #define ENC_POSDH_POSDH_SHIFT (0U)
16510 #define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
16511
16515 #define ENC_REV_REV_MASK (0xFFFFU)
16516 #define ENC_REV_REV_SHIFT (0U)
16517 #define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
16518
16522 #define ENC_REVH_REVH_MASK (0xFFFFU)
16523 #define ENC_REVH_REVH_SHIFT (0U)
16524 #define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
16525
16529 #define ENC_UPOS_POS_MASK (0xFFFFU)
16530 #define ENC_UPOS_POS_SHIFT (0U)
16531 #define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
16532
16536 #define ENC_LPOS_POS_MASK (0xFFFFU)
16537 #define ENC_LPOS_POS_SHIFT (0U)
16538 #define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
16539
16543 #define ENC_UPOSH_POSH_MASK (0xFFFFU)
16544 #define ENC_UPOSH_POSH_SHIFT (0U)
16545 #define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
16546
16550 #define ENC_LPOSH_POSH_MASK (0xFFFFU)
16551 #define ENC_LPOSH_POSH_SHIFT (0U)
16552 #define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
16553
16557 #define ENC_UINIT_INIT_MASK (0xFFFFU)
16558 #define ENC_UINIT_INIT_SHIFT (0U)
16559 #define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
16560
16564 #define ENC_LINIT_INIT_MASK (0xFFFFU)
16565 #define ENC_LINIT_INIT_SHIFT (0U)
16566 #define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
16567
16571 #define ENC_IMR_HOME_MASK (0x1U)
16572 #define ENC_IMR_HOME_SHIFT (0U)
16573 #define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
16574 #define ENC_IMR_INDEX_MASK (0x2U)
16575 #define ENC_IMR_INDEX_SHIFT (1U)
16576 #define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
16577 #define ENC_IMR_PHB_MASK (0x4U)
16578 #define ENC_IMR_PHB_SHIFT (2U)
16579 #define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
16580 #define ENC_IMR_PHA_MASK (0x8U)
16581 #define ENC_IMR_PHA_SHIFT (3U)
16582 #define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
16583 #define ENC_IMR_FHOM_MASK (0x10U)
16584 #define ENC_IMR_FHOM_SHIFT (4U)
16585 #define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
16586 #define ENC_IMR_FIND_MASK (0x20U)
16587 #define ENC_IMR_FIND_SHIFT (5U)
16588 #define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
16589 #define ENC_IMR_FPHB_MASK (0x40U)
16590 #define ENC_IMR_FPHB_SHIFT (6U)
16591 #define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
16592 #define ENC_IMR_FPHA_MASK (0x80U)
16593 #define ENC_IMR_FPHA_SHIFT (7U)
16594 #define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
16595
16599 #define ENC_TST_TEST_COUNT_MASK (0xFFU)
16600 #define ENC_TST_TEST_COUNT_SHIFT (0U)
16601 #define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
16602 #define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
16603 #define ENC_TST_TEST_PERIOD_SHIFT (8U)
16604 #define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
16605 #define ENC_TST_QDN_MASK (0x2000U)
16606 #define ENC_TST_QDN_SHIFT (13U)
16607
16611 #define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
16612 #define ENC_TST_TCE_MASK (0x4000U)
16613 #define ENC_TST_TCE_SHIFT (14U)
16614
16618 #define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
16619 #define ENC_TST_TEN_MASK (0x8000U)
16620 #define ENC_TST_TEN_SHIFT (15U)
16621
16625 #define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
16626
16630 #define ENC_CTRL2_UPDHLD_MASK (0x1U)
16631 #define ENC_CTRL2_UPDHLD_SHIFT (0U)
16632
16636 #define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
16637 #define ENC_CTRL2_UPDPOS_MASK (0x2U)
16638 #define ENC_CTRL2_UPDPOS_SHIFT (1U)
16639
16643 #define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
16644 #define ENC_CTRL2_MOD_MASK (0x4U)
16645 #define ENC_CTRL2_MOD_SHIFT (2U)
16646
16650 #define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
16651 #define ENC_CTRL2_DIR_MASK (0x8U)
16652 #define ENC_CTRL2_DIR_SHIFT (3U)
16653
16657 #define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
16658 #define ENC_CTRL2_RUIE_MASK (0x10U)
16659 #define ENC_CTRL2_RUIE_SHIFT (4U)
16660
16664 #define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
16665 #define ENC_CTRL2_RUIRQ_MASK (0x20U)
16666 #define ENC_CTRL2_RUIRQ_SHIFT (5U)
16667
16671 #define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
16672 #define ENC_CTRL2_ROIE_MASK (0x40U)
16673 #define ENC_CTRL2_ROIE_SHIFT (6U)
16674
16678 #define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
16679 #define ENC_CTRL2_ROIRQ_MASK (0x80U)
16680 #define ENC_CTRL2_ROIRQ_SHIFT (7U)
16681
16685 #define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
16686 #define ENC_CTRL2_REVMOD_MASK (0x100U)
16687 #define ENC_CTRL2_REVMOD_SHIFT (8U)
16688
16692 #define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
16693 #define ENC_CTRL2_OUTCTL_MASK (0x200U)
16694 #define ENC_CTRL2_OUTCTL_SHIFT (9U)
16695
16699 #define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
16700 #define ENC_CTRL2_SABIE_MASK (0x400U)
16701 #define ENC_CTRL2_SABIE_SHIFT (10U)
16702
16706 #define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
16707 #define ENC_CTRL2_SABIRQ_MASK (0x800U)
16708 #define ENC_CTRL2_SABIRQ_SHIFT (11U)
16709
16713 #define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
16714
16718 #define ENC_UMOD_MOD_MASK (0xFFFFU)
16719 #define ENC_UMOD_MOD_SHIFT (0U)
16720 #define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
16721
16725 #define ENC_LMOD_MOD_MASK (0xFFFFU)
16726 #define ENC_LMOD_MOD_SHIFT (0U)
16727 #define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
16728
16732 #define ENC_UCOMP_COMP_MASK (0xFFFFU)
16733 #define ENC_UCOMP_COMP_SHIFT (0U)
16734 #define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
16735
16739 #define ENC_LCOMP_COMP_MASK (0xFFFFU)
16740 #define ENC_LCOMP_COMP_SHIFT (0U)
16741 #define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
16742 /* end of group ENC_Register_Masks */
16748
16749
16750 /* ENC - Peripheral instance base addresses */
16752 #define ENC1_BASE (0x403C8000u)
16753
16754 #define ENC1 ((ENC_Type *)ENC1_BASE)
16755
16756 #define ENC2_BASE (0x403CC000u)
16757
16758 #define ENC2 ((ENC_Type *)ENC2_BASE)
16759
16760 #define ENC3_BASE (0x403D0000u)
16761
16762 #define ENC3 ((ENC_Type *)ENC3_BASE)
16763
16764 #define ENC4_BASE (0x403D4000u)
16765
16766 #define ENC4 ((ENC_Type *)ENC4_BASE)
16767
16768 #define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
16769
16770 #define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
16771
16772 #define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
16773 #define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
16774 #define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
16775 #define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
16776 #define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
16777 /* end of group ENC_Peripheral_Access_Layer */
16781
16782
16783 /* ----------------------------------------------------------------------------
16784 -- ENET Peripheral Access Layer
16785 ---------------------------------------------------------------------------- */
16786
16793 typedef struct {
16794 uint8_t RESERVED_0[4];
16795 __IO uint32_t EIR;
16796 __IO uint32_t EIMR;
16797 uint8_t RESERVED_1[4];
16798 __IO uint32_t RDAR;
16799 __IO uint32_t TDAR;
16800 uint8_t RESERVED_2[12];
16801 __IO uint32_t ECR;
16802 uint8_t RESERVED_3[24];
16803 __IO uint32_t MMFR;
16804 __IO uint32_t MSCR;
16805 uint8_t RESERVED_4[28];
16806 __IO uint32_t MIBC;
16807 uint8_t RESERVED_5[28];
16808 __IO uint32_t RCR;
16809 uint8_t RESERVED_6[60];
16810 __IO uint32_t TCR;
16811 uint8_t RESERVED_7[28];
16812 __IO uint32_t PALR;
16813 __IO uint32_t PAUR;
16814 __IO uint32_t OPD;
16815 __IO uint32_t TXIC;
16816 uint8_t RESERVED_8[12];
16817 __IO uint32_t RXIC;
16818 uint8_t RESERVED_9[20];
16819 __IO uint32_t IAUR;
16820 __IO uint32_t IALR;
16821 __IO uint32_t GAUR;
16822 __IO uint32_t GALR;
16823 uint8_t RESERVED_10[28];
16824 __IO uint32_t TFWR;
16825 uint8_t RESERVED_11[56];
16826 __IO uint32_t RDSR;
16827 __IO uint32_t TDSR;
16828 __IO uint32_t MRBR;
16829 uint8_t RESERVED_12[4];
16830 __IO uint32_t RSFL;
16831 __IO uint32_t RSEM;
16832 __IO uint32_t RAEM;
16833 __IO uint32_t RAFL;
16834 __IO uint32_t TSEM;
16835 __IO uint32_t TAEM;
16836 __IO uint32_t TAFL;
16837 __IO uint32_t TIPG;
16838 __IO uint32_t FTRL;
16839 uint8_t RESERVED_13[12];
16840 __IO uint32_t TACC;
16841 __IO uint32_t RACC;
16842 uint8_t RESERVED_14[56];
16843 uint32_t RMON_T_DROP;
16844 __I uint32_t RMON_T_PACKETS;
16845 __I uint32_t RMON_T_BC_PKT;
16846 __I uint32_t RMON_T_MC_PKT;
16847 __I uint32_t RMON_T_CRC_ALIGN;
16848 __I uint32_t RMON_T_UNDERSIZE;
16849 __I uint32_t RMON_T_OVERSIZE;
16850 __I uint32_t RMON_T_FRAG;
16851 __I uint32_t RMON_T_JAB;
16852 __I uint32_t RMON_T_COL;
16853 __I uint32_t RMON_T_P64;
16854 __I uint32_t RMON_T_P65TO127;
16855 __I uint32_t RMON_T_P128TO255;
16856 __I uint32_t RMON_T_P256TO511;
16857 __I uint32_t RMON_T_P512TO1023;
16858 __I uint32_t RMON_T_P1024TO2047;
16859 __I uint32_t RMON_T_P_GTE2048;
16860 __I uint32_t RMON_T_OCTETS;
16861 uint32_t IEEE_T_DROP;
16862 __I uint32_t IEEE_T_FRAME_OK;
16863 __I uint32_t IEEE_T_1COL;
16864 __I uint32_t IEEE_T_MCOL;
16865 __I uint32_t IEEE_T_DEF;
16866 __I uint32_t IEEE_T_LCOL;
16867 __I uint32_t IEEE_T_EXCOL;
16868 __I uint32_t IEEE_T_MACERR;
16869 __I uint32_t IEEE_T_CSERR;
16870 __I uint32_t IEEE_T_SQE;
16871 __I uint32_t IEEE_T_FDXFC;
16872 __I uint32_t IEEE_T_OCTETS_OK;
16873 uint8_t RESERVED_15[12];
16874 __I uint32_t RMON_R_PACKETS;
16875 __I uint32_t RMON_R_BC_PKT;
16876 __I uint32_t RMON_R_MC_PKT;
16877 __I uint32_t RMON_R_CRC_ALIGN;
16878 __I uint32_t RMON_R_UNDERSIZE;
16879 __I uint32_t RMON_R_OVERSIZE;
16880 __I uint32_t RMON_R_FRAG;
16881 __I uint32_t RMON_R_JAB;
16882 uint32_t RMON_R_RESVD_0;
16883 __I uint32_t RMON_R_P64;
16884 __I uint32_t RMON_R_P65TO127;
16885 __I uint32_t RMON_R_P128TO255;
16886 __I uint32_t RMON_R_P256TO511;
16887 __I uint32_t RMON_R_P512TO1023;
16888 __I uint32_t RMON_R_P1024TO2047;
16889 __I uint32_t RMON_R_P_GTE2048;
16890 __I uint32_t RMON_R_OCTETS;
16891 __I uint32_t IEEE_R_DROP;
16892 __I uint32_t IEEE_R_FRAME_OK;
16893 __I uint32_t IEEE_R_CRC;
16894 __I uint32_t IEEE_R_ALIGN;
16895 __I uint32_t IEEE_R_MACERR;
16896 __I uint32_t IEEE_R_FDXFC;
16897 __I uint32_t IEEE_R_OCTETS_OK;
16898 uint8_t RESERVED_16[284];
16899 __IO uint32_t ATCR;
16900 __IO uint32_t ATVR;
16901 __IO uint32_t ATOFF;
16902 __IO uint32_t ATPER;
16903 __IO uint32_t ATCOR;
16904 __IO uint32_t ATINC;
16905 __I uint32_t ATSTMP;
16906 uint8_t RESERVED_17[488];
16907 __IO uint32_t TGSR;
16908 struct { /* offset: 0x608, array step: 0x8 */
16909 __IO uint32_t TCSR;
16910 __IO uint32_t TCCR;
16911 } CHANNEL[4];
16912 } ENET_Type;
16913
16914 /* ----------------------------------------------------------------------------
16915 -- ENET Register Masks
16916 ---------------------------------------------------------------------------- */
16917
16925 #define ENET_EIR_TS_TIMER_MASK (0x8000U)
16926 #define ENET_EIR_TS_TIMER_SHIFT (15U)
16927
16929 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
16930 #define ENET_EIR_TS_AVAIL_MASK (0x10000U)
16931 #define ENET_EIR_TS_AVAIL_SHIFT (16U)
16932
16934 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
16935 #define ENET_EIR_WAKEUP_MASK (0x20000U)
16936 #define ENET_EIR_WAKEUP_SHIFT (17U)
16937
16939 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
16940 #define ENET_EIR_PLR_MASK (0x40000U)
16941 #define ENET_EIR_PLR_SHIFT (18U)
16942
16944 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
16945 #define ENET_EIR_UN_MASK (0x80000U)
16946 #define ENET_EIR_UN_SHIFT (19U)
16947
16949 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
16950 #define ENET_EIR_RL_MASK (0x100000U)
16951 #define ENET_EIR_RL_SHIFT (20U)
16952
16954 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
16955 #define ENET_EIR_LC_MASK (0x200000U)
16956 #define ENET_EIR_LC_SHIFT (21U)
16957
16959 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
16960 #define ENET_EIR_EBERR_MASK (0x400000U)
16961 #define ENET_EIR_EBERR_SHIFT (22U)
16962
16964 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
16965 #define ENET_EIR_MII_MASK (0x800000U)
16966 #define ENET_EIR_MII_SHIFT (23U)
16967
16969 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
16970 #define ENET_EIR_RXB_MASK (0x1000000U)
16971 #define ENET_EIR_RXB_SHIFT (24U)
16972
16974 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
16975 #define ENET_EIR_RXF_MASK (0x2000000U)
16976 #define ENET_EIR_RXF_SHIFT (25U)
16977
16979 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
16980 #define ENET_EIR_TXB_MASK (0x4000000U)
16981 #define ENET_EIR_TXB_SHIFT (26U)
16982
16984 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
16985 #define ENET_EIR_TXF_MASK (0x8000000U)
16986 #define ENET_EIR_TXF_SHIFT (27U)
16987
16989 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
16990 #define ENET_EIR_GRA_MASK (0x10000000U)
16991 #define ENET_EIR_GRA_SHIFT (28U)
16992
16994 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
16995 #define ENET_EIR_BABT_MASK (0x20000000U)
16996 #define ENET_EIR_BABT_SHIFT (29U)
16997
16999 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
17000 #define ENET_EIR_BABR_MASK (0x40000000U)
17001 #define ENET_EIR_BABR_SHIFT (30U)
17002
17004 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
17005
17009 #define ENET_EIMR_TS_TIMER_MASK (0x8000U)
17010 #define ENET_EIMR_TS_TIMER_SHIFT (15U)
17011
17013 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
17014 #define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
17015 #define ENET_EIMR_TS_AVAIL_SHIFT (16U)
17016
17018 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
17019 #define ENET_EIMR_WAKEUP_MASK (0x20000U)
17020 #define ENET_EIMR_WAKEUP_SHIFT (17U)
17021
17023 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
17024 #define ENET_EIMR_PLR_MASK (0x40000U)
17025 #define ENET_EIMR_PLR_SHIFT (18U)
17026
17028 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
17029 #define ENET_EIMR_UN_MASK (0x80000U)
17030 #define ENET_EIMR_UN_SHIFT (19U)
17031
17033 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
17034 #define ENET_EIMR_RL_MASK (0x100000U)
17035 #define ENET_EIMR_RL_SHIFT (20U)
17036
17038 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
17039 #define ENET_EIMR_LC_MASK (0x200000U)
17040 #define ENET_EIMR_LC_SHIFT (21U)
17041
17043 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
17044 #define ENET_EIMR_EBERR_MASK (0x400000U)
17045 #define ENET_EIMR_EBERR_SHIFT (22U)
17046
17048 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
17049 #define ENET_EIMR_MII_MASK (0x800000U)
17050 #define ENET_EIMR_MII_SHIFT (23U)
17051
17053 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
17054 #define ENET_EIMR_RXB_MASK (0x1000000U)
17055 #define ENET_EIMR_RXB_SHIFT (24U)
17056
17058 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
17059 #define ENET_EIMR_RXF_MASK (0x2000000U)
17060 #define ENET_EIMR_RXF_SHIFT (25U)
17061
17063 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
17064 #define ENET_EIMR_TXB_MASK (0x4000000U)
17065 #define ENET_EIMR_TXB_SHIFT (26U)
17066
17070 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
17071 #define ENET_EIMR_TXF_MASK (0x8000000U)
17072 #define ENET_EIMR_TXF_SHIFT (27U)
17073
17077 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
17078 #define ENET_EIMR_GRA_MASK (0x10000000U)
17079 #define ENET_EIMR_GRA_SHIFT (28U)
17080
17084 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
17085 #define ENET_EIMR_BABT_MASK (0x20000000U)
17086 #define ENET_EIMR_BABT_SHIFT (29U)
17087
17091 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
17092 #define ENET_EIMR_BABR_MASK (0x40000000U)
17093 #define ENET_EIMR_BABR_SHIFT (30U)
17094
17098 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
17099
17103 #define ENET_RDAR_RDAR_MASK (0x1000000U)
17104 #define ENET_RDAR_RDAR_SHIFT (24U)
17105
17107 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
17108
17112 #define ENET_TDAR_TDAR_MASK (0x1000000U)
17113 #define ENET_TDAR_TDAR_SHIFT (24U)
17114
17116 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
17117
17121 #define ENET_ECR_RESET_MASK (0x1U)
17122 #define ENET_ECR_RESET_SHIFT (0U)
17123
17125 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
17126 #define ENET_ECR_ETHEREN_MASK (0x2U)
17127 #define ENET_ECR_ETHEREN_SHIFT (1U)
17128
17132 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
17133 #define ENET_ECR_MAGICEN_MASK (0x4U)
17134 #define ENET_ECR_MAGICEN_SHIFT (2U)
17135
17139 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
17140 #define ENET_ECR_SLEEP_MASK (0x8U)
17141 #define ENET_ECR_SLEEP_SHIFT (3U)
17142
17146 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
17147 #define ENET_ECR_EN1588_MASK (0x10U)
17148 #define ENET_ECR_EN1588_SHIFT (4U)
17149
17153 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
17154 #define ENET_ECR_DBGEN_MASK (0x40U)
17155 #define ENET_ECR_DBGEN_SHIFT (6U)
17156
17160 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
17161 #define ENET_ECR_DBSWP_MASK (0x100U)
17162 #define ENET_ECR_DBSWP_SHIFT (8U)
17163
17167 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
17168
17172 #define ENET_MMFR_DATA_MASK (0xFFFFU)
17173 #define ENET_MMFR_DATA_SHIFT (0U)
17174
17176 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
17177 #define ENET_MMFR_TA_MASK (0x30000U)
17178 #define ENET_MMFR_TA_SHIFT (16U)
17179
17181 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
17182 #define ENET_MMFR_RA_MASK (0x7C0000U)
17183 #define ENET_MMFR_RA_SHIFT (18U)
17184
17186 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
17187 #define ENET_MMFR_PA_MASK (0xF800000U)
17188 #define ENET_MMFR_PA_SHIFT (23U)
17189
17191 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
17192 #define ENET_MMFR_OP_MASK (0x30000000U)
17193 #define ENET_MMFR_OP_SHIFT (28U)
17194
17196 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
17197 #define ENET_MMFR_ST_MASK (0xC0000000U)
17198 #define ENET_MMFR_ST_SHIFT (30U)
17199
17201 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
17202
17206 #define ENET_MSCR_MII_SPEED_MASK (0x7EU)
17207 #define ENET_MSCR_MII_SPEED_SHIFT (1U)
17208
17210 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
17211 #define ENET_MSCR_DIS_PRE_MASK (0x80U)
17212 #define ENET_MSCR_DIS_PRE_SHIFT (7U)
17213
17217 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
17218 #define ENET_MSCR_HOLDTIME_MASK (0x700U)
17219 #define ENET_MSCR_HOLDTIME_SHIFT (8U)
17220
17226 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
17227
17231 #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
17232 #define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
17233
17237 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
17238 #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
17239 #define ENET_MIBC_MIB_IDLE_SHIFT (30U)
17240
17244 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
17245 #define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
17246 #define ENET_MIBC_MIB_DIS_SHIFT (31U)
17247
17251 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
17252
17256 #define ENET_RCR_LOOP_MASK (0x1U)
17257 #define ENET_RCR_LOOP_SHIFT (0U)
17258
17262 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
17263 #define ENET_RCR_DRT_MASK (0x2U)
17264 #define ENET_RCR_DRT_SHIFT (1U)
17265
17269 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
17270 #define ENET_RCR_MII_MODE_MASK (0x4U)
17271 #define ENET_RCR_MII_MODE_SHIFT (2U)
17272
17276 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
17277 #define ENET_RCR_PROM_MASK (0x8U)
17278 #define ENET_RCR_PROM_SHIFT (3U)
17279
17283 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
17284 #define ENET_RCR_BC_REJ_MASK (0x10U)
17285 #define ENET_RCR_BC_REJ_SHIFT (4U)
17286
17288 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
17289 #define ENET_RCR_FCE_MASK (0x20U)
17290 #define ENET_RCR_FCE_SHIFT (5U)
17291
17293 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
17294 #define ENET_RCR_RMII_MODE_MASK (0x100U)
17295 #define ENET_RCR_RMII_MODE_SHIFT (8U)
17296
17300 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
17301 #define ENET_RCR_RMII_10T_MASK (0x200U)
17302 #define ENET_RCR_RMII_10T_SHIFT (9U)
17303
17307 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
17308 #define ENET_RCR_PADEN_MASK (0x1000U)
17309 #define ENET_RCR_PADEN_SHIFT (12U)
17310
17314 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
17315 #define ENET_RCR_PAUFWD_MASK (0x2000U)
17316 #define ENET_RCR_PAUFWD_SHIFT (13U)
17317
17321 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
17322 #define ENET_RCR_CRCFWD_MASK (0x4000U)
17323 #define ENET_RCR_CRCFWD_SHIFT (14U)
17324
17328 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
17329 #define ENET_RCR_CFEN_MASK (0x8000U)
17330 #define ENET_RCR_CFEN_SHIFT (15U)
17331
17335 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
17336 #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
17337 #define ENET_RCR_MAX_FL_SHIFT (16U)
17338
17340 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
17341 #define ENET_RCR_NLC_MASK (0x40000000U)
17342 #define ENET_RCR_NLC_SHIFT (30U)
17343
17347 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
17348 #define ENET_RCR_GRS_MASK (0x80000000U)
17349 #define ENET_RCR_GRS_SHIFT (31U)
17350
17352 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
17353
17357 #define ENET_TCR_GTS_MASK (0x1U)
17358 #define ENET_TCR_GTS_SHIFT (0U)
17359
17361 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
17362 #define ENET_TCR_FDEN_MASK (0x4U)
17363 #define ENET_TCR_FDEN_SHIFT (2U)
17364
17366 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
17367 #define ENET_TCR_TFC_PAUSE_MASK (0x8U)
17368 #define ENET_TCR_TFC_PAUSE_SHIFT (3U)
17369
17373 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
17374 #define ENET_TCR_RFC_PAUSE_MASK (0x10U)
17375 #define ENET_TCR_RFC_PAUSE_SHIFT (4U)
17376
17378 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
17379 #define ENET_TCR_ADDSEL_MASK (0xE0U)
17380 #define ENET_TCR_ADDSEL_SHIFT (5U)
17381
17387 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
17388 #define ENET_TCR_ADDINS_MASK (0x100U)
17389 #define ENET_TCR_ADDINS_SHIFT (8U)
17390
17394 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
17395 #define ENET_TCR_CRCFWD_MASK (0x200U)
17396 #define ENET_TCR_CRCFWD_SHIFT (9U)
17397
17401 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
17402
17406 #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
17407 #define ENET_PALR_PADDR1_SHIFT (0U)
17408
17410 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
17411
17415 #define ENET_PAUR_TYPE_MASK (0xFFFFU)
17416 #define ENET_PAUR_TYPE_SHIFT (0U)
17417
17419 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
17420 #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
17421 #define ENET_PAUR_PADDR2_SHIFT (16U)
17422 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
17423
17427 #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
17428 #define ENET_OPD_PAUSE_DUR_SHIFT (0U)
17429
17431 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
17432 #define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
17433 #define ENET_OPD_OPCODE_SHIFT (16U)
17434
17436 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
17437
17441 #define ENET_TXIC_ICTT_MASK (0xFFFFU)
17442 #define ENET_TXIC_ICTT_SHIFT (0U)
17443
17445 #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
17446 #define ENET_TXIC_ICFT_MASK (0xFF00000U)
17447 #define ENET_TXIC_ICFT_SHIFT (20U)
17448
17450 #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
17451 #define ENET_TXIC_ICCS_MASK (0x40000000U)
17452 #define ENET_TXIC_ICCS_SHIFT (30U)
17453
17457 #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
17458 #define ENET_TXIC_ICEN_MASK (0x80000000U)
17459 #define ENET_TXIC_ICEN_SHIFT (31U)
17460
17464 #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
17465
17469 #define ENET_RXIC_ICTT_MASK (0xFFFFU)
17470 #define ENET_RXIC_ICTT_SHIFT (0U)
17471
17473 #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
17474 #define ENET_RXIC_ICFT_MASK (0xFF00000U)
17475 #define ENET_RXIC_ICFT_SHIFT (20U)
17476
17478 #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
17479 #define ENET_RXIC_ICCS_MASK (0x40000000U)
17480 #define ENET_RXIC_ICCS_SHIFT (30U)
17481
17485 #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
17486 #define ENET_RXIC_ICEN_MASK (0x80000000U)
17487 #define ENET_RXIC_ICEN_SHIFT (31U)
17488
17492 #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
17493
17497 #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
17498 #define ENET_IAUR_IADDR1_SHIFT (0U)
17499 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
17500
17504 #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
17505 #define ENET_IALR_IADDR2_SHIFT (0U)
17506 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
17507
17511 #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
17512 #define ENET_GAUR_GADDR1_SHIFT (0U)
17513 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
17514
17518 #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
17519 #define ENET_GALR_GADDR2_SHIFT (0U)
17520 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
17521
17525 #define ENET_TFWR_TFWR_MASK (0x3FU)
17526 #define ENET_TFWR_TFWR_SHIFT (0U)
17527
17534 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
17535 #define ENET_TFWR_STRFWD_MASK (0x100U)
17536 #define ENET_TFWR_STRFWD_SHIFT (8U)
17537
17541 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
17542
17546 #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
17547 #define ENET_RDSR_R_DES_START_SHIFT (3U)
17548 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
17549
17553 #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
17554 #define ENET_TDSR_X_DES_START_SHIFT (3U)
17555 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
17556
17560 #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
17561 #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
17562 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
17563
17567 #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
17568 #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
17569
17571 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
17572
17576 #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
17577 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
17578
17580 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
17581 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
17582 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
17583
17585 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
17586
17590 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
17591 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
17592
17594 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
17595
17599 #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
17600 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
17601
17603 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
17604
17608 #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
17609 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
17610
17612 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
17613
17617 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
17618 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
17619
17621 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
17622
17626 #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
17627 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
17628
17630 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
17631
17635 #define ENET_TIPG_IPG_MASK (0x1FU)
17636 #define ENET_TIPG_IPG_SHIFT (0U)
17637
17639 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
17640
17644 #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
17645 #define ENET_FTRL_TRUNC_FL_SHIFT (0U)
17646
17648 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
17649
17653 #define ENET_TACC_SHIFT16_MASK (0x1U)
17654 #define ENET_TACC_SHIFT16_SHIFT (0U)
17655
17662 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
17663 #define ENET_TACC_IPCHK_MASK (0x8U)
17664 #define ENET_TACC_IPCHK_SHIFT (3U)
17665
17670 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
17671 #define ENET_TACC_PROCHK_MASK (0x10U)
17672 #define ENET_TACC_PROCHK_SHIFT (4U)
17673
17678 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
17679
17683 #define ENET_RACC_PADREM_MASK (0x1U)
17684 #define ENET_RACC_PADREM_SHIFT (0U)
17685
17689 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
17690 #define ENET_RACC_IPDIS_MASK (0x2U)
17691 #define ENET_RACC_IPDIS_SHIFT (1U)
17692
17698 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
17699 #define ENET_RACC_PRODIS_MASK (0x4U)
17700 #define ENET_RACC_PRODIS_SHIFT (2U)
17701
17707 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
17708 #define ENET_RACC_LINEDIS_MASK (0x40U)
17709 #define ENET_RACC_LINEDIS_SHIFT (6U)
17710
17714 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
17715 #define ENET_RACC_SHIFT16_MASK (0x80U)
17716 #define ENET_RACC_SHIFT16_SHIFT (7U)
17717
17721 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
17722
17726 #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
17727 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
17728
17730 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
17731
17735 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
17736 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
17737
17739 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
17740
17744 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
17745 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
17746
17748 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
17749
17753 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
17754 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
17755
17757 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
17758
17762 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
17763 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
17764
17766 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
17767
17771 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
17772 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
17773
17775 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
17776
17780 #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
17781 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
17782
17784 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
17785
17789 #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
17790 #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
17791
17793 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
17794
17798 #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
17799 #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
17800
17802 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
17803
17807 #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
17808 #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
17809
17811 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
17812
17816 #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
17817 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
17818
17820 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
17821
17825 #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
17826 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
17827
17829 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
17830
17834 #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
17835 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
17836
17838 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
17839
17843 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
17844 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
17845
17847 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
17848
17852 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
17853 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
17854
17856 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
17857
17861 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
17862 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
17863
17865 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
17866
17870 #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
17871 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
17872
17874 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
17875
17879 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
17880 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
17881
17883 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
17884
17888 #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
17889 #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
17890
17892 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
17893
17897 #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
17898 #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
17899
17901 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
17902
17906 #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
17907 #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
17908
17910 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
17911
17915 #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
17916 #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
17917
17919 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
17920
17924 #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
17925 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
17926
17928 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
17929
17933 #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
17934 #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
17935
17937 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
17938
17942 #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
17943 #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
17944
17946 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
17947
17951 #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
17952 #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
17953 #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
17954
17958 #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
17959 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
17960
17962 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
17963
17967 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
17968 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
17969
17971 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
17972
17976 #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
17977 #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
17978
17980 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
17981
17985 #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
17986 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
17987
17989 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
17990
17994 #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
17995 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
17996
17998 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
17999
18003 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
18004 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
18005
18007 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
18008
18012 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
18013 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
18014
18016 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
18017
18021 #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
18022 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
18023
18025 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
18026
18030 #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
18031 #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
18032
18034 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
18035
18039 #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
18040 #define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
18041
18043 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
18044
18048 #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
18049 #define ENET_RMON_R_P64_COUNT_SHIFT (0U)
18050
18052 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
18053
18057 #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
18058 #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
18059
18061 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
18062
18066 #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
18067 #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
18068
18070 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
18071
18075 #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
18076 #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
18077
18079 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
18080
18084 #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
18085 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
18086
18088 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
18089
18093 #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
18094 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
18095
18097 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
18098
18102 #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
18103 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
18104
18106 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
18107
18111 #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
18112 #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
18113
18115 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
18116
18120 #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
18121 #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
18122
18124 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
18125
18129 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
18130 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
18131
18133 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
18134
18138 #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
18139 #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
18140
18142 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
18143
18147 #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
18148 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
18149
18151 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
18152
18156 #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
18157 #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
18158
18160 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
18161
18165 #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
18166 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
18167
18169 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
18170
18174 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
18175 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
18176
18178 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
18179
18183 #define ENET_ATCR_EN_MASK (0x1U)
18184 #define ENET_ATCR_EN_SHIFT (0U)
18185
18189 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
18190 #define ENET_ATCR_OFFEN_MASK (0x4U)
18191 #define ENET_ATCR_OFFEN_SHIFT (2U)
18192
18198 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
18199 #define ENET_ATCR_OFFRST_MASK (0x8U)
18200 #define ENET_ATCR_OFFRST_SHIFT (3U)
18201
18205 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
18206 #define ENET_ATCR_PEREN_MASK (0x10U)
18207 #define ENET_ATCR_PEREN_SHIFT (4U)
18208
18214 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
18215 #define ENET_ATCR_PINPER_MASK (0x80U)
18216 #define ENET_ATCR_PINPER_SHIFT (7U)
18217
18221 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
18222 #define ENET_ATCR_RESTART_MASK (0x200U)
18223 #define ENET_ATCR_RESTART_SHIFT (9U)
18224
18226 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
18227 #define ENET_ATCR_CAPTURE_MASK (0x800U)
18228 #define ENET_ATCR_CAPTURE_SHIFT (11U)
18229
18233 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
18234 #define ENET_ATCR_SLAVE_MASK (0x2000U)
18235 #define ENET_ATCR_SLAVE_SHIFT (13U)
18236
18241 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
18242
18246 #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
18247 #define ENET_ATVR_ATIME_SHIFT (0U)
18248 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
18249
18253 #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
18254 #define ENET_ATOFF_OFFSET_SHIFT (0U)
18255 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
18256
18260 #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
18261 #define ENET_ATPER_PERIOD_SHIFT (0U)
18262 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
18263
18267 #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
18268 #define ENET_ATCOR_COR_SHIFT (0U)
18269
18271 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
18272
18276 #define ENET_ATINC_INC_MASK (0x7FU)
18277 #define ENET_ATINC_INC_SHIFT (0U)
18278
18280 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
18281 #define ENET_ATINC_INC_CORR_MASK (0x7F00U)
18282 #define ENET_ATINC_INC_CORR_SHIFT (8U)
18283
18285 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
18286
18290 #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
18291 #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
18292 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
18293
18297 #define ENET_TGSR_TF0_MASK (0x1U)
18298 #define ENET_TGSR_TF0_SHIFT (0U)
18299
18303 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
18304 #define ENET_TGSR_TF1_MASK (0x2U)
18305 #define ENET_TGSR_TF1_SHIFT (1U)
18306
18310 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
18311 #define ENET_TGSR_TF2_MASK (0x4U)
18312 #define ENET_TGSR_TF2_SHIFT (2U)
18313
18317 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
18318 #define ENET_TGSR_TF3_MASK (0x8U)
18319 #define ENET_TGSR_TF3_SHIFT (3U)
18320
18324 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
18325
18329 #define ENET_TCSR_TDRE_MASK (0x1U)
18330 #define ENET_TCSR_TDRE_SHIFT (0U)
18331
18335 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
18336 #define ENET_TCSR_TMODE_MASK (0x3CU)
18337 #define ENET_TCSR_TMODE_SHIFT (2U)
18338
18354 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
18355 #define ENET_TCSR_TIE_MASK (0x40U)
18356 #define ENET_TCSR_TIE_SHIFT (6U)
18357
18361 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
18362 #define ENET_TCSR_TF_MASK (0x80U)
18363 #define ENET_TCSR_TF_SHIFT (7U)
18364
18368 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
18369 #define ENET_TCSR_TPWC_MASK (0xF800U)
18370 #define ENET_TCSR_TPWC_SHIFT (11U)
18371
18378 #define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
18379
18381 /* The count of ENET_TCSR */
18382 #define ENET_TCSR_COUNT (4U)
18383
18386 #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
18387 #define ENET_TCCR_TCC_SHIFT (0U)
18388
18390 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
18391
18393 /* The count of ENET_TCCR */
18394 #define ENET_TCCR_COUNT (4U)
18395
18396 /* end of group ENET_Register_Masks */
18400
18401
18402 /* ENET - Peripheral instance base addresses */
18404 #define ENET_BASE (0x402D8000u)
18405
18406 #define ENET ((ENET_Type *)ENET_BASE)
18407
18408 #define ENET2_BASE (0x402D4000u)
18409
18410 #define ENET2 ((ENET_Type *)ENET2_BASE)
18411
18412 #define ENET_BASE_ADDRS { ENET_BASE, 0u, ENET2_BASE }
18413
18414 #define ENET_BASE_PTRS { ENET, (ENET_Type *)0u, ENET2 }
18415
18416 #define ENET_Transmit_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
18417 #define ENET_Receive_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
18418 #define ENET_Error_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
18419 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, NotAvail_IRQn, ENET2_1588_Timer_IRQn }
18420 /* ENET Buffer Descriptor and Buffer Address Alignment. */
18421 #define ENET_BUFF_ALIGNMENT (64U)
18422
18423 /* end of group ENET_Peripheral_Access_Layer */
18427
18428
18429 /* ----------------------------------------------------------------------------
18430 -- EWM Peripheral Access Layer
18431 ---------------------------------------------------------------------------- */
18432
18439 typedef struct {
18440 __IO uint8_t CTRL;
18441 __O uint8_t SERV;
18442 __IO uint8_t CMPL;
18443 __IO uint8_t CMPH;
18444 __IO uint8_t CLKCTRL;
18445 __IO uint8_t CLKPRESCALER;
18446 } EWM_Type;
18447
18448 /* ----------------------------------------------------------------------------
18449 -- EWM Register Masks
18450 ---------------------------------------------------------------------------- */
18451
18459 #define EWM_CTRL_EWMEN_MASK (0x1U)
18460 #define EWM_CTRL_EWMEN_SHIFT (0U)
18461
18463 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
18464 #define EWM_CTRL_ASSIN_MASK (0x2U)
18465 #define EWM_CTRL_ASSIN_SHIFT (1U)
18466
18468 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
18469 #define EWM_CTRL_INEN_MASK (0x4U)
18470 #define EWM_CTRL_INEN_SHIFT (2U)
18471
18473 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
18474 #define EWM_CTRL_INTEN_MASK (0x8U)
18475 #define EWM_CTRL_INTEN_SHIFT (3U)
18476
18478 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
18479
18483 #define EWM_SERV_SERVICE_MASK (0xFFU)
18484 #define EWM_SERV_SERVICE_SHIFT (0U)
18485
18487 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
18488
18492 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
18493 #define EWM_CMPL_COMPAREL_SHIFT (0U)
18494
18496 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
18497
18501 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
18502 #define EWM_CMPH_COMPAREH_SHIFT (0U)
18503
18505 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
18506
18510 #define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
18511 #define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
18512
18514 #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
18515
18519 #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
18520 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
18521
18523 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
18524 /* end of group EWM_Register_Masks */
18530
18531
18532 /* EWM - Peripheral instance base addresses */
18534 #define EWM_BASE (0x400B4000u)
18535
18536 #define EWM ((EWM_Type *)EWM_BASE)
18537
18538 #define EWM_BASE_ADDRS { EWM_BASE }
18539
18540 #define EWM_BASE_PTRS { EWM }
18541
18542 #define EWM_IRQS { EWM_IRQn }
18543 /* end of group EWM_Peripheral_Access_Layer */
18547
18548
18549 /* ----------------------------------------------------------------------------
18550 -- FLEXIO Peripheral Access Layer
18551 ---------------------------------------------------------------------------- */
18552
18559 typedef struct {
18560 __I uint32_t VERID;
18561 __I uint32_t PARAM;
18562 __IO uint32_t CTRL;
18563 __I uint32_t PIN;
18564 __IO uint32_t SHIFTSTAT;
18565 __IO uint32_t SHIFTERR;
18566 __IO uint32_t TIMSTAT;
18567 uint8_t RESERVED_0[4];
18568 __IO uint32_t SHIFTSIEN;
18569 __IO uint32_t SHIFTEIEN;
18570 __IO uint32_t TIMIEN;
18571 uint8_t RESERVED_1[4];
18572 __IO uint32_t SHIFTSDEN;
18573 uint8_t RESERVED_2[12];
18574 __IO uint32_t SHIFTSTATE;
18575 uint8_t RESERVED_3[60];
18576 __IO uint32_t SHIFTCTL[4];
18577 uint8_t RESERVED_4[112];
18578 __IO uint32_t SHIFTCFG[4];
18579 uint8_t RESERVED_5[240];
18580 __IO uint32_t SHIFTBUF[4];
18581 uint8_t RESERVED_6[112];
18582 __IO uint32_t SHIFTBUFBIS[4];
18583 uint8_t RESERVED_7[112];
18584 __IO uint32_t SHIFTBUFBYS[4];
18585 uint8_t RESERVED_8[112];
18586 __IO uint32_t SHIFTBUFBBS[4];
18587 uint8_t RESERVED_9[112];
18588 __IO uint32_t TIMCTL[4];
18589 uint8_t RESERVED_10[112];
18590 __IO uint32_t TIMCFG[4];
18591 uint8_t RESERVED_11[112];
18592 __IO uint32_t TIMCMP[4];
18593 uint8_t RESERVED_12[368];
18594 __IO uint32_t SHIFTBUFNBS[4];
18595 uint8_t RESERVED_13[112];
18596 __IO uint32_t SHIFTBUFHWS[4];
18597 uint8_t RESERVED_14[112];
18598 __IO uint32_t SHIFTBUFNIS[4];
18599 } FLEXIO_Type;
18600
18601 /* ----------------------------------------------------------------------------
18602 -- FLEXIO Register Masks
18603 ---------------------------------------------------------------------------- */
18604
18612 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
18613 #define FLEXIO_VERID_FEATURE_SHIFT (0U)
18614
18618 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
18619 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
18620 #define FLEXIO_VERID_MINOR_SHIFT (16U)
18621
18623 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
18624 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
18625 #define FLEXIO_VERID_MAJOR_SHIFT (24U)
18626
18628 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
18629
18633 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
18634 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
18635
18637 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
18638 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
18639 #define FLEXIO_PARAM_TIMER_SHIFT (8U)
18640
18642 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
18643 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
18644 #define FLEXIO_PARAM_PIN_SHIFT (16U)
18645
18647 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
18648 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
18649 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
18650
18652 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
18653
18657 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
18658 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
18659
18663 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
18664 #define FLEXIO_CTRL_SWRST_MASK (0x2U)
18665 #define FLEXIO_CTRL_SWRST_SHIFT (1U)
18666
18670 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
18671 #define FLEXIO_CTRL_FASTACC_MASK (0x4U)
18672 #define FLEXIO_CTRL_FASTACC_SHIFT (2U)
18673
18677 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
18678 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
18679 #define FLEXIO_CTRL_DBGE_SHIFT (30U)
18680
18684 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
18685 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
18686 #define FLEXIO_CTRL_DOZEN_SHIFT (31U)
18687
18691 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
18692
18696 #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
18697 #define FLEXIO_PIN_PDI_SHIFT (0U)
18698
18700 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
18701
18705 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
18706 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
18707
18709 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
18710
18714 #define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
18715 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
18716
18718 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
18719
18723 #define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
18724 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
18725
18727 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
18728
18732 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
18733 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
18734
18736 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
18737
18741 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
18742 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
18743
18745 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
18746
18750 #define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
18751 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
18752
18754 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
18755
18759 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
18760 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
18761
18763 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
18764
18768 #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
18769 #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
18770
18772 #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
18773
18777 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
18778 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
18779
18789 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
18790 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
18791 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
18792
18796 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
18797 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
18798 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
18799
18801 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
18802 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
18803 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
18804
18810 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
18811 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
18812 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
18813
18817 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
18818 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
18819 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
18820
18822 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
18823
18825 /* The count of FLEXIO_SHIFTCTL */
18826 #define FLEXIO_SHIFTCTL_COUNT (4U)
18827
18830 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
18831 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
18832
18838 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
18839 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
18840 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
18841
18847 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
18848 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
18849 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
18850
18854 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
18855 #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
18856 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
18857
18859 #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
18860
18862 /* The count of FLEXIO_SHIFTCFG */
18863 #define FLEXIO_SHIFTCFG_COUNT (4U)
18864
18867 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
18868 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
18869
18871 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
18872
18874 /* The count of FLEXIO_SHIFTBUF */
18875 #define FLEXIO_SHIFTBUF_COUNT (4U)
18876
18879 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
18880 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
18881
18883 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
18884
18886 /* The count of FLEXIO_SHIFTBUFBIS */
18887 #define FLEXIO_SHIFTBUFBIS_COUNT (4U)
18888
18891 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
18892 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
18893
18895 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
18896
18898 /* The count of FLEXIO_SHIFTBUFBYS */
18899 #define FLEXIO_SHIFTBUFBYS_COUNT (4U)
18900
18903 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
18904 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
18905
18907 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
18908
18910 /* The count of FLEXIO_SHIFTBUFBBS */
18911 #define FLEXIO_SHIFTBUFBBS_COUNT (4U)
18912
18915 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
18916 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
18917
18923 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
18924 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
18925 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
18926
18930 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
18931 #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
18932 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
18933
18935 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
18936 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
18937 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
18938
18944 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
18945 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
18946 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
18947
18951 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
18952 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
18953 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
18954
18958 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
18959 #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
18960 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
18961
18963 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
18964
18966 /* The count of FLEXIO_TIMCTL */
18967 #define FLEXIO_TIMCTL_COUNT (4U)
18968
18971 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
18972 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
18973
18977 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
18978 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
18979 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
18980
18986 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
18987 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
18988 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
18989
18999 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
19000 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
19001 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
19002
19012 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
19013 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
19014 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
19015
19025 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
19026 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
19027 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
19028
19034 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
19035 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
19036 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
19037
19043 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
19044
19046 /* The count of FLEXIO_TIMCFG */
19047 #define FLEXIO_TIMCFG_COUNT (4U)
19048
19051 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
19052 #define FLEXIO_TIMCMP_CMP_SHIFT (0U)
19053
19055 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
19056
19058 /* The count of FLEXIO_TIMCMP */
19059 #define FLEXIO_TIMCMP_COUNT (4U)
19060
19063 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
19064 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
19065
19067 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
19068
19070 /* The count of FLEXIO_SHIFTBUFNBS */
19071 #define FLEXIO_SHIFTBUFNBS_COUNT (4U)
19072
19075 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
19076 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
19077
19079 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
19080
19082 /* The count of FLEXIO_SHIFTBUFHWS */
19083 #define FLEXIO_SHIFTBUFHWS_COUNT (4U)
19084
19087 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
19088 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
19089
19091 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
19092
19094 /* The count of FLEXIO_SHIFTBUFNIS */
19095 #define FLEXIO_SHIFTBUFNIS_COUNT (4U)
19096
19097 /* end of group FLEXIO_Register_Masks */
19101
19102
19103 /* FLEXIO - Peripheral instance base addresses */
19105 #define FLEXIO1_BASE (0x401AC000u)
19106
19107 #define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
19108
19109 #define FLEXIO2_BASE (0x401B0000u)
19110
19111 #define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
19112
19113 #define FLEXIO3_BASE (0x42020000u)
19114
19115 #define FLEXIO3 ((FLEXIO_Type *)FLEXIO3_BASE)
19116
19117 #define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE, FLEXIO3_BASE }
19118
19119 #define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2, FLEXIO3 }
19120
19121 #define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn, FLEXIO3_IRQn }
19122 /* end of group FLEXIO_Peripheral_Access_Layer */
19126
19127
19128 /* ----------------------------------------------------------------------------
19129 -- FLEXRAM Peripheral Access Layer
19130 ---------------------------------------------------------------------------- */
19131
19138 typedef struct {
19139 __IO uint32_t TCM_CTRL;
19140 uint8_t RESERVED_0[12];
19141 __IO uint32_t INT_STATUS;
19142 __IO uint32_t INT_STAT_EN;
19143 __IO uint32_t INT_SIG_EN;
19144 } FLEXRAM_Type;
19145
19146 /* ----------------------------------------------------------------------------
19147 -- FLEXRAM Register Masks
19148 ---------------------------------------------------------------------------- */
19149
19157 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
19158 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
19159
19163 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
19164 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
19165 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
19166
19170 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
19171 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
19172 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
19173
19175 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
19176
19180 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
19181 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
19182
19186 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
19187 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
19188 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
19189
19193 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
19194 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
19195 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
19196
19200 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
19201
19205 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
19206 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
19207
19211 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
19212 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
19213 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
19214
19218 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
19219 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
19220 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
19221
19225 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
19226
19230 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
19231 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
19232
19236 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
19237 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
19238 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
19239
19243 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
19244 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
19245 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
19246
19250 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
19251 /* end of group FLEXRAM_Register_Masks */
19257
19258
19259 /* FLEXRAM - Peripheral instance base addresses */
19261 #define FLEXRAM_BASE (0x400B0000u)
19262
19263 #define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
19264
19265 #define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
19266
19267 #define FLEXRAM_BASE_PTRS { FLEXRAM }
19268
19269 #define FLEXRAM_IRQS { FLEXRAM_IRQn }
19270 /* end of group FLEXRAM_Peripheral_Access_Layer */
19274
19275
19276 /* ----------------------------------------------------------------------------
19277 -- FLEXSPI Peripheral Access Layer
19278 ---------------------------------------------------------------------------- */
19279
19286 typedef struct {
19287 __IO uint32_t MCR0;
19288 __IO uint32_t MCR1;
19289 __IO uint32_t MCR2;
19290 __IO uint32_t AHBCR;
19291 __IO uint32_t INTEN;
19292 __IO uint32_t INTR;
19293 __IO uint32_t LUTKEY;
19294 __IO uint32_t LUTCR;
19295 __IO uint32_t AHBRXBUFCR0[4];
19296 uint8_t RESERVED_0[48];
19297 __IO uint32_t FLSHCR0[4];
19298 __IO uint32_t FLSHCR1[4];
19299 __IO uint32_t FLSHCR2[4];
19300 uint8_t RESERVED_1[4];
19301 __IO uint32_t FLSHCR4;
19302 uint8_t RESERVED_2[8];
19303 __IO uint32_t IPCR0;
19304 __IO uint32_t IPCR1;
19305 uint8_t RESERVED_3[8];
19306 __IO uint32_t IPCMD;
19307 uint8_t RESERVED_4[4];
19308 __IO uint32_t IPRXFCR;
19309 __IO uint32_t IPTXFCR;
19310 __IO uint32_t DLLCR[2];
19311 uint8_t RESERVED_5[24];
19312 __I uint32_t STS0;
19313 __I uint32_t STS1;
19314 __I uint32_t STS2;
19315 __I uint32_t AHBSPNDSTS;
19316 __I uint32_t IPRXFSTS;
19317 __I uint32_t IPTXFSTS;
19318 uint8_t RESERVED_6[8];
19319 __I uint32_t RFDR[32];
19320 __O uint32_t TFDR[32];
19321 __IO uint32_t LUT[64];
19322 } FLEXSPI_Type;
19323
19324 /* ----------------------------------------------------------------------------
19325 -- FLEXSPI Register Masks
19326 ---------------------------------------------------------------------------- */
19327
19335 #define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
19336 #define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
19337
19339 #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
19340 #define FLEXSPI_MCR0_MDIS_MASK (0x2U)
19341 #define FLEXSPI_MCR0_MDIS_SHIFT (1U)
19342
19344 #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
19345 #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
19346 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
19347
19353 #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
19354 #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
19355 #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
19356
19360 #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
19361 #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
19362 #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
19363
19367 #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
19368 #define FLEXSPI_MCR0_HSEN_MASK (0x800U)
19369 #define FLEXSPI_MCR0_HSEN_SHIFT (11U)
19370
19374 #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
19375 #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
19376 #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
19377
19381 #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
19382 #define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
19383 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
19384
19388 #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
19389 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
19390 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
19391
19397 #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
19398 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
19399 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
19400
19402 #define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
19403 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
19404 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
19405
19407 #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
19408
19412 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
19413 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
19414 #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
19415 #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
19416 #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
19417 #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
19418
19422 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
19423 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
19424
19431 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
19432 #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
19433 #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
19434
19437 #define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
19438 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
19439 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
19440
19447 #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
19448 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
19449 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
19450
19456 #define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
19457 #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
19458 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
19459
19461 #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
19462
19466 #define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
19467 #define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
19468
19472 #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
19473 #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
19474 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
19475
19479 #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
19480 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
19481 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
19482
19489 #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
19490 #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
19491 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
19492
19494 #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
19495 #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
19496 #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
19497
19502 #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
19503
19507 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
19508 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
19509
19511 #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
19512 #define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
19513 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
19514
19516 #define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
19517 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
19518 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
19519
19521 #define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
19522 #define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
19523 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
19524
19526 #define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
19527 #define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
19528 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
19529
19531 #define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
19532 #define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
19533 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
19534
19536 #define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
19537 #define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
19538 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
19539
19541 #define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
19542 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
19543 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
19544
19546 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
19547 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
19548 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
19549
19551 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
19552 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
19553 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
19554
19556 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
19557 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
19558 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
19559
19561 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
19562
19566 #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
19567 #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
19568
19571 #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
19572 #define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
19573 #define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
19574
19576 #define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
19577 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
19578 #define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
19579
19581 #define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
19582 #define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
19583 #define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
19584
19587 #define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
19588 #define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
19589 #define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
19590
19593 #define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
19594 #define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
19595 #define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
19596
19598 #define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
19599 #define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
19600 #define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
19601
19603 #define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
19604 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
19605 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
19606
19608 #define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
19609 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
19610 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
19611
19613 #define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
19614 #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
19615 #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
19616
19618 #define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
19619 #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
19620 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
19621
19623 #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
19624
19628 #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
19629 #define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
19630
19632 #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
19633
19637 #define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
19638 #define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
19639
19641 #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
19642 #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
19643 #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
19644
19646 #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
19647
19651 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)
19652 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
19653
19655 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
19656 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
19657 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
19658
19660 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
19661 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)
19662 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
19663
19665 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
19666 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
19667 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
19668
19670 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
19671
19673 /* The count of FLEXSPI_AHBRXBUFCR0 */
19674 #define FLEXSPI_AHBRXBUFCR0_COUNT (4U)
19675
19678 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
19679 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
19680
19682 #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
19683
19685 /* The count of FLEXSPI_FLSHCR0 */
19686 #define FLEXSPI_FLSHCR0_COUNT (4U)
19687
19690 #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
19691 #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
19692
19694 #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
19695 #define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
19696 #define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
19697
19699 #define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
19700 #define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
19701 #define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
19702
19704 #define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
19705 #define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
19706 #define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
19707
19709 #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
19710 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
19711 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
19712
19716 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
19717 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
19718 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
19719
19724 #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
19725
19727 /* The count of FLEXSPI_FLSHCR1 */
19728 #define FLEXSPI_FLSHCR1_COUNT (4U)
19729
19732 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
19733 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
19734
19736 #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
19737 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
19738 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
19739
19741 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
19742 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
19743 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
19744
19746 #define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
19747 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
19748 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
19749
19751 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
19752 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
19753 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
19754 #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
19755 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
19756 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
19757
19767 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
19768 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
19769 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
19770
19773 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
19774
19776 /* The count of FLEXSPI_FLSHCR2 */
19777 #define FLEXSPI_FLSHCR2_COUNT (4U)
19778
19781 #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
19782 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
19783
19789 #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
19790 #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
19791 #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
19792
19797 #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
19798 #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
19799 #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
19800
19805 #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
19806
19810 #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
19811 #define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
19812
19814 #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
19815
19819 #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
19820 #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
19821
19823 #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
19824 #define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
19825 #define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
19826
19828 #define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
19829 #define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
19830 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
19831
19833 #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
19834 #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
19835 #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
19836
19840 #define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
19841
19845 #define FLEXSPI_IPCMD_TRG_MASK (0x1U)
19846 #define FLEXSPI_IPCMD_TRG_SHIFT (0U)
19847
19849 #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
19850
19854 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
19855 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
19856
19858 #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
19859 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
19860 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
19861
19865 #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
19866 #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)
19867 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
19868
19870 #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
19871
19875 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
19876 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
19877
19879 #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
19880 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
19881 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
19882
19886 #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
19887 #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)
19888 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
19889
19891 #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
19892
19896 #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
19897 #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
19898
19900 #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
19901 #define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
19902 #define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
19903
19908 #define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
19909 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
19910 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
19911
19913 #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
19914 #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
19915 #define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
19916
19918 #define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
19919 #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
19920 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
19921
19923 #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
19924
19926 /* The count of FLEXSPI_DLLCR */
19927 #define FLEXSPI_DLLCR_COUNT (2U)
19928
19931 #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
19932 #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
19933
19936 #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
19937 #define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
19938 #define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
19939
19944 #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
19945 #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
19946 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
19947
19954 #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
19955
19959 #define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
19960 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
19961
19964 #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
19965 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
19966 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
19967
19976 #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
19977 #define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
19978 #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
19979
19982 #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
19983 #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
19984 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
19985
19996 #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
19997
20001 #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
20002 #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
20003
20005 #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
20006 #define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
20007 #define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
20008
20010 #define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
20011 #define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
20012 #define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
20013
20015 #define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
20016 #define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
20017 #define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
20018
20020 #define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
20021 #define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
20022 #define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
20023
20025 #define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
20026 #define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
20027 #define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
20028
20030 #define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
20031 #define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
20032 #define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
20033
20035 #define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
20036 #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
20037 #define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
20038
20040 #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
20041
20045 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
20046 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
20047
20049 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
20050 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
20051 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
20052
20054 #define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
20055 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
20056 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
20057
20059 #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
20060
20064 #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
20065 #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
20066
20068 #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
20069 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
20070 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
20071
20073 #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
20074
20078 #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
20079 #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
20080
20082 #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
20083 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
20084 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
20085
20087 #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
20088
20092 #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
20093 #define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
20094
20096 #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
20097
20099 /* The count of FLEXSPI_RFDR */
20100 #define FLEXSPI_RFDR_COUNT (32U)
20101
20104 #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
20105 #define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
20106
20108 #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
20109
20111 /* The count of FLEXSPI_TFDR */
20112 #define FLEXSPI_TFDR_COUNT (32U)
20113
20116 #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
20117 #define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
20118
20120 #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
20121 #define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
20122 #define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
20123
20125 #define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
20126 #define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
20127 #define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
20128
20130 #define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
20131 #define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
20132 #define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
20133
20135 #define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
20136 #define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
20137 #define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
20138
20140 #define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
20141 #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
20142 #define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
20143
20145 #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
20146
20148 /* The count of FLEXSPI_LUT */
20149 #define FLEXSPI_LUT_COUNT (64U)
20150
20151 /* end of group FLEXSPI_Register_Masks */
20155
20156
20157 /* FLEXSPI - Peripheral instance base addresses */
20159 #define FLEXSPI_BASE (0x402A8000u)
20160
20161 #define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
20162
20163 #define FLEXSPI2_BASE (0x402A4000u)
20164
20165 #define FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE)
20166
20167 #define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE, 0u, FLEXSPI2_BASE }
20168
20169 #define FLEXSPI_BASE_PTRS { FLEXSPI, (FLEXSPI_Type *)0u, FLEXSPI2 }
20170
20171 #define FLEXSPI_IRQS { FLEXSPI_IRQn, NotAvail_IRQn, FLEXSPI2_IRQn }
20172 /* FlexSPI AMBA address. */
20173 #define FlexSPI_AMBA_BASE (0x60000000U)
20174 /* FlexSPI ASFM address. */
20175 #define FlexSPI_ASFM_BASE (0x60000000U)
20176 /* Base Address of AHB address space mapped to IP RX FIFO. */
20177 #define FlexSPI_ARDF_BASE (0x7FC00000U)
20178 /* Base Address of AHB address space mapped to IP TX FIFO. */
20179 #define FlexSPI_ATDF_BASE (0x7F800000U)
20180 /* FlexSPI2 AMBA address. */
20181 #define FlexSPI2_AMBA_BASE (0x70000000U)
20182 /* FlexSPI ASFM address. */
20183 #define FlexSPI2_ASFM_BASE (0x70000000U)
20184 /* Base Address of AHB address space mapped to IP RX FIFO. */
20185 #define FlexSPI2_ARDF_BASE (0x7F400000U)
20186 /* Base Address of AHB address space mapped to IP TX FIFO. */
20187 #define FlexSPI2_ATDF_BASE (0x7F000000U)
20188
20189 /* end of group FLEXSPI_Peripheral_Access_Layer */
20193
20194
20195 /* ----------------------------------------------------------------------------
20196 -- GPC Peripheral Access Layer
20197 ---------------------------------------------------------------------------- */
20198
20205 typedef struct {
20206 __IO uint32_t CNTR;
20207 uint8_t RESERVED_0[4];
20208 __IO uint32_t IMR[4];
20209 __I uint32_t ISR[4];
20210 uint8_t RESERVED_1[12];
20211 __IO uint32_t IMR5;
20212 __I uint32_t ISR5;
20213 } GPC_Type;
20214
20215 /* ----------------------------------------------------------------------------
20216 -- GPC Register Masks
20217 ---------------------------------------------------------------------------- */
20218
20226 #define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
20227 #define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
20228
20232 #define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
20233 #define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
20234 #define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
20235
20239 #define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
20240 #define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
20241 #define GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
20242
20246 #define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
20247
20251 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
20252 #define GPC_IMR_IMR1_SHIFT (0U)
20253 #define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
20254 #define GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
20255 #define GPC_IMR_IMR2_SHIFT (0U)
20256 #define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
20257 #define GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
20258 #define GPC_IMR_IMR3_SHIFT (0U)
20259 #define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
20260 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
20261 #define GPC_IMR_IMR4_SHIFT (0U)
20262 #define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
20263
20265 /* The count of GPC_IMR */
20266 #define GPC_IMR_COUNT (4U)
20267
20270 #define GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
20271 #define GPC_ISR_ISR1_SHIFT (0U)
20272 #define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
20273 #define GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
20274 #define GPC_ISR_ISR2_SHIFT (0U)
20275 #define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
20276 #define GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
20277 #define GPC_ISR_ISR3_SHIFT (0U)
20278 #define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
20279 #define GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
20280 #define GPC_ISR_ISR4_SHIFT (0U)
20281 #define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
20282
20284 /* The count of GPC_ISR */
20285 #define GPC_ISR_COUNT (4U)
20286
20289 #define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
20290 #define GPC_IMR5_IMR5_SHIFT (0U)
20291 #define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
20292
20296 #define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU)
20297 #define GPC_ISR5_ISR4_SHIFT (0U)
20298 #define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)
20299 /* end of group GPC_Register_Masks */
20305
20306
20307 /* GPC - Peripheral instance base addresses */
20309 #define GPC_BASE (0x400F4000u)
20310
20311 #define GPC ((GPC_Type *)GPC_BASE)
20312
20313 #define GPC_BASE_ADDRS { GPC_BASE }
20314
20315 #define GPC_BASE_PTRS { GPC }
20316
20317 #define GPC_IRQS { GPC_IRQn }
20318 /* end of group GPC_Peripheral_Access_Layer */
20322
20323
20324 /* ----------------------------------------------------------------------------
20325 -- GPIO Peripheral Access Layer
20326 ---------------------------------------------------------------------------- */
20327
20334 typedef struct {
20335 __IO uint32_t DR;
20336 __IO uint32_t GDIR;
20337 __I uint32_t PSR;
20338 __IO uint32_t ICR1;
20339 __IO uint32_t ICR2;
20340 __IO uint32_t IMR;
20341 __IO uint32_t ISR;
20342 __IO uint32_t EDGE_SEL;
20343 uint8_t RESERVED_0[100];
20344 __O uint32_t DR_SET;
20345 __O uint32_t DR_CLEAR;
20346 __O uint32_t DR_TOGGLE;
20347 } GPIO_Type;
20348
20349 /* ----------------------------------------------------------------------------
20350 -- GPIO Register Masks
20351 ---------------------------------------------------------------------------- */
20352
20360 #define GPIO_DR_DR_MASK (0xFFFFFFFFU)
20361 #define GPIO_DR_DR_SHIFT (0U)
20362
20364 #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
20365
20369 #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
20370 #define GPIO_GDIR_GDIR_SHIFT (0U)
20371
20373 #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
20374
20378 #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
20379 #define GPIO_PSR_PSR_SHIFT (0U)
20380
20382 #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
20383
20387 #define GPIO_ICR1_ICR0_MASK (0x3U)
20388 #define GPIO_ICR1_ICR0_SHIFT (0U)
20389
20395 #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
20396 #define GPIO_ICR1_ICR1_MASK (0xCU)
20397 #define GPIO_ICR1_ICR1_SHIFT (2U)
20398
20404 #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
20405 #define GPIO_ICR1_ICR2_MASK (0x30U)
20406 #define GPIO_ICR1_ICR2_SHIFT (4U)
20407
20413 #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
20414 #define GPIO_ICR1_ICR3_MASK (0xC0U)
20415 #define GPIO_ICR1_ICR3_SHIFT (6U)
20416
20422 #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
20423 #define GPIO_ICR1_ICR4_MASK (0x300U)
20424 #define GPIO_ICR1_ICR4_SHIFT (8U)
20425
20431 #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
20432 #define GPIO_ICR1_ICR5_MASK (0xC00U)
20433 #define GPIO_ICR1_ICR5_SHIFT (10U)
20434
20440 #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
20441 #define GPIO_ICR1_ICR6_MASK (0x3000U)
20442 #define GPIO_ICR1_ICR6_SHIFT (12U)
20443
20449 #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
20450 #define GPIO_ICR1_ICR7_MASK (0xC000U)
20451 #define GPIO_ICR1_ICR7_SHIFT (14U)
20452
20458 #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
20459 #define GPIO_ICR1_ICR8_MASK (0x30000U)
20460 #define GPIO_ICR1_ICR8_SHIFT (16U)
20461
20467 #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
20468 #define GPIO_ICR1_ICR9_MASK (0xC0000U)
20469 #define GPIO_ICR1_ICR9_SHIFT (18U)
20470
20476 #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
20477 #define GPIO_ICR1_ICR10_MASK (0x300000U)
20478 #define GPIO_ICR1_ICR10_SHIFT (20U)
20479
20485 #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
20486 #define GPIO_ICR1_ICR11_MASK (0xC00000U)
20487 #define GPIO_ICR1_ICR11_SHIFT (22U)
20488
20494 #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
20495 #define GPIO_ICR1_ICR12_MASK (0x3000000U)
20496 #define GPIO_ICR1_ICR12_SHIFT (24U)
20497
20503 #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
20504 #define GPIO_ICR1_ICR13_MASK (0xC000000U)
20505 #define GPIO_ICR1_ICR13_SHIFT (26U)
20506
20512 #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
20513 #define GPIO_ICR1_ICR14_MASK (0x30000000U)
20514 #define GPIO_ICR1_ICR14_SHIFT (28U)
20515
20521 #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
20522 #define GPIO_ICR1_ICR15_MASK (0xC0000000U)
20523 #define GPIO_ICR1_ICR15_SHIFT (30U)
20524
20530 #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
20531
20535 #define GPIO_ICR2_ICR16_MASK (0x3U)
20536 #define GPIO_ICR2_ICR16_SHIFT (0U)
20537
20543 #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
20544 #define GPIO_ICR2_ICR17_MASK (0xCU)
20545 #define GPIO_ICR2_ICR17_SHIFT (2U)
20546
20552 #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
20553 #define GPIO_ICR2_ICR18_MASK (0x30U)
20554 #define GPIO_ICR2_ICR18_SHIFT (4U)
20555
20561 #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
20562 #define GPIO_ICR2_ICR19_MASK (0xC0U)
20563 #define GPIO_ICR2_ICR19_SHIFT (6U)
20564
20570 #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
20571 #define GPIO_ICR2_ICR20_MASK (0x300U)
20572 #define GPIO_ICR2_ICR20_SHIFT (8U)
20573
20579 #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
20580 #define GPIO_ICR2_ICR21_MASK (0xC00U)
20581 #define GPIO_ICR2_ICR21_SHIFT (10U)
20582
20588 #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
20589 #define GPIO_ICR2_ICR22_MASK (0x3000U)
20590 #define GPIO_ICR2_ICR22_SHIFT (12U)
20591
20597 #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
20598 #define GPIO_ICR2_ICR23_MASK (0xC000U)
20599 #define GPIO_ICR2_ICR23_SHIFT (14U)
20600
20606 #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
20607 #define GPIO_ICR2_ICR24_MASK (0x30000U)
20608 #define GPIO_ICR2_ICR24_SHIFT (16U)
20609
20615 #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
20616 #define GPIO_ICR2_ICR25_MASK (0xC0000U)
20617 #define GPIO_ICR2_ICR25_SHIFT (18U)
20618
20624 #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
20625 #define GPIO_ICR2_ICR26_MASK (0x300000U)
20626 #define GPIO_ICR2_ICR26_SHIFT (20U)
20627
20633 #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
20634 #define GPIO_ICR2_ICR27_MASK (0xC00000U)
20635 #define GPIO_ICR2_ICR27_SHIFT (22U)
20636
20642 #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
20643 #define GPIO_ICR2_ICR28_MASK (0x3000000U)
20644 #define GPIO_ICR2_ICR28_SHIFT (24U)
20645
20651 #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
20652 #define GPIO_ICR2_ICR29_MASK (0xC000000U)
20653 #define GPIO_ICR2_ICR29_SHIFT (26U)
20654
20660 #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
20661 #define GPIO_ICR2_ICR30_MASK (0x30000000U)
20662 #define GPIO_ICR2_ICR30_SHIFT (28U)
20663
20669 #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
20670 #define GPIO_ICR2_ICR31_MASK (0xC0000000U)
20671 #define GPIO_ICR2_ICR31_SHIFT (30U)
20672
20678 #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
20679
20683 #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
20684 #define GPIO_IMR_IMR_SHIFT (0U)
20685
20687 #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
20688
20692 #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
20693 #define GPIO_ISR_ISR_SHIFT (0U)
20694
20696 #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
20697
20701 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
20702 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
20703
20705 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
20706
20710 #define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
20711 #define GPIO_DR_SET_DR_SET_SHIFT (0U)
20712
20714 #define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
20715
20719 #define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
20720 #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
20721
20723 #define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
20724
20728 #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
20729 #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
20730
20732 #define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
20733 /* end of group GPIO_Register_Masks */
20739
20740
20741 /* GPIO - Peripheral instance base addresses */
20743 #define GPIO1_BASE (0x401B8000u)
20744
20745 #define GPIO1 ((GPIO_Type *)GPIO1_BASE)
20746
20747 #define GPIO2_BASE (0x401BC000u)
20748
20749 #define GPIO2 ((GPIO_Type *)GPIO2_BASE)
20750
20751 #define GPIO3_BASE (0x401C0000u)
20752
20753 #define GPIO3 ((GPIO_Type *)GPIO3_BASE)
20754
20755 #define GPIO4_BASE (0x401C4000u)
20756
20757 #define GPIO4 ((GPIO_Type *)GPIO4_BASE)
20758
20759 #define GPIO5_BASE (0x400C0000u)
20760
20761 #define GPIO5 ((GPIO_Type *)GPIO5_BASE)
20762
20763 #define GPIO6_BASE (0x42000000u)
20764
20765 #define GPIO6 ((GPIO_Type *)GPIO6_BASE)
20766
20767 #define GPIO7_BASE (0x42004000u)
20768
20769 #define GPIO7 ((GPIO_Type *)GPIO7_BASE)
20770
20771 #define GPIO8_BASE (0x42008000u)
20772
20773 #define GPIO8 ((GPIO_Type *)GPIO8_BASE)
20774
20775 #define GPIO9_BASE (0x4200C000u)
20776
20777 #define GPIO9 ((GPIO_Type *)GPIO9_BASE)
20778
20779 #define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE }
20780
20781 #define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 }
20782
20783 #define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
20784 #define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }
20785 #define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }
20786 /* end of group GPIO_Peripheral_Access_Layer */
20790
20791
20792 /* ----------------------------------------------------------------------------
20793 -- GPT Peripheral Access Layer
20794 ---------------------------------------------------------------------------- */
20795
20802 typedef struct {
20803 __IO uint32_t CR;
20804 __IO uint32_t PR;
20805 __IO uint32_t SR;
20806 __IO uint32_t IR;
20807 __IO uint32_t OCR[3];
20808 __I uint32_t ICR[2];
20809 __I uint32_t CNT;
20810 } GPT_Type;
20811
20812 /* ----------------------------------------------------------------------------
20813 -- GPT Register Masks
20814 ---------------------------------------------------------------------------- */
20815
20823 #define GPT_CR_EN_MASK (0x1U)
20824 #define GPT_CR_EN_SHIFT (0U)
20825
20829 #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
20830 #define GPT_CR_ENMOD_MASK (0x2U)
20831 #define GPT_CR_ENMOD_SHIFT (1U)
20832
20836 #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
20837 #define GPT_CR_DBGEN_MASK (0x4U)
20838 #define GPT_CR_DBGEN_SHIFT (2U)
20839
20843 #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
20844 #define GPT_CR_WAITEN_MASK (0x8U)
20845 #define GPT_CR_WAITEN_SHIFT (3U)
20846
20850 #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
20851 #define GPT_CR_DOZEEN_MASK (0x10U)
20852 #define GPT_CR_DOZEEN_SHIFT (4U)
20853
20857 #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
20858 #define GPT_CR_STOPEN_MASK (0x20U)
20859 #define GPT_CR_STOPEN_SHIFT (5U)
20860
20864 #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
20865 #define GPT_CR_CLKSRC_MASK (0x1C0U)
20866 #define GPT_CR_CLKSRC_SHIFT (6U)
20867
20875 #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
20876 #define GPT_CR_FRR_MASK (0x200U)
20877 #define GPT_CR_FRR_SHIFT (9U)
20878
20882 #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
20883 #define GPT_CR_EN_24M_MASK (0x400U)
20884 #define GPT_CR_EN_24M_SHIFT (10U)
20885
20889 #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
20890 #define GPT_CR_SWR_MASK (0x8000U)
20891 #define GPT_CR_SWR_SHIFT (15U)
20892
20896 #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
20897 #define GPT_CR_IM1_MASK (0x30000U)
20898 #define GPT_CR_IM1_SHIFT (16U)
20899 #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
20900 #define GPT_CR_IM2_MASK (0xC0000U)
20901 #define GPT_CR_IM2_SHIFT (18U)
20902
20908 #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
20909 #define GPT_CR_OM1_MASK (0x700000U)
20910 #define GPT_CR_OM1_SHIFT (20U)
20911 #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
20912 #define GPT_CR_OM2_MASK (0x3800000U)
20913 #define GPT_CR_OM2_SHIFT (23U)
20914 #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
20915 #define GPT_CR_OM3_MASK (0x1C000000U)
20916 #define GPT_CR_OM3_SHIFT (26U)
20917
20924 #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
20925 #define GPT_CR_FO1_MASK (0x20000000U)
20926 #define GPT_CR_FO1_SHIFT (29U)
20927 #define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
20928 #define GPT_CR_FO2_MASK (0x40000000U)
20929 #define GPT_CR_FO2_SHIFT (30U)
20930 #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
20931 #define GPT_CR_FO3_MASK (0x80000000U)
20932 #define GPT_CR_FO3_SHIFT (31U)
20933
20937 #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
20938
20942 #define GPT_PR_PRESCALER_MASK (0xFFFU)
20943 #define GPT_PR_PRESCALER_SHIFT (0U)
20944
20949 #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
20950 #define GPT_PR_PRESCALER24M_MASK (0xF000U)
20951 #define GPT_PR_PRESCALER24M_SHIFT (12U)
20952
20957 #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
20958
20962 #define GPT_SR_OF1_MASK (0x1U)
20963 #define GPT_SR_OF1_SHIFT (0U)
20964 #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
20965 #define GPT_SR_OF2_MASK (0x2U)
20966 #define GPT_SR_OF2_SHIFT (1U)
20967 #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
20968 #define GPT_SR_OF3_MASK (0x4U)
20969 #define GPT_SR_OF3_SHIFT (2U)
20970
20974 #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
20975 #define GPT_SR_IF1_MASK (0x8U)
20976 #define GPT_SR_IF1_SHIFT (3U)
20977 #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
20978 #define GPT_SR_IF2_MASK (0x10U)
20979 #define GPT_SR_IF2_SHIFT (4U)
20980
20984 #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
20985 #define GPT_SR_ROV_MASK (0x20U)
20986 #define GPT_SR_ROV_SHIFT (5U)
20987
20991 #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
20992
20996 #define GPT_IR_OF1IE_MASK (0x1U)
20997 #define GPT_IR_OF1IE_SHIFT (0U)
20998 #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
20999 #define GPT_IR_OF2IE_MASK (0x2U)
21000 #define GPT_IR_OF2IE_SHIFT (1U)
21001 #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
21002 #define GPT_IR_OF3IE_MASK (0x4U)
21003 #define GPT_IR_OF3IE_SHIFT (2U)
21004
21008 #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
21009 #define GPT_IR_IF1IE_MASK (0x8U)
21010 #define GPT_IR_IF1IE_SHIFT (3U)
21011 #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
21012 #define GPT_IR_IF2IE_MASK (0x10U)
21013 #define GPT_IR_IF2IE_SHIFT (4U)
21014
21018 #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
21019 #define GPT_IR_ROVIE_MASK (0x20U)
21020 #define GPT_IR_ROVIE_SHIFT (5U)
21021
21025 #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
21026
21030 #define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
21031 #define GPT_OCR_COMP_SHIFT (0U)
21032 #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
21033
21035 /* The count of GPT_OCR */
21036 #define GPT_OCR_COUNT (3U)
21037
21040 #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
21041 #define GPT_ICR_CAPT_SHIFT (0U)
21042 #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
21043
21045 /* The count of GPT_ICR */
21046 #define GPT_ICR_COUNT (2U)
21047
21050 #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
21051 #define GPT_CNT_COUNT_SHIFT (0U)
21052 #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
21053 /* end of group GPT_Register_Masks */
21059
21060
21061 /* GPT - Peripheral instance base addresses */
21063 #define GPT1_BASE (0x401EC000u)
21064
21065 #define GPT1 ((GPT_Type *)GPT1_BASE)
21066
21067 #define GPT2_BASE (0x401F0000u)
21068
21069 #define GPT2 ((GPT_Type *)GPT2_BASE)
21070
21071 #define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }
21072
21073 #define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }
21074
21075 #define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
21076 /* end of group GPT_Peripheral_Access_Layer */
21080
21081
21082 /* ----------------------------------------------------------------------------
21083 -- I2S Peripheral Access Layer
21084 ---------------------------------------------------------------------------- */
21085
21092 typedef struct {
21093 __I uint32_t VERID;
21094 __I uint32_t PARAM;
21095 __IO uint32_t TCSR;
21096 __IO uint32_t TCR1;
21097 __IO uint32_t TCR2;
21098 __IO uint32_t TCR3;
21099 __IO uint32_t TCR4;
21100 __IO uint32_t TCR5;
21101 __O uint32_t TDR[4];
21102 uint8_t RESERVED_0[16];
21103 __I uint32_t TFR[4];
21104 uint8_t RESERVED_1[16];
21105 __IO uint32_t TMR;
21106 uint8_t RESERVED_2[36];
21107 __IO uint32_t RCSR;
21108 __IO uint32_t RCR1;
21109 __IO uint32_t RCR2;
21110 __IO uint32_t RCR3;
21111 __IO uint32_t RCR4;
21112 __IO uint32_t RCR5;
21113 __I uint32_t RDR[4];
21114 uint8_t RESERVED_3[16];
21115 __I uint32_t RFR[4];
21116 uint8_t RESERVED_4[16];
21117 __IO uint32_t RMR;
21118 } I2S_Type;
21119
21120 /* ----------------------------------------------------------------------------
21121 -- I2S Register Masks
21122 ---------------------------------------------------------------------------- */
21123
21131 #define I2S_VERID_FEATURE_MASK (0xFFFFU)
21132 #define I2S_VERID_FEATURE_SHIFT (0U)
21133
21136 #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
21137 #define I2S_VERID_MINOR_MASK (0xFF0000U)
21138 #define I2S_VERID_MINOR_SHIFT (16U)
21139
21141 #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
21142 #define I2S_VERID_MAJOR_MASK (0xFF000000U)
21143 #define I2S_VERID_MAJOR_SHIFT (24U)
21144
21146 #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
21147
21151 #define I2S_PARAM_DATALINE_MASK (0xFU)
21152 #define I2S_PARAM_DATALINE_SHIFT (0U)
21153
21155 #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
21156 #define I2S_PARAM_FIFO_MASK (0xF00U)
21157 #define I2S_PARAM_FIFO_SHIFT (8U)
21158
21160 #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
21161 #define I2S_PARAM_FRAME_MASK (0xF0000U)
21162 #define I2S_PARAM_FRAME_SHIFT (16U)
21163
21165 #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
21166
21170 #define I2S_TCSR_FRDE_MASK (0x1U)
21171 #define I2S_TCSR_FRDE_SHIFT (0U)
21172
21176 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
21177 #define I2S_TCSR_FWDE_MASK (0x2U)
21178 #define I2S_TCSR_FWDE_SHIFT (1U)
21179
21183 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
21184 #define I2S_TCSR_FRIE_MASK (0x100U)
21185 #define I2S_TCSR_FRIE_SHIFT (8U)
21186
21190 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
21191 #define I2S_TCSR_FWIE_MASK (0x200U)
21192 #define I2S_TCSR_FWIE_SHIFT (9U)
21193
21197 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
21198 #define I2S_TCSR_FEIE_MASK (0x400U)
21199 #define I2S_TCSR_FEIE_SHIFT (10U)
21200
21204 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
21205 #define I2S_TCSR_SEIE_MASK (0x800U)
21206 #define I2S_TCSR_SEIE_SHIFT (11U)
21207
21211 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
21212 #define I2S_TCSR_WSIE_MASK (0x1000U)
21213 #define I2S_TCSR_WSIE_SHIFT (12U)
21214
21218 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
21219 #define I2S_TCSR_FRF_MASK (0x10000U)
21220 #define I2S_TCSR_FRF_SHIFT (16U)
21221
21225 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
21226 #define I2S_TCSR_FWF_MASK (0x20000U)
21227 #define I2S_TCSR_FWF_SHIFT (17U)
21228
21232 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
21233 #define I2S_TCSR_FEF_MASK (0x40000U)
21234 #define I2S_TCSR_FEF_SHIFT (18U)
21235
21239 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
21240 #define I2S_TCSR_SEF_MASK (0x80000U)
21241 #define I2S_TCSR_SEF_SHIFT (19U)
21242
21246 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
21247 #define I2S_TCSR_WSF_MASK (0x100000U)
21248 #define I2S_TCSR_WSF_SHIFT (20U)
21249
21253 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
21254 #define I2S_TCSR_SR_MASK (0x1000000U)
21255 #define I2S_TCSR_SR_SHIFT (24U)
21256
21260 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
21261 #define I2S_TCSR_FR_MASK (0x2000000U)
21262 #define I2S_TCSR_FR_SHIFT (25U)
21263
21267 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
21268 #define I2S_TCSR_BCE_MASK (0x10000000U)
21269 #define I2S_TCSR_BCE_SHIFT (28U)
21270
21274 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
21275 #define I2S_TCSR_DBGE_MASK (0x20000000U)
21276 #define I2S_TCSR_DBGE_SHIFT (29U)
21277
21281 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
21282 #define I2S_TCSR_STOPE_MASK (0x40000000U)
21283 #define I2S_TCSR_STOPE_SHIFT (30U)
21284
21288 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
21289 #define I2S_TCSR_TE_MASK (0x80000000U)
21290 #define I2S_TCSR_TE_SHIFT (31U)
21291
21295 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
21296
21300 #define I2S_TCR1_TFW_MASK (0x1FU)
21301 #define I2S_TCR1_TFW_SHIFT (0U)
21302
21304 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
21305
21309 #define I2S_TCR2_DIV_MASK (0xFFU)
21310 #define I2S_TCR2_DIV_SHIFT (0U)
21311
21313 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
21314 #define I2S_TCR2_BCD_MASK (0x1000000U)
21315 #define I2S_TCR2_BCD_SHIFT (24U)
21316
21320 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
21321 #define I2S_TCR2_BCP_MASK (0x2000000U)
21322 #define I2S_TCR2_BCP_SHIFT (25U)
21323
21327 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
21328 #define I2S_TCR2_MSEL_MASK (0xC000000U)
21329 #define I2S_TCR2_MSEL_SHIFT (26U)
21330
21336 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
21337 #define I2S_TCR2_BCI_MASK (0x10000000U)
21338 #define I2S_TCR2_BCI_SHIFT (28U)
21339
21343 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
21344 #define I2S_TCR2_BCS_MASK (0x20000000U)
21345 #define I2S_TCR2_BCS_SHIFT (29U)
21346
21350 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
21351 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
21352 #define I2S_TCR2_SYNC_SHIFT (30U)
21353
21359 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
21360
21364 #define I2S_TCR3_WDFL_MASK (0x1FU)
21365 #define I2S_TCR3_WDFL_SHIFT (0U)
21366
21368 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
21369 #define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
21370 #define I2S_TCR3_TCE_SHIFT (16U)
21371
21373 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
21374 #define I2S_TCR3_CFR_MASK (0xF000000U)
21375 #define I2S_TCR3_CFR_SHIFT (24U)
21376
21378 #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
21379
21383 #define I2S_TCR4_FSD_MASK (0x1U)
21384 #define I2S_TCR4_FSD_SHIFT (0U)
21385
21389 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
21390 #define I2S_TCR4_FSP_MASK (0x2U)
21391 #define I2S_TCR4_FSP_SHIFT (1U)
21392
21396 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
21397 #define I2S_TCR4_ONDEM_MASK (0x4U)
21398 #define I2S_TCR4_ONDEM_SHIFT (2U)
21399
21403 #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
21404 #define I2S_TCR4_FSE_MASK (0x8U)
21405 #define I2S_TCR4_FSE_SHIFT (3U)
21406
21410 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
21411 #define I2S_TCR4_MF_MASK (0x10U)
21412 #define I2S_TCR4_MF_SHIFT (4U)
21413
21417 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
21418 #define I2S_TCR4_CHMOD_MASK (0x20U)
21419 #define I2S_TCR4_CHMOD_SHIFT (5U)
21420
21424 #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
21425 #define I2S_TCR4_SYWD_MASK (0x1F00U)
21426 #define I2S_TCR4_SYWD_SHIFT (8U)
21427
21429 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
21430 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
21431 #define I2S_TCR4_FRSZ_SHIFT (16U)
21432
21434 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
21435 #define I2S_TCR4_FPACK_MASK (0x3000000U)
21436 #define I2S_TCR4_FPACK_SHIFT (24U)
21437
21443 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
21444 #define I2S_TCR4_FCOMB_MASK (0xC000000U)
21445 #define I2S_TCR4_FCOMB_SHIFT (26U)
21446
21452 #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
21453 #define I2S_TCR4_FCONT_MASK (0x10000000U)
21454 #define I2S_TCR4_FCONT_SHIFT (28U)
21455
21459 #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
21460
21464 #define I2S_TCR5_FBT_MASK (0x1F00U)
21465 #define I2S_TCR5_FBT_SHIFT (8U)
21466
21468 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
21469 #define I2S_TCR5_W0W_MASK (0x1F0000U)
21470 #define I2S_TCR5_W0W_SHIFT (16U)
21471
21473 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
21474 #define I2S_TCR5_WNW_MASK (0x1F000000U)
21475 #define I2S_TCR5_WNW_SHIFT (24U)
21476
21478 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
21479
21483 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
21484 #define I2S_TDR_TDR_SHIFT (0U)
21485
21487 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
21488
21490 /* The count of I2S_TDR */
21491 #define I2S_TDR_COUNT (4U)
21492
21495 #define I2S_TFR_RFP_MASK (0x3FU)
21496 #define I2S_TFR_RFP_SHIFT (0U)
21497
21499 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
21500 #define I2S_TFR_WFP_MASK (0x3F0000U)
21501 #define I2S_TFR_WFP_SHIFT (16U)
21502
21504 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
21505 #define I2S_TFR_WCP_MASK (0x80000000U)
21506 #define I2S_TFR_WCP_SHIFT (31U)
21507
21511 #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
21512
21514 /* The count of I2S_TFR */
21515 #define I2S_TFR_COUNT (4U)
21516
21519 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
21520 #define I2S_TMR_TWM_SHIFT (0U)
21521
21525 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
21526
21530 #define I2S_RCSR_FRDE_MASK (0x1U)
21531 #define I2S_RCSR_FRDE_SHIFT (0U)
21532
21536 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
21537 #define I2S_RCSR_FWDE_MASK (0x2U)
21538 #define I2S_RCSR_FWDE_SHIFT (1U)
21539
21543 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
21544 #define I2S_RCSR_FRIE_MASK (0x100U)
21545 #define I2S_RCSR_FRIE_SHIFT (8U)
21546
21550 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
21551 #define I2S_RCSR_FWIE_MASK (0x200U)
21552 #define I2S_RCSR_FWIE_SHIFT (9U)
21553
21557 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
21558 #define I2S_RCSR_FEIE_MASK (0x400U)
21559 #define I2S_RCSR_FEIE_SHIFT (10U)
21560
21564 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
21565 #define I2S_RCSR_SEIE_MASK (0x800U)
21566 #define I2S_RCSR_SEIE_SHIFT (11U)
21567
21571 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
21572 #define I2S_RCSR_WSIE_MASK (0x1000U)
21573 #define I2S_RCSR_WSIE_SHIFT (12U)
21574
21578 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
21579 #define I2S_RCSR_FRF_MASK (0x10000U)
21580 #define I2S_RCSR_FRF_SHIFT (16U)
21581
21585 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
21586 #define I2S_RCSR_FWF_MASK (0x20000U)
21587 #define I2S_RCSR_FWF_SHIFT (17U)
21588
21592 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
21593 #define I2S_RCSR_FEF_MASK (0x40000U)
21594 #define I2S_RCSR_FEF_SHIFT (18U)
21595
21599 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
21600 #define I2S_RCSR_SEF_MASK (0x80000U)
21601 #define I2S_RCSR_SEF_SHIFT (19U)
21602
21606 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
21607 #define I2S_RCSR_WSF_MASK (0x100000U)
21608 #define I2S_RCSR_WSF_SHIFT (20U)
21609
21613 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
21614 #define I2S_RCSR_SR_MASK (0x1000000U)
21615 #define I2S_RCSR_SR_SHIFT (24U)
21616
21620 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
21621 #define I2S_RCSR_FR_MASK (0x2000000U)
21622 #define I2S_RCSR_FR_SHIFT (25U)
21623
21627 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
21628 #define I2S_RCSR_BCE_MASK (0x10000000U)
21629 #define I2S_RCSR_BCE_SHIFT (28U)
21630
21634 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
21635 #define I2S_RCSR_DBGE_MASK (0x20000000U)
21636 #define I2S_RCSR_DBGE_SHIFT (29U)
21637
21641 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
21642 #define I2S_RCSR_STOPE_MASK (0x40000000U)
21643 #define I2S_RCSR_STOPE_SHIFT (30U)
21644
21648 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
21649 #define I2S_RCSR_RE_MASK (0x80000000U)
21650 #define I2S_RCSR_RE_SHIFT (31U)
21651
21655 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
21656
21660 #define I2S_RCR1_RFW_MASK (0x1FU)
21661 #define I2S_RCR1_RFW_SHIFT (0U)
21662
21664 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
21665
21669 #define I2S_RCR2_DIV_MASK (0xFFU)
21670 #define I2S_RCR2_DIV_SHIFT (0U)
21671
21673 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
21674 #define I2S_RCR2_BCD_MASK (0x1000000U)
21675 #define I2S_RCR2_BCD_SHIFT (24U)
21676
21680 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
21681 #define I2S_RCR2_BCP_MASK (0x2000000U)
21682 #define I2S_RCR2_BCP_SHIFT (25U)
21683
21687 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
21688 #define I2S_RCR2_MSEL_MASK (0xC000000U)
21689 #define I2S_RCR2_MSEL_SHIFT (26U)
21690
21696 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
21697 #define I2S_RCR2_BCI_MASK (0x10000000U)
21698 #define I2S_RCR2_BCI_SHIFT (28U)
21699
21703 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
21704 #define I2S_RCR2_BCS_MASK (0x20000000U)
21705 #define I2S_RCR2_BCS_SHIFT (29U)
21706
21710 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
21711 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
21712 #define I2S_RCR2_SYNC_SHIFT (30U)
21713
21719 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
21720
21724 #define I2S_RCR3_WDFL_MASK (0x1FU)
21725 #define I2S_RCR3_WDFL_SHIFT (0U)
21726
21728 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
21729 #define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
21730 #define I2S_RCR3_RCE_SHIFT (16U)
21731
21733 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
21734 #define I2S_RCR3_CFR_MASK (0xF000000U)
21735 #define I2S_RCR3_CFR_SHIFT (24U)
21736
21738 #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
21739
21743 #define I2S_RCR4_FSD_MASK (0x1U)
21744 #define I2S_RCR4_FSD_SHIFT (0U)
21745
21749 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
21750 #define I2S_RCR4_FSP_MASK (0x2U)
21751 #define I2S_RCR4_FSP_SHIFT (1U)
21752
21756 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
21757 #define I2S_RCR4_ONDEM_MASK (0x4U)
21758 #define I2S_RCR4_ONDEM_SHIFT (2U)
21759
21763 #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
21764 #define I2S_RCR4_FSE_MASK (0x8U)
21765 #define I2S_RCR4_FSE_SHIFT (3U)
21766
21770 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
21771 #define I2S_RCR4_MF_MASK (0x10U)
21772 #define I2S_RCR4_MF_SHIFT (4U)
21773
21777 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
21778 #define I2S_RCR4_SYWD_MASK (0x1F00U)
21779 #define I2S_RCR4_SYWD_SHIFT (8U)
21780
21782 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
21783 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
21784 #define I2S_RCR4_FRSZ_SHIFT (16U)
21785
21787 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
21788 #define I2S_RCR4_FPACK_MASK (0x3000000U)
21789 #define I2S_RCR4_FPACK_SHIFT (24U)
21790
21796 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
21797 #define I2S_RCR4_FCOMB_MASK (0xC000000U)
21798 #define I2S_RCR4_FCOMB_SHIFT (26U)
21799
21805 #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
21806 #define I2S_RCR4_FCONT_MASK (0x10000000U)
21807 #define I2S_RCR4_FCONT_SHIFT (28U)
21808
21812 #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
21813
21817 #define I2S_RCR5_FBT_MASK (0x1F00U)
21818 #define I2S_RCR5_FBT_SHIFT (8U)
21819
21821 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
21822 #define I2S_RCR5_W0W_MASK (0x1F0000U)
21823 #define I2S_RCR5_W0W_SHIFT (16U)
21824
21826 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
21827 #define I2S_RCR5_WNW_MASK (0x1F000000U)
21828 #define I2S_RCR5_WNW_SHIFT (24U)
21829
21831 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
21832
21836 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
21837 #define I2S_RDR_RDR_SHIFT (0U)
21838
21840 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
21841
21843 /* The count of I2S_RDR */
21844 #define I2S_RDR_COUNT (4U)
21845
21848 #define I2S_RFR_RFP_MASK (0x3FU)
21849 #define I2S_RFR_RFP_SHIFT (0U)
21850
21852 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
21853 #define I2S_RFR_RCP_MASK (0x8000U)
21854 #define I2S_RFR_RCP_SHIFT (15U)
21855
21859 #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
21860 #define I2S_RFR_WFP_MASK (0x3F0000U)
21861 #define I2S_RFR_WFP_SHIFT (16U)
21862
21864 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
21865
21867 /* The count of I2S_RFR */
21868 #define I2S_RFR_COUNT (4U)
21869
21872 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
21873 #define I2S_RMR_RWM_SHIFT (0U)
21874
21878 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
21879 /* end of group I2S_Register_Masks */
21885
21886
21887 /* I2S - Peripheral instance base addresses */
21889 #define SAI1_BASE (0x40384000u)
21890
21891 #define SAI1 ((I2S_Type *)SAI1_BASE)
21892
21893 #define SAI2_BASE (0x40388000u)
21894
21895 #define SAI2 ((I2S_Type *)SAI2_BASE)
21896
21897 #define SAI3_BASE (0x4038C000u)
21898
21899 #define SAI3 ((I2S_Type *)SAI3_BASE)
21900
21901 #define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
21902
21903 #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
21904
21905 #define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
21906 #define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
21907 /* end of group I2S_Peripheral_Access_Layer */
21911
21912
21913 /* ----------------------------------------------------------------------------
21914 -- IOMUXC Peripheral Access Layer
21915 ---------------------------------------------------------------------------- */
21916
21923 typedef struct {
21924 uint8_t RESERVED_0[20];
21925 __IO uint32_t SW_MUX_CTL_PAD[124];
21926 __IO uint32_t SW_PAD_CTL_PAD[124];
21927 __IO uint32_t SELECT_INPUT[154];
21928 __IO uint32_t SW_MUX_CTL_PAD_1[22];
21929 __IO uint32_t SW_PAD_CTL_PAD_1[22];
21930 __IO uint32_t SELECT_INPUT_1[33];
21931 } IOMUXC_Type;
21932
21933 /* ----------------------------------------------------------------------------
21934 -- IOMUXC Register Masks
21935 ---------------------------------------------------------------------------- */
21936
21944 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
21945 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
21946
21954 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
21955 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
21956 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
21957
21961 #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
21962
21964 /* The count of IOMUXC_SW_MUX_CTL_PAD */
21965 #define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)
21966
21969 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
21970 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
21971
21975 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
21976 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)
21977 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)
21978
21988 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
21989 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)
21990 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)
21991
21997 #define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
21998 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)
21999 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)
22000
22004 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
22005 #define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)
22006 #define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)
22007
22011 #define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
22012 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)
22013 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)
22014
22018 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
22019 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)
22020 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)
22021
22027 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
22028 #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)
22029 #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)
22030
22034 #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
22035
22037 /* The count of IOMUXC_SW_PAD_CTL_PAD */
22038 #define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)
22039
22042 #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
22043 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
22044
22048 #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
22049
22051 /* The count of IOMUXC_SELECT_INPUT */
22052 #define IOMUXC_SELECT_INPUT_COUNT (154U)
22053
22056 #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK (0x7U)
22057 #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT (0U)
22058
22061 #define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK)
22062 #define IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK (0x10U)
22063 #define IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT (4U)
22064
22068 #define IOMUXC_SW_MUX_CTL_PAD_1_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK)
22069
22071 /* The count of IOMUXC_SW_MUX_CTL_PAD_1 */
22072 #define IOMUXC_SW_MUX_CTL_PAD_1_COUNT (22U)
22073
22076 #define IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK (0x1U)
22077 #define IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT (0U)
22078
22082 #define IOMUXC_SW_PAD_CTL_PAD_1_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK)
22083 #define IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK (0x38U)
22084 #define IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT (3U)
22085
22095 #define IOMUXC_SW_PAD_CTL_PAD_1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK)
22096 #define IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK (0xC0U)
22097 #define IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT (6U)
22098
22104 #define IOMUXC_SW_PAD_CTL_PAD_1_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK)
22105 #define IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK (0x800U)
22106 #define IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT (11U)
22107
22111 #define IOMUXC_SW_PAD_CTL_PAD_1_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK)
22112 #define IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK (0x1000U)
22113 #define IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT (12U)
22114
22118 #define IOMUXC_SW_PAD_CTL_PAD_1_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK)
22119 #define IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK (0x2000U)
22120 #define IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT (13U)
22121
22125 #define IOMUXC_SW_PAD_CTL_PAD_1_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK)
22126 #define IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK (0xC000U)
22127 #define IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT (14U)
22128
22134 #define IOMUXC_SW_PAD_CTL_PAD_1_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK)
22135 #define IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK (0x10000U)
22136 #define IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT (16U)
22137
22141 #define IOMUXC_SW_PAD_CTL_PAD_1_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK)
22142
22144 /* The count of IOMUXC_SW_PAD_CTL_PAD_1 */
22145 #define IOMUXC_SW_PAD_CTL_PAD_1_COUNT (22U)
22146
22149 #define IOMUXC_SELECT_INPUT_1_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
22150 #define IOMUXC_SELECT_INPUT_1_DAISY_SHIFT (0U)
22151
22156 #define IOMUXC_SELECT_INPUT_1_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_1_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_1_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
22157
22159 /* The count of IOMUXC_SELECT_INPUT_1 */
22160 #define IOMUXC_SELECT_INPUT_1_COUNT (33U)
22161
22162 /* end of group IOMUXC_Register_Masks */
22166
22167
22168 /* IOMUXC - Peripheral instance base addresses */
22170 #define IOMUXC_BASE (0x401F8000u)
22171
22172 #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
22173
22174 #define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
22175
22176 #define IOMUXC_BASE_PTRS { IOMUXC }
22177 /* end of group IOMUXC_Peripheral_Access_Layer */
22181
22182
22183 /* ----------------------------------------------------------------------------
22184 -- IOMUXC_GPR Peripheral Access Layer
22185 ---------------------------------------------------------------------------- */
22186
22193 typedef struct {
22194 uint32_t GPR0;
22195 __IO uint32_t GPR1;
22196 __IO uint32_t GPR2;
22197 __IO uint32_t GPR3;
22198 __IO uint32_t GPR4;
22199 __IO uint32_t GPR5;
22200 __IO uint32_t GPR6;
22201 __IO uint32_t GPR7;
22202 __IO uint32_t GPR8;
22203 uint32_t GPR9;
22204 __IO uint32_t GPR10;
22205 __IO uint32_t GPR11;
22206 __IO uint32_t GPR12;
22207 __IO uint32_t GPR13;
22208 __IO uint32_t GPR14;
22209 uint32_t GPR15;
22210 __IO uint32_t GPR16;
22211 __IO uint32_t GPR17;
22212 __IO uint32_t GPR18;
22213 __IO uint32_t GPR19;
22214 __IO uint32_t GPR20;
22215 __IO uint32_t GPR21;
22216 __IO uint32_t GPR22;
22217 __IO uint32_t GPR23;
22218 __IO uint32_t GPR24;
22219 __IO uint32_t GPR25;
22220 __IO uint32_t GPR26;
22221 __IO uint32_t GPR27;
22222 __IO uint32_t GPR28;
22223 __IO uint32_t GPR29;
22224 __IO uint32_t GPR30;
22225 __IO uint32_t GPR31;
22226 __IO uint32_t GPR32;
22227 __IO uint32_t GPR33;
22228 __IO uint32_t GPR34;
22229 } IOMUXC_GPR_Type;
22230
22231 /* ----------------------------------------------------------------------------
22232 -- IOMUXC_GPR Register Masks
22233 ---------------------------------------------------------------------------- */
22234
22242 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
22243 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
22244
22254 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
22255 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
22256 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
22257
22267 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
22268 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
22269 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
22270
22276 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
22277 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
22278 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
22279
22285 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
22286 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
22287 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
22288
22294 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
22295 #define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
22296 #define IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
22297
22301 #define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
22302 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)
22303 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)
22304
22309 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
22310 #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U)
22311 #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U)
22312
22317 #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK)
22318 #define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)
22319 #define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)
22320
22324 #define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
22325 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)
22326 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)
22327
22331 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
22332 #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U)
22333 #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U)
22334
22338 #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK)
22339 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
22340 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
22341
22345 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
22346 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
22347 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
22348
22352 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
22353 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
22354 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
22355
22359 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
22360 #define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
22361 #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
22362
22366 #define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
22367 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)
22368 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)
22369
22373 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
22374 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
22375 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
22376
22380 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
22381
22385 #define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK (0x1U)
22386 #define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT (0U)
22387
22391 #define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK)
22392 #define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK (0x2U)
22393 #define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT (1U)
22394
22398 #define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK)
22399 #define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK (0x4U)
22400 #define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT (2U)
22401
22405 #define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK)
22406 #define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK (0x8U)
22407 #define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT (3U)
22408
22412 #define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK)
22413 #define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK (0x10U)
22414 #define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT (4U)
22415
22419 #define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK)
22420 #define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK (0x20U)
22421 #define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT (5U)
22422
22426 #define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK)
22427 #define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK (0x40U)
22428 #define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT (6U)
22429
22433 #define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK)
22434 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
22435 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
22436
22440 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
22441 #define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U)
22442 #define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U)
22443
22447 #define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK)
22448 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
22449 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
22450
22454 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
22455 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
22456 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
22457
22715 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
22716 #define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
22717 #define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
22718
22722 #define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
22723 #define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
22724 #define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
22725
22729 #define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
22730 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
22731 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
22732
22736 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
22737 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
22738 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
22739
22743 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
22744 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
22745 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
22746
22750 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
22751 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
22752 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
22753
22757 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
22758 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
22759 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
22760
22764 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
22765
22769 #define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)
22770 #define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)
22771 #define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
22772 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
22773 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
22774
22778 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
22779 #define IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK (0xF00U)
22780 #define IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT (8U)
22781 #define IOMUXC_GPR_GPR3_OCRAM2_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK)
22782 #define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK (0x8000U)
22783 #define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT (15U)
22784
22788 #define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK)
22789 #define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)
22790 #define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)
22791 #define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
22792 #define IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK (0xF000000U)
22793 #define IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT (24U)
22794 #define IOMUXC_GPR_GPR3_OCRAM2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK)
22795 #define IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK (0x80000000U)
22796 #define IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT (31U)
22797
22801 #define IOMUXC_GPR_GPR3_AXBS_L_HALTED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK)
22802
22806 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
22807 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
22808
22812 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
22813 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
22814 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
22815
22819 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
22820 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
22821 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
22822
22826 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
22827 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
22828 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
22829
22833 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
22834 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
22835 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
22836
22840 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
22841 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
22842 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
22843
22847 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
22848 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
22849 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
22850
22854 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
22855 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
22856 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
22857
22861 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
22862 #define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x100U)
22863 #define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (8U)
22864
22868 #define IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK)
22869 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
22870 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
22871
22875 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
22876 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
22877 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
22878
22882 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
22883 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
22884 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
22885
22889 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
22890 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
22891 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
22892
22896 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
22897 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)
22898 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)
22899
22903 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
22904 #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK (0x4000U)
22905 #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT (14U)
22906
22910 #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK)
22911 #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK (0x8000U)
22912 #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT (15U)
22913
22917 #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK)
22918 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
22919 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
22920
22924 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
22925 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
22926 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
22927
22931 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
22932 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
22933 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
22934
22938 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
22939 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
22940 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
22941
22945 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
22946 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
22947 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
22948
22952 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
22953 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
22954 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
22955
22959 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
22960 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
22961 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
22962
22966 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
22967 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
22968 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
22969
22973 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
22974 #define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x1000000U)
22975 #define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (24U)
22976
22980 #define IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK)
22981 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
22982 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
22983
22987 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
22988 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
22989 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
22990
22994 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
22995 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
22996 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
22997
23001 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
23002 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
23003 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
23004
23008 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
23009 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)
23010 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)
23011
23015 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
23016 #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK (0x40000000U)
23017 #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT (30U)
23018
23022 #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK)
23023 #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK (0x80000000U)
23024 #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT (31U)
23025
23029 #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK)
23030
23034 #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
23035 #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
23036
23040 #define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
23041 #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
23042 #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
23043
23047 #define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
23048 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
23049 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
23050
23054 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
23055 #define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U)
23056 #define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U)
23057
23061 #define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK)
23062 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
23063 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
23064
23068 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
23069 #define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U)
23070 #define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U)
23071
23075 #define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK)
23076 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
23077 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
23078
23082 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
23083 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
23084 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
23085
23089 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
23090
23094 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
23095 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
23096
23100 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
23101 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
23102 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
23103
23107 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
23108 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
23109 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
23110
23114 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
23115 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
23116 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
23117
23121 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
23122 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
23123 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
23124
23128 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
23129 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
23130 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
23131
23135 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
23136 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
23137 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
23138
23142 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
23143 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
23144 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
23145
23149 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
23150 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
23151 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
23152
23156 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
23157 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
23158 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
23159
23163 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
23164 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
23165 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
23166
23170 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
23171 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
23172 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
23173
23177 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
23178 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
23179 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
23180
23184 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
23185 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
23186 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
23187
23191 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
23192 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
23193 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
23194
23198 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
23199 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
23200 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
23201
23205 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
23206 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
23207 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
23208
23212 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
23213 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
23214 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
23215
23219 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
23220 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
23221 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
23222
23226 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
23227 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
23228 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
23229
23233 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
23234 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
23235 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
23236
23240 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
23241 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
23242 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
23243
23247 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
23248 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
23249 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
23250
23254 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
23255 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
23256 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
23257
23261 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
23262 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
23263 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
23264
23268 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
23269 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
23270 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
23271
23275 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
23276 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
23277 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
23278
23282 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
23283 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
23284 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
23285
23289 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
23290 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
23291 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
23292
23296 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
23297 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
23298 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
23299
23303 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
23304 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
23305 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
23306
23310 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
23311 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
23312 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
23313
23317 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
23318
23322 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
23323 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
23324
23328 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
23329 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
23330 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
23331
23335 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
23336 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
23337 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
23338
23342 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
23343 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
23344 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
23345
23349 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
23350 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
23351 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
23352
23356 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
23357 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
23358 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
23359
23363 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
23364 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
23365 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
23366
23370 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
23371 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
23372 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
23373
23377 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
23378 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
23379 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
23380
23384 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
23385 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
23386 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
23387
23391 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
23392 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
23393 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
23394
23398 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
23399 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
23400 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
23401
23405 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
23406 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
23407 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
23408
23412 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
23413 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
23414 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
23415
23419 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
23420 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
23421 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
23422
23426 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
23427 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
23428 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
23429
23433 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
23434 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
23435 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
23436
23440 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
23441 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
23442 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
23443
23447 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
23448 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
23449 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
23450
23454 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
23455 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
23456 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
23457
23461 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
23462 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
23463 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
23464
23468 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
23469 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
23470 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
23471
23475 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
23476 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
23477 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
23478
23482 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
23483 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
23484 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
23485
23489 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
23490 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
23491 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
23492
23496 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
23497 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
23498 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
23499
23503 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
23504 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
23505 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
23506
23510 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
23511 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
23512 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
23513
23517 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
23518 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
23519 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
23520
23524 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
23525 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
23526 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
23527
23531 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
23532 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
23533 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
23534
23538 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
23539 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
23540 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
23541
23545 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
23546
23550 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
23551 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
23552
23556 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
23557 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
23558 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
23559
23563 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
23564 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
23565 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
23566
23570 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
23571 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
23572 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
23573
23577 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
23578 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
23579 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
23580
23584 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
23585 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
23586 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
23587
23591 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
23592 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
23593 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
23594
23598 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
23599 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
23600 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
23601
23605 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
23606 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
23607 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
23608
23612 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
23613 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
23614 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
23615
23619 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
23620 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
23621 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
23622
23626 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
23627 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
23628 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
23629
23633 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
23634 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
23635 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
23636
23640 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
23641 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
23642 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
23643
23647 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
23648 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
23649 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
23650
23654 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
23655 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
23656 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
23657
23661 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
23662 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
23663 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
23664
23668 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
23669 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
23670 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
23671
23675 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
23676 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
23677 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
23678
23682 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
23683 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
23684 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
23685
23689 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
23690 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
23691 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
23692
23696 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
23697 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
23698 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
23699
23703 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
23704 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
23705 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
23706
23710 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
23711 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
23712 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
23713
23717 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
23718 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
23719 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
23720
23724 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
23725 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
23726 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
23727
23731 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
23732 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
23733 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
23734
23738 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
23739 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
23740 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
23741
23745 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
23746 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
23747 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
23748
23752 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
23753 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
23754 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
23755
23759 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
23760 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
23761 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
23762
23766 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
23767 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
23768 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
23769
23773 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
23774
23778 #define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
23779 #define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
23780
23784 #define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
23785 #define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
23786 #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
23787
23791 #define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
23792 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
23793 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
23794
23798 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
23799 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
23800 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
23801
23805 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
23806 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
23807 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
23808
23813 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
23814 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)
23815 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
23816 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
23817 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
23818 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
23819
23823 #define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
23824 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
23825 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
23826
23830 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
23831 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
23832 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
23833
23837 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
23838 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
23839 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
23840
23844 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
23845 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
23846 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
23847
23851 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
23852 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
23853 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
23854
23858 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
23859
23863 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
23864 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
23865
23871 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
23872 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
23873 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
23874
23880 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
23881 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
23882 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
23883
23889 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
23890 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
23891 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
23892
23898 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
23899 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
23900 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
23901 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
23902
23906 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
23907 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
23908
23912 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
23913 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
23914 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
23915
23919 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
23920 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
23921 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
23922
23926 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
23927 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)
23928 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)
23929
23933 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
23934 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
23935 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
23936
23940 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
23941 #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK (0x20U)
23942 #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT (5U)
23943
23947 #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK)
23948 #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK (0x40U)
23949 #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT (6U)
23950
23954 #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK)
23955
23959 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
23960 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
23961
23965 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
23966 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
23967 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
23968
23972 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
23973 #define IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK (0x10U)
23974 #define IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT (4U)
23975
23979 #define IOMUXC_GPR_GPR13_CANFD_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK)
23980 #define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
23981 #define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
23982
23986 #define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
23987 #define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
23988 #define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
23989
23993 #define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
23994 #define IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK (0x100000U)
23995 #define IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT (20U)
23996
24000 #define IOMUXC_GPR_GPR13_CANFD_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK)
24001
24005 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
24006 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
24007
24011 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
24012 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
24013 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
24014
24018 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
24019 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
24020 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
24021
24025 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
24026 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
24027 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
24028
24032 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
24033 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
24034 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
24035
24039 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
24040 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
24041 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
24042
24046 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
24047 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
24048 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
24049
24053 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
24054 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
24055 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
24056
24060 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
24061 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
24062 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
24063
24067 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
24068 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
24069 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
24070
24074 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
24075 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
24076 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
24077
24081 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
24082 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
24083 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
24084
24088 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
24089 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)
24090 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)
24091
24102 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
24103 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)
24104 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)
24105
24116 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
24117
24121 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)
24122 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)
24123
24127 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
24128 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)
24129 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)
24130
24134 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
24135 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
24136 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
24137
24141 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
24142
24146 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)
24147 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
24148
24150 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
24151
24155 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
24156 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
24157
24161 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
24162 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
24163 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
24164 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
24165
24169 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
24170 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
24171
24175 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
24176 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
24177 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
24178 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
24179
24183 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
24184 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
24185
24189 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
24190 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
24191 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
24192 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
24193
24197 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
24198 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
24199
24203 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
24204 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
24205 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
24206 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
24207
24211 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
24212 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
24213
24217 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
24218 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
24219 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
24220 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
24221
24225 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
24226 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
24227
24231 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
24232 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
24233 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
24234 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
24235
24239 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
24240 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
24241
24245 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
24246 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
24247 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)
24248 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
24249
24253 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
24254 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
24255
24259 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
24260 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
24261 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
24262 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
24263
24267 #define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK (0xFFFFFFFFU)
24268 #define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT (0U)
24269
24271 #define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)
24272
24276 #define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK (0xFFFFFFFFU)
24277 #define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT (0U)
24278
24280 #define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)
24281
24285 #define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK (0xFFFFFFFFU)
24286 #define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT (0U)
24287
24289 #define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK)
24290
24294 #define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK (0xFFFFFFFFU)
24295 #define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT (0U)
24296
24298 #define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK)
24299
24303 #define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK (0xFFFFF000U)
24304 #define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT (12U)
24305 #define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT)) & IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK)
24306
24310 #define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK (0xFFFFF000U)
24311 #define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT (12U)
24312 #define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT)) & IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK)
24313
24317 #define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK (0xFFFFF000U)
24318 #define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT (12U)
24319 #define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT)) & IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK)
24320
24324 #define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK (0x1U)
24325 #define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT (0U)
24326
24331 #define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK)
24332 #define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK (0xFEU)
24333 #define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT (1U)
24334 #define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK)
24335 #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK (0x10000U)
24336 #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT (16U)
24337
24341 #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK)
24342 #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK (0xFE0000U)
24343 #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT (17U)
24344
24348 #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK)
24349
24353 #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK (0xFFU)
24354 #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT (0U)
24355
24357 #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK)
24358 #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK (0x100U)
24359 #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT (8U)
24360
24364 #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK)
24365 /* end of group IOMUXC_GPR_Register_Masks */
24371
24372
24373 /* IOMUXC_GPR - Peripheral instance base addresses */
24375 #define IOMUXC_GPR_BASE (0x400AC000u)
24376
24377 #define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
24378
24379 #define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
24380
24381 #define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
24382 /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
24386
24387
24388 /* ----------------------------------------------------------------------------
24389 -- IOMUXC_SNVS Peripheral Access Layer
24390 ---------------------------------------------------------------------------- */
24391
24398 typedef struct {
24399 __IO uint32_t SW_MUX_CTL_PAD_WAKEUP;
24400 __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ;
24401 __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ;
24402 __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE;
24403 __IO uint32_t SW_PAD_CTL_PAD_POR_B;
24404 __IO uint32_t SW_PAD_CTL_PAD_ONOFF;
24405 __IO uint32_t SW_PAD_CTL_PAD_WAKEUP;
24406 __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ;
24407 __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ;
24408 } IOMUXC_SNVS_Type;
24409
24410 /* ----------------------------------------------------------------------------
24411 -- IOMUXC_SNVS Register Masks
24412 ---------------------------------------------------------------------------- */
24413
24421 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
24422 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
24423
24427 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
24428 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
24429 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
24430
24434 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
24435
24439 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
24440 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
24441
24445 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
24446 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
24447 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
24448
24452 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
24453
24457 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
24458 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
24459
24463 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
24464 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
24465 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
24466
24470 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
24471
24475 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
24476 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
24477
24481 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
24482 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
24483 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
24484
24494 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
24495 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
24496 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
24497
24500 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
24501 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
24502 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
24503
24507 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
24508 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
24509 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
24510
24514 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
24515 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
24516 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
24517
24521 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
24522 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
24523 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
24524
24530 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
24531 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
24532 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
24533
24537 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
24538
24542 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
24543 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
24544
24548 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
24549 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
24550 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
24551
24561 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
24562 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
24563 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
24564
24567 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
24568 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
24569 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
24570
24574 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
24575 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
24576 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
24577
24581 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
24582 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
24583 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
24584
24588 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
24589 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
24590 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
24591
24597 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
24598 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
24599 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
24600
24604 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
24605
24609 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
24610 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
24611
24615 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
24616 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
24617 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
24618
24628 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
24629 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
24630 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
24631
24634 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
24635 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
24636 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
24637
24641 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
24642 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
24643 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
24644
24648 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
24649 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
24650 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
24651
24655 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
24656 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
24657 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
24658
24664 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
24665 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
24666 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
24667
24671 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
24672
24676 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
24677 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
24678
24682 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
24683 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
24684 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
24685
24695 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
24696 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
24697 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
24698
24701 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
24702 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
24703 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
24704
24708 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
24709 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
24710 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
24711
24715 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
24716 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
24717 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
24718
24722 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
24723 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
24724 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
24725
24731 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
24732 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
24733 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
24734
24738 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
24739
24743 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
24744 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
24745
24749 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
24750 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
24751 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
24752
24762 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
24763 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
24764 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
24765
24768 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
24769 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
24770 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
24771
24775 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
24776 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
24777 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
24778
24782 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
24783 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
24784 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
24785
24789 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
24790 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
24791 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
24792
24798 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
24799 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
24800 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
24801
24805 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
24806
24810 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
24811 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
24812
24816 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
24817 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
24818 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
24819
24829 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
24830 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
24831 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
24832
24835 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
24836 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
24837 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
24838
24842 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
24843 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
24844 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
24845
24849 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
24850 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
24851 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
24852
24856 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
24857 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
24858 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
24859
24865 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
24866 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
24867 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
24868
24872 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)
24873 /* end of group IOMUXC_SNVS_Register_Masks */
24879
24880
24881 /* IOMUXC_SNVS - Peripheral instance base addresses */
24883 #define IOMUXC_SNVS_BASE (0x400A8000u)
24884
24885 #define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
24886
24887 #define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
24888
24889 #define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
24890 /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
24894
24895
24896 /* ----------------------------------------------------------------------------
24897 -- IOMUXC_SNVS_GPR Peripheral Access Layer
24898 ---------------------------------------------------------------------------- */
24899
24906 typedef struct {
24907 uint32_t GPR0;
24908 uint32_t GPR1;
24909 uint32_t GPR2;
24910 __IO uint32_t GPR3;
24911 } IOMUXC_SNVS_GPR_Type;
24912
24913 /* ----------------------------------------------------------------------------
24914 -- IOMUXC_SNVS_GPR Register Masks
24915 ---------------------------------------------------------------------------- */
24916
24924 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
24925 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
24926 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
24927 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
24928 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
24929
24931 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
24932 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
24933 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
24934 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
24935 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
24936 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
24937 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
24938 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
24939 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
24940 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
24941 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
24942 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
24943 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
24944 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
24945 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
24946 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
24947 /* end of group IOMUXC_SNVS_GPR_Register_Masks */
24953
24954
24955 /* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
24957 #define IOMUXC_SNVS_GPR_BASE (0x400A4000u)
24958
24959 #define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
24960
24961 #define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
24962
24963 #define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
24964 /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
24968
24969
24970 /* ----------------------------------------------------------------------------
24971 -- KPP Peripheral Access Layer
24972 ---------------------------------------------------------------------------- */
24973
24980 typedef struct {
24981 __IO uint16_t KPCR;
24982 __IO uint16_t KPSR;
24983 __IO uint16_t KDDR;
24984 __IO uint16_t KPDR;
24985 } KPP_Type;
24986
24987 /* ----------------------------------------------------------------------------
24988 -- KPP Register Masks
24989 ---------------------------------------------------------------------------- */
24990
24998 #define KPP_KPCR_KRE_MASK (0xFFU)
24999 #define KPP_KPCR_KRE_SHIFT (0U)
25000
25004 #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
25005 #define KPP_KPCR_KCO_MASK (0xFF00U)
25006 #define KPP_KPCR_KCO_SHIFT (8U)
25007
25011 #define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
25012
25016 #define KPP_KPSR_KPKD_MASK (0x1U)
25017 #define KPP_KPSR_KPKD_SHIFT (0U)
25018
25022 #define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
25023 #define KPP_KPSR_KPKR_MASK (0x2U)
25024 #define KPP_KPSR_KPKR_SHIFT (1U)
25025
25029 #define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
25030 #define KPP_KPSR_KDSC_MASK (0x4U)
25031 #define KPP_KPSR_KDSC_SHIFT (2U)
25032
25036 #define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
25037 #define KPP_KPSR_KRSS_MASK (0x8U)
25038 #define KPP_KPSR_KRSS_SHIFT (3U)
25039
25043 #define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
25044 #define KPP_KPSR_KDIE_MASK (0x100U)
25045 #define KPP_KPSR_KDIE_SHIFT (8U)
25046
25050 #define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
25051 #define KPP_KPSR_KRIE_MASK (0x200U)
25052 #define KPP_KPSR_KRIE_SHIFT (9U)
25053
25057 #define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
25058
25062 #define KPP_KDDR_KRDD_MASK (0xFFU)
25063 #define KPP_KDDR_KRDD_SHIFT (0U)
25064
25068 #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
25069 #define KPP_KDDR_KCDD_MASK (0xFF00U)
25070 #define KPP_KDDR_KCDD_SHIFT (8U)
25071
25075 #define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
25076
25080 #define KPP_KPDR_KRD_MASK (0xFFU)
25081 #define KPP_KPDR_KRD_SHIFT (0U)
25082 #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
25083 #define KPP_KPDR_KCD_MASK (0xFF00U)
25084 #define KPP_KPDR_KCD_SHIFT (8U)
25085 #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
25086 /* end of group KPP_Register_Masks */
25092
25093
25094 /* KPP - Peripheral instance base addresses */
25096 #define KPP_BASE (0x401FC000u)
25097
25098 #define KPP ((KPP_Type *)KPP_BASE)
25099
25100 #define KPP_BASE_ADDRS { KPP_BASE }
25101
25102 #define KPP_BASE_PTRS { KPP }
25103
25104 #define KPP_IRQS { KPP_IRQn }
25105 /* end of group KPP_Peripheral_Access_Layer */
25109
25110
25111 /* ----------------------------------------------------------------------------
25112 -- LCDIF Peripheral Access Layer
25113 ---------------------------------------------------------------------------- */
25114
25121 typedef struct {
25122 __IO uint32_t CTRL;
25123 __IO uint32_t CTRL_SET;
25124 __IO uint32_t CTRL_CLR;
25125 __IO uint32_t CTRL_TOG;
25126 __IO uint32_t CTRL1;
25127 __IO uint32_t CTRL1_SET;
25128 __IO uint32_t CTRL1_CLR;
25129 __IO uint32_t CTRL1_TOG;
25130 __IO uint32_t CTRL2;
25131 __IO uint32_t CTRL2_SET;
25132 __IO uint32_t CTRL2_CLR;
25133 __IO uint32_t CTRL2_TOG;
25134 __IO uint32_t TRANSFER_COUNT;
25135 uint8_t RESERVED_0[12];
25136 __IO uint32_t CUR_BUF;
25137 uint8_t RESERVED_1[12];
25138 __IO uint32_t NEXT_BUF;
25139 uint8_t RESERVED_2[28];
25140 __IO uint32_t VDCTRL0;
25141 __IO uint32_t VDCTRL0_SET;
25142 __IO uint32_t VDCTRL0_CLR;
25143 __IO uint32_t VDCTRL0_TOG;
25144 __IO uint32_t VDCTRL1;
25145 uint8_t RESERVED_3[12];
25146 __IO uint32_t VDCTRL2;
25147 uint8_t RESERVED_4[12];
25148 __IO uint32_t VDCTRL3;
25149 uint8_t RESERVED_5[12];
25150 __IO uint32_t VDCTRL4;
25151 uint8_t RESERVED_6[220];
25152 __IO uint32_t BM_ERROR_STAT;
25153 uint8_t RESERVED_7[12];
25154 __IO uint32_t CRC_STAT;
25155 uint8_t RESERVED_8[12];
25156 __I uint32_t STAT;
25157 uint8_t RESERVED_9[460];
25158 __IO uint32_t PIGEONCTRL0;
25159 __IO uint32_t PIGEONCTRL0_SET;
25160 __IO uint32_t PIGEONCTRL0_CLR;
25161 __IO uint32_t PIGEONCTRL0_TOG;
25162 __IO uint32_t PIGEONCTRL1;
25163 __IO uint32_t PIGEONCTRL1_SET;
25164 __IO uint32_t PIGEONCTRL1_CLR;
25165 __IO uint32_t PIGEONCTRL1_TOG;
25166 __IO uint32_t PIGEONCTRL2;
25167 __IO uint32_t PIGEONCTRL2_SET;
25168 __IO uint32_t PIGEONCTRL2_CLR;
25169 __IO uint32_t PIGEONCTRL2_TOG;
25170 uint8_t RESERVED_10[1104];
25171 struct { /* offset: 0x800, array step: 0x40 */
25172 __IO uint32_t PIGEON_0;
25173 uint8_t RESERVED_0[12];
25174 __IO uint32_t PIGEON_1;
25175 uint8_t RESERVED_1[12];
25176 __IO uint32_t PIGEON_2;
25177 uint8_t RESERVED_2[28];
25178 } PIGEON[12];
25179 __IO uint32_t LUT_CTRL;
25180 uint8_t RESERVED_11[12];
25181 __IO uint32_t LUT0_ADDR;
25182 uint8_t RESERVED_12[12];
25183 __IO uint32_t LUT0_DATA;
25184 uint8_t RESERVED_13[12];
25185 __IO uint32_t LUT1_ADDR;
25186 uint8_t RESERVED_14[12];
25187 __IO uint32_t LUT1_DATA;
25188 } LCDIF_Type;
25189
25190 /* ----------------------------------------------------------------------------
25191 -- LCDIF Register Masks
25192 ---------------------------------------------------------------------------- */
25193
25201 #define LCDIF_CTRL_RUN_MASK (0x1U)
25202 #define LCDIF_CTRL_RUN_SHIFT (0U)
25203 #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
25204 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
25205 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
25206
25211 #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
25212 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
25213 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
25214
25218 #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
25219 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
25220 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
25221 #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
25222 #define LCDIF_CTRL_RSRVD0_MASK (0x10U)
25223 #define LCDIF_CTRL_RSRVD0_SHIFT (4U)
25224 #define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
25225 #define LCDIF_CTRL_MASTER_MASK (0x20U)
25226 #define LCDIF_CTRL_MASTER_SHIFT (5U)
25227 #define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
25228 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
25229 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
25230 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
25231 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
25232 #define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
25233
25239 #define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
25240 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
25241 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
25242
25248 #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
25249 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
25250 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
25251
25259 #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
25260 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
25261 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
25262
25270 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
25271 #define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
25272 #define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
25273 #define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
25274 #define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
25275 #define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
25276 #define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
25277 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
25278 #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
25279 #define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
25280 #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
25281 #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
25282
25286 #define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
25287 #define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
25288 #define LCDIF_CTRL_CLKGATE_SHIFT (30U)
25289 #define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
25290 #define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
25291 #define LCDIF_CTRL_SFTRST_SHIFT (31U)
25292 #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
25293
25297 #define LCDIF_CTRL_SET_RUN_MASK (0x1U)
25298 #define LCDIF_CTRL_SET_RUN_SHIFT (0U)
25299 #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
25300 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
25301 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
25302
25307 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
25308 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
25309 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
25310
25314 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
25315 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
25316 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
25317 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
25318 #define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
25319 #define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
25320 #define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
25321 #define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
25322 #define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
25323 #define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
25324 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
25325 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
25326 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
25327 #define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
25328 #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
25329
25335 #define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
25336 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
25337 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
25338
25344 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
25345 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
25346 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
25347
25355 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
25356 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
25357 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
25358
25366 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
25367 #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
25368 #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
25369 #define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
25370 #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
25371 #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
25372 #define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
25373 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
25374 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
25375 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
25376 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
25377 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
25378
25382 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
25383 #define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
25384 #define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
25385 #define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
25386 #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
25387 #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
25388 #define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
25389
25393 #define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
25394 #define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
25395 #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
25396 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
25397 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
25398
25403 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
25404 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
25405 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
25406
25410 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
25411 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
25412 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
25413 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
25414 #define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
25415 #define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
25416 #define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
25417 #define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
25418 #define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
25419 #define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
25420 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
25421 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
25422 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
25423 #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
25424 #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
25425
25431 #define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
25432 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
25433 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
25434
25440 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
25441 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
25442 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
25443
25451 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
25452 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
25453 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
25454
25462 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
25463 #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
25464 #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
25465 #define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
25466 #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
25467 #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
25468 #define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
25469 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
25470 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
25471 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
25472 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
25473 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
25474
25478 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
25479 #define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
25480 #define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
25481 #define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
25482 #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
25483 #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
25484 #define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
25485
25489 #define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
25490 #define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
25491 #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
25492 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
25493 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
25494
25499 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
25500 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
25501 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
25502
25506 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
25507 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
25508 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
25509 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
25510 #define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
25511 #define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
25512 #define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
25513 #define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
25514 #define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
25515 #define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
25516 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
25517 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
25518 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
25519 #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
25520 #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
25521
25527 #define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
25528 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
25529 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
25530
25536 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
25537 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
25538 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
25539
25547 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
25548 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
25549 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
25550
25558 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
25559 #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
25560 #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
25561 #define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
25562 #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
25563 #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
25564 #define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
25565 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
25566 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
25567 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
25568 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
25569 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
25570
25574 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
25575 #define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
25576 #define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
25577 #define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
25578 #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
25579 #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
25580 #define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
25581
25585 #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
25586 #define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
25587 #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
25588 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
25589 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
25590
25594 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
25595 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
25596 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
25597
25601 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
25602 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
25603 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
25604
25608 #define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
25609 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
25610 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
25611
25615 #define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
25616 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
25617 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
25618 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
25619 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
25620 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
25621 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
25622 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
25623 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
25624 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
25625 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
25626 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
25627 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
25628 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
25629 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
25630 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
25631 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
25632 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
25633 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
25634 #define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
25635 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
25636 #define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
25637 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
25638 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
25639 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
25640 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
25641 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
25642 #define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
25643 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
25644 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
25645 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
25646 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
25647 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
25648
25652 #define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
25653 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
25654 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
25655 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
25656 #define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)
25657 #define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)
25658 #define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
25659 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)
25660 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)
25661 #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
25662
25666 #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
25667 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
25668 #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
25669 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
25670 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
25671
25675 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
25676 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
25677 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
25678
25682 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
25683 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
25684 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
25685
25689 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
25690 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
25691 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
25692
25696 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
25697 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
25698 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
25699 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
25700 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
25701 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
25702 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
25703 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
25704 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
25705 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
25706 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
25707 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
25708 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
25709 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
25710 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
25711 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
25712 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
25713 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
25714 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
25715 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
25716 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
25717 #define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
25718 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
25719 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
25720 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
25721 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
25722 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
25723 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
25724 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
25725 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
25726 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
25727 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
25728 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
25729
25733 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
25734 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
25735 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
25736 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
25737 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)
25738 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)
25739 #define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
25740 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)
25741 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)
25742 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
25743
25747 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
25748 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
25749 #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
25750 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
25751 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
25752
25756 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
25757 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
25758 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
25759
25763 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
25764 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
25765 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
25766
25770 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
25771 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
25772 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
25773
25777 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
25778 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
25779 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
25780 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
25781 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
25782 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
25783 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
25784 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
25785 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
25786 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
25787 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
25788 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
25789 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
25790 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
25791 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
25792 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
25793 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
25794 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
25795 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
25796 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
25797 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
25798 #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
25799 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
25800 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
25801 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
25802 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
25803 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
25804 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
25805 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
25806 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
25807 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
25808 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
25809 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
25810
25814 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
25815 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
25816 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
25817 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
25818 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)
25819 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)
25820 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
25821 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)
25822 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)
25823 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
25824
25828 #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
25829 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
25830 #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
25831 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
25832 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
25833
25837 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
25838 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
25839 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
25840
25844 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
25845 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
25846 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
25847
25851 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
25852 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
25853 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
25854
25858 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
25859 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
25860 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
25861 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
25862 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
25863 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
25864 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
25865 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
25866 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
25867 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
25868 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
25869 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
25870 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
25871 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
25872 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
25873 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
25874 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
25875 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
25876 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
25877 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
25878 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
25879 #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
25880 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
25881 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
25882 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
25883 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
25884 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
25885 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
25886 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
25887 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
25888 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
25889 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
25890 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
25891
25895 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
25896 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
25897 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
25898 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
25899 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)
25900 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)
25901 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
25902 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)
25903 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)
25904 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
25905
25909 #define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)
25910 #define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
25911 #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
25912 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
25913 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
25914
25922 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
25923 #define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
25924 #define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
25925 #define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
25926 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
25927 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
25928
25936 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
25937 #define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
25938 #define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
25939 #define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
25940 #define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
25941 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
25942 #define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
25943 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
25944 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
25945
25952 #define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
25953 #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
25954 #define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
25955 #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
25956
25960 #define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)
25961 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
25962 #define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
25963 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
25964 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
25965
25973 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
25974 #define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
25975 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
25976 #define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
25977 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
25978 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
25979
25987 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
25988 #define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
25989 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
25990 #define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
25991 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
25992 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
25993 #define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
25994 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
25995 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
25996
26003 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
26004 #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
26005 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
26006 #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
26007
26011 #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)
26012 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
26013 #define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
26014 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
26015 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
26016
26024 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
26025 #define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
26026 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
26027 #define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
26028 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
26029 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
26030
26038 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
26039 #define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
26040 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
26041 #define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
26042 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
26043 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
26044 #define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
26045 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
26046 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
26047
26054 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
26055 #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
26056 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
26057 #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
26058
26062 #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)
26063 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
26064 #define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
26065 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
26066 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
26067
26075 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
26076 #define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
26077 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
26078 #define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
26079 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
26080 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
26081
26089 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
26090 #define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
26091 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
26092 #define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
26093 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
26094 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
26095 #define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
26096 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
26097 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
26098
26105 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
26106 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
26107 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
26108 #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
26109
26113 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
26114 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
26115 #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
26116 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
26117 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
26118 #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
26119
26123 #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
26124 #define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
26125 #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
26126
26130 #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
26131 #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
26132 #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
26133
26137 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
26138 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
26139 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
26140 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
26141 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
26142 #define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
26143 #define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
26144 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
26145 #define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
26146 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
26147 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
26148 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
26149 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
26150 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
26151 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
26152 #define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
26153 #define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
26154 #define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
26155 #define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
26156 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
26157 #define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
26158 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
26159 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
26160 #define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
26161 #define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
26162 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
26163 #define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
26164 #define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
26165 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
26166 #define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
26167 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
26168 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
26169 #define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
26170 #define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)
26171 #define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U)
26172 #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
26173
26177 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
26178 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
26179 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
26180 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
26181 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
26182 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
26183 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
26184 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
26185 #define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
26186 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
26187 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
26188 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
26189 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
26190 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
26191 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
26192 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
26193 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
26194 #define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
26195 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
26196 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
26197 #define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
26198 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
26199 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
26200 #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
26201 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
26202 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
26203 #define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
26204 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
26205 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
26206 #define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
26207 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
26208 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
26209 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
26210 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)
26211 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)
26212 #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
26213
26217 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
26218 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
26219 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
26220 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
26221 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
26222 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
26223 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
26224 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
26225 #define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
26226 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
26227 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
26228 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
26229 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
26230 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
26231 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
26232 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
26233 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
26234 #define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
26235 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
26236 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
26237 #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
26238 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
26239 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
26240 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
26241 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
26242 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
26243 #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
26244 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
26245 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
26246 #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
26247 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
26248 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
26249 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
26250 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)
26251 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)
26252 #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
26253
26257 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
26258 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
26259 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
26260 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
26261 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
26262 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
26263 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
26264 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
26265 #define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
26266 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
26267 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
26268 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
26269 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
26270 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
26271 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
26272 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
26273 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
26274 #define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
26275 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
26276 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
26277 #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
26278 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
26279 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
26280 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
26281 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
26282 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
26283 #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
26284 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
26285 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
26286 #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
26287 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
26288 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
26289 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
26290 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)
26291 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)
26292 #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
26293
26297 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
26298 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
26299 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
26300
26304 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
26305 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
26306 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
26307 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
26308 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
26309 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
26310
26314 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
26315 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
26316 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
26317 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
26318 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
26319 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
26320 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
26321 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
26322 #define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
26323 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
26324 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
26325 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
26326 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
26327 #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
26328 #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
26329
26333 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
26334 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
26335 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
26336 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
26337 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
26338 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
26339 #define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
26340 #define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
26341 #define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
26342 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
26343 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
26344 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
26345
26349 #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
26350 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
26351 #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
26352
26356 #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
26357 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
26358 #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
26359
26363 #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
26364 #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
26365 #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
26366 #define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)
26367 #define LCDIF_STAT_RSRVD0_SHIFT (9U)
26368 #define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
26369 #define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
26370 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
26371 #define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
26372 #define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
26373 #define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
26374 #define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
26375 #define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
26376 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
26377 #define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
26378 #define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
26379 #define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
26380 #define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
26381 #define LCDIF_STAT_DMA_REQ_MASK (0x40000000U)
26382 #define LCDIF_STAT_DMA_REQ_SHIFT (30U)
26383 #define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
26384 #define LCDIF_STAT_PRESENT_MASK (0x80000000U)
26385 #define LCDIF_STAT_PRESENT_SHIFT (31U)
26386 #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
26387
26391 #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
26392 #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
26393 #define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
26394 #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
26395 #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
26396 #define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
26397
26401 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
26402 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
26403 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
26404 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
26405 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
26406 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
26407
26411 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
26412 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
26413 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
26414 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
26415 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
26416 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
26417
26421 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
26422 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
26423 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
26424 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
26425 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
26426 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
26427
26431 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
26432 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
26433 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
26434 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
26435 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
26436 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
26437
26441 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
26442 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
26443 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
26444 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
26445 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
26446 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
26447
26451 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
26452 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
26453 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
26454 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
26455 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
26456 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
26457
26461 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
26462 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
26463 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
26464 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
26465 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
26466 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
26467
26471 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
26472 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
26473 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
26474 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
26475 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
26476 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
26477
26481 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
26482 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
26483 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
26484 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
26485 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
26486 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
26487
26491 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
26492 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
26493 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
26494 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
26495 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
26496 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
26497
26501 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
26502 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
26503 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
26504 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
26505 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
26506 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
26507
26511 #define LCDIF_PIGEON_0_EN_MASK (0x1U)
26512 #define LCDIF_PIGEON_0_EN_SHIFT (0U)
26513 #define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
26514 #define LCDIF_PIGEON_0_POL_MASK (0x2U)
26515 #define LCDIF_PIGEON_0_POL_SHIFT (1U)
26516
26520 #define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
26521 #define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)
26522 #define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)
26523
26529 #define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
26530 #define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)
26531 #define LCDIF_PIGEON_0_OFFSET_SHIFT (4U)
26532 #define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
26533 #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
26534 #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
26535
26545 #define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
26546 #define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)
26547 #define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)
26548 #define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
26549 #define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)
26550 #define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)
26551
26561 #define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
26562
26564 /* The count of LCDIF_PIGEON_0 */
26565 #define LCDIF_PIGEON_0_COUNT (12U)
26566
26569 #define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)
26570 #define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)
26571
26574 #define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
26575 #define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)
26576 #define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)
26577
26580 #define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
26581
26583 /* The count of LCDIF_PIGEON_1 */
26584 #define LCDIF_PIGEON_1_COUNT (12U)
26585
26588 #define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)
26589 #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)
26590
26596 #define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
26597 #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)
26598 #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
26599
26602 #define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
26603 #define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)
26604 #define LCDIF_PIGEON_2_RSVD_SHIFT (9U)
26605 #define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
26606
26608 /* The count of LCDIF_PIGEON_2 */
26609 #define LCDIF_PIGEON_2_COUNT (12U)
26610
26613 #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)
26614 #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)
26615 #define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
26616
26620 #define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)
26621 #define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)
26622 #define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
26623
26627 #define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)
26628 #define LCDIF_LUT0_DATA_DATA_SHIFT (0U)
26629 #define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
26630
26634 #define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)
26635 #define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)
26636 #define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
26637
26641 #define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)
26642 #define LCDIF_LUT1_DATA_DATA_SHIFT (0U)
26643 #define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
26644 /* end of group LCDIF_Register_Masks */
26650
26651
26652 /* LCDIF - Peripheral instance base addresses */
26654 #define LCDIF_BASE (0x402B8000u)
26655
26656 #define LCDIF ((LCDIF_Type *)LCDIF_BASE)
26657
26658 #define LCDIF_BASE_ADDRS { LCDIF_BASE }
26659
26660 #define LCDIF_BASE_PTRS { LCDIF }
26661
26662 #define LCDIF_IRQ0_IRQS { LCDIF_IRQn }
26663 /* end of group LCDIF_Peripheral_Access_Layer */
26667
26668
26669 /* ----------------------------------------------------------------------------
26670 -- LPI2C Peripheral Access Layer
26671 ---------------------------------------------------------------------------- */
26672
26679 typedef struct {
26680 __I uint32_t VERID;
26681 __I uint32_t PARAM;
26682 uint8_t RESERVED_0[8];
26683 __IO uint32_t MCR;
26684 __IO uint32_t MSR;
26685 __IO uint32_t MIER;
26686 __IO uint32_t MDER;
26687 __IO uint32_t MCFGR0;
26688 __IO uint32_t MCFGR1;
26689 __IO uint32_t MCFGR2;
26690 __IO uint32_t MCFGR3;
26691 uint8_t RESERVED_1[16];
26692 __IO uint32_t MDMR;
26693 uint8_t RESERVED_2[4];
26694 __IO uint32_t MCCR0;
26695 uint8_t RESERVED_3[4];
26696 __IO uint32_t MCCR1;
26697 uint8_t RESERVED_4[4];
26698 __IO uint32_t MFCR;
26699 __I uint32_t MFSR;
26700 __O uint32_t MTDR;
26701 uint8_t RESERVED_5[12];
26702 __I uint32_t MRDR;
26703 uint8_t RESERVED_6[156];
26704 __IO uint32_t SCR;
26705 __IO uint32_t SSR;
26706 __IO uint32_t SIER;
26707 __IO uint32_t SDER;
26708 uint8_t RESERVED_7[4];
26709 __IO uint32_t SCFGR1;
26710 __IO uint32_t SCFGR2;
26711 uint8_t RESERVED_8[20];
26712 __IO uint32_t SAMR;
26713 uint8_t RESERVED_9[12];
26714 __I uint32_t SASR;
26715 __IO uint32_t STAR;
26716 uint8_t RESERVED_10[8];
26717 __O uint32_t STDR;
26718 uint8_t RESERVED_11[12];
26719 __I uint32_t SRDR;
26720 } LPI2C_Type;
26721
26722 /* ----------------------------------------------------------------------------
26723 -- LPI2C Register Masks
26724 ---------------------------------------------------------------------------- */
26725
26733 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
26734 #define LPI2C_VERID_FEATURE_SHIFT (0U)
26735
26739 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
26740 #define LPI2C_VERID_MINOR_MASK (0xFF0000U)
26741 #define LPI2C_VERID_MINOR_SHIFT (16U)
26742
26744 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
26745 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
26746 #define LPI2C_VERID_MAJOR_SHIFT (24U)
26747
26749 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
26750
26754 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
26755 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
26756
26758 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
26759 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
26760 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
26761
26763 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
26764
26768 #define LPI2C_MCR_MEN_MASK (0x1U)
26769 #define LPI2C_MCR_MEN_SHIFT (0U)
26770
26774 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
26775 #define LPI2C_MCR_RST_MASK (0x2U)
26776 #define LPI2C_MCR_RST_SHIFT (1U)
26777
26781 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
26782 #define LPI2C_MCR_DOZEN_MASK (0x4U)
26783 #define LPI2C_MCR_DOZEN_SHIFT (2U)
26784
26788 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
26789 #define LPI2C_MCR_DBGEN_MASK (0x8U)
26790 #define LPI2C_MCR_DBGEN_SHIFT (3U)
26791
26795 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
26796 #define LPI2C_MCR_RTF_MASK (0x100U)
26797 #define LPI2C_MCR_RTF_SHIFT (8U)
26798
26802 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
26803 #define LPI2C_MCR_RRF_MASK (0x200U)
26804 #define LPI2C_MCR_RRF_SHIFT (9U)
26805
26809 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
26810
26814 #define LPI2C_MSR_TDF_MASK (0x1U)
26815 #define LPI2C_MSR_TDF_SHIFT (0U)
26816
26820 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
26821 #define LPI2C_MSR_RDF_MASK (0x2U)
26822 #define LPI2C_MSR_RDF_SHIFT (1U)
26823
26827 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
26828 #define LPI2C_MSR_EPF_MASK (0x100U)
26829 #define LPI2C_MSR_EPF_SHIFT (8U)
26830
26834 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
26835 #define LPI2C_MSR_SDF_MASK (0x200U)
26836 #define LPI2C_MSR_SDF_SHIFT (9U)
26837
26841 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
26842 #define LPI2C_MSR_NDF_MASK (0x400U)
26843 #define LPI2C_MSR_NDF_SHIFT (10U)
26844
26848 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
26849 #define LPI2C_MSR_ALF_MASK (0x800U)
26850 #define LPI2C_MSR_ALF_SHIFT (11U)
26851
26855 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
26856 #define LPI2C_MSR_FEF_MASK (0x1000U)
26857 #define LPI2C_MSR_FEF_SHIFT (12U)
26858
26862 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
26863 #define LPI2C_MSR_PLTF_MASK (0x2000U)
26864 #define LPI2C_MSR_PLTF_SHIFT (13U)
26865
26869 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
26870 #define LPI2C_MSR_DMF_MASK (0x4000U)
26871 #define LPI2C_MSR_DMF_SHIFT (14U)
26872
26876 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
26877 #define LPI2C_MSR_MBF_MASK (0x1000000U)
26878 #define LPI2C_MSR_MBF_SHIFT (24U)
26879
26883 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
26884 #define LPI2C_MSR_BBF_MASK (0x2000000U)
26885 #define LPI2C_MSR_BBF_SHIFT (25U)
26886
26890 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
26891
26895 #define LPI2C_MIER_TDIE_MASK (0x1U)
26896 #define LPI2C_MIER_TDIE_SHIFT (0U)
26897
26901 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
26902 #define LPI2C_MIER_RDIE_MASK (0x2U)
26903 #define LPI2C_MIER_RDIE_SHIFT (1U)
26904
26908 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
26909 #define LPI2C_MIER_EPIE_MASK (0x100U)
26910 #define LPI2C_MIER_EPIE_SHIFT (8U)
26911
26915 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
26916 #define LPI2C_MIER_SDIE_MASK (0x200U)
26917 #define LPI2C_MIER_SDIE_SHIFT (9U)
26918
26922 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
26923 #define LPI2C_MIER_NDIE_MASK (0x400U)
26924 #define LPI2C_MIER_NDIE_SHIFT (10U)
26925
26929 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
26930 #define LPI2C_MIER_ALIE_MASK (0x800U)
26931 #define LPI2C_MIER_ALIE_SHIFT (11U)
26932
26936 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
26937 #define LPI2C_MIER_FEIE_MASK (0x1000U)
26938 #define LPI2C_MIER_FEIE_SHIFT (12U)
26939
26943 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
26944 #define LPI2C_MIER_PLTIE_MASK (0x2000U)
26945 #define LPI2C_MIER_PLTIE_SHIFT (13U)
26946
26950 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
26951 #define LPI2C_MIER_DMIE_MASK (0x4000U)
26952 #define LPI2C_MIER_DMIE_SHIFT (14U)
26953
26957 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
26958
26962 #define LPI2C_MDER_TDDE_MASK (0x1U)
26963 #define LPI2C_MDER_TDDE_SHIFT (0U)
26964
26968 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
26969 #define LPI2C_MDER_RDDE_MASK (0x2U)
26970 #define LPI2C_MDER_RDDE_SHIFT (1U)
26971
26975 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
26976
26980 #define LPI2C_MCFGR0_HREN_MASK (0x1U)
26981 #define LPI2C_MCFGR0_HREN_SHIFT (0U)
26982
26986 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
26987 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
26988 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
26989
26993 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
26994 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
26995 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
26996
27000 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
27001 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
27002 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
27003
27007 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
27008 #define LPI2C_MCFGR0_RDMO_MASK (0x200U)
27009 #define LPI2C_MCFGR0_RDMO_SHIFT (9U)
27010
27014 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
27015
27019 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
27020 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
27021
27031 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
27032 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
27033 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
27034
27038 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
27039 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
27040 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
27041
27045 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
27046 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
27047 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
27048
27052 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
27053 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
27054 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
27055
27065 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
27066 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
27067 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
27068
27078 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
27079
27083 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
27084 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
27085
27087 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
27088 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
27089 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
27090
27092 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
27093 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
27094 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
27095
27097 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
27098
27102 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
27103 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
27104
27106 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
27107
27111 #define LPI2C_MDMR_MATCH0_MASK (0xFFU)
27112 #define LPI2C_MDMR_MATCH0_SHIFT (0U)
27113
27115 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
27116 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
27117 #define LPI2C_MDMR_MATCH1_SHIFT (16U)
27118
27120 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
27121
27125 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
27126 #define LPI2C_MCCR0_CLKLO_SHIFT (0U)
27127
27129 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
27130 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
27131 #define LPI2C_MCCR0_CLKHI_SHIFT (8U)
27132
27134 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
27135 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
27136 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
27137
27139 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
27140 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
27141 #define LPI2C_MCCR0_DATAVD_SHIFT (24U)
27142
27144 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
27145
27149 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
27150 #define LPI2C_MCCR1_CLKLO_SHIFT (0U)
27151
27153 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
27154 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
27155 #define LPI2C_MCCR1_CLKHI_SHIFT (8U)
27156
27158 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
27159 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
27160 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
27161
27163 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
27164 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
27165 #define LPI2C_MCCR1_DATAVD_SHIFT (24U)
27166
27168 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
27169
27173 #define LPI2C_MFCR_TXWATER_MASK (0x3U)
27174 #define LPI2C_MFCR_TXWATER_SHIFT (0U)
27175
27177 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
27178 #define LPI2C_MFCR_RXWATER_MASK (0x30000U)
27179 #define LPI2C_MFCR_RXWATER_SHIFT (16U)
27180
27182 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
27183
27187 #define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
27188 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
27189
27191 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
27192 #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
27193 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
27194
27196 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
27197
27201 #define LPI2C_MTDR_DATA_MASK (0xFFU)
27202 #define LPI2C_MTDR_DATA_SHIFT (0U)
27203
27205 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
27206 #define LPI2C_MTDR_CMD_MASK (0x700U)
27207 #define LPI2C_MTDR_CMD_SHIFT (8U)
27208
27218 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
27219
27223 #define LPI2C_MRDR_DATA_MASK (0xFFU)
27224 #define LPI2C_MRDR_DATA_SHIFT (0U)
27225
27227 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
27228 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
27229 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
27230
27234 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
27235
27239 #define LPI2C_SCR_SEN_MASK (0x1U)
27240 #define LPI2C_SCR_SEN_SHIFT (0U)
27241
27245 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
27246 #define LPI2C_SCR_RST_MASK (0x2U)
27247 #define LPI2C_SCR_RST_SHIFT (1U)
27248
27252 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
27253 #define LPI2C_SCR_FILTEN_MASK (0x10U)
27254 #define LPI2C_SCR_FILTEN_SHIFT (4U)
27255
27259 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
27260 #define LPI2C_SCR_FILTDZ_MASK (0x20U)
27261 #define LPI2C_SCR_FILTDZ_SHIFT (5U)
27262
27266 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
27267 #define LPI2C_SCR_RTF_MASK (0x100U)
27268 #define LPI2C_SCR_RTF_SHIFT (8U)
27269
27273 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
27274 #define LPI2C_SCR_RRF_MASK (0x200U)
27275 #define LPI2C_SCR_RRF_SHIFT (9U)
27276
27280 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
27281
27285 #define LPI2C_SSR_TDF_MASK (0x1U)
27286 #define LPI2C_SSR_TDF_SHIFT (0U)
27287
27291 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
27292 #define LPI2C_SSR_RDF_MASK (0x2U)
27293 #define LPI2C_SSR_RDF_SHIFT (1U)
27294
27298 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
27299 #define LPI2C_SSR_AVF_MASK (0x4U)
27300 #define LPI2C_SSR_AVF_SHIFT (2U)
27301
27305 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
27306 #define LPI2C_SSR_TAF_MASK (0x8U)
27307 #define LPI2C_SSR_TAF_SHIFT (3U)
27308
27312 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
27313 #define LPI2C_SSR_RSF_MASK (0x100U)
27314 #define LPI2C_SSR_RSF_SHIFT (8U)
27315
27319 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
27320 #define LPI2C_SSR_SDF_MASK (0x200U)
27321 #define LPI2C_SSR_SDF_SHIFT (9U)
27322
27326 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
27327 #define LPI2C_SSR_BEF_MASK (0x400U)
27328 #define LPI2C_SSR_BEF_SHIFT (10U)
27329
27333 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
27334 #define LPI2C_SSR_FEF_MASK (0x800U)
27335 #define LPI2C_SSR_FEF_SHIFT (11U)
27336
27340 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
27341 #define LPI2C_SSR_AM0F_MASK (0x1000U)
27342 #define LPI2C_SSR_AM0F_SHIFT (12U)
27343
27347 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
27348 #define LPI2C_SSR_AM1F_MASK (0x2000U)
27349 #define LPI2C_SSR_AM1F_SHIFT (13U)
27350
27354 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
27355 #define LPI2C_SSR_GCF_MASK (0x4000U)
27356 #define LPI2C_SSR_GCF_SHIFT (14U)
27357
27361 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
27362 #define LPI2C_SSR_SARF_MASK (0x8000U)
27363 #define LPI2C_SSR_SARF_SHIFT (15U)
27364
27368 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
27369 #define LPI2C_SSR_SBF_MASK (0x1000000U)
27370 #define LPI2C_SSR_SBF_SHIFT (24U)
27371
27375 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
27376 #define LPI2C_SSR_BBF_MASK (0x2000000U)
27377 #define LPI2C_SSR_BBF_SHIFT (25U)
27378
27382 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
27383
27387 #define LPI2C_SIER_TDIE_MASK (0x1U)
27388 #define LPI2C_SIER_TDIE_SHIFT (0U)
27389
27393 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
27394 #define LPI2C_SIER_RDIE_MASK (0x2U)
27395 #define LPI2C_SIER_RDIE_SHIFT (1U)
27396
27400 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
27401 #define LPI2C_SIER_AVIE_MASK (0x4U)
27402 #define LPI2C_SIER_AVIE_SHIFT (2U)
27403
27407 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
27408 #define LPI2C_SIER_TAIE_MASK (0x8U)
27409 #define LPI2C_SIER_TAIE_SHIFT (3U)
27410
27414 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
27415 #define LPI2C_SIER_RSIE_MASK (0x100U)
27416 #define LPI2C_SIER_RSIE_SHIFT (8U)
27417
27421 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
27422 #define LPI2C_SIER_SDIE_MASK (0x200U)
27423 #define LPI2C_SIER_SDIE_SHIFT (9U)
27424
27428 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
27429 #define LPI2C_SIER_BEIE_MASK (0x400U)
27430 #define LPI2C_SIER_BEIE_SHIFT (10U)
27431
27435 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
27436 #define LPI2C_SIER_FEIE_MASK (0x800U)
27437 #define LPI2C_SIER_FEIE_SHIFT (11U)
27438
27442 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
27443 #define LPI2C_SIER_AM0IE_MASK (0x1000U)
27444 #define LPI2C_SIER_AM0IE_SHIFT (12U)
27445
27449 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
27450 #define LPI2C_SIER_AM1F_MASK (0x2000U)
27451 #define LPI2C_SIER_AM1F_SHIFT (13U)
27452
27456 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
27457 #define LPI2C_SIER_GCIE_MASK (0x4000U)
27458 #define LPI2C_SIER_GCIE_SHIFT (14U)
27459
27463 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
27464 #define LPI2C_SIER_SARIE_MASK (0x8000U)
27465 #define LPI2C_SIER_SARIE_SHIFT (15U)
27466
27470 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
27471
27475 #define LPI2C_SDER_TDDE_MASK (0x1U)
27476 #define LPI2C_SDER_TDDE_SHIFT (0U)
27477
27481 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
27482 #define LPI2C_SDER_RDDE_MASK (0x2U)
27483 #define LPI2C_SDER_RDDE_SHIFT (1U)
27484
27488 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
27489 #define LPI2C_SDER_AVDE_MASK (0x4U)
27490 #define LPI2C_SDER_AVDE_SHIFT (2U)
27491
27495 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
27496
27500 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
27501 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
27502
27506 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
27507 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
27508 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
27509
27513 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
27514 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
27515 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
27516
27520 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
27521 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
27522 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
27523
27527 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
27528 #define LPI2C_SCFGR1_GCEN_MASK (0x100U)
27529 #define LPI2C_SCFGR1_GCEN_SHIFT (8U)
27530
27534 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
27535 #define LPI2C_SCFGR1_SAEN_MASK (0x200U)
27536 #define LPI2C_SCFGR1_SAEN_SHIFT (9U)
27537
27541 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
27542 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
27543 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
27544
27548 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
27549 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
27550 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
27551
27557 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
27558 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
27559 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
27560
27564 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
27565 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
27566 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
27567
27571 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
27572 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
27573 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
27574
27584 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
27585
27589 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
27590 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
27591
27593 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
27594 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
27595 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
27596
27598 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
27599 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
27600 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
27601
27603 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
27604 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
27605 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
27606
27608 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
27609
27613 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
27614 #define LPI2C_SAMR_ADDR0_SHIFT (1U)
27615
27617 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
27618 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
27619 #define LPI2C_SAMR_ADDR1_SHIFT (17U)
27620
27622 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
27623
27627 #define LPI2C_SASR_RADDR_MASK (0x7FFU)
27628 #define LPI2C_SASR_RADDR_SHIFT (0U)
27629
27631 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
27632 #define LPI2C_SASR_ANV_MASK (0x4000U)
27633 #define LPI2C_SASR_ANV_SHIFT (14U)
27634
27638 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
27639
27643 #define LPI2C_STAR_TXNACK_MASK (0x1U)
27644 #define LPI2C_STAR_TXNACK_SHIFT (0U)
27645
27649 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
27650
27654 #define LPI2C_STDR_DATA_MASK (0xFFU)
27655 #define LPI2C_STDR_DATA_SHIFT (0U)
27656
27658 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
27659
27663 #define LPI2C_SRDR_DATA_MASK (0xFFU)
27664 #define LPI2C_SRDR_DATA_SHIFT (0U)
27665
27667 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
27668 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
27669 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
27670
27674 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
27675 #define LPI2C_SRDR_SOF_MASK (0x8000U)
27676 #define LPI2C_SRDR_SOF_SHIFT (15U)
27677
27681 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
27682 /* end of group LPI2C_Register_Masks */
27688
27689
27690 /* LPI2C - Peripheral instance base addresses */
27692 #define LPI2C1_BASE (0x403F0000u)
27693
27694 #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
27695
27696 #define LPI2C2_BASE (0x403F4000u)
27697
27698 #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
27699
27700 #define LPI2C3_BASE (0x403F8000u)
27701
27702 #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
27703
27704 #define LPI2C4_BASE (0x403FC000u)
27705
27706 #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
27707
27708 #define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
27709
27710 #define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
27711
27712 #define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
27713 /* end of group LPI2C_Peripheral_Access_Layer */
27717
27718
27719 /* ----------------------------------------------------------------------------
27720 -- LPSPI Peripheral Access Layer
27721 ---------------------------------------------------------------------------- */
27722
27729 typedef struct {
27730 __I uint32_t VERID;
27731 __I uint32_t PARAM;
27732 uint8_t RESERVED_0[8];
27733 __IO uint32_t CR;
27734 __IO uint32_t SR;
27735 __IO uint32_t IER;
27736 __IO uint32_t DER;
27737 __IO uint32_t CFGR0;
27738 __IO uint32_t CFGR1;
27739 uint8_t RESERVED_1[8];
27740 __IO uint32_t DMR0;
27741 __IO uint32_t DMR1;
27742 uint8_t RESERVED_2[8];
27743 __IO uint32_t CCR;
27744 uint8_t RESERVED_3[20];
27745 __IO uint32_t FCR;
27746 __I uint32_t FSR;
27747 __IO uint32_t TCR;
27748 __O uint32_t TDR;
27749 uint8_t RESERVED_4[8];
27750 __I uint32_t RSR;
27751 __I uint32_t RDR;
27752 } LPSPI_Type;
27753
27754 /* ----------------------------------------------------------------------------
27755 -- LPSPI Register Masks
27756 ---------------------------------------------------------------------------- */
27757
27765 #define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
27766 #define LPSPI_VERID_FEATURE_SHIFT (0U)
27767
27770 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
27771 #define LPSPI_VERID_MINOR_MASK (0xFF0000U)
27772 #define LPSPI_VERID_MINOR_SHIFT (16U)
27773
27775 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
27776 #define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
27777 #define LPSPI_VERID_MAJOR_SHIFT (24U)
27778
27780 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
27781
27785 #define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
27786 #define LPSPI_PARAM_TXFIFO_SHIFT (0U)
27787
27789 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
27790 #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
27791 #define LPSPI_PARAM_RXFIFO_SHIFT (8U)
27792
27794 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
27795 #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
27796 #define LPSPI_PARAM_PCSNUM_SHIFT (16U)
27797
27799 #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
27800
27804 #define LPSPI_CR_MEN_MASK (0x1U)
27805 #define LPSPI_CR_MEN_SHIFT (0U)
27806
27810 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
27811 #define LPSPI_CR_RST_MASK (0x2U)
27812 #define LPSPI_CR_RST_SHIFT (1U)
27813
27817 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
27818 #define LPSPI_CR_DOZEN_MASK (0x4U)
27819 #define LPSPI_CR_DOZEN_SHIFT (2U)
27820
27824 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
27825 #define LPSPI_CR_DBGEN_MASK (0x8U)
27826 #define LPSPI_CR_DBGEN_SHIFT (3U)
27827
27831 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
27832 #define LPSPI_CR_RTF_MASK (0x100U)
27833 #define LPSPI_CR_RTF_SHIFT (8U)
27834
27838 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
27839 #define LPSPI_CR_RRF_MASK (0x200U)
27840 #define LPSPI_CR_RRF_SHIFT (9U)
27841
27845 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
27846
27850 #define LPSPI_SR_TDF_MASK (0x1U)
27851 #define LPSPI_SR_TDF_SHIFT (0U)
27852
27856 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
27857 #define LPSPI_SR_RDF_MASK (0x2U)
27858 #define LPSPI_SR_RDF_SHIFT (1U)
27859
27863 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
27864 #define LPSPI_SR_WCF_MASK (0x100U)
27865 #define LPSPI_SR_WCF_SHIFT (8U)
27866
27870 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
27871 #define LPSPI_SR_FCF_MASK (0x200U)
27872 #define LPSPI_SR_FCF_SHIFT (9U)
27873
27877 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
27878 #define LPSPI_SR_TCF_MASK (0x400U)
27879 #define LPSPI_SR_TCF_SHIFT (10U)
27880
27884 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
27885 #define LPSPI_SR_TEF_MASK (0x800U)
27886 #define LPSPI_SR_TEF_SHIFT (11U)
27887
27891 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
27892 #define LPSPI_SR_REF_MASK (0x1000U)
27893 #define LPSPI_SR_REF_SHIFT (12U)
27894
27898 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
27899 #define LPSPI_SR_DMF_MASK (0x2000U)
27900 #define LPSPI_SR_DMF_SHIFT (13U)
27901
27905 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
27906 #define LPSPI_SR_MBF_MASK (0x1000000U)
27907 #define LPSPI_SR_MBF_SHIFT (24U)
27908
27912 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
27913
27917 #define LPSPI_IER_TDIE_MASK (0x1U)
27918 #define LPSPI_IER_TDIE_SHIFT (0U)
27919
27923 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
27924 #define LPSPI_IER_RDIE_MASK (0x2U)
27925 #define LPSPI_IER_RDIE_SHIFT (1U)
27926
27930 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
27931 #define LPSPI_IER_WCIE_MASK (0x100U)
27932 #define LPSPI_IER_WCIE_SHIFT (8U)
27933
27937 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
27938 #define LPSPI_IER_FCIE_MASK (0x200U)
27939 #define LPSPI_IER_FCIE_SHIFT (9U)
27940
27944 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
27945 #define LPSPI_IER_TCIE_MASK (0x400U)
27946 #define LPSPI_IER_TCIE_SHIFT (10U)
27947
27951 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
27952 #define LPSPI_IER_TEIE_MASK (0x800U)
27953 #define LPSPI_IER_TEIE_SHIFT (11U)
27954
27958 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
27959 #define LPSPI_IER_REIE_MASK (0x1000U)
27960 #define LPSPI_IER_REIE_SHIFT (12U)
27961
27965 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
27966 #define LPSPI_IER_DMIE_MASK (0x2000U)
27967 #define LPSPI_IER_DMIE_SHIFT (13U)
27968
27972 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
27973
27977 #define LPSPI_DER_TDDE_MASK (0x1U)
27978 #define LPSPI_DER_TDDE_SHIFT (0U)
27979
27983 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
27984 #define LPSPI_DER_RDDE_MASK (0x2U)
27985 #define LPSPI_DER_RDDE_SHIFT (1U)
27986
27990 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
27991
27995 #define LPSPI_CFGR0_HREN_MASK (0x1U)
27996 #define LPSPI_CFGR0_HREN_SHIFT (0U)
27997
28001 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
28002 #define LPSPI_CFGR0_HRPOL_MASK (0x2U)
28003 #define LPSPI_CFGR0_HRPOL_SHIFT (1U)
28004
28008 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
28009 #define LPSPI_CFGR0_HRSEL_MASK (0x4U)
28010 #define LPSPI_CFGR0_HRSEL_SHIFT (2U)
28011
28015 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
28016 #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
28017 #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
28018
28022 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
28023 #define LPSPI_CFGR0_RDMO_MASK (0x200U)
28024 #define LPSPI_CFGR0_RDMO_SHIFT (9U)
28025
28029 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
28030
28034 #define LPSPI_CFGR1_MASTER_MASK (0x1U)
28035 #define LPSPI_CFGR1_MASTER_SHIFT (0U)
28036
28040 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
28041 #define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
28042 #define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
28043
28047 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
28048 #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
28049 #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
28050
28054 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
28055 #define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
28056 #define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
28057
28061 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
28062 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
28063 #define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
28064
28068 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
28069 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
28070 #define LPSPI_CFGR1_MATCFG_SHIFT (16U)
28071
28083 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
28084 #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
28085 #define LPSPI_CFGR1_PINCFG_SHIFT (24U)
28086
28092 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
28093 #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
28094 #define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
28095
28099 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
28100 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
28101 #define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
28102
28106 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
28107
28111 #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
28112 #define LPSPI_DMR0_MATCH0_SHIFT (0U)
28113
28115 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
28116
28120 #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
28121 #define LPSPI_DMR1_MATCH1_SHIFT (0U)
28122
28124 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
28125
28129 #define LPSPI_CCR_SCKDIV_MASK (0xFFU)
28130 #define LPSPI_CCR_SCKDIV_SHIFT (0U)
28131
28133 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
28134 #define LPSPI_CCR_DBT_MASK (0xFF00U)
28135 #define LPSPI_CCR_DBT_SHIFT (8U)
28136
28138 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
28139 #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
28140 #define LPSPI_CCR_PCSSCK_SHIFT (16U)
28141
28143 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
28144 #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
28145 #define LPSPI_CCR_SCKPCS_SHIFT (24U)
28146
28148 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
28149
28153 #define LPSPI_FCR_TXWATER_MASK (0xFU)
28154 #define LPSPI_FCR_TXWATER_SHIFT (0U)
28155
28157 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
28158 #define LPSPI_FCR_RXWATER_MASK (0xF0000U)
28159 #define LPSPI_FCR_RXWATER_SHIFT (16U)
28160
28162 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
28163
28167 #define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
28168 #define LPSPI_FSR_TXCOUNT_SHIFT (0U)
28169
28171 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
28172 #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
28173 #define LPSPI_FSR_RXCOUNT_SHIFT (16U)
28174
28176 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
28177
28181 #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
28182 #define LPSPI_TCR_FRAMESZ_SHIFT (0U)
28183
28185 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
28186 #define LPSPI_TCR_WIDTH_MASK (0x30000U)
28187 #define LPSPI_TCR_WIDTH_SHIFT (16U)
28188
28194 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
28195 #define LPSPI_TCR_TXMSK_MASK (0x40000U)
28196 #define LPSPI_TCR_TXMSK_SHIFT (18U)
28197
28201 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
28202 #define LPSPI_TCR_RXMSK_MASK (0x80000U)
28203 #define LPSPI_TCR_RXMSK_SHIFT (19U)
28204
28208 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
28209 #define LPSPI_TCR_CONTC_MASK (0x100000U)
28210 #define LPSPI_TCR_CONTC_SHIFT (20U)
28211
28215 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
28216 #define LPSPI_TCR_CONT_MASK (0x200000U)
28217 #define LPSPI_TCR_CONT_SHIFT (21U)
28218
28222 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
28223 #define LPSPI_TCR_BYSW_MASK (0x400000U)
28224 #define LPSPI_TCR_BYSW_SHIFT (22U)
28225
28229 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
28230 #define LPSPI_TCR_LSBF_MASK (0x800000U)
28231 #define LPSPI_TCR_LSBF_SHIFT (23U)
28232
28236 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
28237 #define LPSPI_TCR_PCS_MASK (0x3000000U)
28238 #define LPSPI_TCR_PCS_SHIFT (24U)
28239
28245 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
28246 #define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
28247 #define LPSPI_TCR_PRESCALE_SHIFT (27U)
28248
28258 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
28259 #define LPSPI_TCR_CPHA_MASK (0x40000000U)
28260 #define LPSPI_TCR_CPHA_SHIFT (30U)
28261
28265 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
28266 #define LPSPI_TCR_CPOL_MASK (0x80000000U)
28267 #define LPSPI_TCR_CPOL_SHIFT (31U)
28268
28272 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
28273
28277 #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
28278 #define LPSPI_TDR_DATA_SHIFT (0U)
28279
28281 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
28282
28286 #define LPSPI_RSR_SOF_MASK (0x1U)
28287 #define LPSPI_RSR_SOF_SHIFT (0U)
28288
28292 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
28293 #define LPSPI_RSR_RXEMPTY_MASK (0x2U)
28294 #define LPSPI_RSR_RXEMPTY_SHIFT (1U)
28295
28299 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
28300
28304 #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
28305 #define LPSPI_RDR_DATA_SHIFT (0U)
28306
28308 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
28309 /* end of group LPSPI_Register_Masks */
28315
28316
28317 /* LPSPI - Peripheral instance base addresses */
28319 #define LPSPI1_BASE (0x40394000u)
28320
28321 #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
28322
28323 #define LPSPI2_BASE (0x40398000u)
28324
28325 #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
28326
28327 #define LPSPI3_BASE (0x4039C000u)
28328
28329 #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
28330
28331 #define LPSPI4_BASE (0x403A0000u)
28332
28333 #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
28334
28335 #define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
28336
28337 #define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
28338
28339 #define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
28340 /* end of group LPSPI_Peripheral_Access_Layer */
28344
28345
28346 /* ----------------------------------------------------------------------------
28347 -- LPUART Peripheral Access Layer
28348 ---------------------------------------------------------------------------- */
28349
28356 typedef struct {
28357 __I uint32_t VERID;
28358 __I uint32_t PARAM;
28359 __IO uint32_t GLOBAL;
28360 __IO uint32_t PINCFG;
28361 __IO uint32_t BAUD;
28362 __IO uint32_t STAT;
28363 __IO uint32_t CTRL;
28364 __IO uint32_t DATA;
28365 __IO uint32_t MATCH;
28366 __IO uint32_t MODIR;
28367 __IO uint32_t FIFO;
28368 __IO uint32_t WATER;
28369 } LPUART_Type;
28370
28371 /* ----------------------------------------------------------------------------
28372 -- LPUART Register Masks
28373 ---------------------------------------------------------------------------- */
28374
28382 #define LPUART_VERID_FEATURE_MASK (0xFFFFU)
28383 #define LPUART_VERID_FEATURE_SHIFT (0U)
28384
28388 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
28389 #define LPUART_VERID_MINOR_MASK (0xFF0000U)
28390 #define LPUART_VERID_MINOR_SHIFT (16U)
28391
28393 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
28394 #define LPUART_VERID_MAJOR_MASK (0xFF000000U)
28395 #define LPUART_VERID_MAJOR_SHIFT (24U)
28396
28398 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
28399
28403 #define LPUART_PARAM_TXFIFO_MASK (0xFFU)
28404 #define LPUART_PARAM_TXFIFO_SHIFT (0U)
28405
28407 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
28408 #define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
28409 #define LPUART_PARAM_RXFIFO_SHIFT (8U)
28410
28412 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
28413
28417 #define LPUART_GLOBAL_RST_MASK (0x2U)
28418 #define LPUART_GLOBAL_RST_SHIFT (1U)
28419
28423 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
28424
28428 #define LPUART_PINCFG_TRGSEL_MASK (0x3U)
28429 #define LPUART_PINCFG_TRGSEL_SHIFT (0U)
28430
28436 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
28437
28441 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
28442 #define LPUART_BAUD_SBR_SHIFT (0U)
28443
28445 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
28446 #define LPUART_BAUD_SBNS_MASK (0x2000U)
28447 #define LPUART_BAUD_SBNS_SHIFT (13U)
28448
28452 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
28453 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
28454 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
28455
28459 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
28460 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
28461 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
28462
28466 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
28467 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
28468 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
28469
28473 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
28474 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
28475 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
28476
28480 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
28481 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
28482 #define LPUART_BAUD_MATCFG_SHIFT (18U)
28483
28489 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
28490 #define LPUART_BAUD_RIDMAE_MASK (0x100000U)
28491 #define LPUART_BAUD_RIDMAE_SHIFT (20U)
28492
28496 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
28497 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
28498 #define LPUART_BAUD_RDMAE_SHIFT (21U)
28499
28503 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
28504 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
28505 #define LPUART_BAUD_TDMAE_SHIFT (23U)
28506
28510 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
28511 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
28512 #define LPUART_BAUD_OSR_SHIFT (24U)
28513
28547 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
28548 #define LPUART_BAUD_M10_MASK (0x20000000U)
28549 #define LPUART_BAUD_M10_SHIFT (29U)
28550
28554 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
28555 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
28556 #define LPUART_BAUD_MAEN2_SHIFT (30U)
28557
28561 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
28562 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
28563 #define LPUART_BAUD_MAEN1_SHIFT (31U)
28564
28568 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
28569
28573 #define LPUART_STAT_MA2F_MASK (0x4000U)
28574 #define LPUART_STAT_MA2F_SHIFT (14U)
28575
28579 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
28580 #define LPUART_STAT_MA1F_MASK (0x8000U)
28581 #define LPUART_STAT_MA1F_SHIFT (15U)
28582
28586 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
28587 #define LPUART_STAT_PF_MASK (0x10000U)
28588 #define LPUART_STAT_PF_SHIFT (16U)
28589
28593 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
28594 #define LPUART_STAT_FE_MASK (0x20000U)
28595 #define LPUART_STAT_FE_SHIFT (17U)
28596
28600 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
28601 #define LPUART_STAT_NF_MASK (0x40000U)
28602 #define LPUART_STAT_NF_SHIFT (18U)
28603
28607 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
28608 #define LPUART_STAT_OR_MASK (0x80000U)
28609 #define LPUART_STAT_OR_SHIFT (19U)
28610
28614 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
28615 #define LPUART_STAT_IDLE_MASK (0x100000U)
28616 #define LPUART_STAT_IDLE_SHIFT (20U)
28617
28621 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
28622 #define LPUART_STAT_RDRF_MASK (0x200000U)
28623 #define LPUART_STAT_RDRF_SHIFT (21U)
28624
28628 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
28629 #define LPUART_STAT_TC_MASK (0x400000U)
28630 #define LPUART_STAT_TC_SHIFT (22U)
28631
28635 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
28636 #define LPUART_STAT_TDRE_MASK (0x800000U)
28637 #define LPUART_STAT_TDRE_SHIFT (23U)
28638
28642 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
28643 #define LPUART_STAT_RAF_MASK (0x1000000U)
28644 #define LPUART_STAT_RAF_SHIFT (24U)
28645
28649 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
28650 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
28651 #define LPUART_STAT_LBKDE_SHIFT (25U)
28652
28656 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
28657 #define LPUART_STAT_BRK13_MASK (0x4000000U)
28658 #define LPUART_STAT_BRK13_SHIFT (26U)
28659
28663 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
28664 #define LPUART_STAT_RWUID_MASK (0x8000000U)
28665 #define LPUART_STAT_RWUID_SHIFT (27U)
28666
28672 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
28673 #define LPUART_STAT_RXINV_MASK (0x10000000U)
28674 #define LPUART_STAT_RXINV_SHIFT (28U)
28675
28679 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
28680 #define LPUART_STAT_MSBF_MASK (0x20000000U)
28681 #define LPUART_STAT_MSBF_SHIFT (29U)
28682
28689 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
28690 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
28691 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
28692
28696 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
28697 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
28698 #define LPUART_STAT_LBKDIF_SHIFT (31U)
28699
28703 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
28704
28708 #define LPUART_CTRL_PT_MASK (0x1U)
28709 #define LPUART_CTRL_PT_SHIFT (0U)
28710
28714 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
28715 #define LPUART_CTRL_PE_MASK (0x2U)
28716 #define LPUART_CTRL_PE_SHIFT (1U)
28717
28721 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
28722 #define LPUART_CTRL_ILT_MASK (0x4U)
28723 #define LPUART_CTRL_ILT_SHIFT (2U)
28724
28728 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
28729 #define LPUART_CTRL_WAKE_MASK (0x8U)
28730 #define LPUART_CTRL_WAKE_SHIFT (3U)
28731
28735 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
28736 #define LPUART_CTRL_M_MASK (0x10U)
28737 #define LPUART_CTRL_M_SHIFT (4U)
28738
28742 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
28743 #define LPUART_CTRL_RSRC_MASK (0x20U)
28744 #define LPUART_CTRL_RSRC_SHIFT (5U)
28745
28749 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
28750 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
28751 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
28752
28756 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
28757 #define LPUART_CTRL_LOOPS_MASK (0x80U)
28758 #define LPUART_CTRL_LOOPS_SHIFT (7U)
28759
28763 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
28764 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
28765 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
28766
28776 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
28777 #define LPUART_CTRL_M7_MASK (0x800U)
28778 #define LPUART_CTRL_M7_SHIFT (11U)
28779
28783 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
28784 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
28785 #define LPUART_CTRL_MA2IE_SHIFT (14U)
28786
28790 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
28791 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
28792 #define LPUART_CTRL_MA1IE_SHIFT (15U)
28793
28797 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
28798 #define LPUART_CTRL_SBK_MASK (0x10000U)
28799 #define LPUART_CTRL_SBK_SHIFT (16U)
28800
28804 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
28805 #define LPUART_CTRL_RWU_MASK (0x20000U)
28806 #define LPUART_CTRL_RWU_SHIFT (17U)
28807
28811 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
28812 #define LPUART_CTRL_RE_MASK (0x40000U)
28813 #define LPUART_CTRL_RE_SHIFT (18U)
28814
28818 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
28819 #define LPUART_CTRL_TE_MASK (0x80000U)
28820 #define LPUART_CTRL_TE_SHIFT (19U)
28821
28825 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
28826 #define LPUART_CTRL_ILIE_MASK (0x100000U)
28827 #define LPUART_CTRL_ILIE_SHIFT (20U)
28828
28832 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
28833 #define LPUART_CTRL_RIE_MASK (0x200000U)
28834 #define LPUART_CTRL_RIE_SHIFT (21U)
28835
28839 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
28840 #define LPUART_CTRL_TCIE_MASK (0x400000U)
28841 #define LPUART_CTRL_TCIE_SHIFT (22U)
28842
28846 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
28847 #define LPUART_CTRL_TIE_MASK (0x800000U)
28848 #define LPUART_CTRL_TIE_SHIFT (23U)
28849
28853 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
28854 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
28855 #define LPUART_CTRL_PEIE_SHIFT (24U)
28856
28860 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
28861 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
28862 #define LPUART_CTRL_FEIE_SHIFT (25U)
28863
28867 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
28868 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
28869 #define LPUART_CTRL_NEIE_SHIFT (26U)
28870
28874 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
28875 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
28876 #define LPUART_CTRL_ORIE_SHIFT (27U)
28877
28881 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
28882 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
28883 #define LPUART_CTRL_TXINV_SHIFT (28U)
28884
28888 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
28889 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
28890 #define LPUART_CTRL_TXDIR_SHIFT (29U)
28891
28895 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
28896 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
28897 #define LPUART_CTRL_R9T8_SHIFT (30U)
28898
28900 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
28901 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
28902 #define LPUART_CTRL_R8T9_SHIFT (31U)
28903
28905 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
28906
28910 #define LPUART_DATA_R0T0_MASK (0x1U)
28911 #define LPUART_DATA_R0T0_SHIFT (0U)
28912
28914 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
28915 #define LPUART_DATA_R1T1_MASK (0x2U)
28916 #define LPUART_DATA_R1T1_SHIFT (1U)
28917
28919 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
28920 #define LPUART_DATA_R2T2_MASK (0x4U)
28921 #define LPUART_DATA_R2T2_SHIFT (2U)
28922
28924 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
28925 #define LPUART_DATA_R3T3_MASK (0x8U)
28926 #define LPUART_DATA_R3T3_SHIFT (3U)
28927
28929 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
28930 #define LPUART_DATA_R4T4_MASK (0x10U)
28931 #define LPUART_DATA_R4T4_SHIFT (4U)
28932
28934 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
28935 #define LPUART_DATA_R5T5_MASK (0x20U)
28936 #define LPUART_DATA_R5T5_SHIFT (5U)
28937
28939 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
28940 #define LPUART_DATA_R6T6_MASK (0x40U)
28941 #define LPUART_DATA_R6T6_SHIFT (6U)
28942
28944 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
28945 #define LPUART_DATA_R7T7_MASK (0x80U)
28946 #define LPUART_DATA_R7T7_SHIFT (7U)
28947
28949 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
28950 #define LPUART_DATA_R8T8_MASK (0x100U)
28951 #define LPUART_DATA_R8T8_SHIFT (8U)
28952
28954 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
28955 #define LPUART_DATA_R9T9_MASK (0x200U)
28956 #define LPUART_DATA_R9T9_SHIFT (9U)
28957
28959 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
28960 #define LPUART_DATA_IDLINE_MASK (0x800U)
28961 #define LPUART_DATA_IDLINE_SHIFT (11U)
28962
28966 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
28967 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
28968 #define LPUART_DATA_RXEMPT_SHIFT (12U)
28969
28973 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
28974 #define LPUART_DATA_FRETSC_MASK (0x2000U)
28975 #define LPUART_DATA_FRETSC_SHIFT (13U)
28976
28980 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
28981 #define LPUART_DATA_PARITYE_MASK (0x4000U)
28982 #define LPUART_DATA_PARITYE_SHIFT (14U)
28983
28987 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
28988 #define LPUART_DATA_NOISY_MASK (0x8000U)
28989 #define LPUART_DATA_NOISY_SHIFT (15U)
28990
28994 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
28995
28999 #define LPUART_MATCH_MA1_MASK (0x3FFU)
29000 #define LPUART_MATCH_MA1_SHIFT (0U)
29001
29003 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
29004 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
29005 #define LPUART_MATCH_MA2_SHIFT (16U)
29006
29008 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
29009
29013 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
29014 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
29015
29022 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
29023 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
29024 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
29025
29031 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
29032 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
29033 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
29034
29038 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
29039 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
29040 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
29041
29047 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
29048 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
29049 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
29050
29054 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
29055 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
29056 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
29057
29061 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
29062 #define LPUART_MODIR_RTSWATER_MASK (0x300U)
29063 #define LPUART_MODIR_RTSWATER_SHIFT (8U)
29064
29066 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
29067 #define LPUART_MODIR_TNP_MASK (0x30000U)
29068 #define LPUART_MODIR_TNP_SHIFT (16U)
29069
29075 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
29076 #define LPUART_MODIR_IREN_MASK (0x40000U)
29077 #define LPUART_MODIR_IREN_SHIFT (18U)
29078
29082 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
29083
29087 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
29088 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
29089
29099 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
29100 #define LPUART_FIFO_RXFE_MASK (0x8U)
29101 #define LPUART_FIFO_RXFE_SHIFT (3U)
29102
29106 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
29107 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
29108 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
29109
29119 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
29120 #define LPUART_FIFO_TXFE_MASK (0x80U)
29121 #define LPUART_FIFO_TXFE_SHIFT (7U)
29122
29126 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
29127 #define LPUART_FIFO_RXUFE_MASK (0x100U)
29128 #define LPUART_FIFO_RXUFE_SHIFT (8U)
29129
29133 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
29134 #define LPUART_FIFO_TXOFE_MASK (0x200U)
29135 #define LPUART_FIFO_TXOFE_SHIFT (9U)
29136
29140 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
29141 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
29142 #define LPUART_FIFO_RXIDEN_SHIFT (10U)
29143
29153 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
29154 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
29155 #define LPUART_FIFO_RXFLUSH_SHIFT (14U)
29156
29160 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
29161 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
29162 #define LPUART_FIFO_TXFLUSH_SHIFT (15U)
29163
29167 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
29168 #define LPUART_FIFO_RXUF_MASK (0x10000U)
29169 #define LPUART_FIFO_RXUF_SHIFT (16U)
29170
29174 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
29175 #define LPUART_FIFO_TXOF_MASK (0x20000U)
29176 #define LPUART_FIFO_TXOF_SHIFT (17U)
29177
29181 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
29182 #define LPUART_FIFO_RXEMPT_MASK (0x400000U)
29183 #define LPUART_FIFO_RXEMPT_SHIFT (22U)
29184
29188 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
29189 #define LPUART_FIFO_TXEMPT_MASK (0x800000U)
29190 #define LPUART_FIFO_TXEMPT_SHIFT (23U)
29191
29195 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
29196
29200 #define LPUART_WATER_TXWATER_MASK (0x3U)
29201 #define LPUART_WATER_TXWATER_SHIFT (0U)
29202
29204 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
29205 #define LPUART_WATER_TXCOUNT_MASK (0x700U)
29206 #define LPUART_WATER_TXCOUNT_SHIFT (8U)
29207
29209 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
29210 #define LPUART_WATER_RXWATER_MASK (0x30000U)
29211 #define LPUART_WATER_RXWATER_SHIFT (16U)
29212
29214 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
29215 #define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
29216 #define LPUART_WATER_RXCOUNT_SHIFT (24U)
29217
29219 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
29220 /* end of group LPUART_Register_Masks */
29226
29227
29228 /* LPUART - Peripheral instance base addresses */
29230 #define LPUART1_BASE (0x40184000u)
29231
29232 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
29233
29234 #define LPUART2_BASE (0x40188000u)
29235
29236 #define LPUART2 ((LPUART_Type *)LPUART2_BASE)
29237
29238 #define LPUART3_BASE (0x4018C000u)
29239
29240 #define LPUART3 ((LPUART_Type *)LPUART3_BASE)
29241
29242 #define LPUART4_BASE (0x40190000u)
29243
29244 #define LPUART4 ((LPUART_Type *)LPUART4_BASE)
29245
29246 #define LPUART5_BASE (0x40194000u)
29247
29248 #define LPUART5 ((LPUART_Type *)LPUART5_BASE)
29249
29250 #define LPUART6_BASE (0x40198000u)
29251
29252 #define LPUART6 ((LPUART_Type *)LPUART6_BASE)
29253
29254 #define LPUART7_BASE (0x4019C000u)
29255
29256 #define LPUART7 ((LPUART_Type *)LPUART7_BASE)
29257
29258 #define LPUART8_BASE (0x401A0000u)
29259
29260 #define LPUART8 ((LPUART_Type *)LPUART8_BASE)
29261
29262 #define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
29263
29264 #define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
29265
29266 #define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
29267 /* end of group LPUART_Peripheral_Access_Layer */
29271
29272
29273 /* ----------------------------------------------------------------------------
29274 -- OCOTP Peripheral Access Layer
29275 ---------------------------------------------------------------------------- */
29276
29283 typedef struct {
29284 __IO uint32_t CTRL;
29285 __IO uint32_t CTRL_SET;
29286 __IO uint32_t CTRL_CLR;
29287 __IO uint32_t CTRL_TOG;
29288 __IO uint32_t TIMING;
29289 uint8_t RESERVED_0[12];
29290 __IO uint32_t DATA;
29291 uint8_t RESERVED_1[12];
29292 __IO uint32_t READ_CTRL;
29293 uint8_t RESERVED_2[12];
29294 __IO uint32_t READ_FUSE_DATA;
29295 uint8_t RESERVED_3[12];
29296 __IO uint32_t SW_STICKY;
29297 uint8_t RESERVED_4[12];
29298 __IO uint32_t SCS;
29299 __IO uint32_t SCS_SET;
29300 __IO uint32_t SCS_CLR;
29301 __IO uint32_t SCS_TOG;
29302 __IO uint32_t CRC_ADDR;
29303 uint8_t RESERVED_5[12];
29304 __IO uint32_t CRC_VALUE;
29305 uint8_t RESERVED_6[12];
29306 __I uint32_t VERSION;
29307 uint8_t RESERVED_7[108];
29308 __IO uint32_t TIMING2;
29309 uint8_t RESERVED_8[764];
29310 __IO uint32_t LOCK;
29311 uint8_t RESERVED_9[12];
29312 __IO uint32_t CFG0;
29313 uint8_t RESERVED_10[12];
29314 __IO uint32_t CFG1;
29315 uint8_t RESERVED_11[12];
29316 __IO uint32_t CFG2;
29317 uint8_t RESERVED_12[12];
29318 __IO uint32_t CFG3;
29319 uint8_t RESERVED_13[12];
29320 __IO uint32_t CFG4;
29321 uint8_t RESERVED_14[12];
29322 __IO uint32_t CFG5;
29323 uint8_t RESERVED_15[12];
29324 __IO uint32_t CFG6;
29325 uint8_t RESERVED_16[12];
29326 __IO uint32_t MEM0;
29327 uint8_t RESERVED_17[12];
29328 __IO uint32_t MEM1;
29329 uint8_t RESERVED_18[12];
29330 __IO uint32_t MEM2;
29331 uint8_t RESERVED_19[12];
29332 __IO uint32_t MEM3;
29333 uint8_t RESERVED_20[12];
29334 __IO uint32_t MEM4;
29335 uint8_t RESERVED_21[12];
29336 __IO uint32_t ANA0;
29337 uint8_t RESERVED_22[12];
29338 __IO uint32_t ANA1;
29339 uint8_t RESERVED_23[12];
29340 __IO uint32_t ANA2;
29341 uint8_t RESERVED_24[12];
29342 __IO uint32_t OTPMK0;
29343 uint8_t RESERVED_25[12];
29344 __IO uint32_t OTPMK1;
29345 uint8_t RESERVED_26[12];
29346 __IO uint32_t OTPMK2;
29347 uint8_t RESERVED_27[12];
29348 __IO uint32_t OTPMK3;
29349 uint8_t RESERVED_28[12];
29350 __IO uint32_t OTPMK4;
29351 uint8_t RESERVED_29[12];
29352 __IO uint32_t OTPMK5;
29353 uint8_t RESERVED_30[12];
29354 __IO uint32_t OTPMK6;
29355 uint8_t RESERVED_31[12];
29356 __IO uint32_t OTPMK7;
29357 uint8_t RESERVED_32[12];
29358 __IO uint32_t SRK0;
29359 uint8_t RESERVED_33[12];
29360 __IO uint32_t SRK1;
29361 uint8_t RESERVED_34[12];
29362 __IO uint32_t SRK2;
29363 uint8_t RESERVED_35[12];
29364 __IO uint32_t SRK3;
29365 uint8_t RESERVED_36[12];
29366 __IO uint32_t SRK4;
29367 uint8_t RESERVED_37[12];
29368 __IO uint32_t SRK5;
29369 uint8_t RESERVED_38[12];
29370 __IO uint32_t SRK6;
29371 uint8_t RESERVED_39[12];
29372 __IO uint32_t SRK7;
29373 uint8_t RESERVED_40[12];
29374 __IO uint32_t SJC_RESP0;
29375 uint8_t RESERVED_41[12];
29376 __IO uint32_t SJC_RESP1;
29377 uint8_t RESERVED_42[12];
29378 __IO uint32_t MAC0;
29379 uint8_t RESERVED_43[12];
29380 __IO uint32_t MAC1;
29381 uint8_t RESERVED_44[12];
29382 __IO uint32_t MAC2;
29383 uint8_t RESERVED_45[12];
29384 __IO uint32_t OTPMK_CRC32;
29385 uint8_t RESERVED_46[12];
29386 __IO uint32_t GP1;
29387 uint8_t RESERVED_47[12];
29388 __IO uint32_t GP2;
29389 uint8_t RESERVED_48[12];
29390 __IO uint32_t SW_GP1;
29391 uint8_t RESERVED_49[12];
29392 __IO uint32_t SW_GP20;
29393 uint8_t RESERVED_50[12];
29394 __IO uint32_t SW_GP21;
29395 uint8_t RESERVED_51[12];
29396 __IO uint32_t SW_GP22;
29397 uint8_t RESERVED_52[12];
29398 __IO uint32_t SW_GP23;
29399 uint8_t RESERVED_53[12];
29400 __IO uint32_t MISC_CONF0;
29401 uint8_t RESERVED_54[12];
29402 __IO uint32_t MISC_CONF1;
29403 uint8_t RESERVED_55[12];
29404 __IO uint32_t SRK_REVOKE;
29405 uint8_t RESERVED_56[268];
29406 __IO uint32_t ROM_PATCH0;
29407 uint8_t RESERVED_57[12];
29408 __IO uint32_t ROM_PATCH1;
29409 uint8_t RESERVED_58[12];
29410 __IO uint32_t ROM_PATCH2;
29411 uint8_t RESERVED_59[12];
29412 __IO uint32_t ROM_PATCH3;
29413 uint8_t RESERVED_60[12];
29414 __IO uint32_t ROM_PATCH4;
29415 uint8_t RESERVED_61[12];
29416 __IO uint32_t ROM_PATCH5;
29417 uint8_t RESERVED_62[12];
29418 __IO uint32_t ROM_PATCH6;
29419 uint8_t RESERVED_63[12];
29420 __IO uint32_t ROM_PATCH7;
29421 uint8_t RESERVED_64[12];
29422 __IO uint32_t GP30;
29423 uint8_t RESERVED_65[12];
29424 __IO uint32_t GP31;
29425 uint8_t RESERVED_66[12];
29426 __IO uint32_t GP32;
29427 uint8_t RESERVED_67[12];
29428 __IO uint32_t GP33;
29429 uint8_t RESERVED_68[12];
29430 __IO uint32_t GP40;
29431 uint8_t RESERVED_69[12];
29432 __IO uint32_t GP41;
29433 uint8_t RESERVED_70[12];
29434 __IO uint32_t GP42;
29435 uint8_t RESERVED_71[12];
29436 __IO uint32_t GP43;
29437 } OCOTP_Type;
29438
29439 /* ----------------------------------------------------------------------------
29440 -- OCOTP Register Masks
29441 ---------------------------------------------------------------------------- */
29442
29450 #define OCOTP_CTRL_ADDR_MASK (0x3FU)
29451 #define OCOTP_CTRL_ADDR_SHIFT (0U)
29452
29454 #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
29455 #define OCOTP_CTRL_RSVD0_MASK (0xC0U)
29456 #define OCOTP_CTRL_RSVD0_SHIFT (6U)
29457
29459 #define OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD0_SHIFT)) & OCOTP_CTRL_RSVD0_MASK)
29460 #define OCOTP_CTRL_BUSY_MASK (0x100U)
29461 #define OCOTP_CTRL_BUSY_SHIFT (8U)
29462
29464 #define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
29465 #define OCOTP_CTRL_ERROR_MASK (0x200U)
29466 #define OCOTP_CTRL_ERROR_SHIFT (9U)
29467
29469 #define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
29470 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
29471 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
29472
29474 #define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
29475 #define OCOTP_CTRL_CRC_TEST_MASK (0x800U)
29476 #define OCOTP_CTRL_CRC_TEST_SHIFT (11U)
29477
29479 #define OCOTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_CTRL_CRC_TEST_MASK)
29480 #define OCOTP_CTRL_CRC_FAIL_MASK (0x1000U)
29481 #define OCOTP_CTRL_CRC_FAIL_SHIFT (12U)
29482
29484 #define OCOTP_CTRL_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CRC_FAIL_MASK)
29485 #define OCOTP_CTRL_RSVD1_MASK (0xE000U)
29486 #define OCOTP_CTRL_RSVD1_SHIFT (13U)
29487
29489 #define OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD1_SHIFT)) & OCOTP_CTRL_RSVD1_MASK)
29490 #define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
29491 #define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
29492
29495 #define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
29496
29500 #define OCOTP_CTRL_SET_ADDR_MASK (0x3FU)
29501 #define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
29502
29504 #define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
29505 #define OCOTP_CTRL_SET_RSVD0_MASK (0xC0U)
29506 #define OCOTP_CTRL_SET_RSVD0_SHIFT (6U)
29507
29509 #define OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD0_SHIFT)) & OCOTP_CTRL_SET_RSVD0_MASK)
29510 #define OCOTP_CTRL_SET_BUSY_MASK (0x100U)
29511 #define OCOTP_CTRL_SET_BUSY_SHIFT (8U)
29512
29514 #define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
29515 #define OCOTP_CTRL_SET_ERROR_MASK (0x200U)
29516 #define OCOTP_CTRL_SET_ERROR_SHIFT (9U)
29517
29519 #define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
29520 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
29521 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
29522
29524 #define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
29525 #define OCOTP_CTRL_SET_CRC_TEST_MASK (0x800U)
29526 #define OCOTP_CTRL_SET_CRC_TEST_SHIFT (11U)
29527
29529 #define OCOTP_CTRL_SET_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_TEST_SHIFT)) & OCOTP_CTRL_SET_CRC_TEST_MASK)
29530 #define OCOTP_CTRL_SET_CRC_FAIL_MASK (0x1000U)
29531 #define OCOTP_CTRL_SET_CRC_FAIL_SHIFT (12U)
29532
29534 #define OCOTP_CTRL_SET_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_FAIL_SHIFT)) & OCOTP_CTRL_SET_CRC_FAIL_MASK)
29535 #define OCOTP_CTRL_SET_RSVD1_MASK (0xE000U)
29536 #define OCOTP_CTRL_SET_RSVD1_SHIFT (13U)
29537
29539 #define OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD1_SHIFT)) & OCOTP_CTRL_SET_RSVD1_MASK)
29540 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
29541 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
29542
29544 #define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
29545
29549 #define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)
29550 #define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
29551
29553 #define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
29554 #define OCOTP_CTRL_CLR_RSVD0_MASK (0xC0U)
29555 #define OCOTP_CTRL_CLR_RSVD0_SHIFT (6U)
29556
29558 #define OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD0_SHIFT)) & OCOTP_CTRL_CLR_RSVD0_MASK)
29559 #define OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
29560 #define OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
29561
29563 #define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
29564 #define OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
29565 #define OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
29566
29568 #define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
29569 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
29570 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
29571
29573 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
29574 #define OCOTP_CTRL_CLR_CRC_TEST_MASK (0x800U)
29575 #define OCOTP_CTRL_CLR_CRC_TEST_SHIFT (11U)
29576
29578 #define OCOTP_CTRL_CLR_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_TEST_SHIFT)) & OCOTP_CTRL_CLR_CRC_TEST_MASK)
29579 #define OCOTP_CTRL_CLR_CRC_FAIL_MASK (0x1000U)
29580 #define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT (12U)
29581
29583 #define OCOTP_CTRL_CLR_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CLR_CRC_FAIL_MASK)
29584 #define OCOTP_CTRL_CLR_RSVD1_MASK (0xE000U)
29585 #define OCOTP_CTRL_CLR_RSVD1_SHIFT (13U)
29586
29588 #define OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD1_SHIFT)) & OCOTP_CTRL_CLR_RSVD1_MASK)
29589 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
29590 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
29591
29593 #define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
29594
29598 #define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)
29599 #define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
29600
29602 #define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
29603 #define OCOTP_CTRL_TOG_RSVD0_MASK (0xC0U)
29604 #define OCOTP_CTRL_TOG_RSVD0_SHIFT (6U)
29605
29607 #define OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD0_SHIFT)) & OCOTP_CTRL_TOG_RSVD0_MASK)
29608 #define OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
29609 #define OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
29610
29612 #define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
29613 #define OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
29614 #define OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
29615
29617 #define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
29618 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
29619 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
29620
29622 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
29623 #define OCOTP_CTRL_TOG_CRC_TEST_MASK (0x800U)
29624 #define OCOTP_CTRL_TOG_CRC_TEST_SHIFT (11U)
29625
29627 #define OCOTP_CTRL_TOG_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_TEST_SHIFT)) & OCOTP_CTRL_TOG_CRC_TEST_MASK)
29628 #define OCOTP_CTRL_TOG_CRC_FAIL_MASK (0x1000U)
29629 #define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT (12U)
29630
29632 #define OCOTP_CTRL_TOG_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_FAIL_SHIFT)) & OCOTP_CTRL_TOG_CRC_FAIL_MASK)
29633 #define OCOTP_CTRL_TOG_RSVD1_MASK (0xE000U)
29634 #define OCOTP_CTRL_TOG_RSVD1_SHIFT (13U)
29635
29637 #define OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD1_SHIFT)) & OCOTP_CTRL_TOG_RSVD1_MASK)
29638 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
29639 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
29640
29642 #define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
29643
29647 #define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
29648 #define OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
29649
29651 #define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
29652 #define OCOTP_TIMING_RELAX_MASK (0xF000U)
29653 #define OCOTP_TIMING_RELAX_SHIFT (12U)
29654
29656 #define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
29657 #define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
29658 #define OCOTP_TIMING_STROBE_READ_SHIFT (16U)
29659
29661 #define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
29662 #define OCOTP_TIMING_WAIT_MASK (0xFC00000U)
29663 #define OCOTP_TIMING_WAIT_SHIFT (22U)
29664
29666 #define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
29667 #define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U)
29668 #define OCOTP_TIMING_RSRVD0_SHIFT (28U)
29669
29671 #define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK)
29672
29676 #define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
29677 #define OCOTP_DATA_DATA_SHIFT (0U)
29678
29680 #define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
29681
29685 #define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
29686 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
29687
29689 #define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
29690 #define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU)
29691 #define OCOTP_READ_CTRL_RSVD0_SHIFT (1U)
29692
29694 #define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK)
29695
29699 #define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
29700 #define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
29701
29703 #define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
29704
29708 #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)
29709 #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)
29710
29712 #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)
29713 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
29714 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
29715
29717 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
29718 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
29719 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
29720
29722 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
29723 #define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)
29724 #define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)
29725
29727 #define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)
29728 #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)
29729 #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)
29730
29732 #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)
29733 #define OCOTP_SW_STICKY_RSVD0_MASK (0xFFFFFFE0U)
29734 #define OCOTP_SW_STICKY_RSVD0_SHIFT (5U)
29735
29737 #define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK)
29738
29742 #define OCOTP_SCS_HAB_JDE_MASK (0x1U)
29743 #define OCOTP_SCS_HAB_JDE_SHIFT (0U)
29744
29746 #define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
29747 #define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
29748 #define OCOTP_SCS_SPARE_SHIFT (1U)
29749
29751 #define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
29752 #define OCOTP_SCS_LOCK_MASK (0x80000000U)
29753 #define OCOTP_SCS_LOCK_SHIFT (31U)
29754
29756 #define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
29757
29761 #define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
29762 #define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
29763
29765 #define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
29766 #define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
29767 #define OCOTP_SCS_SET_SPARE_SHIFT (1U)
29768
29770 #define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
29771 #define OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
29772 #define OCOTP_SCS_SET_LOCK_SHIFT (31U)
29773
29775 #define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
29776
29780 #define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
29781 #define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
29782
29784 #define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
29785 #define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
29786 #define OCOTP_SCS_CLR_SPARE_SHIFT (1U)
29787
29789 #define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
29790 #define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
29791 #define OCOTP_SCS_CLR_LOCK_SHIFT (31U)
29792
29794 #define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
29795
29799 #define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
29800 #define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
29801
29803 #define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
29804 #define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
29805 #define OCOTP_SCS_TOG_SPARE_SHIFT (1U)
29806
29808 #define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
29809 #define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
29810 #define OCOTP_SCS_TOG_LOCK_SHIFT (31U)
29811
29813 #define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
29814
29818 #define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xFFU)
29819 #define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0U)
29820
29822 #define OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_START_ADDR_MASK)
29823 #define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xFF00U)
29824 #define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8U)
29825
29827 #define OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_END_ADDR_MASK)
29828 #define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0xFF0000U)
29829 #define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16U)
29830
29832 #define OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)) & OCOTP_CRC_ADDR_CRC_ADDR_MASK)
29833 #define OCOTP_CRC_ADDR_OTPMK_CRC_MASK (0x1000000U)
29834 #define OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT (24U)
29835
29837 #define OCOTP_CRC_ADDR_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT)) & OCOTP_CRC_ADDR_OTPMK_CRC_MASK)
29838 #define OCOTP_CRC_ADDR_RSVD0_MASK (0xFE000000U)
29839 #define OCOTP_CRC_ADDR_RSVD0_SHIFT (25U)
29840
29842 #define OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_RSVD0_SHIFT)) & OCOTP_CRC_ADDR_RSVD0_MASK)
29843
29847 #define OCOTP_CRC_VALUE_DATA_MASK (0xFFFFFFFFU)
29848 #define OCOTP_CRC_VALUE_DATA_SHIFT (0U)
29849
29851 #define OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_VALUE_DATA_SHIFT)) & OCOTP_CRC_VALUE_DATA_MASK)
29852
29856 #define OCOTP_VERSION_STEP_MASK (0xFFFFU)
29857 #define OCOTP_VERSION_STEP_SHIFT (0U)
29858
29860 #define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
29861 #define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
29862 #define OCOTP_VERSION_MINOR_SHIFT (16U)
29863
29865 #define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
29866 #define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
29867 #define OCOTP_VERSION_MAJOR_SHIFT (24U)
29868
29870 #define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
29871
29875 #define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)
29876 #define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)
29877
29879 #define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
29880 #define OCOTP_TIMING2_RSRVD0_MASK (0xF000U)
29881 #define OCOTP_TIMING2_RSRVD0_SHIFT (12U)
29882
29884 #define OCOTP_TIMING2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RSRVD0_SHIFT)) & OCOTP_TIMING2_RSRVD0_MASK)
29885 #define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)
29886 #define OCOTP_TIMING2_RELAX_READ_SHIFT (16U)
29887
29889 #define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
29890 #define OCOTP_TIMING2_RSRVD1_MASK (0xFFC00000U)
29891 #define OCOTP_TIMING2_RSRVD1_SHIFT (22U)
29892
29894 #define OCOTP_TIMING2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RSRVD1_SHIFT)) & OCOTP_TIMING2_RSRVD1_MASK)
29895
29899 #define OCOTP_LOCK_TESTER_MASK (0x3U)
29900 #define OCOTP_LOCK_TESTER_SHIFT (0U)
29901
29903 #define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)
29904 #define OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
29905 #define OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
29906
29908 #define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
29909 #define OCOTP_LOCK_MEM_TRIM_MASK (0x30U)
29910 #define OCOTP_LOCK_MEM_TRIM_SHIFT (4U)
29911
29913 #define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)
29914 #define OCOTP_LOCK_SJC_RESP_MASK (0x40U)
29915 #define OCOTP_LOCK_SJC_RESP_SHIFT (6U)
29916
29918 #define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
29919 #define OCOTP_LOCK_GP4_RLOCK_MASK (0x80U)
29920 #define OCOTP_LOCK_GP4_RLOCK_SHIFT (7U)
29921
29923 #define OCOTP_LOCK_GP4_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_RLOCK_SHIFT)) & OCOTP_LOCK_GP4_RLOCK_MASK)
29924 #define OCOTP_LOCK_MAC_ADDR_MASK (0x300U)
29925 #define OCOTP_LOCK_MAC_ADDR_SHIFT (8U)
29926
29928 #define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
29929 #define OCOTP_LOCK_GP1_MASK (0xC00U)
29930 #define OCOTP_LOCK_GP1_SHIFT (10U)
29931
29933 #define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
29934 #define OCOTP_LOCK_GP2_MASK (0x3000U)
29935 #define OCOTP_LOCK_GP2_SHIFT (12U)
29936
29938 #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
29939 #define OCOTP_LOCK_ROM_PATCH_MASK (0x8000U)
29940 #define OCOTP_LOCK_ROM_PATCH_SHIFT (15U)
29941
29943 #define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK)
29944 #define OCOTP_LOCK_SW_GP1_MASK (0x10000U)
29945 #define OCOTP_LOCK_SW_GP1_SHIFT (16U)
29946
29948 #define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
29949 #define OCOTP_LOCK_OTPMK_MASK (0x20000U)
29950 #define OCOTP_LOCK_OTPMK_SHIFT (17U)
29951
29953 #define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK)
29954 #define OCOTP_LOCK_ANALOG_MASK (0xC0000U)
29955 #define OCOTP_LOCK_ANALOG_SHIFT (18U)
29956
29958 #define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
29959 #define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)
29960 #define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U)
29961
29963 #define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)
29964 #define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)
29965 #define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)
29966
29968 #define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
29969 #define OCOTP_LOCK_MISC_CONF_MASK (0x400000U)
29970 #define OCOTP_LOCK_MISC_CONF_SHIFT (22U)
29971
29973 #define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
29974 #define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)
29975 #define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)
29976
29978 #define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
29979 #define OCOTP_LOCK_GP4_MASK (0x3000000U)
29980 #define OCOTP_LOCK_GP4_SHIFT (24U)
29981
29983 #define OCOTP_LOCK_GP4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_SHIFT)) & OCOTP_LOCK_GP4_MASK)
29984 #define OCOTP_LOCK_GP3_MASK (0xC000000U)
29985 #define OCOTP_LOCK_GP3_SHIFT (26U)
29986
29988 #define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
29989 #define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)
29990 #define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U)
29991
29993 #define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
29994
29998 #define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)
29999 #define OCOTP_CFG0_BITS_SHIFT (0U)
30000
30002 #define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
30003
30007 #define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)
30008 #define OCOTP_CFG1_BITS_SHIFT (0U)
30009
30011 #define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
30012
30016 #define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)
30017 #define OCOTP_CFG2_BITS_SHIFT (0U)
30018
30020 #define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
30021
30025 #define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)
30026 #define OCOTP_CFG3_BITS_SHIFT (0U)
30027
30029 #define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
30030
30034 #define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)
30035 #define OCOTP_CFG4_BITS_SHIFT (0U)
30036
30038 #define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
30039
30043 #define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)
30044 #define OCOTP_CFG5_BITS_SHIFT (0U)
30045
30047 #define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
30048
30052 #define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)
30053 #define OCOTP_CFG6_BITS_SHIFT (0U)
30054
30056 #define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
30057
30061 #define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)
30062 #define OCOTP_MEM0_BITS_SHIFT (0U)
30063
30065 #define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
30066
30070 #define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)
30071 #define OCOTP_MEM1_BITS_SHIFT (0U)
30072
30074 #define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
30075
30079 #define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)
30080 #define OCOTP_MEM2_BITS_SHIFT (0U)
30081
30083 #define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
30084
30088 #define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)
30089 #define OCOTP_MEM3_BITS_SHIFT (0U)
30090
30092 #define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
30093
30097 #define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)
30098 #define OCOTP_MEM4_BITS_SHIFT (0U)
30099
30101 #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
30102
30106 #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
30107 #define OCOTP_ANA0_BITS_SHIFT (0U)
30108
30110 #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
30111
30115 #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
30116 #define OCOTP_ANA1_BITS_SHIFT (0U)
30117
30119 #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
30120
30124 #define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)
30125 #define OCOTP_ANA2_BITS_SHIFT (0U)
30126
30128 #define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
30129
30133 #define OCOTP_OTPMK0_BITS_MASK (0xFFFFFFFFU)
30134 #define OCOTP_OTPMK0_BITS_SHIFT (0U)
30135
30137 #define OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK0_BITS_SHIFT)) & OCOTP_OTPMK0_BITS_MASK)
30138
30142 #define OCOTP_OTPMK1_BITS_MASK (0xFFFFFFFFU)
30143 #define OCOTP_OTPMK1_BITS_SHIFT (0U)
30144
30146 #define OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK1_BITS_SHIFT)) & OCOTP_OTPMK1_BITS_MASK)
30147
30151 #define OCOTP_OTPMK2_BITS_MASK (0xFFFFFFFFU)
30152 #define OCOTP_OTPMK2_BITS_SHIFT (0U)
30153
30155 #define OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK2_BITS_SHIFT)) & OCOTP_OTPMK2_BITS_MASK)
30156
30160 #define OCOTP_OTPMK3_BITS_MASK (0xFFFFFFFFU)
30161 #define OCOTP_OTPMK3_BITS_SHIFT (0U)
30162
30164 #define OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK3_BITS_SHIFT)) & OCOTP_OTPMK3_BITS_MASK)
30165
30169 #define OCOTP_OTPMK4_BITS_MASK (0xFFFFFFFFU)
30170 #define OCOTP_OTPMK4_BITS_SHIFT (0U)
30171
30173 #define OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK4_BITS_SHIFT)) & OCOTP_OTPMK4_BITS_MASK)
30174
30178 #define OCOTP_OTPMK5_BITS_MASK (0xFFFFFFFFU)
30179 #define OCOTP_OTPMK5_BITS_SHIFT (0U)
30180
30182 #define OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK5_BITS_SHIFT)) & OCOTP_OTPMK5_BITS_MASK)
30183
30187 #define OCOTP_OTPMK6_BITS_MASK (0xFFFFFFFFU)
30188 #define OCOTP_OTPMK6_BITS_SHIFT (0U)
30189
30191 #define OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK6_BITS_SHIFT)) & OCOTP_OTPMK6_BITS_MASK)
30192
30196 #define OCOTP_OTPMK7_BITS_MASK (0xFFFFFFFFU)
30197 #define OCOTP_OTPMK7_BITS_SHIFT (0U)
30198
30200 #define OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK7_BITS_SHIFT)) & OCOTP_OTPMK7_BITS_MASK)
30201
30205 #define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
30206 #define OCOTP_SRK0_BITS_SHIFT (0U)
30207
30209 #define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
30210
30214 #define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
30215 #define OCOTP_SRK1_BITS_SHIFT (0U)
30216
30218 #define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
30219
30223 #define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
30224 #define OCOTP_SRK2_BITS_SHIFT (0U)
30225
30227 #define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
30228
30232 #define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
30233 #define OCOTP_SRK3_BITS_SHIFT (0U)
30234
30236 #define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
30237
30241 #define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
30242 #define OCOTP_SRK4_BITS_SHIFT (0U)
30243
30245 #define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
30246
30250 #define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
30251 #define OCOTP_SRK5_BITS_SHIFT (0U)
30252
30254 #define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
30255
30259 #define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
30260 #define OCOTP_SRK6_BITS_SHIFT (0U)
30261
30263 #define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
30264
30268 #define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
30269 #define OCOTP_SRK7_BITS_SHIFT (0U)
30270
30272 #define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
30273
30277 #define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
30278 #define OCOTP_SJC_RESP0_BITS_SHIFT (0U)
30279
30281 #define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
30282
30286 #define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
30287 #define OCOTP_SJC_RESP1_BITS_SHIFT (0U)
30288
30290 #define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
30291
30295 #define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)
30296 #define OCOTP_MAC0_BITS_SHIFT (0U)
30297
30299 #define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
30300
30304 #define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)
30305 #define OCOTP_MAC1_BITS_SHIFT (0U)
30306
30308 #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
30309
30313 #define OCOTP_MAC2_BITS_MASK (0xFFFFFFFFU)
30314 #define OCOTP_MAC2_BITS_SHIFT (0U)
30315
30317 #define OCOTP_MAC2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC2_BITS_SHIFT)) & OCOTP_MAC2_BITS_MASK)
30318
30322 #define OCOTP_OTPMK_CRC32_BITS_MASK (0xFFFFFFFFU)
30323 #define OCOTP_OTPMK_CRC32_BITS_SHIFT (0U)
30324
30326 #define OCOTP_OTPMK_CRC32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK_CRC32_BITS_SHIFT)) & OCOTP_OTPMK_CRC32_BITS_MASK)
30327
30331 #define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)
30332 #define OCOTP_GP1_BITS_SHIFT (0U)
30333
30335 #define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
30336
30340 #define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)
30341 #define OCOTP_GP2_BITS_SHIFT (0U)
30342
30344 #define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
30345
30349 #define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)
30350 #define OCOTP_SW_GP1_BITS_SHIFT (0U)
30351
30353 #define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
30354
30358 #define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)
30359 #define OCOTP_SW_GP20_BITS_SHIFT (0U)
30360
30362 #define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
30363
30367 #define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)
30368 #define OCOTP_SW_GP21_BITS_SHIFT (0U)
30369
30371 #define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
30372
30376 #define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)
30377 #define OCOTP_SW_GP22_BITS_SHIFT (0U)
30378
30380 #define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
30381
30385 #define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)
30386 #define OCOTP_SW_GP23_BITS_SHIFT (0U)
30387
30389 #define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
30390
30394 #define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)
30395 #define OCOTP_MISC_CONF0_BITS_SHIFT (0U)
30396
30398 #define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
30399
30403 #define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)
30404 #define OCOTP_MISC_CONF1_BITS_SHIFT (0U)
30405
30407 #define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
30408
30412 #define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
30413 #define OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
30414
30416 #define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)
30417
30421 #define OCOTP_ROM_PATCH0_BITS_MASK (0xFFFFFFFFU)
30422 #define OCOTP_ROM_PATCH0_BITS_SHIFT (0U)
30423
30425 #define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH0_BITS_SHIFT)) & OCOTP_ROM_PATCH0_BITS_MASK)
30426
30430 #define OCOTP_ROM_PATCH1_BITS_MASK (0xFFFFFFFFU)
30431 #define OCOTP_ROM_PATCH1_BITS_SHIFT (0U)
30432
30434 #define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH1_BITS_SHIFT)) & OCOTP_ROM_PATCH1_BITS_MASK)
30435
30439 #define OCOTP_ROM_PATCH2_BITS_MASK (0xFFFFFFFFU)
30440 #define OCOTP_ROM_PATCH2_BITS_SHIFT (0U)
30441
30443 #define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH2_BITS_SHIFT)) & OCOTP_ROM_PATCH2_BITS_MASK)
30444
30448 #define OCOTP_ROM_PATCH3_BITS_MASK (0xFFFFFFFFU)
30449 #define OCOTP_ROM_PATCH3_BITS_SHIFT (0U)
30450
30452 #define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH3_BITS_SHIFT)) & OCOTP_ROM_PATCH3_BITS_MASK)
30453
30457 #define OCOTP_ROM_PATCH4_BITS_MASK (0xFFFFFFFFU)
30458 #define OCOTP_ROM_PATCH4_BITS_SHIFT (0U)
30459
30461 #define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH4_BITS_SHIFT)) & OCOTP_ROM_PATCH4_BITS_MASK)
30462
30466 #define OCOTP_ROM_PATCH5_BITS_MASK (0xFFFFFFFFU)
30467 #define OCOTP_ROM_PATCH5_BITS_SHIFT (0U)
30468
30470 #define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH5_BITS_SHIFT)) & OCOTP_ROM_PATCH5_BITS_MASK)
30471
30475 #define OCOTP_ROM_PATCH6_BITS_MASK (0xFFFFFFFFU)
30476 #define OCOTP_ROM_PATCH6_BITS_SHIFT (0U)
30477
30479 #define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH6_BITS_SHIFT)) & OCOTP_ROM_PATCH6_BITS_MASK)
30480
30484 #define OCOTP_ROM_PATCH7_BITS_MASK (0xFFFFFFFFU)
30485 #define OCOTP_ROM_PATCH7_BITS_SHIFT (0U)
30486
30488 #define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH7_BITS_SHIFT)) & OCOTP_ROM_PATCH7_BITS_MASK)
30489
30493 #define OCOTP_GP30_BITS_MASK (0xFFFFFFFFU)
30494 #define OCOTP_GP30_BITS_SHIFT (0U)
30495
30497 #define OCOTP_GP30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP30_BITS_SHIFT)) & OCOTP_GP30_BITS_MASK)
30498
30502 #define OCOTP_GP31_BITS_MASK (0xFFFFFFFFU)
30503 #define OCOTP_GP31_BITS_SHIFT (0U)
30504
30506 #define OCOTP_GP31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP31_BITS_SHIFT)) & OCOTP_GP31_BITS_MASK)
30507
30511 #define OCOTP_GP32_BITS_MASK (0xFFFFFFFFU)
30512 #define OCOTP_GP32_BITS_SHIFT (0U)
30513
30515 #define OCOTP_GP32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP32_BITS_SHIFT)) & OCOTP_GP32_BITS_MASK)
30516
30520 #define OCOTP_GP33_BITS_MASK (0xFFFFFFFFU)
30521 #define OCOTP_GP33_BITS_SHIFT (0U)
30522
30524 #define OCOTP_GP33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP33_BITS_SHIFT)) & OCOTP_GP33_BITS_MASK)
30525
30529 #define OCOTP_GP40_BITS_MASK (0xFFFFFFFFU)
30530 #define OCOTP_GP40_BITS_SHIFT (0U)
30531
30533 #define OCOTP_GP40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP40_BITS_SHIFT)) & OCOTP_GP40_BITS_MASK)
30534
30538 #define OCOTP_GP41_BITS_MASK (0xFFFFFFFFU)
30539 #define OCOTP_GP41_BITS_SHIFT (0U)
30540
30542 #define OCOTP_GP41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP41_BITS_SHIFT)) & OCOTP_GP41_BITS_MASK)
30543
30547 #define OCOTP_GP42_BITS_MASK (0xFFFFFFFFU)
30548 #define OCOTP_GP42_BITS_SHIFT (0U)
30549
30551 #define OCOTP_GP42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP42_BITS_SHIFT)) & OCOTP_GP42_BITS_MASK)
30552
30556 #define OCOTP_GP43_BITS_MASK (0xFFFFFFFFU)
30557 #define OCOTP_GP43_BITS_SHIFT (0U)
30558
30560 #define OCOTP_GP43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP43_BITS_SHIFT)) & OCOTP_GP43_BITS_MASK)
30561 /* end of group OCOTP_Register_Masks */
30567
30568
30569 /* OCOTP - Peripheral instance base addresses */
30571 #define OCOTP_BASE (0x401F4000u)
30572
30573 #define OCOTP ((OCOTP_Type *)OCOTP_BASE)
30574
30575 #define OCOTP_BASE_ADDRS { OCOTP_BASE }
30576
30577 #define OCOTP_BASE_PTRS { OCOTP }
30578 /* end of group OCOTP_Peripheral_Access_Layer */
30582
30583
30584 /* ----------------------------------------------------------------------------
30585 -- PGC Peripheral Access Layer
30586 ---------------------------------------------------------------------------- */
30587
30594 typedef struct {
30595 uint8_t RESERVED_0[544];
30596 __IO uint32_t MEGA_CTRL;
30597 __IO uint32_t MEGA_PUPSCR;
30598 __IO uint32_t MEGA_PDNSCR;
30599 __IO uint32_t MEGA_SR;
30600 uint8_t RESERVED_1[112];
30601 __IO uint32_t CPU_CTRL;
30602 __IO uint32_t CPU_PUPSCR;
30603 __IO uint32_t CPU_PDNSCR;
30604 __IO uint32_t CPU_SR;
30605 } PGC_Type;
30606
30607 /* ----------------------------------------------------------------------------
30608 -- PGC Register Masks
30609 ---------------------------------------------------------------------------- */
30610
30618 #define PGC_MEGA_CTRL_PCR_MASK (0x1U)
30619 #define PGC_MEGA_CTRL_PCR_SHIFT (0U)
30620
30624 #define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
30625
30629 #define PGC_MEGA_PUPSCR_SW_MASK (0x3FU)
30630 #define PGC_MEGA_PUPSCR_SW_SHIFT (0U)
30631 #define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
30632 #define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)
30633 #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)
30634 #define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
30635
30639 #define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)
30640 #define PGC_MEGA_PDNSCR_ISO_SHIFT (0U)
30641 #define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
30642 #define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)
30643 #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)
30644 #define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
30645
30649 #define PGC_MEGA_SR_PSR_MASK (0x1U)
30650 #define PGC_MEGA_SR_PSR_SHIFT (0U)
30651
30655 #define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
30656
30660 #define PGC_CPU_CTRL_PCR_MASK (0x1U)
30661 #define PGC_CPU_CTRL_PCR_SHIFT (0U)
30662
30666 #define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
30667
30671 #define PGC_CPU_PUPSCR_SW_MASK (0x3FU)
30672 #define PGC_CPU_PUPSCR_SW_SHIFT (0U)
30673 #define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
30674 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)
30675 #define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)
30676 #define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
30677
30681 #define PGC_CPU_PDNSCR_ISO_MASK (0x3FU)
30682 #define PGC_CPU_PDNSCR_ISO_SHIFT (0U)
30683 #define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
30684 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)
30685 #define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)
30686 #define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
30687
30691 #define PGC_CPU_SR_PSR_MASK (0x1U)
30692 #define PGC_CPU_SR_PSR_SHIFT (0U)
30693
30697 #define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)
30698 /* end of group PGC_Register_Masks */
30704
30705
30706 /* PGC - Peripheral instance base addresses */
30708 #define PGC_BASE (0x400F4000u)
30709
30710 #define PGC ((PGC_Type *)PGC_BASE)
30711
30712 #define PGC_BASE_ADDRS { PGC_BASE }
30713
30714 #define PGC_BASE_PTRS { PGC }
30715 /* end of group PGC_Peripheral_Access_Layer */
30719
30720
30721 /* ----------------------------------------------------------------------------
30722 -- PIT Peripheral Access Layer
30723 ---------------------------------------------------------------------------- */
30724
30731 typedef struct {
30732 __IO uint32_t MCR;
30733 uint8_t RESERVED_0[220];
30734 __I uint32_t LTMR64H;
30735 __I uint32_t LTMR64L;
30736 uint8_t RESERVED_1[24];
30737 struct { /* offset: 0x100, array step: 0x10 */
30738 __IO uint32_t LDVAL;
30739 __I uint32_t CVAL;
30740 __IO uint32_t TCTRL;
30741 __IO uint32_t TFLG;
30742 } CHANNEL[4];
30743 } PIT_Type;
30744
30745 /* ----------------------------------------------------------------------------
30746 -- PIT Register Masks
30747 ---------------------------------------------------------------------------- */
30748
30756 #define PIT_MCR_FRZ_MASK (0x1U)
30757 #define PIT_MCR_FRZ_SHIFT (0U)
30758
30762 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
30763 #define PIT_MCR_MDIS_MASK (0x2U)
30764 #define PIT_MCR_MDIS_SHIFT (1U)
30765
30769 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
30770
30774 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
30775 #define PIT_LTMR64H_LTH_SHIFT (0U)
30776
30778 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
30779
30783 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
30784 #define PIT_LTMR64L_LTL_SHIFT (0U)
30785
30787 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
30788
30792 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
30793 #define PIT_LDVAL_TSV_SHIFT (0U)
30794
30796 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
30797
30799 /* The count of PIT_LDVAL */
30800 #define PIT_LDVAL_COUNT (4U)
30801
30804 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
30805 #define PIT_CVAL_TVL_SHIFT (0U)
30806
30808 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
30809
30811 /* The count of PIT_CVAL */
30812 #define PIT_CVAL_COUNT (4U)
30813
30816 #define PIT_TCTRL_TEN_MASK (0x1U)
30817 #define PIT_TCTRL_TEN_SHIFT (0U)
30818
30822 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
30823 #define PIT_TCTRL_TIE_MASK (0x2U)
30824 #define PIT_TCTRL_TIE_SHIFT (1U)
30825
30829 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
30830 #define PIT_TCTRL_CHN_MASK (0x4U)
30831 #define PIT_TCTRL_CHN_SHIFT (2U)
30832
30836 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
30837
30839 /* The count of PIT_TCTRL */
30840 #define PIT_TCTRL_COUNT (4U)
30841
30844 #define PIT_TFLG_TIF_MASK (0x1U)
30845 #define PIT_TFLG_TIF_SHIFT (0U)
30846
30850 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
30851
30853 /* The count of PIT_TFLG */
30854 #define PIT_TFLG_COUNT (4U)
30855
30856 /* end of group PIT_Register_Masks */
30860
30861
30862 /* PIT - Peripheral instance base addresses */
30864 #define PIT_BASE (0x40084000u)
30865
30866 #define PIT ((PIT_Type *)PIT_BASE)
30867
30868 #define PIT_BASE_ADDRS { PIT_BASE }
30869
30870 #define PIT_BASE_PTRS { PIT }
30871
30872 #define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
30873 /* end of group PIT_Peripheral_Access_Layer */
30877
30878
30879 /* ----------------------------------------------------------------------------
30880 -- PMU Peripheral Access Layer
30881 ---------------------------------------------------------------------------- */
30882
30889 typedef struct {
30890 uint8_t RESERVED_0[272];
30891 __IO uint32_t REG_1P1;
30892 __IO uint32_t REG_1P1_SET;
30893 __IO uint32_t REG_1P1_CLR;
30894 __IO uint32_t REG_1P1_TOG;
30895 __IO uint32_t REG_3P0;
30896 __IO uint32_t REG_3P0_SET;
30897 __IO uint32_t REG_3P0_CLR;
30898 __IO uint32_t REG_3P0_TOG;
30899 __IO uint32_t REG_2P5;
30900 __IO uint32_t REG_2P5_SET;
30901 __IO uint32_t REG_2P5_CLR;
30902 __IO uint32_t REG_2P5_TOG;
30903 __IO uint32_t REG_CORE;
30904 __IO uint32_t REG_CORE_SET;
30905 __IO uint32_t REG_CORE_CLR;
30906 __IO uint32_t REG_CORE_TOG;
30907 __IO uint32_t MISC0;
30908 __IO uint32_t MISC0_SET;
30909 __IO uint32_t MISC0_CLR;
30910 __IO uint32_t MISC0_TOG;
30911 __IO uint32_t MISC1;
30912 __IO uint32_t MISC1_SET;
30913 __IO uint32_t MISC1_CLR;
30914 __IO uint32_t MISC1_TOG;
30915 __IO uint32_t MISC2;
30916 __IO uint32_t MISC2_SET;
30917 __IO uint32_t MISC2_CLR;
30918 __IO uint32_t MISC2_TOG;
30919 } PMU_Type;
30920
30921 /* ----------------------------------------------------------------------------
30922 -- PMU Register Masks
30923 ---------------------------------------------------------------------------- */
30924
30932 #define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
30933 #define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
30934 #define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
30935 #define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
30936 #define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
30937 #define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
30938 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
30939 #define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
30940 #define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
30941 #define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
30942 #define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
30943 #define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
30944 #define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
30945 #define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
30946 #define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
30947 #define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
30948 #define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
30949
30954 #define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
30955 #define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
30956 #define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
30957 #define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
30958 #define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
30959 #define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
30960 #define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
30961 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
30962 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
30963 #define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
30964 #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
30965 #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
30966
30970 #define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
30971
30975 #define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
30976 #define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
30977 #define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
30978 #define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
30979 #define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
30980 #define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
30981 #define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
30982 #define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
30983 #define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
30984 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
30985 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
30986 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
30987 #define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
30988 #define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
30989 #define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
30990 #define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
30991 #define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
30992
30997 #define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
30998 #define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
30999 #define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
31000 #define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
31001 #define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
31002 #define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
31003 #define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
31004 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
31005 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
31006 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
31007 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
31008 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
31009
31013 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
31014
31018 #define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
31019 #define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
31020 #define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
31021 #define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
31022 #define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
31023 #define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
31024 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
31025 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
31026 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
31027 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
31028 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
31029 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
31030 #define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
31031 #define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
31032 #define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
31033 #define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
31034 #define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
31035
31040 #define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
31041 #define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
31042 #define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
31043 #define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
31044 #define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
31045 #define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
31046 #define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
31047 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
31048 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
31049 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
31050 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
31051 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
31052
31056 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
31057
31061 #define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
31062 #define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
31063 #define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
31064 #define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
31065 #define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
31066 #define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
31067 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
31068 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
31069 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
31070 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
31071 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
31072 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
31073 #define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
31074 #define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
31075 #define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
31076 #define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
31077 #define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
31078
31083 #define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
31084 #define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
31085 #define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
31086 #define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
31087 #define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
31088 #define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
31089 #define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
31090 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
31091 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
31092 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
31093 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
31094 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
31095
31099 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
31100
31104 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
31105 #define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
31106 #define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
31107 #define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
31108 #define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
31109 #define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
31110 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
31111 #define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
31112 #define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
31113 #define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
31114 #define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
31115 #define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
31116 #define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
31117 #define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
31118
31122 #define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
31123 #define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
31124 #define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
31125
31130 #define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
31131 #define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
31132 #define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
31133 #define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
31134 #define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
31135 #define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
31136 #define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
31137
31141 #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
31142 #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
31143 #define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
31144 #define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
31145 #define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
31146 #define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
31147 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
31148 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
31149 #define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
31150 #define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
31151 #define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
31152 #define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
31153 #define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
31154 #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
31155
31159 #define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
31160 #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
31161 #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
31162
31167 #define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
31168 #define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
31169 #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
31170 #define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
31171 #define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
31172 #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
31173 #define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
31174
31178 #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
31179 #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
31180 #define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
31181 #define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
31182 #define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
31183 #define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
31184 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
31185 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
31186 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
31187 #define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
31188 #define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
31189 #define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
31190 #define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
31191 #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
31192
31196 #define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
31197 #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
31198 #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
31199
31204 #define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
31205 #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
31206 #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
31207 #define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
31208 #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
31209 #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
31210 #define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
31211
31215 #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
31216 #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
31217 #define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
31218 #define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
31219 #define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
31220 #define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
31221 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
31222 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
31223 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
31224 #define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
31225 #define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
31226 #define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
31227 #define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
31228 #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
31229
31233 #define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
31234 #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
31235 #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
31236
31241 #define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
31242 #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
31243 #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
31244 #define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
31245 #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
31246 #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
31247 #define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
31248
31252 #define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
31253 #define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
31254 #define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
31255 #define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
31256 #define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
31257 #define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
31258 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
31259 #define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
31260 #define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
31261 #define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
31262 #define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
31263 #define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
31264 #define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
31265 #define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
31266 #define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
31267 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
31268 #define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
31269
31274 #define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
31275 #define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
31276 #define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
31277 #define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
31278 #define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
31279 #define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
31280 #define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
31281 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
31282 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
31283 #define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
31284
31288 #define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
31289 #define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
31290 #define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
31291 #define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
31292 #define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
31293 #define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
31294 #define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
31295 #define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
31296 #define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
31297 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
31298 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
31299 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
31300 #define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
31301 #define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
31302 #define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
31303 #define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
31304 #define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
31305
31310 #define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
31311 #define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
31312 #define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
31313 #define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
31314 #define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
31315 #define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
31316 #define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
31317 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
31318 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
31319 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
31320
31324 #define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
31325 #define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
31326 #define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
31327 #define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
31328 #define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
31329 #define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
31330 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
31331 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
31332 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
31333 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
31334 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
31335 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
31336 #define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
31337 #define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
31338 #define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
31339 #define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
31340 #define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
31341
31346 #define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
31347 #define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
31348 #define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
31349 #define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
31350 #define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
31351 #define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
31352 #define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
31353 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
31354 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
31355 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
31356
31360 #define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
31361 #define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
31362 #define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
31363 #define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
31364 #define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
31365 #define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
31366 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
31367 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
31368 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
31369 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
31370 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
31371 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
31372 #define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
31373 #define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
31374 #define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
31375 #define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
31376 #define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
31377
31382 #define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
31383 #define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
31384 #define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
31385 #define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
31386 #define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
31387 #define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
31388 #define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
31389 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
31390 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
31391 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
31392
31396 #define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
31397 #define PMU_REG_CORE_REG0_TARG_SHIFT (0U)
31398
31407 #define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
31408 #define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
31409 #define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
31410
31430 #define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
31431 #define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
31432 #define PMU_REG_CORE_REG1_TARG_SHIFT (9U)
31433
31444 #define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
31445 #define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
31446 #define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
31447
31467 #define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
31468 #define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
31469 #define PMU_REG_CORE_REG2_TARG_SHIFT (18U)
31470
31479 #define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
31480 #define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
31481 #define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
31482
31502 #define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
31503 #define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
31504 #define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
31505
31511 #define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
31512 #define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
31513 #define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
31514 #define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
31515
31519 #define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
31520 #define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
31521
31530 #define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
31531 #define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
31532 #define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
31533
31553 #define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
31554 #define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
31555 #define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
31556
31567 #define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
31568 #define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
31569 #define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
31570
31590 #define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
31591 #define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
31592 #define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
31593
31602 #define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
31603 #define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
31604 #define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
31605
31625 #define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
31626 #define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
31627 #define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
31628
31634 #define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
31635 #define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
31636 #define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
31637 #define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
31638
31642 #define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
31643 #define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
31644
31653 #define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
31654 #define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
31655 #define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
31656
31676 #define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
31677 #define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
31678 #define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
31679
31690 #define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
31691 #define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
31692 #define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
31693
31713 #define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
31714 #define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
31715 #define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
31716
31725 #define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
31726 #define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
31727 #define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
31728
31748 #define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
31749 #define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
31750 #define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
31751
31757 #define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
31758 #define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
31759 #define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
31760 #define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
31761
31765 #define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
31766 #define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
31767
31776 #define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
31777 #define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
31778 #define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
31779
31799 #define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
31800 #define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
31801 #define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
31802
31813 #define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
31814 #define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
31815 #define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
31816
31836 #define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
31837 #define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
31838 #define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
31839
31848 #define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
31849 #define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
31850 #define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
31851
31871 #define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
31872 #define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
31873 #define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
31874
31880 #define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
31881 #define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
31882 #define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
31883 #define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
31884
31888 #define PMU_MISC0_REFTOP_PWD_MASK (0x1U)
31889 #define PMU_MISC0_REFTOP_PWD_SHIFT (0U)
31890 #define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
31891 #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
31892 #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
31893
31897 #define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
31898 #define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
31899 #define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
31900
31910 #define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
31911 #define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
31912 #define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
31913 #define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
31914 #define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
31915 #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
31916
31922 #define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
31923 #define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
31924 #define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
31925
31929 #define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
31930 #define PMU_MISC0_OSC_I_MASK (0x6000U)
31931 #define PMU_MISC0_OSC_I_SHIFT (13U)
31932
31938 #define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
31939 #define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
31940 #define PMU_MISC0_OSC_XTALOK_SHIFT (15U)
31941 #define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
31942 #define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
31943 #define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
31944 #define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
31945 #define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
31946 #define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
31947
31951 #define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
31952 #define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
31953 #define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
31954
31964 #define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
31965 #define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
31966 #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
31967
31971 #define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
31972 #define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
31973 #define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
31974 #define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
31975 #define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
31976 #define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)
31977
31981 #define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
31982
31986 #define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
31987 #define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
31988 #define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
31989 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
31990 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
31991
31995 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
31996 #define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
31997 #define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
31998
32008 #define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
32009 #define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
32010 #define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
32011 #define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
32012 #define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
32013 #define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
32014
32020 #define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
32021 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
32022 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
32023
32027 #define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
32028 #define PMU_MISC0_SET_OSC_I_MASK (0x6000U)
32029 #define PMU_MISC0_SET_OSC_I_SHIFT (13U)
32030
32036 #define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
32037 #define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
32038 #define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
32039 #define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
32040 #define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
32041 #define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
32042 #define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
32043 #define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
32044 #define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
32045
32049 #define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
32050 #define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
32051 #define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
32052
32062 #define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
32063 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
32064 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
32065
32069 #define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
32070 #define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
32071 #define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
32072 #define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
32073 #define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
32074 #define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
32075
32079 #define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
32080
32084 #define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
32085 #define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
32086 #define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
32087 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
32088 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
32089
32093 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
32094 #define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
32095 #define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
32096
32106 #define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
32107 #define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
32108 #define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
32109 #define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
32110 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
32111 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
32112
32118 #define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
32119 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
32120 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
32121
32125 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
32126 #define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
32127 #define PMU_MISC0_CLR_OSC_I_SHIFT (13U)
32128
32134 #define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
32135 #define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
32136 #define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
32137 #define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
32138 #define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
32139 #define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
32140 #define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
32141 #define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
32142 #define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
32143
32147 #define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
32148 #define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
32149 #define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
32150
32160 #define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
32161 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
32162 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
32163
32167 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
32168 #define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
32169 #define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
32170 #define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
32171 #define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
32172 #define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
32173
32177 #define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
32178
32182 #define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
32183 #define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
32184 #define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
32185 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
32186 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
32187
32191 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
32192 #define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
32193 #define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
32194
32204 #define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
32205 #define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
32206 #define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
32207 #define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
32208 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
32209 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
32210
32216 #define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
32217 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
32218 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
32219
32223 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
32224 #define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
32225 #define PMU_MISC0_TOG_OSC_I_SHIFT (13U)
32226
32232 #define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
32233 #define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
32234 #define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
32235 #define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
32236 #define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
32237 #define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
32238 #define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
32239 #define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
32240 #define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
32241
32245 #define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
32246 #define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
32247 #define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
32248
32258 #define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
32259 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
32260 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
32261
32265 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
32266 #define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
32267 #define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
32268 #define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
32269 #define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
32270 #define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
32271
32275 #define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
32276
32280 #define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
32281 #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
32282
32300 #define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
32301 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)
32302 #define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)
32303
32326 #define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
32327 #define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
32328 #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
32329 #define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
32330 #define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)
32331 #define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)
32332 #define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
32333 #define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
32334 #define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
32335 #define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
32336 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)
32337 #define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)
32338 #define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
32339 #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
32340 #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
32341 #define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
32342 #define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
32343 #define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
32344 #define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
32345 #define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
32346 #define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
32347 #define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
32348 #define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
32349 #define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
32350 #define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
32351 #define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
32352 #define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
32353 #define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
32354 #define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
32355 #define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
32356 #define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
32357 #define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
32358 #define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
32359 #define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
32360
32364 #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
32365 #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
32366
32384 #define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
32385 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)
32386 #define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)
32387
32410 #define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
32411 #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
32412 #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
32413 #define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
32414 #define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)
32415 #define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)
32416 #define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
32417 #define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
32418 #define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
32419 #define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
32420 #define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)
32421 #define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)
32422 #define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
32423 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
32424 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
32425 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
32426 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
32427 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
32428 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
32429 #define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
32430 #define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
32431 #define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
32432 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
32433 #define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
32434 #define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
32435 #define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
32436 #define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
32437 #define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
32438 #define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
32439 #define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
32440 #define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
32441 #define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
32442 #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
32443 #define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
32444
32448 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
32449 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
32450
32468 #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
32469 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)
32470 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)
32471
32494 #define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
32495 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
32496 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
32497 #define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
32498 #define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)
32499 #define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)
32500 #define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
32501 #define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
32502 #define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
32503 #define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
32504 #define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)
32505 #define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)
32506 #define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
32507 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
32508 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
32509 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
32510 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
32511 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
32512 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
32513 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
32514 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
32515 #define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
32516 #define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
32517 #define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
32518 #define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
32519 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
32520 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
32521 #define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
32522 #define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
32523 #define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
32524 #define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
32525 #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
32526 #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
32527 #define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
32528
32532 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
32533 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
32534
32552 #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
32553 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)
32554 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)
32555
32578 #define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
32579 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
32580 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
32581 #define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
32582 #define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)
32583 #define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)
32584 #define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
32585 #define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
32586 #define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
32587 #define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
32588 #define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)
32589 #define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)
32590 #define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
32591 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
32592 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
32593 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
32594 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
32595 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
32596 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
32597 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
32598 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
32599 #define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
32600 #define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
32601 #define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
32602 #define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
32603 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
32604 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
32605 #define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
32606 #define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
32607 #define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
32608 #define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
32609 #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
32610 #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
32611 #define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
32612
32616 #define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
32617 #define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
32618
32622 #define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
32623 #define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
32624 #define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
32625
32628 #define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
32629 #define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
32630 #define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
32631 #define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
32632 #define PMU_MISC2_PLL3_disable_MASK (0x80U)
32633 #define PMU_MISC2_PLL3_disable_SHIFT (7U)
32634 #define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
32635 #define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
32636 #define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
32637
32641 #define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
32642 #define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
32643 #define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
32644
32647 #define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
32648 #define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
32649 #define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
32650 #define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
32651 #define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
32652 #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
32653
32657 #define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
32658 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
32659 #define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
32660
32664 #define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
32665 #define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
32666 #define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
32667 #define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
32668 #define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
32669 #define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
32670 #define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
32671 #define PMU_MISC2_REG2_OK_MASK (0x400000U)
32672 #define PMU_MISC2_REG2_OK_SHIFT (22U)
32673 #define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
32674 #define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
32675 #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
32676
32680 #define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
32681 #define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
32682 #define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
32683
32689 #define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
32690 #define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
32691 #define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
32692
32698 #define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
32699 #define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
32700 #define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
32701
32707 #define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
32708 #define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)
32709 #define PMU_MISC2_VIDEO_DIV_SHIFT (30U)
32710
32716 #define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
32717
32721 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
32722 #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
32723
32727 #define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
32728 #define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
32729 #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
32730
32733 #define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
32734 #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
32735 #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
32736 #define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
32737 #define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
32738 #define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
32739 #define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
32740 #define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
32741 #define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
32742
32746 #define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
32747 #define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
32748 #define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
32749
32752 #define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
32753 #define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
32754 #define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
32755 #define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
32756 #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
32757 #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
32758
32762 #define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
32763 #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
32764 #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
32765
32769 #define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
32770 #define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
32771 #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
32772 #define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
32773 #define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
32774 #define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
32775 #define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
32776 #define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
32777 #define PMU_MISC2_SET_REG2_OK_SHIFT (22U)
32778 #define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
32779 #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
32780 #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
32781
32785 #define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
32786 #define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
32787 #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
32788
32794 #define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
32795 #define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
32796 #define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
32797
32803 #define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
32804 #define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
32805 #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
32806
32812 #define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
32813 #define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
32814 #define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)
32815
32821 #define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
32822
32826 #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
32827 #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
32828
32832 #define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
32833 #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
32834 #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
32835
32838 #define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
32839 #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
32840 #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
32841 #define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
32842 #define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
32843 #define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
32844 #define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
32845 #define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
32846 #define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
32847
32851 #define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
32852 #define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
32853 #define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
32854
32857 #define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
32858 #define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
32859 #define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
32860 #define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
32861 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
32862 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
32863
32867 #define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
32868 #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
32869 #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
32870
32874 #define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
32875 #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
32876 #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
32877 #define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
32878 #define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
32879 #define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
32880 #define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
32881 #define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
32882 #define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
32883 #define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
32884 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
32885 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
32886
32890 #define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
32891 #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
32892 #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
32893
32899 #define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
32900 #define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
32901 #define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
32902
32908 #define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
32909 #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
32910 #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
32911
32917 #define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
32918 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
32919 #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
32920
32926 #define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
32927
32931 #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
32932 #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
32933
32937 #define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
32938 #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
32939 #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
32940
32943 #define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
32944 #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
32945 #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
32946 #define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
32947 #define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
32948 #define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
32949 #define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
32950 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
32951 #define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
32952
32956 #define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
32957 #define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
32958 #define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
32959
32962 #define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
32963 #define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
32964 #define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
32965 #define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
32966 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
32967 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
32968
32972 #define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
32973 #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
32974 #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
32975
32979 #define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
32980 #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
32981 #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
32982 #define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
32983 #define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
32984 #define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
32985 #define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
32986 #define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
32987 #define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
32988 #define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
32989 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
32990 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
32991
32995 #define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
32996 #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
32997 #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
32998
33004 #define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
33005 #define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
33006 #define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
33007
33013 #define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
33014 #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
33015 #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
33016
33022 #define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
33023 #define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
33024 #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
33025
33031 #define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)
33032 /* end of group PMU_Register_Masks */
33038
33039
33040 /* PMU - Peripheral instance base addresses */
33042 #define PMU_BASE (0x400D8000u)
33043
33044 #define PMU ((PMU_Type *)PMU_BASE)
33045
33046 #define PMU_BASE_ADDRS { PMU_BASE }
33047
33048 #define PMU_BASE_PTRS { PMU }
33049 /* end of group PMU_Peripheral_Access_Layer */
33053
33054
33055 /* ----------------------------------------------------------------------------
33056 -- PWM Peripheral Access Layer
33057 ---------------------------------------------------------------------------- */
33058
33065 typedef struct {
33066 struct { /* offset: 0x0, array step: 0x60 */
33067 __I uint16_t CNT;
33068 __IO uint16_t INIT;
33069 __IO uint16_t CTRL2;
33070 __IO uint16_t CTRL;
33071 uint8_t RESERVED_0[2];
33072 __IO uint16_t VAL0;
33073 __IO uint16_t FRACVAL1;
33074 __IO uint16_t VAL1;
33075 __IO uint16_t FRACVAL2;
33076 __IO uint16_t VAL2;
33077 __IO uint16_t FRACVAL3;
33078 __IO uint16_t VAL3;
33079 __IO uint16_t FRACVAL4;
33080 __IO uint16_t VAL4;
33081 __IO uint16_t FRACVAL5;
33082 __IO uint16_t VAL5;
33083 __IO uint16_t FRCTRL;
33084 __IO uint16_t OCTRL;
33085 __IO uint16_t STS;
33086 __IO uint16_t INTEN;
33087 __IO uint16_t DMAEN;
33088 __IO uint16_t TCTRL;
33089 __IO uint16_t DISMAP[2];
33090 __IO uint16_t DTCNT0;
33091 __IO uint16_t DTCNT1;
33092 __IO uint16_t CAPTCTRLA;
33093 __IO uint16_t CAPTCOMPA;
33094 __IO uint16_t CAPTCTRLB;
33095 __IO uint16_t CAPTCOMPB;
33096 __IO uint16_t CAPTCTRLX;
33097 __IO uint16_t CAPTCOMPX;
33098 __I uint16_t CVAL0;
33099 __I uint16_t CVAL0CYC;
33100 __I uint16_t CVAL1;
33101 __I uint16_t CVAL1CYC;
33102 __I uint16_t CVAL2;
33103 __I uint16_t CVAL2CYC;
33104 __I uint16_t CVAL3;
33105 __I uint16_t CVAL3CYC;
33106 __I uint16_t CVAL4;
33107 __I uint16_t CVAL4CYC;
33108 __I uint16_t CVAL5;
33109 __I uint16_t CVAL5CYC;
33110 uint8_t RESERVED_1[8];
33111 } SM[4];
33112 __IO uint16_t OUTEN;
33113 __IO uint16_t MASK;
33114 __IO uint16_t SWCOUT;
33115 __IO uint16_t DTSRCSEL;
33116 __IO uint16_t MCTRL;
33117 __IO uint16_t MCTRL2;
33118 __IO uint16_t FCTRL;
33119 __IO uint16_t FSTS;
33120 __IO uint16_t FFILT;
33121 __IO uint16_t FTST;
33122 __IO uint16_t FCTRL2;
33123 } PWM_Type;
33124
33125 /* ----------------------------------------------------------------------------
33126 -- PWM Register Masks
33127 ---------------------------------------------------------------------------- */
33128
33136 #define PWM_CNT_CNT_MASK (0xFFFFU)
33137 #define PWM_CNT_CNT_SHIFT (0U)
33138
33140 #define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
33141
33143 /* The count of PWM_CNT */
33144 #define PWM_CNT_COUNT (4U)
33145
33148 #define PWM_INIT_INIT_MASK (0xFFFFU)
33149 #define PWM_INIT_INIT_SHIFT (0U)
33150
33152 #define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
33153
33155 /* The count of PWM_INIT */
33156 #define PWM_INIT_COUNT (4U)
33157
33160 #define PWM_CTRL2_CLK_SEL_MASK (0x3U)
33161 #define PWM_CTRL2_CLK_SEL_SHIFT (0U)
33162
33169 #define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
33170 #define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
33171 #define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
33172
33177 #define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
33178 #define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
33179 #define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
33180
33193 #define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
33194 #define PWM_CTRL2_FORCE_MASK (0x40U)
33195 #define PWM_CTRL2_FORCE_SHIFT (6U)
33196
33198 #define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
33199 #define PWM_CTRL2_FRCEN_MASK (0x80U)
33200 #define PWM_CTRL2_FRCEN_SHIFT (7U)
33201
33205 #define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
33206 #define PWM_CTRL2_INIT_SEL_MASK (0x300U)
33207 #define PWM_CTRL2_INIT_SEL_SHIFT (8U)
33208
33217 #define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
33218 #define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
33219 #define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
33220
33222 #define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
33223 #define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
33224 #define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
33225
33227 #define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
33228 #define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
33229 #define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
33230
33232 #define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
33233 #define PWM_CTRL2_INDEP_MASK (0x2000U)
33234 #define PWM_CTRL2_INDEP_SHIFT (13U)
33235
33239 #define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
33240 #define PWM_CTRL2_WAITEN_MASK (0x4000U)
33241 #define PWM_CTRL2_WAITEN_SHIFT (14U)
33242
33244 #define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
33245 #define PWM_CTRL2_DBGEN_MASK (0x8000U)
33246 #define PWM_CTRL2_DBGEN_SHIFT (15U)
33247
33249 #define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
33250
33252 /* The count of PWM_CTRL2 */
33253 #define PWM_CTRL2_COUNT (4U)
33254
33257 #define PWM_CTRL_DBLEN_MASK (0x1U)
33258 #define PWM_CTRL_DBLEN_SHIFT (0U)
33259
33263 #define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
33264 #define PWM_CTRL_DBLX_MASK (0x2U)
33265 #define PWM_CTRL_DBLX_SHIFT (1U)
33266
33270 #define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
33271 #define PWM_CTRL_LDMOD_MASK (0x4U)
33272 #define PWM_CTRL_LDMOD_SHIFT (2U)
33273
33278 #define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
33279 #define PWM_CTRL_SPLIT_MASK (0x8U)
33280 #define PWM_CTRL_SPLIT_SHIFT (3U)
33281
33285 #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
33286 #define PWM_CTRL_PRSC_MASK (0x70U)
33287 #define PWM_CTRL_PRSC_SHIFT (4U)
33288
33298 #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
33299 #define PWM_CTRL_COMPMODE_MASK (0x80U)
33300 #define PWM_CTRL_COMPMODE_SHIFT (7U)
33301
33311 #define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
33312 #define PWM_CTRL_DT_MASK (0x300U)
33313 #define PWM_CTRL_DT_SHIFT (8U)
33314
33316 #define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
33317 #define PWM_CTRL_FULL_MASK (0x400U)
33318 #define PWM_CTRL_FULL_SHIFT (10U)
33319
33323 #define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
33324 #define PWM_CTRL_HALF_MASK (0x800U)
33325 #define PWM_CTRL_HALF_SHIFT (11U)
33326
33330 #define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
33331 #define PWM_CTRL_LDFQ_MASK (0xF000U)
33332 #define PWM_CTRL_LDFQ_SHIFT (12U)
33333
33351 #define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
33352
33354 /* The count of PWM_CTRL */
33355 #define PWM_CTRL_COUNT (4U)
33356
33359 #define PWM_VAL0_VAL0_MASK (0xFFFFU)
33360 #define PWM_VAL0_VAL0_SHIFT (0U)
33361
33363 #define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
33364
33366 /* The count of PWM_VAL0 */
33367 #define PWM_VAL0_COUNT (4U)
33368
33371 #define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
33372 #define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
33373
33375 #define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
33376
33378 /* The count of PWM_FRACVAL1 */
33379 #define PWM_FRACVAL1_COUNT (4U)
33380
33383 #define PWM_VAL1_VAL1_MASK (0xFFFFU)
33384 #define PWM_VAL1_VAL1_SHIFT (0U)
33385
33387 #define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
33388
33390 /* The count of PWM_VAL1 */
33391 #define PWM_VAL1_COUNT (4U)
33392
33395 #define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
33396 #define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
33397
33399 #define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
33400
33402 /* The count of PWM_FRACVAL2 */
33403 #define PWM_FRACVAL2_COUNT (4U)
33404
33407 #define PWM_VAL2_VAL2_MASK (0xFFFFU)
33408 #define PWM_VAL2_VAL2_SHIFT (0U)
33409
33411 #define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
33412
33414 /* The count of PWM_VAL2 */
33415 #define PWM_VAL2_COUNT (4U)
33416
33419 #define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
33420 #define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
33421
33423 #define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
33424
33426 /* The count of PWM_FRACVAL3 */
33427 #define PWM_FRACVAL3_COUNT (4U)
33428
33431 #define PWM_VAL3_VAL3_MASK (0xFFFFU)
33432 #define PWM_VAL3_VAL3_SHIFT (0U)
33433
33435 #define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
33436
33438 /* The count of PWM_VAL3 */
33439 #define PWM_VAL3_COUNT (4U)
33440
33443 #define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
33444 #define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
33445
33447 #define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
33448
33450 /* The count of PWM_FRACVAL4 */
33451 #define PWM_FRACVAL4_COUNT (4U)
33452
33455 #define PWM_VAL4_VAL4_MASK (0xFFFFU)
33456 #define PWM_VAL4_VAL4_SHIFT (0U)
33457
33459 #define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
33460
33462 /* The count of PWM_VAL4 */
33463 #define PWM_VAL4_COUNT (4U)
33464
33467 #define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
33468 #define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
33469
33471 #define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
33472
33474 /* The count of PWM_FRACVAL5 */
33475 #define PWM_FRACVAL5_COUNT (4U)
33476
33479 #define PWM_VAL5_VAL5_MASK (0xFFFFU)
33480 #define PWM_VAL5_VAL5_SHIFT (0U)
33481
33483 #define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
33484
33486 /* The count of PWM_VAL5 */
33487 #define PWM_VAL5_COUNT (4U)
33488
33491 #define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
33492 #define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
33493
33497 #define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
33498 #define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
33499 #define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
33500
33504 #define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
33505 #define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
33506 #define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
33507
33511 #define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
33512 #define PWM_FRCTRL_FRAC_PU_MASK (0x100U)
33513 #define PWM_FRCTRL_FRAC_PU_SHIFT (8U)
33514
33518 #define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
33519 #define PWM_FRCTRL_TEST_MASK (0x8000U)
33520 #define PWM_FRCTRL_TEST_SHIFT (15U)
33521
33523 #define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
33524
33526 /* The count of PWM_FRCTRL */
33527 #define PWM_FRCTRL_COUNT (4U)
33528
33531 #define PWM_OCTRL_PWMXFS_MASK (0x3U)
33532 #define PWM_OCTRL_PWMXFS_SHIFT (0U)
33533
33539 #define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
33540 #define PWM_OCTRL_PWMBFS_MASK (0xCU)
33541 #define PWM_OCTRL_PWMBFS_SHIFT (2U)
33542
33548 #define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
33549 #define PWM_OCTRL_PWMAFS_MASK (0x30U)
33550 #define PWM_OCTRL_PWMAFS_SHIFT (4U)
33551
33557 #define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
33558 #define PWM_OCTRL_POLX_MASK (0x100U)
33559 #define PWM_OCTRL_POLX_SHIFT (8U)
33560
33564 #define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
33565 #define PWM_OCTRL_POLB_MASK (0x200U)
33566 #define PWM_OCTRL_POLB_SHIFT (9U)
33567
33571 #define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
33572 #define PWM_OCTRL_POLA_MASK (0x400U)
33573 #define PWM_OCTRL_POLA_SHIFT (10U)
33574
33578 #define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
33579 #define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
33580 #define PWM_OCTRL_PWMX_IN_SHIFT (13U)
33581
33583 #define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
33584 #define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
33585 #define PWM_OCTRL_PWMB_IN_SHIFT (14U)
33586
33588 #define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
33589 #define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
33590 #define PWM_OCTRL_PWMA_IN_SHIFT (15U)
33591
33593 #define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
33594
33596 /* The count of PWM_OCTRL */
33597 #define PWM_OCTRL_COUNT (4U)
33598
33601 #define PWM_STS_CMPF_MASK (0x3FU)
33602 #define PWM_STS_CMPF_SHIFT (0U)
33603
33607 #define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
33608 #define PWM_STS_CFX0_MASK (0x40U)
33609 #define PWM_STS_CFX0_SHIFT (6U)
33610
33612 #define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
33613 #define PWM_STS_CFX1_MASK (0x80U)
33614 #define PWM_STS_CFX1_SHIFT (7U)
33615
33617 #define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
33618 #define PWM_STS_CFB0_MASK (0x100U)
33619 #define PWM_STS_CFB0_SHIFT (8U)
33620
33622 #define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
33623 #define PWM_STS_CFB1_MASK (0x200U)
33624 #define PWM_STS_CFB1_SHIFT (9U)
33625
33627 #define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
33628 #define PWM_STS_CFA0_MASK (0x400U)
33629 #define PWM_STS_CFA0_SHIFT (10U)
33630
33632 #define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
33633 #define PWM_STS_CFA1_MASK (0x800U)
33634 #define PWM_STS_CFA1_SHIFT (11U)
33635
33637 #define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
33638 #define PWM_STS_RF_MASK (0x1000U)
33639 #define PWM_STS_RF_SHIFT (12U)
33640
33644 #define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
33645 #define PWM_STS_REF_MASK (0x2000U)
33646 #define PWM_STS_REF_SHIFT (13U)
33647
33651 #define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
33652 #define PWM_STS_RUF_MASK (0x4000U)
33653 #define PWM_STS_RUF_SHIFT (14U)
33654
33658 #define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
33659
33661 /* The count of PWM_STS */
33662 #define PWM_STS_COUNT (4U)
33663
33666 #define PWM_INTEN_CMPIE_MASK (0x3FU)
33667 #define PWM_INTEN_CMPIE_SHIFT (0U)
33668
33672 #define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
33673 #define PWM_INTEN_CX0IE_MASK (0x40U)
33674 #define PWM_INTEN_CX0IE_SHIFT (6U)
33675
33679 #define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
33680 #define PWM_INTEN_CX1IE_MASK (0x80U)
33681 #define PWM_INTEN_CX1IE_SHIFT (7U)
33682
33686 #define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
33687 #define PWM_INTEN_CB0IE_MASK (0x100U)
33688 #define PWM_INTEN_CB0IE_SHIFT (8U)
33689
33693 #define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
33694 #define PWM_INTEN_CB1IE_MASK (0x200U)
33695 #define PWM_INTEN_CB1IE_SHIFT (9U)
33696
33700 #define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
33701 #define PWM_INTEN_CA0IE_MASK (0x400U)
33702 #define PWM_INTEN_CA0IE_SHIFT (10U)
33703
33707 #define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
33708 #define PWM_INTEN_CA1IE_MASK (0x800U)
33709 #define PWM_INTEN_CA1IE_SHIFT (11U)
33710
33714 #define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
33715 #define PWM_INTEN_RIE_MASK (0x1000U)
33716 #define PWM_INTEN_RIE_SHIFT (12U)
33717
33721 #define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
33722 #define PWM_INTEN_REIE_MASK (0x2000U)
33723 #define PWM_INTEN_REIE_SHIFT (13U)
33724
33728 #define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
33729
33731 /* The count of PWM_INTEN */
33732 #define PWM_INTEN_COUNT (4U)
33733
33736 #define PWM_DMAEN_CX0DE_MASK (0x1U)
33737 #define PWM_DMAEN_CX0DE_SHIFT (0U)
33738
33740 #define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
33741 #define PWM_DMAEN_CX1DE_MASK (0x2U)
33742 #define PWM_DMAEN_CX1DE_SHIFT (1U)
33743
33745 #define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
33746 #define PWM_DMAEN_CB0DE_MASK (0x4U)
33747 #define PWM_DMAEN_CB0DE_SHIFT (2U)
33748
33750 #define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
33751 #define PWM_DMAEN_CB1DE_MASK (0x8U)
33752 #define PWM_DMAEN_CB1DE_SHIFT (3U)
33753
33755 #define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
33756 #define PWM_DMAEN_CA0DE_MASK (0x10U)
33757 #define PWM_DMAEN_CA0DE_SHIFT (4U)
33758
33760 #define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
33761 #define PWM_DMAEN_CA1DE_MASK (0x20U)
33762 #define PWM_DMAEN_CA1DE_SHIFT (5U)
33763
33765 #define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
33766 #define PWM_DMAEN_CAPTDE_MASK (0xC0U)
33767 #define PWM_DMAEN_CAPTDE_SHIFT (6U)
33768
33776 #define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
33777 #define PWM_DMAEN_FAND_MASK (0x100U)
33778 #define PWM_DMAEN_FAND_SHIFT (8U)
33779
33783 #define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
33784 #define PWM_DMAEN_VALDE_MASK (0x200U)
33785 #define PWM_DMAEN_VALDE_SHIFT (9U)
33786
33790 #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
33791
33793 /* The count of PWM_DMAEN */
33794 #define PWM_DMAEN_COUNT (4U)
33795
33798 #define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
33799 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
33800
33804 #define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
33805 #define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
33806 #define PWM_TCTRL_TRGFRQ_SHIFT (12U)
33807
33812 #define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
33813 #define PWM_TCTRL_PWBOT1_MASK (0x4000U)
33814 #define PWM_TCTRL_PWBOT1_SHIFT (14U)
33815
33819 #define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
33820 #define PWM_TCTRL_PWAOT0_MASK (0x8000U)
33821 #define PWM_TCTRL_PWAOT0_SHIFT (15U)
33822
33826 #define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
33827
33829 /* The count of PWM_TCTRL */
33830 #define PWM_TCTRL_COUNT (4U)
33831
33834 #define PWM_DISMAP_DIS0A_MASK (0xFU)
33835 #define PWM_DISMAP_DIS0A_SHIFT (0U)
33836
33838 #define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
33839 #define PWM_DISMAP_DIS1A_MASK (0xFU)
33840 #define PWM_DISMAP_DIS1A_SHIFT (0U)
33841
33843 #define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
33844 #define PWM_DISMAP_DIS0B_MASK (0xF0U)
33845 #define PWM_DISMAP_DIS0B_SHIFT (4U)
33846
33848 #define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
33849 #define PWM_DISMAP_DIS1B_MASK (0xF0U)
33850 #define PWM_DISMAP_DIS1B_SHIFT (4U)
33851
33853 #define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
33854 #define PWM_DISMAP_DIS0X_MASK (0xF00U)
33855 #define PWM_DISMAP_DIS0X_SHIFT (8U)
33856
33858 #define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
33859 #define PWM_DISMAP_DIS1X_MASK (0xF00U)
33860 #define PWM_DISMAP_DIS1X_SHIFT (8U)
33861
33863 #define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
33864
33866 /* The count of PWM_DISMAP */
33867 #define PWM_DISMAP_COUNT (4U)
33868
33869 /* The count of PWM_DISMAP */
33870 #define PWM_DISMAP_COUNT2 (2U)
33871
33874 #define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
33875 #define PWM_DTCNT0_DTCNT0_SHIFT (0U)
33876
33878 #define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
33879
33881 /* The count of PWM_DTCNT0 */
33882 #define PWM_DTCNT0_COUNT (4U)
33883
33886 #define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
33887 #define PWM_DTCNT1_DTCNT1_SHIFT (0U)
33888
33890 #define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
33891
33893 /* The count of PWM_DTCNT1 */
33894 #define PWM_DTCNT1_COUNT (4U)
33895
33898 #define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
33899 #define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
33900
33904 #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
33905 #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
33906 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
33907
33919 #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
33920 #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
33921 #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
33922
33928 #define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
33929 #define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
33930 #define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
33931
33937 #define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
33938 #define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
33939 #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
33940
33947 #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
33948 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
33949 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
33950
33954 #define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
33955 #define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
33956 #define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
33957
33959 #define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
33960 #define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
33961 #define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
33962
33964 #define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
33965 #define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
33966 #define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
33967
33969 #define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
33970
33972 /* The count of PWM_CAPTCTRLA */
33973 #define PWM_CAPTCTRLA_COUNT (4U)
33974
33977 #define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
33978 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
33979
33981 #define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
33982 #define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
33983 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
33984
33986 #define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
33987
33989 /* The count of PWM_CAPTCOMPA */
33990 #define PWM_CAPTCOMPA_COUNT (4U)
33991
33994 #define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
33995 #define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
33996
34000 #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
34001 #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
34002 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
34003
34015 #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
34016 #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
34017 #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
34018
34024 #define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
34025 #define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
34026 #define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
34027
34033 #define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
34034 #define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
34035 #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
34036
34043 #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
34044 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
34045 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
34046
34050 #define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
34051 #define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
34052 #define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
34053
34055 #define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
34056 #define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
34057 #define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
34058
34060 #define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
34061 #define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
34062 #define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
34063
34065 #define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
34066
34068 /* The count of PWM_CAPTCTRLB */
34069 #define PWM_CAPTCTRLB_COUNT (4U)
34070
34073 #define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
34074 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
34075
34077 #define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
34078 #define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
34079 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
34080
34082 #define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
34083
34085 /* The count of PWM_CAPTCOMPB */
34086 #define PWM_CAPTCOMPB_COUNT (4U)
34087
34090 #define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
34091 #define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
34092
34096 #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
34097 #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
34098 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
34099
34111 #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
34112 #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
34113 #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
34114
34120 #define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
34121 #define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
34122 #define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
34123
34129 #define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
34130 #define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
34131 #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
34132
34139 #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
34140 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
34141 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
34142
34146 #define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
34147 #define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
34148 #define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
34149
34151 #define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
34152 #define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
34153 #define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
34154
34156 #define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
34157 #define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
34158 #define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
34159
34161 #define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
34162
34164 /* The count of PWM_CAPTCTRLX */
34165 #define PWM_CAPTCTRLX_COUNT (4U)
34166
34169 #define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
34170 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
34171
34173 #define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
34174 #define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
34175 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
34176
34178 #define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
34179
34181 /* The count of PWM_CAPTCOMPX */
34182 #define PWM_CAPTCOMPX_COUNT (4U)
34183
34186 #define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
34187 #define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
34188
34190 #define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
34191
34193 /* The count of PWM_CVAL0 */
34194 #define PWM_CVAL0_COUNT (4U)
34195
34198 #define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
34199 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
34200
34202 #define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
34203
34205 /* The count of PWM_CVAL0CYC */
34206 #define PWM_CVAL0CYC_COUNT (4U)
34207
34210 #define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
34211 #define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
34212
34214 #define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
34215
34217 /* The count of PWM_CVAL1 */
34218 #define PWM_CVAL1_COUNT (4U)
34219
34222 #define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
34223 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
34224
34226 #define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
34227
34229 /* The count of PWM_CVAL1CYC */
34230 #define PWM_CVAL1CYC_COUNT (4U)
34231
34234 #define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
34235 #define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
34236
34238 #define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
34239
34241 /* The count of PWM_CVAL2 */
34242 #define PWM_CVAL2_COUNT (4U)
34243
34246 #define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
34247 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
34248
34250 #define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
34251
34253 /* The count of PWM_CVAL2CYC */
34254 #define PWM_CVAL2CYC_COUNT (4U)
34255
34258 #define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
34259 #define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
34260
34262 #define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
34263
34265 /* The count of PWM_CVAL3 */
34266 #define PWM_CVAL3_COUNT (4U)
34267
34270 #define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
34271 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
34272
34274 #define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
34275
34277 /* The count of PWM_CVAL3CYC */
34278 #define PWM_CVAL3CYC_COUNT (4U)
34279
34282 #define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
34283 #define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
34284
34286 #define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
34287
34289 /* The count of PWM_CVAL4 */
34290 #define PWM_CVAL4_COUNT (4U)
34291
34294 #define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
34295 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
34296
34298 #define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
34299
34301 /* The count of PWM_CVAL4CYC */
34302 #define PWM_CVAL4CYC_COUNT (4U)
34303
34306 #define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
34307 #define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
34308
34310 #define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
34311
34313 /* The count of PWM_CVAL5 */
34314 #define PWM_CVAL5_COUNT (4U)
34315
34318 #define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
34319 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
34320
34322 #define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
34323
34325 /* The count of PWM_CVAL5CYC */
34326 #define PWM_CVAL5CYC_COUNT (4U)
34327
34330 #define PWM_OUTEN_PWMX_EN_MASK (0xFU)
34331 #define PWM_OUTEN_PWMX_EN_SHIFT (0U)
34332
34336 #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
34337 #define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
34338 #define PWM_OUTEN_PWMB_EN_SHIFT (4U)
34339
34343 #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
34344 #define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
34345 #define PWM_OUTEN_PWMA_EN_SHIFT (8U)
34346
34350 #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
34351
34355 #define PWM_MASK_MASKX_MASK (0xFU)
34356 #define PWM_MASK_MASKX_SHIFT (0U)
34357
34361 #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
34362 #define PWM_MASK_MASKB_MASK (0xF0U)
34363 #define PWM_MASK_MASKB_SHIFT (4U)
34364
34368 #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
34369 #define PWM_MASK_MASKA_MASK (0xF00U)
34370 #define PWM_MASK_MASKA_SHIFT (8U)
34371
34375 #define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
34376 #define PWM_MASK_UPDATE_MASK_MASK (0xF000U)
34377 #define PWM_MASK_UPDATE_MASK_SHIFT (12U)
34378
34382 #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
34383
34387 #define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
34388 #define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
34389
34393 #define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
34394 #define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
34395 #define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
34396
34400 #define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
34401 #define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
34402 #define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
34403
34407 #define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
34408 #define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
34409 #define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
34410
34414 #define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
34415 #define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
34416 #define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
34417
34421 #define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
34422 #define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
34423 #define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
34424
34428 #define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
34429 #define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
34430 #define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
34431
34435 #define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
34436 #define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
34437 #define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
34438
34442 #define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
34443
34447 #define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
34448 #define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
34449
34455 #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
34456 #define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
34457 #define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
34458
34464 #define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
34465 #define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
34466 #define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
34467
34473 #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
34474 #define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
34475 #define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
34476
34482 #define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
34483 #define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
34484 #define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
34485
34491 #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
34492 #define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
34493 #define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
34494
34500 #define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
34501 #define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
34502 #define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
34503
34509 #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
34510 #define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
34511 #define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
34512
34518 #define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
34519
34523 #define PWM_MCTRL_LDOK_MASK (0xFU)
34524 #define PWM_MCTRL_LDOK_SHIFT (0U)
34525
34529 #define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
34530 #define PWM_MCTRL_CLDOK_MASK (0xF0U)
34531 #define PWM_MCTRL_CLDOK_SHIFT (4U)
34532
34534 #define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
34535 #define PWM_MCTRL_RUN_MASK (0xF00U)
34536 #define PWM_MCTRL_RUN_SHIFT (8U)
34537
34541 #define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
34542 #define PWM_MCTRL_IPOL_MASK (0xF000U)
34543 #define PWM_MCTRL_IPOL_SHIFT (12U)
34544
34548 #define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
34549
34553 #define PWM_MCTRL2_MONPLL_MASK (0x3U)
34554 #define PWM_MCTRL2_MONPLL_SHIFT (0U)
34555
34563 #define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
34564
34568 #define PWM_FCTRL_FIE_MASK (0xFU)
34569 #define PWM_FCTRL_FIE_SHIFT (0U)
34570
34574 #define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
34575 #define PWM_FCTRL_FSAFE_MASK (0xF0U)
34576 #define PWM_FCTRL_FSAFE_SHIFT (4U)
34577
34586 #define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
34587 #define PWM_FCTRL_FAUTO_MASK (0xF00U)
34588 #define PWM_FCTRL_FAUTO_SHIFT (8U)
34589
34597 #define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
34598 #define PWM_FCTRL_FLVL_MASK (0xF000U)
34599 #define PWM_FCTRL_FLVL_SHIFT (12U)
34600
34604 #define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
34605
34609 #define PWM_FSTS_FFLAG_MASK (0xFU)
34610 #define PWM_FSTS_FFLAG_SHIFT (0U)
34611
34615 #define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
34616 #define PWM_FSTS_FFULL_MASK (0xF0U)
34617 #define PWM_FSTS_FFULL_SHIFT (4U)
34618
34622 #define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
34623 #define PWM_FSTS_FFPIN_MASK (0xF00U)
34624 #define PWM_FSTS_FFPIN_SHIFT (8U)
34625
34627 #define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
34628 #define PWM_FSTS_FHALF_MASK (0xF000U)
34629 #define PWM_FSTS_FHALF_SHIFT (12U)
34630
34634 #define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
34635
34639 #define PWM_FFILT_FILT_PER_MASK (0xFFU)
34640 #define PWM_FFILT_FILT_PER_SHIFT (0U)
34641
34643 #define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
34644 #define PWM_FFILT_FILT_CNT_MASK (0x700U)
34645 #define PWM_FFILT_FILT_CNT_SHIFT (8U)
34646
34648 #define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
34649 #define PWM_FFILT_GSTR_MASK (0x8000U)
34650 #define PWM_FFILT_GSTR_SHIFT (15U)
34651
34655 #define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
34656
34660 #define PWM_FTST_FTEST_MASK (0x1U)
34661 #define PWM_FTST_FTEST_SHIFT (0U)
34662
34666 #define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
34667
34671 #define PWM_FCTRL2_NOCOMB_MASK (0xFU)
34672 #define PWM_FCTRL2_NOCOMB_SHIFT (0U)
34673
34679 #define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
34680 /* end of group PWM_Register_Masks */
34686
34687
34688 /* PWM - Peripheral instance base addresses */
34690 #define PWM1_BASE (0x403DC000u)
34691
34692 #define PWM1 ((PWM_Type *)PWM1_BASE)
34693
34694 #define PWM2_BASE (0x403E0000u)
34695
34696 #define PWM2 ((PWM_Type *)PWM2_BASE)
34697
34698 #define PWM3_BASE (0x403E4000u)
34699
34700 #define PWM3 ((PWM_Type *)PWM3_BASE)
34701
34702 #define PWM4_BASE (0x403E8000u)
34703
34704 #define PWM4 ((PWM_Type *)PWM4_BASE)
34705
34706 #define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
34707
34708 #define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
34709
34710 #define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
34711 #define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
34712 #define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
34713 #define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
34714 #define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
34715 /* end of group PWM_Peripheral_Access_Layer */
34719
34720
34721 /* ----------------------------------------------------------------------------
34722 -- PXP Peripheral Access Layer
34723 ---------------------------------------------------------------------------- */
34724
34731 typedef struct {
34732 __IO uint32_t CTRL;
34733 __IO uint32_t CTRL_SET;
34734 __IO uint32_t CTRL_CLR;
34735 __IO uint32_t CTRL_TOG;
34736 __IO uint32_t STAT;
34737 __IO uint32_t STAT_SET;
34738 __IO uint32_t STAT_CLR;
34739 __IO uint32_t STAT_TOG;
34740 __IO uint32_t OUT_CTRL;
34741 __IO uint32_t OUT_CTRL_SET;
34742 __IO uint32_t OUT_CTRL_CLR;
34743 __IO uint32_t OUT_CTRL_TOG;
34744 __IO uint32_t OUT_BUF;
34745 uint8_t RESERVED_0[12];
34746 __IO uint32_t OUT_BUF2;
34747 uint8_t RESERVED_1[12];
34748 __IO uint32_t OUT_PITCH;
34749 uint8_t RESERVED_2[12];
34750 __IO uint32_t OUT_LRC;
34751 uint8_t RESERVED_3[12];
34752 __IO uint32_t OUT_PS_ULC;
34753 uint8_t RESERVED_4[12];
34754 __IO uint32_t OUT_PS_LRC;
34755 uint8_t RESERVED_5[12];
34756 __IO uint32_t OUT_AS_ULC;
34757 uint8_t RESERVED_6[12];
34758 __IO uint32_t OUT_AS_LRC;
34759 uint8_t RESERVED_7[12];
34760 __IO uint32_t PS_CTRL;
34761 __IO uint32_t PS_CTRL_SET;
34762 __IO uint32_t PS_CTRL_CLR;
34763 __IO uint32_t PS_CTRL_TOG;
34764 __IO uint32_t PS_BUF;
34765 uint8_t RESERVED_8[12];
34766 __IO uint32_t PS_UBUF;
34767 uint8_t RESERVED_9[12];
34768 __IO uint32_t PS_VBUF;
34769 uint8_t RESERVED_10[12];
34770 __IO uint32_t PS_PITCH;
34771 uint8_t RESERVED_11[12];
34772 __IO uint32_t PS_BACKGROUND;
34773 uint8_t RESERVED_12[12];
34774 __IO uint32_t PS_SCALE;
34775 uint8_t RESERVED_13[12];
34776 __IO uint32_t PS_OFFSET;
34777 uint8_t RESERVED_14[12];
34778 __IO uint32_t PS_CLRKEYLOW;
34779 uint8_t RESERVED_15[12];
34780 __IO uint32_t PS_CLRKEYHIGH;
34781 uint8_t RESERVED_16[12];
34782 __IO uint32_t AS_CTRL;
34783 uint8_t RESERVED_17[12];
34784 __IO uint32_t AS_BUF;
34785 uint8_t RESERVED_18[12];
34786 __IO uint32_t AS_PITCH;
34787 uint8_t RESERVED_19[12];
34788 __IO uint32_t AS_CLRKEYLOW;
34789 uint8_t RESERVED_20[12];
34790 __IO uint32_t AS_CLRKEYHIGH;
34791 uint8_t RESERVED_21[12];
34792 __IO uint32_t CSC1_COEF0;
34793 uint8_t RESERVED_22[12];
34794 __IO uint32_t CSC1_COEF1;
34795 uint8_t RESERVED_23[12];
34796 __IO uint32_t CSC1_COEF2;
34797 uint8_t RESERVED_24[348];
34798 __IO uint32_t POWER;
34799 uint8_t RESERVED_25[220];
34800 __IO uint32_t NEXT;
34801 uint8_t RESERVED_26[60];
34802 __IO uint32_t PORTER_DUFF_CTRL;
34803 } PXP_Type;
34804
34805 /* ----------------------------------------------------------------------------
34806 -- PXP Register Masks
34807 ---------------------------------------------------------------------------- */
34808
34816 #define PXP_CTRL_ENABLE_MASK (0x1U)
34817 #define PXP_CTRL_ENABLE_SHIFT (0U)
34818 #define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
34819 #define PXP_CTRL_IRQ_ENABLE_MASK (0x2U)
34820 #define PXP_CTRL_IRQ_ENABLE_SHIFT (1U)
34821 #define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
34822 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)
34823 #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)
34824 #define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
34825 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
34826 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
34827 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
34828 #define PXP_CTRL_RSVD0_MASK (0xE0U)
34829 #define PXP_CTRL_RSVD0_SHIFT (5U)
34830 #define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)
34831 #define PXP_CTRL_ROTATE_MASK (0x300U)
34832 #define PXP_CTRL_ROTATE_SHIFT (8U)
34833
34839 #define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
34840 #define PXP_CTRL_HFLIP_MASK (0x400U)
34841 #define PXP_CTRL_HFLIP_SHIFT (10U)
34842 #define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
34843 #define PXP_CTRL_VFLIP_MASK (0x800U)
34844 #define PXP_CTRL_VFLIP_SHIFT (11U)
34845 #define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
34846 #define PXP_CTRL_RSVD1_MASK (0x3FF000U)
34847 #define PXP_CTRL_RSVD1_SHIFT (12U)
34848 #define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK)
34849 #define PXP_CTRL_ROT_POS_MASK (0x400000U)
34850 #define PXP_CTRL_ROT_POS_SHIFT (22U)
34851 #define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
34852 #define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)
34853 #define PXP_CTRL_BLOCK_SIZE_SHIFT (23U)
34854
34858 #define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
34859 #define PXP_CTRL_RSVD3_MASK (0xF000000U)
34860 #define PXP_CTRL_RSVD3_SHIFT (24U)
34861 #define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK)
34862 #define PXP_CTRL_EN_REPEAT_MASK (0x10000000U)
34863 #define PXP_CTRL_EN_REPEAT_SHIFT (28U)
34864 #define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
34865 #define PXP_CTRL_RSVD4_MASK (0x20000000U)
34866 #define PXP_CTRL_RSVD4_SHIFT (29U)
34867 #define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK)
34868 #define PXP_CTRL_CLKGATE_MASK (0x40000000U)
34869 #define PXP_CTRL_CLKGATE_SHIFT (30U)
34870 #define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
34871 #define PXP_CTRL_SFTRST_MASK (0x80000000U)
34872 #define PXP_CTRL_SFTRST_SHIFT (31U)
34873 #define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
34874
34878 #define PXP_CTRL_SET_ENABLE_MASK (0x1U)
34879 #define PXP_CTRL_SET_ENABLE_SHIFT (0U)
34880 #define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
34881 #define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)
34882 #define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)
34883 #define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
34884 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)
34885 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)
34886 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
34887 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
34888 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
34889 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
34890 #define PXP_CTRL_SET_RSVD0_MASK (0xE0U)
34891 #define PXP_CTRL_SET_RSVD0_SHIFT (5U)
34892 #define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)
34893 #define PXP_CTRL_SET_ROTATE_MASK (0x300U)
34894 #define PXP_CTRL_SET_ROTATE_SHIFT (8U)
34895
34901 #define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
34902 #define PXP_CTRL_SET_HFLIP_MASK (0x400U)
34903 #define PXP_CTRL_SET_HFLIP_SHIFT (10U)
34904 #define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
34905 #define PXP_CTRL_SET_VFLIP_MASK (0x800U)
34906 #define PXP_CTRL_SET_VFLIP_SHIFT (11U)
34907 #define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
34908 #define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U)
34909 #define PXP_CTRL_SET_RSVD1_SHIFT (12U)
34910 #define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK)
34911 #define PXP_CTRL_SET_ROT_POS_MASK (0x400000U)
34912 #define PXP_CTRL_SET_ROT_POS_SHIFT (22U)
34913 #define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
34914 #define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)
34915 #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)
34916
34920 #define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
34921 #define PXP_CTRL_SET_RSVD3_MASK (0xF000000U)
34922 #define PXP_CTRL_SET_RSVD3_SHIFT (24U)
34923 #define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK)
34924 #define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)
34925 #define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)
34926 #define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
34927 #define PXP_CTRL_SET_RSVD4_MASK (0x20000000U)
34928 #define PXP_CTRL_SET_RSVD4_SHIFT (29U)
34929 #define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK)
34930 #define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)
34931 #define PXP_CTRL_SET_CLKGATE_SHIFT (30U)
34932 #define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
34933 #define PXP_CTRL_SET_SFTRST_MASK (0x80000000U)
34934 #define PXP_CTRL_SET_SFTRST_SHIFT (31U)
34935 #define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
34936
34940 #define PXP_CTRL_CLR_ENABLE_MASK (0x1U)
34941 #define PXP_CTRL_CLR_ENABLE_SHIFT (0U)
34942 #define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
34943 #define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)
34944 #define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)
34945 #define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
34946 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)
34947 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)
34948 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
34949 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
34950 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
34951 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
34952 #define PXP_CTRL_CLR_RSVD0_MASK (0xE0U)
34953 #define PXP_CTRL_CLR_RSVD0_SHIFT (5U)
34954 #define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)
34955 #define PXP_CTRL_CLR_ROTATE_MASK (0x300U)
34956 #define PXP_CTRL_CLR_ROTATE_SHIFT (8U)
34957
34963 #define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
34964 #define PXP_CTRL_CLR_HFLIP_MASK (0x400U)
34965 #define PXP_CTRL_CLR_HFLIP_SHIFT (10U)
34966 #define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
34967 #define PXP_CTRL_CLR_VFLIP_MASK (0x800U)
34968 #define PXP_CTRL_CLR_VFLIP_SHIFT (11U)
34969 #define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
34970 #define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U)
34971 #define PXP_CTRL_CLR_RSVD1_SHIFT (12U)
34972 #define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK)
34973 #define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)
34974 #define PXP_CTRL_CLR_ROT_POS_SHIFT (22U)
34975 #define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
34976 #define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)
34977 #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)
34978
34982 #define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
34983 #define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U)
34984 #define PXP_CTRL_CLR_RSVD3_SHIFT (24U)
34985 #define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK)
34986 #define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)
34987 #define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)
34988 #define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
34989 #define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U)
34990 #define PXP_CTRL_CLR_RSVD4_SHIFT (29U)
34991 #define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK)
34992 #define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
34993 #define PXP_CTRL_CLR_CLKGATE_SHIFT (30U)
34994 #define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
34995 #define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)
34996 #define PXP_CTRL_CLR_SFTRST_SHIFT (31U)
34997 #define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
34998
35002 #define PXP_CTRL_TOG_ENABLE_MASK (0x1U)
35003 #define PXP_CTRL_TOG_ENABLE_SHIFT (0U)
35004 #define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
35005 #define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)
35006 #define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)
35007 #define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
35008 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)
35009 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)
35010 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
35011 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
35012 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
35013 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
35014 #define PXP_CTRL_TOG_RSVD0_MASK (0xE0U)
35015 #define PXP_CTRL_TOG_RSVD0_SHIFT (5U)
35016 #define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)
35017 #define PXP_CTRL_TOG_ROTATE_MASK (0x300U)
35018 #define PXP_CTRL_TOG_ROTATE_SHIFT (8U)
35019
35025 #define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
35026 #define PXP_CTRL_TOG_HFLIP_MASK (0x400U)
35027 #define PXP_CTRL_TOG_HFLIP_SHIFT (10U)
35028 #define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
35029 #define PXP_CTRL_TOG_VFLIP_MASK (0x800U)
35030 #define PXP_CTRL_TOG_VFLIP_SHIFT (11U)
35031 #define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
35032 #define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U)
35033 #define PXP_CTRL_TOG_RSVD1_SHIFT (12U)
35034 #define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK)
35035 #define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)
35036 #define PXP_CTRL_TOG_ROT_POS_SHIFT (22U)
35037 #define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
35038 #define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)
35039 #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)
35040
35044 #define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
35045 #define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U)
35046 #define PXP_CTRL_TOG_RSVD3_SHIFT (24U)
35047 #define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK)
35048 #define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)
35049 #define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)
35050 #define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
35051 #define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U)
35052 #define PXP_CTRL_TOG_RSVD4_SHIFT (29U)
35053 #define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK)
35054 #define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
35055 #define PXP_CTRL_TOG_CLKGATE_SHIFT (30U)
35056 #define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
35057 #define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)
35058 #define PXP_CTRL_TOG_SFTRST_SHIFT (31U)
35059 #define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
35060
35064 #define PXP_STAT_IRQ_MASK (0x1U)
35065 #define PXP_STAT_IRQ_SHIFT (0U)
35066 #define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
35067 #define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)
35068 #define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)
35069 #define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
35070 #define PXP_STAT_AXI_READ_ERROR_MASK (0x4U)
35071 #define PXP_STAT_AXI_READ_ERROR_SHIFT (2U)
35072 #define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
35073 #define PXP_STAT_NEXT_IRQ_MASK (0x8U)
35074 #define PXP_STAT_NEXT_IRQ_SHIFT (3U)
35075 #define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
35076 #define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)
35077 #define PXP_STAT_AXI_ERROR_ID_SHIFT (4U)
35078 #define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
35079 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
35080 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
35081 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
35082 #define PXP_STAT_RSVD2_MASK (0xFE00U)
35083 #define PXP_STAT_RSVD2_SHIFT (9U)
35084 #define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK)
35085 #define PXP_STAT_BLOCKY_MASK (0xFF0000U)
35086 #define PXP_STAT_BLOCKY_SHIFT (16U)
35087 #define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
35088 #define PXP_STAT_BLOCKX_MASK (0xFF000000U)
35089 #define PXP_STAT_BLOCKX_SHIFT (24U)
35090 #define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
35091
35095 #define PXP_STAT_SET_IRQ_MASK (0x1U)
35096 #define PXP_STAT_SET_IRQ_SHIFT (0U)
35097 #define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
35098 #define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)
35099 #define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)
35100 #define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
35101 #define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)
35102 #define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)
35103 #define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
35104 #define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)
35105 #define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)
35106 #define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
35107 #define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)
35108 #define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)
35109 #define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
35110 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
35111 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
35112 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
35113 #define PXP_STAT_SET_RSVD2_MASK (0xFE00U)
35114 #define PXP_STAT_SET_RSVD2_SHIFT (9U)
35115 #define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK)
35116 #define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)
35117 #define PXP_STAT_SET_BLOCKY_SHIFT (16U)
35118 #define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
35119 #define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)
35120 #define PXP_STAT_SET_BLOCKX_SHIFT (24U)
35121 #define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
35122
35126 #define PXP_STAT_CLR_IRQ_MASK (0x1U)
35127 #define PXP_STAT_CLR_IRQ_SHIFT (0U)
35128 #define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
35129 #define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)
35130 #define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)
35131 #define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
35132 #define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)
35133 #define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)
35134 #define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
35135 #define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)
35136 #define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)
35137 #define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
35138 #define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)
35139 #define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)
35140 #define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
35141 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
35142 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
35143 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
35144 #define PXP_STAT_CLR_RSVD2_MASK (0xFE00U)
35145 #define PXP_STAT_CLR_RSVD2_SHIFT (9U)
35146 #define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK)
35147 #define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)
35148 #define PXP_STAT_CLR_BLOCKY_SHIFT (16U)
35149 #define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
35150 #define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)
35151 #define PXP_STAT_CLR_BLOCKX_SHIFT (24U)
35152 #define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
35153
35157 #define PXP_STAT_TOG_IRQ_MASK (0x1U)
35158 #define PXP_STAT_TOG_IRQ_SHIFT (0U)
35159 #define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
35160 #define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)
35161 #define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)
35162 #define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
35163 #define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)
35164 #define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)
35165 #define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
35166 #define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)
35167 #define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)
35168 #define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
35169 #define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)
35170 #define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)
35171 #define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
35172 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
35173 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
35174 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
35175 #define PXP_STAT_TOG_RSVD2_MASK (0xFE00U)
35176 #define PXP_STAT_TOG_RSVD2_SHIFT (9U)
35177 #define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK)
35178 #define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)
35179 #define PXP_STAT_TOG_BLOCKY_SHIFT (16U)
35180 #define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
35181 #define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)
35182 #define PXP_STAT_TOG_BLOCKX_SHIFT (24U)
35183 #define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
35184
35188 #define PXP_OUT_CTRL_FORMAT_MASK (0x1FU)
35189 #define PXP_OUT_CTRL_FORMAT_SHIFT (0U)
35190
35209 #define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
35210 #define PXP_OUT_CTRL_RSVD0_MASK (0xE0U)
35211 #define PXP_OUT_CTRL_RSVD0_SHIFT (5U)
35212 #define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)
35213 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)
35214 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)
35215
35221 #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
35222 #define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U)
35223 #define PXP_OUT_CTRL_RSVD1_SHIFT (10U)
35224 #define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK)
35225 #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)
35226 #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)
35227 #define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
35228 #define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)
35229 #define PXP_OUT_CTRL_ALPHA_SHIFT (24U)
35230 #define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
35231
35235 #define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)
35236 #define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)
35237
35256 #define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
35257 #define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U)
35258 #define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U)
35259 #define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)
35260 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)
35261 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
35262
35268 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
35269 #define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U)
35270 #define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U)
35271 #define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK)
35272 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)
35273 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)
35274 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
35275 #define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)
35276 #define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)
35277 #define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
35278
35282 #define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)
35283 #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)
35284
35303 #define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
35304 #define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U)
35305 #define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U)
35306 #define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)
35307 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)
35308 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
35309
35315 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
35316 #define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U)
35317 #define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U)
35318 #define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK)
35319 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)
35320 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)
35321 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
35322 #define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)
35323 #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)
35324 #define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
35325
35329 #define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)
35330 #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)
35331
35350 #define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
35351 #define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U)
35352 #define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U)
35353 #define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)
35354 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)
35355 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
35356
35362 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
35363 #define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U)
35364 #define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U)
35365 #define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK)
35366 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)
35367 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)
35368 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
35369 #define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)
35370 #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)
35371 #define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
35372
35376 #define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)
35377 #define PXP_OUT_BUF_ADDR_SHIFT (0U)
35378 #define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
35379
35383 #define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)
35384 #define PXP_OUT_BUF2_ADDR_SHIFT (0U)
35385 #define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
35386
35390 #define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)
35391 #define PXP_OUT_PITCH_PITCH_SHIFT (0U)
35392 #define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
35393 #define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U)
35394 #define PXP_OUT_PITCH_RSVD_SHIFT (16U)
35395 #define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK)
35396
35400 #define PXP_OUT_LRC_Y_MASK (0x3FFFU)
35401 #define PXP_OUT_LRC_Y_SHIFT (0U)
35402 #define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
35403 #define PXP_OUT_LRC_RSVD0_MASK (0xC000U)
35404 #define PXP_OUT_LRC_RSVD0_SHIFT (14U)
35405 #define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK)
35406 #define PXP_OUT_LRC_X_MASK (0x3FFF0000U)
35407 #define PXP_OUT_LRC_X_SHIFT (16U)
35408 #define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
35409 #define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U)
35410 #define PXP_OUT_LRC_RSVD1_SHIFT (30U)
35411 #define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK)
35412
35416 #define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)
35417 #define PXP_OUT_PS_ULC_Y_SHIFT (0U)
35418 #define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
35419 #define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U)
35420 #define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U)
35421 #define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK)
35422 #define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)
35423 #define PXP_OUT_PS_ULC_X_SHIFT (16U)
35424 #define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
35425 #define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U)
35426 #define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U)
35427 #define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK)
35428
35432 #define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)
35433 #define PXP_OUT_PS_LRC_Y_SHIFT (0U)
35434 #define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
35435 #define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U)
35436 #define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U)
35437 #define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK)
35438 #define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)
35439 #define PXP_OUT_PS_LRC_X_SHIFT (16U)
35440 #define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
35441 #define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U)
35442 #define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U)
35443 #define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK)
35444
35448 #define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)
35449 #define PXP_OUT_AS_ULC_Y_SHIFT (0U)
35450 #define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
35451 #define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U)
35452 #define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U)
35453 #define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK)
35454 #define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)
35455 #define PXP_OUT_AS_ULC_X_SHIFT (16U)
35456 #define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
35457 #define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U)
35458 #define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U)
35459 #define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK)
35460
35464 #define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)
35465 #define PXP_OUT_AS_LRC_Y_SHIFT (0U)
35466 #define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
35467 #define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U)
35468 #define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U)
35469 #define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK)
35470 #define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)
35471 #define PXP_OUT_AS_LRC_X_SHIFT (16U)
35472 #define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
35473 #define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U)
35474 #define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U)
35475 #define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK)
35476
35480 #define PXP_PS_CTRL_FORMAT_MASK (0x1FU)
35481 #define PXP_PS_CTRL_FORMAT_SHIFT (0U)
35482
35499 #define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
35500 #define PXP_PS_CTRL_WB_SWAP_MASK (0x20U)
35501 #define PXP_PS_CTRL_WB_SWAP_SHIFT (5U)
35502 #define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
35503 #define PXP_PS_CTRL_RSVD0_MASK (0xC0U)
35504 #define PXP_PS_CTRL_RSVD0_SHIFT (6U)
35505 #define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)
35506 #define PXP_PS_CTRL_DECY_MASK (0x300U)
35507 #define PXP_PS_CTRL_DECY_SHIFT (8U)
35508
35514 #define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
35515 #define PXP_PS_CTRL_DECX_MASK (0xC00U)
35516 #define PXP_PS_CTRL_DECX_SHIFT (10U)
35517
35523 #define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
35524 #define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U)
35525 #define PXP_PS_CTRL_RSVD1_SHIFT (12U)
35526 #define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK)
35527
35531 #define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU)
35532 #define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)
35533
35550 #define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
35551 #define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U)
35552 #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U)
35553 #define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
35554 #define PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U)
35555 #define PXP_PS_CTRL_SET_RSVD0_SHIFT (6U)
35556 #define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)
35557 #define PXP_PS_CTRL_SET_DECY_MASK (0x300U)
35558 #define PXP_PS_CTRL_SET_DECY_SHIFT (8U)
35559
35565 #define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
35566 #define PXP_PS_CTRL_SET_DECX_MASK (0xC00U)
35567 #define PXP_PS_CTRL_SET_DECX_SHIFT (10U)
35568
35574 #define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
35575 #define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U)
35576 #define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U)
35577 #define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK)
35578
35582 #define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU)
35583 #define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)
35584
35601 #define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
35602 #define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U)
35603 #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U)
35604 #define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
35605 #define PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U)
35606 #define PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U)
35607 #define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)
35608 #define PXP_PS_CTRL_CLR_DECY_MASK (0x300U)
35609 #define PXP_PS_CTRL_CLR_DECY_SHIFT (8U)
35610
35616 #define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
35617 #define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)
35618 #define PXP_PS_CTRL_CLR_DECX_SHIFT (10U)
35619
35625 #define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
35626 #define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U)
35627 #define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U)
35628 #define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK)
35629
35633 #define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU)
35634 #define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)
35635
35652 #define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
35653 #define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U)
35654 #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U)
35655 #define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
35656 #define PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U)
35657 #define PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U)
35658 #define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)
35659 #define PXP_PS_CTRL_TOG_DECY_MASK (0x300U)
35660 #define PXP_PS_CTRL_TOG_DECY_SHIFT (8U)
35661
35667 #define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
35668 #define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)
35669 #define PXP_PS_CTRL_TOG_DECX_SHIFT (10U)
35670
35676 #define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
35677 #define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U)
35678 #define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U)
35679 #define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK)
35680
35684 #define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)
35685 #define PXP_PS_BUF_ADDR_SHIFT (0U)
35686 #define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
35687
35691 #define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)
35692 #define PXP_PS_UBUF_ADDR_SHIFT (0U)
35693 #define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
35694
35698 #define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)
35699 #define PXP_PS_VBUF_ADDR_SHIFT (0U)
35700 #define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
35701
35705 #define PXP_PS_PITCH_PITCH_MASK (0xFFFFU)
35706 #define PXP_PS_PITCH_PITCH_SHIFT (0U)
35707 #define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
35708 #define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U)
35709 #define PXP_PS_PITCH_RSVD_SHIFT (16U)
35710 #define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK)
35711
35715 #define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)
35716 #define PXP_PS_BACKGROUND_COLOR_SHIFT (0U)
35717 #define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
35718 #define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U)
35719 #define PXP_PS_BACKGROUND_RSVD_SHIFT (24U)
35720 #define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK)
35721
35725 #define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)
35726 #define PXP_PS_SCALE_XSCALE_SHIFT (0U)
35727 #define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
35728 #define PXP_PS_SCALE_RSVD1_MASK (0x8000U)
35729 #define PXP_PS_SCALE_RSVD1_SHIFT (15U)
35730 #define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK)
35731 #define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)
35732 #define PXP_PS_SCALE_YSCALE_SHIFT (16U)
35733 #define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
35734 #define PXP_PS_SCALE_RSVD2_MASK (0x80000000U)
35735 #define PXP_PS_SCALE_RSVD2_SHIFT (31U)
35736 #define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK)
35737
35741 #define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)
35742 #define PXP_PS_OFFSET_XOFFSET_SHIFT (0U)
35743 #define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
35744 #define PXP_PS_OFFSET_RSVD1_MASK (0xF000U)
35745 #define PXP_PS_OFFSET_RSVD1_SHIFT (12U)
35746 #define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK)
35747 #define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)
35748 #define PXP_PS_OFFSET_YOFFSET_SHIFT (16U)
35749 #define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
35750 #define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U)
35751 #define PXP_PS_OFFSET_RSVD2_SHIFT (28U)
35752 #define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK)
35753
35757 #define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
35758 #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)
35759 #define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
35760 #define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
35761 #define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U)
35762 #define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK)
35763
35767 #define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
35768 #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)
35769 #define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
35770 #define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
35771 #define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U)
35772 #define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK)
35773
35777 #define PXP_AS_CTRL_RSVD0_MASK (0x1U)
35778 #define PXP_AS_CTRL_RSVD0_SHIFT (0U)
35779 #define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)
35780 #define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
35781 #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
35782
35789 #define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
35790 #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
35791 #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
35792 #define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
35793 #define PXP_AS_CTRL_FORMAT_MASK (0xF0U)
35794 #define PXP_AS_CTRL_FORMAT_SHIFT (4U)
35795
35804 #define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
35805 #define PXP_AS_CTRL_ALPHA_MASK (0xFF00U)
35806 #define PXP_AS_CTRL_ALPHA_SHIFT (8U)
35807 #define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
35808 #define PXP_AS_CTRL_ROP_MASK (0xF0000U)
35809 #define PXP_AS_CTRL_ROP_SHIFT (16U)
35810
35824 #define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
35825 #define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
35826 #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
35827 #define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
35828 #define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U)
35829 #define PXP_AS_CTRL_RSVD1_SHIFT (21U)
35830 #define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK)
35831
35835 #define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
35836 #define PXP_AS_BUF_ADDR_SHIFT (0U)
35837 #define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
35838
35842 #define PXP_AS_PITCH_PITCH_MASK (0xFFFFU)
35843 #define PXP_AS_PITCH_PITCH_SHIFT (0U)
35844 #define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
35845 #define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U)
35846 #define PXP_AS_PITCH_RSVD_SHIFT (16U)
35847 #define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK)
35848
35852 #define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
35853 #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
35854 #define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
35855 #define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
35856 #define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U)
35857 #define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK)
35858
35862 #define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
35863 #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
35864 #define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
35865 #define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
35866 #define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)
35867 #define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK)
35868
35872 #define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)
35873 #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)
35874 #define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
35875 #define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)
35876 #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)
35877 #define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
35878 #define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)
35879 #define PXP_CSC1_COEF0_C0_SHIFT (18U)
35880 #define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
35881 #define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U)
35882 #define PXP_CSC1_COEF0_RSVD1_SHIFT (29U)
35883 #define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK)
35884 #define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)
35885 #define PXP_CSC1_COEF0_BYPASS_SHIFT (30U)
35886 #define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
35887 #define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)
35888 #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)
35889 #define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
35890
35894 #define PXP_CSC1_COEF1_C4_MASK (0x7FFU)
35895 #define PXP_CSC1_COEF1_C4_SHIFT (0U)
35896 #define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
35897 #define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U)
35898 #define PXP_CSC1_COEF1_RSVD0_SHIFT (11U)
35899 #define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK)
35900 #define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)
35901 #define PXP_CSC1_COEF1_C1_SHIFT (16U)
35902 #define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
35903 #define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U)
35904 #define PXP_CSC1_COEF1_RSVD1_SHIFT (27U)
35905 #define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK)
35906
35910 #define PXP_CSC1_COEF2_C3_MASK (0x7FFU)
35911 #define PXP_CSC1_COEF2_C3_SHIFT (0U)
35912 #define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
35913 #define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U)
35914 #define PXP_CSC1_COEF2_RSVD0_SHIFT (11U)
35915 #define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK)
35916 #define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)
35917 #define PXP_CSC1_COEF2_C2_SHIFT (16U)
35918 #define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
35919 #define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U)
35920 #define PXP_CSC1_COEF2_RSVD1_SHIFT (27U)
35921 #define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK)
35922
35926 #define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)
35927 #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)
35928
35934 #define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
35935 #define PXP_POWER_CTRL_MASK (0xFFFFF000U)
35936 #define PXP_POWER_CTRL_SHIFT (12U)
35937 #define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)
35938
35942 #define PXP_NEXT_ENABLED_MASK (0x1U)
35943 #define PXP_NEXT_ENABLED_SHIFT (0U)
35944 #define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
35945 #define PXP_NEXT_RSVD_MASK (0x2U)
35946 #define PXP_NEXT_RSVD_SHIFT (1U)
35947 #define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK)
35948 #define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)
35949 #define PXP_NEXT_POINTER_SHIFT (2U)
35950 #define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
35951
35955 #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U)
35956 #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U)
35957 #define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK)
35958 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
35959 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
35960 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
35961 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
35962 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
35963 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
35964 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)
35965 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
35966 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
35967 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)
35968 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
35969 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
35970 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
35971 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
35972 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
35973 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
35974 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
35975 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
35976 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)
35977 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
35978 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
35979 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)
35980 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
35981 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
35982 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
35983 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
35984 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
35985 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
35986 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
35987 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
35988 /* end of group PXP_Register_Masks */
35994
35995
35996 /* PXP - Peripheral instance base addresses */
35998 #define PXP_BASE (0x402B4000u)
35999
36000 #define PXP ((PXP_Type *)PXP_BASE)
36001
36002 #define PXP_BASE_ADDRS { PXP_BASE }
36003
36004 #define PXP_BASE_PTRS { PXP }
36005
36006 #define PXP_IRQ0_IRQS { PXP_IRQn }
36007 /* end of group PXP_Peripheral_Access_Layer */
36011
36012
36013 /* ----------------------------------------------------------------------------
36014 -- ROMC Peripheral Access Layer
36015 ---------------------------------------------------------------------------- */
36016
36023 typedef struct {
36024 uint8_t RESERVED_0[212];
36025 __IO uint32_t ROMPATCHD[8];
36026 __IO uint32_t ROMPATCHCNTL;
36027 uint32_t ROMPATCHENH;
36028 __IO uint32_t ROMPATCHENL;
36029 __IO uint32_t ROMPATCHA[16];
36030 uint8_t RESERVED_1[200];
36031 __IO uint32_t ROMPATCHSR;
36032 } ROMC_Type;
36033
36034 /* ----------------------------------------------------------------------------
36035 -- ROMC Register Masks
36036 ---------------------------------------------------------------------------- */
36037
36045 #define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)
36046 #define ROMC_ROMPATCHD_DATAX_SHIFT (0U)
36047 #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
36048
36050 /* The count of ROMC_ROMPATCHD */
36051 #define ROMC_ROMPATCHD_COUNT (8U)
36052
36055 #define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)
36056 #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)
36057
36061 #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
36062 #define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)
36063 #define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)
36064
36068 #define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
36069
36073 #define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)
36074 #define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)
36075
36079 #define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
36080
36084 #define ROMC_ROMPATCHA_THUMBX_MASK (0x1U)
36085 #define ROMC_ROMPATCHA_THUMBX_SHIFT (0U)
36086
36090 #define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
36091 #define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)
36092 #define ROMC_ROMPATCHA_ADDRX_SHIFT (1U)
36093 #define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
36094
36096 /* The count of ROMC_ROMPATCHA */
36097 #define ROMC_ROMPATCHA_COUNT (16U)
36098
36101 #define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)
36102 #define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)
36103
36108 #define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
36109 #define ROMC_ROMPATCHSR_SW_MASK (0x20000U)
36110 #define ROMC_ROMPATCHSR_SW_SHIFT (17U)
36111
36115 #define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
36116 /* end of group ROMC_Register_Masks */
36122
36123
36124 /* ROMC - Peripheral instance base addresses */
36126 #define ROMC_BASE (0x40180000u)
36127
36128 #define ROMC ((ROMC_Type *)ROMC_BASE)
36129
36130 #define ROMC_BASE_ADDRS { ROMC_BASE }
36131
36132 #define ROMC_BASE_PTRS { ROMC }
36133 /* end of group ROMC_Peripheral_Access_Layer */
36137
36138
36139 /* ----------------------------------------------------------------------------
36140 -- RTWDOG Peripheral Access Layer
36141 ---------------------------------------------------------------------------- */
36142
36149 typedef struct {
36150 __IO uint32_t CS;
36151 __IO uint32_t CNT;
36152 __IO uint32_t TOVAL;
36153 __IO uint32_t WIN;
36154 } RTWDOG_Type;
36155
36156 /* ----------------------------------------------------------------------------
36157 -- RTWDOG Register Masks
36158 ---------------------------------------------------------------------------- */
36159
36167 #define RTWDOG_CS_STOP_MASK (0x1U)
36168 #define RTWDOG_CS_STOP_SHIFT (0U)
36169
36173 #define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
36174 #define RTWDOG_CS_WAIT_MASK (0x2U)
36175 #define RTWDOG_CS_WAIT_SHIFT (1U)
36176
36180 #define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
36181 #define RTWDOG_CS_DBG_MASK (0x4U)
36182 #define RTWDOG_CS_DBG_SHIFT (2U)
36183
36187 #define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
36188 #define RTWDOG_CS_TST_MASK (0x18U)
36189 #define RTWDOG_CS_TST_SHIFT (3U)
36190
36197 #define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
36198 #define RTWDOG_CS_UPDATE_MASK (0x20U)
36199 #define RTWDOG_CS_UPDATE_SHIFT (5U)
36200
36204 #define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
36205 #define RTWDOG_CS_INT_MASK (0x40U)
36206 #define RTWDOG_CS_INT_SHIFT (6U)
36207
36211 #define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
36212 #define RTWDOG_CS_EN_MASK (0x80U)
36213 #define RTWDOG_CS_EN_SHIFT (7U)
36214
36218 #define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
36219 #define RTWDOG_CS_CLK_MASK (0x300U)
36220 #define RTWDOG_CS_CLK_SHIFT (8U)
36221
36227 #define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
36228 #define RTWDOG_CS_RCS_MASK (0x400U)
36229 #define RTWDOG_CS_RCS_SHIFT (10U)
36230
36234 #define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
36235 #define RTWDOG_CS_ULK_MASK (0x800U)
36236 #define RTWDOG_CS_ULK_SHIFT (11U)
36237
36241 #define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
36242 #define RTWDOG_CS_PRES_MASK (0x1000U)
36243 #define RTWDOG_CS_PRES_SHIFT (12U)
36244
36248 #define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
36249 #define RTWDOG_CS_CMD32EN_MASK (0x2000U)
36250 #define RTWDOG_CS_CMD32EN_SHIFT (13U)
36251
36255 #define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
36256 #define RTWDOG_CS_FLG_MASK (0x4000U)
36257 #define RTWDOG_CS_FLG_SHIFT (14U)
36258
36262 #define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
36263 #define RTWDOG_CS_WIN_MASK (0x8000U)
36264 #define RTWDOG_CS_WIN_SHIFT (15U)
36265
36269 #define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
36270
36274 #define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
36275 #define RTWDOG_CNT_CNTLOW_SHIFT (0U)
36276
36278 #define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
36279 #define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
36280 #define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
36281
36283 #define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
36284
36288 #define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
36289 #define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
36290
36292 #define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
36293 #define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
36294 #define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
36295
36297 #define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
36298
36302 #define RTWDOG_WIN_WINLOW_MASK (0xFFU)
36303 #define RTWDOG_WIN_WINLOW_SHIFT (0U)
36304
36306 #define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
36307 #define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
36308 #define RTWDOG_WIN_WINHIGH_SHIFT (8U)
36309
36311 #define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
36312 /* end of group RTWDOG_Register_Masks */
36318
36319
36320 /* RTWDOG - Peripheral instance base addresses */
36322 #define RTWDOG_BASE (0x400BC000u)
36323
36324 #define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)
36325
36326 #define RTWDOG_BASE_ADDRS { RTWDOG_BASE }
36327
36328 #define RTWDOG_BASE_PTRS { RTWDOG }
36329
36330 #define RTWDOG_IRQS { RTWDOG_IRQn }
36331 /* Extra definition */
36332 #define RTWDOG_UPDATE_KEY (0xD928C520U)
36333 #define RTWDOG_REFRESH_KEY (0xB480A602U)
36334
36335 /* end of group RTWDOG_Peripheral_Access_Layer */
36339
36340
36341 /* ----------------------------------------------------------------------------
36342 -- SEMC Peripheral Access Layer
36343 ---------------------------------------------------------------------------- */
36344
36351 typedef struct {
36352 __IO uint32_t MCR;
36353 __IO uint32_t IOCR;
36354 __IO uint32_t BMCR0;
36355 __IO uint32_t BMCR1;
36356 __IO uint32_t BR[9];
36357 __IO uint32_t DLLCR;
36358 __IO uint32_t INTEN;
36359 __IO uint32_t INTR;
36360 __IO uint32_t SDRAMCR0;
36361 __IO uint32_t SDRAMCR1;
36362 __IO uint32_t SDRAMCR2;
36363 __IO uint32_t SDRAMCR3;
36364 __IO uint32_t NANDCR0;
36365 __IO uint32_t NANDCR1;
36366 __IO uint32_t NANDCR2;
36367 __IO uint32_t NANDCR3;
36368 __IO uint32_t NORCR0;
36369 __IO uint32_t NORCR1;
36370 __IO uint32_t NORCR2;
36371 __IO uint32_t NORCR3;
36372 __IO uint32_t SRAMCR0;
36373 __IO uint32_t SRAMCR1;
36374 __IO uint32_t SRAMCR2;
36375 uint32_t SRAMCR3;
36376 __IO uint32_t DBICR0;
36377 __IO uint32_t DBICR1;
36378 uint8_t RESERVED_0[8];
36379 __IO uint32_t IPCR0;
36380 __IO uint32_t IPCR1;
36381 __IO uint32_t IPCR2;
36382 __IO uint32_t IPCMD;
36383 __IO uint32_t IPTXDAT;
36384 uint8_t RESERVED_1[12];
36385 __I uint32_t IPRXDAT;
36386 uint8_t RESERVED_2[12];
36387 __I uint32_t STS0;
36388 uint32_t STS1;
36389 __I uint32_t STS2;
36390 uint32_t STS3;
36391 uint32_t STS4;
36392 uint32_t STS5;
36393 uint32_t STS6;
36394 uint32_t STS7;
36395 uint32_t STS8;
36396 uint32_t STS9;
36397 uint32_t STS10;
36398 uint32_t STS11;
36399 __I uint32_t STS12;
36400 __I uint32_t STS13;
36401 uint32_t STS14;
36402 uint32_t STS15;
36403 } SEMC_Type;
36404
36405 /* ----------------------------------------------------------------------------
36406 -- SEMC Register Masks
36407 ---------------------------------------------------------------------------- */
36408
36416 #define SEMC_MCR_SWRST_MASK (0x1U)
36417 #define SEMC_MCR_SWRST_SHIFT (0U)
36418
36420 #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
36421 #define SEMC_MCR_MDIS_MASK (0x2U)
36422 #define SEMC_MCR_MDIS_SHIFT (1U)
36423
36427 #define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
36428 #define SEMC_MCR_DQSMD_MASK (0x4U)
36429 #define SEMC_MCR_DQSMD_SHIFT (2U)
36430
36434 #define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
36435 #define SEMC_MCR_WPOL0_MASK (0x40U)
36436 #define SEMC_MCR_WPOL0_SHIFT (6U)
36437
36441 #define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
36442 #define SEMC_MCR_WPOL1_MASK (0x80U)
36443 #define SEMC_MCR_WPOL1_SHIFT (7U)
36444
36448 #define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
36449 #define SEMC_MCR_DQSSEL_MASK (0x400U)
36450 #define SEMC_MCR_DQSSEL_SHIFT (10U)
36451
36455 #define SEMC_MCR_DQSSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSSEL_SHIFT)) & SEMC_MCR_DQSSEL_MASK)
36456 #define SEMC_MCR_DLLSEL_MASK (0x800U)
36457 #define SEMC_MCR_DLLSEL_SHIFT (11U)
36458
36462 #define SEMC_MCR_DLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DLLSEL_SHIFT)) & SEMC_MCR_DLLSEL_MASK)
36463 #define SEMC_MCR_CTO_MASK (0xFF0000U)
36464 #define SEMC_MCR_CTO_SHIFT (16U)
36465
36467 #define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
36468 #define SEMC_MCR_BTO_MASK (0x1F000000U)
36469 #define SEMC_MCR_BTO_SHIFT (24U)
36470
36475 #define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
36476
36480 #define SEMC_IOCR_MUX_A8_MASK (0x7U)
36481 #define SEMC_IOCR_MUX_A8_SHIFT (0U)
36482
36492 #define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
36493 #define SEMC_IOCR_MUX_CSX0_MASK (0x38U)
36494 #define SEMC_IOCR_MUX_CSX0_SHIFT (3U)
36495
36505 #define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
36506 #define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
36507 #define SEMC_IOCR_MUX_CSX1_SHIFT (6U)
36508
36518 #define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
36519 #define SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
36520 #define SEMC_IOCR_MUX_CSX2_SHIFT (9U)
36521
36531 #define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
36532 #define SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
36533 #define SEMC_IOCR_MUX_CSX3_SHIFT (12U)
36534
36544 #define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
36545 #define SEMC_IOCR_MUX_RDY_MASK (0x38000U)
36546 #define SEMC_IOCR_MUX_RDY_SHIFT (15U)
36547
36557 #define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
36558 #define SEMC_IOCR_MUX_CLKX0_MASK (0x1000000U)
36559 #define SEMC_IOCR_MUX_CLKX0_SHIFT (24U)
36560
36564 #define SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
36565 #define SEMC_IOCR_MUX_CLKX1_MASK (0x2000000U)
36566 #define SEMC_IOCR_MUX_CLKX1_SHIFT (25U)
36567
36571 #define SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)
36572
36576 #define SEMC_BMCR0_WQOS_MASK (0xFU)
36577 #define SEMC_BMCR0_WQOS_SHIFT (0U)
36578
36580 #define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
36581 #define SEMC_BMCR0_WAGE_MASK (0xF0U)
36582 #define SEMC_BMCR0_WAGE_SHIFT (4U)
36583
36585 #define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
36586 #define SEMC_BMCR0_WSH_MASK (0xFF00U)
36587 #define SEMC_BMCR0_WSH_SHIFT (8U)
36588
36590 #define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
36591 #define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
36592 #define SEMC_BMCR0_WRWS_SHIFT (16U)
36593
36595 #define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
36596
36600 #define SEMC_BMCR1_WQOS_MASK (0xFU)
36601 #define SEMC_BMCR1_WQOS_SHIFT (0U)
36602
36604 #define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
36605 #define SEMC_BMCR1_WAGE_MASK (0xF0U)
36606 #define SEMC_BMCR1_WAGE_SHIFT (4U)
36607
36609 #define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
36610 #define SEMC_BMCR1_WPH_MASK (0xFF00U)
36611 #define SEMC_BMCR1_WPH_SHIFT (8U)
36612
36614 #define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
36615 #define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
36616 #define SEMC_BMCR1_WRWS_SHIFT (16U)
36617
36619 #define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
36620 #define SEMC_BMCR1_WBR_MASK (0xFF000000U)
36621 #define SEMC_BMCR1_WBR_SHIFT (24U)
36622
36624 #define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
36625
36629 #define SEMC_BR_VLD_MASK (0x1U)
36630 #define SEMC_BR_VLD_SHIFT (0U)
36631
36633 #define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
36634 #define SEMC_BR_MS_MASK (0x3EU)
36635 #define SEMC_BR_MS_SHIFT (1U)
36636
36670 #define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
36671 #define SEMC_BR_BA_MASK (0xFFFFF000U)
36672 #define SEMC_BR_BA_SHIFT (12U)
36673
36675 #define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
36676
36678 /* The count of SEMC_BR */
36679 #define SEMC_BR_COUNT (9U)
36680
36683 #define SEMC_DLLCR_DLLEN_MASK (0x1U)
36684 #define SEMC_DLLCR_DLLEN_SHIFT (0U)
36685
36687 #define SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
36688 #define SEMC_DLLCR_DLLRESET_MASK (0x2U)
36689 #define SEMC_DLLCR_DLLRESET_SHIFT (1U)
36690
36695 #define SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
36696 #define SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U)
36697 #define SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U)
36698
36700 #define SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
36701 #define SEMC_DLLCR_OVRDEN_MASK (0x100U)
36702 #define SEMC_DLLCR_OVRDEN_SHIFT (8U)
36703
36705 #define SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
36706 #define SEMC_DLLCR_OVRDVAL_MASK (0x7E00U)
36707 #define SEMC_DLLCR_OVRDVAL_SHIFT (9U)
36708
36710 #define SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)
36711
36715 #define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
36716 #define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
36717
36719 #define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
36720 #define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
36721 #define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
36722
36724 #define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
36725 #define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
36726 #define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
36727
36729 #define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
36730 #define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
36731 #define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
36732
36734 #define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
36735 #define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
36736 #define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
36737
36741 #define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
36742 #define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
36743 #define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
36744
36748 #define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
36749
36753 #define SEMC_INTR_IPCMDDONE_MASK (0x1U)
36754 #define SEMC_INTR_IPCMDDONE_SHIFT (0U)
36755
36757 #define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
36758 #define SEMC_INTR_IPCMDERR_MASK (0x2U)
36759 #define SEMC_INTR_IPCMDERR_SHIFT (1U)
36760
36762 #define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
36763 #define SEMC_INTR_AXICMDERR_MASK (0x4U)
36764 #define SEMC_INTR_AXICMDERR_SHIFT (2U)
36765
36767 #define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
36768 #define SEMC_INTR_AXIBUSERR_MASK (0x8U)
36769 #define SEMC_INTR_AXIBUSERR_SHIFT (3U)
36770
36772 #define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
36773 #define SEMC_INTR_NDPAGEEND_MASK (0x10U)
36774 #define SEMC_INTR_NDPAGEEND_SHIFT (4U)
36775
36777 #define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
36778 #define SEMC_INTR_NDNOPEND_MASK (0x20U)
36779 #define SEMC_INTR_NDNOPEND_SHIFT (5U)
36780
36782 #define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
36783
36787 #define SEMC_SDRAMCR0_PS_MASK (0x1U)
36788 #define SEMC_SDRAMCR0_PS_SHIFT (0U)
36789
36793 #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
36794 #define SEMC_SDRAMCR0_BL_MASK (0x70U)
36795 #define SEMC_SDRAMCR0_BL_SHIFT (4U)
36796
36806 #define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
36807 #define SEMC_SDRAMCR0_COL8_MASK (0x80U)
36808 #define SEMC_SDRAMCR0_COL8_SHIFT (7U)
36809
36813 #define SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
36814 #define SEMC_SDRAMCR0_COL_MASK (0x300U)
36815 #define SEMC_SDRAMCR0_COL_SHIFT (8U)
36816
36822 #define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
36823 #define SEMC_SDRAMCR0_CL_MASK (0xC00U)
36824 #define SEMC_SDRAMCR0_CL_SHIFT (10U)
36825
36831 #define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
36832 #define SEMC_SDRAMCR0_BANK2_MASK (0x4000U)
36833 #define SEMC_SDRAMCR0_BANK2_SHIFT (14U)
36834
36838 #define SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)
36839
36843 #define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
36844 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
36845
36847 #define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
36848 #define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
36849 #define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
36850
36852 #define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
36853 #define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
36854 #define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
36855
36857 #define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
36858 #define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
36859 #define SEMC_SDRAMCR1_WRC_SHIFT (13U)
36860
36862 #define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
36863 #define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
36864 #define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
36865
36867 #define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
36868 #define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
36869 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
36870
36872 #define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
36873
36877 #define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
36878 #define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
36879
36881 #define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
36882 #define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
36883 #define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
36884
36886 #define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
36887 #define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
36888 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
36889
36891 #define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
36892 #define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
36893 #define SEMC_SDRAMCR2_ITO_SHIFT (24U)
36894
36898 #define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
36899
36903 #define SEMC_SDRAMCR3_REN_MASK (0x1U)
36904 #define SEMC_SDRAMCR3_REN_SHIFT (0U)
36905
36907 #define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
36908 #define SEMC_SDRAMCR3_REBL_MASK (0xEU)
36909 #define SEMC_SDRAMCR3_REBL_SHIFT (1U)
36910
36920 #define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
36921 #define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
36922 #define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
36923
36927 #define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
36928 #define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
36929 #define SEMC_SDRAMCR3_RT_SHIFT (16U)
36930
36934 #define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
36935 #define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
36936 #define SEMC_SDRAMCR3_UT_SHIFT (24U)
36937
36941 #define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
36942
36946 #define SEMC_NANDCR0_PS_MASK (0x1U)
36947 #define SEMC_NANDCR0_PS_SHIFT (0U)
36948
36952 #define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
36953 #define SEMC_NANDCR0_SYNCEN_MASK (0x2U)
36954 #define SEMC_NANDCR0_SYNCEN_SHIFT (1U)
36955
36959 #define SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
36960 #define SEMC_NANDCR0_BL_MASK (0x70U)
36961 #define SEMC_NANDCR0_BL_SHIFT (4U)
36962
36972 #define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
36973 #define SEMC_NANDCR0_EDO_MASK (0x80U)
36974 #define SEMC_NANDCR0_EDO_SHIFT (7U)
36975
36979 #define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
36980 #define SEMC_NANDCR0_COL_MASK (0x700U)
36981 #define SEMC_NANDCR0_COL_SHIFT (8U)
36982
36992 #define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
36993
36997 #define SEMC_NANDCR1_CES_MASK (0xFU)
36998 #define SEMC_NANDCR1_CES_SHIFT (0U)
36999
37001 #define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
37002 #define SEMC_NANDCR1_CEH_MASK (0xF0U)
37003 #define SEMC_NANDCR1_CEH_SHIFT (4U)
37004
37006 #define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
37007 #define SEMC_NANDCR1_WEL_MASK (0xF00U)
37008 #define SEMC_NANDCR1_WEL_SHIFT (8U)
37009
37011 #define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
37012 #define SEMC_NANDCR1_WEH_MASK (0xF000U)
37013 #define SEMC_NANDCR1_WEH_SHIFT (12U)
37014
37016 #define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
37017 #define SEMC_NANDCR1_REL_MASK (0xF0000U)
37018 #define SEMC_NANDCR1_REL_SHIFT (16U)
37019
37021 #define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
37022 #define SEMC_NANDCR1_REH_MASK (0xF00000U)
37023 #define SEMC_NANDCR1_REH_SHIFT (20U)
37024
37026 #define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
37027 #define SEMC_NANDCR1_TA_MASK (0xF000000U)
37028 #define SEMC_NANDCR1_TA_SHIFT (24U)
37029
37031 #define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
37032 #define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
37033 #define SEMC_NANDCR1_CEITV_SHIFT (28U)
37034
37036 #define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
37037
37041 #define SEMC_NANDCR2_TWHR_MASK (0x3FU)
37042 #define SEMC_NANDCR2_TWHR_SHIFT (0U)
37043
37045 #define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
37046 #define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
37047 #define SEMC_NANDCR2_TRHW_SHIFT (6U)
37048
37050 #define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
37051 #define SEMC_NANDCR2_TADL_MASK (0x3F000U)
37052 #define SEMC_NANDCR2_TADL_SHIFT (12U)
37053
37055 #define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
37056 #define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
37057 #define SEMC_NANDCR2_TRR_SHIFT (18U)
37058
37060 #define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
37061 #define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
37062 #define SEMC_NANDCR2_TWB_SHIFT (24U)
37063
37065 #define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
37066
37070 #define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
37071 #define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
37072
37074 #define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
37075 #define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
37076 #define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
37077
37079 #define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
37080 #define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
37081 #define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
37082
37084 #define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
37085 #define SEMC_NANDCR3_CLE_MASK (0x8U)
37086 #define SEMC_NANDCR3_CLE_SHIFT (3U)
37087
37089 #define SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
37090 #define SEMC_NANDCR3_RDS_MASK (0xF0000U)
37091 #define SEMC_NANDCR3_RDS_SHIFT (16U)
37092
37094 #define SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
37095 #define SEMC_NANDCR3_RDH_MASK (0xF00000U)
37096 #define SEMC_NANDCR3_RDH_SHIFT (20U)
37097
37099 #define SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
37100 #define SEMC_NANDCR3_WDS_MASK (0xF000000U)
37101 #define SEMC_NANDCR3_WDS_SHIFT (24U)
37102
37104 #define SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
37105 #define SEMC_NANDCR3_WDH_MASK (0xF0000000U)
37106 #define SEMC_NANDCR3_WDH_SHIFT (28U)
37107
37109 #define SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)
37110
37114 #define SEMC_NORCR0_PS_MASK (0x1U)
37115 #define SEMC_NORCR0_PS_SHIFT (0U)
37116
37120 #define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
37121 #define SEMC_NORCR0_SYNCEN_MASK (0x2U)
37122 #define SEMC_NORCR0_SYNCEN_SHIFT (1U)
37123
37127 #define SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
37128 #define SEMC_NORCR0_BL_MASK (0x70U)
37129 #define SEMC_NORCR0_BL_SHIFT (4U)
37130
37140 #define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
37141 #define SEMC_NORCR0_AM_MASK (0x300U)
37142 #define SEMC_NORCR0_AM_SHIFT (8U)
37143
37149 #define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
37150 #define SEMC_NORCR0_ADVP_MASK (0x400U)
37151 #define SEMC_NORCR0_ADVP_SHIFT (10U)
37152
37156 #define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
37157 #define SEMC_NORCR0_ADVH_MASK (0x800U)
37158 #define SEMC_NORCR0_ADVH_SHIFT (11U)
37159
37163 #define SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
37164 #define SEMC_NORCR0_COL_MASK (0xF000U)
37165 #define SEMC_NORCR0_COL_SHIFT (12U)
37166
37184 #define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
37185
37189 #define SEMC_NORCR1_CES_MASK (0xFU)
37190 #define SEMC_NORCR1_CES_SHIFT (0U)
37191
37193 #define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
37194 #define SEMC_NORCR1_CEH_MASK (0xF0U)
37195 #define SEMC_NORCR1_CEH_SHIFT (4U)
37196
37198 #define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
37199 #define SEMC_NORCR1_AS_MASK (0xF00U)
37200 #define SEMC_NORCR1_AS_SHIFT (8U)
37201
37203 #define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
37204 #define SEMC_NORCR1_AH_MASK (0xF000U)
37205 #define SEMC_NORCR1_AH_SHIFT (12U)
37206
37208 #define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
37209 #define SEMC_NORCR1_WEL_MASK (0xF0000U)
37210 #define SEMC_NORCR1_WEL_SHIFT (16U)
37211
37213 #define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
37214 #define SEMC_NORCR1_WEH_MASK (0xF00000U)
37215 #define SEMC_NORCR1_WEH_SHIFT (20U)
37216
37218 #define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
37219 #define SEMC_NORCR1_REL_MASK (0xF000000U)
37220 #define SEMC_NORCR1_REL_SHIFT (24U)
37221
37223 #define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
37224 #define SEMC_NORCR1_REH_MASK (0xF0000000U)
37225 #define SEMC_NORCR1_REH_SHIFT (28U)
37226
37228 #define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
37229
37233 #define SEMC_NORCR2_TA_MASK (0xF00U)
37234 #define SEMC_NORCR2_TA_SHIFT (8U)
37235
37237 #define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
37238 #define SEMC_NORCR2_AWDH_MASK (0xF000U)
37239 #define SEMC_NORCR2_AWDH_SHIFT (12U)
37240
37242 #define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
37243 #define SEMC_NORCR2_LC_MASK (0xF0000U)
37244 #define SEMC_NORCR2_LC_SHIFT (16U)
37245
37247 #define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
37248 #define SEMC_NORCR2_RD_MASK (0xF00000U)
37249 #define SEMC_NORCR2_RD_SHIFT (20U)
37250
37252 #define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
37253 #define SEMC_NORCR2_CEITV_MASK (0xF000000U)
37254 #define SEMC_NORCR2_CEITV_SHIFT (24U)
37255
37257 #define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
37258 #define SEMC_NORCR2_RDH_MASK (0xF0000000U)
37259 #define SEMC_NORCR2_RDH_SHIFT (28U)
37260
37262 #define SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
37263
37267 #define SEMC_NORCR3_ASSR_MASK (0xFU)
37268 #define SEMC_NORCR3_ASSR_SHIFT (0U)
37269
37271 #define SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
37272 #define SEMC_NORCR3_AHSR_MASK (0xF0U)
37273 #define SEMC_NORCR3_AHSR_SHIFT (4U)
37274
37276 #define SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)
37277
37281 #define SEMC_SRAMCR0_PS_MASK (0x1U)
37282 #define SEMC_SRAMCR0_PS_SHIFT (0U)
37283
37287 #define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
37288 #define SEMC_SRAMCR0_SYNCEN_MASK (0x2U)
37289 #define SEMC_SRAMCR0_SYNCEN_SHIFT (1U)
37290
37294 #define SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
37295 #define SEMC_SRAMCR0_BL_MASK (0x70U)
37296 #define SEMC_SRAMCR0_BL_SHIFT (4U)
37297
37307 #define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
37308 #define SEMC_SRAMCR0_AM_MASK (0x300U)
37309 #define SEMC_SRAMCR0_AM_SHIFT (8U)
37310
37316 #define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
37317 #define SEMC_SRAMCR0_ADVP_MASK (0x400U)
37318 #define SEMC_SRAMCR0_ADVP_SHIFT (10U)
37319
37323 #define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
37324 #define SEMC_SRAMCR0_ADVH_MASK (0x800U)
37325 #define SEMC_SRAMCR0_ADVH_SHIFT (11U)
37326
37330 #define SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
37331 #define SEMC_SRAMCR0_COL_MASK (0xF000U)
37332 #define SEMC_SRAMCR0_COL_SHIFT (12U)
37333
37351 #define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
37352
37356 #define SEMC_SRAMCR1_CES_MASK (0xFU)
37357 #define SEMC_SRAMCR1_CES_SHIFT (0U)
37358
37360 #define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
37361 #define SEMC_SRAMCR1_CEH_MASK (0xF0U)
37362 #define SEMC_SRAMCR1_CEH_SHIFT (4U)
37363
37365 #define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
37366 #define SEMC_SRAMCR1_AS_MASK (0xF00U)
37367 #define SEMC_SRAMCR1_AS_SHIFT (8U)
37368
37370 #define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
37371 #define SEMC_SRAMCR1_AH_MASK (0xF000U)
37372 #define SEMC_SRAMCR1_AH_SHIFT (12U)
37373
37375 #define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
37376 #define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
37377 #define SEMC_SRAMCR1_WEL_SHIFT (16U)
37378
37380 #define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
37381 #define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
37382 #define SEMC_SRAMCR1_WEH_SHIFT (20U)
37383
37385 #define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
37386 #define SEMC_SRAMCR1_REL_MASK (0xF000000U)
37387 #define SEMC_SRAMCR1_REL_SHIFT (24U)
37388
37390 #define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
37391 #define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
37392 #define SEMC_SRAMCR1_REH_SHIFT (28U)
37393
37395 #define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
37396
37400 #define SEMC_SRAMCR2_WDS_MASK (0xFU)
37401 #define SEMC_SRAMCR2_WDS_SHIFT (0U)
37402
37404 #define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
37405 #define SEMC_SRAMCR2_WDH_MASK (0xF0U)
37406 #define SEMC_SRAMCR2_WDH_SHIFT (4U)
37407
37409 #define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
37410 #define SEMC_SRAMCR2_TA_MASK (0xF00U)
37411 #define SEMC_SRAMCR2_TA_SHIFT (8U)
37412
37414 #define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
37415 #define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
37416 #define SEMC_SRAMCR2_AWDH_SHIFT (12U)
37417
37419 #define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
37420 #define SEMC_SRAMCR2_LC_MASK (0xF0000U)
37421 #define SEMC_SRAMCR2_LC_SHIFT (16U)
37422
37424 #define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
37425 #define SEMC_SRAMCR2_RD_MASK (0xF00000U)
37426 #define SEMC_SRAMCR2_RD_SHIFT (20U)
37427
37429 #define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
37430 #define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
37431 #define SEMC_SRAMCR2_CEITV_SHIFT (24U)
37432
37434 #define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
37435 #define SEMC_SRAMCR2_RDH_MASK (0xF0000000U)
37436 #define SEMC_SRAMCR2_RDH_SHIFT (28U)
37437
37439 #define SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)
37440
37444 #define SEMC_DBICR0_PS_MASK (0x1U)
37445 #define SEMC_DBICR0_PS_SHIFT (0U)
37446
37450 #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
37451 #define SEMC_DBICR0_BL_MASK (0x70U)
37452 #define SEMC_DBICR0_BL_SHIFT (4U)
37453
37463 #define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
37464 #define SEMC_DBICR0_COL_MASK (0xF000U)
37465 #define SEMC_DBICR0_COL_SHIFT (12U)
37466
37484 #define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
37485
37489 #define SEMC_DBICR1_CES_MASK (0xFU)
37490 #define SEMC_DBICR1_CES_SHIFT (0U)
37491
37493 #define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
37494 #define SEMC_DBICR1_CEH_MASK (0xF0U)
37495 #define SEMC_DBICR1_CEH_SHIFT (4U)
37496
37498 #define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
37499 #define SEMC_DBICR1_WEL_MASK (0xF00U)
37500 #define SEMC_DBICR1_WEL_SHIFT (8U)
37501
37503 #define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
37504 #define SEMC_DBICR1_WEH_MASK (0xF000U)
37505 #define SEMC_DBICR1_WEH_SHIFT (12U)
37506
37508 #define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
37509 #define SEMC_DBICR1_REL_MASK (0x3F0000U)
37510 #define SEMC_DBICR1_REL_SHIFT (16U)
37511
37513 #define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
37514 #define SEMC_DBICR1_REH_MASK (0xFC00000U)
37515 #define SEMC_DBICR1_REH_SHIFT (22U)
37516
37518 #define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
37519 #define SEMC_DBICR1_CEITV_MASK (0xF0000000U)
37520 #define SEMC_DBICR1_CEITV_SHIFT (28U)
37521
37523 #define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
37524
37528 #define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
37529 #define SEMC_IPCR0_SA_SHIFT (0U)
37530
37532 #define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
37533
37537 #define SEMC_IPCR1_DATSZ_MASK (0x7U)
37538 #define SEMC_IPCR1_DATSZ_SHIFT (0U)
37539
37549 #define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
37550 #define SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U)
37551 #define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U)
37552
37554 #define SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)
37555
37559 #define SEMC_IPCR2_BM0_MASK (0x1U)
37560 #define SEMC_IPCR2_BM0_SHIFT (0U)
37561
37565 #define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
37566 #define SEMC_IPCR2_BM1_MASK (0x2U)
37567 #define SEMC_IPCR2_BM1_SHIFT (1U)
37568
37572 #define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
37573 #define SEMC_IPCR2_BM2_MASK (0x4U)
37574 #define SEMC_IPCR2_BM2_SHIFT (2U)
37575
37579 #define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
37580 #define SEMC_IPCR2_BM3_MASK (0x8U)
37581 #define SEMC_IPCR2_BM3_SHIFT (3U)
37582
37586 #define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
37587
37591 #define SEMC_IPCMD_CMD_MASK (0xFFFFU)
37592 #define SEMC_IPCMD_CMD_SHIFT (0U)
37593 #define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
37594 #define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
37595 #define SEMC_IPCMD_KEY_SHIFT (16U)
37596 #define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
37597
37601 #define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
37602 #define SEMC_IPTXDAT_DAT_SHIFT (0U)
37603 #define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
37604
37608 #define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
37609 #define SEMC_IPRXDAT_DAT_SHIFT (0U)
37610 #define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
37611
37615 #define SEMC_STS0_IDLE_MASK (0x1U)
37616 #define SEMC_STS0_IDLE_SHIFT (0U)
37617
37619 #define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
37620 #define SEMC_STS0_NARDY_MASK (0x2U)
37621 #define SEMC_STS0_NARDY_SHIFT (1U)
37622
37626 #define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
37627
37631 #define SEMC_STS2_NDWRPEND_MASK (0x8U)
37632 #define SEMC_STS2_NDWRPEND_SHIFT (3U)
37633
37637 #define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
37638
37642 #define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
37643 #define SEMC_STS12_NDADDR_SHIFT (0U)
37644
37646 #define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
37647
37651 #define SEMC_STS13_SLVLOCK_MASK (0x1U)
37652 #define SEMC_STS13_SLVLOCK_SHIFT (0U)
37653
37655 #define SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
37656 #define SEMC_STS13_REFLOCK_MASK (0x2U)
37657 #define SEMC_STS13_REFLOCK_SHIFT (1U)
37658
37660 #define SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
37661 #define SEMC_STS13_SLVSEL_MASK (0xFCU)
37662 #define SEMC_STS13_SLVSEL_SHIFT (2U)
37663
37665 #define SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
37666 #define SEMC_STS13_REFSEL_MASK (0x3F00U)
37667 #define SEMC_STS13_REFSEL_SHIFT (8U)
37668
37670 #define SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)
37671 /* end of group SEMC_Register_Masks */
37677
37678
37679 /* SEMC - Peripheral instance base addresses */
37681 #define SEMC_BASE (0x402F0000u)
37682
37683 #define SEMC ((SEMC_Type *)SEMC_BASE)
37684
37685 #define SEMC_BASE_ADDRS { SEMC_BASE }
37686
37687 #define SEMC_BASE_PTRS { SEMC }
37688
37689 #define SEMC_IRQS { SEMC_IRQn }
37690 /* end of group SEMC_Peripheral_Access_Layer */
37694
37695
37696 /* ----------------------------------------------------------------------------
37697 -- SNVS Peripheral Access Layer
37698 ---------------------------------------------------------------------------- */
37699
37706 typedef struct {
37707 __IO uint32_t HPLR;
37708 __IO uint32_t HPCOMR;
37709 __IO uint32_t HPCR;
37710 __IO uint32_t HPSICR;
37711 __IO uint32_t HPSVCR;
37712 __IO uint32_t HPSR;
37713 __IO uint32_t HPSVSR;
37714 __IO uint32_t HPHACIVR;
37715 __I uint32_t HPHACR;
37716 __IO uint32_t HPRTCMR;
37717 __IO uint32_t HPRTCLR;
37718 __IO uint32_t HPTAMR;
37719 __IO uint32_t HPTALR;
37720 __IO uint32_t LPLR;
37721 __IO uint32_t LPCR;
37722 __IO uint32_t LPMKCR;
37723 __IO uint32_t LPSVCR;
37724 uint8_t RESERVED_0[4];
37725 __IO uint32_t LPTDCR;
37726 __IO uint32_t LPSR;
37727 __IO uint32_t LPSRTCMR;
37728 __IO uint32_t LPSRTCLR;
37729 __IO uint32_t LPTAR;
37730 __I uint32_t LPSMCMR;
37731 __I uint32_t LPSMCLR;
37732 __IO uint32_t LPPGDR;
37733 __IO uint32_t LPGPR0_LEGACY_ALIAS;
37734 __IO uint32_t LPZMKR[8];
37735 uint8_t RESERVED_1[4];
37736 __IO uint32_t LPGPR_ALIAS[4];
37737 uint8_t RESERVED_2[96];
37738 __IO uint32_t LPGPR[8];
37739 uint8_t RESERVED_3[2776];
37740 __I uint32_t HPVIDR1;
37741 __I uint32_t HPVIDR2;
37742 } SNVS_Type;
37743
37744 /* ----------------------------------------------------------------------------
37745 -- SNVS Register Masks
37746 ---------------------------------------------------------------------------- */
37747
37755 #define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
37756 #define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
37757
37761 #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
37762 #define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
37763 #define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
37764
37768 #define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
37769 #define SNVS_HPLR_SRTC_SL_MASK (0x4U)
37770 #define SNVS_HPLR_SRTC_SL_SHIFT (2U)
37771
37775 #define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
37776 #define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
37777 #define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
37778
37782 #define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
37783 #define SNVS_HPLR_MC_SL_MASK (0x10U)
37784 #define SNVS_HPLR_MC_SL_SHIFT (4U)
37785
37789 #define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
37790 #define SNVS_HPLR_GPR_SL_MASK (0x20U)
37791 #define SNVS_HPLR_GPR_SL_SHIFT (5U)
37792
37796 #define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
37797 #define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
37798 #define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
37799
37803 #define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
37804 #define SNVS_HPLR_LPTDCR_SL_MASK (0x100U)
37805 #define SNVS_HPLR_LPTDCR_SL_SHIFT (8U)
37806
37810 #define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)
37811 #define SNVS_HPLR_MKS_SL_MASK (0x200U)
37812 #define SNVS_HPLR_MKS_SL_SHIFT (9U)
37813
37817 #define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
37818 #define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
37819 #define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
37820
37824 #define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
37825 #define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
37826 #define SNVS_HPLR_HPSICR_L_SHIFT (17U)
37827
37831 #define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
37832 #define SNVS_HPLR_HAC_L_MASK (0x40000U)
37833 #define SNVS_HPLR_HAC_L_SHIFT (18U)
37834
37838 #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
37839
37843 #define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
37844 #define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
37845 #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
37846 #define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
37847 #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
37848
37852 #define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
37853 #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
37854 #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
37855
37859 #define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
37860 #define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
37861 #define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
37862
37866 #define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
37867 #define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
37868 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
37869
37873 #define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
37874 #define SNVS_HPCOMR_SW_SV_MASK (0x100U)
37875 #define SNVS_HPCOMR_SW_SV_SHIFT (8U)
37876 #define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
37877 #define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
37878 #define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
37879 #define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
37880 #define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
37881 #define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
37882 #define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
37883 #define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
37884 #define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
37885
37889 #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
37890 #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
37891 #define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
37892
37896 #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
37897 #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
37898 #define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
37899
37903 #define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
37904 #define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
37905 #define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
37906
37910 #define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
37911 #define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
37912 #define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
37913
37917 #define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
37918 #define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
37919 #define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
37920 #define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
37921 #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
37922 #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
37923 #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
37924
37928 #define SNVS_HPCR_RTC_EN_MASK (0x1U)
37929 #define SNVS_HPCR_RTC_EN_SHIFT (0U)
37930
37934 #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
37935 #define SNVS_HPCR_HPTA_EN_MASK (0x2U)
37936 #define SNVS_HPCR_HPTA_EN_SHIFT (1U)
37937
37941 #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
37942 #define SNVS_HPCR_DIS_PI_MASK (0x4U)
37943 #define SNVS_HPCR_DIS_PI_SHIFT (2U)
37944
37948 #define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
37949 #define SNVS_HPCR_PI_EN_MASK (0x8U)
37950 #define SNVS_HPCR_PI_EN_SHIFT (3U)
37951
37955 #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
37956 #define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
37957 #define SNVS_HPCR_PI_FREQ_SHIFT (4U)
37958
37976 #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
37977 #define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
37978 #define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
37979
37983 #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
37984 #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
37985 #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
37986
37996 #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
37997 #define SNVS_HPCR_HP_TS_MASK (0x10000U)
37998 #define SNVS_HPCR_HP_TS_SHIFT (16U)
37999
38003 #define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
38004 #define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
38005 #define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
38006 #define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
38007 #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
38008 #define SNVS_HPCR_BTN_MASK_SHIFT (27U)
38009 #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
38010
38014 #define SNVS_HPSICR_SV0_EN_MASK (0x1U)
38015 #define SNVS_HPSICR_SV0_EN_SHIFT (0U)
38016
38020 #define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
38021 #define SNVS_HPSICR_SV1_EN_MASK (0x2U)
38022 #define SNVS_HPSICR_SV1_EN_SHIFT (1U)
38023
38027 #define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
38028 #define SNVS_HPSICR_SV2_EN_MASK (0x4U)
38029 #define SNVS_HPSICR_SV2_EN_SHIFT (2U)
38030
38034 #define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
38035 #define SNVS_HPSICR_SV3_EN_MASK (0x8U)
38036 #define SNVS_HPSICR_SV3_EN_SHIFT (3U)
38037
38041 #define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
38042 #define SNVS_HPSICR_SV4_EN_MASK (0x10U)
38043 #define SNVS_HPSICR_SV4_EN_SHIFT (4U)
38044
38048 #define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
38049 #define SNVS_HPSICR_SV5_EN_MASK (0x20U)
38050 #define SNVS_HPSICR_SV5_EN_SHIFT (5U)
38051
38055 #define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
38056 #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
38057 #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
38058
38062 #define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
38063
38067 #define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
38068 #define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
38069
38073 #define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
38074 #define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
38075 #define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
38076
38080 #define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
38081 #define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
38082 #define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
38083
38087 #define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
38088 #define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
38089 #define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
38090
38094 #define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
38095 #define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
38096 #define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
38097
38101 #define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
38102 #define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
38103 #define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
38104
38109 #define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
38110 #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
38111 #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
38112
38117 #define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
38118
38122 #define SNVS_HPSR_HPTA_MASK (0x1U)
38123 #define SNVS_HPSR_HPTA_SHIFT (0U)
38124
38128 #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
38129 #define SNVS_HPSR_PI_MASK (0x2U)
38130 #define SNVS_HPSR_PI_SHIFT (1U)
38131
38135 #define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
38136 #define SNVS_HPSR_LPDIS_MASK (0x10U)
38137 #define SNVS_HPSR_LPDIS_SHIFT (4U)
38138 #define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
38139 #define SNVS_HPSR_BTN_MASK (0x40U)
38140 #define SNVS_HPSR_BTN_SHIFT (6U)
38141 #define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
38142 #define SNVS_HPSR_BI_MASK (0x80U)
38143 #define SNVS_HPSR_BI_SHIFT (7U)
38144 #define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
38145 #define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
38146 #define SNVS_HPSR_SSM_STATE_SHIFT (8U)
38147
38157 #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
38158 #define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)
38159 #define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)
38160
38166 #define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)
38167 #define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
38168 #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
38169 #define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
38170 #define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
38171 #define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
38172
38176 #define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
38177 #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
38178 #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
38179
38183 #define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
38184
38188 #define SNVS_HPSVSR_SV0_MASK (0x1U)
38189 #define SNVS_HPSVSR_SV0_SHIFT (0U)
38190
38194 #define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
38195 #define SNVS_HPSVSR_SV1_MASK (0x2U)
38196 #define SNVS_HPSVSR_SV1_SHIFT (1U)
38197
38201 #define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
38202 #define SNVS_HPSVSR_SV2_MASK (0x4U)
38203 #define SNVS_HPSVSR_SV2_SHIFT (2U)
38204
38208 #define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
38209 #define SNVS_HPSVSR_SV3_MASK (0x8U)
38210 #define SNVS_HPSVSR_SV3_SHIFT (3U)
38211
38215 #define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
38216 #define SNVS_HPSVSR_SV4_MASK (0x10U)
38217 #define SNVS_HPSVSR_SV4_SHIFT (4U)
38218
38222 #define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
38223 #define SNVS_HPSVSR_SV5_MASK (0x20U)
38224 #define SNVS_HPSVSR_SV5_SHIFT (5U)
38225
38229 #define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
38230 #define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
38231 #define SNVS_HPSVSR_SW_SV_SHIFT (13U)
38232 #define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
38233 #define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
38234 #define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
38235 #define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
38236 #define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
38237 #define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
38238 #define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
38239 #define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
38240 #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
38241 #define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
38242 #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
38243 #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
38244
38248 #define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
38249 #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
38250 #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
38251 #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
38252
38256 #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
38257 #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
38258 #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
38259
38263 #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
38264 #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
38265 #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
38266
38270 #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
38271 #define SNVS_HPRTCMR_RTC_SHIFT (0U)
38272 #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
38273
38277 #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
38278 #define SNVS_HPRTCLR_RTC_SHIFT (0U)
38279 #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
38280
38284 #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
38285 #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
38286 #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
38287
38291 #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
38292 #define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
38293 #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
38294
38298 #define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
38299 #define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
38300
38304 #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
38305 #define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
38306 #define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
38307
38311 #define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
38312 #define SNVS_LPLR_SRTC_HL_MASK (0x4U)
38313 #define SNVS_LPLR_SRTC_HL_SHIFT (2U)
38314
38318 #define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
38319 #define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
38320 #define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
38321
38325 #define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
38326 #define SNVS_LPLR_MC_HL_MASK (0x10U)
38327 #define SNVS_LPLR_MC_HL_SHIFT (4U)
38328
38332 #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
38333 #define SNVS_LPLR_GPR_HL_MASK (0x20U)
38334 #define SNVS_LPLR_GPR_HL_SHIFT (5U)
38335
38339 #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
38340 #define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
38341 #define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
38342
38346 #define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
38347 #define SNVS_LPLR_LPTDCR_HL_MASK (0x100U)
38348 #define SNVS_LPLR_LPTDCR_HL_SHIFT (8U)
38349
38353 #define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)
38354 #define SNVS_LPLR_MKS_HL_MASK (0x200U)
38355 #define SNVS_LPLR_MKS_HL_SHIFT (9U)
38356
38360 #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
38361
38365 #define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
38366 #define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
38367
38371 #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
38372 #define SNVS_LPCR_LPTA_EN_MASK (0x2U)
38373 #define SNVS_LPCR_LPTA_EN_SHIFT (1U)
38374
38378 #define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
38379 #define SNVS_LPCR_MC_ENV_MASK (0x4U)
38380 #define SNVS_LPCR_MC_ENV_SHIFT (2U)
38381
38385 #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
38386 #define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
38387 #define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
38388 #define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
38389 #define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
38390 #define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
38391
38395 #define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
38396 #define SNVS_LPCR_DP_EN_MASK (0x20U)
38397 #define SNVS_LPCR_DP_EN_SHIFT (5U)
38398
38402 #define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
38403 #define SNVS_LPCR_TOP_MASK (0x40U)
38404 #define SNVS_LPCR_TOP_SHIFT (6U)
38405
38409 #define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
38410 #define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)
38411 #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)
38412 #define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
38413 #define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
38414 #define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
38415
38419 #define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
38420 #define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
38421 #define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
38422
38432 #define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
38433 #define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
38434 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
38435 #define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
38436 #define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
38437 #define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
38438 #define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
38439 #define SNVS_LPCR_ON_TIME_MASK (0x300000U)
38440 #define SNVS_LPCR_ON_TIME_SHIFT (20U)
38441 #define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
38442 #define SNVS_LPCR_PK_EN_MASK (0x400000U)
38443 #define SNVS_LPCR_PK_EN_SHIFT (22U)
38444 #define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
38445 #define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
38446 #define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
38447 #define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
38448 #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
38449 #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
38450 #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
38451
38455 #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
38456 #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
38457
38462 #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
38463 #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
38464 #define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
38465
38469 #define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
38470 #define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
38471 #define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
38472
38476 #define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
38477 #define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
38478 #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
38479
38483 #define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
38484 #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
38485 #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
38486 #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
38487
38491 #define SNVS_LPSVCR_SV0_EN_MASK (0x1U)
38492 #define SNVS_LPSVCR_SV0_EN_SHIFT (0U)
38493
38497 #define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
38498 #define SNVS_LPSVCR_SV1_EN_MASK (0x2U)
38499 #define SNVS_LPSVCR_SV1_EN_SHIFT (1U)
38500
38504 #define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
38505 #define SNVS_LPSVCR_SV2_EN_MASK (0x4U)
38506 #define SNVS_LPSVCR_SV2_EN_SHIFT (2U)
38507
38511 #define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
38512 #define SNVS_LPSVCR_SV3_EN_MASK (0x8U)
38513 #define SNVS_LPSVCR_SV3_EN_SHIFT (3U)
38514
38518 #define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
38519 #define SNVS_LPSVCR_SV4_EN_MASK (0x10U)
38520 #define SNVS_LPSVCR_SV4_EN_SHIFT (4U)
38521
38525 #define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
38526 #define SNVS_LPSVCR_SV5_EN_MASK (0x20U)
38527 #define SNVS_LPSVCR_SV5_EN_SHIFT (5U)
38528
38532 #define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
38533
38537 #define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
38538 #define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
38539
38543 #define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
38544 #define SNVS_LPTDCR_MCR_EN_MASK (0x4U)
38545 #define SNVS_LPTDCR_MCR_EN_SHIFT (2U)
38546
38550 #define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
38551 #define SNVS_LPTDCR_ET1_EN_MASK (0x200U)
38552 #define SNVS_LPTDCR_ET1_EN_SHIFT (9U)
38553
38557 #define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
38558 #define SNVS_LPTDCR_ET1P_MASK (0x800U)
38559 #define SNVS_LPTDCR_ET1P_SHIFT (11U)
38560
38564 #define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
38565 #define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
38566 #define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
38567 #define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
38568 #define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
38569 #define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
38570 #define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
38571 #define SNVS_LPTDCR_OSCB_MASK (0x10000000U)
38572 #define SNVS_LPTDCR_OSCB_SHIFT (28U)
38573
38577 #define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
38578
38582 #define SNVS_LPSR_LPTA_MASK (0x1U)
38583 #define SNVS_LPSR_LPTA_SHIFT (0U)
38584
38588 #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
38589 #define SNVS_LPSR_SRTCR_MASK (0x2U)
38590 #define SNVS_LPSR_SRTCR_SHIFT (1U)
38591
38595 #define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
38596 #define SNVS_LPSR_MCR_MASK (0x4U)
38597 #define SNVS_LPSR_MCR_SHIFT (2U)
38598
38602 #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
38603 #define SNVS_LPSR_PGD_MASK (0x8U)
38604 #define SNVS_LPSR_PGD_SHIFT (3U)
38605 #define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
38606 #define SNVS_LPSR_ET1D_MASK (0x200U)
38607 #define SNVS_LPSR_ET1D_SHIFT (9U)
38608
38612 #define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
38613 #define SNVS_LPSR_ESVD_MASK (0x10000U)
38614 #define SNVS_LPSR_ESVD_SHIFT (16U)
38615
38619 #define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
38620 #define SNVS_LPSR_EO_MASK (0x20000U)
38621 #define SNVS_LPSR_EO_SHIFT (17U)
38622
38626 #define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
38627 #define SNVS_LPSR_SPO_MASK (0x40000U)
38628 #define SNVS_LPSR_SPO_SHIFT (18U)
38629
38633 #define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)
38634 #define SNVS_LPSR_SED_MASK (0x100000U)
38635 #define SNVS_LPSR_SED_SHIFT (20U)
38636
38640 #define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)
38641 #define SNVS_LPSR_LPNS_MASK (0x40000000U)
38642 #define SNVS_LPSR_LPNS_SHIFT (30U)
38643
38647 #define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
38648 #define SNVS_LPSR_LPS_MASK (0x80000000U)
38649 #define SNVS_LPSR_LPS_SHIFT (31U)
38650
38654 #define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
38655
38659 #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
38660 #define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
38661 #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
38662
38666 #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
38667 #define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
38668 #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
38669
38673 #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
38674 #define SNVS_LPTAR_LPTA_SHIFT (0U)
38675 #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
38676
38680 #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
38681 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
38682 #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
38683 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
38684 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
38685 #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
38686
38690 #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
38691 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
38692 #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
38693
38697 #define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
38698 #define SNVS_LPPGDR_PGD_SHIFT (0U)
38699 #define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
38700
38704 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
38705 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
38706 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
38707
38711 #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
38712 #define SNVS_LPZMKR_ZMK_SHIFT (0U)
38713 #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
38714
38716 /* The count of SNVS_LPZMKR */
38717 #define SNVS_LPZMKR_COUNT (8U)
38718
38721 #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
38722 #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
38723 #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
38724
38726 /* The count of SNVS_LPGPR_ALIAS */
38727 #define SNVS_LPGPR_ALIAS_COUNT (4U)
38728
38731 #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
38732 #define SNVS_LPGPR_GPR_SHIFT (0U)
38733 #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
38734
38736 /* The count of SNVS_LPGPR */
38737 #define SNVS_LPGPR_COUNT (8U)
38738
38741 #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
38742 #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
38743 #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
38744 #define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
38745 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
38746 #define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
38747 #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
38748 #define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
38749 #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
38750
38754 #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
38755 #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
38756 #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
38757 #define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
38758 #define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
38759 #define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
38760 #define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
38761 #define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
38762 #define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
38763 #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
38764 #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
38765 #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
38766 /* end of group SNVS_Register_Masks */
38772
38773
38774 /* SNVS - Peripheral instance base addresses */
38776 #define SNVS_BASE (0x400D4000u)
38777
38778 #define SNVS ((SNVS_Type *)SNVS_BASE)
38779
38780 #define SNVS_BASE_ADDRS { SNVS_BASE }
38781
38782 #define SNVS_BASE_PTRS { SNVS }
38783
38784 #define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }
38785 #define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }
38786 #define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }
38787 /* end of group SNVS_Peripheral_Access_Layer */
38791
38792
38793 /* ----------------------------------------------------------------------------
38794 -- SPDIF Peripheral Access Layer
38795 ---------------------------------------------------------------------------- */
38796
38803 typedef struct {
38804 __IO uint32_t SCR;
38805 __IO uint32_t SRCD;
38806 __IO uint32_t SRPC;
38807 __IO uint32_t SIE;
38808 union { /* offset: 0x10 */
38809 __O uint32_t SIC;
38810 __I uint32_t SIS;
38811 };
38812 __I uint32_t SRL;
38813 __I uint32_t SRR;
38814 __I uint32_t SRCSH;
38815 __I uint32_t SRCSL;
38816 __I uint32_t SRU;
38817 __I uint32_t SRQ;
38818 __O uint32_t STL;
38819 __O uint32_t STR;
38820 __IO uint32_t STCSCH;
38821 __IO uint32_t STCSCL;
38822 uint8_t RESERVED_0[8];
38823 __I uint32_t SRFM;
38824 uint8_t RESERVED_1[8];
38825 __IO uint32_t STC;
38826 } SPDIF_Type;
38827
38828 /* ----------------------------------------------------------------------------
38829 -- SPDIF Register Masks
38830 ---------------------------------------------------------------------------- */
38831
38839 #define SPDIF_SCR_USRC_SEL_MASK (0x3U)
38840 #define SPDIF_SCR_USRC_SEL_SHIFT (0U)
38841
38847 #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
38848 #define SPDIF_SCR_TXSEL_MASK (0x1CU)
38849 #define SPDIF_SCR_TXSEL_SHIFT (2U)
38850
38855 #define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
38856 #define SPDIF_SCR_VALCTRL_MASK (0x20U)
38857 #define SPDIF_SCR_VALCTRL_SHIFT (5U)
38858
38862 #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
38863 #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
38864 #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
38865 #define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
38866 #define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
38867 #define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
38868 #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
38869 #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
38870 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
38871
38877 #define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
38878 #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
38879 #define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
38880 #define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
38881 #define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
38882 #define SPDIF_SCR_LOW_POWER_SHIFT (13U)
38883 #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
38884 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
38885 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
38886
38892 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
38893 #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
38894 #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
38895
38899 #define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
38900 #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
38901 #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
38902
38906 #define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
38907 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
38908 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
38909
38915 #define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
38916 #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
38917 #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
38918
38922 #define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
38923 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
38924 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
38925
38929 #define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
38930 #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
38931 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
38932
38936 #define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
38937
38941 #define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
38942 #define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
38943
38947 #define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
38948
38952 #define SPDIF_SRPC_GAINSEL_MASK (0x38U)
38953 #define SPDIF_SRPC_GAINSEL_SHIFT (3U)
38954
38963 #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
38964 #define SPDIF_SRPC_LOCK_MASK (0x40U)
38965 #define SPDIF_SRPC_LOCK_SHIFT (6U)
38966 #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
38967 #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
38968 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
38969
38977 #define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
38978
38982 #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
38983 #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
38984 #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
38985 #define SPDIF_SIE_TXEM_MASK (0x2U)
38986 #define SPDIF_SIE_TXEM_SHIFT (1U)
38987 #define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
38988 #define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
38989 #define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
38990 #define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
38991 #define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
38992 #define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
38993 #define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
38994 #define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
38995 #define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
38996 #define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
38997 #define SPDIF_SIE_UQERR_MASK (0x20U)
38998 #define SPDIF_SIE_UQERR_SHIFT (5U)
38999 #define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
39000 #define SPDIF_SIE_UQSYNC_MASK (0x40U)
39001 #define SPDIF_SIE_UQSYNC_SHIFT (6U)
39002 #define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
39003 #define SPDIF_SIE_QRXOV_MASK (0x80U)
39004 #define SPDIF_SIE_QRXOV_SHIFT (7U)
39005 #define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
39006 #define SPDIF_SIE_QRXFUL_MASK (0x100U)
39007 #define SPDIF_SIE_QRXFUL_SHIFT (8U)
39008 #define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
39009 #define SPDIF_SIE_URXOV_MASK (0x200U)
39010 #define SPDIF_SIE_URXOV_SHIFT (9U)
39011 #define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
39012 #define SPDIF_SIE_URXFUL_MASK (0x400U)
39013 #define SPDIF_SIE_URXFUL_SHIFT (10U)
39014 #define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
39015 #define SPDIF_SIE_BITERR_MASK (0x4000U)
39016 #define SPDIF_SIE_BITERR_SHIFT (14U)
39017 #define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
39018 #define SPDIF_SIE_SYMERR_MASK (0x8000U)
39019 #define SPDIF_SIE_SYMERR_SHIFT (15U)
39020 #define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
39021 #define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
39022 #define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
39023 #define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
39024 #define SPDIF_SIE_CNEW_MASK (0x20000U)
39025 #define SPDIF_SIE_CNEW_SHIFT (17U)
39026 #define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
39027 #define SPDIF_SIE_TXRESYN_MASK (0x40000U)
39028 #define SPDIF_SIE_TXRESYN_SHIFT (18U)
39029 #define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
39030 #define SPDIF_SIE_TXUNOV_MASK (0x80000U)
39031 #define SPDIF_SIE_TXUNOV_SHIFT (19U)
39032 #define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
39033 #define SPDIF_SIE_LOCK_MASK (0x100000U)
39034 #define SPDIF_SIE_LOCK_SHIFT (20U)
39035 #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
39036
39040 #define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
39041 #define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
39042 #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
39043 #define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
39044 #define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
39045 #define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
39046 #define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
39047 #define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
39048 #define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
39049 #define SPDIF_SIC_UQERR_MASK (0x20U)
39050 #define SPDIF_SIC_UQERR_SHIFT (5U)
39051 #define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
39052 #define SPDIF_SIC_UQSYNC_MASK (0x40U)
39053 #define SPDIF_SIC_UQSYNC_SHIFT (6U)
39054 #define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
39055 #define SPDIF_SIC_QRXOV_MASK (0x80U)
39056 #define SPDIF_SIC_QRXOV_SHIFT (7U)
39057 #define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
39058 #define SPDIF_SIC_URXOV_MASK (0x200U)
39059 #define SPDIF_SIC_URXOV_SHIFT (9U)
39060 #define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
39061 #define SPDIF_SIC_BITERR_MASK (0x4000U)
39062 #define SPDIF_SIC_BITERR_SHIFT (14U)
39063 #define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
39064 #define SPDIF_SIC_SYMERR_MASK (0x8000U)
39065 #define SPDIF_SIC_SYMERR_SHIFT (15U)
39066 #define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
39067 #define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
39068 #define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
39069 #define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
39070 #define SPDIF_SIC_CNEW_MASK (0x20000U)
39071 #define SPDIF_SIC_CNEW_SHIFT (17U)
39072 #define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
39073 #define SPDIF_SIC_TXRESYN_MASK (0x40000U)
39074 #define SPDIF_SIC_TXRESYN_SHIFT (18U)
39075 #define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
39076 #define SPDIF_SIC_TXUNOV_MASK (0x80000U)
39077 #define SPDIF_SIC_TXUNOV_SHIFT (19U)
39078 #define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
39079 #define SPDIF_SIC_LOCK_MASK (0x100000U)
39080 #define SPDIF_SIC_LOCK_SHIFT (20U)
39081 #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
39082
39086 #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
39087 #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
39088 #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
39089 #define SPDIF_SIS_TXEM_MASK (0x2U)
39090 #define SPDIF_SIS_TXEM_SHIFT (1U)
39091 #define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
39092 #define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
39093 #define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
39094 #define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
39095 #define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
39096 #define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
39097 #define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
39098 #define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
39099 #define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
39100 #define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
39101 #define SPDIF_SIS_UQERR_MASK (0x20U)
39102 #define SPDIF_SIS_UQERR_SHIFT (5U)
39103 #define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
39104 #define SPDIF_SIS_UQSYNC_MASK (0x40U)
39105 #define SPDIF_SIS_UQSYNC_SHIFT (6U)
39106 #define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
39107 #define SPDIF_SIS_QRXOV_MASK (0x80U)
39108 #define SPDIF_SIS_QRXOV_SHIFT (7U)
39109 #define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
39110 #define SPDIF_SIS_QRXFUL_MASK (0x100U)
39111 #define SPDIF_SIS_QRXFUL_SHIFT (8U)
39112 #define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
39113 #define SPDIF_SIS_URXOV_MASK (0x200U)
39114 #define SPDIF_SIS_URXOV_SHIFT (9U)
39115 #define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
39116 #define SPDIF_SIS_URXFUL_MASK (0x400U)
39117 #define SPDIF_SIS_URXFUL_SHIFT (10U)
39118 #define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
39119 #define SPDIF_SIS_BITERR_MASK (0x4000U)
39120 #define SPDIF_SIS_BITERR_SHIFT (14U)
39121 #define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
39122 #define SPDIF_SIS_SYMERR_MASK (0x8000U)
39123 #define SPDIF_SIS_SYMERR_SHIFT (15U)
39124 #define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
39125 #define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
39126 #define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
39127 #define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
39128 #define SPDIF_SIS_CNEW_MASK (0x20000U)
39129 #define SPDIF_SIS_CNEW_SHIFT (17U)
39130 #define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
39131 #define SPDIF_SIS_TXRESYN_MASK (0x40000U)
39132 #define SPDIF_SIS_TXRESYN_SHIFT (18U)
39133 #define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
39134 #define SPDIF_SIS_TXUNOV_MASK (0x80000U)
39135 #define SPDIF_SIS_TXUNOV_SHIFT (19U)
39136 #define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
39137 #define SPDIF_SIS_LOCK_MASK (0x100000U)
39138 #define SPDIF_SIS_LOCK_SHIFT (20U)
39139 #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
39140
39144 #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
39145 #define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
39146 #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
39147
39151 #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
39152 #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
39153 #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
39154
39158 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
39159 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
39160 #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
39161
39165 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
39166 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
39167 #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
39168
39172 #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
39173 #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
39174 #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
39175
39179 #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
39180 #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
39181 #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
39182
39186 #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
39187 #define SPDIF_STL_TXDATALEFT_SHIFT (0U)
39188 #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
39189
39193 #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
39194 #define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
39195 #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
39196
39200 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
39201 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
39202 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
39203
39207 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
39208 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
39209 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
39210
39214 #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
39215 #define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
39216 #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
39217
39221 #define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
39222 #define SPDIF_STC_TXCLK_DF_SHIFT (0U)
39223
39228 #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
39229 #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
39230 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
39231
39235 #define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
39236 #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
39237 #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
39238
39247 #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
39248 #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
39249 #define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
39250
39255 #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
39256 /* end of group SPDIF_Register_Masks */
39262
39263
39264 /* SPDIF - Peripheral instance base addresses */
39266 #define SPDIF_BASE (0x40380000u)
39267
39268 #define SPDIF ((SPDIF_Type *)SPDIF_BASE)
39269
39270 #define SPDIF_BASE_ADDRS { SPDIF_BASE }
39271
39272 #define SPDIF_BASE_PTRS { SPDIF }
39273
39274 #define SPDIF_IRQS { SPDIF_IRQn }
39275 /* end of group SPDIF_Peripheral_Access_Layer */
39279
39280
39281 /* ----------------------------------------------------------------------------
39282 -- SRC Peripheral Access Layer
39283 ---------------------------------------------------------------------------- */
39284
39291 typedef struct {
39292 __IO uint32_t SCR;
39293 __I uint32_t SBMR1;
39294 __IO uint32_t SRSR;
39295 uint8_t RESERVED_0[16];
39296 __I uint32_t SBMR2;
39297 __IO uint32_t GPR[10];
39298 } SRC_Type;
39299
39300 /* ----------------------------------------------------------------------------
39301 -- SRC Register Masks
39302 ---------------------------------------------------------------------------- */
39303
39311 #define SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
39312 #define SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
39313
39317 #define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
39318 #define SRC_SCR_CORE0_RST_MASK (0x2000U)
39319 #define SRC_SCR_CORE0_RST_SHIFT (13U)
39320
39324 #define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
39325 #define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
39326 #define SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
39327
39331 #define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
39332 #define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
39333 #define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
39334
39338 #define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
39339 #define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
39340 #define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
39341
39345 #define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
39346
39350 #define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
39351 #define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
39352 #define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
39353 #define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
39354 #define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
39355 #define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
39356 #define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
39357 #define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
39358 #define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
39359 #define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
39360 #define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
39361 #define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
39362
39366 #define SRC_SRSR_IPP_RESET_B_MASK (0x1U)
39367 #define SRC_SRSR_IPP_RESET_B_SHIFT (0U)
39368
39372 #define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
39373 #define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)
39374 #define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)
39375
39379 #define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
39380 #define SRC_SRSR_CSU_RESET_B_MASK (0x4U)
39381 #define SRC_SRSR_CSU_RESET_B_SHIFT (2U)
39382
39386 #define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
39387 #define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
39388 #define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
39389
39393 #define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
39394 #define SRC_SRSR_WDOG_RST_B_MASK (0x10U)
39395 #define SRC_SRSR_WDOG_RST_B_SHIFT (4U)
39396
39400 #define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
39401 #define SRC_SRSR_JTAG_RST_B_MASK (0x20U)
39402 #define SRC_SRSR_JTAG_RST_B_SHIFT (5U)
39403
39407 #define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
39408 #define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
39409 #define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
39410
39414 #define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
39415 #define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
39416 #define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
39417
39421 #define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
39422 #define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
39423 #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
39424
39428 #define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
39429
39433 #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
39434 #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
39435 #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
39436 #define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
39437 #define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
39438 #define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
39439 #define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
39440 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
39441 #define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
39442 #define SRC_SBMR2_BMOD_MASK (0x3000000U)
39443 #define SRC_SBMR2_BMOD_SHIFT (24U)
39444 #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
39445
39449 #define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
39450 #define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
39451 #define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
39452 #define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
39453 #define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
39454 #define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
39455
39457 /* The count of SRC_GPR */
39458 #define SRC_GPR_COUNT (10U)
39459
39460 /* end of group SRC_Register_Masks */
39464
39465
39466 /* SRC - Peripheral instance base addresses */
39468 #define SRC_BASE (0x400F8000u)
39469
39470 #define SRC ((SRC_Type *)SRC_BASE)
39471
39472 #define SRC_BASE_ADDRS { SRC_BASE }
39473
39474 #define SRC_BASE_PTRS { SRC }
39475
39476 #define SRC_IRQS { SRC_IRQn }
39477 /* Backward compatibility */
39478 #define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK
39479 #define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT
39480 #define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)
39481 #define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK
39482 #define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT
39483 #define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)
39484 #define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK
39485 #define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT
39486 #define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)
39487 #define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK
39488 #define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT
39489 #define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)
39490 #define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK
39491 #define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT
39492 #define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)
39493 /* Extra definition */
39494 #define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \
39495 | SRC_SRSR_JTAG_SW_RST_MASK \
39496 | SRC_SRSR_JTAG_RST_B_MASK \
39497 | SRC_SRSR_WDOG_RST_B_MASK \
39498 | SRC_SRSR_IPP_USER_RESET_B_MASK \
39499 | SRC_SRSR_CSU_RESET_B_MASK \
39500 | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \
39501 | SRC_SRSR_IPP_RESET_B_MASK)
39502
39503 /* end of group SRC_Peripheral_Access_Layer */
39507
39508
39509 /* ----------------------------------------------------------------------------
39510 -- TEMPMON Peripheral Access Layer
39511 ---------------------------------------------------------------------------- */
39512
39519 typedef struct {
39520 uint8_t RESERVED_0[384];
39521 __IO uint32_t TEMPSENSE0;
39522 __IO uint32_t TEMPSENSE0_SET;
39523 __IO uint32_t TEMPSENSE0_CLR;
39524 __IO uint32_t TEMPSENSE0_TOG;
39525 __IO uint32_t TEMPSENSE1;
39526 __IO uint32_t TEMPSENSE1_SET;
39527 __IO uint32_t TEMPSENSE1_CLR;
39528 __IO uint32_t TEMPSENSE1_TOG;
39529 uint8_t RESERVED_1[240];
39530 __IO uint32_t TEMPSENSE2;
39531 __IO uint32_t TEMPSENSE2_SET;
39532 __IO uint32_t TEMPSENSE2_CLR;
39533 __IO uint32_t TEMPSENSE2_TOG;
39534 } TEMPMON_Type;
39535
39536 /* ----------------------------------------------------------------------------
39537 -- TEMPMON Register Masks
39538 ---------------------------------------------------------------------------- */
39539
39547 #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)
39548 #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)
39549
39553 #define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
39554 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)
39555 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)
39556
39560 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
39561 #define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)
39562 #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)
39563
39567 #define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
39568 #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)
39569 #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)
39570 #define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
39571 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)
39572 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)
39573 #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
39574
39578 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)
39579 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)
39580
39584 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
39585 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
39586 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
39587
39591 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
39592 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)
39593 #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)
39594
39598 #define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
39599 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)
39600 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)
39601 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
39602 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)
39603 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
39604 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
39605
39609 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)
39610 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)
39611
39615 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
39616 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
39617 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
39618
39622 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
39623 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)
39624 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)
39625
39629 #define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
39630 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)
39631 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)
39632 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
39633 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)
39634 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
39635 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
39636
39640 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)
39641 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)
39642
39646 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
39647 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
39648 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
39649
39653 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
39654 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)
39655 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)
39656
39660 #define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
39661 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)
39662 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)
39663 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
39664 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)
39665 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
39666 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
39667
39671 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)
39672 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)
39673 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
39674
39678 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
39679 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
39680 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
39681
39685 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
39686 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
39687 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
39688
39692 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
39693 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
39694 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
39695
39699 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)
39700 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
39701 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
39702 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
39703 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
39704 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
39705
39709 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
39710 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
39711 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
39712 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
39713 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
39714 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
39715
39719 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
39720 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
39721 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
39722 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
39723 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
39724 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
39725
39729 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
39730 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
39731 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
39732 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
39733 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
39734 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)
39735 /* end of group TEMPMON_Register_Masks */
39741
39742
39743 /* TEMPMON - Peripheral instance base addresses */
39745 #define TEMPMON_BASE (0x400D8000u)
39746
39747 #define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)
39748
39749 #define TEMPMON_BASE_ADDRS { TEMPMON_BASE }
39750
39751 #define TEMPMON_BASE_PTRS { TEMPMON }
39752 /* end of group TEMPMON_Peripheral_Access_Layer */
39756
39757
39758 /* ----------------------------------------------------------------------------
39759 -- TMR Peripheral Access Layer
39760 ---------------------------------------------------------------------------- */
39761
39768 typedef struct {
39769 struct { /* offset: 0x0, array step: 0x20 */
39770 __IO uint16_t COMP1;
39771 __IO uint16_t COMP2;
39772 __IO uint16_t CAPT;
39773 __IO uint16_t LOAD;
39774 __IO uint16_t HOLD;
39775 __IO uint16_t CNTR;
39776 __IO uint16_t CTRL;
39777 __IO uint16_t SCTRL;
39778 __IO uint16_t CMPLD1;
39779 __IO uint16_t CMPLD2;
39780 __IO uint16_t CSCTRL;
39781 __IO uint16_t FILT;
39782 __IO uint16_t DMA;
39783 uint8_t RESERVED_0[4];
39784 __IO uint16_t ENBL;
39785 } CHANNEL[4];
39786 } TMR_Type;
39787
39788 /* ----------------------------------------------------------------------------
39789 -- TMR Register Masks
39790 ---------------------------------------------------------------------------- */
39791
39799 #define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
39800 #define TMR_COMP1_COMPARISON_1_SHIFT (0U)
39801
39803 #define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
39804
39806 /* The count of TMR_COMP1 */
39807 #define TMR_COMP1_COUNT (4U)
39808
39811 #define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
39812 #define TMR_COMP2_COMPARISON_2_SHIFT (0U)
39813
39815 #define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
39816
39818 /* The count of TMR_COMP2 */
39819 #define TMR_COMP2_COUNT (4U)
39820
39823 #define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
39824 #define TMR_CAPT_CAPTURE_SHIFT (0U)
39825
39827 #define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
39828
39830 /* The count of TMR_CAPT */
39831 #define TMR_CAPT_COUNT (4U)
39832
39835 #define TMR_LOAD_LOAD_MASK (0xFFFFU)
39836 #define TMR_LOAD_LOAD_SHIFT (0U)
39837
39839 #define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
39840
39842 /* The count of TMR_LOAD */
39843 #define TMR_LOAD_COUNT (4U)
39844
39847 #define TMR_HOLD_HOLD_MASK (0xFFFFU)
39848 #define TMR_HOLD_HOLD_SHIFT (0U)
39849 #define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
39850
39852 /* The count of TMR_HOLD */
39853 #define TMR_HOLD_COUNT (4U)
39854
39857 #define TMR_CNTR_COUNTER_MASK (0xFFFFU)
39858 #define TMR_CNTR_COUNTER_SHIFT (0U)
39859 #define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
39860
39862 /* The count of TMR_CNTR */
39863 #define TMR_CNTR_COUNT (4U)
39864
39867 #define TMR_CTRL_OUTMODE_MASK (0x7U)
39868 #define TMR_CTRL_OUTMODE_SHIFT (0U)
39869
39879 #define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
39880 #define TMR_CTRL_COINIT_MASK (0x8U)
39881 #define TMR_CTRL_COINIT_SHIFT (3U)
39882
39886 #define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
39887 #define TMR_CTRL_DIR_MASK (0x10U)
39888 #define TMR_CTRL_DIR_SHIFT (4U)
39889
39893 #define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
39894 #define TMR_CTRL_LENGTH_MASK (0x20U)
39895 #define TMR_CTRL_LENGTH_SHIFT (5U)
39896
39904 #define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
39905 #define TMR_CTRL_ONCE_MASK (0x40U)
39906 #define TMR_CTRL_ONCE_SHIFT (6U)
39907
39914 #define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
39915 #define TMR_CTRL_SCS_MASK (0x180U)
39916 #define TMR_CTRL_SCS_SHIFT (7U)
39917
39923 #define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
39924 #define TMR_CTRL_PCS_MASK (0x1E00U)
39925 #define TMR_CTRL_PCS_SHIFT (9U)
39926
39944 #define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
39945 #define TMR_CTRL_CM_MASK (0xE000U)
39946 #define TMR_CTRL_CM_SHIFT (13U)
39947
39960 #define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
39961
39963 /* The count of TMR_CTRL */
39964 #define TMR_CTRL_COUNT (4U)
39965
39968 #define TMR_SCTRL_OEN_MASK (0x1U)
39969 #define TMR_SCTRL_OEN_SHIFT (0U)
39970
39975 #define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
39976 #define TMR_SCTRL_OPS_MASK (0x2U)
39977 #define TMR_SCTRL_OPS_SHIFT (1U)
39978
39982 #define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
39983 #define TMR_SCTRL_FORCE_MASK (0x4U)
39984 #define TMR_SCTRL_FORCE_SHIFT (2U)
39985
39987 #define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
39988 #define TMR_SCTRL_VAL_MASK (0x8U)
39989 #define TMR_SCTRL_VAL_SHIFT (3U)
39990
39992 #define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
39993 #define TMR_SCTRL_EEOF_MASK (0x10U)
39994 #define TMR_SCTRL_EEOF_SHIFT (4U)
39995
39997 #define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
39998 #define TMR_SCTRL_MSTR_MASK (0x20U)
39999 #define TMR_SCTRL_MSTR_SHIFT (5U)
40000
40002 #define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
40003 #define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
40004 #define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
40005
40011 #define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
40012 #define TMR_SCTRL_INPUT_MASK (0x100U)
40013 #define TMR_SCTRL_INPUT_SHIFT (8U)
40014
40016 #define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
40017 #define TMR_SCTRL_IPS_MASK (0x200U)
40018 #define TMR_SCTRL_IPS_SHIFT (9U)
40019
40021 #define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
40022 #define TMR_SCTRL_IEFIE_MASK (0x400U)
40023 #define TMR_SCTRL_IEFIE_SHIFT (10U)
40024
40026 #define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
40027 #define TMR_SCTRL_IEF_MASK (0x800U)
40028 #define TMR_SCTRL_IEF_SHIFT (11U)
40029
40031 #define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
40032 #define TMR_SCTRL_TOFIE_MASK (0x1000U)
40033 #define TMR_SCTRL_TOFIE_SHIFT (12U)
40034
40036 #define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
40037 #define TMR_SCTRL_TOF_MASK (0x2000U)
40038 #define TMR_SCTRL_TOF_SHIFT (13U)
40039
40041 #define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
40042 #define TMR_SCTRL_TCFIE_MASK (0x4000U)
40043 #define TMR_SCTRL_TCFIE_SHIFT (14U)
40044
40046 #define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
40047 #define TMR_SCTRL_TCF_MASK (0x8000U)
40048 #define TMR_SCTRL_TCF_SHIFT (15U)
40049
40051 #define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
40052
40054 /* The count of TMR_SCTRL */
40055 #define TMR_SCTRL_COUNT (4U)
40056
40059 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
40060 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
40061 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
40062
40064 /* The count of TMR_CMPLD1 */
40065 #define TMR_CMPLD1_COUNT (4U)
40066
40069 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
40070 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
40071 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
40072
40074 /* The count of TMR_CMPLD2 */
40075 #define TMR_CMPLD2_COUNT (4U)
40076
40079 #define TMR_CSCTRL_CL1_MASK (0x3U)
40080 #define TMR_CSCTRL_CL1_SHIFT (0U)
40081
40087 #define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
40088 #define TMR_CSCTRL_CL2_MASK (0xCU)
40089 #define TMR_CSCTRL_CL2_SHIFT (2U)
40090
40096 #define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
40097 #define TMR_CSCTRL_TCF1_MASK (0x10U)
40098 #define TMR_CSCTRL_TCF1_SHIFT (4U)
40099
40101 #define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
40102 #define TMR_CSCTRL_TCF2_MASK (0x20U)
40103 #define TMR_CSCTRL_TCF2_SHIFT (5U)
40104
40106 #define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
40107 #define TMR_CSCTRL_TCF1EN_MASK (0x40U)
40108 #define TMR_CSCTRL_TCF1EN_SHIFT (6U)
40109
40111 #define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
40112 #define TMR_CSCTRL_TCF2EN_MASK (0x80U)
40113 #define TMR_CSCTRL_TCF2EN_SHIFT (7U)
40114
40116 #define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
40117 #define TMR_CSCTRL_UP_MASK (0x200U)
40118 #define TMR_CSCTRL_UP_SHIFT (9U)
40119
40123 #define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
40124 #define TMR_CSCTRL_TCI_MASK (0x400U)
40125 #define TMR_CSCTRL_TCI_SHIFT (10U)
40126
40130 #define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
40131 #define TMR_CSCTRL_ROC_MASK (0x800U)
40132 #define TMR_CSCTRL_ROC_SHIFT (11U)
40133
40137 #define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
40138 #define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
40139 #define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
40140
40144 #define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
40145 #define TMR_CSCTRL_FAULT_MASK (0x2000U)
40146 #define TMR_CSCTRL_FAULT_SHIFT (13U)
40147
40151 #define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
40152 #define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
40153 #define TMR_CSCTRL_DBG_EN_SHIFT (14U)
40154
40160 #define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
40161
40163 /* The count of TMR_CSCTRL */
40164 #define TMR_CSCTRL_COUNT (4U)
40165
40168 #define TMR_FILT_FILT_PER_MASK (0xFFU)
40169 #define TMR_FILT_FILT_PER_SHIFT (0U)
40170
40172 #define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
40173 #define TMR_FILT_FILT_CNT_MASK (0x700U)
40174 #define TMR_FILT_FILT_CNT_SHIFT (8U)
40175
40177 #define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
40178
40180 /* The count of TMR_FILT */
40181 #define TMR_FILT_COUNT (4U)
40182
40185 #define TMR_DMA_IEFDE_MASK (0x1U)
40186 #define TMR_DMA_IEFDE_SHIFT (0U)
40187
40189 #define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
40190 #define TMR_DMA_CMPLD1DE_MASK (0x2U)
40191 #define TMR_DMA_CMPLD1DE_SHIFT (1U)
40192
40194 #define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
40195 #define TMR_DMA_CMPLD2DE_MASK (0x4U)
40196 #define TMR_DMA_CMPLD2DE_SHIFT (2U)
40197
40199 #define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
40200
40202 /* The count of TMR_DMA */
40203 #define TMR_DMA_COUNT (4U)
40204
40207 #define TMR_ENBL_ENBL_MASK (0xFU)
40208 #define TMR_ENBL_ENBL_SHIFT (0U)
40209
40213 #define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
40214
40216 /* The count of TMR_ENBL */
40217 #define TMR_ENBL_COUNT (4U)
40218
40219 /* end of group TMR_Register_Masks */
40223
40224
40225 /* TMR - Peripheral instance base addresses */
40227 #define TMR1_BASE (0x401DC000u)
40228
40229 #define TMR1 ((TMR_Type *)TMR1_BASE)
40230
40231 #define TMR2_BASE (0x401E0000u)
40232
40233 #define TMR2 ((TMR_Type *)TMR2_BASE)
40234
40235 #define TMR3_BASE (0x401E4000u)
40236
40237 #define TMR3 ((TMR_Type *)TMR3_BASE)
40238
40239 #define TMR4_BASE (0x401E8000u)
40240
40241 #define TMR4 ((TMR_Type *)TMR4_BASE)
40242
40243 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
40244
40245 #define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
40246
40247 #define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
40248 /* end of group TMR_Peripheral_Access_Layer */
40252
40253
40254 /* ----------------------------------------------------------------------------
40255 -- TRNG Peripheral Access Layer
40256 ---------------------------------------------------------------------------- */
40257
40264 typedef struct {
40265 __IO uint32_t MCTL;
40266 __IO uint32_t SCMISC;
40267 __IO uint32_t PKRRNG;
40268 union { /* offset: 0xC */
40269 __IO uint32_t PKRMAX;
40270 __I uint32_t PKRSQ;
40271 };
40272 __IO uint32_t SDCTL;
40273 union { /* offset: 0x14 */
40274 __IO uint32_t SBLIM;
40275 __I uint32_t TOTSAM;
40276 };
40277 __IO uint32_t FRQMIN;
40278 union { /* offset: 0x1C */
40279 __I uint32_t FRQCNT;
40280 __IO uint32_t FRQMAX;
40281 };
40282 union { /* offset: 0x20 */
40283 __I uint32_t SCMC;
40284 __IO uint32_t SCML;
40285 };
40286 union { /* offset: 0x24 */
40287 __I uint32_t SCR1C;
40288 __IO uint32_t SCR1L;
40289 };
40290 union { /* offset: 0x28 */
40291 __I uint32_t SCR2C;
40292 __IO uint32_t SCR2L;
40293 };
40294 union { /* offset: 0x2C */
40295 __I uint32_t SCR3C;
40296 __IO uint32_t SCR3L;
40297 };
40298 union { /* offset: 0x30 */
40299 __I uint32_t SCR4C;
40300 __IO uint32_t SCR4L;
40301 };
40302 union { /* offset: 0x34 */
40303 __I uint32_t SCR5C;
40304 __IO uint32_t SCR5L;
40305 };
40306 union { /* offset: 0x38 */
40307 __I uint32_t SCR6PC;
40308 __IO uint32_t SCR6PL;
40309 };
40310 __I uint32_t STATUS;
40311 __I uint32_t ENT[16];
40312 __I uint32_t PKRCNT10;
40313 __I uint32_t PKRCNT32;
40314 __I uint32_t PKRCNT54;
40315 __I uint32_t PKRCNT76;
40316 __I uint32_t PKRCNT98;
40317 __I uint32_t PKRCNTBA;
40318 __I uint32_t PKRCNTDC;
40319 __I uint32_t PKRCNTFE;
40320 __IO uint32_t SEC_CFG;
40321 __IO uint32_t INT_CTRL;
40322 __IO uint32_t INT_MASK;
40323 __I uint32_t INT_STATUS;
40324 uint8_t RESERVED_0[64];
40325 __I uint32_t VID1;
40326 __I uint32_t VID2;
40327 } TRNG_Type;
40328
40329 /* ----------------------------------------------------------------------------
40330 -- TRNG Register Masks
40331 ---------------------------------------------------------------------------- */
40332
40340 #define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
40341 #define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
40342
40348 #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
40349 #define TRNG_MCTL_OSC_DIV_MASK (0xCU)
40350 #define TRNG_MCTL_OSC_DIV_SHIFT (2U)
40351
40357 #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
40358 #define TRNG_MCTL_UNUSED4_MASK (0x10U)
40359 #define TRNG_MCTL_UNUSED4_SHIFT (4U)
40360 #define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
40361 #define TRNG_MCTL_UNUSED5_MASK (0x20U)
40362 #define TRNG_MCTL_UNUSED5_SHIFT (5U)
40363 #define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
40364 #define TRNG_MCTL_RST_DEF_MASK (0x40U)
40365 #define TRNG_MCTL_RST_DEF_SHIFT (6U)
40366 #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
40367 #define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
40368 #define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
40369 #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
40370 #define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
40371 #define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
40372 #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
40373 #define TRNG_MCTL_FCT_VAL_MASK (0x200U)
40374 #define TRNG_MCTL_FCT_VAL_SHIFT (9U)
40375 #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
40376 #define TRNG_MCTL_ENT_VAL_MASK (0x400U)
40377 #define TRNG_MCTL_ENT_VAL_SHIFT (10U)
40378 #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
40379 #define TRNG_MCTL_TST_OUT_MASK (0x800U)
40380 #define TRNG_MCTL_TST_OUT_SHIFT (11U)
40381 #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
40382 #define TRNG_MCTL_ERR_MASK (0x1000U)
40383 #define TRNG_MCTL_ERR_SHIFT (12U)
40384 #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
40385 #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
40386 #define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
40387 #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
40388 #define TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
40389 #define TRNG_MCTL_LRUN_CONT_SHIFT (14U)
40390 #define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
40391 #define TRNG_MCTL_PRGM_MASK (0x10000U)
40392 #define TRNG_MCTL_PRGM_SHIFT (16U)
40393 #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
40394
40398 #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
40399 #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
40400 #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
40401 #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
40402 #define TRNG_SCMISC_RTY_CT_SHIFT (16U)
40403 #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
40404
40408 #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
40409 #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
40410 #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
40411
40415 #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
40416 #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
40417
40419 #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
40420
40424 #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
40425 #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
40426
40428 #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
40429
40433 #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
40434 #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
40435 #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
40436 #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
40437 #define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
40438 #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
40439
40443 #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
40444 #define TRNG_SBLIM_SB_LIM_SHIFT (0U)
40445 #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
40446
40450 #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
40451 #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
40452 #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
40453
40457 #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
40458 #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
40459 #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
40460
40464 #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
40465 #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
40466 #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
40467
40471 #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
40472 #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
40473 #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
40474
40478 #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
40479 #define TRNG_SCMC_MONO_CT_SHIFT (0U)
40480 #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
40481
40485 #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
40486 #define TRNG_SCML_MONO_MAX_SHIFT (0U)
40487 #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
40488 #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
40489 #define TRNG_SCML_MONO_RNG_SHIFT (16U)
40490 #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
40491
40495 #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
40496 #define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
40497 #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
40498 #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
40499 #define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
40500 #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
40501
40505 #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
40506 #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
40507 #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
40508 #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
40509 #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
40510 #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
40511
40515 #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
40516 #define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
40517 #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
40518 #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
40519 #define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
40520 #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
40521
40525 #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
40526 #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
40527 #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
40528 #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
40529 #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
40530 #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
40531
40535 #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
40536 #define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
40537 #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
40538 #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
40539 #define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
40540 #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
40541
40545 #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
40546 #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
40547 #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
40548 #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
40549 #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
40550 #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
40551
40555 #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
40556 #define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
40557 #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
40558 #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
40559 #define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
40560 #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
40561
40565 #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
40566 #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
40567 #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
40568 #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
40569 #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
40570 #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
40571
40575 #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
40576 #define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
40577 #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
40578 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
40579 #define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
40580 #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
40581
40585 #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
40586 #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
40587 #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
40588 #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
40589 #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
40590 #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
40591
40595 #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
40596 #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
40597 #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
40598 #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
40599 #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
40600 #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
40601
40605 #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
40606 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
40607 #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
40608 #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
40609 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
40610 #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
40611
40615 #define TRNG_STATUS_TF1BR0_MASK (0x1U)
40616 #define TRNG_STATUS_TF1BR0_SHIFT (0U)
40617 #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
40618 #define TRNG_STATUS_TF1BR1_MASK (0x2U)
40619 #define TRNG_STATUS_TF1BR1_SHIFT (1U)
40620 #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
40621 #define TRNG_STATUS_TF2BR0_MASK (0x4U)
40622 #define TRNG_STATUS_TF2BR0_SHIFT (2U)
40623 #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
40624 #define TRNG_STATUS_TF2BR1_MASK (0x8U)
40625 #define TRNG_STATUS_TF2BR1_SHIFT (3U)
40626 #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
40627 #define TRNG_STATUS_TF3BR0_MASK (0x10U)
40628 #define TRNG_STATUS_TF3BR0_SHIFT (4U)
40629 #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
40630 #define TRNG_STATUS_TF3BR1_MASK (0x20U)
40631 #define TRNG_STATUS_TF3BR1_SHIFT (5U)
40632 #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
40633 #define TRNG_STATUS_TF4BR0_MASK (0x40U)
40634 #define TRNG_STATUS_TF4BR0_SHIFT (6U)
40635 #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
40636 #define TRNG_STATUS_TF4BR1_MASK (0x80U)
40637 #define TRNG_STATUS_TF4BR1_SHIFT (7U)
40638 #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
40639 #define TRNG_STATUS_TF5BR0_MASK (0x100U)
40640 #define TRNG_STATUS_TF5BR0_SHIFT (8U)
40641 #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
40642 #define TRNG_STATUS_TF5BR1_MASK (0x200U)
40643 #define TRNG_STATUS_TF5BR1_SHIFT (9U)
40644 #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
40645 #define TRNG_STATUS_TF6PBR0_MASK (0x400U)
40646 #define TRNG_STATUS_TF6PBR0_SHIFT (10U)
40647 #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
40648 #define TRNG_STATUS_TF6PBR1_MASK (0x800U)
40649 #define TRNG_STATUS_TF6PBR1_SHIFT (11U)
40650 #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
40651 #define TRNG_STATUS_TFSB_MASK (0x1000U)
40652 #define TRNG_STATUS_TFSB_SHIFT (12U)
40653 #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
40654 #define TRNG_STATUS_TFLR_MASK (0x2000U)
40655 #define TRNG_STATUS_TFLR_SHIFT (13U)
40656 #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
40657 #define TRNG_STATUS_TFP_MASK (0x4000U)
40658 #define TRNG_STATUS_TFP_SHIFT (14U)
40659 #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
40660 #define TRNG_STATUS_TFMB_MASK (0x8000U)
40661 #define TRNG_STATUS_TFMB_SHIFT (15U)
40662 #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
40663 #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
40664 #define TRNG_STATUS_RETRY_CT_SHIFT (16U)
40665 #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
40666
40670 #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
40671 #define TRNG_ENT_ENT_SHIFT (0U)
40672 #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
40673
40675 /* The count of TRNG_ENT */
40676 #define TRNG_ENT_COUNT (16U)
40677
40680 #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
40681 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
40682 #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
40683 #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
40684 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
40685 #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
40686
40690 #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
40691 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
40692 #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
40693 #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
40694 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
40695 #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
40696
40700 #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
40701 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
40702 #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
40703 #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
40704 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
40705 #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
40706
40710 #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
40711 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
40712 #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
40713 #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
40714 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
40715 #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
40716
40720 #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
40721 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
40722 #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
40723 #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
40724 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
40725 #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
40726
40730 #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
40731 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
40732 #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
40733 #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
40734 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
40735 #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
40736
40740 #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
40741 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
40742 #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
40743 #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
40744 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
40745 #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
40746
40750 #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
40751 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
40752 #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
40753 #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
40754 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
40755 #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
40756
40760 #define TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
40761 #define TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
40762 #define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
40763 #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
40764 #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
40765
40769 #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
40770 #define TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
40771 #define TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
40772 #define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
40773
40777 #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
40778 #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
40779
40783 #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
40784 #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
40785 #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
40786
40790 #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
40791 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
40792 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
40793
40797 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
40798 #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
40799 #define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
40800 #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
40801
40805 #define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
40806 #define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
40807
40811 #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
40812 #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
40813 #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
40814
40818 #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
40819 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
40820 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
40821
40825 #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
40826
40830 #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
40831 #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
40832
40836 #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
40837 #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
40838 #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
40839
40843 #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
40844 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
40845 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
40846
40850 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
40851
40855 #define TRNG_VID1_MIN_REV_MASK (0xFFU)
40856 #define TRNG_VID1_MIN_REV_SHIFT (0U)
40857
40860 #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
40861 #define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
40862 #define TRNG_VID1_MAJ_REV_SHIFT (8U)
40863
40866 #define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
40867 #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
40868 #define TRNG_VID1_IP_ID_SHIFT (16U)
40869
40872 #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
40873
40877 #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
40878 #define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
40879
40882 #define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
40883 #define TRNG_VID2_ECO_REV_MASK (0xFF00U)
40884 #define TRNG_VID2_ECO_REV_SHIFT (8U)
40885
40888 #define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
40889 #define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
40890 #define TRNG_VID2_INTG_OPT_SHIFT (16U)
40891
40894 #define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
40895 #define TRNG_VID2_ERA_MASK (0xFF000000U)
40896 #define TRNG_VID2_ERA_SHIFT (24U)
40897
40900 #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
40901 /* end of group TRNG_Register_Masks */
40907
40908
40909 /* TRNG - Peripheral instance base addresses */
40911 #define TRNG_BASE (0x400CC000u)
40912
40913 #define TRNG ((TRNG_Type *)TRNG_BASE)
40914
40915 #define TRNG_BASE_ADDRS { TRNG_BASE }
40916
40917 #define TRNG_BASE_PTRS { TRNG }
40918
40919 #define TRNG_IRQS { TRNG_IRQn }
40920 /* end of group TRNG_Peripheral_Access_Layer */
40924
40925
40926 /* ----------------------------------------------------------------------------
40927 -- TSC Peripheral Access Layer
40928 ---------------------------------------------------------------------------- */
40929
40936 typedef struct {
40937 __IO uint32_t BASIC_SETTING;
40938 uint8_t RESERVED_0[12];
40939 __IO uint32_t PRE_CHARGE_TIME;
40940 uint8_t RESERVED_1[12];
40941 __IO uint32_t FLOW_CONTROL;
40942 uint8_t RESERVED_2[12];
40943 __I uint32_t MEASEURE_VALUE;
40944 uint8_t RESERVED_3[12];
40945 __IO uint32_t INT_EN;
40946 uint8_t RESERVED_4[12];
40947 __IO uint32_t INT_SIG_EN;
40948 uint8_t RESERVED_5[12];
40949 __IO uint32_t INT_STATUS;
40950 uint8_t RESERVED_6[12];
40951 __IO uint32_t DEBUG_MODE;
40952 uint8_t RESERVED_7[12];
40953 __IO uint32_t DEBUG_MODE2;
40954 } TSC_Type;
40955
40956 /* ----------------------------------------------------------------------------
40957 -- TSC Register Masks
40958 ---------------------------------------------------------------------------- */
40959
40967 #define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)
40968 #define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)
40969
40973 #define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
40974 #define TSC_BASIC_SETTING_WIRE_4_5_MASK (0x10U)
40975 #define TSC_BASIC_SETTING_WIRE_4_5_SHIFT (4U)
40976
40980 #define TSC_BASIC_SETTING_WIRE_4_5(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_WIRE_4_5_SHIFT)) & TSC_BASIC_SETTING_WIRE_4_5_MASK)
40981 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
40982 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
40983
40985 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)
40986
40990 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)
40991 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U)
40992 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK)
40993
40997 #define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)
40998 #define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)
40999
41001 #define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
41002 #define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)
41003 #define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)
41004
41008 #define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
41009 #define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)
41010 #define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)
41011
41015 #define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
41016 #define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)
41017 #define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)
41018
41022 #define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
41023 #define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)
41024 #define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)
41025
41029 #define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
41030
41034 #define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)
41035 #define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)
41036
41038 #define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)
41039 #define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)
41040 #define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)
41041
41043 #define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)
41044
41048 #define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)
41049 #define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)
41050
41054 #define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
41055 #define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U)
41056 #define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U)
41057
41061 #define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
41062 #define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)
41063 #define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)
41064
41068 #define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
41069
41073 #define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)
41074 #define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)
41075
41077 #define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
41078 #define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)
41079 #define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)
41080
41084 #define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
41085 #define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)
41086 #define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)
41087
41091 #define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
41092 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)
41093 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)
41094
41098 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
41099
41103 #define TSC_INT_STATUS_MEASURE_MASK (0x1U)
41104 #define TSC_INT_STATUS_MEASURE_SHIFT (0U)
41105
41109 #define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
41110 #define TSC_INT_STATUS_DETECT_MASK (0x10U)
41111 #define TSC_INT_STATUS_DETECT_SHIFT (4U)
41112
41116 #define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
41117 #define TSC_INT_STATUS_VALID_MASK (0x100U)
41118 #define TSC_INT_STATUS_VALID_SHIFT (8U)
41119
41123 #define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
41124 #define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)
41125 #define TSC_INT_STATUS_IDLE_SW_SHIFT (12U)
41126
41130 #define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
41131
41135 #define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)
41136 #define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)
41137
41139 #define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)
41140 #define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)
41141 #define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)
41142
41144 #define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)
41145 #define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)
41146 #define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)
41147
41149 #define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
41150 #define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)
41151 #define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)
41152
41156 #define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
41157 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)
41158 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)
41159
41163 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
41164 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
41165 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
41166
41170 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
41171 #define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)
41172 #define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)
41173
41177 #define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
41178
41182 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)
41183 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)
41184
41188 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
41189 #define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)
41190 #define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)
41191
41195 #define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
41196 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)
41197 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)
41198
41202 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
41203 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)
41204 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)
41205
41209 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
41210 #define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)
41211 #define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)
41212
41216 #define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
41217 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)
41218 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)
41219
41223 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
41224 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)
41225 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)
41226
41230 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
41231 #define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)
41232 #define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)
41233
41237 #define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
41238 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)
41239 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)
41240
41244 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
41245 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)
41246 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)
41247
41251 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
41252 #define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)
41253 #define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)
41254
41258 #define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
41259 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)
41260 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)
41261
41265 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
41266 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)
41267 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)
41268
41272 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
41273 #define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)
41274 #define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)
41275
41279 #define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
41280 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)
41281 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
41282
41286 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
41287 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)
41288 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)
41289
41293 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
41294 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)
41295 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)
41296
41300 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
41301 #define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)
41302 #define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)
41303
41312 #define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
41313 #define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)
41314 #define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)
41315
41319 #define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
41320 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
41321 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
41322
41326 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
41327 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
41328 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
41329
41333 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
41334 #define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)
41335 #define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)
41336
41342 #define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)
41343 /* end of group TSC_Register_Masks */
41349
41350
41351 /* TSC - Peripheral instance base addresses */
41353 #define TSC_BASE (0x400E0000u)
41354
41355 #define TSC ((TSC_Type *)TSC_BASE)
41356
41357 #define TSC_BASE_ADDRS { TSC_BASE }
41358
41359 #define TSC_BASE_PTRS { TSC }
41360
41361 #define TSC_IRQS { TSC_DIG_IRQn }
41362 /* Backward compatibility */
41363 #define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_WIRE_4_5_MASK
41364 #define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_WIRE_4_5_SHIFT
41365 #define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_WIRE_4_5(x)
41366
41367 /* end of group TSC_Peripheral_Access_Layer */
41371
41372
41373 /* ----------------------------------------------------------------------------
41374 -- USB Peripheral Access Layer
41375 ---------------------------------------------------------------------------- */
41376
41383 typedef struct {
41384 __I uint32_t ID;
41385 __I uint32_t HWGENERAL;
41386 __I uint32_t HWHOST;
41387 __I uint32_t HWDEVICE;
41388 __I uint32_t HWTXBUF;
41389 __I uint32_t HWRXBUF;
41390 uint8_t RESERVED_0[104];
41391 __IO uint32_t GPTIMER0LD;
41392 __IO uint32_t GPTIMER0CTRL;
41393 __IO uint32_t GPTIMER1LD;
41394 __IO uint32_t GPTIMER1CTRL;
41395 __IO uint32_t SBUSCFG;
41396 uint8_t RESERVED_1[108];
41397 __I uint8_t CAPLENGTH;
41398 uint8_t RESERVED_2[1];
41399 __I uint16_t HCIVERSION;
41400 __I uint32_t HCSPARAMS;
41401 __I uint32_t HCCPARAMS;
41402 uint8_t RESERVED_3[20];
41403 __I uint16_t DCIVERSION;
41404 uint8_t RESERVED_4[2];
41405 __I uint32_t DCCPARAMS;
41406 uint8_t RESERVED_5[24];
41407 __IO uint32_t USBCMD;
41408 __IO uint32_t USBSTS;
41409 __IO uint32_t USBINTR;
41410 __IO uint32_t FRINDEX;
41411 uint8_t RESERVED_6[4];
41412 union { /* offset: 0x154 */
41413 __IO uint32_t DEVICEADDR;
41414 __IO uint32_t PERIODICLISTBASE;
41415 };
41416 union { /* offset: 0x158 */
41417 __IO uint32_t ASYNCLISTADDR;
41418 __IO uint32_t ENDPTLISTADDR;
41419 };
41420 uint8_t RESERVED_7[4];
41421 __IO uint32_t BURSTSIZE;
41422 __IO uint32_t TXFILLTUNING;
41423 uint8_t RESERVED_8[16];
41424 __IO uint32_t ENDPTNAK;
41425 __IO uint32_t ENDPTNAKEN;
41426 __I uint32_t CONFIGFLAG;
41427 __IO uint32_t PORTSC1;
41428 uint8_t RESERVED_9[28];
41429 __IO uint32_t OTGSC;
41430 __IO uint32_t USBMODE;
41431 __IO uint32_t ENDPTSETUPSTAT;
41432 __IO uint32_t ENDPTPRIME;
41433 __IO uint32_t ENDPTFLUSH;
41434 __I uint32_t ENDPTSTAT;
41435 __IO uint32_t ENDPTCOMPLETE;
41436 __IO uint32_t ENDPTCTRL0;
41437 __IO uint32_t ENDPTCTRL[7];
41438 } USB_Type;
41439
41440 /* ----------------------------------------------------------------------------
41441 -- USB Register Masks
41442 ---------------------------------------------------------------------------- */
41443
41451 #define USB_ID_ID_MASK (0x3FU)
41452 #define USB_ID_ID_SHIFT (0U)
41453 #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
41454 #define USB_ID_NID_MASK (0x3F00U)
41455 #define USB_ID_NID_SHIFT (8U)
41456 #define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
41457 #define USB_ID_REVISION_MASK (0xFF0000U)
41458 #define USB_ID_REVISION_SHIFT (16U)
41459 #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
41460
41464 #define USB_HWGENERAL_PHYW_MASK (0x30U)
41465 #define USB_HWGENERAL_PHYW_SHIFT (4U)
41466
41472 #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
41473 #define USB_HWGENERAL_PHYM_MASK (0x1C0U)
41474 #define USB_HWGENERAL_PHYM_SHIFT (6U)
41475
41485 #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
41486 #define USB_HWGENERAL_SM_MASK (0x600U)
41487 #define USB_HWGENERAL_SM_SHIFT (9U)
41488
41494 #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
41495
41499 #define USB_HWHOST_HC_MASK (0x1U)
41500 #define USB_HWHOST_HC_SHIFT (0U)
41501
41505 #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
41506 #define USB_HWHOST_NPORT_MASK (0xEU)
41507 #define USB_HWHOST_NPORT_SHIFT (1U)
41508 #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
41509
41513 #define USB_HWDEVICE_DC_MASK (0x1U)
41514 #define USB_HWDEVICE_DC_SHIFT (0U)
41515
41519 #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
41520 #define USB_HWDEVICE_DEVEP_MASK (0x3EU)
41521 #define USB_HWDEVICE_DEVEP_SHIFT (1U)
41522 #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
41523
41527 #define USB_HWTXBUF_TXBURST_MASK (0xFFU)
41528 #define USB_HWTXBUF_TXBURST_SHIFT (0U)
41529 #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
41530 #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
41531 #define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
41532 #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
41533
41537 #define USB_HWRXBUF_RXBURST_MASK (0xFFU)
41538 #define USB_HWRXBUF_RXBURST_SHIFT (0U)
41539 #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
41540 #define USB_HWRXBUF_RXADD_MASK (0xFF00U)
41541 #define USB_HWRXBUF_RXADD_SHIFT (8U)
41542 #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
41543
41547 #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
41548 #define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
41549 #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
41550
41554 #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
41555 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
41556 #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
41557 #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
41558 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
41559
41563 #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
41564 #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
41565 #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
41566
41570 #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
41571 #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
41572 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
41573
41577 #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
41578
41582 #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
41583 #define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
41584 #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
41585
41589 #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
41590 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
41591 #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
41592 #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
41593 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
41594
41598 #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
41599 #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
41600 #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
41601
41605 #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
41606 #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
41607 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
41608
41612 #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
41613
41617 #define USB_SBUSCFG_AHBBRST_MASK (0x7U)
41618 #define USB_SBUSCFG_AHBBRST_SHIFT (0U)
41619
41629 #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
41630
41634 #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
41635 #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
41636 #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
41637
41641 #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
41642 #define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
41643 #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
41644
41648 #define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
41649 #define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
41650 #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
41651 #define USB_HCSPARAMS_PPC_MASK (0x10U)
41652 #define USB_HCSPARAMS_PPC_SHIFT (4U)
41653 #define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
41654 #define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
41655 #define USB_HCSPARAMS_N_PCC_SHIFT (8U)
41656 #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
41657 #define USB_HCSPARAMS_N_CC_MASK (0xF000U)
41658 #define USB_HCSPARAMS_N_CC_SHIFT (12U)
41659
41663 #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
41664 #define USB_HCSPARAMS_PI_MASK (0x10000U)
41665 #define USB_HCSPARAMS_PI_SHIFT (16U)
41666 #define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
41667 #define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
41668 #define USB_HCSPARAMS_N_PTT_SHIFT (20U)
41669 #define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
41670 #define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
41671 #define USB_HCSPARAMS_N_TT_SHIFT (24U)
41672 #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
41673
41677 #define USB_HCCPARAMS_ADC_MASK (0x1U)
41678 #define USB_HCCPARAMS_ADC_SHIFT (0U)
41679 #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
41680 #define USB_HCCPARAMS_PFL_MASK (0x2U)
41681 #define USB_HCCPARAMS_PFL_SHIFT (1U)
41682 #define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
41683 #define USB_HCCPARAMS_ASP_MASK (0x4U)
41684 #define USB_HCCPARAMS_ASP_SHIFT (2U)
41685 #define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
41686 #define USB_HCCPARAMS_IST_MASK (0xF0U)
41687 #define USB_HCCPARAMS_IST_SHIFT (4U)
41688 #define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
41689 #define USB_HCCPARAMS_EECP_MASK (0xFF00U)
41690 #define USB_HCCPARAMS_EECP_SHIFT (8U)
41691 #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
41692
41696 #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
41697 #define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
41698 #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
41699
41703 #define USB_DCCPARAMS_DEN_MASK (0x1FU)
41704 #define USB_DCCPARAMS_DEN_SHIFT (0U)
41705 #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
41706 #define USB_DCCPARAMS_DC_MASK (0x80U)
41707 #define USB_DCCPARAMS_DC_SHIFT (7U)
41708 #define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
41709 #define USB_DCCPARAMS_HC_MASK (0x100U)
41710 #define USB_DCCPARAMS_HC_SHIFT (8U)
41711 #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
41712
41716 #define USB_USBCMD_RS_MASK (0x1U)
41717 #define USB_USBCMD_RS_SHIFT (0U)
41718 #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
41719 #define USB_USBCMD_RST_MASK (0x2U)
41720 #define USB_USBCMD_RST_SHIFT (1U)
41721 #define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
41722 #define USB_USBCMD_FS_1_MASK (0xCU)
41723 #define USB_USBCMD_FS_1_SHIFT (2U)
41724 #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
41725 #define USB_USBCMD_PSE_MASK (0x10U)
41726 #define USB_USBCMD_PSE_SHIFT (4U)
41727
41731 #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
41732 #define USB_USBCMD_ASE_MASK (0x20U)
41733 #define USB_USBCMD_ASE_SHIFT (5U)
41734
41738 #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
41739 #define USB_USBCMD_IAA_MASK (0x40U)
41740 #define USB_USBCMD_IAA_SHIFT (6U)
41741 #define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
41742 #define USB_USBCMD_ASP_MASK (0x300U)
41743 #define USB_USBCMD_ASP_SHIFT (8U)
41744 #define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
41745 #define USB_USBCMD_ASPE_MASK (0x800U)
41746 #define USB_USBCMD_ASPE_SHIFT (11U)
41747 #define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
41748 #define USB_USBCMD_ATDTW_MASK (0x1000U)
41749 #define USB_USBCMD_ATDTW_SHIFT (12U)
41750 #define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
41751 #define USB_USBCMD_SUTW_MASK (0x2000U)
41752 #define USB_USBCMD_SUTW_SHIFT (13U)
41753 #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
41754 #define USB_USBCMD_FS_2_MASK (0x8000U)
41755 #define USB_USBCMD_FS_2_SHIFT (15U)
41756
41760 #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
41761 #define USB_USBCMD_ITC_MASK (0xFF0000U)
41762 #define USB_USBCMD_ITC_SHIFT (16U)
41763
41773 #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
41774
41778 #define USB_USBSTS_UI_MASK (0x1U)
41779 #define USB_USBSTS_UI_SHIFT (0U)
41780 #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
41781 #define USB_USBSTS_UEI_MASK (0x2U)
41782 #define USB_USBSTS_UEI_SHIFT (1U)
41783 #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
41784 #define USB_USBSTS_PCI_MASK (0x4U)
41785 #define USB_USBSTS_PCI_SHIFT (2U)
41786 #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
41787 #define USB_USBSTS_FRI_MASK (0x8U)
41788 #define USB_USBSTS_FRI_SHIFT (3U)
41789 #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
41790 #define USB_USBSTS_SEI_MASK (0x10U)
41791 #define USB_USBSTS_SEI_SHIFT (4U)
41792 #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
41793 #define USB_USBSTS_AAI_MASK (0x20U)
41794 #define USB_USBSTS_AAI_SHIFT (5U)
41795 #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
41796 #define USB_USBSTS_URI_MASK (0x40U)
41797 #define USB_USBSTS_URI_SHIFT (6U)
41798 #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
41799 #define USB_USBSTS_SRI_MASK (0x80U)
41800 #define USB_USBSTS_SRI_SHIFT (7U)
41801 #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
41802 #define USB_USBSTS_SLI_MASK (0x100U)
41803 #define USB_USBSTS_SLI_SHIFT (8U)
41804 #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
41805 #define USB_USBSTS_ULPII_MASK (0x400U)
41806 #define USB_USBSTS_ULPII_SHIFT (10U)
41807 #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
41808 #define USB_USBSTS_HCH_MASK (0x1000U)
41809 #define USB_USBSTS_HCH_SHIFT (12U)
41810 #define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
41811 #define USB_USBSTS_RCL_MASK (0x2000U)
41812 #define USB_USBSTS_RCL_SHIFT (13U)
41813 #define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
41814 #define USB_USBSTS_PS_MASK (0x4000U)
41815 #define USB_USBSTS_PS_SHIFT (14U)
41816 #define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
41817 #define USB_USBSTS_AS_MASK (0x8000U)
41818 #define USB_USBSTS_AS_SHIFT (15U)
41819 #define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
41820 #define USB_USBSTS_NAKI_MASK (0x10000U)
41821 #define USB_USBSTS_NAKI_SHIFT (16U)
41822 #define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
41823 #define USB_USBSTS_TI0_MASK (0x1000000U)
41824 #define USB_USBSTS_TI0_SHIFT (24U)
41825 #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
41826 #define USB_USBSTS_TI1_MASK (0x2000000U)
41827 #define USB_USBSTS_TI1_SHIFT (25U)
41828 #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
41829
41833 #define USB_USBINTR_UE_MASK (0x1U)
41834 #define USB_USBINTR_UE_SHIFT (0U)
41835 #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
41836 #define USB_USBINTR_UEE_MASK (0x2U)
41837 #define USB_USBINTR_UEE_SHIFT (1U)
41838 #define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
41839 #define USB_USBINTR_PCE_MASK (0x4U)
41840 #define USB_USBINTR_PCE_SHIFT (2U)
41841 #define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
41842 #define USB_USBINTR_FRE_MASK (0x8U)
41843 #define USB_USBINTR_FRE_SHIFT (3U)
41844 #define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
41845 #define USB_USBINTR_SEE_MASK (0x10U)
41846 #define USB_USBINTR_SEE_SHIFT (4U)
41847 #define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
41848 #define USB_USBINTR_AAE_MASK (0x20U)
41849 #define USB_USBINTR_AAE_SHIFT (5U)
41850 #define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
41851 #define USB_USBINTR_URE_MASK (0x40U)
41852 #define USB_USBINTR_URE_SHIFT (6U)
41853 #define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
41854 #define USB_USBINTR_SRE_MASK (0x80U)
41855 #define USB_USBINTR_SRE_SHIFT (7U)
41856 #define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
41857 #define USB_USBINTR_SLE_MASK (0x100U)
41858 #define USB_USBINTR_SLE_SHIFT (8U)
41859 #define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
41860 #define USB_USBINTR_ULPIE_MASK (0x400U)
41861 #define USB_USBINTR_ULPIE_SHIFT (10U)
41862 #define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
41863 #define USB_USBINTR_NAKE_MASK (0x10000U)
41864 #define USB_USBINTR_NAKE_SHIFT (16U)
41865 #define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
41866 #define USB_USBINTR_UAIE_MASK (0x40000U)
41867 #define USB_USBINTR_UAIE_SHIFT (18U)
41868 #define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
41869 #define USB_USBINTR_UPIE_MASK (0x80000U)
41870 #define USB_USBINTR_UPIE_SHIFT (19U)
41871 #define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
41872 #define USB_USBINTR_TIE0_MASK (0x1000000U)
41873 #define USB_USBINTR_TIE0_SHIFT (24U)
41874 #define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
41875 #define USB_USBINTR_TIE1_MASK (0x2000000U)
41876 #define USB_USBINTR_TIE1_SHIFT (25U)
41877 #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
41878
41882 #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
41883 #define USB_FRINDEX_FRINDEX_SHIFT (0U)
41884
41894 #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
41895
41899 #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
41900 #define USB_DEVICEADDR_USBADRA_SHIFT (24U)
41901 #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
41902 #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
41903 #define USB_DEVICEADDR_USBADR_SHIFT (25U)
41904 #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
41905
41909 #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
41910 #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
41911 #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
41912
41916 #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
41917 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
41918 #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
41919
41923 #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
41924 #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
41925 #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
41926
41930 #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
41931 #define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
41932 #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
41933 #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
41934 #define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
41935 #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
41936
41940 #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
41941 #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
41942 #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
41943 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
41944 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
41945 #define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
41946 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
41947 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
41948 #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
41949
41953 #define USB_ENDPTNAK_EPRN_MASK (0xFFU)
41954 #define USB_ENDPTNAK_EPRN_SHIFT (0U)
41955 #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
41956 #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
41957 #define USB_ENDPTNAK_EPTN_SHIFT (16U)
41958 #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
41959
41963 #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
41964 #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
41965 #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
41966 #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
41967 #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
41968 #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
41969
41973 #define USB_CONFIGFLAG_CF_MASK (0x1U)
41974 #define USB_CONFIGFLAG_CF_SHIFT (0U)
41975
41979 #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
41980
41984 #define USB_PORTSC1_CCS_MASK (0x1U)
41985 #define USB_PORTSC1_CCS_SHIFT (0U)
41986 #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
41987 #define USB_PORTSC1_CSC_MASK (0x2U)
41988 #define USB_PORTSC1_CSC_SHIFT (1U)
41989 #define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
41990 #define USB_PORTSC1_PE_MASK (0x4U)
41991 #define USB_PORTSC1_PE_SHIFT (2U)
41992 #define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
41993 #define USB_PORTSC1_PEC_MASK (0x8U)
41994 #define USB_PORTSC1_PEC_SHIFT (3U)
41995 #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
41996 #define USB_PORTSC1_OCA_MASK (0x10U)
41997 #define USB_PORTSC1_OCA_SHIFT (4U)
41998
42002 #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
42003 #define USB_PORTSC1_OCC_MASK (0x20U)
42004 #define USB_PORTSC1_OCC_SHIFT (5U)
42005 #define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
42006 #define USB_PORTSC1_FPR_MASK (0x40U)
42007 #define USB_PORTSC1_FPR_SHIFT (6U)
42008 #define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
42009 #define USB_PORTSC1_SUSP_MASK (0x80U)
42010 #define USB_PORTSC1_SUSP_SHIFT (7U)
42011 #define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
42012 #define USB_PORTSC1_PR_MASK (0x100U)
42013 #define USB_PORTSC1_PR_SHIFT (8U)
42014 #define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
42015 #define USB_PORTSC1_HSP_MASK (0x200U)
42016 #define USB_PORTSC1_HSP_SHIFT (9U)
42017 #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
42018 #define USB_PORTSC1_LS_MASK (0xC00U)
42019 #define USB_PORTSC1_LS_SHIFT (10U)
42020
42026 #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
42027 #define USB_PORTSC1_PP_MASK (0x1000U)
42028 #define USB_PORTSC1_PP_SHIFT (12U)
42029 #define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
42030 #define USB_PORTSC1_PO_MASK (0x2000U)
42031 #define USB_PORTSC1_PO_SHIFT (13U)
42032 #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
42033 #define USB_PORTSC1_PIC_MASK (0xC000U)
42034 #define USB_PORTSC1_PIC_SHIFT (14U)
42035
42041 #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
42042 #define USB_PORTSC1_PTC_MASK (0xF0000U)
42043 #define USB_PORTSC1_PTC_SHIFT (16U)
42044
42054 #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
42055 #define USB_PORTSC1_WKCN_MASK (0x100000U)
42056 #define USB_PORTSC1_WKCN_SHIFT (20U)
42057 #define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
42058 #define USB_PORTSC1_WKDC_MASK (0x200000U)
42059 #define USB_PORTSC1_WKDC_SHIFT (21U)
42060 #define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
42061 #define USB_PORTSC1_WKOC_MASK (0x400000U)
42062 #define USB_PORTSC1_WKOC_SHIFT (22U)
42063 #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
42064 #define USB_PORTSC1_PHCD_MASK (0x800000U)
42065 #define USB_PORTSC1_PHCD_SHIFT (23U)
42066
42070 #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
42071 #define USB_PORTSC1_PFSC_MASK (0x1000000U)
42072 #define USB_PORTSC1_PFSC_SHIFT (24U)
42073
42077 #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
42078 #define USB_PORTSC1_PTS_2_MASK (0x2000000U)
42079 #define USB_PORTSC1_PTS_2_SHIFT (25U)
42080 #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
42081 #define USB_PORTSC1_PSPD_MASK (0xC000000U)
42082 #define USB_PORTSC1_PSPD_SHIFT (26U)
42083
42089 #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
42090 #define USB_PORTSC1_PTW_MASK (0x10000000U)
42091 #define USB_PORTSC1_PTW_SHIFT (28U)
42092
42096 #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
42097 #define USB_PORTSC1_STS_MASK (0x20000000U)
42098 #define USB_PORTSC1_STS_SHIFT (29U)
42099 #define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
42100 #define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
42101 #define USB_PORTSC1_PTS_1_SHIFT (30U)
42102 #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
42103
42107 #define USB_OTGSC_VD_MASK (0x1U)
42108 #define USB_OTGSC_VD_SHIFT (0U)
42109 #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
42110 #define USB_OTGSC_VC_MASK (0x2U)
42111 #define USB_OTGSC_VC_SHIFT (1U)
42112 #define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
42113 #define USB_OTGSC_OT_MASK (0x8U)
42114 #define USB_OTGSC_OT_SHIFT (3U)
42115 #define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
42116 #define USB_OTGSC_DP_MASK (0x10U)
42117 #define USB_OTGSC_DP_SHIFT (4U)
42118 #define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
42119 #define USB_OTGSC_IDPU_MASK (0x20U)
42120 #define USB_OTGSC_IDPU_SHIFT (5U)
42121 #define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
42122 #define USB_OTGSC_ID_MASK (0x100U)
42123 #define USB_OTGSC_ID_SHIFT (8U)
42124 #define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
42125 #define USB_OTGSC_AVV_MASK (0x200U)
42126 #define USB_OTGSC_AVV_SHIFT (9U)
42127 #define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
42128 #define USB_OTGSC_ASV_MASK (0x400U)
42129 #define USB_OTGSC_ASV_SHIFT (10U)
42130 #define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
42131 #define USB_OTGSC_BSV_MASK (0x800U)
42132 #define USB_OTGSC_BSV_SHIFT (11U)
42133 #define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
42134 #define USB_OTGSC_BSE_MASK (0x1000U)
42135 #define USB_OTGSC_BSE_SHIFT (12U)
42136 #define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
42137 #define USB_OTGSC_TOG_1MS_MASK (0x2000U)
42138 #define USB_OTGSC_TOG_1MS_SHIFT (13U)
42139 #define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
42140 #define USB_OTGSC_DPS_MASK (0x4000U)
42141 #define USB_OTGSC_DPS_SHIFT (14U)
42142 #define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
42143 #define USB_OTGSC_IDIS_MASK (0x10000U)
42144 #define USB_OTGSC_IDIS_SHIFT (16U)
42145 #define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
42146 #define USB_OTGSC_AVVIS_MASK (0x20000U)
42147 #define USB_OTGSC_AVVIS_SHIFT (17U)
42148 #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
42149 #define USB_OTGSC_ASVIS_MASK (0x40000U)
42150 #define USB_OTGSC_ASVIS_SHIFT (18U)
42151 #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
42152 #define USB_OTGSC_BSVIS_MASK (0x80000U)
42153 #define USB_OTGSC_BSVIS_SHIFT (19U)
42154 #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
42155 #define USB_OTGSC_BSEIS_MASK (0x100000U)
42156 #define USB_OTGSC_BSEIS_SHIFT (20U)
42157 #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
42158 #define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
42159 #define USB_OTGSC_STATUS_1MS_SHIFT (21U)
42160 #define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
42161 #define USB_OTGSC_DPIS_MASK (0x400000U)
42162 #define USB_OTGSC_DPIS_SHIFT (22U)
42163 #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
42164 #define USB_OTGSC_IDIE_MASK (0x1000000U)
42165 #define USB_OTGSC_IDIE_SHIFT (24U)
42166 #define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
42167 #define USB_OTGSC_AVVIE_MASK (0x2000000U)
42168 #define USB_OTGSC_AVVIE_SHIFT (25U)
42169 #define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
42170 #define USB_OTGSC_ASVIE_MASK (0x4000000U)
42171 #define USB_OTGSC_ASVIE_SHIFT (26U)
42172 #define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
42173 #define USB_OTGSC_BSVIE_MASK (0x8000000U)
42174 #define USB_OTGSC_BSVIE_SHIFT (27U)
42175 #define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
42176 #define USB_OTGSC_BSEIE_MASK (0x10000000U)
42177 #define USB_OTGSC_BSEIE_SHIFT (28U)
42178 #define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
42179 #define USB_OTGSC_EN_1MS_MASK (0x20000000U)
42180 #define USB_OTGSC_EN_1MS_SHIFT (29U)
42181 #define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
42182 #define USB_OTGSC_DPIE_MASK (0x40000000U)
42183 #define USB_OTGSC_DPIE_SHIFT (30U)
42184 #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
42185
42189 #define USB_USBMODE_CM_MASK (0x3U)
42190 #define USB_USBMODE_CM_SHIFT (0U)
42191
42197 #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
42198 #define USB_USBMODE_ES_MASK (0x4U)
42199 #define USB_USBMODE_ES_SHIFT (2U)
42200
42204 #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
42205 #define USB_USBMODE_SLOM_MASK (0x8U)
42206 #define USB_USBMODE_SLOM_SHIFT (3U)
42207
42211 #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
42212 #define USB_USBMODE_SDIS_MASK (0x10U)
42213 #define USB_USBMODE_SDIS_SHIFT (4U)
42214 #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
42215
42219 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
42220 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
42221 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
42222
42226 #define USB_ENDPTPRIME_PERB_MASK (0xFFU)
42227 #define USB_ENDPTPRIME_PERB_SHIFT (0U)
42228 #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
42229 #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
42230 #define USB_ENDPTPRIME_PETB_SHIFT (16U)
42231 #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
42232
42236 #define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
42237 #define USB_ENDPTFLUSH_FERB_SHIFT (0U)
42238 #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
42239 #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
42240 #define USB_ENDPTFLUSH_FETB_SHIFT (16U)
42241 #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
42242
42246 #define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
42247 #define USB_ENDPTSTAT_ERBR_SHIFT (0U)
42248 #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
42249 #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
42250 #define USB_ENDPTSTAT_ETBR_SHIFT (16U)
42251 #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
42252
42256 #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
42257 #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
42258 #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
42259 #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
42260 #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
42261 #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
42262
42266 #define USB_ENDPTCTRL0_RXS_MASK (0x1U)
42267 #define USB_ENDPTCTRL0_RXS_SHIFT (0U)
42268 #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
42269 #define USB_ENDPTCTRL0_RXT_MASK (0xCU)
42270 #define USB_ENDPTCTRL0_RXT_SHIFT (2U)
42271 #define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
42272 #define USB_ENDPTCTRL0_RXE_MASK (0x80U)
42273 #define USB_ENDPTCTRL0_RXE_SHIFT (7U)
42274 #define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
42275 #define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
42276 #define USB_ENDPTCTRL0_TXS_SHIFT (16U)
42277 #define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
42278 #define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
42279 #define USB_ENDPTCTRL0_TXT_SHIFT (18U)
42280 #define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
42281 #define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
42282 #define USB_ENDPTCTRL0_TXE_SHIFT (23U)
42283 #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
42284
42288 #define USB_ENDPTCTRL_RXS_MASK (0x1U)
42289 #define USB_ENDPTCTRL_RXS_SHIFT (0U)
42290 #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
42291 #define USB_ENDPTCTRL_RXD_MASK (0x2U)
42292 #define USB_ENDPTCTRL_RXD_SHIFT (1U)
42293 #define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
42294 #define USB_ENDPTCTRL_RXT_MASK (0xCU)
42295 #define USB_ENDPTCTRL_RXT_SHIFT (2U)
42296 #define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
42297 #define USB_ENDPTCTRL_RXI_MASK (0x20U)
42298 #define USB_ENDPTCTRL_RXI_SHIFT (5U)
42299 #define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
42300 #define USB_ENDPTCTRL_RXR_MASK (0x40U)
42301 #define USB_ENDPTCTRL_RXR_SHIFT (6U)
42302 #define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
42303 #define USB_ENDPTCTRL_RXE_MASK (0x80U)
42304 #define USB_ENDPTCTRL_RXE_SHIFT (7U)
42305 #define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
42306 #define USB_ENDPTCTRL_TXS_MASK (0x10000U)
42307 #define USB_ENDPTCTRL_TXS_SHIFT (16U)
42308 #define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
42309 #define USB_ENDPTCTRL_TXD_MASK (0x20000U)
42310 #define USB_ENDPTCTRL_TXD_SHIFT (17U)
42311 #define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
42312 #define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
42313 #define USB_ENDPTCTRL_TXT_SHIFT (18U)
42314 #define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
42315 #define USB_ENDPTCTRL_TXI_MASK (0x200000U)
42316 #define USB_ENDPTCTRL_TXI_SHIFT (21U)
42317 #define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
42318 #define USB_ENDPTCTRL_TXR_MASK (0x400000U)
42319 #define USB_ENDPTCTRL_TXR_SHIFT (22U)
42320 #define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
42321 #define USB_ENDPTCTRL_TXE_MASK (0x800000U)
42322 #define USB_ENDPTCTRL_TXE_SHIFT (23U)
42323 #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
42324
42326 /* The count of USB_ENDPTCTRL */
42327 #define USB_ENDPTCTRL_COUNT (7U)
42328
42329 /* end of group USB_Register_Masks */
42333
42334
42335 /* USB - Peripheral instance base addresses */
42337 #define USB1_BASE (0x402E0000u)
42338
42339 #define USB1 ((USB_Type *)USB1_BASE)
42340
42341 #define USB2_BASE (0x402E0200u)
42342
42343 #define USB2 ((USB_Type *)USB2_BASE)
42344
42345 #define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }
42346
42347 #define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }
42348
42349 #define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
42350 /* Backward compatibility */
42351 #define GPTIMER0CTL GPTIMER0CTRL
42352 #define GPTIMER1CTL GPTIMER1CTRL
42353 #define USB_SBUSCFG SBUSCFG
42354 #define EPLISTADDR ENDPTLISTADDR
42355 #define EPSETUPSR ENDPTSETUPSTAT
42356 #define EPPRIME ENDPTPRIME
42357 #define EPFLUSH ENDPTFLUSH
42358 #define EPSR ENDPTSTAT
42359 #define EPCOMPLETE ENDPTCOMPLETE
42360 #define EPCR ENDPTCTRL
42361 #define EPCR0 ENDPTCTRL0
42362 #define USBHS_ID_ID_MASK USB_ID_ID_MASK
42363 #define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
42364 #define USBHS_ID_ID(x) USB_ID_ID(x)
42365 #define USBHS_ID_NID_MASK USB_ID_NID_MASK
42366 #define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
42367 #define USBHS_ID_NID(x) USB_ID_NID(x)
42368 #define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
42369 #define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
42370 #define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
42371 #define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
42372 #define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
42373 #define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
42374 #define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
42375 #define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
42376 #define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
42377 #define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
42378 #define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
42379 #define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
42380 #define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
42381 #define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
42382 #define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
42383 #define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
42384 #define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
42385 #define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
42386 #define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
42387 #define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
42388 #define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
42389 #define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
42390 #define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
42391 #define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
42392 #define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
42393 #define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
42394 #define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
42395 #define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
42396 #define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
42397 #define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
42398 #define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
42399 #define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
42400 #define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
42401 #define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
42402 #define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
42403 #define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
42404 #define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
42405 #define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
42406 #define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
42407 #define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
42408 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
42409 #define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
42410 #define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
42411 #define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
42412 #define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
42413 #define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
42414 #define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
42415 #define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
42416 #define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
42417 #define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
42418 #define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
42419 #define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
42420 #define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
42421 #define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
42422 #define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
42423 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
42424 #define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
42425 #define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
42426 #define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
42427 #define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
42428 #define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
42429 #define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
42430 #define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
42431 #define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
42432 #define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
42433 #define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
42434 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
42435 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
42436 #define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
42437 #define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
42438 #define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
42439 #define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
42440 #define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
42441 #define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
42442 #define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
42443 #define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
42444 #define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
42445 #define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
42446 #define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
42447 #define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
42448 #define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
42449 #define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
42450 #define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
42451 #define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
42452 #define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
42453 #define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
42454 #define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
42455 #define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
42456 #define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
42457 #define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
42458 #define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
42459 #define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
42460 #define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
42461 #define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
42462 #define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
42463 #define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
42464 #define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
42465 #define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
42466 #define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
42467 #define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
42468 #define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
42469 #define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
42470 #define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
42471 #define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
42472 #define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
42473 #define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
42474 #define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
42475 #define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
42476 #define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
42477 #define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
42478 #define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
42479 #define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
42480 #define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
42481 #define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
42482 #define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
42483 #define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
42484 #define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
42485 #define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
42486 #define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
42487 #define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
42488 #define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
42489 #define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
42490 #define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
42491 #define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
42492 #define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
42493 #define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
42494 #define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
42495 #define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
42496 #define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
42497 #define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
42498 #define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
42499 #define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
42500 #define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
42501 #define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
42502 #define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
42503 #define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
42504 #define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
42505 #define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
42506 #define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
42507 #define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
42508 #define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
42509 #define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
42510 #define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
42511 #define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
42512 #define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
42513 #define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
42514 #define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
42515 #define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
42516 #define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
42517 #define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
42518 #define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
42519 #define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
42520 #define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
42521 #define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
42522 #define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
42523 #define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
42524 #define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
42525 #define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
42526 #define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
42527 #define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
42528 #define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
42529 #define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
42530 #define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
42531 #define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
42532 #define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
42533 #define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
42534 #define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
42535 #define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
42536 #define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
42537 #define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
42538 #define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
42539 #define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
42540 #define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
42541 #define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
42542 #define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
42543 #define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
42544 #define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
42545 #define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
42546 #define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
42547 #define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
42548 #define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
42549 #define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
42550 #define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
42551 #define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
42552 #define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
42553 #define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
42554 #define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
42555 #define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
42556 #define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
42557 #define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
42558 #define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
42559 #define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
42560 #define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
42561 #define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
42562 #define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
42563 #define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
42564 #define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
42565 #define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
42566 #define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
42567 #define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
42568 #define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
42569 #define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
42570 #define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
42571 #define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
42572 #define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
42573 #define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
42574 #define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
42575 #define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
42576 #define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
42577 #define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
42578 #define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
42579 #define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
42580 #define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
42581 #define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
42582 #define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
42583 #define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
42584 #define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
42585 #define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
42586 #define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
42587 #define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
42588 #define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
42589 #define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
42590 #define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
42591 #define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
42592 #define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
42593 #define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
42594 #define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
42595 #define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
42596 #define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
42597 #define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
42598 #define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
42599 #define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
42600 #define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
42601 #define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
42602 #define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
42603 #define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
42604 #define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
42605 #define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
42606 #define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
42607 #define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
42608 #define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
42609 #define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
42610 #define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
42611 #define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
42612 #define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
42613 #define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
42614 #define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
42615 #define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
42616 #define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
42617 #define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
42618 #define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
42619 #define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
42620 #define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
42621 #define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
42622 #define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
42623 #define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
42624 #define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
42625 #define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
42626 #define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
42627 #define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
42628 #define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
42629 #define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
42630 #define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
42631 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
42632 #define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
42633 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
42634 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
42635 #define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
42636 #define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
42637 #define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
42638 #define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
42639 #define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
42640 #define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
42641 #define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
42642 #define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
42643 #define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
42644 #define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
42645 #define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
42646 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
42647 #define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
42648 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
42649 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
42650 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
42651 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
42652 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
42653 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
42654 #define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
42655 #define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
42656 #define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
42657 #define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
42658 #define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
42659 #define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
42660 #define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
42661 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
42662 #define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
42663 #define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
42664 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
42665 #define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
42666 #define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
42667 #define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
42668 #define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
42669 #define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
42670 #define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
42671 #define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
42672 #define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
42673 #define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
42674 #define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
42675 #define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
42676 #define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
42677 #define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
42678 #define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
42679 #define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
42680 #define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
42681 #define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
42682 #define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
42683 #define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
42684 #define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
42685 #define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
42686 #define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
42687 #define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
42688 #define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
42689 #define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
42690 #define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
42691 #define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
42692 #define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
42693 #define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
42694 #define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
42695 #define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
42696 #define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
42697 #define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
42698 #define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
42699 #define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
42700 #define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
42701 #define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
42702 #define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
42703 #define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
42704 #define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
42705 #define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
42706 #define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
42707 #define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
42708 #define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
42709 #define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
42710 #define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
42711 #define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
42712 #define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
42713 #define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
42714 #define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
42715 #define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
42716 #define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
42717 #define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
42718 #define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
42719 #define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
42720 #define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
42721 #define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
42722 #define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
42723 #define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
42724 #define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
42725 #define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
42726 #define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
42727 #define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
42728 #define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
42729 #define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
42730 #define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
42731 #define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
42732 #define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
42733 #define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
42734 #define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
42735 #define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
42736 #define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
42737 #define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
42738 #define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
42739 #define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
42740 #define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
42741 #define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
42742 #define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
42743 #define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
42744 #define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
42745 #define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
42746 #define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
42747 #define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
42748 #define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
42749 #define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
42750 #define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
42751 #define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
42752 #define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
42753 #define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
42754 #define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
42755 #define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
42756 #define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
42757 #define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
42758 #define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
42759 #define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
42760 #define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
42761 #define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
42762 #define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
42763 #define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
42764 #define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
42765 #define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
42766 #define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
42767 #define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
42768 #define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
42769 #define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
42770 #define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
42771 #define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
42772 #define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
42773 #define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
42774 #define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
42775 #define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
42776 #define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
42777 #define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
42778 #define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
42779 #define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
42780 #define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
42781 #define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
42782 #define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
42783 #define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
42784 #define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
42785 #define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
42786 #define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
42787 #define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
42788 #define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
42789 #define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
42790 #define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
42791 #define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
42792 #define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
42793 #define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
42794 #define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
42795 #define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
42796 #define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
42797 #define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
42798 #define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
42799 #define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
42800 #define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
42801 #define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
42802 #define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
42803 #define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
42804 #define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
42805 #define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
42806 #define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
42807 #define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
42808 #define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
42809 #define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
42810 #define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
42811 #define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
42812 #define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
42813 #define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
42814 #define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
42815 #define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
42816 #define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
42817 #define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
42818 #define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
42819 #define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
42820 #define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
42821 #define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
42822 #define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
42823 #define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
42824 #define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
42825 #define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
42826 #define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
42827 #define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
42828 #define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
42829 #define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
42830 #define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
42831 #define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
42832 #define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
42833 #define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
42834 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
42835 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
42836 #define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
42837 #define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
42838 #define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
42839 #define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
42840 #define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
42841 #define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
42842 #define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
42843 #define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
42844 #define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
42845 #define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
42846 #define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
42847 #define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
42848 #define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
42849 #define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
42850 #define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
42851 #define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
42852 #define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
42853 #define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
42854 #define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
42855 #define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
42856 #define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
42857 #define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
42858 #define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
42859 #define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
42860 #define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
42861 #define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
42862 #define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
42863 #define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
42864 #define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
42865 #define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
42866 #define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
42867 #define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
42868 #define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
42869 #define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
42870 #define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
42871 #define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
42872 #define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
42873 #define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
42874 #define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
42875 #define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
42876 #define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
42877 #define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
42878 #define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
42879 #define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
42880 #define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
42881 #define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
42882 #define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
42883 #define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
42884 #define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
42885 #define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
42886 #define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
42887 #define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
42888 #define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
42889 #define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
42890 #define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
42891 #define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
42892 #define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
42893 #define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
42894 #define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
42895 #define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
42896 #define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
42897 #define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
42898 #define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
42899 #define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
42900 #define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
42901 #define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
42902 #define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
42903 #define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
42904 #define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
42905 #define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
42906 #define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
42907 #define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
42908 #define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
42909 #define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
42910 #define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
42911 #define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
42912 #define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
42913 #define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
42914 #define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
42915 #define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
42916 #define USBHS_Type USB_Type
42917 #define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE }
42918 #define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
42919 #define USBHS_IRQHandler USB_OTG1_IRQHandler
42920
42921 /* end of group USB_Peripheral_Access_Layer */
42925
42926
42927 /* ----------------------------------------------------------------------------
42928 -- USBNC Peripheral Access Layer
42929 ---------------------------------------------------------------------------- */
42930
42937 typedef struct {
42938 uint8_t RESERVED_0[2048];
42939 __IO uint32_t USB_OTGn_CTRL;
42940 uint8_t RESERVED_1[20];
42941 __IO uint32_t USB_OTGn_PHY_CTRL_0;
42942 } USBNC_Type;
42943
42944 /* ----------------------------------------------------------------------------
42945 -- USBNC Register Masks
42946 ---------------------------------------------------------------------------- */
42947
42955 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)
42956 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)
42957
42961 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
42962 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)
42963 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)
42964
42968 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
42969 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)
42970 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)
42971
42975 #define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
42976 #define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)
42977 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)
42978
42982 #define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
42983 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)
42984 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)
42985
42989 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
42990 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)
42991 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)
42992
42996 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
42997 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)
42998 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)
42999
43003 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
43004 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)
43005 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)
43006
43010 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
43011 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)
43012 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)
43013
43017 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
43018 #define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)
43019 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)
43020
43024 #define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
43025
43029 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
43030 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
43031
43035 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)
43036 /* end of group USBNC_Register_Masks */
43042
43043
43044 /* USBNC - Peripheral instance base addresses */
43046 #define USBNC1_BASE (0x402E0000u)
43047
43048 #define USBNC1 ((USBNC_Type *)USBNC1_BASE)
43049
43050 #define USBNC2_BASE (0x402E0004u)
43051
43052 #define USBNC2 ((USBNC_Type *)USBNC2_BASE)
43053
43054 #define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }
43055
43056 #define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }
43057 /* end of group USBNC_Peripheral_Access_Layer */
43061
43062
43063 /* ----------------------------------------------------------------------------
43064 -- USBPHY Peripheral Access Layer
43065 ---------------------------------------------------------------------------- */
43066
43073 typedef struct {
43074 __IO uint32_t PWD;
43075 __IO uint32_t PWD_SET;
43076 __IO uint32_t PWD_CLR;
43077 __IO uint32_t PWD_TOG;
43078 __IO uint32_t TX;
43079 __IO uint32_t TX_SET;
43080 __IO uint32_t TX_CLR;
43081 __IO uint32_t TX_TOG;
43082 __IO uint32_t RX;
43083 __IO uint32_t RX_SET;
43084 __IO uint32_t RX_CLR;
43085 __IO uint32_t RX_TOG;
43086 __IO uint32_t CTRL;
43087 __IO uint32_t CTRL_SET;
43088 __IO uint32_t CTRL_CLR;
43089 __IO uint32_t CTRL_TOG;
43090 __IO uint32_t STATUS;
43091 uint8_t RESERVED_0[12];
43092 __IO uint32_t DEBUGr;
43093 __IO uint32_t DEBUG_SET;
43094 __IO uint32_t DEBUG_CLR;
43095 __IO uint32_t DEBUG_TOG;
43096 __I uint32_t DEBUG0_STATUS;
43097 uint8_t RESERVED_1[12];
43098 __IO uint32_t DEBUG1;
43099 __IO uint32_t DEBUG1_SET;
43100 __IO uint32_t DEBUG1_CLR;
43101 __IO uint32_t DEBUG1_TOG;
43102 __I uint32_t VERSION;
43103 } USBPHY_Type;
43104
43105 /* ----------------------------------------------------------------------------
43106 -- USBPHY Register Masks
43107 ---------------------------------------------------------------------------- */
43108
43116 #define USBPHY_PWD_RSVD0_MASK (0x3FFU)
43117 #define USBPHY_PWD_RSVD0_SHIFT (0U)
43118 #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
43119 #define USBPHY_PWD_TXPWDFS_MASK (0x400U)
43120 #define USBPHY_PWD_TXPWDFS_SHIFT (10U)
43121 #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
43122 #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
43123 #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
43124 #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
43125 #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
43126 #define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
43127 #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
43128 #define USBPHY_PWD_RSVD1_MASK (0x1E000U)
43129 #define USBPHY_PWD_RSVD1_SHIFT (13U)
43130 #define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
43131 #define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
43132 #define USBPHY_PWD_RXPWDENV_SHIFT (17U)
43133 #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
43134 #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
43135 #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
43136 #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
43137 #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
43138 #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
43139 #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
43140 #define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
43141 #define USBPHY_PWD_RXPWDRX_SHIFT (20U)
43142 #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
43143 #define USBPHY_PWD_RSVD2_MASK (0xFFE00000U)
43144 #define USBPHY_PWD_RSVD2_SHIFT (21U)
43145 #define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
43146
43150 #define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)
43151 #define USBPHY_PWD_SET_RSVD0_SHIFT (0U)
43152 #define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
43153 #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
43154 #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
43155 #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
43156 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
43157 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
43158 #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
43159 #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
43160 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
43161 #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
43162 #define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)
43163 #define USBPHY_PWD_SET_RSVD1_SHIFT (13U)
43164 #define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
43165 #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
43166 #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
43167 #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
43168 #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
43169 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
43170 #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
43171 #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
43172 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
43173 #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
43174 #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
43175 #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
43176 #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
43177 #define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)
43178 #define USBPHY_PWD_SET_RSVD2_SHIFT (21U)
43179 #define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
43180
43184 #define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)
43185 #define USBPHY_PWD_CLR_RSVD0_SHIFT (0U)
43186 #define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
43187 #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
43188 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
43189 #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
43190 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
43191 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
43192 #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
43193 #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
43194 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
43195 #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
43196 #define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)
43197 #define USBPHY_PWD_CLR_RSVD1_SHIFT (13U)
43198 #define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
43199 #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
43200 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
43201 #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
43202 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
43203 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
43204 #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
43205 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
43206 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
43207 #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
43208 #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
43209 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
43210 #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
43211 #define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)
43212 #define USBPHY_PWD_CLR_RSVD2_SHIFT (21U)
43213 #define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
43214
43218 #define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)
43219 #define USBPHY_PWD_TOG_RSVD0_SHIFT (0U)
43220 #define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
43221 #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
43222 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
43223 #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
43224 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
43225 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
43226 #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
43227 #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
43228 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
43229 #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
43230 #define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)
43231 #define USBPHY_PWD_TOG_RSVD1_SHIFT (13U)
43232 #define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
43233 #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
43234 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
43235 #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
43236 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
43237 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
43238 #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
43239 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
43240 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
43241 #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
43242 #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
43243 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
43244 #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
43245 #define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)
43246 #define USBPHY_PWD_TOG_RSVD2_SHIFT (21U)
43247 #define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
43248
43252 #define USBPHY_TX_D_CAL_MASK (0xFU)
43253 #define USBPHY_TX_D_CAL_SHIFT (0U)
43254 #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
43255 #define USBPHY_TX_RSVD0_MASK (0xF0U)
43256 #define USBPHY_TX_RSVD0_SHIFT (4U)
43257 #define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
43258 #define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
43259 #define USBPHY_TX_TXCAL45DN_SHIFT (8U)
43260 #define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
43261 #define USBPHY_TX_RSVD1_MASK (0xF000U)
43262 #define USBPHY_TX_RSVD1_SHIFT (12U)
43263 #define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
43264 #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
43265 #define USBPHY_TX_TXCAL45DP_SHIFT (16U)
43266 #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
43267 #define USBPHY_TX_RSVD2_MASK (0x3F00000U)
43268 #define USBPHY_TX_RSVD2_SHIFT (20U)
43269 #define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
43270 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
43271 #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
43272 #define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
43273 #define USBPHY_TX_RSVD5_MASK (0xE0000000U)
43274 #define USBPHY_TX_RSVD5_SHIFT (29U)
43275 #define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
43276
43280 #define USBPHY_TX_SET_D_CAL_MASK (0xFU)
43281 #define USBPHY_TX_SET_D_CAL_SHIFT (0U)
43282 #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
43283 #define USBPHY_TX_SET_RSVD0_MASK (0xF0U)
43284 #define USBPHY_TX_SET_RSVD0_SHIFT (4U)
43285 #define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
43286 #define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
43287 #define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
43288 #define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
43289 #define USBPHY_TX_SET_RSVD1_MASK (0xF000U)
43290 #define USBPHY_TX_SET_RSVD1_SHIFT (12U)
43291 #define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
43292 #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
43293 #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
43294 #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
43295 #define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)
43296 #define USBPHY_TX_SET_RSVD2_SHIFT (20U)
43297 #define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
43298 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
43299 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
43300 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
43301 #define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)
43302 #define USBPHY_TX_SET_RSVD5_SHIFT (29U)
43303 #define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
43304
43308 #define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
43309 #define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
43310 #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
43311 #define USBPHY_TX_CLR_RSVD0_MASK (0xF0U)
43312 #define USBPHY_TX_CLR_RSVD0_SHIFT (4U)
43313 #define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
43314 #define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
43315 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
43316 #define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
43317 #define USBPHY_TX_CLR_RSVD1_MASK (0xF000U)
43318 #define USBPHY_TX_CLR_RSVD1_SHIFT (12U)
43319 #define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
43320 #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
43321 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
43322 #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
43323 #define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)
43324 #define USBPHY_TX_CLR_RSVD2_SHIFT (20U)
43325 #define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
43326 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
43327 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
43328 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
43329 #define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)
43330 #define USBPHY_TX_CLR_RSVD5_SHIFT (29U)
43331 #define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
43332
43336 #define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
43337 #define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
43338 #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
43339 #define USBPHY_TX_TOG_RSVD0_MASK (0xF0U)
43340 #define USBPHY_TX_TOG_RSVD0_SHIFT (4U)
43341 #define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
43342 #define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
43343 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
43344 #define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
43345 #define USBPHY_TX_TOG_RSVD1_MASK (0xF000U)
43346 #define USBPHY_TX_TOG_RSVD1_SHIFT (12U)
43347 #define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
43348 #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
43349 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
43350 #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
43351 #define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)
43352 #define USBPHY_TX_TOG_RSVD2_SHIFT (20U)
43353 #define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
43354 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
43355 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
43356 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
43357 #define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)
43358 #define USBPHY_TX_TOG_RSVD5_SHIFT (29U)
43359 #define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
43360
43364 #define USBPHY_RX_ENVADJ_MASK (0x7U)
43365 #define USBPHY_RX_ENVADJ_SHIFT (0U)
43366 #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
43367 #define USBPHY_RX_RSVD0_MASK (0x8U)
43368 #define USBPHY_RX_RSVD0_SHIFT (3U)
43369 #define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
43370 #define USBPHY_RX_DISCONADJ_MASK (0x70U)
43371 #define USBPHY_RX_DISCONADJ_SHIFT (4U)
43372 #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
43373 #define USBPHY_RX_RSVD1_MASK (0x3FFF80U)
43374 #define USBPHY_RX_RSVD1_SHIFT (7U)
43375 #define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
43376 #define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
43377 #define USBPHY_RX_RXDBYPASS_SHIFT (22U)
43378 #define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
43379 #define USBPHY_RX_RSVD2_MASK (0xFF800000U)
43380 #define USBPHY_RX_RSVD2_SHIFT (23U)
43381 #define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
43382
43386 #define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
43387 #define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
43388 #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
43389 #define USBPHY_RX_SET_RSVD0_MASK (0x8U)
43390 #define USBPHY_RX_SET_RSVD0_SHIFT (3U)
43391 #define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
43392 #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
43393 #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
43394 #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
43395 #define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)
43396 #define USBPHY_RX_SET_RSVD1_SHIFT (7U)
43397 #define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
43398 #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
43399 #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
43400 #define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
43401 #define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)
43402 #define USBPHY_RX_SET_RSVD2_SHIFT (23U)
43403 #define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
43404
43408 #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
43409 #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
43410 #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
43411 #define USBPHY_RX_CLR_RSVD0_MASK (0x8U)
43412 #define USBPHY_RX_CLR_RSVD0_SHIFT (3U)
43413 #define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
43414 #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
43415 #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
43416 #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
43417 #define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)
43418 #define USBPHY_RX_CLR_RSVD1_SHIFT (7U)
43419 #define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
43420 #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
43421 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
43422 #define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
43423 #define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)
43424 #define USBPHY_RX_CLR_RSVD2_SHIFT (23U)
43425 #define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
43426
43430 #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
43431 #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
43432 #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
43433 #define USBPHY_RX_TOG_RSVD0_MASK (0x8U)
43434 #define USBPHY_RX_TOG_RSVD0_SHIFT (3U)
43435 #define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
43436 #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
43437 #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
43438 #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
43439 #define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)
43440 #define USBPHY_RX_TOG_RSVD1_SHIFT (7U)
43441 #define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
43442 #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
43443 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
43444 #define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
43445 #define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)
43446 #define USBPHY_RX_TOG_RSVD2_SHIFT (23U)
43447 #define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
43448
43452 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
43453 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
43454 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
43455 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
43456 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
43457 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
43458 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
43459 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
43460 #define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
43461 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
43462 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
43463 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
43464 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
43465 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
43466 #define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
43467 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
43468 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
43469 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
43470 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
43471 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
43472 #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
43473 #define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
43474 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
43475 #define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
43476 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
43477 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
43478 #define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
43479 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
43480 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
43481 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
43482 #define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
43483 #define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
43484 #define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
43485 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
43486 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
43487 #define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
43488 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
43489 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
43490 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
43491 #define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)
43492 #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)
43493 #define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
43494 #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
43495 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
43496 #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
43497 #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
43498 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
43499 #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
43500 #define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
43501 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
43502 #define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
43503 #define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
43504 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
43505 #define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
43506 #define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)
43507 #define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)
43508 #define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
43509 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
43510 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
43511 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
43512 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
43513 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
43514 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
43515 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
43516 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
43517 #define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
43518 #define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
43519 #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
43520 #define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
43521 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
43522 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
43523 #define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
43524 #define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
43525 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
43526 #define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
43527 #define USBPHY_CTRL_RSVD1_MASK (0x6000000U)
43528 #define USBPHY_CTRL_RSVD1_SHIFT (25U)
43529 #define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
43530 #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
43531 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
43532 #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
43533 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
43534 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
43535 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
43536 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
43537 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
43538 #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
43539 #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
43540 #define USBPHY_CTRL_CLKGATE_SHIFT (30U)
43541 #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
43542 #define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
43543 #define USBPHY_CTRL_SFTRST_SHIFT (31U)
43544 #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
43545
43549 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
43550 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
43551 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
43552 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
43553 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
43554 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
43555 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
43556 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
43557 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
43558 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
43559 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
43560 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
43561 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
43562 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
43563 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
43564 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
43565 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
43566 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
43567 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
43568 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
43569 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
43570 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
43571 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
43572 #define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
43573 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
43574 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
43575 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
43576 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
43577 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
43578 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
43579 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
43580 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
43581 #define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
43582 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
43583 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
43584 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
43585 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
43586 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
43587 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
43588 #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)
43589 #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)
43590 #define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
43591 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
43592 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
43593 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
43594 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
43595 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
43596 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
43597 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
43598 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
43599 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
43600 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
43601 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
43602 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
43603 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)
43604 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)
43605 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
43606 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
43607 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
43608 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
43609 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
43610 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
43611 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
43612 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
43613 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
43614 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
43615 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
43616 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
43617 #define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
43618 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
43619 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
43620 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
43621 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
43622 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
43623 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
43624 #define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)
43625 #define USBPHY_CTRL_SET_RSVD1_SHIFT (25U)
43626 #define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
43627 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
43628 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
43629 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
43630 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
43631 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
43632 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
43633 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
43634 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
43635 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
43636 #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
43637 #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
43638 #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
43639 #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
43640 #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
43641 #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
43642
43646 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
43647 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
43648 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
43649 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
43650 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
43651 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
43652 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
43653 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
43654 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
43655 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
43656 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
43657 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
43658 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
43659 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
43660 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
43661 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
43662 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
43663 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
43664 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
43665 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
43666 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
43667 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
43668 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
43669 #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
43670 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
43671 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
43672 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
43673 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
43674 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
43675 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
43676 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
43677 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
43678 #define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
43679 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
43680 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
43681 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
43682 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
43683 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
43684 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
43685 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)
43686 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)
43687 #define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
43688 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
43689 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
43690 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
43691 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
43692 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
43693 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
43694 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
43695 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
43696 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
43697 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
43698 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
43699 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
43700 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)
43701 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)
43702 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
43703 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
43704 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
43705 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
43706 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
43707 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
43708 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
43709 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
43710 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
43711 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
43712 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
43713 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
43714 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
43715 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
43716 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
43717 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
43718 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
43719 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
43720 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
43721 #define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)
43722 #define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)
43723 #define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
43724 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
43725 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
43726 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
43727 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
43728 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
43729 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
43730 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
43731 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
43732 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
43733 #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
43734 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
43735 #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
43736 #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
43737 #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
43738 #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
43739
43743 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
43744 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
43745 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
43746 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
43747 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
43748 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
43749 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
43750 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
43751 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
43752 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
43753 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
43754 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
43755 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
43756 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
43757 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
43758 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
43759 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
43760 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
43761 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
43762 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
43763 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
43764 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
43765 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
43766 #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
43767 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
43768 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
43769 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
43770 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
43771 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
43772 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
43773 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
43774 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
43775 #define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
43776 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
43777 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
43778 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
43779 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
43780 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
43781 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
43782 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)
43783 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)
43784 #define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
43785 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
43786 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
43787 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
43788 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
43789 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
43790 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
43791 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
43792 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
43793 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
43794 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
43795 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
43796 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
43797 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)
43798 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)
43799 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
43800 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
43801 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
43802 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
43803 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
43804 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
43805 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
43806 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
43807 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
43808 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
43809 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
43810 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
43811 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
43812 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
43813 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
43814 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
43815 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
43816 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
43817 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
43818 #define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)
43819 #define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)
43820 #define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
43821 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
43822 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
43823 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
43824 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
43825 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
43826 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
43827 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
43828 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
43829 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
43830 #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
43831 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
43832 #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
43833 #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
43834 #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
43835 #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
43836
43840 #define USBPHY_STATUS_RSVD0_MASK (0x7U)
43841 #define USBPHY_STATUS_RSVD0_SHIFT (0U)
43842 #define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
43843 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
43844 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
43845 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
43846 #define USBPHY_STATUS_RSVD1_MASK (0x30U)
43847 #define USBPHY_STATUS_RSVD1_SHIFT (4U)
43848 #define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
43849 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
43850 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
43851 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
43852 #define USBPHY_STATUS_RSVD2_MASK (0x80U)
43853 #define USBPHY_STATUS_RSVD2_SHIFT (7U)
43854 #define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
43855 #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
43856 #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
43857 #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
43858 #define USBPHY_STATUS_RSVD3_MASK (0x200U)
43859 #define USBPHY_STATUS_RSVD3_SHIFT (9U)
43860 #define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
43861 #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
43862 #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
43863 #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
43864 #define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)
43865 #define USBPHY_STATUS_RSVD4_SHIFT (11U)
43866 #define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
43867
43871 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
43872 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
43873 #define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
43874 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
43875 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
43876 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
43877 #define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
43878 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
43879 #define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
43880 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
43881 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
43882 #define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
43883 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U)
43884 #define USBPHY_DEBUG_RSVD0_SHIFT (6U)
43885 #define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
43886 #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
43887 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
43888 #define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
43889 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
43890 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
43891 #define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
43892 #define USBPHY_DEBUG_RSVD1_MASK (0xE000U)
43893 #define USBPHY_DEBUG_RSVD1_SHIFT (13U)
43894 #define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
43895 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
43896 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
43897 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
43898 #define USBPHY_DEBUG_RSVD2_MASK (0xE00000U)
43899 #define USBPHY_DEBUG_RSVD2_SHIFT (21U)
43900 #define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
43901 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
43902 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
43903 #define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
43904 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
43905 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
43906 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
43907 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
43908 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
43909 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
43910 #define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
43911 #define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
43912 #define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
43913 #define USBPHY_DEBUG_RSVD3_MASK (0x80000000U)
43914 #define USBPHY_DEBUG_RSVD3_SHIFT (31U)
43915 #define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
43916
43920 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
43921 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
43922 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
43923 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
43924 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
43925 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
43926 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
43927 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
43928 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
43929 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
43930 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
43931 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
43932 #define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)
43933 #define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)
43934 #define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
43935 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
43936 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
43937 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
43938 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
43939 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
43940 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
43941 #define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)
43942 #define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)
43943 #define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
43944 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
43945 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
43946 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
43947 #define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)
43948 #define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)
43949 #define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
43950 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
43951 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
43952 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
43953 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
43954 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
43955 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
43956 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
43957 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
43958 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
43959 #define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
43960 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
43961 #define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
43962 #define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)
43963 #define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)
43964 #define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
43965
43969 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
43970 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
43971 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
43972 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
43973 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
43974 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
43975 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
43976 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
43977 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
43978 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
43979 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
43980 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
43981 #define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)
43982 #define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)
43983 #define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
43984 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
43985 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
43986 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
43987 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
43988 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
43989 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
43990 #define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)
43991 #define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)
43992 #define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
43993 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
43994 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
43995 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
43996 #define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)
43997 #define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)
43998 #define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
43999 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
44000 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
44001 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
44002 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
44003 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
44004 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
44005 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
44006 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
44007 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
44008 #define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
44009 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
44010 #define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
44011 #define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)
44012 #define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)
44013 #define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
44014
44018 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
44019 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
44020 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
44021 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
44022 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
44023 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
44024 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
44025 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
44026 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
44027 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
44028 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
44029 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
44030 #define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)
44031 #define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)
44032 #define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
44033 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
44034 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
44035 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
44036 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
44037 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
44038 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
44039 #define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)
44040 #define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)
44041 #define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
44042 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
44043 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
44044 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
44045 #define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)
44046 #define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)
44047 #define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
44048 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
44049 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
44050 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
44051 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
44052 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
44053 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
44054 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
44055 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
44056 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
44057 #define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
44058 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
44059 #define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
44060 #define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)
44061 #define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)
44062 #define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
44063
44067 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
44068 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
44069 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
44070 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
44071 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
44072 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
44073 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
44074 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
44075 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
44076
44080 #define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)
44081 #define USBPHY_DEBUG1_RSVD0_SHIFT (0U)
44082 #define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
44083 #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
44084 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
44085 #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
44086 #define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)
44087 #define USBPHY_DEBUG1_RSVD1_SHIFT (15U)
44088 #define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
44089
44093 #define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)
44094 #define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)
44095 #define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
44096 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
44097 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
44098 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
44099 #define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)
44100 #define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)
44101 #define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
44102
44106 #define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)
44107 #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)
44108 #define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
44109 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
44110 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
44111 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
44112 #define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)
44113 #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)
44114 #define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
44115
44119 #define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)
44120 #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)
44121 #define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
44122 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
44123 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
44124 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
44125 #define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)
44126 #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)
44127 #define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
44128
44132 #define USBPHY_VERSION_STEP_MASK (0xFFFFU)
44133 #define USBPHY_VERSION_STEP_SHIFT (0U)
44134 #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
44135 #define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
44136 #define USBPHY_VERSION_MINOR_SHIFT (16U)
44137 #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
44138 #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
44139 #define USBPHY_VERSION_MAJOR_SHIFT (24U)
44140 #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
44141 /* end of group USBPHY_Register_Masks */
44147
44148
44149 /* USBPHY - Peripheral instance base addresses */
44151 #define USBPHY1_BASE (0x400D9000u)
44152
44153 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
44154
44155 #define USBPHY2_BASE (0x400DA000u)
44156
44157 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
44158
44159 #define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
44160
44161 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
44162
44163 #define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
44164 /* Backward compatibility */
44165 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
44166 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
44167 #define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
44168 #define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
44169 #define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
44170 #define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
44171
44172 /* end of group USBPHY_Peripheral_Access_Layer */
44176
44177
44178 /* ----------------------------------------------------------------------------
44179 -- USB_ANALOG Peripheral Access Layer
44180 ---------------------------------------------------------------------------- */
44181
44188 typedef struct {
44189 uint8_t RESERVED_0[416];
44190 struct { /* offset: 0x1A0, array step: 0x60 */
44191 __IO uint32_t VBUS_DETECT;
44192 __IO uint32_t VBUS_DETECT_SET;
44193 __IO uint32_t VBUS_DETECT_CLR;
44194 __IO uint32_t VBUS_DETECT_TOG;
44195 __IO uint32_t CHRG_DETECT;
44196 __IO uint32_t CHRG_DETECT_SET;
44197 __IO uint32_t CHRG_DETECT_CLR;
44198 __IO uint32_t CHRG_DETECT_TOG;
44199 __I uint32_t VBUS_DETECT_STAT;
44200 uint8_t RESERVED_0[12];
44201 __I uint32_t CHRG_DETECT_STAT;
44202 uint8_t RESERVED_1[12];
44203 __IO uint32_t LOOPBACK;
44204 __IO uint32_t LOOPBACK_SET;
44205 __IO uint32_t LOOPBACK_CLR;
44206 __IO uint32_t LOOPBACK_TOG;
44207 __IO uint32_t MISC;
44208 __IO uint32_t MISC_SET;
44209 __IO uint32_t MISC_CLR;
44210 __IO uint32_t MISC_TOG;
44211 } INSTANCE[2];
44212 __I uint32_t DIGPROG;
44213 } USB_ANALOG_Type;
44214
44215 /* ----------------------------------------------------------------------------
44216 -- USB_ANALOG Register Masks
44217 ---------------------------------------------------------------------------- */
44218
44226 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
44227 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
44228
44238 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
44239 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
44240 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
44241 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
44242 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
44243 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
44244 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
44245 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)
44246 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
44247 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
44248
44250 /* The count of USB_ANALOG_VBUS_DETECT */
44251 #define USB_ANALOG_VBUS_DETECT_COUNT (2U)
44252
44255 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
44256 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
44257
44267 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
44268 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
44269 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
44270 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
44271 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
44272 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
44273 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
44274 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
44275 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
44276 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
44277
44279 /* The count of USB_ANALOG_VBUS_DETECT_SET */
44280 #define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)
44281
44284 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
44285 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
44286
44296 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
44297 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
44298 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
44299 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
44300 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
44301 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
44302 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
44303 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
44304 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
44305 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
44306
44308 /* The count of USB_ANALOG_VBUS_DETECT_CLR */
44309 #define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)
44310
44313 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
44314 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
44315
44325 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
44326 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
44327 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
44328 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
44329 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
44330 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
44331 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
44332 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
44333 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
44334 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
44335
44337 /* The count of USB_ANALOG_VBUS_DETECT_TOG */
44338 #define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)
44339
44342 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
44343 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
44344
44348 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
44349 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)
44350 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
44351
44355 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
44356 #define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)
44357 #define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)
44358
44362 #define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
44363
44365 /* The count of USB_ANALOG_CHRG_DETECT */
44366 #define USB_ANALOG_CHRG_DETECT_COUNT (2U)
44367
44370 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
44371 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
44372
44376 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
44377 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
44378 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
44379
44383 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
44384 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)
44385 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)
44386
44390 #define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
44391
44393 /* The count of USB_ANALOG_CHRG_DETECT_SET */
44394 #define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)
44395
44398 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
44399 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
44400
44404 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
44405 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
44406 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
44407
44411 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
44412 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)
44413 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)
44414
44418 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
44419
44421 /* The count of USB_ANALOG_CHRG_DETECT_CLR */
44422 #define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)
44423
44426 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
44427 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
44428
44432 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
44433 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
44434 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
44435
44439 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
44440 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)
44441 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)
44442
44446 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
44447
44449 /* The count of USB_ANALOG_CHRG_DETECT_TOG */
44450 #define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)
44451
44454 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
44455 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
44456 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
44457 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)
44458 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
44459 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
44460 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)
44461 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
44462 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
44463 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
44464 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
44465 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
44466
44468 /* The count of USB_ANALOG_VBUS_DETECT_STAT */
44469 #define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)
44470
44473 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
44474 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
44475
44479 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
44480 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
44481 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
44482
44486 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
44487 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
44488 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
44489 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
44490 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
44491 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
44492 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
44493
44495 /* The count of USB_ANALOG_CHRG_DETECT_STAT */
44496 #define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)
44497
44500 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
44501 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
44502 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
44503
44505 /* The count of USB_ANALOG_LOOPBACK */
44506 #define USB_ANALOG_LOOPBACK_COUNT (2U)
44507
44510 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
44511 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
44512 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
44513
44515 /* The count of USB_ANALOG_LOOPBACK_SET */
44516 #define USB_ANALOG_LOOPBACK_SET_COUNT (2U)
44517
44520 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
44521 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
44522 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
44523
44525 /* The count of USB_ANALOG_LOOPBACK_CLR */
44526 #define USB_ANALOG_LOOPBACK_CLR_COUNT (2U)
44527
44530 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
44531 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
44532 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
44533
44535 /* The count of USB_ANALOG_LOOPBACK_TOG */
44536 #define USB_ANALOG_LOOPBACK_TOG_COUNT (2U)
44537
44540 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)
44541 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)
44542 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
44543 #define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)
44544 #define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)
44545 #define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
44546 #define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)
44547 #define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)
44548 #define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
44549
44551 /* The count of USB_ANALOG_MISC */
44552 #define USB_ANALOG_MISC_COUNT (2U)
44553
44556 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
44557 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
44558 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
44559 #define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)
44560 #define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)
44561 #define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
44562 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)
44563 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)
44564 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
44565
44567 /* The count of USB_ANALOG_MISC_SET */
44568 #define USB_ANALOG_MISC_SET_COUNT (2U)
44569
44572 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
44573 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
44574 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
44575 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)
44576 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)
44577 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
44578 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)
44579 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)
44580 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
44581
44583 /* The count of USB_ANALOG_MISC_CLR */
44584 #define USB_ANALOG_MISC_CLR_COUNT (2U)
44585
44588 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
44589 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
44590 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
44591 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)
44592 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)
44593 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
44594 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)
44595 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)
44596 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
44597
44599 /* The count of USB_ANALOG_MISC_TOG */
44600 #define USB_ANALOG_MISC_TOG_COUNT (2U)
44601
44604 #define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
44605 #define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
44606
44609 #define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)
44610 /* end of group USB_ANALOG_Register_Masks */
44616
44617
44618 /* USB_ANALOG - Peripheral instance base addresses */
44620 #define USB_ANALOG_BASE (0x400D8000u)
44621
44622 #define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)
44623
44624 #define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }
44625
44626 #define USB_ANALOG_BASE_PTRS { USB_ANALOG }
44627 /* end of group USB_ANALOG_Peripheral_Access_Layer */
44631
44632
44633 /* ----------------------------------------------------------------------------
44634 -- USDHC Peripheral Access Layer
44635 ---------------------------------------------------------------------------- */
44636
44643 typedef struct {
44644 __IO uint32_t DS_ADDR;
44645 __IO uint32_t BLK_ATT;
44646 __IO uint32_t CMD_ARG;
44647 __IO uint32_t CMD_XFR_TYP;
44648 __I uint32_t CMD_RSP0;
44649 __I uint32_t CMD_RSP1;
44650 __I uint32_t CMD_RSP2;
44651 __I uint32_t CMD_RSP3;
44652 __IO uint32_t DATA_BUFF_ACC_PORT;
44653 __I uint32_t PRES_STATE;
44654 __IO uint32_t PROT_CTRL;
44655 __IO uint32_t SYS_CTRL;
44656 __IO uint32_t INT_STATUS;
44657 __IO uint32_t INT_STATUS_EN;
44658 __IO uint32_t INT_SIGNAL_EN;
44659 __IO uint32_t AUTOCMD12_ERR_STATUS;
44660 __IO uint32_t HOST_CTRL_CAP;
44661 __IO uint32_t WTMK_LVL;
44662 __IO uint32_t MIX_CTRL;
44663 uint8_t RESERVED_0[4];
44664 __O uint32_t FORCE_EVENT;
44665 __I uint32_t ADMA_ERR_STATUS;
44666 __IO uint32_t ADMA_SYS_ADDR;
44667 uint8_t RESERVED_1[4];
44668 __IO uint32_t DLL_CTRL;
44669 __I uint32_t DLL_STATUS;
44670 __IO uint32_t CLK_TUNE_CTRL_STATUS;
44671 uint8_t RESERVED_2[84];
44672 __IO uint32_t VEND_SPEC;
44673 __IO uint32_t MMC_BOOT;
44674 __IO uint32_t VEND_SPEC2;
44675 __IO uint32_t TUNING_CTRL;
44676 } USDHC_Type;
44677
44678 /* ----------------------------------------------------------------------------
44679 -- USDHC Register Masks
44680 ---------------------------------------------------------------------------- */
44681
44689 #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
44690 #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
44691
44693 #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
44694
44698 #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
44699 #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
44700
44711 #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
44712 #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
44713 #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
44714
44720 #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
44721
44725 #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
44726 #define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
44727
44729 #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
44730
44734 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
44735 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
44736
44742 #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
44743 #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
44744 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
44745
44749 #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
44750 #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
44751 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
44752
44756 #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
44757 #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
44758 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
44759
44763 #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
44764 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
44765 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
44766
44772 #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
44773 #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
44774 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
44775
44777 #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
44778
44782 #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
44783 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
44784
44786 #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
44787
44791 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
44792 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
44793
44795 #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
44796
44800 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
44801 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
44802
44804 #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
44805
44809 #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
44810 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
44811
44813 #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
44814
44818 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
44819 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
44820
44822 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
44823
44827 #define USDHC_PRES_STATE_CIHB_MASK (0x1U)
44828 #define USDHC_PRES_STATE_CIHB_SHIFT (0U)
44829
44833 #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
44834 #define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
44835 #define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
44836
44840 #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
44841 #define USDHC_PRES_STATE_DLA_MASK (0x4U)
44842 #define USDHC_PRES_STATE_DLA_SHIFT (2U)
44843
44847 #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
44848 #define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
44849 #define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
44850
44854 #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
44855 #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
44856 #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
44857
44861 #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
44862 #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
44863 #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
44864
44868 #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
44869 #define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
44870 #define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
44871
44875 #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
44876 #define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
44877 #define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
44878
44882 #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
44883 #define USDHC_PRES_STATE_WTA_MASK (0x100U)
44884 #define USDHC_PRES_STATE_WTA_SHIFT (8U)
44885
44889 #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
44890 #define USDHC_PRES_STATE_RTA_MASK (0x200U)
44891 #define USDHC_PRES_STATE_RTA_SHIFT (9U)
44892
44896 #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
44897 #define USDHC_PRES_STATE_BWEN_MASK (0x400U)
44898 #define USDHC_PRES_STATE_BWEN_SHIFT (10U)
44899
44903 #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
44904 #define USDHC_PRES_STATE_BREN_MASK (0x800U)
44905 #define USDHC_PRES_STATE_BREN_SHIFT (11U)
44906
44910 #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
44911 #define USDHC_PRES_STATE_RTR_MASK (0x1000U)
44912 #define USDHC_PRES_STATE_RTR_SHIFT (12U)
44913
44917 #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
44918 #define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
44919 #define USDHC_PRES_STATE_TSCD_SHIFT (15U)
44920
44924 #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
44925 #define USDHC_PRES_STATE_CINST_MASK (0x10000U)
44926 #define USDHC_PRES_STATE_CINST_SHIFT (16U)
44927
44931 #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
44932 #define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
44933 #define USDHC_PRES_STATE_CDPL_SHIFT (18U)
44934
44938 #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
44939 #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
44940 #define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
44941
44945 #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
44946 #define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
44947 #define USDHC_PRES_STATE_CLSL_SHIFT (23U)
44948
44950 #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
44951 #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
44952 #define USDHC_PRES_STATE_DLSL_SHIFT (24U)
44953
44963 #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
44964
44968 #define USDHC_PROT_CTRL_LCTL_MASK (0x1U)
44969 #define USDHC_PROT_CTRL_LCTL_SHIFT (0U)
44970
44974 #define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
44975 #define USDHC_PROT_CTRL_DTW_MASK (0x6U)
44976 #define USDHC_PROT_CTRL_DTW_SHIFT (1U)
44977
44983 #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
44984 #define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
44985 #define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
44986
44990 #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
44991 #define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
44992 #define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
44993
44999 #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
45000 #define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
45001 #define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
45002
45006 #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
45007 #define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
45008 #define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
45009
45013 #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
45014 #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
45015 #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
45016
45022 #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
45023 #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
45024 #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
45025
45029 #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
45030 #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
45031 #define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
45032
45036 #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
45037 #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
45038 #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
45039
45043 #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
45044 #define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
45045 #define USDHC_PROT_CTRL_IABG_SHIFT (19U)
45046
45050 #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
45051 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
45052 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
45053
45055 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
45056 #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
45057 #define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
45058
45062 #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
45063 #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
45064 #define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
45065
45069 #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
45070 #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
45071 #define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
45072
45076 #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
45077 #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
45078 #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
45079
45084 #define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
45085 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
45086 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
45087
45091 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
45092
45096 #define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
45097 #define USDHC_SYS_CTRL_DVS_SHIFT (4U)
45098
45104 #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
45105 #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
45106 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
45107
45109 #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
45110 #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
45111 #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
45112
45119 #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
45120 #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
45121 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
45122
45124 #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
45125 #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
45126 #define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
45127
45131 #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
45132 #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
45133 #define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
45134
45138 #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
45139 #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
45140 #define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
45141
45145 #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
45146 #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
45147 #define USDHC_SYS_CTRL_INITA_SHIFT (27U)
45148
45150 #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
45151 #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
45152 #define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
45153
45155 #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
45156
45160 #define USDHC_INT_STATUS_CC_MASK (0x1U)
45161 #define USDHC_INT_STATUS_CC_SHIFT (0U)
45162
45166 #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
45167 #define USDHC_INT_STATUS_TC_MASK (0x2U)
45168 #define USDHC_INT_STATUS_TC_SHIFT (1U)
45169
45173 #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
45174 #define USDHC_INT_STATUS_BGE_MASK (0x4U)
45175 #define USDHC_INT_STATUS_BGE_SHIFT (2U)
45176
45180 #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
45181 #define USDHC_INT_STATUS_DINT_MASK (0x8U)
45182 #define USDHC_INT_STATUS_DINT_SHIFT (3U)
45183
45187 #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
45188 #define USDHC_INT_STATUS_BWR_MASK (0x10U)
45189 #define USDHC_INT_STATUS_BWR_SHIFT (4U)
45190
45194 #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
45195 #define USDHC_INT_STATUS_BRR_MASK (0x20U)
45196 #define USDHC_INT_STATUS_BRR_SHIFT (5U)
45197
45201 #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
45202 #define USDHC_INT_STATUS_CINS_MASK (0x40U)
45203 #define USDHC_INT_STATUS_CINS_SHIFT (6U)
45204
45208 #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
45209 #define USDHC_INT_STATUS_CRM_MASK (0x80U)
45210 #define USDHC_INT_STATUS_CRM_SHIFT (7U)
45211
45215 #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
45216 #define USDHC_INT_STATUS_CINT_MASK (0x100U)
45217 #define USDHC_INT_STATUS_CINT_SHIFT (8U)
45218
45222 #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
45223 #define USDHC_INT_STATUS_RTE_MASK (0x1000U)
45224 #define USDHC_INT_STATUS_RTE_SHIFT (12U)
45225
45229 #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
45230 #define USDHC_INT_STATUS_TP_MASK (0x4000U)
45231 #define USDHC_INT_STATUS_TP_SHIFT (14U)
45232
45234 #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
45235 #define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
45236 #define USDHC_INT_STATUS_CTOE_SHIFT (16U)
45237
45241 #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
45242 #define USDHC_INT_STATUS_CCE_MASK (0x20000U)
45243 #define USDHC_INT_STATUS_CCE_SHIFT (17U)
45244
45248 #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
45249 #define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
45250 #define USDHC_INT_STATUS_CEBE_SHIFT (18U)
45251
45255 #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
45256 #define USDHC_INT_STATUS_CIE_MASK (0x80000U)
45257 #define USDHC_INT_STATUS_CIE_SHIFT (19U)
45258
45262 #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
45263 #define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
45264 #define USDHC_INT_STATUS_DTOE_SHIFT (20U)
45265
45269 #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
45270 #define USDHC_INT_STATUS_DCE_MASK (0x200000U)
45271 #define USDHC_INT_STATUS_DCE_SHIFT (21U)
45272
45276 #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
45277 #define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
45278 #define USDHC_INT_STATUS_DEBE_SHIFT (22U)
45279
45283 #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
45284 #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
45285 #define USDHC_INT_STATUS_AC12E_SHIFT (24U)
45286
45290 #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
45291 #define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
45292 #define USDHC_INT_STATUS_TNE_SHIFT (26U)
45293
45295 #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
45296 #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
45297 #define USDHC_INT_STATUS_DMAE_SHIFT (28U)
45298
45302 #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
45303
45307 #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
45308 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
45309
45313 #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
45314 #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
45315 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
45316
45320 #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
45321 #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
45322 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
45323
45327 #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
45328 #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
45329 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
45330
45334 #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
45335 #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
45336 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
45337
45341 #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
45342 #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
45343 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
45344
45348 #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
45349 #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
45350 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
45351
45355 #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
45356 #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
45357 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
45358
45362 #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
45363 #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
45364 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
45365
45369 #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
45370 #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
45371 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
45372
45376 #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
45377 #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
45378 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
45379
45383 #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
45384 #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
45385 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
45386
45390 #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
45391 #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
45392 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
45393
45397 #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
45398 #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
45399 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
45400
45404 #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
45405 #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
45406 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
45407
45411 #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
45412 #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
45413 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
45414
45418 #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
45419 #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
45420 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
45421
45425 #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
45426 #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
45427 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
45428
45432 #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
45433 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
45434 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
45435
45439 #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
45440 #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
45441 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
45442
45446 #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
45447 #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
45448 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
45449
45453 #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
45454
45458 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
45459 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
45460
45464 #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
45465 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
45466 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
45467
45471 #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
45472 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
45473 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
45474
45478 #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
45479 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
45480 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
45481
45485 #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
45486 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
45487 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
45488
45492 #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
45493 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
45494 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
45495
45499 #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
45500 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
45501 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
45502
45506 #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
45507 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
45508 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
45509
45513 #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
45514 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
45515 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
45516
45520 #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
45521 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
45522 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
45523
45527 #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
45528 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
45529 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
45530
45534 #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
45535 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
45536 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
45537
45541 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
45542 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
45543 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
45544
45548 #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
45549 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
45550 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
45551
45555 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
45556 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
45557 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
45558
45562 #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
45563 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
45564 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
45565
45569 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
45570 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
45571 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
45572
45576 #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
45577 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
45578 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
45579
45583 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
45584 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
45585 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
45586
45590 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
45591 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
45592 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
45593
45597 #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
45598 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
45599 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
45600
45604 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
45605
45609 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
45610 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
45611
45615 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
45616 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
45617 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
45618
45622 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
45623 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
45624 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
45625
45629 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
45630 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
45631 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
45632
45636 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
45637 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
45638 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
45639
45643 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
45644 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
45645 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
45646
45650 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
45651 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
45652 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
45653
45655 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
45656 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
45657 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
45658
45662 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
45663
45667 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
45668 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
45669
45671 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
45672 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
45673 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
45674
45676 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
45677 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
45678 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
45679
45681 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
45682 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
45683 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
45684
45686 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
45687 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
45688 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
45689
45693 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
45694 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
45695 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
45696
45702 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
45703 #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
45704 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
45705
45711 #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
45712 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
45713 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
45714
45718 #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
45719 #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
45720 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
45721
45725 #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
45726 #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
45727 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
45728
45732 #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
45733 #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
45734 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
45735
45739 #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
45740 #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
45741 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
45742
45746 #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
45747 #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
45748 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
45749
45753 #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
45754 #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
45755 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
45756
45760 #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
45761
45765 #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
45766 #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
45767
45769 #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
45770 #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
45771 #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
45772
45774 #define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
45775 #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
45776 #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
45777
45779 #define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
45780 #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
45781 #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
45782
45784 #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
45785
45789 #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
45790 #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
45791
45795 #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
45796 #define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
45797 #define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
45798
45802 #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
45803 #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
45804 #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
45805
45809 #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
45810 #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
45811 #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
45812
45814 #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
45815 #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
45816 #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
45817
45821 #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
45822 #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
45823 #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
45824
45828 #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
45829 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
45830 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
45831
45833 #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
45834 #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
45835 #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
45836
45838 #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
45839 #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
45840 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
45841
45845 #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
45846 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
45847 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
45848
45852 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
45853 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
45854 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
45855
45859 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
45860 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
45861 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
45862
45866 #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
45867
45871 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
45872 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
45873
45875 #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
45876 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
45877 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
45878
45880 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
45881 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
45882 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
45883
45885 #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
45886 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
45887 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
45888
45890 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
45891 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
45892 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
45893
45895 #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
45896 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
45897 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
45898
45900 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
45901 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
45902 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
45903
45905 #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
45906 #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
45907 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
45908
45910 #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
45911 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
45912 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
45913
45915 #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
45916 #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
45917 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
45918
45920 #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
45921 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
45922 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
45923
45925 #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
45926 #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
45927 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
45928
45930 #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
45931 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
45932 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
45933
45935 #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
45936 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
45937 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
45938
45940 #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
45941 #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
45942 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
45943
45945 #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
45946 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
45947 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
45948
45950 #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
45951 #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
45952 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
45953
45955 #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
45956
45960 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
45961 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
45962
45964 #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
45965 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
45966 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
45967
45971 #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
45972 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
45973 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
45974
45978 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
45979
45983 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
45984 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
45985
45987 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
45988
45992 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
45993 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
45994
45996 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
45997 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
45998 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
45999
46001 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
46002 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
46003 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
46004
46006 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
46007 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
46008 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
46009
46011 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
46012 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
46013 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
46014
46016 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
46017 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
46018 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
46019
46021 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
46022 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
46023 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
46024
46026 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
46027 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
46028 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
46029
46031 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
46032 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
46033 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
46034
46036 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
46037 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
46038 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
46039
46041 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
46042
46046 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
46047 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
46048
46050 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
46051 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
46052 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
46053
46055 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
46056 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
46057 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
46058
46060 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
46061 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
46062 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
46063
46065 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
46066
46070 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
46071 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
46072
46074 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
46075 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
46076 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
46077
46079 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
46080 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
46081 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
46082
46084 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
46085 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
46086 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
46087
46089 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
46090 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
46091 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
46092
46094 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
46095 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
46096 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
46097
46099 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
46100 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
46101 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
46102
46104 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
46105 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
46106 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
46107
46109 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
46110
46114 #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
46115 #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
46116
46120 #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
46121 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
46122 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
46123
46127 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
46128 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
46129 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
46130
46134 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
46135 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
46136 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
46137
46141 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
46142 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
46143 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
46144
46148 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
46149 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
46150 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
46151
46155 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
46156
46160 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
46161 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
46162
46174 #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
46175 #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
46176 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
46177
46181 #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
46182 #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
46183 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
46184
46188 #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
46189 #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
46190 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
46191
46195 #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
46196 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
46197 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
46198
46200 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
46201 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
46202 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
46203
46207 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
46208 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
46209 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
46210
46212 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
46213
46217 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
46218 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
46219
46223 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
46224 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
46225 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
46226
46228 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
46229 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
46230 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
46231
46233 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
46234 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
46235 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
46236
46240 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
46241 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
46242 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
46243
46247 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
46248 #define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U)
46249 #define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U)
46250
46252 #define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
46253 #define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U)
46254 #define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U)
46255
46257 #define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)
46258
46262 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
46263 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
46264
46266 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
46267 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
46268 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
46269
46271 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
46272 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
46273 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
46274
46276 #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
46277 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
46278 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
46279
46281 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
46282 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
46283 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
46284
46286 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
46287 /* end of group USDHC_Register_Masks */
46293
46294
46295 /* USDHC - Peripheral instance base addresses */
46297 #define USDHC1_BASE (0x402C0000u)
46298
46299 #define USDHC1 ((USDHC_Type *)USDHC1_BASE)
46300
46301 #define USDHC2_BASE (0x402C4000u)
46302
46303 #define USDHC2 ((USDHC_Type *)USDHC2_BASE)
46304
46305 #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
46306
46307 #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
46308
46309 #define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
46310 /* end of group USDHC_Peripheral_Access_Layer */
46314
46315
46316 /* ----------------------------------------------------------------------------
46317 -- WDOG Peripheral Access Layer
46318 ---------------------------------------------------------------------------- */
46319
46326 typedef struct {
46327 __IO uint16_t WCR;
46328 __IO uint16_t WSR;
46329 __I uint16_t WRSR;
46330 __IO uint16_t WICR;
46331 __IO uint16_t WMCR;
46332 } WDOG_Type;
46333
46334 /* ----------------------------------------------------------------------------
46335 -- WDOG Register Masks
46336 ---------------------------------------------------------------------------- */
46337
46345 #define WDOG_WCR_WDZST_MASK (0x1U)
46346 #define WDOG_WCR_WDZST_SHIFT (0U)
46347
46351 #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
46352 #define WDOG_WCR_WDBG_MASK (0x2U)
46353 #define WDOG_WCR_WDBG_SHIFT (1U)
46354
46358 #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
46359 #define WDOG_WCR_WDE_MASK (0x4U)
46360 #define WDOG_WCR_WDE_SHIFT (2U)
46361
46365 #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
46366 #define WDOG_WCR_WDT_MASK (0x8U)
46367 #define WDOG_WCR_WDT_SHIFT (3U)
46368
46372 #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
46373 #define WDOG_WCR_SRS_MASK (0x10U)
46374 #define WDOG_WCR_SRS_SHIFT (4U)
46375
46379 #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
46380 #define WDOG_WCR_WDA_MASK (0x20U)
46381 #define WDOG_WCR_WDA_SHIFT (5U)
46382
46386 #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
46387 #define WDOG_WCR_SRE_MASK (0x40U)
46388 #define WDOG_WCR_SRE_SHIFT (6U)
46389
46393 #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
46394 #define WDOG_WCR_WDW_MASK (0x80U)
46395 #define WDOG_WCR_WDW_SHIFT (7U)
46396
46400 #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
46401 #define WDOG_WCR_WT_MASK (0xFF00U)
46402 #define WDOG_WCR_WT_SHIFT (8U)
46403
46410 #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
46411
46415 #define WDOG_WSR_WSR_MASK (0xFFFFU)
46416 #define WDOG_WSR_WSR_SHIFT (0U)
46417
46421 #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
46422
46426 #define WDOG_WRSR_SFTW_MASK (0x1U)
46427 #define WDOG_WRSR_SFTW_SHIFT (0U)
46428
46432 #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
46433 #define WDOG_WRSR_TOUT_MASK (0x2U)
46434 #define WDOG_WRSR_TOUT_SHIFT (1U)
46435
46439 #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
46440 #define WDOG_WRSR_POR_MASK (0x10U)
46441 #define WDOG_WRSR_POR_SHIFT (4U)
46442
46446 #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
46447
46451 #define WDOG_WICR_WICT_MASK (0xFFU)
46452 #define WDOG_WICR_WICT_SHIFT (0U)
46453
46459 #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
46460 #define WDOG_WICR_WTIS_MASK (0x4000U)
46461 #define WDOG_WICR_WTIS_SHIFT (14U)
46462
46466 #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
46467 #define WDOG_WICR_WIE_MASK (0x8000U)
46468 #define WDOG_WICR_WIE_SHIFT (15U)
46469
46473 #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
46474
46478 #define WDOG_WMCR_PDE_MASK (0x1U)
46479 #define WDOG_WMCR_PDE_SHIFT (0U)
46480
46484 #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
46485 /* end of group WDOG_Register_Masks */
46491
46492
46493 /* WDOG - Peripheral instance base addresses */
46495 #define WDOG1_BASE (0x400B8000u)
46496
46497 #define WDOG1 ((WDOG_Type *)WDOG1_BASE)
46498
46499 #define WDOG2_BASE (0x400D0000u)
46500
46501 #define WDOG2 ((WDOG_Type *)WDOG2_BASE)
46502
46503 #define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
46504
46505 #define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
46506
46507 #define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
46508 /* end of group WDOG_Peripheral_Access_Layer */
46512
46513
46514 /* ----------------------------------------------------------------------------
46515 -- XBARA Peripheral Access Layer
46516 ---------------------------------------------------------------------------- */
46517
46524 typedef struct {
46525 __IO uint16_t SEL0;
46526 __IO uint16_t SEL1;
46527 __IO uint16_t SEL2;
46528 __IO uint16_t SEL3;
46529 __IO uint16_t SEL4;
46530 __IO uint16_t SEL5;
46531 __IO uint16_t SEL6;
46532 __IO uint16_t SEL7;
46533 __IO uint16_t SEL8;
46534 __IO uint16_t SEL9;
46535 __IO uint16_t SEL10;
46536 __IO uint16_t SEL11;
46537 __IO uint16_t SEL12;
46538 __IO uint16_t SEL13;
46539 __IO uint16_t SEL14;
46540 __IO uint16_t SEL15;
46541 __IO uint16_t SEL16;
46542 __IO uint16_t SEL17;
46543 __IO uint16_t SEL18;
46544 __IO uint16_t SEL19;
46545 __IO uint16_t SEL20;
46546 __IO uint16_t SEL21;
46547 __IO uint16_t SEL22;
46548 __IO uint16_t SEL23;
46549 __IO uint16_t SEL24;
46550 __IO uint16_t SEL25;
46551 __IO uint16_t SEL26;
46552 __IO uint16_t SEL27;
46553 __IO uint16_t SEL28;
46554 __IO uint16_t SEL29;
46555 __IO uint16_t SEL30;
46556 __IO uint16_t SEL31;
46557 __IO uint16_t SEL32;
46558 __IO uint16_t SEL33;
46559 __IO uint16_t SEL34;
46560 __IO uint16_t SEL35;
46561 __IO uint16_t SEL36;
46562 __IO uint16_t SEL37;
46563 __IO uint16_t SEL38;
46564 __IO uint16_t SEL39;
46565 __IO uint16_t SEL40;
46566 __IO uint16_t SEL41;
46567 __IO uint16_t SEL42;
46568 __IO uint16_t SEL43;
46569 __IO uint16_t SEL44;
46570 __IO uint16_t SEL45;
46571 __IO uint16_t SEL46;
46572 __IO uint16_t SEL47;
46573 __IO uint16_t SEL48;
46574 __IO uint16_t SEL49;
46575 __IO uint16_t SEL50;
46576 __IO uint16_t SEL51;
46577 __IO uint16_t SEL52;
46578 __IO uint16_t SEL53;
46579 __IO uint16_t SEL54;
46580 __IO uint16_t SEL55;
46581 __IO uint16_t SEL56;
46582 __IO uint16_t SEL57;
46583 __IO uint16_t SEL58;
46584 __IO uint16_t SEL59;
46585 __IO uint16_t SEL60;
46586 __IO uint16_t SEL61;
46587 __IO uint16_t SEL62;
46588 __IO uint16_t SEL63;
46589 __IO uint16_t SEL64;
46590 __IO uint16_t SEL65;
46591 __IO uint16_t CTRL0;
46592 __IO uint16_t CTRL1;
46593 } XBARA_Type;
46594
46595 /* ----------------------------------------------------------------------------
46596 -- XBARA Register Masks
46597 ---------------------------------------------------------------------------- */
46598
46606 #define XBARA_SEL0_SEL0_MASK (0x7FU)
46607 #define XBARA_SEL0_SEL0_SHIFT (0U)
46608 #define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
46609 #define XBARA_SEL0_SEL1_MASK (0x7F00U)
46610 #define XBARA_SEL0_SEL1_SHIFT (8U)
46611 #define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
46612
46616 #define XBARA_SEL1_SEL2_MASK (0x7FU)
46617 #define XBARA_SEL1_SEL2_SHIFT (0U)
46618 #define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
46619 #define XBARA_SEL1_SEL3_MASK (0x7F00U)
46620 #define XBARA_SEL1_SEL3_SHIFT (8U)
46621 #define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
46622
46626 #define XBARA_SEL2_SEL4_MASK (0x7FU)
46627 #define XBARA_SEL2_SEL4_SHIFT (0U)
46628 #define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
46629 #define XBARA_SEL2_SEL5_MASK (0x7F00U)
46630 #define XBARA_SEL2_SEL5_SHIFT (8U)
46631 #define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
46632
46636 #define XBARA_SEL3_SEL6_MASK (0x7FU)
46637 #define XBARA_SEL3_SEL6_SHIFT (0U)
46638 #define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
46639 #define XBARA_SEL3_SEL7_MASK (0x7F00U)
46640 #define XBARA_SEL3_SEL7_SHIFT (8U)
46641 #define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
46642
46646 #define XBARA_SEL4_SEL8_MASK (0x7FU)
46647 #define XBARA_SEL4_SEL8_SHIFT (0U)
46648 #define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
46649 #define XBARA_SEL4_SEL9_MASK (0x7F00U)
46650 #define XBARA_SEL4_SEL9_SHIFT (8U)
46651 #define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
46652
46656 #define XBARA_SEL5_SEL10_MASK (0x7FU)
46657 #define XBARA_SEL5_SEL10_SHIFT (0U)
46658 #define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
46659 #define XBARA_SEL5_SEL11_MASK (0x7F00U)
46660 #define XBARA_SEL5_SEL11_SHIFT (8U)
46661 #define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
46662
46666 #define XBARA_SEL6_SEL12_MASK (0x7FU)
46667 #define XBARA_SEL6_SEL12_SHIFT (0U)
46668 #define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
46669 #define XBARA_SEL6_SEL13_MASK (0x7F00U)
46670 #define XBARA_SEL6_SEL13_SHIFT (8U)
46671 #define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
46672
46676 #define XBARA_SEL7_SEL14_MASK (0x7FU)
46677 #define XBARA_SEL7_SEL14_SHIFT (0U)
46678 #define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
46679 #define XBARA_SEL7_SEL15_MASK (0x7F00U)
46680 #define XBARA_SEL7_SEL15_SHIFT (8U)
46681 #define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
46682
46686 #define XBARA_SEL8_SEL16_MASK (0x7FU)
46687 #define XBARA_SEL8_SEL16_SHIFT (0U)
46688 #define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
46689 #define XBARA_SEL8_SEL17_MASK (0x7F00U)
46690 #define XBARA_SEL8_SEL17_SHIFT (8U)
46691 #define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
46692
46696 #define XBARA_SEL9_SEL18_MASK (0x7FU)
46697 #define XBARA_SEL9_SEL18_SHIFT (0U)
46698 #define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
46699 #define XBARA_SEL9_SEL19_MASK (0x7F00U)
46700 #define XBARA_SEL9_SEL19_SHIFT (8U)
46701 #define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
46702
46706 #define XBARA_SEL10_SEL20_MASK (0x7FU)
46707 #define XBARA_SEL10_SEL20_SHIFT (0U)
46708 #define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
46709 #define XBARA_SEL10_SEL21_MASK (0x7F00U)
46710 #define XBARA_SEL10_SEL21_SHIFT (8U)
46711 #define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
46712
46716 #define XBARA_SEL11_SEL22_MASK (0x7FU)
46717 #define XBARA_SEL11_SEL22_SHIFT (0U)
46718 #define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
46719 #define XBARA_SEL11_SEL23_MASK (0x7F00U)
46720 #define XBARA_SEL11_SEL23_SHIFT (8U)
46721 #define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
46722
46726 #define XBARA_SEL12_SEL24_MASK (0x7FU)
46727 #define XBARA_SEL12_SEL24_SHIFT (0U)
46728 #define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
46729 #define XBARA_SEL12_SEL25_MASK (0x7F00U)
46730 #define XBARA_SEL12_SEL25_SHIFT (8U)
46731 #define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
46732
46736 #define XBARA_SEL13_SEL26_MASK (0x7FU)
46737 #define XBARA_SEL13_SEL26_SHIFT (0U)
46738 #define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
46739 #define XBARA_SEL13_SEL27_MASK (0x7F00U)
46740 #define XBARA_SEL13_SEL27_SHIFT (8U)
46741 #define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
46742
46746 #define XBARA_SEL14_SEL28_MASK (0x7FU)
46747 #define XBARA_SEL14_SEL28_SHIFT (0U)
46748 #define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
46749 #define XBARA_SEL14_SEL29_MASK (0x7F00U)
46750 #define XBARA_SEL14_SEL29_SHIFT (8U)
46751 #define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
46752
46756 #define XBARA_SEL15_SEL30_MASK (0x7FU)
46757 #define XBARA_SEL15_SEL30_SHIFT (0U)
46758 #define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
46759 #define XBARA_SEL15_SEL31_MASK (0x7F00U)
46760 #define XBARA_SEL15_SEL31_SHIFT (8U)
46761 #define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
46762
46766 #define XBARA_SEL16_SEL32_MASK (0x7FU)
46767 #define XBARA_SEL16_SEL32_SHIFT (0U)
46768 #define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
46769 #define XBARA_SEL16_SEL33_MASK (0x7F00U)
46770 #define XBARA_SEL16_SEL33_SHIFT (8U)
46771 #define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
46772
46776 #define XBARA_SEL17_SEL34_MASK (0x7FU)
46777 #define XBARA_SEL17_SEL34_SHIFT (0U)
46778 #define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
46779 #define XBARA_SEL17_SEL35_MASK (0x7F00U)
46780 #define XBARA_SEL17_SEL35_SHIFT (8U)
46781 #define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
46782
46786 #define XBARA_SEL18_SEL36_MASK (0x7FU)
46787 #define XBARA_SEL18_SEL36_SHIFT (0U)
46788 #define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
46789 #define XBARA_SEL18_SEL37_MASK (0x7F00U)
46790 #define XBARA_SEL18_SEL37_SHIFT (8U)
46791 #define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
46792
46796 #define XBARA_SEL19_SEL38_MASK (0x7FU)
46797 #define XBARA_SEL19_SEL38_SHIFT (0U)
46798 #define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
46799 #define XBARA_SEL19_SEL39_MASK (0x7F00U)
46800 #define XBARA_SEL19_SEL39_SHIFT (8U)
46801 #define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
46802
46806 #define XBARA_SEL20_SEL40_MASK (0x7FU)
46807 #define XBARA_SEL20_SEL40_SHIFT (0U)
46808 #define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
46809 #define XBARA_SEL20_SEL41_MASK (0x7F00U)
46810 #define XBARA_SEL20_SEL41_SHIFT (8U)
46811 #define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
46812
46816 #define XBARA_SEL21_SEL42_MASK (0x7FU)
46817 #define XBARA_SEL21_SEL42_SHIFT (0U)
46818 #define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
46819 #define XBARA_SEL21_SEL43_MASK (0x7F00U)
46820 #define XBARA_SEL21_SEL43_SHIFT (8U)
46821 #define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
46822
46826 #define XBARA_SEL22_SEL44_MASK (0x7FU)
46827 #define XBARA_SEL22_SEL44_SHIFT (0U)
46828 #define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
46829 #define XBARA_SEL22_SEL45_MASK (0x7F00U)
46830 #define XBARA_SEL22_SEL45_SHIFT (8U)
46831 #define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
46832
46836 #define XBARA_SEL23_SEL46_MASK (0x7FU)
46837 #define XBARA_SEL23_SEL46_SHIFT (0U)
46838 #define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
46839 #define XBARA_SEL23_SEL47_MASK (0x7F00U)
46840 #define XBARA_SEL23_SEL47_SHIFT (8U)
46841 #define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
46842
46846 #define XBARA_SEL24_SEL48_MASK (0x7FU)
46847 #define XBARA_SEL24_SEL48_SHIFT (0U)
46848 #define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
46849 #define XBARA_SEL24_SEL49_MASK (0x7F00U)
46850 #define XBARA_SEL24_SEL49_SHIFT (8U)
46851 #define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
46852
46856 #define XBARA_SEL25_SEL50_MASK (0x7FU)
46857 #define XBARA_SEL25_SEL50_SHIFT (0U)
46858 #define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
46859 #define XBARA_SEL25_SEL51_MASK (0x7F00U)
46860 #define XBARA_SEL25_SEL51_SHIFT (8U)
46861 #define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
46862
46866 #define XBARA_SEL26_SEL52_MASK (0x7FU)
46867 #define XBARA_SEL26_SEL52_SHIFT (0U)
46868 #define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
46869 #define XBARA_SEL26_SEL53_MASK (0x7F00U)
46870 #define XBARA_SEL26_SEL53_SHIFT (8U)
46871 #define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
46872
46876 #define XBARA_SEL27_SEL54_MASK (0x7FU)
46877 #define XBARA_SEL27_SEL54_SHIFT (0U)
46878 #define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
46879 #define XBARA_SEL27_SEL55_MASK (0x7F00U)
46880 #define XBARA_SEL27_SEL55_SHIFT (8U)
46881 #define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
46882
46886 #define XBARA_SEL28_SEL56_MASK (0x7FU)
46887 #define XBARA_SEL28_SEL56_SHIFT (0U)
46888 #define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
46889 #define XBARA_SEL28_SEL57_MASK (0x7F00U)
46890 #define XBARA_SEL28_SEL57_SHIFT (8U)
46891 #define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
46892
46896 #define XBARA_SEL29_SEL58_MASK (0x7FU)
46897 #define XBARA_SEL29_SEL58_SHIFT (0U)
46898 #define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
46899 #define XBARA_SEL29_SEL59_MASK (0x7F00U)
46900 #define XBARA_SEL29_SEL59_SHIFT (8U)
46901 #define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
46902
46906 #define XBARA_SEL30_SEL60_MASK (0x7FU)
46907 #define XBARA_SEL30_SEL60_SHIFT (0U)
46908 #define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
46909 #define XBARA_SEL30_SEL61_MASK (0x7F00U)
46910 #define XBARA_SEL30_SEL61_SHIFT (8U)
46911 #define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
46912
46916 #define XBARA_SEL31_SEL62_MASK (0x7FU)
46917 #define XBARA_SEL31_SEL62_SHIFT (0U)
46918 #define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
46919 #define XBARA_SEL31_SEL63_MASK (0x7F00U)
46920 #define XBARA_SEL31_SEL63_SHIFT (8U)
46921 #define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
46922
46926 #define XBARA_SEL32_SEL64_MASK (0x7FU)
46927 #define XBARA_SEL32_SEL64_SHIFT (0U)
46928 #define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
46929 #define XBARA_SEL32_SEL65_MASK (0x7F00U)
46930 #define XBARA_SEL32_SEL65_SHIFT (8U)
46931 #define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
46932
46936 #define XBARA_SEL33_SEL66_MASK (0x7FU)
46937 #define XBARA_SEL33_SEL66_SHIFT (0U)
46938 #define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
46939 #define XBARA_SEL33_SEL67_MASK (0x7F00U)
46940 #define XBARA_SEL33_SEL67_SHIFT (8U)
46941 #define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
46942
46946 #define XBARA_SEL34_SEL68_MASK (0x7FU)
46947 #define XBARA_SEL34_SEL68_SHIFT (0U)
46948 #define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
46949 #define XBARA_SEL34_SEL69_MASK (0x7F00U)
46950 #define XBARA_SEL34_SEL69_SHIFT (8U)
46951 #define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
46952
46956 #define XBARA_SEL35_SEL70_MASK (0x7FU)
46957 #define XBARA_SEL35_SEL70_SHIFT (0U)
46958 #define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
46959 #define XBARA_SEL35_SEL71_MASK (0x7F00U)
46960 #define XBARA_SEL35_SEL71_SHIFT (8U)
46961 #define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
46962
46966 #define XBARA_SEL36_SEL72_MASK (0x7FU)
46967 #define XBARA_SEL36_SEL72_SHIFT (0U)
46968 #define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
46969 #define XBARA_SEL36_SEL73_MASK (0x7F00U)
46970 #define XBARA_SEL36_SEL73_SHIFT (8U)
46971 #define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
46972
46976 #define XBARA_SEL37_SEL74_MASK (0x7FU)
46977 #define XBARA_SEL37_SEL74_SHIFT (0U)
46978 #define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
46979 #define XBARA_SEL37_SEL75_MASK (0x7F00U)
46980 #define XBARA_SEL37_SEL75_SHIFT (8U)
46981 #define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
46982
46986 #define XBARA_SEL38_SEL76_MASK (0x7FU)
46987 #define XBARA_SEL38_SEL76_SHIFT (0U)
46988 #define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
46989 #define XBARA_SEL38_SEL77_MASK (0x7F00U)
46990 #define XBARA_SEL38_SEL77_SHIFT (8U)
46991 #define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
46992
46996 #define XBARA_SEL39_SEL78_MASK (0x7FU)
46997 #define XBARA_SEL39_SEL78_SHIFT (0U)
46998 #define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
46999 #define XBARA_SEL39_SEL79_MASK (0x7F00U)
47000 #define XBARA_SEL39_SEL79_SHIFT (8U)
47001 #define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
47002
47006 #define XBARA_SEL40_SEL80_MASK (0x7FU)
47007 #define XBARA_SEL40_SEL80_SHIFT (0U)
47008 #define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
47009 #define XBARA_SEL40_SEL81_MASK (0x7F00U)
47010 #define XBARA_SEL40_SEL81_SHIFT (8U)
47011 #define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
47012
47016 #define XBARA_SEL41_SEL82_MASK (0x7FU)
47017 #define XBARA_SEL41_SEL82_SHIFT (0U)
47018 #define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
47019 #define XBARA_SEL41_SEL83_MASK (0x7F00U)
47020 #define XBARA_SEL41_SEL83_SHIFT (8U)
47021 #define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
47022
47026 #define XBARA_SEL42_SEL84_MASK (0x7FU)
47027 #define XBARA_SEL42_SEL84_SHIFT (0U)
47028 #define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
47029 #define XBARA_SEL42_SEL85_MASK (0x7F00U)
47030 #define XBARA_SEL42_SEL85_SHIFT (8U)
47031 #define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
47032
47036 #define XBARA_SEL43_SEL86_MASK (0x7FU)
47037 #define XBARA_SEL43_SEL86_SHIFT (0U)
47038 #define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
47039 #define XBARA_SEL43_SEL87_MASK (0x7F00U)
47040 #define XBARA_SEL43_SEL87_SHIFT (8U)
47041 #define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
47042
47046 #define XBARA_SEL44_SEL88_MASK (0x7FU)
47047 #define XBARA_SEL44_SEL88_SHIFT (0U)
47048 #define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
47049 #define XBARA_SEL44_SEL89_MASK (0x7F00U)
47050 #define XBARA_SEL44_SEL89_SHIFT (8U)
47051 #define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
47052
47056 #define XBARA_SEL45_SEL90_MASK (0x7FU)
47057 #define XBARA_SEL45_SEL90_SHIFT (0U)
47058 #define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
47059 #define XBARA_SEL45_SEL91_MASK (0x7F00U)
47060 #define XBARA_SEL45_SEL91_SHIFT (8U)
47061 #define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
47062
47066 #define XBARA_SEL46_SEL92_MASK (0x7FU)
47067 #define XBARA_SEL46_SEL92_SHIFT (0U)
47068 #define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
47069 #define XBARA_SEL46_SEL93_MASK (0x7F00U)
47070 #define XBARA_SEL46_SEL93_SHIFT (8U)
47071 #define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
47072
47076 #define XBARA_SEL47_SEL94_MASK (0x7FU)
47077 #define XBARA_SEL47_SEL94_SHIFT (0U)
47078 #define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
47079 #define XBARA_SEL47_SEL95_MASK (0x7F00U)
47080 #define XBARA_SEL47_SEL95_SHIFT (8U)
47081 #define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
47082
47086 #define XBARA_SEL48_SEL96_MASK (0x7FU)
47087 #define XBARA_SEL48_SEL96_SHIFT (0U)
47088 #define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
47089 #define XBARA_SEL48_SEL97_MASK (0x7F00U)
47090 #define XBARA_SEL48_SEL97_SHIFT (8U)
47091 #define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
47092
47096 #define XBARA_SEL49_SEL98_MASK (0x7FU)
47097 #define XBARA_SEL49_SEL98_SHIFT (0U)
47098 #define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
47099 #define XBARA_SEL49_SEL99_MASK (0x7F00U)
47100 #define XBARA_SEL49_SEL99_SHIFT (8U)
47101 #define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
47102
47106 #define XBARA_SEL50_SEL100_MASK (0x7FU)
47107 #define XBARA_SEL50_SEL100_SHIFT (0U)
47108 #define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
47109 #define XBARA_SEL50_SEL101_MASK (0x7F00U)
47110 #define XBARA_SEL50_SEL101_SHIFT (8U)
47111 #define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
47112
47116 #define XBARA_SEL51_SEL102_MASK (0x7FU)
47117 #define XBARA_SEL51_SEL102_SHIFT (0U)
47118 #define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
47119 #define XBARA_SEL51_SEL103_MASK (0x7F00U)
47120 #define XBARA_SEL51_SEL103_SHIFT (8U)
47121 #define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
47122
47126 #define XBARA_SEL52_SEL104_MASK (0x7FU)
47127 #define XBARA_SEL52_SEL104_SHIFT (0U)
47128 #define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
47129 #define XBARA_SEL52_SEL105_MASK (0x7F00U)
47130 #define XBARA_SEL52_SEL105_SHIFT (8U)
47131 #define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
47132
47136 #define XBARA_SEL53_SEL106_MASK (0x7FU)
47137 #define XBARA_SEL53_SEL106_SHIFT (0U)
47138 #define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
47139 #define XBARA_SEL53_SEL107_MASK (0x7F00U)
47140 #define XBARA_SEL53_SEL107_SHIFT (8U)
47141 #define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
47142
47146 #define XBARA_SEL54_SEL108_MASK (0x7FU)
47147 #define XBARA_SEL54_SEL108_SHIFT (0U)
47148 #define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
47149 #define XBARA_SEL54_SEL109_MASK (0x7F00U)
47150 #define XBARA_SEL54_SEL109_SHIFT (8U)
47151 #define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
47152
47156 #define XBARA_SEL55_SEL110_MASK (0x7FU)
47157 #define XBARA_SEL55_SEL110_SHIFT (0U)
47158 #define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
47159 #define XBARA_SEL55_SEL111_MASK (0x7F00U)
47160 #define XBARA_SEL55_SEL111_SHIFT (8U)
47161 #define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
47162
47166 #define XBARA_SEL56_SEL112_MASK (0x7FU)
47167 #define XBARA_SEL56_SEL112_SHIFT (0U)
47168 #define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
47169 #define XBARA_SEL56_SEL113_MASK (0x7F00U)
47170 #define XBARA_SEL56_SEL113_SHIFT (8U)
47171 #define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
47172
47176 #define XBARA_SEL57_SEL114_MASK (0x7FU)
47177 #define XBARA_SEL57_SEL114_SHIFT (0U)
47178 #define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
47179 #define XBARA_SEL57_SEL115_MASK (0x7F00U)
47180 #define XBARA_SEL57_SEL115_SHIFT (8U)
47181 #define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
47182
47186 #define XBARA_SEL58_SEL116_MASK (0x7FU)
47187 #define XBARA_SEL58_SEL116_SHIFT (0U)
47188 #define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
47189 #define XBARA_SEL58_SEL117_MASK (0x7F00U)
47190 #define XBARA_SEL58_SEL117_SHIFT (8U)
47191 #define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
47192
47196 #define XBARA_SEL59_SEL118_MASK (0x7FU)
47197 #define XBARA_SEL59_SEL118_SHIFT (0U)
47198 #define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
47199 #define XBARA_SEL59_SEL119_MASK (0x7F00U)
47200 #define XBARA_SEL59_SEL119_SHIFT (8U)
47201 #define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
47202
47206 #define XBARA_SEL60_SEL120_MASK (0x7FU)
47207 #define XBARA_SEL60_SEL120_SHIFT (0U)
47208 #define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
47209 #define XBARA_SEL60_SEL121_MASK (0x7F00U)
47210 #define XBARA_SEL60_SEL121_SHIFT (8U)
47211 #define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
47212
47216 #define XBARA_SEL61_SEL122_MASK (0x7FU)
47217 #define XBARA_SEL61_SEL122_SHIFT (0U)
47218 #define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
47219 #define XBARA_SEL61_SEL123_MASK (0x7F00U)
47220 #define XBARA_SEL61_SEL123_SHIFT (8U)
47221 #define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
47222
47226 #define XBARA_SEL62_SEL124_MASK (0x7FU)
47227 #define XBARA_SEL62_SEL124_SHIFT (0U)
47228 #define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
47229 #define XBARA_SEL62_SEL125_MASK (0x7F00U)
47230 #define XBARA_SEL62_SEL125_SHIFT (8U)
47231 #define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
47232
47236 #define XBARA_SEL63_SEL126_MASK (0x7FU)
47237 #define XBARA_SEL63_SEL126_SHIFT (0U)
47238 #define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
47239 #define XBARA_SEL63_SEL127_MASK (0x7F00U)
47240 #define XBARA_SEL63_SEL127_SHIFT (8U)
47241 #define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
47242
47246 #define XBARA_SEL64_SEL128_MASK (0x7FU)
47247 #define XBARA_SEL64_SEL128_SHIFT (0U)
47248 #define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
47249 #define XBARA_SEL64_SEL129_MASK (0x7F00U)
47250 #define XBARA_SEL64_SEL129_SHIFT (8U)
47251 #define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
47252
47256 #define XBARA_SEL65_SEL130_MASK (0x7FU)
47257 #define XBARA_SEL65_SEL130_SHIFT (0U)
47258 #define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
47259 #define XBARA_SEL65_SEL131_MASK (0x7F00U)
47260 #define XBARA_SEL65_SEL131_SHIFT (8U)
47261 #define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
47262
47266 #define XBARA_CTRL0_DEN0_MASK (0x1U)
47267 #define XBARA_CTRL0_DEN0_SHIFT (0U)
47268
47272 #define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
47273 #define XBARA_CTRL0_IEN0_MASK (0x2U)
47274 #define XBARA_CTRL0_IEN0_SHIFT (1U)
47275
47279 #define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
47280 #define XBARA_CTRL0_EDGE0_MASK (0xCU)
47281 #define XBARA_CTRL0_EDGE0_SHIFT (2U)
47282
47288 #define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
47289 #define XBARA_CTRL0_STS0_MASK (0x10U)
47290 #define XBARA_CTRL0_STS0_SHIFT (4U)
47291
47295 #define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
47296 #define XBARA_CTRL0_DEN1_MASK (0x100U)
47297 #define XBARA_CTRL0_DEN1_SHIFT (8U)
47298
47302 #define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
47303 #define XBARA_CTRL0_IEN1_MASK (0x200U)
47304 #define XBARA_CTRL0_IEN1_SHIFT (9U)
47305
47309 #define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
47310 #define XBARA_CTRL0_EDGE1_MASK (0xC00U)
47311 #define XBARA_CTRL0_EDGE1_SHIFT (10U)
47312
47318 #define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
47319 #define XBARA_CTRL0_STS1_MASK (0x1000U)
47320 #define XBARA_CTRL0_STS1_SHIFT (12U)
47321
47325 #define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
47326
47330 #define XBARA_CTRL1_DEN2_MASK (0x1U)
47331 #define XBARA_CTRL1_DEN2_SHIFT (0U)
47332
47336 #define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
47337 #define XBARA_CTRL1_IEN2_MASK (0x2U)
47338 #define XBARA_CTRL1_IEN2_SHIFT (1U)
47339
47343 #define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
47344 #define XBARA_CTRL1_EDGE2_MASK (0xCU)
47345 #define XBARA_CTRL1_EDGE2_SHIFT (2U)
47346
47352 #define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
47353 #define XBARA_CTRL1_STS2_MASK (0x10U)
47354 #define XBARA_CTRL1_STS2_SHIFT (4U)
47355
47359 #define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
47360 #define XBARA_CTRL1_DEN3_MASK (0x100U)
47361 #define XBARA_CTRL1_DEN3_SHIFT (8U)
47362
47366 #define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
47367 #define XBARA_CTRL1_IEN3_MASK (0x200U)
47368 #define XBARA_CTRL1_IEN3_SHIFT (9U)
47369
47373 #define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
47374 #define XBARA_CTRL1_EDGE3_MASK (0xC00U)
47375 #define XBARA_CTRL1_EDGE3_SHIFT (10U)
47376
47382 #define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
47383 #define XBARA_CTRL1_STS3_MASK (0x1000U)
47384 #define XBARA_CTRL1_STS3_SHIFT (12U)
47385
47389 #define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
47390 /* end of group XBARA_Register_Masks */
47396
47397
47398 /* XBARA - Peripheral instance base addresses */
47400 #define XBARA1_BASE (0x403BC000u)
47401
47402 #define XBARA1 ((XBARA_Type *)XBARA1_BASE)
47403
47404 #define XBARA_BASE_ADDRS { XBARA1_BASE }
47405
47406 #define XBARA_BASE_PTRS { XBARA1 }
47407 /* end of group XBARA_Peripheral_Access_Layer */
47411
47412
47413 /* ----------------------------------------------------------------------------
47414 -- XBARB Peripheral Access Layer
47415 ---------------------------------------------------------------------------- */
47416
47423 typedef struct {
47424 __IO uint16_t SEL0;
47425 __IO uint16_t SEL1;
47426 __IO uint16_t SEL2;
47427 __IO uint16_t SEL3;
47428 __IO uint16_t SEL4;
47429 __IO uint16_t SEL5;
47430 __IO uint16_t SEL6;
47431 __IO uint16_t SEL7;
47432 } XBARB_Type;
47433
47434 /* ----------------------------------------------------------------------------
47435 -- XBARB Register Masks
47436 ---------------------------------------------------------------------------- */
47437
47445 #define XBARB_SEL0_SEL0_MASK (0x3FU)
47446 #define XBARB_SEL0_SEL0_SHIFT (0U)
47447 #define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
47448 #define XBARB_SEL0_SEL1_MASK (0x3F00U)
47449 #define XBARB_SEL0_SEL1_SHIFT (8U)
47450 #define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
47451
47455 #define XBARB_SEL1_SEL2_MASK (0x3FU)
47456 #define XBARB_SEL1_SEL2_SHIFT (0U)
47457 #define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
47458 #define XBARB_SEL1_SEL3_MASK (0x3F00U)
47459 #define XBARB_SEL1_SEL3_SHIFT (8U)
47460 #define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
47461
47465 #define XBARB_SEL2_SEL4_MASK (0x3FU)
47466 #define XBARB_SEL2_SEL4_SHIFT (0U)
47467 #define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
47468 #define XBARB_SEL2_SEL5_MASK (0x3F00U)
47469 #define XBARB_SEL2_SEL5_SHIFT (8U)
47470 #define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
47471
47475 #define XBARB_SEL3_SEL6_MASK (0x3FU)
47476 #define XBARB_SEL3_SEL6_SHIFT (0U)
47477 #define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
47478 #define XBARB_SEL3_SEL7_MASK (0x3F00U)
47479 #define XBARB_SEL3_SEL7_SHIFT (8U)
47480 #define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
47481
47485 #define XBARB_SEL4_SEL8_MASK (0x3FU)
47486 #define XBARB_SEL4_SEL8_SHIFT (0U)
47487 #define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
47488 #define XBARB_SEL4_SEL9_MASK (0x3F00U)
47489 #define XBARB_SEL4_SEL9_SHIFT (8U)
47490 #define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
47491
47495 #define XBARB_SEL5_SEL10_MASK (0x3FU)
47496 #define XBARB_SEL5_SEL10_SHIFT (0U)
47497 #define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
47498 #define XBARB_SEL5_SEL11_MASK (0x3F00U)
47499 #define XBARB_SEL5_SEL11_SHIFT (8U)
47500 #define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
47501
47505 #define XBARB_SEL6_SEL12_MASK (0x3FU)
47506 #define XBARB_SEL6_SEL12_SHIFT (0U)
47507 #define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
47508 #define XBARB_SEL6_SEL13_MASK (0x3F00U)
47509 #define XBARB_SEL6_SEL13_SHIFT (8U)
47510 #define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
47511
47515 #define XBARB_SEL7_SEL14_MASK (0x3FU)
47516 #define XBARB_SEL7_SEL14_SHIFT (0U)
47517 #define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
47518 #define XBARB_SEL7_SEL15_MASK (0x3F00U)
47519 #define XBARB_SEL7_SEL15_SHIFT (8U)
47520 #define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
47521 /* end of group XBARB_Register_Masks */
47527
47528
47529 /* XBARB - Peripheral instance base addresses */
47531 #define XBARB2_BASE (0x403C0000u)
47532
47533 #define XBARB2 ((XBARB_Type *)XBARB2_BASE)
47534
47535 #define XBARB3_BASE (0x403C4000u)
47536
47537 #define XBARB3 ((XBARB_Type *)XBARB3_BASE)
47538
47539 #define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
47540
47541 #define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
47542 /* end of group XBARB_Peripheral_Access_Layer */
47546
47547
47548 /* ----------------------------------------------------------------------------
47549 -- XTALOSC24M Peripheral Access Layer
47550 ---------------------------------------------------------------------------- */
47551
47558 typedef struct {
47559 uint8_t RESERVED_0[336];
47560 __IO uint32_t MISC0;
47561 __IO uint32_t MISC0_SET;
47562 __IO uint32_t MISC0_CLR;
47563 __IO uint32_t MISC0_TOG;
47564 uint8_t RESERVED_1[272];
47565 __IO uint32_t LOWPWR_CTRL;
47566 __IO uint32_t LOWPWR_CTRL_SET;
47567 __IO uint32_t LOWPWR_CTRL_CLR;
47568 __IO uint32_t LOWPWR_CTRL_TOG;
47569 uint8_t RESERVED_2[32];
47570 __IO uint32_t OSC_CONFIG0;
47571 __IO uint32_t OSC_CONFIG0_SET;
47572 __IO uint32_t OSC_CONFIG0_CLR;
47573 __IO uint32_t OSC_CONFIG0_TOG;
47574 __IO uint32_t OSC_CONFIG1;
47575 __IO uint32_t OSC_CONFIG1_SET;
47576 __IO uint32_t OSC_CONFIG1_CLR;
47577 __IO uint32_t OSC_CONFIG1_TOG;
47578 __IO uint32_t OSC_CONFIG2;
47579 __IO uint32_t OSC_CONFIG2_SET;
47580 __IO uint32_t OSC_CONFIG2_CLR;
47581 __IO uint32_t OSC_CONFIG2_TOG;
47582 } XTALOSC24M_Type;
47583
47584 /* ----------------------------------------------------------------------------
47585 -- XTALOSC24M Register Masks
47586 ---------------------------------------------------------------------------- */
47587
47595 #define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
47596 #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
47597 #define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
47598 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
47599 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
47600
47604 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
47605 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
47606 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
47607
47617 #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
47618 #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
47619 #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
47620 #define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
47621 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
47622 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
47623
47629 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
47630 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
47631 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
47632
47636 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
47637 #define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
47638 #define XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
47639
47645 #define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
47646 #define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
47647 #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
47648 #define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
47649 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
47650 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
47651 #define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
47652 #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
47653 #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
47654
47658 #define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
47659 #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
47660 #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
47661
47671 #define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
47672 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
47673 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
47674
47678 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
47679 #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
47680 #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
47681 #define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
47682 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
47683 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
47684
47688 #define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
47689
47693 #define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
47694 #define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
47695 #define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
47696 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
47697 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
47698
47702 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
47703 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
47704 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
47705
47715 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
47716 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
47717 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
47718 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
47719 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
47720 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
47721
47727 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
47728 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
47729 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
47730
47734 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
47735 #define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
47736 #define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
47737
47743 #define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
47744 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
47745 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
47746 #define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
47747 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
47748 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
47749 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
47750 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
47751 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
47752
47756 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
47757 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
47758 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
47759
47769 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
47770 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
47771 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
47772
47776 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
47777 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
47778 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
47779 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
47780 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
47781 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
47782
47786 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
47787
47791 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
47792 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
47793 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
47794 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
47795 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
47796
47800 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
47801 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
47802 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
47803
47813 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
47814 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
47815 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
47816 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
47817 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
47818 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
47819
47825 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
47826 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
47827 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
47828
47832 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
47833 #define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
47834 #define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
47835
47841 #define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
47842 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
47843 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
47844 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
47845 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
47846 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
47847 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
47848 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
47849 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
47850
47854 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
47855 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
47856 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
47857
47867 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
47868 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
47869 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
47870
47874 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
47875 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
47876 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
47877 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
47878 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
47879 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
47880
47884 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
47885
47889 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
47890 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
47891 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
47892 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
47893 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
47894
47898 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
47899 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
47900 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
47901
47911 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
47912 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
47913 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
47914 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
47915 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
47916 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
47917
47923 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
47924 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
47925 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
47926
47930 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
47931 #define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
47932 #define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
47933
47939 #define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
47940 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
47941 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
47942 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
47943 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
47944 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
47945 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
47946 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
47947 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
47948
47952 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
47953 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
47954 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
47955
47965 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
47966 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
47967 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
47968
47972 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
47973 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
47974 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
47975 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
47976 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
47977 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
47978
47982 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
47983
47987 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
47988 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
47989
47993 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
47994 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
47995 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
47996
48000 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
48001 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
48002 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
48003
48007 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
48008 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
48009 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
48010 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
48011 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
48012 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
48013 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
48014 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
48015 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
48016 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
48017 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
48018 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
48019 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
48020 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
48021 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
48022 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
48023 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
48024 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
48025 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
48026 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
48027 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
48028 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
48029 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
48030 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
48031
48037 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
48038 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
48039 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
48040
48044 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
48045 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
48046 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
48047 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
48048 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
48049 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
48050 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
48051
48055 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
48056 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
48057
48061 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
48062 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
48063 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
48064
48068 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
48069 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
48070 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
48071
48075 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
48076 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
48077 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
48078 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
48079 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
48080 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
48081 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
48082 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
48083 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
48084 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
48085 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
48086 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
48087 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
48088 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
48089 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
48090 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
48091 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
48092 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
48093 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
48094 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
48095 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
48096 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
48097 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
48098 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
48099
48105 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
48106 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
48107 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
48108
48112 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
48113 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
48114 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
48115 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
48116 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
48117 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
48118 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
48119
48123 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
48124 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
48125
48129 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
48130 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
48131 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
48132
48136 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
48137 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
48138 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
48139
48143 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
48144 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
48145 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
48146 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
48147 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
48148 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
48149 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
48150 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
48151 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
48152 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
48153 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
48154 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
48155 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
48156 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
48157 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
48158 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
48159 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
48160 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
48161 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
48162 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
48163 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
48164 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
48165 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
48166 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
48167
48173 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
48174 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
48175 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
48176
48180 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
48181 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
48182 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
48183 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
48184 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
48185 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
48186 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
48187
48191 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
48192 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
48193
48197 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
48198 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
48199 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
48200
48204 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
48205 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
48206 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
48207
48211 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
48212 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
48213 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
48214 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
48215 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
48216 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
48217 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
48218 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
48219 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
48220 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
48221 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
48222 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
48223 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
48224 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
48225 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
48226 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
48227 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
48228 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
48229 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
48230 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
48231 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
48232 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
48233 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
48234 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
48235
48241 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
48242 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
48243 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
48244
48248 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
48249 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
48250 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
48251 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
48252 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
48253 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
48254 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
48255
48259 #define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
48260 #define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
48261 #define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
48262 #define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
48263 #define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
48264 #define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
48265 #define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
48266 #define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
48267 #define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
48268 #define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
48269 #define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
48270 #define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
48271 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
48272 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
48273 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
48274 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
48275 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
48276 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
48277 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
48278 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
48279 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
48280 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
48281 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
48282 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
48283
48287 #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
48288 #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
48289 #define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
48290 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
48291 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
48292 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
48293 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
48294 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
48295 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
48296 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
48297 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
48298 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
48299 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
48300 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
48301 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
48302 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
48303 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
48304 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
48305 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
48306 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
48307 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
48308 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
48309 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
48310 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
48311
48315 #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
48316 #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
48317 #define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
48318 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
48319 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
48320 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
48321 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
48322 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
48323 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
48324 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
48325 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
48326 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
48327 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
48328 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
48329 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
48330 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
48331 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
48332 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
48333 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
48334 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
48335 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
48336 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
48337 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
48338 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
48339
48343 #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
48344 #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
48345 #define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
48346 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
48347 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
48348 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
48349 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
48350 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
48351 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
48352 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
48353 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
48354 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
48355 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
48356 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
48357 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
48358 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
48359 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
48360 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
48361 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
48362 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
48363 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
48364 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
48365 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
48366 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
48367
48371 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
48372 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
48373 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
48374 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
48375 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
48376 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
48377
48381 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
48382 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
48383 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
48384 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
48385 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
48386 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
48387
48391 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
48392 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
48393 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
48394 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
48395 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
48396 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
48397
48401 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
48402 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
48403 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
48404 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
48405 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
48406 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
48407
48411 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
48412 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
48413 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
48414 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
48415 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
48416 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
48417 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
48418 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
48419 #define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
48420 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
48421 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
48422 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
48423
48427 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
48428 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
48429 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
48430 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
48431 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
48432 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
48433 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
48434 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
48435 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
48436 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
48437 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
48438 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
48439
48443 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
48444 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
48445 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
48446 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
48447 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
48448 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
48449 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
48450 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
48451 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
48452 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
48453 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
48454 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
48455
48459 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
48460 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
48461 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
48462 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
48463 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
48464 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
48465 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
48466 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
48467 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
48468 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
48469 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
48470 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)
48471 /* end of group XTALOSC24M_Register_Masks */
48477
48478
48479 /* XTALOSC24M - Peripheral instance base addresses */
48481 #define XTALOSC24M_BASE (0x400D8000u)
48482
48483 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)
48484
48485 #define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }
48486
48487 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
48488 /* end of group XTALOSC24M_Peripheral_Access_Layer */
48492
48493
48494 /*
48495 ** End of section using anonymous unions
48496 */
48497
48498 #if defined(__ARMCC_VERSION)
48499 #if (__ARMCC_VERSION >= 6010050)
48500 #pragma clang diagnostic pop
48501 #else
48502 #pragma pop
48503 #endif
48504 #elif defined(__CWCC__)
48505 #pragma pop
48506 #elif defined(__GNUC__)
48507 /* leave anonymous unions enabled */
48508 #elif defined(__IAR_SYSTEMS_ICC__)
48509 #pragma language=default
48510 #else
48511 #error Not supported compiler type
48512 #endif
48513 /* end of group Peripheral_access_layer */
48517
48518
48519 /* ----------------------------------------------------------------------------
48520 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
48521 ---------------------------------------------------------------------------- */
48522
48528 #if defined(__ARMCC_VERSION)
48529 #if (__ARMCC_VERSION >= 6010050)
48530 #pragma clang system_header
48531 #endif
48532 #elif defined(__IAR_SYSTEMS_ICC__)
48533 #pragma system_include
48534 #endif
48535
48542 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
48543
48549 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
48550 /* end of group Bit_Field_Generic_Macros */
48554
48555
48556 /* ----------------------------------------------------------------------------
48557 -- SDK Compatibility
48558 ---------------------------------------------------------------------------- */
48559
48565 /* No SDK compatibility issues. */
48566 /* end of group SDK_Compatibility_Symbols */
48570
48571
48572 #endif /* _MIMXRT1062_H_ */
48573
kDmaRequestMuxFlexSPITx
Definition: MIMXRT1062.h:335
kXBARB2_InputAdcEtcXbar0Coco0
Definition: MIMXRT1062.h:1127
kXBARA1_InputIomuxXbarInout09
Definition: MIMXRT1062.h:1010
kXBARA1_OutputFlexpwm4ExtSync0
Definition: MIMXRT1062.h:1268
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06
Definition: MIMXRT1062.h:775
kIOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT
Definition: MIMXRT1062.h:982
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11
Definition: MIMXRT1062.h:598
kDmaRequestMuxFlexPWM1ValueSub3
Definition: MIMXRT1062.h:345
kXBARA1_OutputEwmEwmIn
Definition: MIMXRT1062.h:1311
CTI0_ERROR_IRQn
Definition: MIMXRT1062.h:107
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
Definition: MIMXRT1062.h:651
kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT
Definition: MIMXRT1062.h:902
kXBARB2_InputDmaDone2
Definition: MIMXRT1062.h:1141
kDmaRequestMuxFlexPWM3ValueSub2
Definition: MIMXRT1062.h:352
kXBARB3_OutputAoi2In12
Definition: MIMXRT1062.h:1368
kXBARB3_InputLogicLow
Definition: MIMXRT1062.h:1147
kXBARA1_OutputIomuxXbarInout18
Definition: MIMXRT1062.h:1227
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
Definition: MIMXRT1062.h:736
kXBARA1_OutputRESERVED24
Definition: MIMXRT1062.h:1233
kXBARA1_InputIomuxXbarInout15
Definition: MIMXRT1062.h:1016
kDmaRequestMuxFlexPWM2CaptureSub2
Definition: MIMXRT1062.h:399
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
Definition: MIMXRT1062.h:552
kDmaRequestMuxLPI2C3
Definition: MIMXRT1062.h:325
kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT
Definition: MIMXRT1062.h:906
BEE_Type
Definition: MIMXRT1062.h:3136
LPSPI2_IRQn
Definition: MIMXRT1062.h:123
kXBARA1_OutputFlexpwm1Fault1
Definition: MIMXRT1062.h:1245
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35
Definition: MIMXRT1062.h:662
kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT
Definition: MIMXRT1062.h:836
DCP_VMI_IRQn
Definition: MIMXRT1062.h:141
ACMP2_IRQn
Definition: MIMXRT1062.h:214
kDmaRequestMuxQTIMER1CaptTimer3
Definition: MIMXRT1062.h:357
kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT
Definition: MIMXRT1062.h:898
kIOMUXC_LPSPI4_PCS0_SELECT_INPUT
Definition: MIMXRT1062.h:875
PXP_IRQn
Definition: MIMXRT1062.h:134
kXBARB2_InputRESERVED4
Definition: MIMXRT1062.h:1093
kXBARB3_OutputAoi2In04
Definition: MIMXRT1062.h:1360
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
Definition: MIMXRT1062.h:530
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00
Definition: MIMXRT1062.h:669
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
Definition: MIMXRT1062.h:702
kXBARB3_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1062.h:1175
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
Definition: MIMXRT1062.h:664
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04
Definition: MIMXRT1062.h:673
kXBARA1_InputQtimer3Tmr2Output
Definition: MIMXRT1062.h:1035
MemoryManagement_IRQn
Definition: MIMXRT1062.h:81
kIOMUXC_XBAR1_IN19_SELECT_INPUT
Definition: MIMXRT1062.h:953
kXBARA1_OutputEnc4Trigger
Definition: MIMXRT1062.h:1294
kXBARB3_InputEnc3PosMatch
Definition: MIMXRT1062.h:1195
LPSPI_Type
Definition: MIMXRT1062.h:27724
kIOMUXC_FLEXCAN2_RX_SELECT_INPUT
Definition: MIMXRT1062.h:824
TRNG_IRQn
Definition: MIMXRT1062.h:143
kXBARA1_OutputEnc4Index
Definition: MIMXRT1062.h:1292
kIOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT
Definition: MIMXRT1062.h:988
kXBARB2_InputAdcEtcXbar1Coco1
Definition: MIMXRT1062.h:1132
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16
Definition: MIMXRT1062.h:461
kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1062.h:418
kIOMUXC_XBAR1_IN18_SELECT_INPUT
Definition: MIMXRT1062.h:944
kXBARA1_InputIomuxXbarInout06
Definition: MIMXRT1062.h:1007
CSI_Type
Definition: MIMXRT1062.h:9975
kXBARB2_InputLogicLow
Definition: MIMXRT1062.h:1089
kXBARA1_InputIomuxXbarIn20
Definition: MIMXRT1062.h:1021
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01
Definition: MIMXRT1062.h:602
kXBARA1_OutputQtimer4Tmr2Input
Definition: MIMXRT1062.h:1309
LPI2C_Type
Definition: MIMXRT1062.h:26674
kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1062.h:423
NonMaskableInt_IRQn
Definition: MIMXRT1062.h:79
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
Definition: MIMXRT1062.h:505
Reserved87_IRQn
Definition: MIMXRT1062.h:161
kXBARB2_OutputAoi1In08
Definition: MIMXRT1062.h:1348
kXBARB3_InputEnc2PosMatch
Definition: MIMXRT1062.h:1194
kIOMUXC_USDHC2_CLK_SELECT_INPUT
Definition: MIMXRT1062.h:923
kXBARA1_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1062.h:1055
kIOMUXC_XBAR1_IN25_SELECT_INPUT
Definition: MIMXRT1062.h:952
XTALOSC24M_Type
Definition: MIMXRT1062.h:47553
kXBARB3_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1062.h:1172
kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT
Definition: MIMXRT1062.h:979
kXBARA1_InputAdcEtcXbar1Coco0
Definition: MIMXRT1062.h:1085
PWM1_1_IRQn
Definition: MIMXRT1062.h:193
kXBARA1_InputIomuxXbarInout18
Definition: MIMXRT1062.h:1019
_iomuxc_sw_pad_ctl_pad
_iomuxc_sw_pad_ctl_pad
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Definition: MIMXRT1062.h:624
kDmaRequestMuxLPUART4Rx
Definition: MIMXRT1062.h:373
_iomuxc_select_input
_iomuxc_select_input
Enumeration for the IOMUXC select input.
Definition: MIMXRT1062.h:799
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01
Definition: MIMXRT1062.h:446
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14
Definition: MIMXRT1062.h:549
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
Definition: MIMXRT1062.h:490
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
Definition: MIMXRT1062.h:691
kXBARA1_InputIomuxXbarInout17
Definition: MIMXRT1062.h:1018
kDmaRequestMuxACMP3
Definition: MIMXRT1062.h:333
kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT
Definition: MIMXRT1062.h:841
CTI1_ERROR_IRQn
Definition: MIMXRT1062.h:108
kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1062.h:904
kIOMUXC_CSI_DATA03_SELECT_INPUT
Definition: MIMXRT1062.h:805
kXBARA1_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1062.h:1041
DMA2_DMA18_IRQn
Definition: MIMXRT1062.h:92
GPT2_IRQn
Definition: MIMXRT1062.h:191
LPSPI4_IRQn
Definition: MIMXRT1062.h:125
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05
Definition: MIMXRT1062.h:592
kXBARB3_InputQtimer4Tmr1Output
Definition: MIMXRT1062.h:1164
ADC_ETC_Type
Definition: MIMXRT1062.h:1743
RTWDOG_Type
Definition: MIMXRT1062.h:36144
kXBARB3_InputAdcEtcXbar1Coco0
Definition: MIMXRT1062.h:1189
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01
Definition: MIMXRT1062.h:588
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
Definition: MIMXRT1062.h:685
kXBARB3_InputAdcEtcXbar1Coco2
Definition: MIMXRT1062.h:1191
kIOMUXC_LPSPI4_SDO_SELECT_INPUT
Definition: MIMXRT1062.h:878
kDmaRequestMuxSai2Rx
Definition: MIMXRT1062.h:328
kXBARB3_InputQtimer4Tmr0Output
Definition: MIMXRT1062.h:1163
FLEXRAM_IRQn
Definition: MIMXRT1062.h:128
USB_ANALOG_Type
Definition: MIMXRT1062.h:44183
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
Definition: MIMXRT1062.h:650
SNVS_HP_WRAPPER_IRQn
Definition: MIMXRT1062.h:136
Reserved78_IRQn
Definition: MIMXRT1062.h:152
kDmaRequestMuxCAN3
Definition: MIMXRT1062.h:318
HardFault_IRQn
Definition: MIMXRT1062.h:80
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18
Definition: MIMXRT1062.h:645
kXBARB2_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1062.h:1120
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
Definition: MIMXRT1062.h:655
FLEXIO_Type
Definition: MIMXRT1062.h:18554
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04
Definition: MIMXRT1062.h:591
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
Definition: MIMXRT1062.h:635
kDmaRequestMuxQTIMER1CaptTimer1
Definition: MIMXRT1062.h:355
kXBARA1_OutputFlexpwm3ExtSync0
Definition: MIMXRT1062.h:1261
kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT
Definition: MIMXRT1062.h:831
kIOMUXC_XBAR1_IN04_SELECT_INPUT
Definition: MIMXRT1062.h:937
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06
Definition: MIMXRT1062.h:563
PMU_EVENT_IRQn
Definition: MIMXRT1062.h:151
kXBARA1_OutputIomuxXbarInout04
Definition: MIMXRT1062.h:1213
CAN_Type::@21::@24::ID
__IO uint32_t ID
Definition: MIMXRT1062.h:3471
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20
Definition: MIMXRT1062.h:465
LPUART1_IRQn
Definition: MIMXRT1062.h:110
kDmaRequestMuxLPSPI4Rx
Definition: MIMXRT1062.h:382
__IO
#define __IO
Definition: core_armv81mml.h:277
kDmaRequestMuxXBAR1Request3
Definition: MIMXRT1062.h:396
kXBARA1_OutputIomuxXbarInout14
Definition: MIMXRT1062.h:1223
kXBARB3_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1062.h:1178
LPI2C4_IRQn
Definition: MIMXRT1062.h:121
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13
Definition: MIMXRT1062.h:714
DMA15_DMA31_IRQn
Definition: MIMXRT1062.h:105
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
Definition: MIMXRT1062.h:452
CAN3_IRQn
Definition: MIMXRT1062.h:244
LPUART_Type
Definition: MIMXRT1062.h:28351
kXBARA1_InputAdcEtcXbar0Coco3
Definition: MIMXRT1062.h:1084
kXBARA1_InputAoi1Out0
Definition: MIMXRT1062.h:1073
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
Definition: MIMXRT1062.h:663
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
Definition: MIMXRT1062.h:489
kDmaRequestMuxLPUART5Rx
Definition: MIMXRT1062.h:315
kXBARB3_OutputAoi2In03
Definition: MIMXRT1062.h:1359
USB_PHY1_IRQn
Definition: MIMXRT1062.h:155
kIOMUXC_FLEXCAN1_RX_SELECT_INPUT
Definition: MIMXRT1062.h:823
kXBARB2_InputQtimer4Tmr2Output
Definition: MIMXRT1062.h:1107
kXBARB2_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1062.h:1117
kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT
Definition: MIMXRT1062.h:837
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07
Definition: MIMXRT1062.h:708
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
Definition: MIMXRT1062.h:700
kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT
Definition: MIMXRT1062.h:815
kXBARB3_InputDmaDone7
Definition: MIMXRT1062.h:1204
kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT
Definition: MIMXRT1062.h:901
FLEXIO1_IRQn
Definition: MIMXRT1062.h:180
kDmaRequestMuxQTIMER2CaptTimer0
Definition: MIMXRT1062.h:413
kDmaRequestMuxEnetTimer1
Definition: MIMXRT1062.h:394
kIOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT
Definition: MIMXRT1062.h:985
kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1062.h:421
kIOMUXC_USDHC2_DATA0_SELECT_INPUT
Definition: MIMXRT1062.h:926
kIOMUXC_LPSPI4_SCK_SELECT_INPUT
Definition: MIMXRT1062.h:876
kXBARA1_OutputEnc2Index
Definition: MIMXRT1062.h:1282
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
Definition: MIMXRT1062.h:701
kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1062.h:422
kIOMUXC_CSI_DATA05_SELECT_INPUT
Definition: MIMXRT1062.h:807
SPDIF_IRQn
Definition: MIMXRT1062.h:150
kXBARB3_OutputAoi2In02
Definition: MIMXRT1062.h:1358
kXBARA1_OutputDmaChMuxReq31
Definition: MIMXRT1062.h:1210
kXBARA1_OutputFlexpwm1ExtSync1
Definition: MIMXRT1062.h:1240
NotAvail_IRQn
Definition: MIMXRT1062.h:76
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
Definition: MIMXRT1062.h:632
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
Definition: MIMXRT1062.h:730
kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT
Definition: MIMXRT1062.h:899
CSU_IRQn
Definition: MIMXRT1062.h:139
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11
Definition: MIMXRT1062.h:498
PWM2_2_IRQn
Definition: MIMXRT1062.h:229
kXBARB2_InputDmaDone5
Definition: MIMXRT1062.h:1144
kXBARA1_InputRESERVED31
Definition: MIMXRT1062.h:1032
kXBARB2_InputDmaDone7
Definition: MIMXRT1062.h:1146
kXBARA1_InputAdcEtcXbar0Coco1
Definition: MIMXRT1062.h:1082
DMA_Type
Definition: MIMXRT1062.h:13131
kXBARB3_OutputAoi2In13
Definition: MIMXRT1062.h:1369
TMR_Type
Definition: MIMXRT1062.h:39763
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07
Definition: MIMXRT1062.h:608
kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT
Definition: MIMXRT1062.h:833
kXBARA1_InputIomuxXbarIn02
Definition: MIMXRT1062.h:1003
kIOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT
Definition: MIMXRT1062.h:986
kXBARB3_InputAdcEtcXbar1Coco1
Definition: MIMXRT1062.h:1190
USB_OTG2_IRQn
Definition: MIMXRT1062.h:202
SysTick_IRQn
Definition: MIMXRT1062.h:87
kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT
Definition: MIMXRT1062.h:849
DMA13_DMA29_IRQn
Definition: MIMXRT1062.h:103
AIPSTZ_Type
Definition: MIMXRT1062.h:2203
CAN_Type::@21::@25::ID
__IO uint32_t ID
Definition: MIMXRT1062.h:3476
kIOMUXC_LPSPI3_SCK_SELECT_INPUT
Definition: MIMXRT1062.h:872
kDmaRequestMuxFlexPWM4CaptureSub3
Definition: MIMXRT1062.h:408
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
Definition: MIMXRT1062.h:659
ENC2_IRQn
Definition: MIMXRT1062.h:220
kXBARA1_OutputQtimer2Tmr2Input
Definition: MIMXRT1062.h:1301
DMA7_DMA23_IRQn
Definition: MIMXRT1062.h:97
PWM2_3_IRQn
Definition: MIMXRT1062.h:230
kXBARA1_OutputFlexpwm3Fault0
Definition: MIMXRT1062.h:1265
ADC_ETC_IRQ0_IRQn
Definition: MIMXRT1062.h:208
kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT
Definition: MIMXRT1062.h:851
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
Definition: MIMXRT1062.h:553
kXBARB2_InputAcmp1Out
Definition: MIMXRT1062.h:1095
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1062.h:557
kXBARB2_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1062.h:1109
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00
Definition: MIMXRT1062.h:445
GPIO1_INT6_IRQn
Definition: MIMXRT1062.h:168
kIOMUXC_CSI_DATA08_SELECT_INPUT
Definition: MIMXRT1062.h:810
DMA9_DMA25_IRQn
Definition: MIMXRT1062.h:99
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
Definition: MIMXRT1062.h:517
kXBARB3_InputAcmp4Out
Definition: MIMXRT1062.h:1156
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
Definition: MIMXRT1062.h:508
kDmaRequestMuxLPSPI4Tx
Definition: MIMXRT1062.h:383
kXBARA1_OutputEnc2PhaseAInput
Definition: MIMXRT1062.h:1280
TMR4_IRQn
Definition: MIMXRT1062.h:226
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
Definition: MIMXRT1062.h:556
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18
Definition: MIMXRT1062.h:463
PMU_Type
Definition: MIMXRT1062.h:30884
kDmaRequestMuxFlexPWM3CaptureSub2
Definition: MIMXRT1062.h:348
kXBARB3_OutputAoi2In05
Definition: MIMXRT1062.h:1361
kXBARA1_OutputFlexpwm1ExtSync0
Definition: MIMXRT1062.h:1239
kXBARA1_InputAoi2Out1
Definition: MIMXRT1062.h:1078
kDmaRequestMuxLPUART2Rx
Definition: MIMXRT1062.h:371
XBARB_Type
Definition: MIMXRT1062.h:47418
kXBARA1_InputIomuxXbarInout14
Definition: MIMXRT1062.h:1015
kXBARB2_InputPitTrigger1
Definition: MIMXRT1062.h:1126
kXBARA1_InputLogicHigh
Definition: MIMXRT1062.h:1002
kXBARB3_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1062.h:1173
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08
Definition: MIMXRT1062.h:495
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
Definition: MIMXRT1062.h:654
kXBARB3_InputRESERVED11
Definition: MIMXRT1062.h:1158
DMAMUX_Type
Definition: MIMXRT1062.h:16244
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
Definition: MIMXRT1062.h:537
kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT
Definition: MIMXRT1062.h:977
kIOMUXC_XBAR1_IN14_SELECT_INPUT
Definition: MIMXRT1062.h:949
kIOMUXC_ENET_MDIO_SELECT_INPUT
Definition: MIMXRT1062.h:816
_xbar_input_signal
_xbar_input_signal
Definition: MIMXRT1062.h:999
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
Definition: MIMXRT1062.h:547
kXBARA1_InputIomuxXbarIn03
Definition: MIMXRT1062.h:1004
kXBARA1_InputQtimer4Tmr3Output
Definition: MIMXRT1062.h:1040
kXBARB2_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1062.h:1119
kIOMUXC_ENET_RXERR_SELECT_INPUT
Definition: MIMXRT1062.h:820
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
Definition: MIMXRT1062.h:468
GPIO1_INT3_IRQn
Definition: MIMXRT1062.h:165
_xbar_output_signal
_xbar_output_signal
Definition: MIMXRT1062.h:1207
kXBARA1_InputDmaDone6
Definition: MIMXRT1062.h:1071
PWM1_0_IRQn
Definition: MIMXRT1062.h:192
PWM2_0_IRQn
Definition: MIMXRT1062.h:227
LPUART3_IRQn
Definition: MIMXRT1062.h:112
kXBARA1_OutputLpuart8TrgInput
Definition: MIMXRT1062.h:1335
kDmaRequestMuxADC1
Definition: MIMXRT1062.h:331
kXBARA1_OutputFlexpwm1Exta1
Definition: MIMXRT1062.h:1236
kIOMUXC_CSI_DATA09_SELECT_INPUT
Definition: MIMXRT1062.h:811
kXBARB3_InputPitTrigger1
Definition: MIMXRT1062.h:1184
GPIO2_Combined_16_31_IRQn
Definition: MIMXRT1062.h:173
kXBARB2_OutputAoi1In12
Definition: MIMXRT1062.h:1352
kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1062.h:359
iomuxc_sw_mux_ctl_pad_t
enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT
Definition: MIMXRT1062.h:840
kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT
Definition: MIMXRT1062.h:826
kXBARA1_OutputFlexpwm234Exta0
Definition: MIMXRT1062.h:1249
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11
Definition: MIMXRT1062.h:680
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11
Definition: MIMXRT1062.h:638
kXBARB3_OutputAoi2In08
Definition: MIMXRT1062.h:1364
kDmaRequestMuxLCDIF
Definition: MIMXRT1062.h:379
kDmaRequestMuxLPSPI3Tx
Definition: MIMXRT1062.h:323
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
Definition: MIMXRT1062.h:535
kIOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT
Definition: MIMXRT1062.h:995
kXBARA1_OutputQtimer1Tmr2Input
Definition: MIMXRT1062.h:1297
kDmaRequestMuxFlexPWM4ValueSub3
Definition: MIMXRT1062.h:412
kDmaRequestMuxQTIMER2CaptTimer1
Definition: MIMXRT1062.h:414
kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT
Definition: MIMXRT1062.h:845
GPIO1_INT7_IRQn
Definition: MIMXRT1062.h:169
kXBARB2_InputAdcEtcXbar0Coco1
Definition: MIMXRT1062.h:1128
kIOMUXC_USDHC2_DATA4_SELECT_INPUT
Definition: MIMXRT1062.h:930
DCP_Type
Definition: MIMXRT1062.h:11453
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33
Definition: MIMXRT1062.h:478
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06
Definition: MIMXRT1062.h:789
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
Definition: MIMXRT1062.h:720
kIOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT
Definition: MIMXRT1062.h:972
USDHC1_IRQn
Definition: MIMXRT1062.h:200
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08
Definition: MIMXRT1062.h:777
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04
Definition: MIMXRT1062.h:491
DMA12_DMA28_IRQn
Definition: MIMXRT1062.h:102
CMP_Type
Definition: MIMXRT1062.h:9725
_iomuxc_select_input_1
_iomuxc_select_input_1
Enumeration for the IOMUXC select input.
Definition: MIMXRT1062.h:962
GPT_Type
Definition: MIMXRT1062.h:20797
kIOMUXC_LPSPI3_SDO_SELECT_INPUT
Definition: MIMXRT1062.h:874
kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT
Definition: MIMXRT1062.h:980
PIT_IRQn
Definition: MIMXRT1062.h:212
kIOMUXC_SAI2_MCLK2_SELECT_INPUT
Definition: MIMXRT1062.h:912
kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1062.h:910
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
Definition: MIMXRT1062.h:504
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
Definition: MIMXRT1062.h:522
kXBARA1_InputIomuxXbarInout08
Definition: MIMXRT1062.h:1009
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
Definition: MIMXRT1062.h:699
Reserved144_IRQn
Definition: MIMXRT1062.h:218
GPIO3_Combined_16_31_IRQn
Definition: MIMXRT1062.h:175
CSU_Type
Definition: MIMXRT1062.h:10653
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01
Definition: MIMXRT1062.h:670
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
Definition: MIMXRT1062.h:554
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
Definition: MIMXRT1062.h:507
ACMP1_IRQn
Definition: MIMXRT1062.h:213
kIOMUXC_USDHC2_DATA5_SELECT_INPUT
Definition: MIMXRT1062.h:931
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14
Definition: MIMXRT1062.h:533
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01
Definition: MIMXRT1062.h:784
FLEXIO2_IRQn
Definition: MIMXRT1062.h:181
ADC1_IRQn
Definition: MIMXRT1062.h:157
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
Definition: MIMXRT1062.h:695
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12
Definition: MIMXRT1062.h:599
Reserved68_IRQn
Definition: MIMXRT1062.h:142
DMA14_DMA30_IRQn
Definition: MIMXRT1062.h:104
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12
Definition: MIMXRT1062.h:781
GPIO5_Combined_16_31_IRQn
Definition: MIMXRT1062.h:179
kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT
Definition: MIMXRT1062.h:850
kIOMUXC_USDHC2_CD_B_SELECT_INPUT
Definition: MIMXRT1062.h:924
kXBARB2_OutputAoi1In07
Definition: MIMXRT1062.h:1347
kDmaRequestMuxFlexIO1Request0Request1
Definition: MIMXRT1062.h:308
kXBARB3_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1062.h:1179
kXBARB3_InputDmaDone5
Definition: MIMXRT1062.h:1202
kXBARB2_InputEnc4PosMatch
Definition: MIMXRT1062.h:1138
PWM3_1_IRQn
Definition: MIMXRT1062.h:233
BusFault_IRQn
Definition: MIMXRT1062.h:82
AOI_Type
Definition: MIMXRT1062.h:2927
OCOTP_Type
Definition: MIMXRT1062.h:29278
kXBARA1_OutputFlexio1TriggerIn1
Definition: MIMXRT1062.h:1337
kXBARB3_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1062.h:1171
PWM1_FAULT_IRQn
Definition: MIMXRT1062.h:196
kXBARB2_InputAdcEtcXbar1Coco0
Definition: MIMXRT1062.h:1131
kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT
Definition: MIMXRT1062.h:907
kXBARB3_OutputAoi2In10
Definition: MIMXRT1062.h:1366
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10
Definition: MIMXRT1062.h:779
CCM_ANALOG_Type
Definition: MIMXRT1062.h:7252
CAN_Type
Definition: MIMXRT1062.h:3438
kXBARB2_InputPitTrigger0
Definition: MIMXRT1062.h:1125
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13
Definition: MIMXRT1062.h:600
kIOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT
Definition: MIMXRT1062.h:983
kXBARB3_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1062.h:1170
kIOMUXC_USDHC2_DATA2_SELECT_INPUT
Definition: MIMXRT1062.h:928
LPUART5_IRQn
Definition: MIMXRT1062.h:114
_iomuxc_sw_mux_ctl_pad_1
_iomuxc_sw_mux_ctl_pad_1
Enumeration for the IOMUXC SW_MUX_CTL_PAD_1.
Definition: MIMXRT1062.h:584
EWM_Type
Definition: MIMXRT1062.h:18434
kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1062.h:365
kXBARA1_OutputIomuxXbarInout15
Definition: MIMXRT1062.h:1224
TRNG_Type
Definition: MIMXRT1062.h:40259
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05
Definition: MIMXRT1062.h:606
kIOMUXC_LPUART3_CTS_B_SELECT_INPUT
Definition: MIMXRT1062.h:881
kDmaRequestMuxFlexIO2Request0Request1
Definition: MIMXRT1062.h:309
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04
Definition: MIMXRT1062.h:523
SRC_Type
Definition: MIMXRT1062.h:39286
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07
Definition: MIMXRT1062.h:776
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
Definition: MIMXRT1062.h:711
kXBARA1_OutputFlexpwm1234Fault3
Definition: MIMXRT1062.h:1247
kDmaRequestMuxSai1Tx
Definition: MIMXRT1062.h:327
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
Definition: MIMXRT1062.h:520
kDmaRequestMuxFlexSPIRx
Definition: MIMXRT1062.h:334
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10
Definition: MIMXRT1062.h:497
kDmaRequestMuxSai2Tx
Definition: MIMXRT1062.h:329
kIOMUXC_XBAR1_IN21_SELECT_INPUT
Definition: MIMXRT1062.h:954
kXBARA1_OutputDmaChMuxReq94
Definition: MIMXRT1062.h:1211
kXBARA1_OutputFlexpwm2ExtSync2
Definition: MIMXRT1062.h:1255
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
Definition: MIMXRT1062.h:687
kIOMUXC_XBAR1_IN20_SELECT_INPUT
Definition: MIMXRT1062.h:945
PWM3_3_IRQn
Definition: MIMXRT1062.h:235
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03
Definition: MIMXRT1062.h:448
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02
Definition: MIMXRT1062.h:589
kXBARB3_InputAdcEtcXbar0Coco3
Definition: MIMXRT1062.h:1188
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
Definition: MIMXRT1062.h:718
kXBARA1_OutputIomuxXbarInout06
Definition: MIMXRT1062.h:1215
kXBARA1_OutputAdcEtcXbar1Trig2
Definition: MIMXRT1062.h:1318
FLEXSPI_Type
Definition: MIMXRT1062.h:19281
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
Definition: MIMXRT1062.h:712
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1062.h:420
kXBARB3_InputQtimer4Tmr2Output
Definition: MIMXRT1062.h:1165
kXBARA1_OutputLpuart6TrgInput
Definition: MIMXRT1062.h:1333
kXBARB2_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1062.h:1111
kIOMUXC_LPUART3_TX_SELECT_INPUT
Definition: MIMXRT1062.h:883
kDmaRequestMuxFlexPWM2ValueSub2
Definition: MIMXRT1062.h:403
kXBARA1_InputIomuxXbarIn25
Definition: MIMXRT1062.h:1026
kXBARB3_InputRESERVED10
Definition: MIMXRT1062.h:1157
kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT
Definition: MIMXRT1062.h:843
kDmaRequestMuxADC2
Definition: MIMXRT1062.h:390
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10
Definition: MIMXRT1062.h:727
kDmaRequestMuxLPUART2Tx
Definition: MIMXRT1062.h:370
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
Definition: MIMXRT1062.h:681
kDmaRequestMuxFlexPWM1CaptureSub2
Definition: MIMXRT1062.h:340
ENET2_IRQn
Definition: MIMXRT1062.h:242
kXBARA1_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1062.h:1045
SNVS_Type
Definition: MIMXRT1062.h:37701
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15
Definition: MIMXRT1062.h:460
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
Definition: MIMXRT1062.h:472
LPI2C1_IRQn
Definition: MIMXRT1062.h:118
kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1062.h:358
kXBARB3_InputQtimer3Tmr3Output
Definition: MIMXRT1062.h:1162
SRC_IRQn
Definition: MIMXRT1062.h:188
kXBARA1_OutputAdcEtcXbar0Trig0
Definition: MIMXRT1062.h:1312
kXBARA1_OutputFlexpwm3ExtSync2
Definition: MIMXRT1062.h:1263
kXBARA1_OutputEnc3Trigger
Definition: MIMXRT1062.h:1289
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05
Definition: MIMXRT1062.h:788
kIOMUXC_ENET_RXEN_SELECT_INPUT
Definition: MIMXRT1062.h:819
kXBARA1_InputIomuxXbarInout05
Definition: MIMXRT1062.h:1006
kIOMUXC_SPDIF_IN_SELECT_INPUT
Definition: MIMXRT1062.h:918
kXBARA1_OutputEnc3PhaseBInput
Definition: MIMXRT1062.h:1286
TEMPMON_Type
Definition: MIMXRT1062.h:39514
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
Definition: MIMXRT1062.h:499
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09
Definition: MIMXRT1062.h:778
CORE_IRQn
Definition: MIMXRT1062.h:109
kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1062.h:424
PWM2_FAULT_IRQn
Definition: MIMXRT1062.h:231
CAN_Type::@21::@26::ID
__IO uint32_t ID
Definition: MIMXRT1062.h:3481
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07
Definition: MIMXRT1062.h:542
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19
Definition: MIMXRT1062.h:464
ADC_ETC_IRQ2_IRQn
Definition: MIMXRT1062.h:210
kDmaRequestMuxLPI2C1
Definition: MIMXRT1062.h:324
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05
Definition: MIMXRT1062.h:492
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
Definition: MIMXRT1062.h:717
kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT
Definition: MIMXRT1062.h:908
kDmaRequestMuxQTIMER1CaptTimer2
Definition: MIMXRT1062.h:356
kDmaRequestMuxACMP2
Definition: MIMXRT1062.h:391
kXBARA1_InputIomuxXbarIn21
Definition: MIMXRT1062.h:1022
kXBARB3_OutputAoi2In14
Definition: MIMXRT1062.h:1370
kXBARB3_OutputAoi2In09
Definition: MIMXRT1062.h:1365
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08
Definition: MIMXRT1062.h:709
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
Definition: MIMXRT1062.h:689
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
Definition: MIMXRT1062.h:671
Reserved143_IRQn
Definition: MIMXRT1062.h:217
kXBARA1_OutputIomuxXbarInout10
Definition: MIMXRT1062.h:1219
kXBARA1_OutputFlexpwm1Fault0
Definition: MIMXRT1062.h:1244
kXBARA1_OutputFlexpwm2ExtSync0
Definition: MIMXRT1062.h:1253
UsageFault_IRQn
Definition: MIMXRT1062.h:83
kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT
Definition: MIMXRT1062.h:853
kXBARA1_OutputQtimer4Tmr0Input
Definition: MIMXRT1062.h:1307
kDmaRequestMuxFlexPWM4ValueSub0
Definition: MIMXRT1062.h:409
WDOG_Type
Definition: MIMXRT1062.h:46321
kXBARB2_InputQtimer4Tmr1Output
Definition: MIMXRT1062.h:1106
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10
Definition: MIMXRT1062.h:637
kXBARB2_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1062.h:1118
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06
Definition: MIMXRT1062.h:675
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
Definition: MIMXRT1062.h:719
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11
Definition: MIMXRT1062.h:456
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04
Definition: MIMXRT1062.h:605
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08
Definition: MIMXRT1062.h:747
kXBARA1_OutputFlexpwm4ExtSync3
Definition: MIMXRT1062.h:1271
kXBARA1_OutputFlexpwm234Exta2
Definition: MIMXRT1062.h:1251
kDmaRequestMuxFlexPWM3CaptureSub3
Definition: MIMXRT1062.h:349
kXBARA1_OutputRESERVED25
Definition: MIMXRT1062.h:1234
kIOMUXC_LPSPI2_SDO_SELECT_INPUT
Definition: MIMXRT1062.h:870
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40
Definition: MIMXRT1062.h:485
DMA0_DMA16_IRQn
Definition: MIMXRT1062.h:90
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08
Definition: MIMXRT1062.h:565
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03
Definition: MIMXRT1062.h:786
kIOMUXC_LPUART8_RX_SELECT_INPUT
Definition: MIMXRT1062.h:892
kXBARA1_InputAcmp4Out
Definition: MIMXRT1062.h:1030
kXBARA1_OutputLpuart3TrgInput
Definition: MIMXRT1062.h:1330
kIOMUXC_XBAR1_IN15_SELECT_INPUT
Definition: MIMXRT1062.h:950
kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT
Definition: MIMXRT1062.h:827
kXBARA1_OutputAdcEtcXbar1Trig1
Definition: MIMXRT1062.h:1317
CAN_Type::@21::@27::ID
__IO uint32_t ID
Definition: MIMXRT1062.h:3486
kXBARB2_InputAdcEtcXbar0Coco3
Definition: MIMXRT1062.h:1130
dma_request_source_t
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
LPI2C2_IRQn
Definition: MIMXRT1062.h:119
kXBARB2_InputAdcEtcXbar1Coco3
Definition: MIMXRT1062.h:1134
kXBARA1_OutputIomuxXbarInout13
Definition: MIMXRT1062.h:1222
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13
Definition: MIMXRT1062.h:782
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
Definition: MIMXRT1062.h:482
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09
Definition: MIMXRT1062.h:636
kXBARB2_InputRESERVED3
Definition: MIMXRT1062.h:1092
SNVS_HP_WRAPPER_TZ_IRQn
Definition: MIMXRT1062.h:137
kXBARA1_OutputEnc3PhaseAInput
Definition: MIMXRT1062.h:1285
kIOMUXC_ENET1_RXDATA_SELECT_INPUT
Definition: MIMXRT1062.h:818
IRQn_Type
enum IRQn IRQn_Type
kXBARB3_InputEnc4PosMatch
Definition: MIMXRT1062.h:1196
kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT
Definition: MIMXRT1062.h:842
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05
Definition: MIMXRT1062.h:674
kXBARA1_OutputAcmp3Sample
Definition: MIMXRT1062.h:1231
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02
Definition: MIMXRT1062.h:629
kIOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT
Definition: MIMXRT1062.h:965
GPIO2_Combined_0_15_IRQn
Definition: MIMXRT1062.h:172
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
Definition: MIMXRT1062.h:633
GPC_IRQn
Definition: MIMXRT1062.h:187
kXBARA1_OutputEnc1PhaseBInput
Definition: MIMXRT1062.h:1276
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07
Definition: MIMXRT1062.h:676
kXBARB3_InputAcmp1Out
Definition: MIMXRT1062.h:1153
kXBARB3_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1062.h:1169
kXBARA1_OutputFlexpwm1ExtSync2
Definition: MIMXRT1062.h:1241
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10
Definition: MIMXRT1062.h:567
kXBARB2_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1062.h:1116
kXBARB3_InputAdcEtcXbar0Coco2
Definition: MIMXRT1062.h:1187
TMR3_IRQn
Definition: MIMXRT1062.h:225
DCDC_IRQn
Definition: MIMXRT1062.h:159
kXBARA1_OutputEnc4Home
Definition: MIMXRT1062.h:1293
LPUART7_IRQn
Definition: MIMXRT1062.h:116
IOMUXC_SNVS_Type
Definition: MIMXRT1062.h:24393
kXBARA1_OutputFlexpwm1Exta2
Definition: MIMXRT1062.h:1237
kXBARA1_OutputLpspi4TrgInput
Definition: MIMXRT1062.h:1327
CAN_Type::@21::@25::CS
__IO uint32_t CS
Definition: MIMXRT1062.h:3475
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
Definition: MIMXRT1062.h:686
kIOMUXC_LPUART7_RX_SELECT_INPUT
Definition: MIMXRT1062.h:890
kXBARA1_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1062.h:1049
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07
Definition: MIMXRT1062.h:526
kDmaRequestMuxFlexPWM1CaptureSub3
Definition: MIMXRT1062.h:341
GPIO1_INT1_IRQn
Definition: MIMXRT1062.h:163
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
Definition: MIMXRT1062.h:653
kXBARA1_OutputFlexpwm4ExtSync2
Definition: MIMXRT1062.h:1270
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17
Definition: MIMXRT1062.h:644
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17
Definition: MIMXRT1062.h:462
kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT
Definition: MIMXRT1062.h:981
kDmaRequestMuxXBAR1Request2
Definition: MIMXRT1062.h:395
SAI2_IRQn
Definition: MIMXRT1062.h:147
kXBARB2_InputQtimer4Tmr3Output
Definition: MIMXRT1062.h:1108
kXBARA1_OutputQtimer3Tmr0Input
Definition: MIMXRT1062.h:1303
kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT
Definition: MIMXRT1062.h:993
kXBARA1_OutputFlexpwm3ExtSync1
Definition: MIMXRT1062.h:1262
kXBARA1_InputQtimer4Tmr0Output
Definition: MIMXRT1062.h:1037
PXP_Type
Definition: MIMXRT1062.h:34726
CAN_Type::@21::@27::CS
__IO uint32_t CS
Definition: MIMXRT1062.h:3485
kDmaRequestMuxACMP1
Definition: MIMXRT1062.h:332
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
Definition: MIMXRT1062.h:514
kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1062.h:419
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
Definition: MIMXRT1062.h:509
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
Definition: MIMXRT1062.h:551
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41
Definition: MIMXRT1062.h:486
kDmaRequestMuxFlexSPI2Rx
Definition: MIMXRT1062.h:366
Reserved171_IRQn
Definition: MIMXRT1062.h:245
kIOMUXC_LPSPI2_PCS0_SELECT_INPUT
Definition: MIMXRT1062.h:867
kXBARA1_OutputFlexpwm4ExtSync1
Definition: MIMXRT1062.h:1269
PendSV_IRQn
Definition: MIMXRT1062.h:86
kIOMUXC_XBAR1_IN16_SELECT_INPUT
Definition: MIMXRT1062.h:951
kIOMUXC_XBAR1_IN07_SELECT_INPUT
Definition: MIMXRT1062.h:940
kXBARA1_InputAoi2Out3
Definition: MIMXRT1062.h:1080
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
Definition: MIMXRT1062.h:729
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00
Definition: MIMXRT1062.h:487
kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT
Definition: MIMXRT1062.h:852
PWM4_FAULT_IRQn
Definition: MIMXRT1062.h:241
LPSPI1_IRQn
Definition: MIMXRT1062.h:122
kIOMUXC_USDHC1_WP_SELECT_INPUT
Definition: MIMXRT1062.h:922
kIOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT
Definition: MIMXRT1062.h:971
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41
Definition: MIMXRT1062.h:668
kDmaRequestMuxFlexPWM1CaptureSub0
Definition: MIMXRT1062.h:338
GPIO4_Combined_16_31_IRQn
Definition: MIMXRT1062.h:177
kDmaRequestMuxLPSPI1Rx
Definition: MIMXRT1062.h:320
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
Definition: MIMXRT1062.h:450
kXBARA1_OutputFlexpwm4ExtForce
Definition: MIMXRT1062.h:1274
kDmaRequestMuxLPUART7Rx
Definition: MIMXRT1062.h:317
kXBARB3_InputRESERVED3
Definition: MIMXRT1062.h:1150
kDmaRequestMuxFlexPWM1ValueSub2
Definition: MIMXRT1062.h:344
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
Definition: MIMXRT1062.h:703
kIOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT
Definition: MIMXRT1062.h:996
CCM_Type
Definition: MIMXRT1062.h:5279
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11
Definition: MIMXRT1062.h:750
SAI1_IRQn
Definition: MIMXRT1062.h:146
kXBARB3_InputRESERVED4
Definition: MIMXRT1062.h:1151
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01
Definition: MIMXRT1062.h:488
kXBARA1_OutputLpuart1TrgInput
Definition: MIMXRT1062.h:1328
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
Definition: MIMXRT1062.h:733
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21
Definition: MIMXRT1062.h:466
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00
Definition: MIMXRT1062.h:769
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
Definition: MIMXRT1062.h:738
kXBARB3_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1062.h:1174
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
Definition: MIMXRT1062.h:449
PWM3_0_IRQn
Definition: MIMXRT1062.h:232
ADC_Type
Definition: MIMXRT1062.h:1422
kDmaRequestMuxFlexPWM4ValueSub1
Definition: MIMXRT1062.h:410
kXBARA1_OutputFlexpwm3ExtForce
Definition: MIMXRT1062.h:1267
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15
Definition: MIMXRT1062.h:684
TEMP_PANIC_IRQn
Definition: MIMXRT1062.h:154
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
Definition: MIMXRT1062.h:510
LPI2C3_IRQn
Definition: MIMXRT1062.h:120
kIOMUXC_USDHC2_DATA6_SELECT_INPUT
Definition: MIMXRT1062.h:932
kXBARB2_InputRESERVED10
Definition: MIMXRT1062.h:1099
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
Definition: MIMXRT1062.h:471
kXBARA1_OutputIomuxXbarInout08
Definition: MIMXRT1062.h:1217
PWM3_2_IRQn
Definition: MIMXRT1062.h:234
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20
Definition: MIMXRT1062.h:647
kDmaRequestMuxEnetTimer0
Definition: MIMXRT1062.h:393
kXBARA1_OutputLpspi2TrgInput
Definition: MIMXRT1062.h:1325
kXBARB2_OutputAoi1In10
Definition: MIMXRT1062.h:1350
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07
Definition: MIMXRT1062.h:564
kDmaRequestMuxFlexPWM3ValueSub3
Definition: MIMXRT1062.h:353
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
Definition: MIMXRT1062.h:513
kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1062.h:363
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30
Definition: MIMXRT1062.h:657
SPDIF_Type
Definition: MIMXRT1062.h:38798
kXBARA1_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1062.h:1048
kXBARB2_OutputAoi1In02
Definition: MIMXRT1062.h:1342
kIOMUXC_LPUART5_TX_SELECT_INPUT
Definition: MIMXRT1062.h:887
kXBARA1_OutputAdcEtcXbar1Trig3
Definition: MIMXRT1062.h:1319
kXBARA1_InputAoi1Out2
Definition: MIMXRT1062.h:1075
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07
Definition: MIMXRT1062.h:746
kXBARA1_OutputLpuart7TrgInput
Definition: MIMXRT1062.h:1334
kIOMUXC_XBAR1_IN17_SELECT_INPUT
Definition: MIMXRT1062.h:943
DMA4_DMA20_IRQn
Definition: MIMXRT1062.h:94
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
Definition: MIMXRT1062.h:634
kXBARA1_InputDmaDone7
Definition: MIMXRT1062.h:1072
CAN2_IRQn
Definition: MIMXRT1062.h:127
kDmaRequestMuxLPUART1Rx
Definition: MIMXRT1062.h:311
kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT
Definition: MIMXRT1062.h:848
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01
Definition: MIMXRT1062.h:628
kXBARA1_InputPitTrigger0
Definition: MIMXRT1062.h:1057
kXBARA1_OutputEnc1PhaseAInput
Definition: MIMXRT1062.h:1275
WDOG1_IRQn
Definition: MIMXRT1062.h:182
kXBARA1_InputIomuxXbarInout16
Definition: MIMXRT1062.h:1017
kXBARB2_InputAdcEtcXbar0Coco2
Definition: MIMXRT1062.h:1129
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30
Definition: MIMXRT1062.h:475
kDmaRequestMuxLPUART3Rx
Definition: MIMXRT1062.h:313
USDHC2_IRQn
Definition: MIMXRT1062.h:201
SAI3_TX_IRQn
Definition: MIMXRT1062.h:149
kXBARA1_InputAoi2Out2
Definition: MIMXRT1062.h:1079
_iomuxc_sw_mux_ctl_pad
_iomuxc_sw_mux_ctl_pad
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Definition: MIMXRT1062.h:442
kXBARB2_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1062.h:1113
kXBARA1_InputIomuxXbarInout11
Definition: MIMXRT1062.h:1012
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
Definition: MIMXRT1062.h:713
IOMUXC_Type
Definition: MIMXRT1062.h:21918
LPUART2_IRQn
Definition: MIMXRT1062.h:111
kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT
Definition: MIMXRT1062.h:847
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10
Definition: MIMXRT1062.h:545
kXBARB2_InputRESERVED5
Definition: MIMXRT1062.h:1094
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
Definition: MIMXRT1062.h:516
kXBARB2_OutputAoi1In01
Definition: MIMXRT1062.h:1341
kXBARA1_OutputQtimer2Tmr1Input
Definition: MIMXRT1062.h:1300
kXBARA1_OutputAcmp1Sample
Definition: MIMXRT1062.h:1229
kXBARA1_OutputIomuxXbarInout09
Definition: MIMXRT1062.h:1218
kXBARB2_OutputAoi1In11
Definition: MIMXRT1062.h:1351
kXBARB3_InputPitTrigger0
Definition: MIMXRT1062.h:1183
WDOG2_IRQn
Definition: MIMXRT1062.h:135
kXBARA1_InputAdcEtcXbar1Coco1
Definition: MIMXRT1062.h:1086
kXBARA1_OutputFlexpwm1ExtClk
Definition: MIMXRT1062.h:1243
kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1062.h:916
kXBARA1_OutputFlexpwm2ExtForce
Definition: MIMXRT1062.h:1260
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40
Definition: MIMXRT1062.h:667
TMR1_IRQn
Definition: MIMXRT1062.h:223
kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1062.h:909
kXBARA1_OutputFlexpwm3ExtSync3
Definition: MIMXRT1062.h:1264
kIOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT
Definition: MIMXRT1062.h:987
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15
Definition: MIMXRT1062.h:642
USBNC_Type
Definition: MIMXRT1062.h:42932
kXBARB2_InputEnc2PosMatch
Definition: MIMXRT1062.h:1136
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
Definition: MIMXRT1062.h:521
kXBARA1_InputAdcEtcXbar1Coco3
Definition: MIMXRT1062.h:1088
kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT
Definition: MIMXRT1062.h:976
kXBARA1_OutputEnc2PhaseBInput
Definition: MIMXRT1062.h:1281
kXBARA1_OutputFlexpwm1ExtForce
Definition: MIMXRT1062.h:1248
kXBARB3_InputAcmp2Out
Definition: MIMXRT1062.h:1154
ADC_ETC_ERROR_IRQ_IRQn
Definition: MIMXRT1062.h:211
kDmaRequestMuxLPSPI3Rx
Definition: MIMXRT1062.h:322
kXBARA1_OutputFlexpwm2ExtSync3
Definition: MIMXRT1062.h:1256
ENET_IRQn
Definition: MIMXRT1062.h:204
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
Definition: MIMXRT1062.h:511
xbar_output_signal_t
enum _xbar_output_signal xbar_output_signal_t
TEMP_LOW_HIGH_IRQn
Definition: MIMXRT1062.h:153
TMR2_IRQn
Definition: MIMXRT1062.h:224
kIOMUXC_USDHC2_CMD_SELECT_INPUT
Definition: MIMXRT1062.h:925
system_MIMXRT1062.h
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
Definition: MIMXRT1062.h:477
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19
Definition: MIMXRT1062.h:646
kIOMUXC_LPI2C2_SDA_SELECT_INPUT
Definition: MIMXRT1062.h:858
iomuxc_sw_pad_ctl_pad_1_t
enum _iomuxc_sw_pad_ctl_pad_1 iomuxc_sw_pad_ctl_pad_1_t
Enumeration for the IOMUXC SW_PAD_CTL_PAD_1.
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13
Definition: MIMXRT1062.h:458
kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT
Definition: MIMXRT1062.h:990
kXBARA1_OutputFlexpwm1ExtSync3
Definition: MIMXRT1062.h:1242
FLEXRAM_Type
Definition: MIMXRT1062.h:19133
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10
Definition: MIMXRT1062.h:597
kIOMUXC_LPUART6_RX_SELECT_INPUT
Definition: MIMXRT1062.h:888
kDmaRequestMuxFlexSPI2Tx
Definition: MIMXRT1062.h:367
kXBARB2_InputAcmp2Out
Definition: MIMXRT1062.h:1096
kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1062.h:917
GPIO5_Combined_0_15_IRQn
Definition: MIMXRT1062.h:178
kIOMUXC_USDHC2_WP_SELECT_INPUT
Definition: MIMXRT1062.h:934
kDmaRequestMuxQTIMER2CaptTimer2
Definition: MIMXRT1062.h:415
kIOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0
Definition: MIMXRT1062.h:970
PWM4_0_IRQn
Definition: MIMXRT1062.h:237
XBARA_Type
Definition: MIMXRT1062.h:46519
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06
Definition: MIMXRT1062.h:607
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02
Definition: MIMXRT1062.h:785
kXBARB2_InputAcmp3Out
Definition: MIMXRT1062.h:1097
LCDIF_IRQn
Definition: MIMXRT1062.h:132
DMA8_DMA24_IRQn
Definition: MIMXRT1062.h:98
iomuxc_select_input_1_t
enum _iomuxc_select_input_1 iomuxc_select_input_1_t
Enumeration for the IOMUXC select input.
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15
Definition: MIMXRT1062.h:534
kDmaRequestMuxACMP4
Definition: MIMXRT1062.h:392
kXBARA1_InputEnc2PosMatch
Definition: MIMXRT1062.h:1062
kXBARB2_InputEnc3PosMatch
Definition: MIMXRT1062.h:1137
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05
Definition: MIMXRT1062.h:706
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06
Definition: MIMXRT1062.h:541
kIOMUXC_SAI1_MCLK2_SELECT_INPUT
Definition: MIMXRT1062.h:903
kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT
Definition: MIMXRT1062.h:828
kXBARA1_InputAoi1Out1
Definition: MIMXRT1062.h:1074
kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1062.h:914
DMA10_DMA26_IRQn
Definition: MIMXRT1062.h:100
SEMC_Type
Definition: MIMXRT1062.h:36346
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00
Definition: MIMXRT1062.h:783
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11
Definition: MIMXRT1062.h:546
kIOMUXC_XBAR1_IN05_SELECT_INPUT
Definition: MIMXRT1062.h:938
LPUART8_IRQn
Definition: MIMXRT1062.h:117
TSC_DIG_IRQn
Definition: MIMXRT1062.h:130
IOMUXC_SNVS_GPR_Type
Definition: MIMXRT1062.h:24901
kXBARA1_OutputEnc2Home
Definition: MIMXRT1062.h:1283
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09
Definition: MIMXRT1062.h:710
KPP_Type
Definition: MIMXRT1062.h:24975
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1062.h:360
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1062.h:744
DMA1_DMA17_IRQn
Definition: MIMXRT1062.h:91
kIOMUXC_LPI2C4_SCL_SELECT_INPUT
Definition: MIMXRT1062.h:861
kIOMUXC_LPSPI1_SDI_SELECT_INPUT
Definition: MIMXRT1062.h:865
kIOMUXC_XBAR1_IN24_SELECT_INPUT
Definition: MIMXRT1062.h:948
kXBARB3_InputAdcEtcXbar0Coco0
Definition: MIMXRT1062.h:1185
ENET_1588_Timer_IRQn
Definition: MIMXRT1062.h:205
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00
Definition: MIMXRT1062.h:627
ENET_Type
Definition: MIMXRT1062.h:16788
kXBARA1_InputAdcEtcXbar0Coco2
Definition: MIMXRT1062.h:1083
kIOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT
Definition: MIMXRT1062.h:968
USB_Type
Definition: MIMXRT1062.h:41378
kDmaRequestMuxQTIMER2CaptTimer3
Definition: MIMXRT1062.h:416
kDmaRequestMuxFlexPWM2CaptureSub1
Definition: MIMXRT1062.h:398
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15
Definition: MIMXRT1062.h:550
kIOMUXC_LPI2C2_SCL_SELECT_INPUT
Definition: MIMXRT1062.h:857
kXBARB2_OutputAoi1In00
Definition: MIMXRT1062.h:1340
FLEXSPI_IRQn
Definition: MIMXRT1062.h:198
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11
Definition: MIMXRT1062.h:780
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
Definition: MIMXRT1062.h:538
kXBARA1_InputAoi2Out0
Definition: MIMXRT1062.h:1077
kXBARA1_OutputEnc3Index
Definition: MIMXRT1062.h:1287
kXBARB2_InputDmaDone4
Definition: MIMXRT1062.h:1143
kXBARA1_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1062.h:1051
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1062.h:562
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09
Definition: MIMXRT1062.h:454
SAI3_RX_IRQn
Definition: MIMXRT1062.h:148
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07
Definition: MIMXRT1062.h:494
kDmaRequestMuxPxp
Definition: MIMXRT1062.h:378
kXBARA1_OutputLpspi3TrgInput
Definition: MIMXRT1062.h:1326
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09
Definition: MIMXRT1062.h:528
kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1062.h:362
kXBARB3_OutputAoi2In01
Definition: MIMXRT1062.h:1357
kIOMUXC_CSI_DATA07_SELECT_INPUT
Definition: MIMXRT1062.h:809
GPIO1_Combined_0_15_IRQn
Definition: MIMXRT1062.h:170
kXBARB2_OutputAoi1In13
Definition: MIMXRT1062.h:1353
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07
Definition: MIMXRT1062.h:594
kDmaRequestMuxADC_ETC
Definition: MIMXRT1062.h:330
RTWDOG_IRQn
Definition: MIMXRT1062.h:183
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10
Definition: MIMXRT1062.h:455
PWM1_3_IRQn
Definition: MIMXRT1062.h:195
kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT
Definition: MIMXRT1062.h:854
kXBARA1_OutputFlexio2TriggerIn0
Definition: MIMXRT1062.h:1338
kXBARB2_InputEnc1PosMatch
Definition: MIMXRT1062.h:1135
kDmaRequestMuxLPUART8Rx
Definition: MIMXRT1062.h:377
kXBARA1_OutputEnc1Home
Definition: MIMXRT1062.h:1278
kXBARB3_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1062.h:1182
kXBARA1_OutputAcmp2Sample
Definition: MIMXRT1062.h:1230
kXBARB3_InputQtimer3Tmr1Output
Definition: MIMXRT1062.h:1160
kIOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT
Definition: MIMXRT1062.h:969
kXBARA1_InputIomuxXbarIn23
Definition: MIMXRT1062.h:1024
kXBARA1_OutputQtimer4Tmr3Input
Definition: MIMXRT1062.h:1310
kXBARA1_InputDmaDone0
Definition: MIMXRT1062.h:1065
kXBARA1_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1062.h:1043
kXBARB2_OutputAoi1In03
Definition: MIMXRT1062.h:1343
kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT
Definition: MIMXRT1062.h:900
iomuxc_sw_pad_ctl_pad_t
enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
kXBARB2_InputDmaDone6
Definition: MIMXRT1062.h:1145
kXBARB3_OutputAoi2In15
Definition: MIMXRT1062.h:1371
kDmaRequestMuxFlexPWM4CaptureSub2
Definition: MIMXRT1062.h:407
kDmaRequestMuxFlexPWM2ValueSub0
Definition: MIMXRT1062.h:401
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
Definition: MIMXRT1062.h:631
ACMP3_IRQn
Definition: MIMXRT1062.h:215
kDmaRequestMuxXBAR1Request0
Definition: MIMXRT1062.h:336
kDmaRequestMuxLPI2C2
Definition: MIMXRT1062.h:384
kIOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT
Definition: MIMXRT1062.h:984
kXBARA1_InputRESERVED30
Definition: MIMXRT1062.h:1031
kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0
Definition: MIMXRT1062.h:991
kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT
Definition: MIMXRT1062.h:973
kXBARA1_OutputFlexpwm1234Fault2
Definition: MIMXRT1062.h:1246
kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT
Definition: MIMXRT1062.h:846
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10
Definition: MIMXRT1062.h:749
kDmaRequestMuxFlexIO2Request2Request3
Definition: MIMXRT1062.h:369
ENC_Type
Definition: MIMXRT1062.h:16322
kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT
Definition: MIMXRT1062.h:895
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38
Definition: MIMXRT1062.h:665
kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT
Definition: MIMXRT1062.h:844
kDmaRequestMuxLPSPI1Tx
Definition: MIMXRT1062.h:321
kIOMUXC_USB_OTG2_OC_SELECT_INPUT
Definition: MIMXRT1062.h:919
__I
#define __I
Definition: core_armv81mml.h:274
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
Definition: MIMXRT1062.h:453
kXBARB3_InputEnc1PosMatch
Definition: MIMXRT1062.h:1193
kXBARB2_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1062.h:1122
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38
Definition: MIMXRT1062.h:483
kDmaRequestMuxFlexPWM2ValueSub1
Definition: MIMXRT1062.h:402
kXBARA1_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1062.h:1053
kXBARB3_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1062.h:1180
PWM3_FAULT_IRQn
Definition: MIMXRT1062.h:236
CAN_Type::@21::@26::CS
__IO uint32_t CS
Definition: MIMXRT1062.h:3480
kDmaRequestMuxSpdifTx
Definition: MIMXRT1062.h:389
kXBARA1_OutputQtimer3Tmr2Input
Definition: MIMXRT1062.h:1305
SJC_IRQn
Definition: MIMXRT1062.h:144
kIOMUXC_LPI2C3_SDA_SELECT_INPUT
Definition: MIMXRT1062.h:860
EWM_IRQn
Definition: MIMXRT1062.h:184
kXBARB2_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1062.h:1115
kXBARB3_InputQtimer3Tmr0Output
Definition: MIMXRT1062.h:1159
kXBARA1_OutputQtimer1Tmr1Input
Definition: MIMXRT1062.h:1296
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
Definition: MIMXRT1062.h:697
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01
Definition: MIMXRT1062.h:770
kIOMUXC_LPUART6_TX_SELECT_INPUT
Definition: MIMXRT1062.h:889
kDmaRequestMuxFlexPWM2CaptureSub0
Definition: MIMXRT1062.h:397
kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1062.h:915
kXBARB2_InputRESERVED11
Definition: MIMXRT1062.h:1100
kIOMUXC_LPSPI2_SCK_SELECT_INPUT
Definition: MIMXRT1062.h:868
kXBARA1_OutputFlexpwm2Fault1
Definition: MIMXRT1062.h:1259
kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT
Definition: MIMXRT1062.h:838
PGC_Type
Definition: MIMXRT1062.h:30589
GPIO1_INT4_IRQn
Definition: MIMXRT1062.h:166
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1062.h:742
kIOMUXC_CSI_HSYNC_SELECT_INPUT
Definition: MIMXRT1062.h:812
kXBARB3_InputDmaDone6
Definition: MIMXRT1062.h:1203
kXBARA1_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1062.h:1054
kXBARA1_OutputFlexpwm4Fault0
Definition: MIMXRT1062.h:1272
kXBARA1_InputQtimer4Tmr2Output
Definition: MIMXRT1062.h:1039
kXBARA1_InputAoi1Out3
Definition: MIMXRT1062.h:1076
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05
Definition: MIMXRT1062.h:524
kXBARB3_InputAdcEtcXbar0Coco1
Definition: MIMXRT1062.h:1186
kIOMUXC_XBAR1_IN09_SELECT_INPUT
Definition: MIMXRT1062.h:942
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14
Definition: MIMXRT1062.h:731
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34
Definition: MIMXRT1062.h:661
kXBARA1_OutputEnc3Home
Definition: MIMXRT1062.h:1288
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
Definition: MIMXRT1062.h:470
kXBARA1_OutputLpuart5TrgInput
Definition: MIMXRT1062.h:1332
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08
Definition: MIMXRT1062.h:595
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
Definition: MIMXRT1062.h:531
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15
Definition: MIMXRT1062.h:732
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
Definition: MIMXRT1062.h:474
kXBARA1_OutputLpi2c2TrgInput
Definition: MIMXRT1062.h:1321
DCP_IRQn
Definition: MIMXRT1062.h:140
kXBARB3_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1062.h:1181
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04
Definition: MIMXRT1062.h:539
CCM_2_IRQn
Definition: MIMXRT1062.h:186
kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT
Definition: MIMXRT1062.h:839
kXBARA1_OutputQtimer4Tmr1Input
Definition: MIMXRT1062.h:1308
kXBARA1_OutputDmaChMuxReq30
Definition: MIMXRT1062.h:1209
kIOMUXC_NMI_SELECT_INPUT
Definition: MIMXRT1062.h:894
kDmaRequestMuxFlexPWM3ValueSub0
Definition: MIMXRT1062.h:350
kXBARA1_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1062.h:1047
kXBARB3_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1062.h:1167
kXBARA1_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1062.h:1046
kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT
Definition: MIMXRT1062.h:802
ADC_ETC_IRQ1_IRQn
Definition: MIMXRT1062.h:209
kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1062.h:364
kXBARA1_OutputQtimer3Tmr1Input
Definition: MIMXRT1062.h:1304
kDmaRequestMuxFlexPWM4CaptureSub0
Definition: MIMXRT1062.h:405
kXBARA1_OutputLpuart2TrgInput
Definition: MIMXRT1062.h:1329
DMA11_DMA27_IRQn
Definition: MIMXRT1062.h:101
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
Definition: MIMXRT1062.h:656
kDmaRequestMuxSai3Tx
Definition: MIMXRT1062.h:387
kXBARA1_InputDmaDone2
Definition: MIMXRT1062.h:1067
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
Definition: MIMXRT1062.h:529
kIOMUXC_CCM_PMIC_READY_SELECT_INPUT
Definition: MIMXRT1062.h:803
kIOMUXC_XBAR1_IN23_SELECT_INPUT
Definition: MIMXRT1062.h:947
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
Definition: MIMXRT1062.h:469
kIOMUXC_LPUART5_RX_SELECT_INPUT
Definition: MIMXRT1062.h:886
CAN1_IRQn
Definition: MIMXRT1062.h:126
kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT
Definition: MIMXRT1062.h:897
kIOMUXC_XBAR1_IN06_SELECT_INPUT
Definition: MIMXRT1062.h:939
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03
Definition: MIMXRT1062.h:590
kXBARB2_InputDmaDone3
Definition: MIMXRT1062.h:1142
kXBARA1_InputAcmp3Out
Definition: MIMXRT1062.h:1029
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13
Definition: MIMXRT1062.h:532
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
Definition: MIMXRT1062.h:734
DMA5_DMA21_IRQn
Definition: MIMXRT1062.h:95
GPIO1_INT5_IRQn
Definition: MIMXRT1062.h:167
ENET2_1588_Timer_IRQn
Definition: MIMXRT1062.h:243
kXBARA1_OutputLpspi1TrgInput
Definition: MIMXRT1062.h:1324
kXBARA1_InputEnc4PosMatch
Definition: MIMXRT1062.h:1064
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13
Definition: MIMXRT1062.h:640
kXBARB3_OutputAoi2In07
Definition: MIMXRT1062.h:1363
kXBARB2_InputQtimer3Tmr3Output
Definition: MIMXRT1062.h:1104
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
Definition: MIMXRT1062.h:555
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09
Definition: MIMXRT1062.h:496
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09
Definition: MIMXRT1062.h:566
kXBARA1_InputEnc3PosMatch
Definition: MIMXRT1062.h:1063
GPIO6_7_8_9_IRQn
Definition: MIMXRT1062.h:247
kDmaRequestMuxCSI
Definition: MIMXRT1062.h:319
ADC2_IRQn
Definition: MIMXRT1062.h:158
kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1062.h:417
kDmaRequestMuxFlexPWM3ValueSub1
Definition: MIMXRT1062.h:351
kXBARA1_OutputFlexio1TriggerIn0
Definition: MIMXRT1062.h:1336
iomuxc_select_input_t
enum _iomuxc_select_input iomuxc_select_input_t
Enumeration for the IOMUXC select input.
kXBARB2_InputDmaDone1
Definition: MIMXRT1062.h:1140
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
Definition: MIMXRT1062.h:515
kDmaRequestMuxXBAR1Request1
Definition: MIMXRT1062.h:337
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10
Definition: MIMXRT1062.h:679
kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT
Definition: MIMXRT1062.h:825
kXBARA1_InputIomuxXbarInout12
Definition: MIMXRT1062.h:1013
kXBARA1_OutputIomuxXbarInout11
Definition: MIMXRT1062.h:1220
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03
Definition: MIMXRT1062.h:772
kXBARA1_OutputQtimer2Tmr0Input
Definition: MIMXRT1062.h:1299
GPT1_IRQn
Definition: MIMXRT1062.h:190
kIOMUXC_CSI_DATA02_SELECT_INPUT
Definition: MIMXRT1062.h:804
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
Definition: MIMXRT1062.h:481
SNVS_LP_WRAPPER_IRQn
Definition: MIMXRT1062.h:138
kXBARB3_InputDmaDone1
Definition: MIMXRT1062.h:1198
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02
Definition: MIMXRT1062.h:447
kXBARA1_InputDmaDone3
Definition: MIMXRT1062.h:1068
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04
Definition: MIMXRT1062.h:721
kXBARA1_OutputIomuxXbarInout07
Definition: MIMXRT1062.h:1216
I2S_Type
Definition: MIMXRT1062.h:21087
kXBARA1_OutputEnc4PhaseBInput
Definition: MIMXRT1062.h:1291
kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1062.h:361
CCM_1_IRQn
Definition: MIMXRT1062.h:185
kXBARA1_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1062.h:1042
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
Definition: MIMXRT1062.h:506
IOMUXC_GPR_Type
Definition: MIMXRT1062.h:22188
kIOMUXC_USDHC2_DATA7_SELECT_INPUT
Definition: MIMXRT1062.h:933
kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT
Definition: MIMXRT1062.h:992
kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1
Definition: MIMXRT1062.h:967
kXBARA1_InputDmaDone4
Definition: MIMXRT1062.h:1069
kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT
Definition: MIMXRT1062.h:835
kXBARB3_InputRESERVED5
Definition: MIMXRT1062.h:1152
kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT
Definition: MIMXRT1062.h:896
kXBARB2_InputQtimer3Tmr1Output
Definition: MIMXRT1062.h:1102
kDmaRequestMuxFlexPWM2ValueSub3
Definition: MIMXRT1062.h:404
kDmaRequestMuxSai3Rx
Definition: MIMXRT1062.h:386
kXBARB2_OutputAoi1In06
Definition: MIMXRT1062.h:1346
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
Definition: MIMXRT1062.h:467
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
Definition: MIMXRT1062.h:503
LPSPI3_IRQn
Definition: MIMXRT1062.h:124
kXBARA1_OutputFlexio2TriggerIn1
Definition: MIMXRT1062.h:1339
GPR_IRQ_IRQn
Definition: MIMXRT1062.h:131
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14
Definition: MIMXRT1062.h:459
TSC_Type
Definition: MIMXRT1062.h:40931
kXBARA1_InputLogicLow
Definition: MIMXRT1062.h:1001
kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT
Definition: MIMXRT1062.h:834
kXBARB2_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1062.h:1112
kXBARB3_InputQtimer4Tmr3Output
Definition: MIMXRT1062.h:1166
kIOMUXC_LPSPI1_SCK_SELECT_INPUT
Definition: MIMXRT1062.h:864
kXBARB3_OutputAoi2In11
Definition: MIMXRT1062.h:1367
kXBARB2_InputAdcEtcXbar1Coco2
Definition: MIMXRT1062.h:1133
kIOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT
Definition: MIMXRT1062.h:964
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09
Definition: MIMXRT1062.h:596
kXBARB3_InputQtimer3Tmr2Output
Definition: MIMXRT1062.h:1161
PIT_Type
Definition: MIMXRT1062.h:30726
kIOMUXC_LPUART2_RX_SELECT_INPUT
Definition: MIMXRT1062.h:879
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
Definition: MIMXRT1062.h:536
kXBARB2_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1062.h:1124
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
Definition: MIMXRT1062.h:692
kIOMUXC_ENET_TXCLK_SELECT_INPUT
Definition: MIMXRT1062.h:822
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
Definition: MIMXRT1062.h:451
kXBARA1_OutputIomuxXbarInout12
Definition: MIMXRT1062.h:1221
kXBARA1_InputAdcEtcXbar1Coco2
Definition: MIMXRT1062.h:1087
DMA3_DMA19_IRQn
Definition: MIMXRT1062.h:93
CSI_IRQn
Definition: MIMXRT1062.h:133
kIOMUXC_XBAR1_IN03_SELECT_INPUT
Definition: MIMXRT1062.h:936
kXBARA1_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1062.h:1044
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
Definition: MIMXRT1062.h:694
kXBARB3_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1062.h:1177
_dma_request_source
_dma_request_source
Structure for the DMA hardware request.
Definition: MIMXRT1062.h:305
kXBARA1_OutputFlexpwm3Fault1
Definition: MIMXRT1062.h:1266
kXBARA1_InputDmaDone1
Definition: MIMXRT1062.h:1066
kXBARA1_OutputQtimer2Tmr3Input
Definition: MIMXRT1062.h:1302
kDmaRequestMuxSpdifRx
Definition: MIMXRT1062.h:388
kXBARA1_OutputIomuxXbarInout19
Definition: MIMXRT1062.h:1228
kXBARA1_OutputLpi2c4TrgInput
Definition: MIMXRT1062.h:1323
kXBARA1_InputIomuxXbarInout13
Definition: MIMXRT1062.h:1014
kXBARB2_OutputAoi1In09
Definition: MIMXRT1062.h:1349
kXBARA1_OutputQtimer1Tmr3Input
Definition: MIMXRT1062.h:1298
kXBARB3_InputRESERVED2
Definition: MIMXRT1062.h:1149
PWM_Type
Definition: MIMXRT1062.h:33060
kXBARB3_InputDmaDone2
Definition: MIMXRT1062.h:1199
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1062.h:743
kDmaRequestMuxLPUART8Tx
Definition: MIMXRT1062.h:376
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
Definition: MIMXRT1062.h:735
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11
Definition: MIMXRT1062.h:568
kXBARA1_InputQtimer3Tmr0Output
Definition: MIMXRT1062.h:1033
kIOMUXC_LPSPI1_SDO_SELECT_INPUT
Definition: MIMXRT1062.h:866
kXBARB3_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1062.h:1176
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35
Definition: MIMXRT1062.h:480
kDmaRequestMuxLPUART7Tx
Definition: MIMXRT1062.h:316
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00
Definition: MIMXRT1062.h:601
kXBARB3_InputDmaDone4
Definition: MIMXRT1062.h:1201
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1062.h:741
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
Definition: MIMXRT1062.h:696
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16
Definition: MIMXRT1062.h:643
GPIO1_INT0_IRQn
Definition: MIMXRT1062.h:162
kDmaRequestMuxLPUART5Tx
Definition: MIMXRT1062.h:314
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08
Definition: MIMXRT1062.h:543
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
Definition: MIMXRT1062.h:652
kXBARB3_InputLogicHigh
Definition: MIMXRT1062.h:1148
kXBARA1_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1062.h:1056
kXBARB3_OutputAoi2In00
Definition: MIMXRT1062.h:1356
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
Definition: MIMXRT1062.h:518
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
Definition: MIMXRT1062.h:688
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
Definition: MIMXRT1062.h:512
LCDIF_Type
Definition: MIMXRT1062.h:25116
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02
Definition: MIMXRT1062.h:603
kXBARA1_OutputAdcEtcXbar0Trig3
Definition: MIMXRT1062.h:1315
kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT
Definition: MIMXRT1062.h:832
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04
Definition: MIMXRT1062.h:705
USBPHY_Type
Definition: MIMXRT1062.h:43068
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39
Definition: MIMXRT1062.h:666
USB_OTG1_IRQn
Definition: MIMXRT1062.h:203
kXBARA1_OutputFlexpwm1Exta3
Definition: MIMXRT1062.h:1238
FLEXIO3_IRQn
Definition: MIMXRT1062.h:246
kIOMUXC_CSI_DATA04_SELECT_INPUT
Definition: MIMXRT1062.h:806
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06
Definition: MIMXRT1062.h:593
kDmaRequestMuxFlexPWM3CaptureSub0
Definition: MIMXRT1062.h:346
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04
Definition: MIMXRT1062.h:787
kIOMUXC_XBAR1_IN08_SELECT_INPUT
Definition: MIMXRT1062.h:941
kXBARB2_OutputAoi1In04
Definition: MIMXRT1062.h:1344
kIOMUXC_CSI_PIXCLK_SELECT_INPUT
Definition: MIMXRT1062.h:813
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
Definition: MIMXRT1062.h:519
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03
Definition: MIMXRT1062.h:604
kIOMUXC_XBAR1_IN22_SELECT_INPUT
Definition: MIMXRT1062.h:946
kXBARB2_InputDmaDone0
Definition: MIMXRT1062.h:1139
kXBARA1_InputAcmp2Out
Definition: MIMXRT1062.h:1028
kIOMUXC_XBAR1_IN02_SELECT_INPUT
Definition: MIMXRT1062.h:935
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
Definition: MIMXRT1062.h:672
kXBARA1_OutputAdcEtcXbar0Trig1
Definition: MIMXRT1062.h:1313
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
Definition: MIMXRT1062.h:682
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
Definition: MIMXRT1062.h:698
KPP_IRQn
Definition: MIMXRT1062.h:129
kXBARA1_InputIomuxXbarInout19
Definition: MIMXRT1062.h:1020
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15
Definition: MIMXRT1062.h:716
_iomuxc_sw_pad_ctl_pad_1
_iomuxc_sw_pad_ctl_pad_1
Enumeration for the IOMUXC SW_PAD_CTL_PAD_1.
Definition: MIMXRT1062.h:766
SVCall_IRQn
Definition: MIMXRT1062.h:84
kIOMUXC_USDHC2_DATA1_SELECT_INPUT
Definition: MIMXRT1062.h:927
PWM4_3_IRQn
Definition: MIMXRT1062.h:240
kXBARA1_InputQtimer3Tmr3Output
Definition: MIMXRT1062.h:1036
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09
Definition: MIMXRT1062.h:544
kIOMUXC_LPI2C3_SCL_SELECT_INPUT
Definition: MIMXRT1062.h:859
kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2
Definition: MIMXRT1062.h:989
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14
Definition: MIMXRT1062.h:715
kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT
Definition: MIMXRT1062.h:974
CAN_Type::@21::@24::CS
__IO uint32_t CS
Definition: MIMXRT1062.h:3470
LPUART6_IRQn
Definition: MIMXRT1062.h:115
GPIO_Type
Definition: MIMXRT1062.h:20329
kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0
Definition: MIMXRT1062.h:966
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09
Definition: MIMXRT1062.h:748
kDmaRequestMuxFlexIO1Request2Request3
Definition: MIMXRT1062.h:368
kIOMUXC_LPSPI2_SDI_SELECT_INPUT
Definition: MIMXRT1062.h:869
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14
Definition: MIMXRT1062.h:501
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
Definition: MIMXRT1062.h:500
kXBARA1_InputIomuxXbarInout10
Definition: MIMXRT1062.h:1011
kDmaRequestMuxEnet2Timer0
Definition: MIMXRT1062.h:425
kIOMUXC_CSI_VSYNC_SELECT_INPUT
Definition: MIMXRT1062.h:814
kXBARA1_InputEnc1PosMatch
Definition: MIMXRT1062.h:1061
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06
Definition: MIMXRT1062.h:707
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09
Definition: MIMXRT1062.h:678
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
Definition: MIMXRT1062.h:693
kXBARA1_OutputFlexpwm2Fault0
Definition: MIMXRT1062.h:1258
kXBARA1_OutputFlexpwm2ExtSync1
Definition: MIMXRT1062.h:1254
kXBARA1_OutputAdcEtcXbar0Trig2
Definition: MIMXRT1062.h:1314
kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT
Definition: MIMXRT1062.h:829
LPUART4_IRQn
Definition: MIMXRT1062.h:113
kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT
Definition: MIMXRT1062.h:975
kXBARB2_OutputAoi1In14
Definition: MIMXRT1062.h:1354
kIOMUXC_LPI2C1_SCL_SELECT_INPUT
Definition: MIMXRT1062.h:855
DMA_ERROR_IRQn
Definition: MIMXRT1062.h:106
kDmaRequestMuxLPUART6Tx
Definition: MIMXRT1062.h:374
XBAR1_IRQ_2_3_IRQn
Definition: MIMXRT1062.h:207
ENC3_IRQn
Definition: MIMXRT1062.h:221
PWM4_1_IRQn
Definition: MIMXRT1062.h:238
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1062.h:560
kIOMUXC_CSI_DATA06_SELECT_INPUT
Definition: MIMXRT1062.h:808
FLEXSPI2_IRQn
Definition: MIMXRT1062.h:197
ACMP4_IRQn
Definition: MIMXRT1062.h:216
kDmaRequestMuxLPUART1Tx
Definition: MIMXRT1062.h:310
USB_PHY2_IRQn
Definition: MIMXRT1062.h:156
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1062.h:558
kDmaRequestMuxFlexPWM3CaptureSub1
Definition: MIMXRT1062.h:347
ROMC_Type
Definition: MIMXRT1062.h:36018
kDmaRequestMuxFlexPWM1CaptureSub1
Definition: MIMXRT1062.h:339
kXBARB2_OutputAoi1In15
Definition: MIMXRT1062.h:1355
kXBARB2_InputAcmp4Out
Definition: MIMXRT1062.h:1098
kXBARA1_InputPitTrigger3
Definition: MIMXRT1062.h:1060
kXBARA1_InputQtimer4Tmr1Output
Definition: MIMXRT1062.h:1038
XBAR1_IRQ_0_1_IRQn
Definition: MIMXRT1062.h:206
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02
Definition: MIMXRT1062.h:771
kXBARA1_InputAcmp1Out
Definition: MIMXRT1062.h:1027
kXBARA1_InputIomuxXbarIn22
Definition: MIMXRT1062.h:1023
kXBARB2_InputLogicHigh
Definition: MIMXRT1062.h:1090
kXBARB2_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1062.h:1121
kXBARA1_OutputFlexpwm234Exta1
Definition: MIMXRT1062.h:1250
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08
Definition: MIMXRT1062.h:527
kDmaRequestMuxQTIMER1CaptTimer0
Definition: MIMXRT1062.h:354
SEMC_IRQn
Definition: MIMXRT1062.h:199
kIOMUXC_LPUART3_RX_SELECT_INPUT
Definition: MIMXRT1062.h:882
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05
Definition: MIMXRT1062.h:774
kIOMUXC_LPI2C4_SDA_SELECT_INPUT
Definition: MIMXRT1062.h:862
GPIO4_Combined_0_15_IRQn
Definition: MIMXRT1062.h:176
kDmaRequestMuxFlexPWM4ValueSub2
Definition: MIMXRT1062.h:411
kIOMUXC_LPUART7_TX_SELECT_INPUT
Definition: MIMXRT1062.h:891
DMA6_DMA22_IRQn
Definition: MIMXRT1062.h:96
kXBARA1_InputPitTrigger1
Definition: MIMXRT1062.h:1058
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15
Definition: MIMXRT1062.h:502
PWM2_1_IRQn
Definition: MIMXRT1062.h:228
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06
Definition: MIMXRT1062.h:745
kXBARA1_OutputFlexpwm234ExtClk
Definition: MIMXRT1062.h:1257
kXBARA1_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1062.h:1052
kDmaRequestMuxLPUART3Tx
Definition: MIMXRT1062.h:312
kXBARA1_OutputLpuart4TrgInput
Definition: MIMXRT1062.h:1331
kXBARB2_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1062.h:1123
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
Definition: MIMXRT1062.h:649
kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT
Definition: MIMXRT1062.h:830
kIOMUXC_USDHC1_CD_B_SELECT_INPUT
Definition: MIMXRT1062.h:921
__O
#define __O
Definition: core_armv81mml.h:276
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03
Definition: MIMXRT1062.h:630
GPC_Type
Definition: MIMXRT1062.h:20200
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT
Definition: MIMXRT1062.h:801
kXBARB2_InputQtimer3Tmr2Output
Definition: MIMXRT1062.h:1103
iomuxc_sw_mux_ctl_pad_1_t
enum _iomuxc_sw_mux_ctl_pad_1 iomuxc_sw_mux_ctl_pad_1_t
Enumeration for the IOMUXC SW_MUX_CTL_PAD_1.
kXBARA1_OutputEnc1Index
Definition: MIMXRT1062.h:1277
kIOMUXC_LPSPI4_SDI_SELECT_INPUT
Definition: MIMXRT1062.h:877
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
Definition: MIMXRT1062.h:473
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07
Definition: MIMXRT1062.h:724
kXBARA1_OutputQtimer3Tmr3Input
Definition: MIMXRT1062.h:1306
kXBARB2_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1062.h:1110
kDmaRequestMuxLPUART6Rx
Definition: MIMXRT1062.h:375
kDmaRequestMuxFlexPWM2CaptureSub3
Definition: MIMXRT1062.h:400
kXBARA1_InputDmaDone5
Definition: MIMXRT1062.h:1070
kXBARA1_OutputFlexpwm234Exta3
Definition: MIMXRT1062.h:1252
kXBARA1_OutputEnc2Trigger
Definition: MIMXRT1062.h:1284
kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT
Definition: MIMXRT1062.h:994
kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT
Definition: MIMXRT1062.h:978
kXBARB2_InputRESERVED2
Definition: MIMXRT1062.h:1091
kXBARA1_InputAdcEtcXbar0Coco0
Definition: MIMXRT1062.h:1081
kXBARA1_OutputFlexpwm4Fault1
Definition: MIMXRT1062.h:1273
kXBARA1_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1062.h:1050
kDmaRequestMuxEnet2Timer1
Definition: MIMXRT1062.h:426
DCDC_Type
Definition: MIMXRT1062.h:11268
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14
Definition: MIMXRT1062.h:641
kDmaRequestMuxFlexPWM1ValueSub1
Definition: MIMXRT1062.h:343
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04
Definition: MIMXRT1062.h:773
Reserved86_IRQn
Definition: MIMXRT1062.h:160
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06
Definition: MIMXRT1062.h:723
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06
Definition: MIMXRT1062.h:525
kXBARB3_InputDmaDone3
Definition: MIMXRT1062.h:1200
kDmaRequestMuxLPI2C4
Definition: MIMXRT1062.h:385
kIOMUXC_LPSPI3_SDI_SELECT_INPUT
Definition: MIMXRT1062.h:873
kDmaRequestMuxFlexPWM4CaptureSub1
Definition: MIMXRT1062.h:406
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
Definition: MIMXRT1062.h:658
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21
Definition: MIMXRT1062.h:648
BEE_IRQn
Definition: MIMXRT1062.h:145
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33
Definition: MIMXRT1062.h:660
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12
Definition: MIMXRT1062.h:457
ENC1_IRQn
Definition: MIMXRT1062.h:219
kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1062.h:913
Reserved115_IRQn
Definition: MIMXRT1062.h:189
kXBARA1_OutputIomuxXbarInout17
Definition: MIMXRT1062.h:1226
kXBARB2_OutputAoi1In05
Definition: MIMXRT1062.h:1345
kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1062.h:911
kIOMUXC_LPUART2_TX_SELECT_INPUT
Definition: MIMXRT1062.h:880
kXBARA1_OutputFlexpwm1Exta0
Definition: MIMXRT1062.h:1235
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1062.h:561
xbar_input_signal_t
enum _xbar_input_signal xbar_input_signal_t
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14
Definition: MIMXRT1062.h:683
kXBARB3_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1062.h:1168
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
Definition: MIMXRT1062.h:690
kXBARA1_OutputLpi2c1TrgInput
Definition: MIMXRT1062.h:1320
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05
Definition: MIMXRT1062.h:540
kXBARA1_OutputAdcEtcXbar1Trig0
Definition: MIMXRT1062.h:1316
kXBARA1_InputIomuxXbarIn24
Definition: MIMXRT1062.h:1025
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
Definition: MIMXRT1062.h:704
kIOMUXC_LPSPI3_PCS0_SELECT_INPUT
Definition: MIMXRT1062.h:871
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1062.h:739
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11
Definition: MIMXRT1062.h:728
kXBARA1_OutputLpi2c3TrgInput
Definition: MIMXRT1062.h:1322
kXBARA1_OutputQtimer1Tmr0Input
Definition: MIMXRT1062.h:1295
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08
Definition: MIMXRT1062.h:725
DebugMonitor_IRQn
Definition: MIMXRT1062.h:85
PWM1_2_IRQn
Definition: MIMXRT1062.h:194
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07
Definition: MIMXRT1062.h:790
kDmaRequestMuxSai1Rx
Definition: MIMXRT1062.h:326
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06
Definition: MIMXRT1062.h:493
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
Definition: MIMXRT1062.h:476
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34
Definition: MIMXRT1062.h:479
kXBARB3_InputAcmp3Out
Definition: MIMXRT1062.h:1155
kIOMUXC_USDHC2_DATA3_SELECT_INPUT
Definition: MIMXRT1062.h:929
kXBARA1_InputIomuxXbarInout04
Definition: MIMXRT1062.h:1005
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12
Definition: MIMXRT1062.h:639
kIOMUXC_LPSPI1_PCS0_SELECT_INPUT
Definition: MIMXRT1062.h:863
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
Definition: MIMXRT1062.h:737
kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1062.h:905
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09
Definition: MIMXRT1062.h:726
kXBARA1_OutputIomuxXbarInout05
Definition: MIMXRT1062.h:1214
kXBARA1_InputIomuxXbarInout07
Definition: MIMXRT1062.h:1008
kIOMUXC_ENET0_TIMER_SELECT_INPUT
Definition: MIMXRT1062.h:821
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00
Definition: MIMXRT1062.h:587
kDmaRequestMuxFlexPWM1ValueSub0
Definition: MIMXRT1062.h:342
USDHC_Type
Definition: MIMXRT1062.h:44638
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08
Definition: MIMXRT1062.h:677
PWM4_2_IRQn
Definition: MIMXRT1062.h:239
kXBARB3_InputDmaDone0
Definition: MIMXRT1062.h:1197
kIOMUXC_USB_OTG1_OC_SELECT_INPUT
Definition: MIMXRT1062.h:920
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1062.h:740
kDmaRequestMuxLPSPI2Tx
Definition: MIMXRT1062.h:381
kXBARB3_InputAdcEtcXbar1Coco3
Definition: MIMXRT1062.h:1192
kIOMUXC_LPUART4_TX_SELECT_INPUT
Definition: MIMXRT1062.h:885
kDmaRequestMuxLPUART4Tx
Definition: MIMXRT1062.h:372
kXBARA1_OutputDmaChMuxReq95
Definition: MIMXRT1062.h:1212
kXBARB2_InputQtimer3Tmr0Output
Definition: MIMXRT1062.h:1101
kIOMUXC_LPI2C1_SDA_SELECT_INPUT
Definition: MIMXRT1062.h:856
kIOMUXC_LPUART8_TX_SELECT_INPUT
Definition: MIMXRT1062.h:893
kXBARA1_OutputAcmp4Sample
Definition: MIMXRT1062.h:1232
kXBARA1_OutputEnc4PhaseAInput
Definition: MIMXRT1062.h:1290
kXBARB2_InputQtimer4Tmr0Output
Definition: MIMXRT1062.h:1105
kIOMUXC_ENET0_RXDATA_SELECT_INPUT
Definition: MIMXRT1062.h:817
kDmaRequestMuxLPSPI2Rx
Definition: MIMXRT1062.h:380
kIOMUXC_LPUART4_RX_SELECT_INPUT
Definition: MIMXRT1062.h:884
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1062.h:559
kXBARA1_InputPitTrigger2
Definition: MIMXRT1062.h:1059
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
Definition: MIMXRT1062.h:548
ENC4_IRQn
Definition: MIMXRT1062.h:222
kXBARA1_OutputIomuxXbarInout16
Definition: MIMXRT1062.h:1225
kXBARB3_OutputAoi2In06
Definition: MIMXRT1062.h:1362
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05
Definition: MIMXRT1062.h:722
GPIO1_INT2_IRQn
Definition: MIMXRT1062.h:164
kXBARA1_OutputEnc1Trigger
Definition: MIMXRT1062.h:1279
GPIO1_Combined_16_31_IRQn
Definition: MIMXRT1062.h:171
GPIO3_Combined_0_15_IRQn
Definition: MIMXRT1062.h:174
kXBARB2_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1062.h:1114
kXBARA1_InputQtimer3Tmr1Output
Definition: MIMXRT1062.h:1034
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39
Definition: MIMXRT1062.h:484