Callisto4Bootloader: CMSIS/mpu_armv7.h Source File

Callisto4Bootloader

mpu_armv7.h
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1 /******************************************************************************
2 * @file mpu_armv7.h
3 * @brief CMSIS MPU API for Armv7-M MPU
4 * @version V5.1.0
5 * @date 08. March 2019
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef ARM_MPU_ARMV7_H
32 #define ARM_MPU_ARMV7_H
33
34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
62
63 #define ARM_MPU_AP_NONE 0U
64 #define ARM_MPU_AP_PRIV 1U
65 #define ARM_MPU_AP_URO 2U
66 #define ARM_MPU_AP_FULL 3U
67 #define ARM_MPU_AP_PRO 5U
68 #define ARM_MPU_AP_RO 6U
69
70
75 #define ARM_MPU_RBAR(Region, BaseAddress) \
76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 ((Region) & MPU_RBAR_REGION_Msk) | \
78 (MPU_RBAR_VALID_Msk))
79
88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93
103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
107 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
108 (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
109 (((MPU_RASR_ENABLE_Msk))))
110
123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
124 ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
125
133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
134
144 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
145
157 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
158
162 #define ARM_MPU_CACHEP_NOCACHE 0U
163
167 #define ARM_MPU_CACHEP_WB_WRA 1U
168
172 #define ARM_MPU_CACHEP_WT_NWA 2U
173
177 #define ARM_MPU_CACHEP_WB_NWA 3U
178
179
183 typedef struct {
184 uint32_t RBAR;
185 uint32_t RASR;
186 } ARM_MPU_Region_t;
187
191 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
192 {
193 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
194 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
195 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
196 #endif
197 __DSB();
198 __ISB();
199 }
200
203 __STATIC_INLINE void ARM_MPU_Disable(void)
204 {
205 __DMB();
206 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
207 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
208 #endif
209 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
210 }
211
215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
216 {
217 MPU->RNR = rnr;
218 MPU->RASR = 0U;
219 }
220
225 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
226 {
227 MPU->RBAR = rbar;
228 MPU->RASR = rasr;
229 }
230
236 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
237 {
238 MPU->RNR = rnr;
239 MPU->RBAR = rbar;
240 MPU->RASR = rasr;
241 }
242
248 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
249 {
250 uint32_t i;
251 for (i = 0U; i < len; ++i)
252 {
253 dst[i] = src[i];
254 }
255 }
256
261 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
262 {
263 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
264 while (cnt > MPU_TYPE_RALIASES) {
265 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
266 table += MPU_TYPE_RALIASES;
267 cnt -= MPU_TYPE_RALIASES;
268 }
269 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
270 }
271
272 #endif
__RESTRICT
#define __RESTRICT
Definition: cmsis_armcc.h:105
ARM_MPU_Load
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt)
Definition: mpu_armv7.h:260
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866
ARM_MPU_Region_t
Definition: mpu_armv7.h:182
ARM_MPU_SetRegion
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
Definition: mpu_armv7.h:224
SCB_SHCSR_MEMFAULTENA_Msk
#define SCB_SHCSR_MEMFAULTENA_Msk
Definition: core_armv81mml.h:694
i
volatile int i
Definition: excep_test.c:17
ARM_MPU_Enable
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Definition: mpu_armv7.h:190
ARM_MPU_Disable
__STATIC_INLINE void ARM_MPU_Disable(void)
Definition: mpu_armv7.h:202
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
__DMB
__STATIC_FORCEINLINE void __DMB(void)
Data Memory Barrier.
Definition: cmsis_gcc.h:888
ARM_MPU_SetRegionEx
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
Definition: mpu_armv7.h:235
ARM_MPU_Region_t::RBAR
uint32_t RBAR
The region base address register value (RBAR)
Definition: mpu_armv7.h:183
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:63
ARM_MPU_OrderedMemcpy
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
Definition: mpu_armv7.h:247
ARM_MPU_ClrRegion
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Definition: mpu_armv7.h:214
SCB
#define SCB
Definition: core_armv81mml.h:2043