Callisto4Bootloader: GPT Register Masks

Callisto4Bootloader

Macros
GPT Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » GPT Peripheral Access Layer

## Macros

#define | GPT_OCR_COUNT (3U)
#define | GPT_ICR_COUNT (2U)

## CR - GPT Control Register

#define | GPT_CR_EN_MASK (0x1U)
#define | GPT_CR_EN_SHIFT (0U)
#define | GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
#define | GPT_CR_ENMOD_MASK (0x2U)
#define | GPT_CR_ENMOD_SHIFT (1U)
#define | GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
#define | GPT_CR_DBGEN_MASK (0x4U)
#define | GPT_CR_DBGEN_SHIFT (2U)
#define | GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
#define | GPT_CR_WAITEN_MASK (0x8U)
#define | GPT_CR_WAITEN_SHIFT (3U)
#define | GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
#define | GPT_CR_DOZEEN_MASK (0x10U)
#define | GPT_CR_DOZEEN_SHIFT (4U)
#define | GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
#define | GPT_CR_STOPEN_MASK (0x20U)
#define | GPT_CR_STOPEN_SHIFT (5U)
#define | GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
#define | GPT_CR_CLKSRC_MASK (0x1C0U)
#define | GPT_CR_CLKSRC_SHIFT (6U)
#define | GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
#define | GPT_CR_FRR_MASK (0x200U)
#define | GPT_CR_FRR_SHIFT (9U)
#define | GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
#define | GPT_CR_EN_24M_MASK (0x400U)
#define | GPT_CR_EN_24M_SHIFT (10U)
#define | GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
#define | GPT_CR_SWR_MASK (0x8000U)
#define | GPT_CR_SWR_SHIFT (15U)
#define | GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
#define | GPT_CR_IM1_MASK (0x30000U)
#define | GPT_CR_IM1_SHIFT (16U)
#define | GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
#define | GPT_CR_IM2_MASK (0xC0000U)
#define | GPT_CR_IM2_SHIFT (18U)
#define | GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
#define | GPT_CR_OM1_MASK (0x700000U)
#define | GPT_CR_OM1_SHIFT (20U)
#define | GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
#define | GPT_CR_OM2_MASK (0x3800000U)
#define | GPT_CR_OM2_SHIFT (23U)
#define | GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
#define | GPT_CR_OM3_MASK (0x1C000000U)
#define | GPT_CR_OM3_SHIFT (26U)
#define | GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
#define | GPT_CR_FO1_MASK (0x20000000U)
#define | GPT_CR_FO1_SHIFT (29U)
#define | GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
#define | GPT_CR_FO2_MASK (0x40000000U)
#define | GPT_CR_FO2_SHIFT (30U)
#define | GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
#define | GPT_CR_FO3_MASK (0x80000000U)
#define | GPT_CR_FO3_SHIFT (31U)
#define | GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)

## PR - GPT Prescaler Register

#define | GPT_PR_PRESCALER_MASK (0xFFFU)
#define | GPT_PR_PRESCALER_SHIFT (0U)
#define | GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
#define | GPT_PR_PRESCALER24M_MASK (0xF000U)
#define | GPT_PR_PRESCALER24M_SHIFT (12U)
#define | GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)

## SR - GPT Status Register

#define | GPT_SR_OF1_MASK (0x1U)
#define | GPT_SR_OF1_SHIFT (0U)
#define | GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
#define | GPT_SR_OF2_MASK (0x2U)
#define | GPT_SR_OF2_SHIFT (1U)
#define | GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
#define | GPT_SR_OF3_MASK (0x4U)
#define | GPT_SR_OF3_SHIFT (2U)
#define | GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
#define | GPT_SR_IF1_MASK (0x8U)
#define | GPT_SR_IF1_SHIFT (3U)
#define | GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
#define | GPT_SR_IF2_MASK (0x10U)
#define | GPT_SR_IF2_SHIFT (4U)
#define | GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
#define | GPT_SR_ROV_MASK (0x20U)
#define | GPT_SR_ROV_SHIFT (5U)
#define | GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)

## IR - GPT Interrupt Register

#define | GPT_IR_OF1IE_MASK (0x1U)
#define | GPT_IR_OF1IE_SHIFT (0U)
#define | GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
#define | GPT_IR_OF2IE_MASK (0x2U)
#define | GPT_IR_OF2IE_SHIFT (1U)
#define | GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
#define | GPT_IR_OF3IE_MASK (0x4U)
#define | GPT_IR_OF3IE_SHIFT (2U)
#define | GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
#define | GPT_IR_IF1IE_MASK (0x8U)
#define | GPT_IR_IF1IE_SHIFT (3U)
#define | GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
#define | GPT_IR_IF2IE_MASK (0x10U)
#define | GPT_IR_IF2IE_SHIFT (4U)
#define | GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
#define | GPT_IR_ROVIE_MASK (0x20U)
#define | GPT_IR_ROVIE_SHIFT (5U)
#define | GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)

## OCR - GPT Output Compare Register 1..GPT Output Compare Register 3

#define | GPT_OCR_COMP_MASK (0xFFFFFFFFU)
#define | GPT_OCR_COMP_SHIFT (0U)
#define | GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)

## ICR - GPT Input Capture Register 1..GPT Input Capture Register 2

#define | GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
#define | GPT_ICR_CAPT_SHIFT (0U)
#define | GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)

## CNT - GPT Counter Register

#define | GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
#define | GPT_CNT_COUNT_SHIFT (0U)
#define | GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ GPT_CNT_COUNT

#define GPT_CNT_COUNT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)

Definition at line 21047 of file MIMXRT1062.h.

## ◆ GPT_CNT_COUNT_MASK

#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)

Definition at line 21045 of file MIMXRT1062.h.

## ◆ GPT_CNT_COUNT_SHIFT

#define GPT_CNT_COUNT_SHIFT (0U)

Definition at line 21046 of file MIMXRT1062.h.

## ◆ GPT_CR_CLKSRC

#define GPT_CR_CLKSRC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)

CLKSRC 0b000..No clock 0b001..Peripheral Clock (ipg_clk) 0b010..High Frequency Reference Clock (ipg_clk_highfreq) 0b011..External Clock 0b100..Low Frequency Reference Clock (ipg_clk_32k) 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)

Definition at line 20870 of file MIMXRT1062.h.

## ◆ GPT_CR_CLKSRC_MASK

#define GPT_CR_CLKSRC_MASK (0x1C0U)

Definition at line 20860 of file MIMXRT1062.h.

## ◆ GPT_CR_CLKSRC_SHIFT

#define GPT_CR_CLKSRC_SHIFT (6U)

Definition at line 20861 of file MIMXRT1062.h.

## ◆ GPT_CR_DBGEN

#define GPT_CR_DBGEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)

DBGEN 0b0..GPT is disabled in debug mode. 0b1..GPT is enabled in debug mode.

Definition at line 20838 of file MIMXRT1062.h.

## ◆ GPT_CR_DBGEN_MASK

#define GPT_CR_DBGEN_MASK (0x4U)

Definition at line 20832 of file MIMXRT1062.h.

## ◆ GPT_CR_DBGEN_SHIFT

#define GPT_CR_DBGEN_SHIFT (2U)

Definition at line 20833 of file MIMXRT1062.h.

## ◆ GPT_CR_DOZEEN

#define GPT_CR_DOZEEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)

DOZEEN 0b0..GPT is disabled in doze mode. 0b1..GPT is enabled in doze mode.

Definition at line 20852 of file MIMXRT1062.h.

## ◆ GPT_CR_DOZEEN_MASK

#define GPT_CR_DOZEEN_MASK (0x10U)

Definition at line 20846 of file MIMXRT1062.h.

## ◆ GPT_CR_DOZEEN_SHIFT

#define GPT_CR_DOZEEN_SHIFT (4U)

Definition at line 20847 of file MIMXRT1062.h.

## ◆ GPT_CR_EN

#define GPT_CR_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)

EN 0b0..GPT is disabled. 0b1..GPT is enabled.

Definition at line 20824 of file MIMXRT1062.h.

## ◆ GPT_CR_EN_24M

#define GPT_CR_EN_24M | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)

EN_24M 0b0..24M clock disabled 0b1..24M clock enabled

Definition at line 20884 of file MIMXRT1062.h.

## ◆ GPT_CR_EN_24M_MASK

#define GPT_CR_EN_24M_MASK (0x400U)

Definition at line 20878 of file MIMXRT1062.h.

## ◆ GPT_CR_EN_24M_SHIFT

#define GPT_CR_EN_24M_SHIFT (10U)

Definition at line 20879 of file MIMXRT1062.h.

## ◆ GPT_CR_EN_MASK

#define GPT_CR_EN_MASK (0x1U)

Definition at line 20818 of file MIMXRT1062.h.

## ◆ GPT_CR_EN_SHIFT

#define GPT_CR_EN_SHIFT (0U)

Definition at line 20819 of file MIMXRT1062.h.

## ◆ GPT_CR_ENMOD

#define GPT_CR_ENMOD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)

ENMOD 0b0..GPT counter will retain its value when it is disabled. 0b1..GPT counter value is reset to 0 when it is disabled.

Definition at line 20831 of file MIMXRT1062.h.

## ◆ GPT_CR_ENMOD_MASK

#define GPT_CR_ENMOD_MASK (0x2U)

Definition at line 20825 of file MIMXRT1062.h.

## ◆ GPT_CR_ENMOD_SHIFT

#define GPT_CR_ENMOD_SHIFT (1U)

Definition at line 20826 of file MIMXRT1062.h.

## ◆ GPT_CR_FO1

#define GPT_CR_FO1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)

Definition at line 20922 of file MIMXRT1062.h.

## ◆ GPT_CR_FO1_MASK

#define GPT_CR_FO1_MASK (0x20000000U)

Definition at line 20920 of file MIMXRT1062.h.

## ◆ GPT_CR_FO1_SHIFT

#define GPT_CR_FO1_SHIFT (29U)

Definition at line 20921 of file MIMXRT1062.h.

## ◆ GPT_CR_FO2

#define GPT_CR_FO2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)

Definition at line 20925 of file MIMXRT1062.h.

## ◆ GPT_CR_FO2_MASK

#define GPT_CR_FO2_MASK (0x40000000U)

Definition at line 20923 of file MIMXRT1062.h.

## ◆ GPT_CR_FO2_SHIFT

#define GPT_CR_FO2_SHIFT (30U)

Definition at line 20924 of file MIMXRT1062.h.

## ◆ GPT_CR_FO3

#define GPT_CR_FO3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)

FO3 0b0..Writing a 0 has no effect. 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.

Definition at line 20932 of file MIMXRT1062.h.

## ◆ GPT_CR_FO3_MASK

#define GPT_CR_FO3_MASK (0x80000000U)

Definition at line 20926 of file MIMXRT1062.h.

## ◆ GPT_CR_FO3_SHIFT

#define GPT_CR_FO3_SHIFT (31U)

Definition at line 20927 of file MIMXRT1062.h.

## ◆ GPT_CR_FRR

#define GPT_CR_FRR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)

FRR 0b0..Restart mode 0b1..Free-Run mode

Definition at line 20877 of file MIMXRT1062.h.

## ◆ GPT_CR_FRR_MASK

#define GPT_CR_FRR_MASK (0x200U)

Definition at line 20871 of file MIMXRT1062.h.

## ◆ GPT_CR_FRR_SHIFT

#define GPT_CR_FRR_SHIFT (9U)

Definition at line 20872 of file MIMXRT1062.h.

## ◆ GPT_CR_IM1

#define GPT_CR_IM1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)

Definition at line 20894 of file MIMXRT1062.h.

## ◆ GPT_CR_IM1_MASK

#define GPT_CR_IM1_MASK (0x30000U)

Definition at line 20892 of file MIMXRT1062.h.

## ◆ GPT_CR_IM1_SHIFT

#define GPT_CR_IM1_SHIFT (16U)

Definition at line 20893 of file MIMXRT1062.h.

## ◆ GPT_CR_IM2

#define GPT_CR_IM2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)

IM2 0b00..capture disabled 0b01..capture on rising edge only 0b10..capture on falling edge only 0b11..capture on both edges

Definition at line 20903 of file MIMXRT1062.h.

## ◆ GPT_CR_IM2_MASK

#define GPT_CR_IM2_MASK (0xC0000U)

Definition at line 20895 of file MIMXRT1062.h.

## ◆ GPT_CR_IM2_SHIFT

#define GPT_CR_IM2_SHIFT (18U)

Definition at line 20896 of file MIMXRT1062.h.

## ◆ GPT_CR_OM1

#define GPT_CR_OM1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)

Definition at line 20906 of file MIMXRT1062.h.

## ◆ GPT_CR_OM1_MASK

#define GPT_CR_OM1_MASK (0x700000U)

Definition at line 20904 of file MIMXRT1062.h.

## ◆ GPT_CR_OM1_SHIFT

#define GPT_CR_OM1_SHIFT (20U)

Definition at line 20905 of file MIMXRT1062.h.

## ◆ GPT_CR_OM2

#define GPT_CR_OM2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)

Definition at line 20909 of file MIMXRT1062.h.

## ◆ GPT_CR_OM2_MASK

#define GPT_CR_OM2_MASK (0x3800000U)

Definition at line 20907 of file MIMXRT1062.h.

## ◆ GPT_CR_OM2_SHIFT

#define GPT_CR_OM2_SHIFT (23U)

Definition at line 20908 of file MIMXRT1062.h.

## ◆ GPT_CR_OM3

#define GPT_CR_OM3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)

OM3 0b000..Output disconnected. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.

Definition at line 20919 of file MIMXRT1062.h.

## ◆ GPT_CR_OM3_MASK

#define GPT_CR_OM3_MASK (0x1C000000U)

Definition at line 20910 of file MIMXRT1062.h.

## ◆ GPT_CR_OM3_SHIFT

#define GPT_CR_OM3_SHIFT (26U)

Definition at line 20911 of file MIMXRT1062.h.

## ◆ GPT_CR_STOPEN

#define GPT_CR_STOPEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)

STOPEN 0b0..GPT is disabled in Stop mode. 0b1..GPT is enabled in Stop mode.

Definition at line 20859 of file MIMXRT1062.h.

## ◆ GPT_CR_STOPEN_MASK

#define GPT_CR_STOPEN_MASK (0x20U)

Definition at line 20853 of file MIMXRT1062.h.

## ◆ GPT_CR_STOPEN_SHIFT

#define GPT_CR_STOPEN_SHIFT (5U)

Definition at line 20854 of file MIMXRT1062.h.

## ◆ GPT_CR_SWR

#define GPT_CR_SWR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)

SWR 0b0..GPT is not in reset state 0b1..GPT is in reset state

Definition at line 20891 of file MIMXRT1062.h.

## ◆ GPT_CR_SWR_MASK

#define GPT_CR_SWR_MASK (0x8000U)

Definition at line 20885 of file MIMXRT1062.h.

## ◆ GPT_CR_SWR_SHIFT

#define GPT_CR_SWR_SHIFT (15U)

Definition at line 20886 of file MIMXRT1062.h.

## ◆ GPT_CR_WAITEN

#define GPT_CR_WAITEN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)

WAITEN 0b0..GPT is disabled in wait mode. 0b1..GPT is enabled in wait mode.

Definition at line 20845 of file MIMXRT1062.h.

## ◆ GPT_CR_WAITEN_MASK

#define GPT_CR_WAITEN_MASK (0x8U)

Definition at line 20839 of file MIMXRT1062.h.

## ◆ GPT_CR_WAITEN_SHIFT

#define GPT_CR_WAITEN_SHIFT (3U)

Definition at line 20840 of file MIMXRT1062.h.

## ◆ GPT_ICR_CAPT

#define GPT_ICR_CAPT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)

Definition at line 21037 of file MIMXRT1062.h.

## ◆ GPT_ICR_CAPT_MASK

#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)

Definition at line 21035 of file MIMXRT1062.h.

## ◆ GPT_ICR_CAPT_SHIFT

#define GPT_ICR_CAPT_SHIFT (0U)

Definition at line 21036 of file MIMXRT1062.h.

## ◆ GPT_ICR_COUNT

#define GPT_ICR_COUNT (2U)

Definition at line 21041 of file MIMXRT1062.h.

## ◆ GPT_IR_IF1IE

#define GPT_IR_IF1IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)

Definition at line 21006 of file MIMXRT1062.h.

## ◆ GPT_IR_IF1IE_MASK

#define GPT_IR_IF1IE_MASK (0x8U)

Definition at line 21004 of file MIMXRT1062.h.

## ◆ GPT_IR_IF1IE_SHIFT

#define GPT_IR_IF1IE_SHIFT (3U)

Definition at line 21005 of file MIMXRT1062.h.

## ◆ GPT_IR_IF2IE

#define GPT_IR_IF2IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)

IF2IE 0b0..IF2IE Input Capture n Interrupt Enable is disabled. 0b1..IF2IE Input Capture n Interrupt Enable is enabled.

Definition at line 21013 of file MIMXRT1062.h.

## ◆ GPT_IR_IF2IE_MASK

#define GPT_IR_IF2IE_MASK (0x10U)

Definition at line 21007 of file MIMXRT1062.h.

## ◆ GPT_IR_IF2IE_SHIFT

#define GPT_IR_IF2IE_SHIFT (4U)

Definition at line 21008 of file MIMXRT1062.h.

## ◆ GPT_IR_OF1IE

#define GPT_IR_OF1IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)

Definition at line 20993 of file MIMXRT1062.h.

## ◆ GPT_IR_OF1IE_MASK

#define GPT_IR_OF1IE_MASK (0x1U)

Definition at line 20991 of file MIMXRT1062.h.

## ◆ GPT_IR_OF1IE_SHIFT

#define GPT_IR_OF1IE_SHIFT (0U)

Definition at line 20992 of file MIMXRT1062.h.

## ◆ GPT_IR_OF2IE

#define GPT_IR_OF2IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)

Definition at line 20996 of file MIMXRT1062.h.

## ◆ GPT_IR_OF2IE_MASK

#define GPT_IR_OF2IE_MASK (0x2U)

Definition at line 20994 of file MIMXRT1062.h.

## ◆ GPT_IR_OF2IE_SHIFT

#define GPT_IR_OF2IE_SHIFT (1U)

Definition at line 20995 of file MIMXRT1062.h.

## ◆ GPT_IR_OF3IE

#define GPT_IR_OF3IE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)

OF3IE 0b0..Output Compare Channel n interrupt is disabled. 0b1..Output Compare Channel n interrupt is enabled.

Definition at line 21003 of file MIMXRT1062.h.

## ◆ GPT_IR_OF3IE_MASK

#define GPT_IR_OF3IE_MASK (0x4U)

Definition at line 20997 of file MIMXRT1062.h.

## ◆ GPT_IR_OF3IE_SHIFT

#define GPT_IR_OF3IE_SHIFT (2U)

Definition at line 20998 of file MIMXRT1062.h.

## ◆ GPT_IR_ROVIE

#define GPT_IR_ROVIE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)

ROVIE 0b0..Rollover interrupt is disabled. 0b1..Rollover interrupt enabled.

Definition at line 21020 of file MIMXRT1062.h.

## ◆ GPT_IR_ROVIE_MASK

#define GPT_IR_ROVIE_MASK (0x20U)

Definition at line 21014 of file MIMXRT1062.h.

## ◆ GPT_IR_ROVIE_SHIFT

#define GPT_IR_ROVIE_SHIFT (5U)

Definition at line 21015 of file MIMXRT1062.h.

## ◆ GPT_OCR_COMP

#define GPT_OCR_COMP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)

Definition at line 21027 of file MIMXRT1062.h.

## ◆ GPT_OCR_COMP_MASK

#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)

Definition at line 21025 of file MIMXRT1062.h.

## ◆ GPT_OCR_COMP_SHIFT

#define GPT_OCR_COMP_SHIFT (0U)

Definition at line 21026 of file MIMXRT1062.h.

## ◆ GPT_OCR_COUNT

#define GPT_OCR_COUNT (3U)

Definition at line 21031 of file MIMXRT1062.h.

## ◆ GPT_PR_PRESCALER

#define GPT_PR_PRESCALER | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)

PRESCALER 0b000000000000..Divide by 1 0b000000000001..Divide by 2 0b111111111111..Divide by 4096

Definition at line 20944 of file MIMXRT1062.h.

## ◆ GPT_PR_PRESCALER24M

#define GPT_PR_PRESCALER24M | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)

PRESCALER24M 0b0000..Divide by 1 0b0001..Divide by 2 0b1111..Divide by 16

Definition at line 20952 of file MIMXRT1062.h.

## ◆ GPT_PR_PRESCALER24M_MASK

#define GPT_PR_PRESCALER24M_MASK (0xF000U)

Definition at line 20945 of file MIMXRT1062.h.

## ◆ GPT_PR_PRESCALER24M_SHIFT

#define GPT_PR_PRESCALER24M_SHIFT (12U)

Definition at line 20946 of file MIMXRT1062.h.

## ◆ GPT_PR_PRESCALER_MASK

#define GPT_PR_PRESCALER_MASK (0xFFFU)

Definition at line 20937 of file MIMXRT1062.h.

## ◆ GPT_PR_PRESCALER_SHIFT

#define GPT_PR_PRESCALER_SHIFT (0U)

Definition at line 20938 of file MIMXRT1062.h.

## ◆ GPT_SR_IF1

#define GPT_SR_IF1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)

Definition at line 20972 of file MIMXRT1062.h.

## ◆ GPT_SR_IF1_MASK

#define GPT_SR_IF1_MASK (0x8U)

Definition at line 20970 of file MIMXRT1062.h.

## ◆ GPT_SR_IF1_SHIFT

#define GPT_SR_IF1_SHIFT (3U)

Definition at line 20971 of file MIMXRT1062.h.

## ◆ GPT_SR_IF2

#define GPT_SR_IF2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)

IF2 0b0..Capture event has not occurred. 0b1..Capture event has occurred.

Definition at line 20979 of file MIMXRT1062.h.

## ◆ GPT_SR_IF2_MASK

#define GPT_SR_IF2_MASK (0x10U)

Definition at line 20973 of file MIMXRT1062.h.

## ◆ GPT_SR_IF2_SHIFT

#define GPT_SR_IF2_SHIFT (4U)

Definition at line 20974 of file MIMXRT1062.h.

## ◆ GPT_SR_OF1

#define GPT_SR_OF1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)

Definition at line 20959 of file MIMXRT1062.h.

## ◆ GPT_SR_OF1_MASK

#define GPT_SR_OF1_MASK (0x1U)

Definition at line 20957 of file MIMXRT1062.h.

## ◆ GPT_SR_OF1_SHIFT

#define GPT_SR_OF1_SHIFT (0U)

Definition at line 20958 of file MIMXRT1062.h.

## ◆ GPT_SR_OF2

#define GPT_SR_OF2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)

Definition at line 20962 of file MIMXRT1062.h.

## ◆ GPT_SR_OF2_MASK

#define GPT_SR_OF2_MASK (0x2U)

Definition at line 20960 of file MIMXRT1062.h.

## ◆ GPT_SR_OF2_SHIFT

#define GPT_SR_OF2_SHIFT (1U)

Definition at line 20961 of file MIMXRT1062.h.

## ◆ GPT_SR_OF3

#define GPT_SR_OF3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)

OF3 0b0..Compare event has not occurred. 0b1..Compare event has occurred.

Definition at line 20969 of file MIMXRT1062.h.

## ◆ GPT_SR_OF3_MASK

#define GPT_SR_OF3_MASK (0x4U)

Definition at line 20963 of file MIMXRT1062.h.

## ◆ GPT_SR_OF3_SHIFT

#define GPT_SR_OF3_SHIFT (2U)

Definition at line 20964 of file MIMXRT1062.h.

## ◆ GPT_SR_ROV

#define GPT_SR_ROV | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)

ROV 0b0..Rollover has not occurred. 0b1..Rollover has occurred.

Definition at line 20986 of file MIMXRT1062.h.

## ◆ GPT_SR_ROV_MASK

#define GPT_SR_ROV_MASK (0x20U)

Definition at line 20980 of file MIMXRT1062.h.

## ◆ GPT_SR_ROV_SHIFT

#define GPT_SR_ROV_SHIFT (5U)

Definition at line 20981 of file MIMXRT1062.h.