Callisto4Bootloader: c4_SRC_reg_t Struct Reference

Callisto4Bootloader

Data Fields
c4_SRC_reg_t Struct Reference

System Reset Controller (SRC) More...

`#include <c4_watchdog_types.h>`

## Data Fields

union {
struct {
uint32_t rsvd_0: 7
uint32_t maskWdogRst: 4
| Mask wdog_rst_b source. More...
uint32_t rsvd_1: 2
uint32_t core0Rst: 1
| Software reset for core0 only. More...
uint32_t rsvd_2: 3
uint32_t core0DbgRst: 1
| Software reset for core0 debug only. More...
uint32_t rsvd_3: 7
uint32_t dbgRstMskPg: 1
| Do not assert debug resets after power gating event of core. More...
uint32_t rsvd_4: 2
uint32_t maskWdog3Rst: 4
| Mask wdog3_rst_b source. More...
} B
uint32_t R
} | SCR
| SRC Control Register (SRC_SCR) More...
union {
struct {
uint32_t bootCfg1: 8
uint32_t bootCfg2: 8
uint32_t bootCfg3: 8
uint32_t bootCfg4: 8
} B
uint32_t R
} | SBMR1
| SRC Boot Mode Register 1 (SRC_SBMR1) More...
union {
struct {
uint32_t ippResetB: 1
| Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) More...
uint32_t lockupSysResetReq: 1
| Indicates a reset has been caused by CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core. More...
uint32_t csuResetB: 1
| Indicates whether the reset was the result of the csu_reset_b input. More...
uint32_t ippUserResetB: 1
| Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. More...
uint32_t wdogRstB: 1
| IC Watchdog Time-out reset. Indicates whether the reset was the result of the watchdog time-out event. More...
uint32_t jtagRstB: 1
| HIGH - Z JTAG reset. More...
uint32_t jtagSwRst: 1
| JTAG software reset. More...
uint32_t wdog3RstB: 1
| IC Watchdog3 Time-out reset. More...
uint32_t tempSenseRstB: 1
| Temper Sensor software reset. More...
uint32_t rsvd_0: 23
| Reserved. More...
} B
uint32_t R
} | SRSR
uint32_t | RESERVED_0 [4]
| Reserved. More...
union {
struct {
uint32_t secConfig: 2
| SECONFIG[1] shows the state of the SECONFIG[1] fuse. More...
uint32_t rsvd_0: 1
| This read-only field is reserved and always has the value 0. More...
uint32_t dirBtDis: 1
| DIR_BT_DIS shows the state of the DIR_BT_DIS fuse. More...
uint32_t btFuseSel: 1
| BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse. See Fusemap for additional information on this fuse. More...
uint32_t rsvd1: 19
| This read-only field is reserved and always has the value 0. More...
uint32_t bmod: 2
| BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B. More...
uint32_t rsvd_3: 6
| This read-only field is reserved and always has the value 0. More...
} B
uint32_t R
} | SBMR2
union {
struct {
uint32_t rsvd_0
| Reserved. More...
} B
uint32_t R
} | GPR [10]

## Detailed Description

System Reset Controller (SRC)

This uses bitfield structures to represent the register elements and is overlaid on the memory-mapped registers. It is equivalent to the

See also
  WDOG_Type defined in FreeRTOS which uses shift and mask macros.

Definition at line 282 of file c4_watchdog_types.h.

## Field Documentation

## ◆ B [1/5]

struct { ... } c4_SRC_reg_t::B

Bitfield representation.

## ◆ B [2/5]

struct { ... } c4_SRC_reg_t::B

Bitfield representation.

## ◆ B [3/5]

struct { ... } c4_SRC_reg_t::B

Bitfield representation.

## ◆ B [4/5]

struct { ... } c4_SRC_reg_t::B

Bitfield representation.

## ◆ B [5/5]

struct { ... } c4_SRC_reg_t::B

Bitfield representation.

## ◆ bmod

uint32_t c4_SRC_reg_t::bmod

BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B.

See the Boot mode pin settings section of System Boot.

Definition at line 467 of file c4_watchdog_types.h.

## ◆ bootCfg1

uint32_t c4_SRC_reg_t::bootCfg1

Refer to fusemap.

Definition at line 356 of file c4_watchdog_types.h.

## ◆ bootCfg2

uint32_t c4_SRC_reg_t::bootCfg2

Refer to fusemap.

Definition at line 357 of file c4_watchdog_types.h.

## ◆ bootCfg3

uint32_t c4_SRC_reg_t::bootCfg3

Refer to fusemap.

Definition at line 358 of file c4_watchdog_types.h.

## ◆ bootCfg4

uint32_t c4_SRC_reg_t::bootCfg4

Refer to fusemap.

Definition at line 359 of file c4_watchdog_types.h.

## ◆ btFuseSel

uint32_t c4_SRC_reg_t::btFuseSel

BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse. See Fusemap for additional information on this fuse.

Definition at line 464 of file c4_watchdog_types.h.

## ◆ core0DbgRst

uint32_t c4_SRC_reg_t::core0DbgRst

Software reset for core0 debug only.

Note
  This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this bit will be self cleared.

- 0 do not assert core0 debug reset
- 1 assert core0 debug reset

Definition at line 319 of file c4_watchdog_types.h.

## ◆ core0Rst

uint32_t c4_SRC_reg_t::core0Rst

Software reset for core0 only.

Note
  : This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this bit will be self cleared.

- 0 do not assert core0 reset
- 1 assert core0 reset

Definition at line 311 of file c4_watchdog_types.h.

## ◆ csuResetB

uint32_t c4_SRC_reg_t::csuResetB

Indicates whether the reset was the result of the csu_reset_b input.

- 0 Reset is not a result of the csu_reset_b event.
- 1 Reset is a result of the csu_reset_b event.

Definition at line 394 of file c4_watchdog_types.h.

## ◆ dbgRstMskPg

uint32_t c4_SRC_reg_t::dbgRstMskPg

Do not assert debug resets after power gating event of core.

- 0 do not mask core debug resets (debug resets will be asserted after power gating event)
- 1 mask core debug resets (debug resets won't be asserted after power gating event)

Definition at line 327 of file c4_watchdog_types.h.

## ◆ dirBtDis

uint32_t c4_SRC_reg_t::dirBtDis

DIR_BT_DIS shows the state of the DIR_BT_DIS fuse.

See Chapter 5, Fusemap for additional information on this fuse.

Definition at line 461 of file c4_watchdog_types.h.

## ◆ GPR

union { ... } c4_SRC_reg_t::GPR[10]

SRC General Purpose Register (SRC_GPR#)

Note
  These registers are used by the ROM code and should not be used by application software.

## ◆ ippResetB

uint32_t c4_SRC_reg_t::ippResetB

Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)

- 0 Reset is not a result of ipp_reset_b pin.
- 1 Reset is a result of ipp_reset_b pin.

Definition at line 379 of file c4_watchdog_types.h.

## ◆ ippUserResetB

uint32_t c4_SRC_reg_t::ippUserResetB

Indicates whether the reset was the result of the ipp_user_reset_b qualified reset.

- 0 Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
- 1 Reset is a result of the ipp_user_reset_b qualified as COLD reset event.

Definition at line 399 of file c4_watchdog_types.h.

## ◆ jtagRstB

uint32_t c4_SRC_reg_t::jtagRstB

HIGH - Z JTAG reset.

Indicates whether the reset was the result of HIGH-Z reset from JTA

- 0 Reset is not a result of HIGH-Z reset from JTAG.
- 1 Reset is a result of HIGH-Z reset from JTAG.

Definition at line 410 of file c4_watchdog_types.h.

## ◆ jtagSwRst

uint32_t c4_SRC_reg_t::jtagSwRst

JTAG software reset.

Indicates whether the reset was the result of software reset from JTAG.

- 0 Reset is not a result of software reset from JTAG.
- 1 Reset is a result of software reset from JTAG.

Definition at line 417 of file c4_watchdog_types.h.

## ◆ lockupSysResetReq

uint32_t c4_SRC_reg_t::lockupSysResetReq

Indicates a reset has been caused by CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core.

SW needs to set some GPR bit before writing SYSRESETREQ bit and use the GPR bit to distinguish if the reset is caused by SYSRESETREQ or CPU lockup.

- 0 Reset is not a result of the mentioned case.
- 1 Reset is a result of the mentioned case.

Definition at line 384 of file c4_watchdog_types.h.

## ◆ maskWdog3Rst

uint32_t c4_SRC_reg_t::maskWdog3Rst

Mask wdog3_rst_b source.

If these 4 bits are coded from A to 5 then, the wdog3_rst_b input to SRC will be masked and the wdog3_rst_b will not create a reset to the chip.

Note
  Any other code than 0101 will be coded to 1010 i.e. wdog3_rst_b is not masked

- 0101 wdog3_rst_b is masked
- 1010 wdog3_rst_b is not masked

Definition at line 332 of file c4_watchdog_types.h.

## ◆ maskWdogRst

uint32_t c4_SRC_reg_t::maskWdogRst

Mask wdog_rst_b source.

If these 4 bits are coded from A to 5 then, the wdog_rst_b input to SRC will be masked and the wdog_rst_b will not create a reset to the chip.

Note
  During the time the WDOG event is masked using SRC logic, it is likely that the WDOG Reset Status Register (WRSR) bit 1 (which indicates a WDOG timeout event) will get asserted. software / OS developer must prepare for this case. Re-enabling the WDOG is possible, by unmasking it in SRC, though it must be preceded by servicing the WDOG. However, for the case that the event has been asserted, the status bit (WRSR bit-1) will remain asserted, regardless of servicing the WDOG module.

(Hardware reset is the only way to cause the de-assertion of that bit).

any other code will be coded to 1010 i.e. wdog_rst_b is not masked

- 0101 wdog_rst_b is masked
- 1010 wdog_rst_b is not masked (default)

Definition at line 293 of file c4_watchdog_types.h.

## ◆ R

uint32_t c4_SRC_reg_t::R

Register representation.

Definition at line 342 of file c4_watchdog_types.h.

## ◆ RESERVED_0

uint32_t c4_SRC_reg_t::RESERVED_0[4]

Reserved.

SRC Boot Mode Register 2 (SRC_SBMR2)

The Boot Mode register (SBMR), contains bits that reflect the status of Boot Mode Pins of the chip. The default values for those bits depends on the values of pins/fuses during reset sequence, hence the question mark on their default value.

Definition at line 444 of file c4_watchdog_types.h.

## ◆ rsvd1

uint32_t c4_SRC_reg_t::rsvd1

This read-only field is reserved and always has the value 0.

Definition at line 466 of file c4_watchdog_types.h.

## ◆ rsvd_0

uint32_t c4_SRC_reg_t::rsvd_0

Reserved.

This read-only field is reserved and always has the value 0.

Reserved

Definition at line 292 of file c4_watchdog_types.h.

## ◆ rsvd_1

uint32_t c4_SRC_reg_t::rsvd_1

Reserved

Definition at line 310 of file c4_watchdog_types.h.

## ◆ rsvd_2

uint32_t c4_SRC_reg_t::rsvd_2

This read-only field is reserved and always has the value 0.

Definition at line 318 of file c4_watchdog_types.h.

## ◆ rsvd_3

uint32_t c4_SRC_reg_t::rsvd_3

This read-only field is reserved and always has the value 0.

Reserved

Definition at line 326 of file c4_watchdog_types.h.

## ◆ rsvd_4

uint32_t c4_SRC_reg_t::rsvd_4

Reserved

Definition at line 331 of file c4_watchdog_types.h.

## ◆ SBMR1

union { ... } c4_SRC_reg_t::SBMR1

SRC Boot Mode Register 1 (SRC_SBMR1)

The Boot Mode register (SBMR) contains bits that reflect the status of Boot Mode Pins of the chip. The reset value is configuration dependent (depending on boot/fuses/IO pads). If SRC_GPR10[28] bit is set, this bit instructs the ROM code to use the SRC_GPR9 register as if it is SBMR1. This allows software to override the fuse bits and boot from an alternate boot source.

SRC Reset Status Register (SRC_SRSR)

The SRSR is a write to one clear register which records the source of the reset events for the chip. The SRC reset status register will capture all the reset sources that have occurred. This register is reset on ipp_reset_b. This is a read-write register.

For bit[6-0] - writing zero does not have any effect. Writing one will clear the corresponding bit. The individual bits can be cleared by writing one to that bit. When the system comes out of reset, this register will have bits set corresponding to all the reset sources that occurred during system reset. Software has to take care to clear this register by writing one after every reset that occurs so that the register will contain the information of recently occurred reset.

## ◆ SBMR2

union { ... } c4_SRC_reg_t::SBMR2

## ◆ SCR

union { ... } c4_SRC_reg_t::SCR

SRC Control Register (SRC_SCR)

The Reset control register (SCR), contains bits that control operation of the reset controller.

## ◆ secConfig

uint32_t c4_SRC_reg_t::secConfig

SECONFIG[1] shows the state of the SECONFIG[1] fuse.

See Fusemap for additional information on this fuse. SECONFIG[0] shows the state of the SECONFIG[0] fuse. This fuse is shown as reserved in Fusemap (address 0x440[1]) because it does not have a user-relevant function.

Definition at line 455 of file c4_watchdog_types.h.

## ◆ SRSR

union { ... } c4_SRC_reg_t::SRSR

## ◆ tempSenseRstB

uint32_t c4_SRC_reg_t::tempSenseRstB

Temper Sensor software reset.

Indicates whether the reset was the result of software reset from on-chip Temperature Sensor.

- 0 Reset is not a result of software reset from Temperature Sensor.
- 1 Reset is a result of software reset from Temperature Sensor.

Definition at line 431 of file c4_watchdog_types.h.

## ◆ wdog3RstB

uint32_t c4_SRC_reg_t::wdog3RstB

IC Watchdog3 Time-out reset.

Indicates whether the reset was the result of the watchdog3 time-out event.

- 0 Reset is not a result of the watchdog3 time-out event.
- 1 Reset is a result of the watchdog3 time-out event.

Definition at line 424 of file c4_watchdog_types.h.

## ◆ wdogRstB

uint32_t c4_SRC_reg_t::wdogRstB

IC Watchdog Time-out reset. Indicates whether the reset was the result of the watchdog time-out event.

- 0 Reset is not a result of the watchdog time-out event.
- 1 Reset is a result of the watchdog time-out event.

Definition at line 404 of file c4_watchdog_types.h.

The documentation for this struct was generated from the following file:

- lib/c4_watchdog_types.h