Callisto4Bootloader: SRC Register Masks

Callisto4Bootloader

Macros
SRC Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » SRC Peripheral Access Layer

## Macros

#define | SRC_GPR_COUNT (10U)

## SCR - SRC Control Register

#define | SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
#define | SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
#define | SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
#define | SRC_SCR_CORE0_RST_MASK (0x2000U)
#define | SRC_SCR_CORE0_RST_SHIFT (13U)
#define | SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
#define | SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
#define | SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
#define | SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
#define | SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
#define | SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
#define | SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
#define | SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
#define | SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
#define | SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)

## SBMR1 - SRC Boot Mode Register 1

#define | SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
#define | SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
#define | SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
#define | SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
#define | SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
#define | SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
#define | SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
#define | SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
#define | SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
#define | SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
#define | SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
#define | SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)

## SRSR - SRC Reset Status Register

#define | SRC_SRSR_IPP_RESET_B_MASK (0x1U)
#define | SRC_SRSR_IPP_RESET_B_SHIFT (0U)
#define | SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
#define | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)
#define | SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)
#define | SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
#define | SRC_SRSR_CSU_RESET_B_MASK (0x4U)
#define | SRC_SRSR_CSU_RESET_B_SHIFT (2U)
#define | SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
#define | SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
#define | SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
#define | SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
#define | SRC_SRSR_WDOG_RST_B_MASK (0x10U)
#define | SRC_SRSR_WDOG_RST_B_SHIFT (4U)
#define | SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
#define | SRC_SRSR_JTAG_RST_B_MASK (0x20U)
#define | SRC_SRSR_JTAG_RST_B_SHIFT (5U)
#define | SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
#define | SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
#define | SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
#define | SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
#define | SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
#define | SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
#define | SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
#define | SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
#define | SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
#define | SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)

## SBMR2 - SRC Boot Mode Register 2

#define | SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
#define | SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
#define | SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
#define | SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
#define | SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
#define | SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
#define | SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
#define | SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
#define | SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
#define | SRC_SBMR2_BMOD_MASK (0x3000000U)
#define | SRC_SBMR2_BMOD_SHIFT (24U)
#define | SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)

## GPR - SRC General Purpose Register 1..SRC General Purpose Register 10

#define | SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
#define | SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
#define | SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
#define | SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
#define | SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
#define | SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ SRC_GPR_COUNT

#define SRC_GPR_COUNT (10U)

Definition at line 39453 of file MIMXRT1062.h.

## ◆ SRC_GPR_PERSISTENT_ARG0

#define SRC_GPR_PERSISTENT_ARG0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)

Definition at line 39446 of file MIMXRT1062.h.

## ◆ SRC_GPR_PERSISTENT_ARG0_MASK

#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)

Definition at line 39444 of file MIMXRT1062.h.

## ◆ SRC_GPR_PERSISTENT_ARG0_SHIFT

#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)

Definition at line 39445 of file MIMXRT1062.h.

## ◆ SRC_GPR_PERSISTENT_ENTRY0

#define SRC_GPR_PERSISTENT_ENTRY0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)

Definition at line 39449 of file MIMXRT1062.h.

## ◆ SRC_GPR_PERSISTENT_ENTRY0_MASK

#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)

Definition at line 39447 of file MIMXRT1062.h.

## ◆ SRC_GPR_PERSISTENT_ENTRY0_SHIFT

#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)

Definition at line 39448 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG1

#define SRC_SBMR1_BOOT_CFG1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)

Definition at line 39347 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG1_MASK

#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)

Definition at line 39345 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG1_SHIFT

#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)

Definition at line 39346 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG2

#define SRC_SBMR1_BOOT_CFG2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)

Definition at line 39350 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG2_MASK

#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)

Definition at line 39348 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG2_SHIFT

#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)

Definition at line 39349 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG3

#define SRC_SBMR1_BOOT_CFG3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)

Definition at line 39353 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG3_MASK

#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)

Definition at line 39351 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG3_SHIFT

#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)

Definition at line 39352 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG4

#define SRC_SBMR1_BOOT_CFG4 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)

Definition at line 39356 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG4_MASK

#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)

Definition at line 39354 of file MIMXRT1062.h.

## ◆ SRC_SBMR1_BOOT_CFG4_SHIFT

#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)

Definition at line 39355 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_BMOD

#define SRC_SBMR2_BMOD | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)

Definition at line 39439 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_BMOD_MASK

#define SRC_SBMR2_BMOD_MASK (0x3000000U)

Definition at line 39437 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_BMOD_SHIFT

#define SRC_SBMR2_BMOD_SHIFT (24U)

Definition at line 39438 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_BT_FUSE_SEL

#define SRC_SBMR2_BT_FUSE_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)

Definition at line 39436 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_BT_FUSE_SEL_MASK

#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)

Definition at line 39434 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_BT_FUSE_SEL_SHIFT

#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)

Definition at line 39435 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_DIR_BT_DIS

#define SRC_SBMR2_DIR_BT_DIS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)

Definition at line 39433 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_DIR_BT_DIS_MASK

#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)

Definition at line 39431 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_DIR_BT_DIS_SHIFT

#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)

Definition at line 39432 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_SEC_CONFIG

#define SRC_SBMR2_SEC_CONFIG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)

Definition at line 39430 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_SEC_CONFIG_MASK

#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)

Definition at line 39428 of file MIMXRT1062.h.

## ◆ SRC_SBMR2_SEC_CONFIG_SHIFT

#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)

Definition at line 39429 of file MIMXRT1062.h.

## ◆ SRC_SCR_CORE0_DBG_RST

#define SRC_SCR_CORE0_DBG_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)

core0_dbg_rst 0b0..do not assert core0 debug reset 0b1..assert core0 debug reset

Definition at line 39326 of file MIMXRT1062.h.

## ◆ SRC_SCR_CORE0_DBG_RST_MASK

#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)

Definition at line 39320 of file MIMXRT1062.h.

## ◆ SRC_SCR_CORE0_DBG_RST_SHIFT

#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U)

Definition at line 39321 of file MIMXRT1062.h.

## ◆ SRC_SCR_CORE0_RST

#define SRC_SCR_CORE0_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)

core0_rst 0b0..do not assert core0 reset 0b1..assert core0 reset

Definition at line 39319 of file MIMXRT1062.h.

## ◆ SRC_SCR_CORE0_RST_MASK

#define SRC_SCR_CORE0_RST_MASK (0x2000U)

Definition at line 39313 of file MIMXRT1062.h.

## ◆ SRC_SCR_CORE0_RST_SHIFT

#define SRC_SCR_CORE0_RST_SHIFT (13U)

Definition at line 39314 of file MIMXRT1062.h.

## ◆ SRC_SCR_DBG_RST_MSK_PG

#define SRC_SCR_DBG_RST_MSK_PG | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)

dbg_rst_msk_pg 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) 0b1..mask core debug resets (debug resets won't be asserted after power gating event)

Definition at line 39333 of file MIMXRT1062.h.

## ◆ SRC_SCR_DBG_RST_MSK_PG_MASK

#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)

Definition at line 39327 of file MIMXRT1062.h.

## ◆ SRC_SCR_DBG_RST_MSK_PG_SHIFT

#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)

Definition at line 39328 of file MIMXRT1062.h.

## ◆ SRC_SCR_MASK_WDOG3_RST

#define SRC_SCR_MASK_WDOG3_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)

mask_wdog3_rst 0b0101..wdog3_rst_b is masked 0b1010..wdog3_rst_b is not masked

Definition at line 39340 of file MIMXRT1062.h.

## ◆ SRC_SCR_MASK_WDOG3_RST_MASK

#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)

Definition at line 39334 of file MIMXRT1062.h.

## ◆ SRC_SCR_MASK_WDOG3_RST_SHIFT

#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)

Definition at line 39335 of file MIMXRT1062.h.

## ◆ SRC_SCR_MASK_WDOG_RST

#define SRC_SCR_MASK_WDOG_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)

mask_wdog_rst 0b0101..wdog_rst_b is masked 0b1010..wdog_rst_b is not masked (default)

Definition at line 39312 of file MIMXRT1062.h.

## ◆ SRC_SCR_MASK_WDOG_RST_MASK

#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U)

Definition at line 39306 of file MIMXRT1062.h.

## ◆ SRC_SCR_MASK_WDOG_RST_SHIFT

#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U)

Definition at line 39307 of file MIMXRT1062.h.

## ◆ SRC_SRSR_CSU_RESET_B

#define SRC_SRSR_CSU_RESET_B | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)

csu_reset_b 0b0..Reset is not a result of the csu_reset_b event. 0b1..Reset is a result of the csu_reset_b event.

Definition at line 39381 of file MIMXRT1062.h.

## ◆ SRC_SRSR_CSU_RESET_B_MASK

#define SRC_SRSR_CSU_RESET_B_MASK (0x4U)

Definition at line 39375 of file MIMXRT1062.h.

## ◆ SRC_SRSR_CSU_RESET_B_SHIFT

#define SRC_SRSR_CSU_RESET_B_SHIFT (2U)

Definition at line 39376 of file MIMXRT1062.h.

## ◆ SRC_SRSR_IPP_RESET_B

#define SRC_SRSR_IPP_RESET_B | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)

ipp_reset_b 0b0..Reset is not a result of ipp_reset_b pin. 0b1..Reset is a result of ipp_reset_b pin.

Definition at line 39367 of file MIMXRT1062.h.

## ◆ SRC_SRSR_IPP_RESET_B_MASK

#define SRC_SRSR_IPP_RESET_B_MASK (0x1U)

Definition at line 39361 of file MIMXRT1062.h.

## ◆ SRC_SRSR_IPP_RESET_B_SHIFT

#define SRC_SRSR_IPP_RESET_B_SHIFT (0U)

Definition at line 39362 of file MIMXRT1062.h.

## ◆ SRC_SRSR_IPP_USER_RESET_B

#define SRC_SRSR_IPP_USER_RESET_B | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)

ipp_user_reset_b 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.

Definition at line 39388 of file MIMXRT1062.h.

## ◆ SRC_SRSR_IPP_USER_RESET_B_MASK

#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)

Definition at line 39382 of file MIMXRT1062.h.

## ◆ SRC_SRSR_IPP_USER_RESET_B_SHIFT

#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)

Definition at line 39383 of file MIMXRT1062.h.

## ◆ SRC_SRSR_JTAG_RST_B

#define SRC_SRSR_JTAG_RST_B | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)

jtag_rst_b 0b0..Reset is not a result of HIGH-Z reset from JTAG. 0b1..Reset is a result of HIGH-Z reset from JTAG.

Definition at line 39402 of file MIMXRT1062.h.

## ◆ SRC_SRSR_JTAG_RST_B_MASK

#define SRC_SRSR_JTAG_RST_B_MASK (0x20U)

Definition at line 39396 of file MIMXRT1062.h.

## ◆ SRC_SRSR_JTAG_RST_B_SHIFT

#define SRC_SRSR_JTAG_RST_B_SHIFT (5U)

Definition at line 39397 of file MIMXRT1062.h.

## ◆ SRC_SRSR_JTAG_SW_RST

#define SRC_SRSR_JTAG_SW_RST | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)

jtag_sw_rst 0b0..Reset is not a result of software reset from JTAG. 0b1..Reset is a result of software reset from JTAG.

Definition at line 39409 of file MIMXRT1062.h.

## ◆ SRC_SRSR_JTAG_SW_RST_MASK

#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)

Definition at line 39403 of file MIMXRT1062.h.

## ◆ SRC_SRSR_JTAG_SW_RST_SHIFT

#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)

Definition at line 39404 of file MIMXRT1062.h.

## ◆ SRC_SRSR_LOCKUP_SYSRESETREQ

#define SRC_SRSR_LOCKUP_SYSRESETREQ | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)

lockup_sysresetreq 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

Definition at line 39374 of file MIMXRT1062.h.

## ◆ SRC_SRSR_LOCKUP_SYSRESETREQ_MASK

#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)

Definition at line 39368 of file MIMXRT1062.h.

## ◆ SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT

#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)

Definition at line 39369 of file MIMXRT1062.h.

## ◆ SRC_SRSR_TEMPSENSE_RST_B

#define SRC_SRSR_TEMPSENSE_RST_B | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)

tempsense_rst_b 0b0..Reset is not a result of software reset from Temperature Sensor. 0b1..Reset is a result of software reset from Temperature Sensor.

Definition at line 39423 of file MIMXRT1062.h.

## ◆ SRC_SRSR_TEMPSENSE_RST_B_MASK

#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)

Definition at line 39417 of file MIMXRT1062.h.

## ◆ SRC_SRSR_TEMPSENSE_RST_B_SHIFT

#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)

Definition at line 39418 of file MIMXRT1062.h.

## ◆ SRC_SRSR_WDOG3_RST_B

#define SRC_SRSR_WDOG3_RST_B | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)

wdog3_rst_b 0b0..Reset is not a result of the watchdog3 time-out event. 0b1..Reset is a result of the watchdog3 time-out event.

Definition at line 39416 of file MIMXRT1062.h.

## ◆ SRC_SRSR_WDOG3_RST_B_MASK

#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)

Definition at line 39410 of file MIMXRT1062.h.

## ◆ SRC_SRSR_WDOG3_RST_B_SHIFT

#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)

Definition at line 39411 of file MIMXRT1062.h.

## ◆ SRC_SRSR_WDOG_RST_B

#define SRC_SRSR_WDOG_RST_B | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)

wdog_rst_b 0b0..Reset is not a result of the watchdog time-out event. 0b1..Reset is a result of the watchdog time-out event.

Definition at line 39395 of file MIMXRT1062.h.

## ◆ SRC_SRSR_WDOG_RST_B_MASK

#define SRC_SRSR_WDOG_RST_B_MASK (0x10U)

Definition at line 39389 of file MIMXRT1062.h.

## ◆ SRC_SRSR_WDOG_RST_B_SHIFT

#define SRC_SRSR_WDOG_RST_B_SHIFT (4U)

Definition at line 39390 of file MIMXRT1062.h.