Callisto4Bootloader: BEE Register Masks

Callisto4Bootloader

BEE Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » BEE Peripheral Access Layer

## CTRL - Control Register

#define | BEE_CTRL_BEE_ENABLE_MASK (0x1U)
#define | BEE_CTRL_BEE_ENABLE_SHIFT (0U)
#define | BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
#define | BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
#define | BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
#define | BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
#define | BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
#define | BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
#define | BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
#define | BEE_CTRL_KEY_VALID_MASK (0x10U)
#define | BEE_CTRL_KEY_VALID_SHIFT (4U)
#define | BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
#define | BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
#define | BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
#define | BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
#define | BEE_CTRL_AC_PROT_EN_MASK (0x40U)
#define | BEE_CTRL_AC_PROT_EN_SHIFT (6U)
#define | BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
#define | BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
#define | BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
#define | BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
#define | BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
#define | BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
#define | BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
#define | BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
#define | BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
#define | BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
#define | BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
#define | BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
#define | BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
#define | BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
#define | BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
#define | BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
#define | BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
#define | BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
#define | BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
#define | BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
#define | BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
#define | BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
#define | BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
#define | BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
#define | BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
#define | BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
#define | BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
#define | BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
#define | BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
#define | BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
#define | BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
#define | BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
#define | BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
#define | BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
#define | BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
#define | BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
#define | BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
#define | BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
#define | BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
#define | BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
#define | BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
#define | BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
#define | BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
#define | BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
#define | BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
#define | BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
#define | BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
#define | BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
#define | BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
#define | BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
#define | BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
#define | BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
#define | BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
#define | BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
#define | BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
#define | BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
#define | BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
#define | BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
#define | ENC_CTRL_CMPIE_MASK (0x1U)
#define | ENC_CTRL_CMPIE_SHIFT (0U)
#define | ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
#define | ENC_CTRL_CMPIRQ_MASK (0x2U)
#define | ENC_CTRL_CMPIRQ_SHIFT (1U)
#define | ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
#define | ENC_CTRL_WDE_MASK (0x4U)
#define | ENC_CTRL_WDE_SHIFT (2U)
#define | ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
#define | ENC_CTRL_DIE_MASK (0x8U)
#define | ENC_CTRL_DIE_SHIFT (3U)
#define | ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
#define | ENC_CTRL_DIRQ_MASK (0x10U)
#define | ENC_CTRL_DIRQ_SHIFT (4U)
#define | ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
#define | ENC_CTRL_XNE_MASK (0x20U)
#define | ENC_CTRL_XNE_SHIFT (5U)
#define | ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
#define | ENC_CTRL_XIP_MASK (0x40U)
#define | ENC_CTRL_XIP_SHIFT (6U)
#define | ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
#define | ENC_CTRL_XIE_MASK (0x80U)
#define | ENC_CTRL_XIE_SHIFT (7U)
#define | ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
#define | ENC_CTRL_XIRQ_MASK (0x100U)
#define | ENC_CTRL_XIRQ_SHIFT (8U)
#define | ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
#define | ENC_CTRL_PH1_MASK (0x200U)
#define | ENC_CTRL_PH1_SHIFT (9U)
#define | ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
#define | ENC_CTRL_REV_MASK (0x400U)
#define | ENC_CTRL_REV_SHIFT (10U)
#define | ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
#define | ENC_CTRL_SWIP_MASK (0x800U)
#define | ENC_CTRL_SWIP_SHIFT (11U)
#define | ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
#define | ENC_CTRL_HNE_MASK (0x1000U)
#define | ENC_CTRL_HNE_SHIFT (12U)
#define | ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
#define | ENC_CTRL_HIP_MASK (0x2000U)
#define | ENC_CTRL_HIP_SHIFT (13U)
#define | ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
#define | ENC_CTRL_HIE_MASK (0x4000U)
#define | ENC_CTRL_HIE_SHIFT (14U)
#define | ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
#define | ENC_CTRL_HIRQ_MASK (0x8000U)
#define | ENC_CTRL_HIRQ_SHIFT (15U)
#define | ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
#define | EWM_CTRL_EWMEN_MASK (0x1U)
#define | EWM_CTRL_EWMEN_SHIFT (0U)
#define | EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
#define | EWM_CTRL_ASSIN_MASK (0x2U)
#define | EWM_CTRL_ASSIN_SHIFT (1U)
#define | EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
#define | EWM_CTRL_INEN_MASK (0x4U)
#define | EWM_CTRL_INEN_SHIFT (2U)
#define | EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
#define | EWM_CTRL_INTEN_MASK (0x8U)
#define | EWM_CTRL_INTEN_SHIFT (3U)
#define | EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
#define | PWM_CTRL_DBLEN_MASK (0x1U)
#define | PWM_CTRL_DBLEN_SHIFT (0U)
#define | PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
#define | PWM_CTRL_DBLX_MASK (0x2U)
#define | PWM_CTRL_DBLX_SHIFT (1U)
#define | PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
#define | PWM_CTRL_LDMOD_MASK (0x4U)
#define | PWM_CTRL_LDMOD_SHIFT (2U)
#define | PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
#define | PWM_CTRL_SPLIT_MASK (0x8U)
#define | PWM_CTRL_SPLIT_SHIFT (3U)
#define | PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
#define | PWM_CTRL_PRSC_MASK (0x70U)
#define | PWM_CTRL_PRSC_SHIFT (4U)
#define | PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
#define | PWM_CTRL_COMPMODE_MASK (0x80U)
#define | PWM_CTRL_COMPMODE_SHIFT (7U)
#define | PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
#define | PWM_CTRL_DT_MASK (0x300U)
#define | PWM_CTRL_DT_SHIFT (8U)
#define | PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
#define | PWM_CTRL_FULL_MASK (0x400U)
#define | PWM_CTRL_FULL_SHIFT (10U)
#define | PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
#define | PWM_CTRL_HALF_MASK (0x800U)
#define | PWM_CTRL_HALF_SHIFT (11U)
#define | PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
#define | PWM_CTRL_LDFQ_MASK (0xF000U)
#define | PWM_CTRL_LDFQ_SHIFT (12U)
#define | PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

## ADDR_OFFSET0 - Offset region 0 Register

#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)

## ADDR_OFFSET1 - Offset region 1 Register

#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)

## AES_KEY0_W0 - AES Key 0 Register

#define | BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
#define | BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
#define | BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)

## AES_KEY0_W1 - AES Key 1 Register

#define | BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
#define | BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
#define | BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)

## AES_KEY0_W2 - AES Key 2 Register

#define | BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
#define | BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
#define | BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)

## AES_KEY0_W3 - AES Key 3 Register

#define | BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
#define | BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
#define | BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)

## STATUS - Status Register

#define | BEE_STATUS_IRQ_VEC_MASK (0xFFU)
#define | BEE_STATUS_IRQ_VEC_SHIFT (0U)
#define | BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
#define | BEE_STATUS_BEE_IDLE_MASK (0x100U)
#define | BEE_STATUS_BEE_IDLE_SHIFT (8U)
#define | BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
#define | TRNG_STATUS_TF1BR0_MASK (0x1U)
#define | TRNG_STATUS_TF1BR0_SHIFT (0U)
#define | TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
#define | TRNG_STATUS_TF1BR1_MASK (0x2U)
#define | TRNG_STATUS_TF1BR1_SHIFT (1U)
#define | TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
#define | TRNG_STATUS_TF2BR0_MASK (0x4U)
#define | TRNG_STATUS_TF2BR0_SHIFT (2U)
#define | TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
#define | TRNG_STATUS_TF2BR1_MASK (0x8U)
#define | TRNG_STATUS_TF2BR1_SHIFT (3U)
#define | TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
#define | TRNG_STATUS_TF3BR0_MASK (0x10U)
#define | TRNG_STATUS_TF3BR0_SHIFT (4U)
#define | TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
#define | TRNG_STATUS_TF3BR1_MASK (0x20U)
#define | TRNG_STATUS_TF3BR1_SHIFT (5U)
#define | TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
#define | TRNG_STATUS_TF4BR0_MASK (0x40U)
#define | TRNG_STATUS_TF4BR0_SHIFT (6U)
#define | TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
#define | TRNG_STATUS_TF4BR1_MASK (0x80U)
#define | TRNG_STATUS_TF4BR1_SHIFT (7U)
#define | TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
#define | TRNG_STATUS_TF5BR0_MASK (0x100U)
#define | TRNG_STATUS_TF5BR0_SHIFT (8U)
#define | TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
#define | TRNG_STATUS_TF5BR1_MASK (0x200U)
#define | TRNG_STATUS_TF5BR1_SHIFT (9U)
#define | TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
#define | TRNG_STATUS_TF6PBR0_MASK (0x400U)
#define | TRNG_STATUS_TF6PBR0_SHIFT (10U)
#define | TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
#define | TRNG_STATUS_TF6PBR1_MASK (0x800U)
#define | TRNG_STATUS_TF6PBR1_SHIFT (11U)
#define | TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
#define | TRNG_STATUS_TFSB_MASK (0x1000U)
#define | TRNG_STATUS_TFSB_SHIFT (12U)
#define | TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
#define | TRNG_STATUS_TFLR_MASK (0x2000U)
#define | TRNG_STATUS_TFLR_SHIFT (13U)
#define | TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
#define | TRNG_STATUS_TFP_MASK (0x4000U)
#define | TRNG_STATUS_TFP_SHIFT (14U)
#define | TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
#define | TRNG_STATUS_TFMB_MASK (0x8000U)
#define | TRNG_STATUS_TFMB_SHIFT (15U)
#define | TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
#define | TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
#define | TRNG_STATUS_RETRY_CT_SHIFT (16U)
#define | TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)

## CTR_NONCE0_W0 - NONCE00 Register

#define | BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
#define | BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)

## CTR_NONCE0_W1 - NONCE01 Register

#define | BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
#define | BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)

## CTR_NONCE0_W2 - NONCE02 Register

#define | BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
#define | BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)

## CTR_NONCE0_W3 - NONCE03 Register

#define | BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
#define | BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)

## CTR_NONCE1_W0 - NONCE10 Register

#define | BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
#define | BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)

## CTR_NONCE1_W1 - NONCE11 Register

#define | BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
#define | BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)

## CTR_NONCE1_W2 - NONCE12 Register

#define | BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
#define | BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)

## CTR_NONCE1_W3 - NONCE13 Register

#define | BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
#define | BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)

## REGION1_TOP - Region1 Top Address Register

#define | BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
#define | BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
#define | BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)

## REGION1_BOT - Region1 Bottom Address Register

#define | BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
#define | BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
#define | BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ BEE_ADDR_OFFSET0_ADDR_OFFSET0

#define BEE_ADDR_OFFSET0_ADDR_OFFSET0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)

Definition at line 3271 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK

#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)

Definition at line 3274 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK

#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)

Definition at line 3272 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT

#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)

Definition at line 3273 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK

#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)

Definition at line 3269 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT

#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)

Definition at line 3270 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET1_ADDR_OFFSET1

#define BEE_ADDR_OFFSET1_ADDR_OFFSET1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)

Definition at line 3281 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK

#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)

Definition at line 3284 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK

#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)

Definition at line 3282 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT

#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)

Definition at line 3283 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK

#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)

Definition at line 3279 of file MIMXRT1062.h.

## ◆ BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT

#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)

Definition at line 3280 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W0_KEY0

#define BEE_AES_KEY0_W0_KEY0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)

KEY0 - AES 128 key from software

Definition at line 3293 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W0_KEY0_MASK

#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)

Definition at line 3289 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W0_KEY0_SHIFT

#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)

Definition at line 3290 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W1_KEY1

#define BEE_AES_KEY0_W1_KEY1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)

KEY1 - AES 128 key from software

Definition at line 3302 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W1_KEY1_MASK

#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)

Definition at line 3298 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W1_KEY1_SHIFT

#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)

Definition at line 3299 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W2_KEY2

#define BEE_AES_KEY0_W2_KEY2 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)

KEY2 - AES 128 key from software

Definition at line 3311 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W2_KEY2_MASK

#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)

Definition at line 3307 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W2_KEY2_SHIFT

#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)

Definition at line 3308 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W3_KEY3

#define BEE_AES_KEY0_W3_KEY3 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)

KEY3 - AES 128 key from software

Definition at line 3320 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W3_KEY3_MASK

#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)

Definition at line 3316 of file MIMXRT1062.h.

## ◆ BEE_AES_KEY0_W3_KEY3_SHIFT

#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)

Definition at line 3317 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W0_NONCE00

#define BEE_CTR_NONCE0_W0_NONCE00 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)

Definition at line 3337 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W0_NONCE00_MASK

#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)

Definition at line 3335 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W0_NONCE00_SHIFT

#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)

Definition at line 3336 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W1_NONCE01

#define BEE_CTR_NONCE0_W1_NONCE01 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)

Definition at line 3344 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W1_NONCE01_MASK

#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)

Definition at line 3342 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W1_NONCE01_SHIFT

#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)

Definition at line 3343 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W2_NONCE02

#define BEE_CTR_NONCE0_W2_NONCE02 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)

Definition at line 3351 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W2_NONCE02_MASK

#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)

Definition at line 3349 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W2_NONCE02_SHIFT

#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)

Definition at line 3350 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W3_NONCE03

#define BEE_CTR_NONCE0_W3_NONCE03 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)

Definition at line 3358 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W3_NONCE03_MASK

#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)

Definition at line 3356 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE0_W3_NONCE03_SHIFT

#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)

Definition at line 3357 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W0_NONCE10

#define BEE_CTR_NONCE1_W0_NONCE10 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)

Definition at line 3365 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W0_NONCE10_MASK

#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)

Definition at line 3363 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W0_NONCE10_SHIFT

#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)

Definition at line 3364 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W1_NONCE11

#define BEE_CTR_NONCE1_W1_NONCE11 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)

Definition at line 3372 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W1_NONCE11_MASK

#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)

Definition at line 3370 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W1_NONCE11_SHIFT

#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)

Definition at line 3371 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W2_NONCE12

#define BEE_CTR_NONCE1_W2_NONCE12 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)

Definition at line 3379 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W2_NONCE12_MASK

#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)

Definition at line 3377 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W2_NONCE12_SHIFT

#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)

Definition at line 3378 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W3_NONCE13

#define BEE_CTR_NONCE1_W3_NONCE13 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)

Definition at line 3386 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W3_NONCE13_MASK

#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)

Definition at line 3384 of file MIMXRT1062.h.

## ◆ BEE_CTR_NONCE1_W3_NONCE13_SHIFT

#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)

Definition at line 3385 of file MIMXRT1062.h.

## ◆ BEE_CTRL_AC_PROT_EN

#define BEE_CTRL_AC_PROT_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)

Definition at line 3193 of file MIMXRT1062.h.

## ◆ BEE_CTRL_AC_PROT_EN_LOCK

#define BEE_CTRL_AC_PROT_EN_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)

Definition at line 3243 of file MIMXRT1062.h.

## ◆ BEE_CTRL_AC_PROT_EN_LOCK_MASK

#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)

Definition at line 3241 of file MIMXRT1062.h.

## ◆ BEE_CTRL_AC_PROT_EN_LOCK_SHIFT

#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)

Definition at line 3242 of file MIMXRT1062.h.

## ◆ BEE_CTRL_AC_PROT_EN_MASK

#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)

Definition at line 3191 of file MIMXRT1062.h.

## ◆ BEE_CTRL_AC_PROT_EN_SHIFT

#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)

Definition at line 3192 of file MIMXRT1062.h.

## ◆ BEE_CTRL_BEE_ENABLE

#define BEE_CTRL_BEE_ENABLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)

BEE_ENABLE 0b0..Disable BEE 0b1..Enable BEE

Definition at line 3174 of file MIMXRT1062.h.

## ◆ BEE_CTRL_BEE_ENABLE_LOCK

#define BEE_CTRL_BEE_ENABLE_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)

Definition at line 3225 of file MIMXRT1062.h.

## ◆ BEE_CTRL_BEE_ENABLE_LOCK_MASK

#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)

Definition at line 3223 of file MIMXRT1062.h.

## ◆ BEE_CTRL_BEE_ENABLE_LOCK_SHIFT

#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)

Definition at line 3224 of file MIMXRT1062.h.

## ◆ BEE_CTRL_BEE_ENABLE_MASK

#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)

Definition at line 3168 of file MIMXRT1062.h.

## ◆ BEE_CTRL_BEE_ENABLE_SHIFT

#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)

Definition at line 3169 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R0

#define BEE_CTRL_CTRL_AES_MODE_R0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)

CTRL_AES_MODE_R0 0b0..ECB 0b1..CTR

Definition at line 3212 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R0_LOCK

#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)

Definition at line 3252 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK

#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)

Definition at line 3250 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT

#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)

Definition at line 3251 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R0_MASK

#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)

Definition at line 3206 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R0_SHIFT

#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)

Definition at line 3207 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R1

#define BEE_CTRL_CTRL_AES_MODE_R1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)

CTRL_AES_MODE_R1 0b0..ECB 0b1..CTR

Definition at line 3222 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R1_LOCK

#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)

Definition at line 3261 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK

#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)

Definition at line 3259 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT

#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)

Definition at line 3260 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R1_MASK

#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)

Definition at line 3216 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_AES_MODE_R1_SHIFT

#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)

Definition at line 3217 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_CLK_EN

#define BEE_CTRL_CTRL_CLK_EN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)

Definition at line 3177 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_CLK_EN_LOCK

#define BEE_CTRL_CTRL_CLK_EN_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)

Definition at line 3228 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_CLK_EN_LOCK_MASK

#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)

Definition at line 3226 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT

#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)

Definition at line 3227 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_CLK_EN_MASK

#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)

Definition at line 3175 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_CLK_EN_SHIFT

#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)

Definition at line 3176 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_SFTRST_N

#define BEE_CTRL_CTRL_SFTRST_N | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)

Definition at line 3180 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_SFTRST_N_LOCK

#define BEE_CTRL_CTRL_SFTRST_N_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)

Definition at line 3231 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK

#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)

Definition at line 3229 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT

#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)

Definition at line 3230 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_SFTRST_N_MASK

#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)

Definition at line 3178 of file MIMXRT1062.h.

## ◆ BEE_CTRL_CTRL_SFTRST_N_SHIFT

#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)

Definition at line 3179 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_REGION_SEL

#define BEE_CTRL_KEY_REGION_SEL | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)

KEY_REGION_SEL 0b0..Load AES key for region0 0b1..Load AES key for region1

Definition at line 3190 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_REGION_SEL_LOCK

#define BEE_CTRL_KEY_REGION_SEL_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)

Definition at line 3240 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_REGION_SEL_LOCK_MASK

#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)

Definition at line 3238 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT

#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)

Definition at line 3239 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_REGION_SEL_MASK

#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)

Definition at line 3184 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_REGION_SEL_SHIFT

#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)

Definition at line 3185 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_VALID

#define BEE_CTRL_KEY_VALID | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)

Definition at line 3183 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_VALID_LOCK

#define BEE_CTRL_KEY_VALID_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)

Definition at line 3237 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_VALID_LOCK_MASK

#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)

Definition at line 3235 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_VALID_LOCK_SHIFT

#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)

Definition at line 3236 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_VALID_MASK

#define BEE_CTRL_KEY_VALID_MASK (0x10U)

Definition at line 3181 of file MIMXRT1062.h.

## ◆ BEE_CTRL_KEY_VALID_SHIFT

#define BEE_CTRL_KEY_VALID_SHIFT (4U)

Definition at line 3182 of file MIMXRT1062.h.

## ◆ BEE_CTRL_LITTLE_ENDIAN

#define BEE_CTRL_LITTLE_ENDIAN | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)

LITTLE_ENDIAN 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15. 0b1..The input and output data of AES core is not swapped.

Definition at line 3202 of file MIMXRT1062.h.

## ◆ BEE_CTRL_LITTLE_ENDIAN_LOCK

#define BEE_CTRL_LITTLE_ENDIAN_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)

Definition at line 3246 of file MIMXRT1062.h.

## ◆ BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK

#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)

Definition at line 3244 of file MIMXRT1062.h.

## ◆ BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT

#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)

Definition at line 3245 of file MIMXRT1062.h.

## ◆ BEE_CTRL_LITTLE_ENDIAN_MASK

#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)

Definition at line 3194 of file MIMXRT1062.h.

## ◆ BEE_CTRL_LITTLE_ENDIAN_SHIFT

#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)

Definition at line 3195 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION0_KEY_LOCK

#define BEE_CTRL_REGION0_KEY_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)

Definition at line 3255 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION0_KEY_LOCK_MASK

#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)

Definition at line 3253 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION0_KEY_LOCK_SHIFT

#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)

Definition at line 3254 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION1_ADDR_LOCK

#define BEE_CTRL_REGION1_ADDR_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)

Definition at line 3234 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION1_ADDR_LOCK_MASK

#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)

Definition at line 3232 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION1_ADDR_LOCK_SHIFT

#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)

Definition at line 3233 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION1_KEY_LOCK

#define BEE_CTRL_REGION1_KEY_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)

Definition at line 3264 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION1_KEY_LOCK_MASK

#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)

Definition at line 3262 of file MIMXRT1062.h.

## ◆ BEE_CTRL_REGION1_KEY_LOCK_SHIFT

#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)

Definition at line 3263 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R0

#define BEE_CTRL_SECURITY_LEVEL_R0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)

Definition at line 3205 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R0_LOCK

#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)

Definition at line 3249 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK

#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)

Definition at line 3247 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT

#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)

Definition at line 3248 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R0_MASK

#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)

Definition at line 3203 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R0_SHIFT

#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)

Definition at line 3204 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R1

#define BEE_CTRL_SECURITY_LEVEL_R1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)

Definition at line 3215 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R1_LOCK

#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)

Definition at line 3258 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK

#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)

Definition at line 3256 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT

#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)

Definition at line 3257 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R1_MASK

#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)

Definition at line 3213 of file MIMXRT1062.h.

## ◆ BEE_CTRL_SECURITY_LEVEL_R1_SHIFT

#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)

Definition at line 3214 of file MIMXRT1062.h.

## ◆ BEE_REGION1_BOT_REGION1_BOT

#define BEE_REGION1_BOT_REGION1_BOT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)

REGION1_BOT - Address lower limit of region1

Definition at line 3404 of file MIMXRT1062.h.

## ◆ BEE_REGION1_BOT_REGION1_BOT_MASK

#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)

Definition at line 3400 of file MIMXRT1062.h.

## ◆ BEE_REGION1_BOT_REGION1_BOT_SHIFT

#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)

Definition at line 3401 of file MIMXRT1062.h.

## ◆ BEE_REGION1_TOP_REGION1_TOP

#define BEE_REGION1_TOP_REGION1_TOP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)

REGION1_TOP - Address upper limit of region1

Definition at line 3395 of file MIMXRT1062.h.

## ◆ BEE_REGION1_TOP_REGION1_TOP_MASK

#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)

Definition at line 3391 of file MIMXRT1062.h.

## ◆ BEE_REGION1_TOP_REGION1_TOP_SHIFT

#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)

Definition at line 3392 of file MIMXRT1062.h.

## ◆ BEE_STATUS_BEE_IDLE

#define BEE_STATUS_BEE_IDLE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)

Definition at line 3330 of file MIMXRT1062.h.

## ◆ BEE_STATUS_BEE_IDLE_MASK

#define BEE_STATUS_BEE_IDLE_MASK (0x100U)

Definition at line 3328 of file MIMXRT1062.h.

## ◆ BEE_STATUS_BEE_IDLE_SHIFT

#define BEE_STATUS_BEE_IDLE_SHIFT (8U)

Definition at line 3329 of file MIMXRT1062.h.

## ◆ BEE_STATUS_IRQ_VEC

#define BEE_STATUS_IRQ_VEC | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)

Definition at line 3327 of file MIMXRT1062.h.

## ◆ BEE_STATUS_IRQ_VEC_MASK

#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)

Definition at line 3325 of file MIMXRT1062.h.

## ◆ BEE_STATUS_IRQ_VEC_SHIFT

#define BEE_STATUS_IRQ_VEC_SHIFT (0U)

Definition at line 3326 of file MIMXRT1062.h.

## ◆ ENC_CTRL_CMPIE

#define ENC_CTRL_CMPIE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

CMPIE - Compare Interrupt Enable 0b0..Compare interrupt is disabled 0b1..Compare interrupt is enabled

Definition at line 16362 of file MIMXRT1062.h.

## ◆ ENC_CTRL_CMPIE_MASK

#define ENC_CTRL_CMPIE_MASK (0x1U)

Definition at line 16356 of file MIMXRT1062.h.

## ◆ ENC_CTRL_CMPIE_SHIFT

#define ENC_CTRL_CMPIE_SHIFT (0U)

Definition at line 16357 of file MIMXRT1062.h.

## ◆ ENC_CTRL_CMPIRQ

#define ENC_CTRL_CMPIRQ | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

CMPIRQ - Compare Interrupt Request 0b0..No match has occurred 0b1..COMP match has occurred

Definition at line 16369 of file MIMXRT1062.h.

## ◆ ENC_CTRL_CMPIRQ_MASK

#define ENC_CTRL_CMPIRQ_MASK (0x2U)

Definition at line 16363 of file MIMXRT1062.h.

## ◆ ENC_CTRL_CMPIRQ_SHIFT

#define ENC_CTRL_CMPIRQ_SHIFT (1U)

Definition at line 16364 of file MIMXRT1062.h.

## ◆ ENC_CTRL_DIE

#define ENC_CTRL_DIE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

DIE - Watchdog Timeout Interrupt Enable 0b0..Watchdog timer interrupt is disabled 0b1..Watchdog timer interrupt is enabled

Definition at line 16383 of file MIMXRT1062.h.

## ◆ ENC_CTRL_DIE_MASK

#define ENC_CTRL_DIE_MASK (0x8U)

Definition at line 16377 of file MIMXRT1062.h.

## ◆ ENC_CTRL_DIE_SHIFT

#define ENC_CTRL_DIE_SHIFT (3U)

Definition at line 16378 of file MIMXRT1062.h.

## ◆ ENC_CTRL_DIRQ

#define ENC_CTRL_DIRQ | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

DIRQ - Watchdog Timeout Interrupt Request 0b0..No interrupt has occurred 0b1..Watchdog timeout interrupt has occurred

Definition at line 16390 of file MIMXRT1062.h.

## ◆ ENC_CTRL_DIRQ_MASK

#define ENC_CTRL_DIRQ_MASK (0x10U)

Definition at line 16384 of file MIMXRT1062.h.

## ◆ ENC_CTRL_DIRQ_SHIFT

#define ENC_CTRL_DIRQ_SHIFT (4U)

Definition at line 16385 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIE

#define ENC_CTRL_HIE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

HIE - HOME Interrupt Enable 0b0..Disable HOME interrupts 0b1..Enable HOME interrupts

Definition at line 16463 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIE_MASK

#define ENC_CTRL_HIE_MASK (0x4000U)

Definition at line 16457 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIE_SHIFT

#define ENC_CTRL_HIE_SHIFT (14U)

Definition at line 16458 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIP

#define ENC_CTRL_HIP | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

HIP - Enable HOME to Initialize Position Counters UPOS and LPOS 0b0..No action 0b1..HOME signal initializes the position counter

Definition at line 16456 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIP_MASK

#define ENC_CTRL_HIP_MASK (0x2000U)

Definition at line 16450 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIP_SHIFT

#define ENC_CTRL_HIP_SHIFT (13U)

Definition at line 16451 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIRQ

#define ENC_CTRL_HIRQ | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)

HIRQ - HOME Signal Transition Interrupt Request 0b0..No interrupt 0b1..HOME signal transition interrupt request

Definition at line 16470 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIRQ_MASK

#define ENC_CTRL_HIRQ_MASK (0x8000U)

Definition at line 16464 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HIRQ_SHIFT

#define ENC_CTRL_HIRQ_SHIFT (15U)

Definition at line 16465 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HNE

#define ENC_CTRL_HNE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

HNE - Use Negative Edge of HOME Input 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS

Definition at line 16449 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HNE_MASK

#define ENC_CTRL_HNE_MASK (0x1000U)

Definition at line 16443 of file MIMXRT1062.h.

## ◆ ENC_CTRL_HNE_SHIFT

#define ENC_CTRL_HNE_SHIFT (12U)

Definition at line 16444 of file MIMXRT1062.h.

## ◆ ENC_CTRL_PH1

#define ENC_CTRL_PH1 | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

PH1 - Enable Signal Phase Count Mode 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up

Definition at line 16428 of file MIMXRT1062.h.

## ◆ ENC_CTRL_PH1_MASK

#define ENC_CTRL_PH1_MASK (0x200U)

Definition at line 16419 of file MIMXRT1062.h.

## ◆ ENC_CTRL_PH1_SHIFT

#define ENC_CTRL_PH1_SHIFT (9U)

Definition at line 16420 of file MIMXRT1062.h.

## ◆ ENC_CTRL_REV

#define ENC_CTRL_REV | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

REV - Enable Reverse Direction Counting 0b0..Count normally 0b1..Count in the reverse direction

Definition at line 16435 of file MIMXRT1062.h.

## ◆ ENC_CTRL_REV_MASK

#define ENC_CTRL_REV_MASK (0x400U)

Definition at line 16429 of file MIMXRT1062.h.

## ◆ ENC_CTRL_REV_SHIFT

#define ENC_CTRL_REV_SHIFT (10U)

Definition at line 16430 of file MIMXRT1062.h.

## ◆ ENC_CTRL_SWIP

#define ENC_CTRL_SWIP | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..Initialize position counter

Definition at line 16442 of file MIMXRT1062.h.

## ◆ ENC_CTRL_SWIP_MASK

#define ENC_CTRL_SWIP_MASK (0x800U)

Definition at line 16436 of file MIMXRT1062.h.

## ◆ ENC_CTRL_SWIP_SHIFT

#define ENC_CTRL_SWIP_SHIFT (11U)

Definition at line 16437 of file MIMXRT1062.h.

## ◆ ENC_CTRL_WDE

#define ENC_CTRL_WDE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

WDE - Watchdog Enable 0b0..Watchdog timer is disabled 0b1..Watchdog timer is enabled

Definition at line 16376 of file MIMXRT1062.h.

## ◆ ENC_CTRL_WDE_MASK

#define ENC_CTRL_WDE_MASK (0x4U)

Definition at line 16370 of file MIMXRT1062.h.

## ◆ ENC_CTRL_WDE_SHIFT

#define ENC_CTRL_WDE_SHIFT (2U)

Definition at line 16371 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIE

#define ENC_CTRL_XIE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

XIE - INDEX Pulse Interrupt Enable 0b0..INDEX pulse interrupt is disabled 0b1..INDEX pulse interrupt is enabled

Definition at line 16411 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIE_MASK

#define ENC_CTRL_XIE_MASK (0x80U)

Definition at line 16405 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIE_SHIFT

#define ENC_CTRL_XIE_SHIFT (7U)

Definition at line 16406 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIP

#define ENC_CTRL_XIP | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..INDEX pulse initializes the position counter

Definition at line 16404 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIP_MASK

#define ENC_CTRL_XIP_MASK (0x40U)

Definition at line 16398 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIP_SHIFT

#define ENC_CTRL_XIP_SHIFT (6U)

Definition at line 16399 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIRQ

#define ENC_CTRL_XIRQ | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

XIRQ - INDEX Pulse Interrupt Request 0b0..No interrupt has occurred 0b1..INDEX pulse interrupt has occurred

Definition at line 16418 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIRQ_MASK

#define ENC_CTRL_XIRQ_MASK (0x100U)

Definition at line 16412 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XIRQ_SHIFT

#define ENC_CTRL_XIRQ_SHIFT (8U)

Definition at line 16413 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XNE

#define ENC_CTRL_XNE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

XNE - Use Negative Edge of INDEX Pulse 0b0..Use positive transition edge of INDEX pulse 0b1..Use negative transition edge of INDEX pulse

Definition at line 16397 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XNE_MASK

#define ENC_CTRL_XNE_MASK (0x20U)

Definition at line 16391 of file MIMXRT1062.h.

## ◆ ENC_CTRL_XNE_SHIFT

#define ENC_CTRL_XNE_SHIFT (5U)

Definition at line 16392 of file MIMXRT1062.h.

## ◆ EWM_CTRL_ASSIN

#define EWM_CTRL_ASSIN | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

ASSIN - EWM_in's Assertion State Select.

Definition at line 18463 of file MIMXRT1062.h.

## ◆ EWM_CTRL_ASSIN_MASK

#define EWM_CTRL_ASSIN_MASK (0x2U)

Definition at line 18459 of file MIMXRT1062.h.

## ◆ EWM_CTRL_ASSIN_SHIFT

#define EWM_CTRL_ASSIN_SHIFT (1U)

Definition at line 18460 of file MIMXRT1062.h.

## ◆ EWM_CTRL_EWMEN

#define EWM_CTRL_EWMEN | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

EWMEN - EWM enable.

Definition at line 18458 of file MIMXRT1062.h.

## ◆ EWM_CTRL_EWMEN_MASK

#define EWM_CTRL_EWMEN_MASK (0x1U)

Definition at line 18454 of file MIMXRT1062.h.

## ◆ EWM_CTRL_EWMEN_SHIFT

#define EWM_CTRL_EWMEN_SHIFT (0U)

Definition at line 18455 of file MIMXRT1062.h.

## ◆ EWM_CTRL_INEN

#define EWM_CTRL_INEN | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

INEN - Input Enable.

Definition at line 18468 of file MIMXRT1062.h.

## ◆ EWM_CTRL_INEN_MASK

#define EWM_CTRL_INEN_MASK (0x4U)

Definition at line 18464 of file MIMXRT1062.h.

## ◆ EWM_CTRL_INEN_SHIFT

#define EWM_CTRL_INEN_SHIFT (2U)

Definition at line 18465 of file MIMXRT1062.h.

## ◆ EWM_CTRL_INTEN

#define EWM_CTRL_INTEN | ( |  | x | ) | (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)

INTEN - Interrupt Enable.

Definition at line 18473 of file MIMXRT1062.h.

## ◆ EWM_CTRL_INTEN_MASK

#define EWM_CTRL_INTEN_MASK (0x8U)

Definition at line 18469 of file MIMXRT1062.h.

## ◆ EWM_CTRL_INTEN_SHIFT

#define EWM_CTRL_INTEN_SHIFT (3U)

Definition at line 18470 of file MIMXRT1062.h.

## ◆ PWM_CTRL_COMPMODE

#define PWM_CTRL_COMPMODE | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)

COMPMODE - Compare Mode 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.

Definition at line 33306 of file MIMXRT1062.h.

## ◆ PWM_CTRL_COMPMODE_MASK

#define PWM_CTRL_COMPMODE_MASK (0x80U)

Definition at line 33294 of file MIMXRT1062.h.

## ◆ PWM_CTRL_COMPMODE_SHIFT

#define PWM_CTRL_COMPMODE_SHIFT (7U)

Definition at line 33295 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DBLEN

#define PWM_CTRL_DBLEN | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

DBLEN - Double Switching Enable 0b0..Double switching disabled. 0b1..Double switching enabled.

Definition at line 33258 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DBLEN_MASK

#define PWM_CTRL_DBLEN_MASK (0x1U)

Definition at line 33252 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DBLEN_SHIFT

#define PWM_CTRL_DBLEN_SHIFT (0U)

Definition at line 33253 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DBLX

#define PWM_CTRL_DBLX | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

DBLX - PWMX Double Switching Enable 0b0..PWMX double pulse disabled. 0b1..PWMX double pulse enabled.

Definition at line 33265 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DBLX_MASK

#define PWM_CTRL_DBLX_MASK (0x2U)

Definition at line 33259 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DBLX_SHIFT

#define PWM_CTRL_DBLX_SHIFT (1U)

Definition at line 33260 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DT

#define PWM_CTRL_DT | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

DT - Deadtime

Definition at line 33311 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DT_MASK

#define PWM_CTRL_DT_MASK (0x300U)

Definition at line 33307 of file MIMXRT1062.h.

## ◆ PWM_CTRL_DT_SHIFT

#define PWM_CTRL_DT_SHIFT (8U)

Definition at line 33308 of file MIMXRT1062.h.

## ◆ PWM_CTRL_FULL

#define PWM_CTRL_FULL | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

FULL - Full Cycle Reload 0b0..Full-cycle reloads disabled. 0b1..Full-cycle reloads enabled.

Definition at line 33318 of file MIMXRT1062.h.

## ◆ PWM_CTRL_FULL_MASK

#define PWM_CTRL_FULL_MASK (0x400U)

Definition at line 33312 of file MIMXRT1062.h.

## ◆ PWM_CTRL_FULL_SHIFT

#define PWM_CTRL_FULL_SHIFT (10U)

Definition at line 33313 of file MIMXRT1062.h.

## ◆ PWM_CTRL_HALF

#define PWM_CTRL_HALF | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

HALF - Half Cycle Reload 0b0..Half-cycle reloads disabled. 0b1..Half-cycle reloads enabled.

Definition at line 33325 of file MIMXRT1062.h.

## ◆ PWM_CTRL_HALF_MASK

#define PWM_CTRL_HALF_MASK (0x800U)

Definition at line 33319 of file MIMXRT1062.h.

## ◆ PWM_CTRL_HALF_SHIFT

#define PWM_CTRL_HALF_SHIFT (11U)

Definition at line 33320 of file MIMXRT1062.h.

## ◆ PWM_CTRL_LDFQ

#define PWM_CTRL_LDFQ | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

LDFQ - Load Frequency 0b0000..Every PWM opportunity 0b0001..Every 2 PWM opportunities 0b0010..Every 3 PWM opportunities 0b0011..Every 4 PWM opportunities 0b0100..Every 5 PWM opportunities 0b0101..Every 6 PWM opportunities 0b0110..Every 7 PWM opportunities 0b0111..Every 8 PWM opportunities 0b1000..Every 9 PWM opportunities 0b1001..Every 10 PWM opportunities 0b1010..Every 11 PWM opportunities 0b1011..Every 12 PWM opportunities 0b1100..Every 13 PWM opportunities 0b1101..Every 14 PWM opportunities 0b1110..Every 15 PWM opportunities 0b1111..Every 16 PWM opportunities

Definition at line 33346 of file MIMXRT1062.h.

## ◆ PWM_CTRL_LDFQ_MASK

#define PWM_CTRL_LDFQ_MASK (0xF000U)

Definition at line 33326 of file MIMXRT1062.h.

## ◆ PWM_CTRL_LDFQ_SHIFT

#define PWM_CTRL_LDFQ_SHIFT (12U)

Definition at line 33327 of file MIMXRT1062.h.

## ◆ PWM_CTRL_LDMOD

#define PWM_CTRL_LDMOD | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

LDMOD - Load Mode Select 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].

Definition at line 33273 of file MIMXRT1062.h.

## ◆ PWM_CTRL_LDMOD_MASK

#define PWM_CTRL_LDMOD_MASK (0x4U)

Definition at line 33266 of file MIMXRT1062.h.

## ◆ PWM_CTRL_LDMOD_SHIFT

#define PWM_CTRL_LDMOD_SHIFT (2U)

Definition at line 33267 of file MIMXRT1062.h.

## ◆ PWM_CTRL_PRSC

#define PWM_CTRL_PRSC | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

PRSC - Prescaler 0b000..PWM clock frequency = fclk 0b001..PWM clock frequency = fclk/2 0b010..PWM clock frequency = fclk/4 0b011..PWM clock frequency = fclk/8 0b100..PWM clock frequency = fclk/16 0b101..PWM clock frequency = fclk/32 0b110..PWM clock frequency = fclk/64 0b111..PWM clock frequency = fclk/128

Definition at line 33293 of file MIMXRT1062.h.

## ◆ PWM_CTRL_PRSC_MASK

#define PWM_CTRL_PRSC_MASK (0x70U)

Definition at line 33281 of file MIMXRT1062.h.

## ◆ PWM_CTRL_PRSC_SHIFT

#define PWM_CTRL_PRSC_SHIFT (4U)

Definition at line 33282 of file MIMXRT1062.h.

## ◆ PWM_CTRL_SPLIT

#define PWM_CTRL_SPLIT | ( |  | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)

SPLIT - Split the DBLPWM signal to PWMA and PWMB 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. 0b1..DBLPWM is split to PWMA and PWMB.

Definition at line 33280 of file MIMXRT1062.h.

## ◆ PWM_CTRL_SPLIT_MASK

#define PWM_CTRL_SPLIT_MASK (0x8U)

Definition at line 33274 of file MIMXRT1062.h.

## ◆ PWM_CTRL_SPLIT_SHIFT

#define PWM_CTRL_SPLIT_SHIFT (3U)

Definition at line 33275 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_RETRY_CT

#define TRNG_STATUS_RETRY_CT | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)

Definition at line 40660 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_RETRY_CT_MASK

#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)

Definition at line 40658 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_RETRY_CT_SHIFT

#define TRNG_STATUS_RETRY_CT_SHIFT (16U)

Definition at line 40659 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF1BR0

#define TRNG_STATUS_TF1BR0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)

Definition at line 40612 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF1BR0_MASK

#define TRNG_STATUS_TF1BR0_MASK (0x1U)

Definition at line 40610 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF1BR0_SHIFT

#define TRNG_STATUS_TF1BR0_SHIFT (0U)

Definition at line 40611 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF1BR1

#define TRNG_STATUS_TF1BR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)

Definition at line 40615 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF1BR1_MASK

#define TRNG_STATUS_TF1BR1_MASK (0x2U)

Definition at line 40613 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF1BR1_SHIFT

#define TRNG_STATUS_TF1BR1_SHIFT (1U)

Definition at line 40614 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF2BR0

#define TRNG_STATUS_TF2BR0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)

Definition at line 40618 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF2BR0_MASK

#define TRNG_STATUS_TF2BR0_MASK (0x4U)

Definition at line 40616 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF2BR0_SHIFT

#define TRNG_STATUS_TF2BR0_SHIFT (2U)

Definition at line 40617 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF2BR1

#define TRNG_STATUS_TF2BR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)

Definition at line 40621 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF2BR1_MASK

#define TRNG_STATUS_TF2BR1_MASK (0x8U)

Definition at line 40619 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF2BR1_SHIFT

#define TRNG_STATUS_TF2BR1_SHIFT (3U)

Definition at line 40620 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF3BR0

#define TRNG_STATUS_TF3BR0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)

Definition at line 40624 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF3BR0_MASK

#define TRNG_STATUS_TF3BR0_MASK (0x10U)

Definition at line 40622 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF3BR0_SHIFT

#define TRNG_STATUS_TF3BR0_SHIFT (4U)

Definition at line 40623 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF3BR1

#define TRNG_STATUS_TF3BR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)

Definition at line 40627 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF3BR1_MASK

#define TRNG_STATUS_TF3BR1_MASK (0x20U)

Definition at line 40625 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF3BR1_SHIFT

#define TRNG_STATUS_TF3BR1_SHIFT (5U)

Definition at line 40626 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF4BR0

#define TRNG_STATUS_TF4BR0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)

Definition at line 40630 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF4BR0_MASK

#define TRNG_STATUS_TF4BR0_MASK (0x40U)

Definition at line 40628 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF4BR0_SHIFT

#define TRNG_STATUS_TF4BR0_SHIFT (6U)

Definition at line 40629 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF4BR1

#define TRNG_STATUS_TF4BR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)

Definition at line 40633 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF4BR1_MASK

#define TRNG_STATUS_TF4BR1_MASK (0x80U)

Definition at line 40631 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF4BR1_SHIFT

#define TRNG_STATUS_TF4BR1_SHIFT (7U)

Definition at line 40632 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF5BR0

#define TRNG_STATUS_TF5BR0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)

Definition at line 40636 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF5BR0_MASK

#define TRNG_STATUS_TF5BR0_MASK (0x100U)

Definition at line 40634 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF5BR0_SHIFT

#define TRNG_STATUS_TF5BR0_SHIFT (8U)

Definition at line 40635 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF5BR1

#define TRNG_STATUS_TF5BR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)

Definition at line 40639 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF5BR1_MASK

#define TRNG_STATUS_TF5BR1_MASK (0x200U)

Definition at line 40637 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF5BR1_SHIFT

#define TRNG_STATUS_TF5BR1_SHIFT (9U)

Definition at line 40638 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF6PBR0

#define TRNG_STATUS_TF6PBR0 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)

Definition at line 40642 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF6PBR0_MASK

#define TRNG_STATUS_TF6PBR0_MASK (0x400U)

Definition at line 40640 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF6PBR0_SHIFT

#define TRNG_STATUS_TF6PBR0_SHIFT (10U)

Definition at line 40641 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF6PBR1

#define TRNG_STATUS_TF6PBR1 | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)

Definition at line 40645 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF6PBR1_MASK

#define TRNG_STATUS_TF6PBR1_MASK (0x800U)

Definition at line 40643 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TF6PBR1_SHIFT

#define TRNG_STATUS_TF6PBR1_SHIFT (11U)

Definition at line 40644 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFLR

#define TRNG_STATUS_TFLR | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)

Definition at line 40651 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFLR_MASK

#define TRNG_STATUS_TFLR_MASK (0x2000U)

Definition at line 40649 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFLR_SHIFT

#define TRNG_STATUS_TFLR_SHIFT (13U)

Definition at line 40650 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFMB

#define TRNG_STATUS_TFMB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)

Definition at line 40657 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFMB_MASK

#define TRNG_STATUS_TFMB_MASK (0x8000U)

Definition at line 40655 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFMB_SHIFT

#define TRNG_STATUS_TFMB_SHIFT (15U)

Definition at line 40656 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFP

#define TRNG_STATUS_TFP | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)

Definition at line 40654 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFP_MASK

#define TRNG_STATUS_TFP_MASK (0x4000U)

Definition at line 40652 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFP_SHIFT

#define TRNG_STATUS_TFP_SHIFT (14U)

Definition at line 40653 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFSB

#define TRNG_STATUS_TFSB | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)

Definition at line 40648 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFSB_MASK

#define TRNG_STATUS_TFSB_MASK (0x1000U)

Definition at line 40646 of file MIMXRT1062.h.

## ◆ TRNG_STATUS_TFSB_SHIFT

#define TRNG_STATUS_TFSB_SHIFT (12U)

Definition at line 40647 of file MIMXRT1062.h.