Callisto4Bootloader: CMSIS/core_armv8mml.h Source File

Callisto4Bootloader

core_armv8mml.h
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1 /**************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_ARMV8MML_H_GENERIC
32 #define __CORE_ARMV8MML_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
63 #include "cmsis_version.h"
64
65 /* CMSIS Armv8MML definitions */
66 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
69 __ARMv8MML_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (81U)
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88 #if defined(__ARM_FEATURE_DSP)
89 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
90 #define __DSP_USED 1U
91 #else
92 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
93 #define __DSP_USED 0U
94 #endif
95 #else
96 #define __DSP_USED 0U
97 #endif
98
99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
100 #if defined __ARM_FP
101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
102 #define __FPU_USED 1U
103 #else
104 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
105 #define __FPU_USED 0U
106 #endif
107 #else
108 #define __FPU_USED 0U
109 #endif
110
111 #if defined(__ARM_FEATURE_DSP)
112 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
113 #define __DSP_USED 1U
114 #else
115 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
116 #define __DSP_USED 0U
117 #endif
118 #else
119 #define __DSP_USED 0U
120 #endif
121
122 #elif defined ( __GNUC__ )
123 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
125 #define __FPU_USED 1U
126 #else
127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #define __FPU_USED 0U
129 #endif
130 #else
131 #define __FPU_USED 0U
132 #endif
133
134 #if defined(__ARM_FEATURE_DSP)
135 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
136 #define __DSP_USED 1U
137 #else
138 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
139 #define __DSP_USED 0U
140 #endif
141 #else
142 #define __DSP_USED 0U
143 #endif
144
145 #elif defined ( __ICCARM__ )
146 #if defined __ARMVFP__
147 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
148 #define __FPU_USED 1U
149 #else
150 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
151 #define __FPU_USED 0U
152 #endif
153 #else
154 #define __FPU_USED 0U
155 #endif
156
157 #if defined(__ARM_FEATURE_DSP)
158 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
159 #define __DSP_USED 1U
160 #else
161 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
162 #define __DSP_USED 0U
163 #endif
164 #else
165 #define __DSP_USED 0U
166 #endif
167
168 #elif defined ( __TI_ARM__ )
169 #if defined __TI_VFP_SUPPORT__
170 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
171 #define __FPU_USED 1U
172 #else
173 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
174 #define __FPU_USED 0U
175 #endif
176 #else
177 #define __FPU_USED 0U
178 #endif
179
180 #elif defined ( __TASKING__ )
181 #if defined __FPU_VFP__
182 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
183 #define __FPU_USED 1U
184 #else
185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
186 #define __FPU_USED 0U
187 #endif
188 #else
189 #define __FPU_USED 0U
190 #endif
191
192 #elif defined ( __CSMC__ )
193 #if ( __CSMC__ & 0x400U)
194 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
195 #define __FPU_USED 1U
196 #else
197 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
198 #define __FPU_USED 0U
199 #endif
200 #else
201 #define __FPU_USED 0U
202 #endif
203
204 #endif
205
206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
207
208
209 #ifdef __cplusplus
210 }
211 #endif
212
213 #endif /* __CORE_ARMV8MML_H_GENERIC */
214
215 #ifndef __CMSIS_GENERIC
216
217 #ifndef __CORE_ARMV8MML_H_DEPENDANT
218 #define __CORE_ARMV8MML_H_DEPENDANT
219
220 #ifdef __cplusplus
221 extern "C" {
222 #endif
223
224 /* check device defines and use defaults */
225 #if defined __CHECK_DEVICE_DEFINES
226 #ifndef __ARMv8MML_REV
227 #define __ARMv8MML_REV 0x0000U
228 #warning "__ARMv8MML_REV not defined in device header file; using default!"
229 #endif
230
231 #ifndef __FPU_PRESENT
232 #define __FPU_PRESENT 0U
233 #warning "__FPU_PRESENT not defined in device header file; using default!"
234 #endif
235
236 #ifndef __MPU_PRESENT
237 #define __MPU_PRESENT 0U
238 #warning "__MPU_PRESENT not defined in device header file; using default!"
239 #endif
240
241 #ifndef __SAUREGION_PRESENT
242 #define __SAUREGION_PRESENT 0U
243 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
244 #endif
245
246 #ifndef __DSP_PRESENT
247 #define __DSP_PRESENT 0U
248 #warning "__DSP_PRESENT not defined in device header file; using default!"
249 #endif
250
251 #ifndef __NVIC_PRIO_BITS
252 #define __NVIC_PRIO_BITS 3U
253 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
254 #endif
255
256 #ifndef __Vendor_SysTickConfig
257 #define __Vendor_SysTickConfig 0U
258 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
259 #endif
260 #endif
261
262 /* IO definitions (access restrictions to peripheral registers) */
270 #ifdef __cplusplus
271 #define __I volatile
272 #else
273 #define __I volatile const
274 #endif
275 #define __O volatile
276 #define __IO volatile
278 /* following defines should be used for structure members */
279 #define __IM volatile const
280 #define __OM volatile
281 #define __IOM volatile
283
287 /*******************************************************************************
288 * Register Abstraction
289 Core Register contain:
290 - Core Register
291 - Core NVIC Register
292 - Core SCB Register
293 - Core SysTick Register
294 - Core Debug Register
295 - Core MPU Register
296 - Core SAU Register
297 - Core FPU Register
298 ******************************************************************************/
299
314 typedef union
315 {
316 struct
317 {
318 uint32_t _reserved0:16;
319 uint32_t GE:4;
320 uint32_t _reserved1:7;
321 uint32_t Q:1;
322 uint32_t V:1;
323 uint32_t C:1;
324 uint32_t Z:1;
325 uint32_t N:1;
326 } b;
327 uint32_t w;
328 } APSR_Type;
329
330 /* APSR Register Definitions */
331 #define APSR_N_Pos 31U
332 #define APSR_N_Msk (1UL << APSR_N_Pos)
334 #define APSR_Z_Pos 30U
335 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
337 #define APSR_C_Pos 29U
338 #define APSR_C_Msk (1UL << APSR_C_Pos)
340 #define APSR_V_Pos 28U
341 #define APSR_V_Msk (1UL << APSR_V_Pos)
343 #define APSR_Q_Pos 27U
344 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
346 #define APSR_GE_Pos 16U
347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
353 typedef union
354 {
355 struct
356 {
357 uint32_t ISR:9;
358 uint32_t _reserved0:23;
359 } b;
360 uint32_t w;
361 } IPSR_Type;
362
363 /* IPSR Register Definitions */
364 #define IPSR_ISR_Pos 0U
365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
371 typedef union
372 {
373 struct
374 {
375 uint32_t ISR:9;
376 uint32_t _reserved0:7;
377 uint32_t GE:4;
378 uint32_t _reserved1:4;
379 uint32_t T:1;
380 uint32_t IT:2;
381 uint32_t Q:1;
382 uint32_t V:1;
383 uint32_t C:1;
384 uint32_t Z:1;
385 uint32_t N:1;
386 } b;
387 uint32_t w;
388 } xPSR_Type;
389
390 /* xPSR Register Definitions */
391 #define xPSR_N_Pos 31U
392 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
394 #define xPSR_Z_Pos 30U
395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
397 #define xPSR_C_Pos 29U
398 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
400 #define xPSR_V_Pos 28U
401 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
403 #define xPSR_Q_Pos 27U
404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
406 #define xPSR_IT_Pos 25U
407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
409 #define xPSR_T_Pos 24U
410 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
412 #define xPSR_GE_Pos 16U
413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
415 #define xPSR_ISR_Pos 0U
416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
422 typedef union
423 {
424 struct
425 {
426 uint32_t nPRIV:1;
427 uint32_t SPSEL:1;
428 uint32_t FPCA:1;
429 uint32_t SFPA:1;
430 uint32_t _reserved1:28;
431 } b;
432 uint32_t w;
433 } CONTROL_Type;
434
435 /* CONTROL Register Definitions */
436 #define CONTROL_SFPA_Pos 3U
437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
439 #define CONTROL_FPCA_Pos 2U
440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
442 #define CONTROL_SPSEL_Pos 1U
443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
445 #define CONTROL_nPRIV_Pos 0U
446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
448
461 typedef struct
462 {
463 __IOM uint32_t ISER[16U];
464 uint32_t RESERVED0[16U];
465 __IOM uint32_t ICER[16U];
466 uint32_t RSERVED1[16U];
467 __IOM uint32_t ISPR[16U];
468 uint32_t RESERVED2[16U];
469 __IOM uint32_t ICPR[16U];
470 uint32_t RESERVED3[16U];
471 __IOM uint32_t IABR[16U];
472 uint32_t RESERVED4[16U];
473 __IOM uint32_t ITNS[16U];
474 uint32_t RESERVED5[16U];
475 __IOM uint8_t IPR[496U];
476 uint32_t RESERVED6[580U];
477 __OM uint32_t STIR;
478 } NVIC_Type;
479
480 /* Software Triggered Interrupt Register Definitions */
481 #define NVIC_STIR_INTID_Pos 0U
482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
484
497 typedef struct
498 {
499 __IM uint32_t CPUID;
500 __IOM uint32_t ICSR;
501 __IOM uint32_t VTOR;
502 __IOM uint32_t AIRCR;
503 __IOM uint32_t SCR;
504 __IOM uint32_t CCR;
505 __IOM uint8_t SHPR[12U];
506 __IOM uint32_t SHCSR;
507 __IOM uint32_t CFSR;
508 __IOM uint32_t HFSR;
509 __IOM uint32_t DFSR;
510 __IOM uint32_t MMFAR;
511 __IOM uint32_t BFAR;
512 __IOM uint32_t AFSR;
513 __IM uint32_t ID_PFR[2U];
514 __IM uint32_t ID_DFR;
515 __IM uint32_t ID_ADR;
516 __IM uint32_t ID_MMFR[4U];
517 __IM uint32_t ID_ISAR[6U];
518 __IM uint32_t CLIDR;
519 __IM uint32_t CTR;
520 __IM uint32_t CCSIDR;
521 __IOM uint32_t CSSELR;
522 __IOM uint32_t CPACR;
523 __IOM uint32_t NSACR;
524 uint32_t RESERVED3[92U];
525 __OM uint32_t STIR;
526 uint32_t RESERVED4[15U];
527 __IM uint32_t MVFR0;
528 __IM uint32_t MVFR1;
529 __IM uint32_t MVFR2;
530 uint32_t RESERVED5[1U];
531 __OM uint32_t ICIALLU;
532 uint32_t RESERVED6[1U];
533 __OM uint32_t ICIMVAU;
534 __OM uint32_t DCIMVAC;
535 __OM uint32_t DCISW;
536 __OM uint32_t DCCMVAU;
537 __OM uint32_t DCCMVAC;
538 __OM uint32_t DCCSW;
539 __OM uint32_t DCCIMVAC;
540 __OM uint32_t DCCISW;
541 } SCB_Type;
542
543 /* SCB CPUID Register Definitions */
544 #define SCB_CPUID_IMPLEMENTER_Pos 24U
545 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
547 #define SCB_CPUID_VARIANT_Pos 20U
548 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
550 #define SCB_CPUID_ARCHITECTURE_Pos 16U
551 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
553 #define SCB_CPUID_PARTNO_Pos 4U
554 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
556 #define SCB_CPUID_REVISION_Pos 0U
557 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
559 /* SCB Interrupt Control State Register Definitions */
560 #define SCB_ICSR_PENDNMISET_Pos 31U
561 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
563 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
564 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
566 #define SCB_ICSR_PENDNMICLR_Pos 30U
567 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
569 #define SCB_ICSR_PENDSVSET_Pos 28U
570 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
572 #define SCB_ICSR_PENDSVCLR_Pos 27U
573 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
575 #define SCB_ICSR_PENDSTSET_Pos 26U
576 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
578 #define SCB_ICSR_PENDSTCLR_Pos 25U
579 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
581 #define SCB_ICSR_STTNS_Pos 24U
582 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
584 #define SCB_ICSR_ISRPREEMPT_Pos 23U
585 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
587 #define SCB_ICSR_ISRPENDING_Pos 22U
588 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
590 #define SCB_ICSR_VECTPENDING_Pos 12U
591 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
593 #define SCB_ICSR_RETTOBASE_Pos 11U
594 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
596 #define SCB_ICSR_VECTACTIVE_Pos 0U
597 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
599 /* SCB Vector Table Offset Register Definitions */
600 #define SCB_VTOR_TBLOFF_Pos 7U
601 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
603 /* SCB Application Interrupt and Reset Control Register Definitions */
604 #define SCB_AIRCR_VECTKEY_Pos 16U
605 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
607 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
608 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
610 #define SCB_AIRCR_ENDIANESS_Pos 15U
611 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
613 #define SCB_AIRCR_PRIS_Pos 14U
614 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
616 #define SCB_AIRCR_BFHFNMINS_Pos 13U
617 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
619 #define SCB_AIRCR_PRIGROUP_Pos 8U
620 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
622 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
623 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
625 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
626 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
628 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
629 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
631 /* SCB System Control Register Definitions */
632 #define SCB_SCR_SEVONPEND_Pos 4U
633 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
635 #define SCB_SCR_SLEEPDEEPS_Pos 3U
636 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
638 #define SCB_SCR_SLEEPDEEP_Pos 2U
639 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
641 #define SCB_SCR_SLEEPONEXIT_Pos 1U
642 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
644 /* SCB Configuration Control Register Definitions */
645 #define SCB_CCR_BP_Pos 18U
646 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
648 #define SCB_CCR_IC_Pos 17U
649 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
651 #define SCB_CCR_DC_Pos 16U
652 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
654 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
655 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
657 #define SCB_CCR_BFHFNMIGN_Pos 8U
658 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
660 #define SCB_CCR_DIV_0_TRP_Pos 4U
661 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
663 #define SCB_CCR_UNALIGN_TRP_Pos 3U
664 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
666 #define SCB_CCR_USERSETMPEND_Pos 1U
667 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
669 /* SCB System Handler Control and State Register Definitions */
670 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
671 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
673 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
674 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
676 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U
677 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
679 #define SCB_SHCSR_USGFAULTENA_Pos 18U
680 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
682 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
683 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
685 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
686 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
688 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
689 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
691 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
692 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
694 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
695 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
697 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
698 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
700 #define SCB_SHCSR_SYSTICKACT_Pos 11U
701 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
703 #define SCB_SHCSR_PENDSVACT_Pos 10U
704 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
706 #define SCB_SHCSR_MONITORACT_Pos 8U
707 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
709 #define SCB_SHCSR_SVCALLACT_Pos 7U
710 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
712 #define SCB_SHCSR_NMIACT_Pos 5U
713 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
715 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U
716 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
718 #define SCB_SHCSR_USGFAULTACT_Pos 3U
719 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
721 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
722 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
724 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
725 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
727 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
728 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
730 /* SCB Configurable Fault Status Register Definitions */
731 #define SCB_CFSR_USGFAULTSR_Pos 16U
732 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
734 #define SCB_CFSR_BUSFAULTSR_Pos 8U
735 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
737 #define SCB_CFSR_MEMFAULTSR_Pos 0U
738 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
740 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
741 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
742 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
744 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
745 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
747 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
748 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
750 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
751 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
753 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
754 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
756 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
757 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
759 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
760 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
761 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
763 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
764 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
766 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
767 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
769 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
770 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
772 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
773 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
775 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
776 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
778 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
779 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
781 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
782 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
783 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
785 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
786 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
788 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
789 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
791 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
792 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
794 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
795 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
797 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
798 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
800 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
801 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
803 /* SCB Hard Fault Status Register Definitions */
804 #define SCB_HFSR_DEBUGEVT_Pos 31U
805 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
807 #define SCB_HFSR_FORCED_Pos 30U
808 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
810 #define SCB_HFSR_VECTTBL_Pos 1U
811 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
813 /* SCB Debug Fault Status Register Definitions */
814 #define SCB_DFSR_EXTERNAL_Pos 4U
815 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
817 #define SCB_DFSR_VCATCH_Pos 3U
818 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
820 #define SCB_DFSR_DWTTRAP_Pos 2U
821 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
823 #define SCB_DFSR_BKPT_Pos 1U
824 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
826 #define SCB_DFSR_HALTED_Pos 0U
827 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
829 /* SCB Non-Secure Access Control Register Definitions */
830 #define SCB_NSACR_CP11_Pos 11U
831 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
833 #define SCB_NSACR_CP10_Pos 10U
834 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
836 #define SCB_NSACR_CPn_Pos 0U
837 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
839 /* SCB Cache Level ID Register Definitions */
840 #define SCB_CLIDR_LOUU_Pos 27U
841 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
843 #define SCB_CLIDR_LOC_Pos 24U
844 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
846 /* SCB Cache Type Register Definitions */
847 #define SCB_CTR_FORMAT_Pos 29U
848 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
850 #define SCB_CTR_CWG_Pos 24U
851 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
853 #define SCB_CTR_ERG_Pos 20U
854 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
856 #define SCB_CTR_DMINLINE_Pos 16U
857 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
859 #define SCB_CTR_IMINLINE_Pos 0U
860 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
862 /* SCB Cache Size ID Register Definitions */
863 #define SCB_CCSIDR_WT_Pos 31U
864 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
866 #define SCB_CCSIDR_WB_Pos 30U
867 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
869 #define SCB_CCSIDR_RA_Pos 29U
870 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
872 #define SCB_CCSIDR_WA_Pos 28U
873 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
875 #define SCB_CCSIDR_NUMSETS_Pos 13U
876 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
878 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
879 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
881 #define SCB_CCSIDR_LINESIZE_Pos 0U
882 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
884 /* SCB Cache Size Selection Register Definitions */
885 #define SCB_CSSELR_LEVEL_Pos 1U
886 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
888 #define SCB_CSSELR_IND_Pos 0U
889 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
891 /* SCB Software Triggered Interrupt Register Definitions */
892 #define SCB_STIR_INTID_Pos 0U
893 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
895 /* SCB D-Cache Invalidate by Set-way Register Definitions */
896 #define SCB_DCISW_WAY_Pos 30U
897 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
899 #define SCB_DCISW_SET_Pos 5U
900 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
902 /* SCB D-Cache Clean by Set-way Register Definitions */
903 #define SCB_DCCSW_WAY_Pos 30U
904 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
906 #define SCB_DCCSW_SET_Pos 5U
907 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
909 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
910 #define SCB_DCCISW_WAY_Pos 30U
911 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
913 #define SCB_DCCISW_SET_Pos 5U
914 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
916
929 typedef struct
930 {
931 uint32_t RESERVED0[1U];
932 __IM uint32_t ICTR;
933 __IOM uint32_t ACTLR;
934 __IOM uint32_t CPPWR;
935 } SCnSCB_Type;
936
937 /* Interrupt Controller Type Register Definitions */
938 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
939 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
941
954 typedef struct
955 {
956 __IOM uint32_t CTRL;
957 __IOM uint32_t LOAD;
958 __IOM uint32_t VAL;
959 __IM uint32_t CALIB;
960 } SysTick_Type;
961
962 /* SysTick Control / Status Register Definitions */
963 #define SysTick_CTRL_COUNTFLAG_Pos 16U
964 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
966 #define SysTick_CTRL_CLKSOURCE_Pos 2U
967 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
969 #define SysTick_CTRL_TICKINT_Pos 1U
970 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
972 #define SysTick_CTRL_ENABLE_Pos 0U
973 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
975 /* SysTick Reload Register Definitions */
976 #define SysTick_LOAD_RELOAD_Pos 0U
977 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
979 /* SysTick Current Register Definitions */
980 #define SysTick_VAL_CURRENT_Pos 0U
981 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
983 /* SysTick Calibration Register Definitions */
984 #define SysTick_CALIB_NOREF_Pos 31U
985 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
987 #define SysTick_CALIB_SKEW_Pos 30U
988 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
990 #define SysTick_CALIB_TENMS_Pos 0U
991 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
993
1006 typedef struct
1007 {
1008 __OM union
1009 {
1010 __OM uint8_t u8;
1011 __OM uint16_t u16;
1012 __OM uint32_t u32;
1013 } PORT [32U];
1014 uint32_t RESERVED0[864U];
1015 __IOM uint32_t TER;
1016 uint32_t RESERVED1[15U];
1017 __IOM uint32_t TPR;
1018 uint32_t RESERVED2[15U];
1019 __IOM uint32_t TCR;
1020 uint32_t RESERVED3[32U];
1021 uint32_t RESERVED4[43U];
1022 __OM uint32_t LAR;
1023 __IM uint32_t LSR;
1024 uint32_t RESERVED5[1U];
1025 __IM uint32_t DEVARCH;
1026 uint32_t RESERVED6[4U];
1027 __IM uint32_t PID4;
1028 __IM uint32_t PID5;
1029 __IM uint32_t PID6;
1030 __IM uint32_t PID7;
1031 __IM uint32_t PID0;
1032 __IM uint32_t PID1;
1033 __IM uint32_t PID2;
1034 __IM uint32_t PID3;
1035 __IM uint32_t CID0;
1036 __IM uint32_t CID1;
1037 __IM uint32_t CID2;
1038 __IM uint32_t CID3;
1039 } ITM_Type;
1040
1041 /* ITM Stimulus Port Register Definitions */
1042 #define ITM_STIM_DISABLED_Pos 1U
1043 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1045 #define ITM_STIM_FIFOREADY_Pos 0U
1046 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1048 /* ITM Trace Privilege Register Definitions */
1049 #define ITM_TPR_PRIVMASK_Pos 0U
1050 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1052 /* ITM Trace Control Register Definitions */
1053 #define ITM_TCR_BUSY_Pos 23U
1054 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1056 #define ITM_TCR_TRACEBUSID_Pos 16U
1057 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1059 #define ITM_TCR_GTSFREQ_Pos 10U
1060 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1062 #define ITM_TCR_TSPRESCALE_Pos 8U
1063 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1065 #define ITM_TCR_STALLENA_Pos 5U
1066 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1068 #define ITM_TCR_SWOENA_Pos 4U
1069 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1071 #define ITM_TCR_DWTENA_Pos 3U
1072 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1074 #define ITM_TCR_SYNCENA_Pos 2U
1075 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1077 #define ITM_TCR_TSENA_Pos 1U
1078 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1080 #define ITM_TCR_ITMENA_Pos 0U
1081 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1083 /* ITM Lock Status Register Definitions */
1084 #define ITM_LSR_ByteAcc_Pos 2U
1085 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1087 #define ITM_LSR_Access_Pos 1U
1088 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1090 #define ITM_LSR_Present_Pos 0U
1091 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1093 /* end of group CMSIS_ITM */
1094
1095
1106 typedef struct
1107 {
1108 __IOM uint32_t CTRL;
1109 __IOM uint32_t CYCCNT;
1110 __IOM uint32_t CPICNT;
1111 __IOM uint32_t EXCCNT;
1112 __IOM uint32_t SLEEPCNT;
1113 __IOM uint32_t LSUCNT;
1114 __IOM uint32_t FOLDCNT;
1115 __IM uint32_t PCSR;
1116 __IOM uint32_t COMP0;
1117 uint32_t RESERVED1[1U];
1118 __IOM uint32_t FUNCTION0;
1119 uint32_t RESERVED2[1U];
1120 __IOM uint32_t COMP1;
1121 uint32_t RESERVED3[1U];
1122 __IOM uint32_t FUNCTION1;
1123 uint32_t RESERVED4[1U];
1124 __IOM uint32_t COMP2;
1125 uint32_t RESERVED5[1U];
1126 __IOM uint32_t FUNCTION2;
1127 uint32_t RESERVED6[1U];
1128 __IOM uint32_t COMP3;
1129 uint32_t RESERVED7[1U];
1130 __IOM uint32_t FUNCTION3;
1131 uint32_t RESERVED8[1U];
1132 __IOM uint32_t COMP4;
1133 uint32_t RESERVED9[1U];
1134 __IOM uint32_t FUNCTION4;
1135 uint32_t RESERVED10[1U];
1136 __IOM uint32_t COMP5;
1137 uint32_t RESERVED11[1U];
1138 __IOM uint32_t FUNCTION5;
1139 uint32_t RESERVED12[1U];
1140 __IOM uint32_t COMP6;
1141 uint32_t RESERVED13[1U];
1142 __IOM uint32_t FUNCTION6;
1143 uint32_t RESERVED14[1U];
1144 __IOM uint32_t COMP7;
1145 uint32_t RESERVED15[1U];
1146 __IOM uint32_t FUNCTION7;
1147 uint32_t RESERVED16[1U];
1148 __IOM uint32_t COMP8;
1149 uint32_t RESERVED17[1U];
1150 __IOM uint32_t FUNCTION8;
1151 uint32_t RESERVED18[1U];
1152 __IOM uint32_t COMP9;
1153 uint32_t RESERVED19[1U];
1154 __IOM uint32_t FUNCTION9;
1155 uint32_t RESERVED20[1U];
1156 __IOM uint32_t COMP10;
1157 uint32_t RESERVED21[1U];
1158 __IOM uint32_t FUNCTION10;
1159 uint32_t RESERVED22[1U];
1160 __IOM uint32_t COMP11;
1161 uint32_t RESERVED23[1U];
1162 __IOM uint32_t FUNCTION11;
1163 uint32_t RESERVED24[1U];
1164 __IOM uint32_t COMP12;
1165 uint32_t RESERVED25[1U];
1166 __IOM uint32_t FUNCTION12;
1167 uint32_t RESERVED26[1U];
1168 __IOM uint32_t COMP13;
1169 uint32_t RESERVED27[1U];
1170 __IOM uint32_t FUNCTION13;
1171 uint32_t RESERVED28[1U];
1172 __IOM uint32_t COMP14;
1173 uint32_t RESERVED29[1U];
1174 __IOM uint32_t FUNCTION14;
1175 uint32_t RESERVED30[1U];
1176 __IOM uint32_t COMP15;
1177 uint32_t RESERVED31[1U];
1178 __IOM uint32_t FUNCTION15;
1179 uint32_t RESERVED32[934U];
1180 __IM uint32_t LSR;
1181 uint32_t RESERVED33[1U];
1182 __IM uint32_t DEVARCH;
1183 } DWT_Type;
1184
1185 /* DWT Control Register Definitions */
1186 #define DWT_CTRL_NUMCOMP_Pos 28U
1187 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1189 #define DWT_CTRL_NOTRCPKT_Pos 27U
1190 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1192 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1193 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1195 #define DWT_CTRL_NOCYCCNT_Pos 25U
1196 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1198 #define DWT_CTRL_NOPRFCNT_Pos 24U
1199 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1201 #define DWT_CTRL_CYCDISS_Pos 23U
1202 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1204 #define DWT_CTRL_CYCEVTENA_Pos 22U
1205 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1207 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1208 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1210 #define DWT_CTRL_LSUEVTENA_Pos 20U
1211 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1213 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1214 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1216 #define DWT_CTRL_EXCEVTENA_Pos 18U
1217 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1219 #define DWT_CTRL_CPIEVTENA_Pos 17U
1220 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1222 #define DWT_CTRL_EXCTRCENA_Pos 16U
1223 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1225 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1226 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1228 #define DWT_CTRL_SYNCTAP_Pos 10U
1229 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1231 #define DWT_CTRL_CYCTAP_Pos 9U
1232 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1234 #define DWT_CTRL_POSTINIT_Pos 5U
1235 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1237 #define DWT_CTRL_POSTPRESET_Pos 1U
1238 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1240 #define DWT_CTRL_CYCCNTENA_Pos 0U
1241 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1243 /* DWT CPI Count Register Definitions */
1244 #define DWT_CPICNT_CPICNT_Pos 0U
1245 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1247 /* DWT Exception Overhead Count Register Definitions */
1248 #define DWT_EXCCNT_EXCCNT_Pos 0U
1249 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1251 /* DWT Sleep Count Register Definitions */
1252 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1253 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1255 /* DWT LSU Count Register Definitions */
1256 #define DWT_LSUCNT_LSUCNT_Pos 0U
1257 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1259 /* DWT Folded-instruction Count Register Definitions */
1260 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1261 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1263 /* DWT Comparator Function Register Definitions */
1264 #define DWT_FUNCTION_ID_Pos 27U
1265 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1267 #define DWT_FUNCTION_MATCHED_Pos 24U
1268 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1270 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1271 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1273 #define DWT_FUNCTION_ACTION_Pos 4U
1274 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1276 #define DWT_FUNCTION_MATCH_Pos 0U
1277 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
1279 /* end of group CMSIS_DWT */
1280
1281
1292 typedef struct
1293 {
1294 __IM uint32_t SSPSR;
1295 __IOM uint32_t CSPSR;
1296 uint32_t RESERVED0[2U];
1297 __IOM uint32_t ACPR;
1298 uint32_t RESERVED1[55U];
1299 __IOM uint32_t SPPR;
1300 uint32_t RESERVED2[131U];
1301 __IM uint32_t FFSR;
1302 __IOM uint32_t FFCR;
1303 __IOM uint32_t PSCR;
1304 uint32_t RESERVED3[809U];
1305 __OM uint32_t LAR;
1306 __IM uint32_t LSR;
1307 uint32_t RESERVED4[4U];
1308 __IM uint32_t TYPE;
1309 __IM uint32_t DEVTYPE;
1310 } TPI_Type;
1311
1312 /* TPI Asynchronous Clock Prescaler Register Definitions */
1313 #define TPI_ACPR_SWOSCALER_Pos 0U
1314 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
1316 /* TPI Selected Pin Protocol Register Definitions */
1317 #define TPI_SPPR_TXMODE_Pos 0U
1318 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1320 /* TPI Formatter and Flush Status Register Definitions */
1321 #define TPI_FFSR_FtNonStop_Pos 3U
1322 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1324 #define TPI_FFSR_TCPresent_Pos 2U
1325 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1327 #define TPI_FFSR_FtStopped_Pos 1U
1328 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1330 #define TPI_FFSR_FlInProg_Pos 0U
1331 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1333 /* TPI Formatter and Flush Control Register Definitions */
1334 #define TPI_FFCR_TrigIn_Pos 8U
1335 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1337 #define TPI_FFCR_FOnMan_Pos 6U
1338 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1340 #define TPI_FFCR_EnFCont_Pos 1U
1341 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1343 /* TPI Periodic Synchronization Control Register Definitions */
1344 #define TPI_PSCR_PSCount_Pos 0U
1345 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
1347 /* TPI Software Lock Status Register Definitions */
1348 #define TPI_LSR_nTT_Pos 1U
1349 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
1351 #define TPI_LSR_SLK_Pos 1U
1352 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
1354 #define TPI_LSR_SLI_Pos 0U
1355 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
1357 /* TPI DEVID Register Definitions */
1358 #define TPI_DEVID_NRZVALID_Pos 11U
1359 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1361 #define TPI_DEVID_MANCVALID_Pos 10U
1362 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1364 #define TPI_DEVID_PTINVALID_Pos 9U
1365 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1367 #define TPI_DEVID_FIFOSZ_Pos 6U
1368 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1370 /* TPI DEVTYPE Register Definitions */
1371 #define TPI_DEVTYPE_SubType_Pos 4U
1372 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1374 #define TPI_DEVTYPE_MajorType_Pos 0U
1375 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1377 /* end of group CMSIS_TPI */
1378
1379
1380 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1381
1391 typedef struct
1392 {
1393 __IM uint32_t TYPE;
1394 __IOM uint32_t CTRL;
1395 __IOM uint32_t RNR;
1396 __IOM uint32_t RBAR;
1397 __IOM uint32_t RLAR;
1398 __IOM uint32_t RBAR_A1;
1399 __IOM uint32_t RLAR_A1;
1400 __IOM uint32_t RBAR_A2;
1401 __IOM uint32_t RLAR_A2;
1402 __IOM uint32_t RBAR_A3;
1403 __IOM uint32_t RLAR_A3;
1404 uint32_t RESERVED0[1];
1405 union {
1406 __IOM uint32_t MAIR[2];
1407 struct {
1408 __IOM uint32_t MAIR0;
1409 __IOM uint32_t MAIR1;
1410 };
1411 };
1412 } MPU_Type;
1413
1414 #define MPU_TYPE_RALIASES 4U
1415
1416 /* MPU Type Register Definitions */
1417 #define MPU_TYPE_IREGION_Pos 16U
1418 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1420 #define MPU_TYPE_DREGION_Pos 8U
1421 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1423 #define MPU_TYPE_SEPARATE_Pos 0U
1424 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1426 /* MPU Control Register Definitions */
1427 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1428 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1430 #define MPU_CTRL_HFNMIENA_Pos 1U
1431 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1433 #define MPU_CTRL_ENABLE_Pos 0U
1434 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1436 /* MPU Region Number Register Definitions */
1437 #define MPU_RNR_REGION_Pos 0U
1438 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1440 /* MPU Region Base Address Register Definitions */
1441 #define MPU_RBAR_BASE_Pos 5U
1442 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
1444 #define MPU_RBAR_SH_Pos 3U
1445 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1447 #define MPU_RBAR_AP_Pos 1U
1448 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1450 #define MPU_RBAR_XN_Pos 0U
1451 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1453 /* MPU Region Limit Address Register Definitions */
1454 #define MPU_RLAR_LIMIT_Pos 5U
1455 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1457 #define MPU_RLAR_AttrIndx_Pos 1U
1458 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1460 #define MPU_RLAR_EN_Pos 0U
1461 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1463 /* MPU Memory Attribute Indirection Register 0 Definitions */
1464 #define MPU_MAIR0_Attr3_Pos 24U
1465 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1467 #define MPU_MAIR0_Attr2_Pos 16U
1468 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1470 #define MPU_MAIR0_Attr1_Pos 8U
1471 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1473 #define MPU_MAIR0_Attr0_Pos 0U
1474 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1476 /* MPU Memory Attribute Indirection Register 1 Definitions */
1477 #define MPU_MAIR1_Attr7_Pos 24U
1478 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1480 #define MPU_MAIR1_Attr6_Pos 16U
1481 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1483 #define MPU_MAIR1_Attr5_Pos 8U
1484 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1486 #define MPU_MAIR1_Attr4_Pos 0U
1487 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1489
1490 #endif
1491
1492
1493 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1494
1504 typedef struct
1505 {
1506 __IOM uint32_t CTRL;
1507 __IM uint32_t TYPE;
1508 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1509 __IOM uint32_t RNR;
1510 __IOM uint32_t RBAR;
1511 __IOM uint32_t RLAR;
1512 #else
1513 uint32_t RESERVED0[3];
1514 #endif
1515 __IOM uint32_t SFSR;
1516 __IOM uint32_t SFAR;
1517 } SAU_Type;
1518
1519 /* SAU Control Register Definitions */
1520 #define SAU_CTRL_ALLNS_Pos 1U
1521 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1523 #define SAU_CTRL_ENABLE_Pos 0U
1524 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1526 /* SAU Type Register Definitions */
1527 #define SAU_TYPE_SREGION_Pos 0U
1528 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1530 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1531 /* SAU Region Number Register Definitions */
1532 #define SAU_RNR_REGION_Pos 0U
1533 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1535 /* SAU Region Base Address Register Definitions */
1536 #define SAU_RBAR_BADDR_Pos 5U
1537 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1539 /* SAU Region Limit Address Register Definitions */
1540 #define SAU_RLAR_LADDR_Pos 5U
1541 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1543 #define SAU_RLAR_NSC_Pos 1U
1544 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1546 #define SAU_RLAR_ENABLE_Pos 0U
1547 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1549 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1550
1551 /* Secure Fault Status Register Definitions */
1552 #define SAU_SFSR_LSERR_Pos 7U
1553 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1555 #define SAU_SFSR_SFARVALID_Pos 6U
1556 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1558 #define SAU_SFSR_LSPERR_Pos 5U
1559 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1561 #define SAU_SFSR_INVTRAN_Pos 4U
1562 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1564 #define SAU_SFSR_AUVIOL_Pos 3U
1565 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1567 #define SAU_SFSR_INVER_Pos 2U
1568 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1570 #define SAU_SFSR_INVIS_Pos 1U
1571 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1573 #define SAU_SFSR_INVEP_Pos 0U
1574 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1576
1577 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1578
1579
1590 typedef struct
1591 {
1592 uint32_t RESERVED0[1U];
1593 __IOM uint32_t FPCCR;
1594 __IOM uint32_t FPCAR;
1595 __IOM uint32_t FPDSCR;
1596 __IM uint32_t MVFR0;
1597 __IM uint32_t MVFR1;
1598 } FPU_Type;
1599
1600 /* Floating-Point Context Control Register Definitions */
1601 #define FPU_FPCCR_ASPEN_Pos 31U
1602 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1604 #define FPU_FPCCR_LSPEN_Pos 30U
1605 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1607 #define FPU_FPCCR_LSPENS_Pos 29U
1608 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1610 #define FPU_FPCCR_CLRONRET_Pos 28U
1611 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1613 #define FPU_FPCCR_CLRONRETS_Pos 27U
1614 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1616 #define FPU_FPCCR_TS_Pos 26U
1617 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1619 #define FPU_FPCCR_UFRDY_Pos 10U
1620 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1622 #define FPU_FPCCR_SPLIMVIOL_Pos 9U
1623 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1625 #define FPU_FPCCR_MONRDY_Pos 8U
1626 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1628 #define FPU_FPCCR_SFRDY_Pos 7U
1629 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1631 #define FPU_FPCCR_BFRDY_Pos 6U
1632 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1634 #define FPU_FPCCR_MMRDY_Pos 5U
1635 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1637 #define FPU_FPCCR_HFRDY_Pos 4U
1638 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1640 #define FPU_FPCCR_THREAD_Pos 3U
1641 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1643 #define FPU_FPCCR_S_Pos 2U
1644 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1646 #define FPU_FPCCR_USER_Pos 1U
1647 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1649 #define FPU_FPCCR_LSPACT_Pos 0U
1650 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1652 /* Floating-Point Context Address Register Definitions */
1653 #define FPU_FPCAR_ADDRESS_Pos 3U
1654 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1656 /* Floating-Point Default Status Control Register Definitions */
1657 #define FPU_FPDSCR_AHP_Pos 26U
1658 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1660 #define FPU_FPDSCR_DN_Pos 25U
1661 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1663 #define FPU_FPDSCR_FZ_Pos 24U
1664 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1666 #define FPU_FPDSCR_RMode_Pos 22U
1667 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1669 /* Media and FP Feature Register 0 Definitions */
1670 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1671 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1673 #define FPU_MVFR0_Short_vectors_Pos 24U
1674 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1676 #define FPU_MVFR0_Square_root_Pos 20U
1677 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1679 #define FPU_MVFR0_Divide_Pos 16U
1680 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1682 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1683 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1685 #define FPU_MVFR0_Double_precision_Pos 8U
1686 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1688 #define FPU_MVFR0_Single_precision_Pos 4U
1689 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1691 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1692 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1694 /* Media and FP Feature Register 1 Definitions */
1695 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1696 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1698 #define FPU_MVFR1_FP_HPFP_Pos 24U
1699 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1701 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1702 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1704 #define FPU_MVFR1_FtZ_mode_Pos 0U
1705 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1707
1720 typedef struct
1721 {
1722 __IOM uint32_t DHCSR;
1723 __OM uint32_t DCRSR;
1724 __IOM uint32_t DCRDR;
1725 __IOM uint32_t DEMCR;
1726 uint32_t RESERVED4[1U];
1727 __IOM uint32_t DAUTHCTRL;
1728 __IOM uint32_t DSCSR;
1729 } CoreDebug_Type;
1730
1731 /* Debug Halting Control and Status Register Definitions */
1732 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1733 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1735 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1736 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1738 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1739 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1741 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1742 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1744 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1745 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1747 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1748 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1750 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1751 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1753 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1754 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1756 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1757 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1759 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1760 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1762 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1763 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1765 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1766 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1768 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1769 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1771 /* Debug Core Register Selector Register Definitions */
1772 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1773 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1775 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1776 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1778 /* Debug Exception and Monitor Control Register Definitions */
1779 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1780 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1782 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1783 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1785 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1786 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1788 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1789 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1791 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1792 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1794 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1795 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1797 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1798 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1800 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1801 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1803 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1804 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1806 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1807 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1809 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1810 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1812 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1813 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1815 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1816 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1818 /* Debug Authentication Control Register Definitions */
1819 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1820 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1822 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1823 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1825 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1826 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1828 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1829 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1831 /* Debug Security Control and Status Register Definitions */
1832 #define CoreDebug_DSCSR_CDS_Pos 16U
1833 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1835 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1836 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1838 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1839 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1841
1857 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1858
1865 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1866
1877 /* Memory mapping of Core Hardware */
1878 #define SCS_BASE (0xE000E000UL)
1879 #define ITM_BASE (0xE0000000UL)
1880 #define DWT_BASE (0xE0001000UL)
1881 #define TPI_BASE (0xE0040000UL)
1882 #define CoreDebug_BASE (0xE000EDF0UL)
1883 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1884 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1885 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1887 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1888 #define SCB ((SCB_Type *) SCB_BASE )
1889 #define SysTick ((SysTick_Type *) SysTick_BASE )
1890 #define NVIC ((NVIC_Type *) NVIC_BASE )
1891 #define ITM ((ITM_Type *) ITM_BASE )
1892 #define DWT ((DWT_Type *) DWT_BASE )
1893 #define TPI ((TPI_Type *) TPI_BASE )
1894 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
1896 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1897 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1898 #define MPU ((MPU_Type *) MPU_BASE )
1899 #endif
1900
1901 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1902 #define SAU_BASE (SCS_BASE + 0x0DD0UL)
1903 #define SAU ((SAU_Type *) SAU_BASE )
1904 #endif
1905
1906 #define FPU_BASE (SCS_BASE + 0x0F30UL)
1907 #define FPU ((FPU_Type *) FPU_BASE )
1909 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1910 #define SCS_BASE_NS (0xE002E000UL)
1911 #define CoreDebug_BASE_NS (0xE002EDF0UL)
1912 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
1913 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
1914 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
1916 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
1917 #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
1918 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
1919 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
1920 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
1922 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1923 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
1924 #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
1925 #endif
1926
1927 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
1928 #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
1930 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1931
1935 /*******************************************************************************
1936 * Hardware Abstraction Layer
1937 Core Function Interface contains:
1938 - Core NVIC Functions
1939 - Core SysTick Functions
1940 - Core Debug Functions
1941 - Core Register Access Functions
1942 ******************************************************************************/
1949 /* ########################## NVIC functions #################################### */
1957 #ifdef CMSIS_NVIC_VIRTUAL
1958 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1959 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1960 #endif
1961 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1962 #else
1963 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1964 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1965 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1966 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1967 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1968 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1969 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1970 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1971 #define NVIC_GetActive __NVIC_GetActive
1972 #define NVIC_SetPriority __NVIC_SetPriority
1973 #define NVIC_GetPriority __NVIC_GetPriority
1974 #define NVIC_SystemReset __NVIC_SystemReset
1975 #endif /* CMSIS_NVIC_VIRTUAL */
1976
1977 #ifdef CMSIS_VECTAB_VIRTUAL
1978 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1979 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1980 #endif
1981 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1982 #else
1983 #define NVIC_SetVector __NVIC_SetVector
1984 #define NVIC_GetVector __NVIC_GetVector
1985 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1986
1987 #define NVIC_USER_IRQ_OFFSET 16
1988
1989
1990 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1991
1992 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1993 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1994
1995 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1996 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1997 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1998 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1999 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2000 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2001 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2002 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2003
2004 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2005 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2006 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2007 #else
2008 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2009 #endif
2010
2011
2021 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2022 {
2023 uint32_t reg_value;
2024 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2025
2026 reg_value = SCB->AIRCR; /* read old register configuration */
2027 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2028 reg_value = (reg_value |
2029 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2030 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2031 SCB->AIRCR = reg_value;
2032 }
2033
2034
2040 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2041 {
2042 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2043 }
2044
2045
2052 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2053 {
2054 if ((int32_t)(IRQn) >= 0)
2055 {
2056 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2057 }
2058 }
2059
2060
2069 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2070 {
2071 if ((int32_t)(IRQn) >= 0)
2072 {
2073 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2074 }
2075 else
2076 {
2077 return(0U);
2078 }
2079 }
2080
2081
2088 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2089 {
2090 if ((int32_t)(IRQn) >= 0)
2091 {
2092 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2093 __DSB();
2094 __ISB();
2095 }
2096 }
2097
2098
2107 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2108 {
2109 if ((int32_t)(IRQn) >= 0)
2110 {
2111 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2112 }
2113 else
2114 {
2115 return(0U);
2116 }
2117 }
2118
2119
2126 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2127 {
2128 if ((int32_t)(IRQn) >= 0)
2129 {
2130 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2131 }
2132 }
2133
2134
2141 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2142 {
2143 if ((int32_t)(IRQn) >= 0)
2144 {
2145 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2146 }
2147 }
2148
2149
2158 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2159 {
2160 if ((int32_t)(IRQn) >= 0)
2161 {
2162 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2163 }
2164 else
2165 {
2166 return(0U);
2167 }
2168 }
2169
2170
2171 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2172
2180 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2181 {
2182 if ((int32_t)(IRQn) >= 0)
2183 {
2184 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2185 }
2186 else
2187 {
2188 return(0U);
2189 }
2190 }
2191
2192
2201 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2202 {
2203 if ((int32_t)(IRQn) >= 0)
2204 {
2205 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2206 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2207 }
2208 else
2209 {
2210 return(0U);
2211 }
2212 }
2213
2214
2223 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2224 {
2225 if ((int32_t)(IRQn) >= 0)
2226 {
2227 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2228 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2229 }
2230 else
2231 {
2232 return(0U);
2233 }
2234 }
2235 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2236
2237
2247 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2248 {
2249 if ((int32_t)(IRQn) >= 0)
2250 {
2251 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2252 }
2253 else
2254 {
2255 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2256 }
2257 }
2258
2259
2269 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2270 {
2271
2272 if ((int32_t)(IRQn) >= 0)
2273 {
2274 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2275 }
2276 else
2277 {
2278 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2279 }
2280 }
2281
2282
2294 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2295 {
2296 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2297 uint32_t PreemptPriorityBits;
2298 uint32_t SubPriorityBits;
2299
2300 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2301 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2302
2303 return (
2304 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2305 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2306 );
2307 }
2308
2309
2321 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2322 {
2323 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2324 uint32_t PreemptPriorityBits;
2325 uint32_t SubPriorityBits;
2326
2327 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2328 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2329
2330 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2331 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2332 }
2333
2334
2344 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2345 {
2346 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2347 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2348 }
2349
2350
2359 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2360 {
2361 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2362 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2363 }
2364
2365
2370 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2371 {
2372 __DSB(); /* Ensure all outstanding memory accesses included
2373 buffered write are completed before reset */
2374 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2375 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2376 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2377 __DSB(); /* Ensure completion of memory access */
2378
2379 for(;;) /* wait until reset */
2380 {
2381 __NOP();
2382 }
2383 }
2384
2385 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2386
2395 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2396 {
2397 uint32_t reg_value;
2398 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2399
2400 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2401 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2402 reg_value = (reg_value |
2403 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2404 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2405 SCB_NS->AIRCR = reg_value;
2406 }
2407
2408
2414 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2415 {
2416 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2417 }
2418
2419
2426 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2427 {
2428 if ((int32_t)(IRQn) >= 0)
2429 {
2430 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2431 }
2432 }
2433
2434
2443 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2444 {
2445 if ((int32_t)(IRQn) >= 0)
2446 {
2447 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2448 }
2449 else
2450 {
2451 return(0U);
2452 }
2453 }
2454
2455
2462 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2463 {
2464 if ((int32_t)(IRQn) >= 0)
2465 {
2466 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2467 }
2468 }
2469
2470
2479 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2480 {
2481 if ((int32_t)(IRQn) >= 0)
2482 {
2483 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2484 }
2485 else
2486 {
2487 return(0U);
2488 }
2489 }
2490
2491
2498 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2499 {
2500 if ((int32_t)(IRQn) >= 0)
2501 {
2502 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2503 }
2504 }
2505
2506
2513 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2514 {
2515 if ((int32_t)(IRQn) >= 0)
2516 {
2517 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2518 }
2519 }
2520
2521
2530 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2531 {
2532 if ((int32_t)(IRQn) >= 0)
2533 {
2534 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2535 }
2536 else
2537 {
2538 return(0U);
2539 }
2540 }
2541
2542
2552 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2553 {
2554 if ((int32_t)(IRQn) >= 0)
2555 {
2556 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2557 }
2558 else
2559 {
2560 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2561 }
2562 }
2563
2564
2573 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2574 {
2575
2576 if ((int32_t)(IRQn) >= 0)
2577 {
2578 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2579 }
2580 else
2581 {
2582 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2583 }
2584 }
2585 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2586
2589 /* ########################## MPU functions #################################### */
2590
2591 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2592
2593 #include "mpu_armv8.h"
2594
2595 #endif
2596
2597 /* ########################## FPU functions #################################### */
2613 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2614 {
2615 uint32_t mvfr0;
2616
2617 mvfr0 = FPU->MVFR0;
2618 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2619 {
2620 return 2U; /* Double + Single precision FPU */
2621 }
2622 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2623 {
2624 return 1U; /* Single precision FPU */
2625 }
2626 else
2627 {
2628 return 0U; /* No FPU */
2629 }
2630 }
2631
2632
2637 /* ########################## SAU functions #################################### */
2645 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2646
2651 __STATIC_INLINE void TZ_SAU_Enable(void)
2652 {
2653 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2654 }
2655
2656
2657
2662 __STATIC_INLINE void TZ_SAU_Disable(void)
2663 {
2664 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2665 }
2666
2667 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2668
2674 /* ################################## SysTick function ############################################ */
2682 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2683
2695 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2696 {
2697 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2698 {
2699 return (1UL); /* Reload value impossible */
2700 }
2701
2702 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2703 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2704 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2705 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2706 SysTick_CTRL_TICKINT_Msk |
2707 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2708 return (0UL); /* Function successful */
2709 }
2710
2711 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2712
2724 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2725 {
2726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2727 {
2728 return (1UL); /* Reload value impossible */
2729 }
2730
2731 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2732 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2733 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2734 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2735 SysTick_CTRL_TICKINT_Msk |
2736 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2737 return (0UL); /* Function successful */
2738 }
2739 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2740
2741 #endif
2742
2747 /* ##################################### Debug In/Output function ########################################### */
2755 extern volatile int32_t ITM_RxBuffer;
2756 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2767 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2768 {
2769 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2770 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2771 {
2772 while (ITM->PORT[0U].u32 == 0UL)
2773 {
2774 __NOP();
2775 }
2776 ITM->PORT[0U].u8 = (uint8_t)ch;
2777 }
2778 return (ch);
2779 }
2780
2781
2788 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2789 {
2790 int32_t ch = -1; /* no character available */
2791
2792 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2793 {
2794 ch = ITM_RxBuffer;
2795 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2796 }
2797
2798 return (ch);
2799 }
2800
2801
2808 __STATIC_INLINE int32_t ITM_CheckChar (void)
2809 {
2810
2811 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2812 {
2813 return (0); /* no character available */
2814 }
2815 else
2816 {
2817 return (1); /* character available */
2818 }
2819 }
2820
2826 #ifdef __cplusplus
2827 }
2828 #endif
2829
2830 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
2831
2832 #endif /* __CMSIS_GENERIC */
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1034
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: MIMXRT1062.h:268
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv81mml.h:2173
NVIC
#define NVIC
Definition: core_armv8mml.h:1888
__IOM
#define __IOM
Definition: core_armv8mml.h:280
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:2259
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv81mml.h:2154
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:2380
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:2274
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:2746
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:371
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_armv8mml.h:2753
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866
FPU
#define FPU
Definition: core_armv8mml.h:1905
SysTick_IRQn
Definition: MIMXRT1062.h:87
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv8mml.h:1969
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:2185
mpu_armv8.h
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1387
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv81mml.h:1086
SysTick
#define SysTick
Definition: core_armv8mml.h:1887
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_armv81mml.h:1745
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:497
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv8mml.h:968
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:2291
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv81mml.h:2941
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:2477
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_armv8mml.h:618
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:2427
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv81mml.h:1009
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:391
IRQn
IRQn
Definition: MIMXRT1062.h:74
IRQn_Type
enum IRQn IRQn_Type
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:353
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv8mml.h:975
cmsis_version.h
CMSIS Core(M) Version definitions.
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv81mml.h:2921
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:2221
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_armv8mml.h:1079
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:2503
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: core_armv8mml.h:1687
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:2492
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_armv8mml.h:617
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:422
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:63
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:2240
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv8mml.h:624
__IM
#define __IM
Definition: core_armv8mml.h:278
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:2402
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_armv8mml.h:603
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv8mml.h:971
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_armv81mml.h:1875
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:461
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:2202
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_armcc.h:69
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: core_armv8mml.h:1684
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:314
cmsis_compiler.h
CMSIS compiler generic header file.
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv8mml.h:965
ITM
#define ITM
Definition: core_armv8mml.h:1889
SCB
#define SCB
Definition: core_armv8mml.h:1886
__OM
#define __OM
Definition: core_armv8mml.h:279
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:2454
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv8mml.h:1984
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv8mml.h:602
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1201