Callisto4Bootloader: Globals

Callisto4Bootloader

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

### - i -

- i : excep_test.c
- I2S_BASE_ADDRS : MIMXRT1062.h
- I2S_BASE_PTRS : MIMXRT1062.h
- I2S_PARAM_DATALINE : MIMXRT1062.h
- I2S_PARAM_DATALINE_MASK : MIMXRT1062.h
- I2S_PARAM_DATALINE_SHIFT : MIMXRT1062.h
- I2S_PARAM_FIFO : MIMXRT1062.h
- I2S_PARAM_FIFO_MASK : MIMXRT1062.h
- I2S_PARAM_FIFO_SHIFT : MIMXRT1062.h
- I2S_PARAM_FRAME : MIMXRT1062.h
- I2S_PARAM_FRAME_MASK : MIMXRT1062.h
- I2S_PARAM_FRAME_SHIFT : MIMXRT1062.h
- I2S_RCR1_RFW : MIMXRT1062.h
- I2S_RCR1_RFW_MASK : MIMXRT1062.h
- I2S_RCR1_RFW_SHIFT : MIMXRT1062.h
- I2S_RCR2_BCD : MIMXRT1062.h
- I2S_RCR2_BCD_MASK : MIMXRT1062.h
- I2S_RCR2_BCD_SHIFT : MIMXRT1062.h
- I2S_RCR2_BCI : MIMXRT1062.h
- I2S_RCR2_BCI_MASK : MIMXRT1062.h
- I2S_RCR2_BCI_SHIFT : MIMXRT1062.h
- I2S_RCR2_BCP : MIMXRT1062.h
- I2S_RCR2_BCP_MASK : MIMXRT1062.h
- I2S_RCR2_BCP_SHIFT : MIMXRT1062.h
- I2S_RCR2_BCS : MIMXRT1062.h
- I2S_RCR2_BCS_MASK : MIMXRT1062.h
- I2S_RCR2_BCS_SHIFT : MIMXRT1062.h
- I2S_RCR2_DIV : MIMXRT1062.h
- I2S_RCR2_DIV_MASK : MIMXRT1062.h
- I2S_RCR2_DIV_SHIFT : MIMXRT1062.h
- I2S_RCR2_MSEL : MIMXRT1062.h
- I2S_RCR2_MSEL_MASK : MIMXRT1062.h
- I2S_RCR2_MSEL_SHIFT : MIMXRT1062.h
- I2S_RCR2_SYNC : MIMXRT1062.h
- I2S_RCR2_SYNC_MASK : MIMXRT1062.h
- I2S_RCR2_SYNC_SHIFT : MIMXRT1062.h
- I2S_RCR3_CFR : MIMXRT1062.h
- I2S_RCR3_CFR_MASK : MIMXRT1062.h
- I2S_RCR3_CFR_SHIFT : MIMXRT1062.h
- I2S_RCR3_RCE : MIMXRT1062.h
- I2S_RCR3_RCE_MASK : MIMXRT1062.h
- I2S_RCR3_RCE_SHIFT : MIMXRT1062.h
- I2S_RCR3_WDFL : MIMXRT1062.h
- I2S_RCR3_WDFL_MASK : MIMXRT1062.h
- I2S_RCR3_WDFL_SHIFT : MIMXRT1062.h
- I2S_RCR4_FCOMB : MIMXRT1062.h
- I2S_RCR4_FCOMB_MASK : MIMXRT1062.h
- I2S_RCR4_FCOMB_SHIFT : MIMXRT1062.h
- I2S_RCR4_FCONT : MIMXRT1062.h
- I2S_RCR4_FCONT_MASK : MIMXRT1062.h
- I2S_RCR4_FCONT_SHIFT : MIMXRT1062.h
- I2S_RCR4_FPACK : MIMXRT1062.h
- I2S_RCR4_FPACK_MASK : MIMXRT1062.h
- I2S_RCR4_FPACK_SHIFT : MIMXRT1062.h
- I2S_RCR4_FRSZ : MIMXRT1062.h
- I2S_RCR4_FRSZ_MASK : MIMXRT1062.h
- I2S_RCR4_FRSZ_SHIFT : MIMXRT1062.h
- I2S_RCR4_FSD : MIMXRT1062.h
- I2S_RCR4_FSD_MASK : MIMXRT1062.h
- I2S_RCR4_FSD_SHIFT : MIMXRT1062.h
- I2S_RCR4_FSE : MIMXRT1062.h
- I2S_RCR4_FSE_MASK : MIMXRT1062.h
- I2S_RCR4_FSE_SHIFT : MIMXRT1062.h
- I2S_RCR4_FSP : MIMXRT1062.h
- I2S_RCR4_FSP_MASK : MIMXRT1062.h
- I2S_RCR4_FSP_SHIFT : MIMXRT1062.h
- I2S_RCR4_MF : MIMXRT1062.h
- I2S_RCR4_MF_MASK : MIMXRT1062.h
- I2S_RCR4_MF_SHIFT : MIMXRT1062.h
- I2S_RCR4_ONDEM : MIMXRT1062.h
- I2S_RCR4_ONDEM_MASK : MIMXRT1062.h
- I2S_RCR4_ONDEM_SHIFT : MIMXRT1062.h
- I2S_RCR4_SYWD : MIMXRT1062.h
- I2S_RCR4_SYWD_MASK : MIMXRT1062.h
- I2S_RCR4_SYWD_SHIFT : MIMXRT1062.h
- I2S_RCR5_FBT : MIMXRT1062.h
- I2S_RCR5_FBT_MASK : MIMXRT1062.h
- I2S_RCR5_FBT_SHIFT : MIMXRT1062.h
- I2S_RCR5_W0W : MIMXRT1062.h
- I2S_RCR5_W0W_MASK : MIMXRT1062.h
- I2S_RCR5_W0W_SHIFT : MIMXRT1062.h
- I2S_RCR5_WNW : MIMXRT1062.h
- I2S_RCR5_WNW_MASK : MIMXRT1062.h
- I2S_RCR5_WNW_SHIFT : MIMXRT1062.h
- I2S_RCSR_BCE : MIMXRT1062.h
- I2S_RCSR_BCE_MASK : MIMXRT1062.h
- I2S_RCSR_BCE_SHIFT : MIMXRT1062.h
- I2S_RCSR_DBGE : MIMXRT1062.h
- I2S_RCSR_DBGE_MASK : MIMXRT1062.h
- I2S_RCSR_DBGE_SHIFT : MIMXRT1062.h
- I2S_RCSR_FEF : MIMXRT1062.h
- I2S_RCSR_FEF_MASK : MIMXRT1062.h
- I2S_RCSR_FEF_SHIFT : MIMXRT1062.h
- I2S_RCSR_FEIE : MIMXRT1062.h
- I2S_RCSR_FEIE_MASK : MIMXRT1062.h
- I2S_RCSR_FEIE_SHIFT : MIMXRT1062.h
- I2S_RCSR_FR : MIMXRT1062.h
- I2S_RCSR_FR_MASK : MIMXRT1062.h
- I2S_RCSR_FR_SHIFT : MIMXRT1062.h
- I2S_RCSR_FRDE : MIMXRT1062.h
- I2S_RCSR_FRDE_MASK : MIMXRT1062.h
- I2S_RCSR_FRDE_SHIFT : MIMXRT1062.h
- I2S_RCSR_FRF : MIMXRT1062.h
- I2S_RCSR_FRF_MASK : MIMXRT1062.h
- I2S_RCSR_FRF_SHIFT : MIMXRT1062.h
- I2S_RCSR_FRIE : MIMXRT1062.h
- I2S_RCSR_FRIE_MASK : MIMXRT1062.h
- I2S_RCSR_FRIE_SHIFT : MIMXRT1062.h
- I2S_RCSR_FWDE : MIMXRT1062.h
- I2S_RCSR_FWDE_MASK : MIMXRT1062.h
- I2S_RCSR_FWDE_SHIFT : MIMXRT1062.h
- I2S_RCSR_FWF : MIMXRT1062.h
- I2S_RCSR_FWF_MASK : MIMXRT1062.h
- I2S_RCSR_FWF_SHIFT : MIMXRT1062.h
- I2S_RCSR_FWIE : MIMXRT1062.h
- I2S_RCSR_FWIE_MASK : MIMXRT1062.h
- I2S_RCSR_FWIE_SHIFT : MIMXRT1062.h
- I2S_RCSR_RE : MIMXRT1062.h
- I2S_RCSR_RE_MASK : MIMXRT1062.h
- I2S_RCSR_RE_SHIFT : MIMXRT1062.h
- I2S_RCSR_SEF : MIMXRT1062.h
- I2S_RCSR_SEF_MASK : MIMXRT1062.h
- I2S_RCSR_SEF_SHIFT : MIMXRT1062.h
- I2S_RCSR_SEIE : MIMXRT1062.h
- I2S_RCSR_SEIE_MASK : MIMXRT1062.h
- I2S_RCSR_SEIE_SHIFT : MIMXRT1062.h
- I2S_RCSR_SR : MIMXRT1062.h
- I2S_RCSR_SR_MASK : MIMXRT1062.h
- I2S_RCSR_SR_SHIFT : MIMXRT1062.h
- I2S_RCSR_STOPE : MIMXRT1062.h
- I2S_RCSR_STOPE_MASK : MIMXRT1062.h
- I2S_RCSR_STOPE_SHIFT : MIMXRT1062.h
- I2S_RCSR_WSF : MIMXRT1062.h
- I2S_RCSR_WSF_MASK : MIMXRT1062.h
- I2S_RCSR_WSF_SHIFT : MIMXRT1062.h
- I2S_RCSR_WSIE : MIMXRT1062.h
- I2S_RCSR_WSIE_MASK : MIMXRT1062.h
- I2S_RCSR_WSIE_SHIFT : MIMXRT1062.h
- I2S_RDR_COUNT : MIMXRT1062.h
- I2S_RDR_RDR : MIMXRT1062.h
- I2S_RDR_RDR_MASK : MIMXRT1062.h
- I2S_RDR_RDR_SHIFT : MIMXRT1062.h
- I2S_RFR_COUNT : MIMXRT1062.h
- I2S_RFR_RCP : MIMXRT1062.h
- I2S_RFR_RCP_MASK : MIMXRT1062.h
- I2S_RFR_RCP_SHIFT : MIMXRT1062.h
- I2S_RFR_RFP : MIMXRT1062.h
- I2S_RFR_RFP_MASK : MIMXRT1062.h
- I2S_RFR_RFP_SHIFT : MIMXRT1062.h
- I2S_RFR_WFP : MIMXRT1062.h
- I2S_RFR_WFP_MASK : MIMXRT1062.h
- I2S_RFR_WFP_SHIFT : MIMXRT1062.h
- I2S_RMR_RWM : MIMXRT1062.h
- I2S_RMR_RWM_MASK : MIMXRT1062.h
- I2S_RMR_RWM_SHIFT : MIMXRT1062.h
- I2S_RX_IRQS : MIMXRT1062.h
- I2S_TCR1_TFW : MIMXRT1062.h
- I2S_TCR1_TFW_MASK : MIMXRT1062.h
- I2S_TCR1_TFW_SHIFT : MIMXRT1062.h
- I2S_TCR2_BCD : MIMXRT1062.h
- I2S_TCR2_BCD_MASK : MIMXRT1062.h
- I2S_TCR2_BCD_SHIFT : MIMXRT1062.h
- I2S_TCR2_BCI : MIMXRT1062.h
- I2S_TCR2_BCI_MASK : MIMXRT1062.h
- I2S_TCR2_BCI_SHIFT : MIMXRT1062.h
- I2S_TCR2_BCP : MIMXRT1062.h
- I2S_TCR2_BCP_MASK : MIMXRT1062.h
- I2S_TCR2_BCP_SHIFT : MIMXRT1062.h
- I2S_TCR2_BCS : MIMXRT1062.h
- I2S_TCR2_BCS_MASK : MIMXRT1062.h
- I2S_TCR2_BCS_SHIFT : MIMXRT1062.h
- I2S_TCR2_DIV : MIMXRT1062.h
- I2S_TCR2_DIV_MASK : MIMXRT1062.h
- I2S_TCR2_DIV_SHIFT : MIMXRT1062.h
- I2S_TCR2_MSEL : MIMXRT1062.h
- I2S_TCR2_MSEL_MASK : MIMXRT1062.h
- I2S_TCR2_MSEL_SHIFT : MIMXRT1062.h
- I2S_TCR2_SYNC : MIMXRT1062.h
- I2S_TCR2_SYNC_MASK : MIMXRT1062.h
- I2S_TCR2_SYNC_SHIFT : MIMXRT1062.h
- I2S_TCR3_CFR : MIMXRT1062.h
- I2S_TCR3_CFR_MASK : MIMXRT1062.h
- I2S_TCR3_CFR_SHIFT : MIMXRT1062.h
- I2S_TCR3_TCE : MIMXRT1062.h
- I2S_TCR3_TCE_MASK : MIMXRT1062.h
- I2S_TCR3_TCE_SHIFT : MIMXRT1062.h
- I2S_TCR3_WDFL : MIMXRT1062.h
- I2S_TCR3_WDFL_MASK : MIMXRT1062.h
- I2S_TCR3_WDFL_SHIFT : MIMXRT1062.h
- I2S_TCR4_CHMOD : MIMXRT1062.h
- I2S_TCR4_CHMOD_MASK : MIMXRT1062.h
- I2S_TCR4_CHMOD_SHIFT : MIMXRT1062.h
- I2S_TCR4_FCOMB : MIMXRT1062.h
- I2S_TCR4_FCOMB_MASK : MIMXRT1062.h
- I2S_TCR4_FCOMB_SHIFT : MIMXRT1062.h
- I2S_TCR4_FCONT : MIMXRT1062.h
- I2S_TCR4_FCONT_MASK : MIMXRT1062.h
- I2S_TCR4_FCONT_SHIFT : MIMXRT1062.h
- I2S_TCR4_FPACK : MIMXRT1062.h
- I2S_TCR4_FPACK_MASK : MIMXRT1062.h
- I2S_TCR4_FPACK_SHIFT : MIMXRT1062.h
- I2S_TCR4_FRSZ : MIMXRT1062.h
- I2S_TCR4_FRSZ_MASK : MIMXRT1062.h
- I2S_TCR4_FRSZ_SHIFT : MIMXRT1062.h
- I2S_TCR4_FSD : MIMXRT1062.h
- I2S_TCR4_FSD_MASK : MIMXRT1062.h
- I2S_TCR4_FSD_SHIFT : MIMXRT1062.h
- I2S_TCR4_FSE : MIMXRT1062.h
- I2S_TCR4_FSE_MASK : MIMXRT1062.h
- I2S_TCR4_FSE_SHIFT : MIMXRT1062.h
- I2S_TCR4_FSP : MIMXRT1062.h
- I2S_TCR4_FSP_MASK : MIMXRT1062.h
- I2S_TCR4_FSP_SHIFT : MIMXRT1062.h
- I2S_TCR4_MF : MIMXRT1062.h
- I2S_TCR4_MF_MASK : MIMXRT1062.h
- I2S_TCR4_MF_SHIFT : MIMXRT1062.h
- I2S_TCR4_ONDEM : MIMXRT1062.h
- I2S_TCR4_ONDEM_MASK : MIMXRT1062.h
- I2S_TCR4_ONDEM_SHIFT : MIMXRT1062.h
- I2S_TCR4_SYWD : MIMXRT1062.h
- I2S_TCR4_SYWD_MASK : MIMXRT1062.h
- I2S_TCR4_SYWD_SHIFT : MIMXRT1062.h
- I2S_TCR5_FBT : MIMXRT1062.h
- I2S_TCR5_FBT_MASK : MIMXRT1062.h
- I2S_TCR5_FBT_SHIFT : MIMXRT1062.h
- I2S_TCR5_W0W : MIMXRT1062.h
- I2S_TCR5_W0W_MASK : MIMXRT1062.h
- I2S_TCR5_W0W_SHIFT : MIMXRT1062.h
- I2S_TCR5_WNW : MIMXRT1062.h
- I2S_TCR5_WNW_MASK : MIMXRT1062.h
- I2S_TCR5_WNW_SHIFT : MIMXRT1062.h
- I2S_TCSR_BCE : MIMXRT1062.h
- I2S_TCSR_BCE_MASK : MIMXRT1062.h
- I2S_TCSR_BCE_SHIFT : MIMXRT1062.h
- I2S_TCSR_DBGE : MIMXRT1062.h
- I2S_TCSR_DBGE_MASK : MIMXRT1062.h
- I2S_TCSR_DBGE_SHIFT : MIMXRT1062.h
- I2S_TCSR_FEF : MIMXRT1062.h
- I2S_TCSR_FEF_MASK : MIMXRT1062.h
- I2S_TCSR_FEF_SHIFT : MIMXRT1062.h
- I2S_TCSR_FEIE : MIMXRT1062.h
- I2S_TCSR_FEIE_MASK : MIMXRT1062.h
- I2S_TCSR_FEIE_SHIFT : MIMXRT1062.h
- I2S_TCSR_FR : MIMXRT1062.h
- I2S_TCSR_FR_MASK : MIMXRT1062.h
- I2S_TCSR_FR_SHIFT : MIMXRT1062.h
- I2S_TCSR_FRDE : MIMXRT1062.h
- I2S_TCSR_FRDE_MASK : MIMXRT1062.h
- I2S_TCSR_FRDE_SHIFT : MIMXRT1062.h
- I2S_TCSR_FRF : MIMXRT1062.h
- I2S_TCSR_FRF_MASK : MIMXRT1062.h
- I2S_TCSR_FRF_SHIFT : MIMXRT1062.h
- I2S_TCSR_FRIE : MIMXRT1062.h
- I2S_TCSR_FRIE_MASK : MIMXRT1062.h
- I2S_TCSR_FRIE_SHIFT : MIMXRT1062.h
- I2S_TCSR_FWDE : MIMXRT1062.h
- I2S_TCSR_FWDE_MASK : MIMXRT1062.h
- I2S_TCSR_FWDE_SHIFT : MIMXRT1062.h
- I2S_TCSR_FWF : MIMXRT1062.h
- I2S_TCSR_FWF_MASK : MIMXRT1062.h
- I2S_TCSR_FWF_SHIFT : MIMXRT1062.h
- I2S_TCSR_FWIE : MIMXRT1062.h
- I2S_TCSR_FWIE_MASK : MIMXRT1062.h
- I2S_TCSR_FWIE_SHIFT : MIMXRT1062.h
- I2S_TCSR_SEF : MIMXRT1062.h
- I2S_TCSR_SEF_MASK : MIMXRT1062.h
- I2S_TCSR_SEF_SHIFT : MIMXRT1062.h
- I2S_TCSR_SEIE : MIMXRT1062.h
- I2S_TCSR_SEIE_MASK : MIMXRT1062.h
- I2S_TCSR_SEIE_SHIFT : MIMXRT1062.h
- I2S_TCSR_SR : MIMXRT1062.h
- I2S_TCSR_SR_MASK : MIMXRT1062.h
- I2S_TCSR_SR_SHIFT : MIMXRT1062.h
- I2S_TCSR_STOPE : MIMXRT1062.h
- I2S_TCSR_STOPE_MASK : MIMXRT1062.h
- I2S_TCSR_STOPE_SHIFT : MIMXRT1062.h
- I2S_TCSR_TE : MIMXRT1062.h
- I2S_TCSR_TE_MASK : MIMXRT1062.h
- I2S_TCSR_TE_SHIFT : MIMXRT1062.h
- I2S_TCSR_WSF : MIMXRT1062.h
- I2S_TCSR_WSF_MASK : MIMXRT1062.h
- I2S_TCSR_WSF_SHIFT : MIMXRT1062.h
- I2S_TCSR_WSIE : MIMXRT1062.h
- I2S_TCSR_WSIE_MASK : MIMXRT1062.h
- I2S_TCSR_WSIE_SHIFT : MIMXRT1062.h
- I2S_TDR_COUNT : MIMXRT1062.h
- I2S_TDR_TDR : MIMXRT1062.h
- I2S_TDR_TDR_MASK : MIMXRT1062.h
- I2S_TDR_TDR_SHIFT : MIMXRT1062.h
- I2S_TFR_COUNT : MIMXRT1062.h
- I2S_TFR_RFP : MIMXRT1062.h
- I2S_TFR_RFP_MASK : MIMXRT1062.h
- I2S_TFR_RFP_SHIFT : MIMXRT1062.h
- I2S_TFR_WCP : MIMXRT1062.h
- I2S_TFR_WCP_MASK : MIMXRT1062.h
- I2S_TFR_WCP_SHIFT : MIMXRT1062.h
- I2S_TFR_WFP : MIMXRT1062.h
- I2S_TFR_WFP_MASK : MIMXRT1062.h
- I2S_TFR_WFP_SHIFT : MIMXRT1062.h
- I2S_TMR_TWM : MIMXRT1062.h
- I2S_TMR_TWM_MASK : MIMXRT1062.h
- I2S_TMR_TWM_SHIFT : MIMXRT1062.h
- I2S_TX_IRQS : MIMXRT1062.h
- I2S_VERID_FEATURE : MIMXRT1062.h
- I2S_VERID_FEATURE_MASK : MIMXRT1062.h
- I2S_VERID_FEATURE_SHIFT : MIMXRT1062.h
- I2S_VERID_MAJOR : MIMXRT1062.h
- I2S_VERID_MAJOR_MASK : MIMXRT1062.h
- I2S_VERID_MAJOR_SHIFT : MIMXRT1062.h
- I2S_VERID_MINOR : MIMXRT1062.h
- I2S_VERID_MINOR_MASK : MIMXRT1062.h
- I2S_VERID_MINOR_SHIFT : MIMXRT1062.h
- image_vector_table : bootloader.c
- INDEX_MASK : arm_math.h
- init_hardware() : bootloader_common.h
- InitialiseI2C2() : platform_eeprom.c
- InitialiseI2CMasterClock() : platform_eeprom.c
- INPUT_SPACING : arm_math.h
- IntDefaultHandler() : startup_mimxrt1062.c
- IOMUXC : MIMXRT1062.h
- IOMUXC_BASE : MIMXRT1062.h
- IOMUXC_BASE_ADDRS : MIMXRT1062.h
- IOMUXC_BASE_PTRS : MIMXRT1062.h
- IOMUXC_GPR : MIMXRT1062.h
- IOMUXC_GPR_BASE : MIMXRT1062.h
- IOMUXC_GPR_BASE_ADDRS : MIMXRT1062.h
- IOMUXC_GPR_BASE_PTRS : MIMXRT1062.h
- IOMUXC_GPR_GPR10_DBG_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR10_DBG_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_DBG_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX : MIMXRT1062.h
- IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_DBG_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_NIDEN : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_NIDEN : MIMXRT1062.h
- IOMUXC_GPR_GPR10_NIDEN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_NIDEN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR : MIMXRT1062.h
- IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_OCRAM_TZ_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR10_SEC_ERR_RESP : MIMXRT1062.h
- IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR11_BEE_DE_RX_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR13_ARCACHE_USDHC : MIMXRT1062.h
- IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR13_AWCACHE_USDHC : MIMXRT1062.h
- IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CACHE_ENET : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CACHE_ENET_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CACHE_USB : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CACHE_USB_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CACHE_USB_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CANFD_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CANFD_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ : MIMXRT1062.h
- IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR14_CM7_CFGITCMSZ : MIMXRT1062.h
- IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR16_INIT_DTCM_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR16_INIT_ITCM_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG : MIMXRT1062.h
- IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT : MIMXRT1062.h
- IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT : MIMXRT1062.h
- IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP : MIMXRT1062.h
- IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP : MIMXRT1062.h
- IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET1_CLK_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET2_CLK_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_EXC_MON : MIMXRT1062.h
- IOMUXC_GPR_GPR1_EXC_MON_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_EXC_MON_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_GINT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_GINT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_GINT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK_DIR : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI2_MCLK_DIR : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI3_MCLK_DIR : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR1_USB_EXP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT : MIMXRT1062.h
- IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT : MIMXRT1062.h
- IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP : MIMXRT1062.h
- IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP : MIMXRT1062.h
- IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT : MIMXRT1062.h
- IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT : MIMXRT1062.h
- IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP : MIMXRT1062.h
- IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP : MIMXRT1062.h
- IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT : MIMXRT1062.h
- IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT : MIMXRT1062.h
- IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP : MIMXRT1062.h
- IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP : MIMXRT1062.h
- IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS : MIMXRT1062.h
- IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP : MIMXRT1062.h
- IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING : MIMXRT1062.h
- IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_CLK_DIV : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_OVERSAMPLE : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_SW_RST : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_SW_RST_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START : MIMXRT1062.h
- IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END : MIMXRT1062.h
- IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET : MIMXRT1062.h
- IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR : MIMXRT1062.h
- IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR : MIMXRT1062.h
- IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR33_OCRAM2_TZ_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN : MIMXRT1062.h
- IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR3_AXBS_L_HALTED : MIMXRT1062.h
- IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR3_DCP_KEY_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM2_CTL : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM2_STATUS : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM_CTL : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM_CTL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM_STATUS : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN1_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN1_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN2_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN2_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_EDMA_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_EDMA_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET2_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET2_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_PIT_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_PIT_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI1_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI1_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI2_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI2_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI3_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI3_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SEMC_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SEMC_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_TRNG_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR4_TRNG_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1 : MIMXRT1062.h
- IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2 : MIMXRT1062.h
- IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR5_WDOG1_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_WDOG1_MASK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR5_WDOG2_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_WDOG2_MASK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9 : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART1_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART1_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART2_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART2_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART3_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART3_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART4_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART4_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART5_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART5_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART6_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART6_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART7_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART7_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART8_STOP_ACK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART8_STOP_REQ : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK : MIMXRT1062.h
- IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_SELECT_INPUT_1_COUNT : MIMXRT1062.h
- IOMUXC_SELECT_INPUT_1_DAISY : MIMXRT1062.h
- IOMUXC_SELECT_INPUT_1_DAISY_MASK : MIMXRT1062.h
- IOMUXC_SELECT_INPUT_1_DAISY_SHIFT : MIMXRT1062.h
- iomuxc_select_input_1_t : MIMXRT1062.h
- IOMUXC_SELECT_INPUT_COUNT : MIMXRT1062.h
- IOMUXC_SELECT_INPUT_DAISY : MIMXRT1062.h
- IOMUXC_SELECT_INPUT_DAISY_MASK : MIMXRT1062.h
- IOMUXC_SELECT_INPUT_DAISY_SHIFT : MIMXRT1062.h
- iomuxc_select_input_t : MIMXRT1062.h
- IOMUXC_SNVS : MIMXRT1062.h
- IOMUXC_SNVS_BASE : MIMXRT1062.h
- IOMUXC_SNVS_BASE_ADDRS : MIMXRT1062.h
- IOMUXC_SNVS_BASE_PTRS : MIMXRT1062.h
- IOMUXC_SNVS_GPR : MIMXRT1062.h
- IOMUXC_SNVS_GPR_BASE : MIMXRT1062.h
- IOMUXC_SNVS_GPR_BASE_ADDRS : MIMXRT1062.h
- IOMUXC_SNVS_GPR_BASE_PTRS : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK : MIMXRT1062.h
- IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_1_COUNT : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_1_SION : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT : MIMXRT1062.h
- iomuxc_sw_mux_ctl_pad_1_t : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_COUNT : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_MUX_MODE : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_SION : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_SION_MASK : MIMXRT1062.h
- IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT : MIMXRT1062.h
- iomuxc_sw_mux_ctl_pad_t : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_COUNT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_DSE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_HYS : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_ODE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PKE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PUE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PUS : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_SPEED : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_SRE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT : MIMXRT1062.h
- iomuxc_sw_pad_ctl_pad_1_t : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_COUNT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_DSE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_DSE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_HYS : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_HYS_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_ODE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_ODE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PKE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PKE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PUE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PUE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PUS : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PUS_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_SPEED : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_SRE : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_SRE_MASK : MIMXRT1062.h
- IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT : MIMXRT1062.h
- iomuxc_sw_pad_ctl_pad_t : MIMXRT1062.h
- ipaddress_show() : bootloader.c , c4_tftp.c
- IPSR_ISR_Msk : core_armv8mbl.h , core_cm7.h , core_armv8mml.h , core_armv81mml.h
- IPSR_ISR_Pos : core_armv8mbl.h , core_armv81mml.h , core_armv8mml.h , core_cm7.h
- IRQn : MIMXRT1062.h
- IRQn_Type : MIMXRT1062.h
- is_boot_pin_asserted() : bootloader_common.h
- is_flexspi_nor_present() : bootloader_common.h
- is_in_execute_only_region() : bootloader_common.h
- is_ltc_present() : bootloader_common.h
- is_otfad_present() : bootloader_common.h
- is_qspi_present() : bootloader_common.h
- is_second_core_present() : bootloader_common.h
- is_secondary_i2c_slave_address_enabled() : bootloader_common.h
- is_semc_nor_present() : bootloader_common.h
- ITM : core_armv8mml.h , core_cm7.h , core_armv81mml.h
- ITM_BASE : core_cm7.h , core_armv81mml.h , core_armv8mml.h
- ITM_CheckChar() : core_armv81mml.h
- ITM_IMCR_INTEGRATION_Msk : core_armv81mml.h
- ITM_IMCR_INTEGRATION_Pos : core_armv81mml.h
- ITM_IRR_ATREADYM_Msk : core_armv81mml.h
- ITM_IRR_ATREADYM_Pos : core_armv81mml.h
- ITM_IWR_ATVALIDM_Msk : core_armv81mml.h
- ITM_IWR_ATVALIDM_Pos : core_armv81mml.h
- ITM_LSR_Access_Msk : core_cm7.h , core_armv8mml.h , core_armv81mml.h
- ITM_LSR_Access_Pos : core_cm7.h , core_armv8mml.h , core_armv81mml.h
- ITM_LSR_ByteAcc_Msk : core_armv8mml.h , core_cm7.h , core_armv81mml.h
- ITM_LSR_ByteAcc_Pos : core_armv81mml.h , core_cm7.h , core_armv8mml.h
- ITM_LSR_Present_Msk : core_armv8mml.h , core_armv81mml.h , core_cm7.h
- ITM_LSR_Present_Pos : core_armv81mml.h , core_armv8mml.h , core_cm7.h
- ITM_ReceiveChar() : core_armv81mml.h
- ITM_RxBuffer : core_armv81mml.h , core_cm7.h , core_armv8mml.h
- ITM_RXBUFFER_EMPTY : core_armv8mml.h , core_armv81mml.h , core_cm7.h
- ITM_SendChar() : core_armv81mml.h
- ITM_STIM_DISABLED_Msk : core_armv8mml.h , core_armv81mml.h
- ITM_STIM_DISABLED_Pos : core_armv8mml.h , core_armv81mml.h
- ITM_STIM_FIFOREADY_Msk : core_armv8mml.h , core_armv81mml.h
- ITM_STIM_FIFOREADY_Pos : core_armv8mml.h , core_armv81mml.h
- ITM_TCR_BUSY_Msk : core_armv81mml.h , core_armv8mml.h , core_cm7.h
- ITM_TCR_BUSY_Pos : core_armv8mml.h , core_cm7.h , core_armv81mml.h
- ITM_TCR_DWTENA_Msk : core_armv81mml.h , core_cm7.h , core_armv8mml.h
- ITM_TCR_DWTENA_Pos : core_armv81mml.h , core_armv8mml.h , core_cm7.h
- ITM_TCR_GTSFREQ_Msk : core_armv81mml.h , core_cm7.h , core_armv8mml.h
- ITM_TCR_GTSFREQ_Pos : core_cm7.h , core_armv8mml.h , core_armv81mml.h
- ITM_TCR_ITMENA_Msk : core_armv81mml.h , core_armv8mml.h , core_cm7.h
- ITM_TCR_ITMENA_Pos : core_armv81mml.h , core_cm7.h , core_armv8mml.h
- ITM_TCR_STALLENA_Msk : core_armv81mml.h , core_armv8mml.h
- ITM_TCR_STALLENA_Pos : core_armv8mml.h , core_armv81mml.h
- ITM_TCR_SWOENA_Msk : core_armv8mml.h , core_cm7.h , core_armv81mml.h
- ITM_TCR_SWOENA_Pos : core_armv8mml.h , core_armv81mml.h , core_cm7.h
- ITM_TCR_SYNCENA_Msk : core_armv8mml.h , core_cm7.h , core_armv81mml.h
- ITM_TCR_SYNCENA_Pos : core_cm7.h , core_armv81mml.h , core_armv8mml.h
- ITM_TCR_TRACEBUSID_Msk : core_armv8mml.h
- ITM_TCR_TraceBusID_Msk : core_cm7.h
- ITM_TCR_TRACEBUSID_Msk : core_armv81mml.h
- ITM_TCR_TraceBusID_Pos : core_cm7.h
- ITM_TCR_TRACEBUSID_Pos : core_armv8mml.h , core_armv81mml.h
- ITM_TCR_TSENA_Msk : core_armv8mml.h , core_armv81mml.h , core_cm7.h
- ITM_TCR_TSENA_Pos : core_armv8mml.h , core_cm7.h , core_armv81mml.h
- ITM_TCR_TSPrescale_Msk : core_cm7.h
- ITM_TCR_TSPRESCALE_Msk : core_armv8mml.h , core_armv81mml.h
- ITM_TCR_TSPRESCALE_Pos : core_armv81mml.h
- ITM_TCR_TSPrescale_Pos : core_cm7.h
- ITM_TCR_TSPRESCALE_Pos : core_armv8mml.h
- ITM_TPR_PRIVMASK_Msk : core_armv8mml.h , core_cm7.h , core_armv81mml.h
- ITM_TPR_PRIVMASK_Pos : core_armv81mml.h , core_armv8mml.h , core_cm7.h
- IVT_offset : bootloader.c