Callisto4Bootloader: device/MIMXRT1062.h File Reference

Callisto4Bootloader

Data Structures | Macros | Typedefs | Enumerations
MIMXRT1062.h File Reference

CMSIS Peripheral Access Layer for MIMXRT1062. More...

`#include "core_cm7.h"`
`#include "system_MIMXRT1062.h"`

Go to the source code of this file.

## Data Structures

struct | ADC_Type
struct | ADC_ETC_Type
struct | AIPSTZ_Type
struct | AOI_Type
struct | BEE_Type
struct | CAN_Type
struct | CCM_Type
struct | CCM_ANALOG_Type
struct | CMP_Type
struct | CSI_Type
struct | CSU_Type
struct | DCDC_Type
struct | DCP_Type
struct | DMA_Type
struct | DMAMUX_Type
struct | ENC_Type
struct | ENET_Type
struct | EWM_Type
struct | FLEXIO_Type
struct | FLEXRAM_Type
struct | FLEXSPI_Type
struct | GPC_Type
struct | GPIO_Type
struct | GPT_Type
struct | I2S_Type
struct | IOMUXC_Type
struct | IOMUXC_GPR_Type
struct | IOMUXC_SNVS_Type
struct | IOMUXC_SNVS_GPR_Type
struct | KPP_Type
struct | LCDIF_Type
struct | LPI2C_Type
struct | LPSPI_Type
struct | LPUART_Type
struct | OCOTP_Type
struct | PGC_Type
struct | PIT_Type
struct | PMU_Type
struct | PWM_Type
struct | PXP_Type
struct | ROMC_Type
struct | RTWDOG_Type
struct | SEMC_Type
struct | SNVS_Type
struct | SPDIF_Type
struct | SRC_Type
struct | TEMPMON_Type
struct | TMR_Type
struct | TRNG_Type
struct | TSC_Type
struct | USB_Type
struct | USBNC_Type
struct | USBPHY_Type
struct | USB_ANALOG_Type
struct | USDHC_Type
struct | WDOG_Type
struct | XBARA_Type
struct | XBARB_Type
struct | XTALOSC24M_Type

## Macros

#define | _MIMXRT1062_H_
#define | MCU_MEM_MAP_VERSION 0x0100U
#define | MCU_MEM_MAP_VERSION_MINOR 0x0002U
#define | NUMBER_OF_INT_VECTORS 174
#define | __MPU_PRESENT 1
#define | __ICACHE_PRESENT 1
#define | __DCACHE_PRESENT 1
#define | __DTCM_PRESENT 1
#define | __NVIC_PRIO_BITS 4
#define | __Vendor_SysTickConfig 0
#define | __FPU_PRESENT 1
#define | ADC_HC_COUNT (8U)
#define | ADC_R_COUNT (8U)
#define | ADC1_BASE (0x400C4000u)
#define | ADC1 ((ADC_Type *)ADC1_BASE)
#define | ADC2_BASE (0x400C8000u)
#define | ADC2 ((ADC_Type *)ADC2_BASE)
#define | ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
#define | ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
#define | ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
#define | ADC_ETC_TRIGn_CTRL_COUNT (8U)
#define | ADC_ETC_TRIGn_COUNTER_COUNT (8U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
#define | ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
#define | ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
#define | ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
#define | ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
#define | ADC_ETC_BASE (0x403B0000u)
#define | ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
#define | ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
#define | ADC_ETC_BASE_PTRS { ADC_ETC }
#define | ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
#define | ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
#define | AIPSTZ1_BASE (0x4007C000u)
#define | AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
#define | AIPSTZ2_BASE (0x4017C000u)
#define | AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
#define | AIPSTZ3_BASE (0x4027C000u)
#define | AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
#define | AIPSTZ4_BASE (0x4037C000u)
#define | AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
#define | AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
#define | AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
#define | AOI_BFCRT01_COUNT (4U)
#define | AOI_BFCRT23_COUNT (4U)
#define | AOI1_BASE (0x403B4000u)
#define | AOI1 ((AOI_Type *)AOI1_BASE)
#define | AOI2_BASE (0x403B8000u)
#define | AOI2 ((AOI_Type *)AOI2_BASE)
#define | AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
#define | AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
#define | BEE_BASE (0x403EC000u)
#define | BEE ((BEE_Type *)BEE_BASE)
#define | BEE_BASE_ADDRS { BEE_BASE }
#define | BEE_BASE_PTRS { BEE }
#define | CAN_CS_COUNT_MB8B (64U)
#define | CAN_ID_COUNT_MB8B (64U)
#define | CAN_WORD_COUNT_MB8B (64U)
#define | CAN_WORD_COUNT_MB8B2 (2U)
#define | CAN_CS_COUNT_MB16B (42U)
#define | CAN_ID_COUNT_MB16B (42U)
#define | CAN_WORD_COUNT_MB16B (42U)
#define | CAN_WORD_COUNT_MB16B2 (4U)
#define | CAN_CS_COUNT_MB32B (24U)
#define | CAN_ID_COUNT_MB32B (24U)
#define | CAN_WORD_COUNT_MB32B (24U)
#define | CAN_WORD_COUNT_MB32B2 (8U)
#define | CAN_CS_COUNT_MB64B (14U)
#define | CAN_ID_COUNT_MB64B (14U)
#define | CAN_WORD_COUNT_MB64B (14U)
#define | CAN_WORD_COUNT_MB64B2 (16U)
#define | CAN_CS_COUNT (64U)
#define | CAN_ID_COUNT (64U)
#define | CAN_WORD0_COUNT (64U)
#define | CAN_WORD1_COUNT (64U)
#define | CAN_RXIMR_COUNT (64U)
#define | CAN_HR_TIME_STAMP_COUNT (64U)
#define | CAN_ERFFEL_COUNT (128U)
#define | CAN1_BASE (0x401D0000u)
#define | CAN1 ((CAN_Type *)CAN1_BASE)
#define | CAN2_BASE (0x401D4000u)
#define | CAN2 ((CAN_Type *)CAN2_BASE)
#define | CAN3_BASE (0x401D8000u)
#define | CAN3 ((CAN_Type *)CAN3_BASE)
#define | CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
#define | CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
#define | CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define | CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define | CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define | CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define | CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define | CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define | CCM_BASE (0x400FC000u)
#define | CCM ((CCM_Type *)CCM_BASE)
#define | CCM_BASE_ADDRS { CCM_BASE }
#define | CCM_BASE_PTRS { CCM }
#define | CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
#define | CCM_ANALOG_BASE (0x400D8000u)
#define | CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
#define | CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
#define | CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
#define | CMP1_BASE (0x40094000u)
#define | CMP1 ((CMP_Type *)CMP1_BASE)
#define | CMP2_BASE (0x40094008u)
#define | CMP2 ((CMP_Type *)CMP2_BASE)
#define | CMP3_BASE (0x40094010u)
#define | CMP3 ((CMP_Type *)CMP3_BASE)
#define | CMP4_BASE (0x40094018u)
#define | CMP4 ((CMP_Type *)CMP4_BASE)
#define | CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
#define | CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
#define | CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
#define | CSI_BASE (0x402BC000u)
#define | CSI ((CSI_Type *)CSI_BASE)
#define | CSI_BASE_ADDRS { CSI_BASE }
#define | CSI_BASE_PTRS { CSI }
#define | CSI_IRQS { CSI_IRQn }
#define | CSU_CSL_COUNT (32U)
#define | CSU_BASE (0x400DC000u)
#define | CSU ((CSU_Type *)CSU_BASE)
#define | CSU_BASE_ADDRS { CSU_BASE }
#define | CSU_BASE_PTRS { CSU }
#define | DCDC_BASE (0x40080000u)
#define | DCDC ((DCDC_Type *)DCDC_BASE)
#define | DCDC_BASE_ADDRS { DCDC_BASE }
#define | DCDC_BASE_PTRS { DCDC }
#define | DCDC_IRQS { DCDC_IRQn }
#define | DCP_BASE (0x402FC000u)
#define | DCP ((DCP_Type *)DCP_BASE)
#define | DCP_BASE_ADDRS { DCP_BASE }
#define | DCP_BASE_PTRS { DCP }
#define | DCP_IRQS { DCP_IRQn }
#define | DCP_VMI_IRQS { DCP_VMI_IRQn }
#define | DMA_SADDR_COUNT (32U)
#define | DMA_SOFF_COUNT (32U)
#define | DMA_ATTR_COUNT (32U)
#define | DMA_NBYTES_MLNO_COUNT (32U)
#define | DMA_NBYTES_MLOFFNO_COUNT (32U)
#define | DMA_NBYTES_MLOFFYES_COUNT (32U)
#define | DMA_SLAST_COUNT (32U)
#define | DMA_DADDR_COUNT (32U)
#define | DMA_DOFF_COUNT (32U)
#define | DMA_CITER_ELINKNO_COUNT (32U)
#define | DMA_CITER_ELINKYES_COUNT (32U)
#define | DMA_DLAST_SGA_COUNT (32U)
#define | DMA_CSR_COUNT (32U)
#define | DMA_BITER_ELINKNO_COUNT (32U)
#define | DMA_BITER_ELINKYES_COUNT (32U)
#define | DMA0_BASE (0x400E8000u)
#define | DMA0 ((DMA_Type *)DMA0_BASE)
#define | DMA_BASE_ADDRS { DMA0_BASE }
#define | DMA_BASE_PTRS { DMA0 }
#define | DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
#define | DMA_ERROR_IRQS { DMA_ERROR_IRQn }
#define | DMAMUX_CHCFG_COUNT (32U)
#define | DMAMUX_BASE (0x400EC000u)
#define | DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
#define | DMAMUX_BASE_ADDRS { DMAMUX_BASE }
#define | DMAMUX_BASE_PTRS { DMAMUX }
#define | ENC1_BASE (0x403C8000u)
#define | ENC1 ((ENC_Type *)ENC1_BASE)
#define | ENC2_BASE (0x403CC000u)
#define | ENC2 ((ENC_Type *)ENC2_BASE)
#define | ENC3_BASE (0x403D0000u)
#define | ENC3 ((ENC_Type *)ENC3_BASE)
#define | ENC4_BASE (0x403D4000u)
#define | ENC4 ((ENC_Type *)ENC4_BASE)
#define | ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
#define | ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
#define | ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define | ENET_TCSR_COUNT (4U)
#define | ENET_TCCR_COUNT (4U)
#define | ENET_BASE (0x402D8000u)
#define | ENET ((ENET_Type *)ENET_BASE)
#define | ENET2_BASE (0x402D4000u)
#define | ENET2 ((ENET_Type *)ENET2_BASE)
#define | ENET_BASE_ADDRS { ENET_BASE, 0u, ENET2_BASE }
#define | ENET_BASE_PTRS { ENET, (ENET_Type *)0u, ENET2 }
#define | ENET_Transmit_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
#define | ENET_Receive_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
#define | ENET_Error_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
#define | ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, NotAvail_IRQn, ENET2_1588_Timer_IRQn }
#define | ENET_BUFF_ALIGNMENT (64U)
#define | EWM_BASE (0x400B4000u)
#define | EWM ((EWM_Type *)EWM_BASE)
#define | EWM_BASE_ADDRS { EWM_BASE }
#define | EWM_BASE_PTRS { EWM }
#define | EWM_IRQS { EWM_IRQn }
#define | FLEXIO_SHIFTCTL_COUNT (4U)
#define | FLEXIO_SHIFTCFG_COUNT (4U)
#define | FLEXIO_SHIFTBUF_COUNT (4U)
#define | FLEXIO_SHIFTBUFBIS_COUNT (4U)
#define | FLEXIO_SHIFTBUFBYS_COUNT (4U)
#define | FLEXIO_SHIFTBUFBBS_COUNT (4U)
#define | FLEXIO_TIMCTL_COUNT (4U)
#define | FLEXIO_TIMCFG_COUNT (4U)
#define | FLEXIO_TIMCMP_COUNT (4U)
#define | FLEXIO_SHIFTBUFNBS_COUNT (4U)
#define | FLEXIO_SHIFTBUFHWS_COUNT (4U)
#define | FLEXIO_SHIFTBUFNIS_COUNT (4U)
#define | FLEXIO1_BASE (0x401AC000u)
#define | FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
#define | FLEXIO2_BASE (0x401B0000u)
#define | FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
#define | FLEXIO3_BASE (0x42020000u)
#define | FLEXIO3 ((FLEXIO_Type *)FLEXIO3_BASE)
#define | FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE, FLEXIO3_BASE }
#define | FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2, FLEXIO3 }
#define | FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn, FLEXIO3_IRQn }
#define | FLEXRAM_BASE (0x400B0000u)
#define | FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
#define | FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
#define | FLEXRAM_BASE_PTRS { FLEXRAM }
#define | FLEXRAM_IRQS { FLEXRAM_IRQn }
#define | FLEXSPI_AHBRXBUFCR0_COUNT (4U)
#define | FLEXSPI_FLSHCR0_COUNT (4U)
#define | FLEXSPI_FLSHCR1_COUNT (4U)
#define | FLEXSPI_FLSHCR2_COUNT (4U)
#define | FLEXSPI_DLLCR_COUNT (2U)
#define | FLEXSPI_RFDR_COUNT (32U)
#define | FLEXSPI_TFDR_COUNT (32U)
#define | FLEXSPI_LUT_COUNT (64U)
#define | FLEXSPI_BASE (0x402A8000u)
#define | FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
#define | FLEXSPI2_BASE (0x402A4000u)
#define | FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE)
#define | FLEXSPI_BASE_ADDRS { FLEXSPI_BASE, 0u, FLEXSPI2_BASE }
#define | FLEXSPI_BASE_PTRS { FLEXSPI, (FLEXSPI_Type *)0u, FLEXSPI2 }
#define | FLEXSPI_IRQS { FLEXSPI_IRQn, NotAvail_IRQn, FLEXSPI2_IRQn }
#define | FlexSPI_AMBA_BASE (0x60000000U)
#define | FlexSPI_ASFM_BASE (0x60000000U)
#define | FlexSPI_ARDF_BASE (0x7FC00000U)
#define | FlexSPI_ATDF_BASE (0x7F800000U)
#define | FlexSPI2_AMBA_BASE (0x70000000U)
#define | FlexSPI2_ASFM_BASE (0x70000000U)
#define | FlexSPI2_ARDF_BASE (0x7F400000U)
#define | FlexSPI2_ATDF_BASE (0x7F000000U)
#define | GPC_IMR_COUNT (4U)
#define | GPC_ISR_COUNT (4U)
#define | GPC_BASE (0x400F4000u)
#define | GPC ((GPC_Type *)GPC_BASE)
#define | GPC_BASE_ADDRS { GPC_BASE }
#define | GPC_BASE_PTRS { GPC }
#define | GPC_IRQS { GPC_IRQn }
#define | GPIO1_BASE (0x401B8000u)
#define | GPIO1 ((GPIO_Type *)GPIO1_BASE)
#define | GPIO2_BASE (0x401BC000u)
#define | GPIO2 ((GPIO_Type *)GPIO2_BASE)
#define | GPIO3_BASE (0x401C0000u)
#define | GPIO3 ((GPIO_Type *)GPIO3_BASE)
#define | GPIO4_BASE (0x401C4000u)
#define | GPIO4 ((GPIO_Type *)GPIO4_BASE)
#define | GPIO5_BASE (0x400C0000u)
#define | GPIO5 ((GPIO_Type *)GPIO5_BASE)
#define | GPIO6_BASE (0x42000000u)
#define | GPIO6 ((GPIO_Type *)GPIO6_BASE)
#define | GPIO7_BASE (0x42004000u)
#define | GPIO7 ((GPIO_Type *)GPIO7_BASE)
#define | GPIO8_BASE (0x42008000u)
#define | GPIO8 ((GPIO_Type *)GPIO8_BASE)
#define | GPIO9_BASE (0x4200C000u)
#define | GPIO9 ((GPIO_Type *)GPIO9_BASE)
#define | GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE }
#define | GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 }
#define | GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
#define | GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }
#define | GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }
#define | GPT_OCR_COUNT (3U)
#define | GPT_ICR_COUNT (2U)
#define | GPT1_BASE (0x401EC000u)
#define | GPT1 ((GPT_Type *)GPT1_BASE)
#define | GPT2_BASE (0x401F0000u)
#define | GPT2 ((GPT_Type *)GPT2_BASE)
#define | GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }
#define | GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }
#define | GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
#define | I2S_TDR_COUNT (4U)
#define | I2S_TFR_COUNT (4U)
#define | I2S_RDR_COUNT (4U)
#define | I2S_RFR_COUNT (4U)
#define | SAI1_BASE (0x40384000u)
#define | SAI1 ((I2S_Type *)SAI1_BASE)
#define | SAI2_BASE (0x40388000u)
#define | SAI2 ((I2S_Type *)SAI2_BASE)
#define | SAI3_BASE (0x4038C000u)
#define | SAI3 ((I2S_Type *)SAI3_BASE)
#define | I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
#define | I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
#define | I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
#define | I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
#define | IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)
#define | IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)
#define | IOMUXC_SELECT_INPUT_COUNT (154U)
#define | IOMUXC_SW_MUX_CTL_PAD_1_COUNT (22U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_COUNT (22U)
#define | IOMUXC_SELECT_INPUT_1_COUNT (33U)
#define | IOMUXC_BASE (0x401F8000u)
#define | IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
#define | IOMUXC_BASE_ADDRS { IOMUXC_BASE }
#define | IOMUXC_BASE_PTRS { IOMUXC }
#define | IOMUXC_GPR_BASE (0x400AC000u)
#define | IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
#define | IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
#define | IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
#define | IOMUXC_SNVS_BASE (0x400A8000u)
#define | IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
#define | IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
#define | IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
#define | IOMUXC_SNVS_GPR_BASE (0x400A4000u)
#define | IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
#define | IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
#define | IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
#define | KPP_BASE (0x401FC000u)
#define | KPP ((KPP_Type *)KPP_BASE)
#define | KPP_BASE_ADDRS { KPP_BASE }
#define | KPP_BASE_PTRS { KPP }
#define | KPP_IRQS { KPP_IRQn }
#define | LCDIF_PIGEON_0_COUNT (12U)
#define | LCDIF_PIGEON_1_COUNT (12U)
#define | LCDIF_PIGEON_2_COUNT (12U)
#define | LCDIF_BASE (0x402B8000u)
#define | LCDIF ((LCDIF_Type *)LCDIF_BASE)
#define | LCDIF_BASE_ADDRS { LCDIF_BASE }
#define | LCDIF_BASE_PTRS { LCDIF }
#define | LCDIF_IRQ0_IRQS { LCDIF_IRQn }
#define | LPI2C1_BASE (0x403F0000u)
#define | LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
#define | LPI2C2_BASE (0x403F4000u)
#define | LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
#define | LPI2C3_BASE (0x403F8000u)
#define | LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
#define | LPI2C4_BASE (0x403FC000u)
#define | LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
#define | LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
#define | LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
#define | LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
#define | LPSPI1_BASE (0x40394000u)
#define | LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
#define | LPSPI2_BASE (0x40398000u)
#define | LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
#define | LPSPI3_BASE (0x4039C000u)
#define | LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
#define | LPSPI4_BASE (0x403A0000u)
#define | LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
#define | LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
#define | LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
#define | LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
#define | LPUART1_BASE (0x40184000u)
#define | LPUART1 ((LPUART_Type *)LPUART1_BASE)
#define | LPUART2_BASE (0x40188000u)
#define | LPUART2 ((LPUART_Type *)LPUART2_BASE)
#define | LPUART3_BASE (0x4018C000u)
#define | LPUART3 ((LPUART_Type *)LPUART3_BASE)
#define | LPUART4_BASE (0x40190000u)
#define | LPUART4 ((LPUART_Type *)LPUART4_BASE)
#define | LPUART5_BASE (0x40194000u)
#define | LPUART5 ((LPUART_Type *)LPUART5_BASE)
#define | LPUART6_BASE (0x40198000u)
#define | LPUART6 ((LPUART_Type *)LPUART6_BASE)
#define | LPUART7_BASE (0x4019C000u)
#define | LPUART7 ((LPUART_Type *)LPUART7_BASE)
#define | LPUART8_BASE (0x401A0000u)
#define | LPUART8 ((LPUART_Type *)LPUART8_BASE)
#define | LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
#define | LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
#define | LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
#define | OCOTP_BASE (0x401F4000u)
#define | OCOTP ((OCOTP_Type *)OCOTP_BASE)
#define | OCOTP_BASE_ADDRS { OCOTP_BASE }
#define | OCOTP_BASE_PTRS { OCOTP }
#define | PGC_BASE (0x400F4000u)
#define | PGC ((PGC_Type *)PGC_BASE)
#define | PGC_BASE_ADDRS { PGC_BASE }
#define | PGC_BASE_PTRS { PGC }
#define | PIT_LDVAL_COUNT (4U)
#define | PIT_CVAL_COUNT (4U)
#define | PIT_TCTRL_COUNT (4U)
#define | PIT_TFLG_COUNT (4U)
#define | PIT_BASE (0x40084000u)
#define | PIT ((PIT_Type *)PIT_BASE)
#define | PIT_BASE_ADDRS { PIT_BASE }
#define | PIT_BASE_PTRS { PIT }
#define | PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
#define | PMU_BASE (0x400D8000u)
#define | PMU ((PMU_Type *)PMU_BASE)
#define | PMU_BASE_ADDRS { PMU_BASE }
#define | PMU_BASE_PTRS { PMU }
#define | PWM_CNT_COUNT (4U)
#define | PWM_INIT_COUNT (4U)
#define | PWM_CTRL2_COUNT (4U)
#define | PWM_CTRL_COUNT (4U)
#define | PWM_VAL0_COUNT (4U)
#define | PWM_FRACVAL1_COUNT (4U)
#define | PWM_VAL1_COUNT (4U)
#define | PWM_FRACVAL2_COUNT (4U)
#define | PWM_VAL2_COUNT (4U)
#define | PWM_FRACVAL3_COUNT (4U)
#define | PWM_VAL3_COUNT (4U)
#define | PWM_FRACVAL4_COUNT (4U)
#define | PWM_VAL4_COUNT (4U)
#define | PWM_FRACVAL5_COUNT (4U)
#define | PWM_VAL5_COUNT (4U)
#define | PWM_FRCTRL_COUNT (4U)
#define | PWM_OCTRL_COUNT (4U)
#define | PWM_STS_COUNT (4U)
#define | PWM_INTEN_COUNT (4U)
#define | PWM_DMAEN_COUNT (4U)
#define | PWM_TCTRL_COUNT (4U)
#define | PWM_DISMAP_COUNT (4U)
#define | PWM_DISMAP_COUNT2 (2U)
#define | PWM_DTCNT0_COUNT (4U)
#define | PWM_DTCNT1_COUNT (4U)
#define | PWM_CAPTCTRLA_COUNT (4U)
#define | PWM_CAPTCOMPA_COUNT (4U)
#define | PWM_CAPTCTRLB_COUNT (4U)
#define | PWM_CAPTCOMPB_COUNT (4U)
#define | PWM_CAPTCTRLX_COUNT (4U)
#define | PWM_CAPTCOMPX_COUNT (4U)
#define | PWM_CVAL0_COUNT (4U)
#define | PWM_CVAL0CYC_COUNT (4U)
#define | PWM_CVAL1_COUNT (4U)
#define | PWM_CVAL1CYC_COUNT (4U)
#define | PWM_CVAL2_COUNT (4U)
#define | PWM_CVAL2CYC_COUNT (4U)
#define | PWM_CVAL3_COUNT (4U)
#define | PWM_CVAL3CYC_COUNT (4U)
#define | PWM_CVAL4_COUNT (4U)
#define | PWM_CVAL4CYC_COUNT (4U)
#define | PWM_CVAL5_COUNT (4U)
#define | PWM_CVAL5CYC_COUNT (4U)
#define | PWM1_BASE (0x403DC000u)
#define | PWM1 ((PWM_Type *)PWM1_BASE)
#define | PWM2_BASE (0x403E0000u)
#define | PWM2 ((PWM_Type *)PWM2_BASE)
#define | PWM3_BASE (0x403E4000u)
#define | PWM3 ((PWM_Type *)PWM3_BASE)
#define | PWM4_BASE (0x403E8000u)
#define | PWM4 ((PWM_Type *)PWM4_BASE)
#define | PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
#define | PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
#define | PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define | PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define | PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define | PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define | PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define | PXP_BASE (0x402B4000u)
#define | PXP ((PXP_Type *)PXP_BASE)
#define | PXP_BASE_ADDRS { PXP_BASE }
#define | PXP_BASE_PTRS { PXP }
#define | PXP_IRQ0_IRQS { PXP_IRQn }
#define | ROMC_ROMPATCHD_COUNT (8U)
#define | ROMC_ROMPATCHA_COUNT (16U)
#define | ROMC_BASE (0x40180000u)
#define | ROMC ((ROMC_Type *)ROMC_BASE)
#define | ROMC_BASE_ADDRS { ROMC_BASE }
#define | ROMC_BASE_PTRS { ROMC }
#define | RTWDOG_BASE (0x400BC000u)
#define | RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)
#define | RTWDOG_BASE_ADDRS { RTWDOG_BASE }
#define | RTWDOG_BASE_PTRS { RTWDOG }
#define | RTWDOG_IRQS { RTWDOG_IRQn }
#define | RTWDOG_UPDATE_KEY (0xD928C520U)
#define | RTWDOG_REFRESH_KEY (0xB480A602U)
#define | SEMC_BR_COUNT (9U)
#define | SEMC_BASE (0x402F0000u)
#define | SEMC ((SEMC_Type *)SEMC_BASE)
#define | SEMC_BASE_ADDRS { SEMC_BASE }
#define | SEMC_BASE_PTRS { SEMC }
#define | SEMC_IRQS { SEMC_IRQn }
#define | SNVS_LPZMKR_COUNT (8U)
#define | SNVS_LPGPR_ALIAS_COUNT (4U)
#define | SNVS_LPGPR_COUNT (8U)
#define | SNVS_BASE (0x400D4000u)
#define | SNVS ((SNVS_Type *)SNVS_BASE)
#define | SNVS_BASE_ADDRS { SNVS_BASE }
#define | SNVS_BASE_PTRS { SNVS }
#define | SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }
#define | SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }
#define | SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }
#define | SPDIF_BASE (0x40380000u)
#define | SPDIF ((SPDIF_Type *)SPDIF_BASE)
#define | SPDIF_BASE_ADDRS { SPDIF_BASE }
#define | SPDIF_BASE_PTRS { SPDIF }
#define | SPDIF_IRQS { SPDIF_IRQn }
#define | SRC_GPR_COUNT (10U)
#define | SRC_BASE (0x400F8000u)
#define | SRC ((SRC_Type *)SRC_BASE)
#define | SRC_BASE_ADDRS { SRC_BASE }
#define | SRC_BASE_PTRS { SRC }
#define | SRC_IRQS { SRC_IRQn }
#define | SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK
#define | SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT
#define | SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)
#define | SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK
#define | SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT
#define | SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)
#define | SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK
#define | SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT
#define | SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)
#define | SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK
#define | SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT
#define | SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)
#define | SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK
#define | SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT
#define | SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)
#define | SRC_SRSR_W1C_BITS_MASK
#define | TEMPMON_BASE (0x400D8000u)
#define | TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)
#define | TEMPMON_BASE_ADDRS { TEMPMON_BASE }
#define | TEMPMON_BASE_PTRS { TEMPMON }
#define | TMR_COMP1_COUNT (4U)
#define | TMR_COMP2_COUNT (4U)
#define | TMR_CAPT_COUNT (4U)
#define | TMR_LOAD_COUNT (4U)
#define | TMR_HOLD_COUNT (4U)
#define | TMR_CNTR_COUNT (4U)
#define | TMR_CTRL_COUNT (4U)
#define | TMR_SCTRL_COUNT (4U)
#define | TMR_CMPLD1_COUNT (4U)
#define | TMR_CMPLD2_COUNT (4U)
#define | TMR_CSCTRL_COUNT (4U)
#define | TMR_FILT_COUNT (4U)
#define | TMR_DMA_COUNT (4U)
#define | TMR_ENBL_COUNT (4U)
#define | TMR1_BASE (0x401DC000u)
#define | TMR1 ((TMR_Type *)TMR1_BASE)
#define | TMR2_BASE (0x401E0000u)
#define | TMR2 ((TMR_Type *)TMR2_BASE)
#define | TMR3_BASE (0x401E4000u)
#define | TMR3 ((TMR_Type *)TMR3_BASE)
#define | TMR4_BASE (0x401E8000u)
#define | TMR4 ((TMR_Type *)TMR4_BASE)
#define | TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
#define | TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
#define | TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
#define | TRNG_ENT_COUNT (16U)
#define | TRNG_BASE (0x400CC000u)
#define | TRNG ((TRNG_Type *)TRNG_BASE)
#define | TRNG_BASE_ADDRS { TRNG_BASE }
#define | TRNG_BASE_PTRS { TRNG }
#define | TRNG_IRQS { TRNG_IRQn }
#define | TSC_BASE (0x400E0000u)
#define | TSC ((TSC_Type *)TSC_BASE)
#define | TSC_BASE_ADDRS { TSC_BASE }
#define | TSC_BASE_PTRS { TSC }
#define | TSC_IRQS { TSC_DIG_IRQn }
#define | TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_WIRE_4_5_MASK
#define | TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_WIRE_4_5_SHIFT
#define | TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_WIRE_4_5(x)
#define | USB_ENDPTCTRL_COUNT (7U)
#define | USB1_BASE (0x402E0000u)
#define | USB1 ((USB_Type *)USB1_BASE)
#define | USB2_BASE (0x402E0200u)
#define | USB2 ((USB_Type *)USB2_BASE)
#define | USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }
#define | USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }
#define | USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
#define | GPTIMER0CTL GPTIMER0CTRL
#define | GPTIMER1CTL GPTIMER1CTRL
#define | USB_SBUSCFG SBUSCFG
#define | EPLISTADDR ENDPTLISTADDR
#define | EPSETUPSR ENDPTSETUPSTAT
#define | EPPRIME ENDPTPRIME
#define | EPFLUSH ENDPTFLUSH
#define | EPSR ENDPTSTAT
#define | EPCOMPLETE ENDPTCOMPLETE
#define | EPCR ENDPTCTRL
#define | EPCR0 ENDPTCTRL0
#define | USBHS_ID_ID_MASK USB_ID_ID_MASK
#define | USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
#define | USBHS_ID_ID(x) USB_ID_ID(x)
#define | USBHS_ID_NID_MASK USB_ID_NID_MASK
#define | USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
#define | USBHS_ID_NID(x) USB_ID_NID(x)
#define | USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
#define | USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
#define | USBHS_ID_REVISION(x) USB_ID_REVISION(x)
#define | USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
#define | USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
#define | USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
#define | USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
#define | USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
#define | USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
#define | USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
#define | USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
#define | USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
#define | USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
#define | USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
#define | USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
#define | USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
#define | USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
#define | USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
#define | USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
#define | USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
#define | USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
#define | USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
#define | USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
#define | USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
#define | USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
#define | USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
#define | USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
#define | USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
#define | USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
#define | USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
#define | USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
#define | USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
#define | USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
#define | USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
#define | USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
#define | USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
#define | USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
#define | USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
#define | USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
#define | USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
#define | USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
#define | USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
#define | USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
#define | USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
#define | USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
#define | USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
#define | USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
#define | USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
#define | USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
#define | USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
#define | USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
#define | USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
#define | USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
#define | USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
#define | USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
#define | USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
#define | USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
#define | USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
#define | USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
#define | USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
#define | USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
#define | USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
#define | USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
#define | USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
#define | USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
#define | USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
#define | USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
#define | USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
#define | USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
#define | USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
#define | USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
#define | USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
#define | USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
#define | USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
#define | USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
#define | USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
#define | USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
#define | USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
#define | USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
#define | USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
#define | USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
#define | USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
#define | USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
#define | USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
#define | USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
#define | USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
#define | USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
#define | USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
#define | USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
#define | USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
#define | USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
#define | USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
#define | USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
#define | USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
#define | USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
#define | USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
#define | USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
#define | USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
#define | USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
#define | USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
#define | USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
#define | USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
#define | USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
#define | USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
#define | USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
#define | USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
#define | USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
#define | USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
#define | USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
#define | USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
#define | USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
#define | USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
#define | USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
#define | USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
#define | USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
#define | USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
#define | USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
#define | USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
#define | USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
#define | USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
#define | USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
#define | USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
#define | USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
#define | USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
#define | USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
#define | USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
#define | USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
#define | USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
#define | USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
#define | USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
#define | USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
#define | USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
#define | USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
#define | USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
#define | USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
#define | USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
#define | USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
#define | USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
#define | USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
#define | USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
#define | USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
#define | USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
#define | USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
#define | USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
#define | USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
#define | USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
#define | USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
#define | USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
#define | USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
#define | USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
#define | USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
#define | USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
#define | USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
#define | USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
#define | USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
#define | USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
#define | USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
#define | USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
#define | USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
#define | USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
#define | USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
#define | USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
#define | USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
#define | USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
#define | USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
#define | USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
#define | USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
#define | USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
#define | USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
#define | USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
#define | USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
#define | USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
#define | USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
#define | USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
#define | USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
#define | USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
#define | USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
#define | USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
#define | USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
#define | USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
#define | USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
#define | USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
#define | USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
#define | USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
#define | USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
#define | USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
#define | USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
#define | USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
#define | USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
#define | USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
#define | USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
#define | USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
#define | USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
#define | USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
#define | USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
#define | USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
#define | USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
#define | USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
#define | USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
#define | USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
#define | USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
#define | USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
#define | USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
#define | USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
#define | USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
#define | USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
#define | USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
#define | USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
#define | USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
#define | USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
#define | USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
#define | USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
#define | USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
#define | USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
#define | USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
#define | USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
#define | USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
#define | USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
#define | USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
#define | USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
#define | USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
#define | USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
#define | USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
#define | USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
#define | USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
#define | USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
#define | USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
#define | USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
#define | USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
#define | USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
#define | USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
#define | USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
#define | USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
#define | USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
#define | USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
#define | USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
#define | USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
#define | USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
#define | USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
#define | USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
#define | USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
#define | USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
#define | USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
#define | USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
#define | USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
#define | USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
#define | USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
#define | USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
#define | USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
#define | USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
#define | USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
#define | USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
#define | USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
#define | USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
#define | USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
#define | USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
#define | USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
#define | USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
#define | USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
#define | USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
#define | USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
#define | USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
#define | USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
#define | USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
#define | USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
#define | USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
#define | USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
#define | USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
#define | USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
#define | USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
#define | USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
#define | USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
#define | USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
#define | USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
#define | USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
#define | USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
#define | USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
#define | USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
#define | USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
#define | USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
#define | USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
#define | USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
#define | USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
#define | USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
#define | USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
#define | USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
#define | USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
#define | USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
#define | USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
#define | USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
#define | USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
#define | USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
#define | USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
#define | USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
#define | USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
#define | USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
#define | USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
#define | USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
#define | USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
#define | USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
#define | USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
#define | USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
#define | USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
#define | USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
#define | USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
#define | USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
#define | USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
#define | USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
#define | USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
#define | USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
#define | USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
#define | USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
#define | USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
#define | USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
#define | USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
#define | USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
#define | USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
#define | USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
#define | USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
#define | USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
#define | USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
#define | USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
#define | USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
#define | USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
#define | USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
#define | USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
#define | USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
#define | USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
#define | USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
#define | USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
#define | USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
#define | USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
#define | USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
#define | USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
#define | USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
#define | USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
#define | USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
#define | USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
#define | USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
#define | USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
#define | USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
#define | USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
#define | USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
#define | USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
#define | USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
#define | USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
#define | USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
#define | USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
#define | USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
#define | USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
#define | USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
#define | USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
#define | USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
#define | USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
#define | USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
#define | USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
#define | USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
#define | USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
#define | USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
#define | USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
#define | USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
#define | USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
#define | USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
#define | USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
#define | USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
#define | USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
#define | USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
#define | USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
#define | USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
#define | USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
#define | USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
#define | USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
#define | USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
#define | USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
#define | USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
#define | USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
#define | USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
#define | USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
#define | USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
#define | USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
#define | USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
#define | USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
#define | USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
#define | USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
#define | USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
#define | USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
#define | USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
#define | USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
#define | USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
#define | USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
#define | USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
#define | USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
#define | USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
#define | USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
#define | USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
#define | USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
#define | USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
#define | USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
#define | USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
#define | USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
#define | USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
#define | USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
#define | USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
#define | USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
#define | USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
#define | USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
#define | USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
#define | USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
#define | USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
#define | USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
#define | USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
#define | USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
#define | USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
#define | USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
#define | USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
#define | USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
#define | USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
#define | USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
#define | USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
#define | USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
#define | USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
#define | USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
#define | USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
#define | USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
#define | USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
#define | USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
#define | USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
#define | USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
#define | USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
#define | USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
#define | USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
#define | USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
#define | USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
#define | USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
#define | USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
#define | USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
#define | USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
#define | USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
#define | USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
#define | USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
#define | USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
#define | USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
#define | USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
#define | USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
#define | USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
#define | USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
#define | USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
#define | USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
#define | USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
#define | USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
#define | USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
#define | USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
#define | USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
#define | USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
#define | USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
#define | USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
#define | USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
#define | USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
#define | USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
#define | USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
#define | USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
#define | USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
#define | USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
#define | USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
#define | USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
#define | USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
#define | USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
#define | USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
#define | USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
#define | USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
#define | USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
#define | USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
#define | USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
#define | USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
#define | USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
#define | USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
#define | USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
#define | USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
#define | USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
#define | USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
#define | USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
#define | USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
#define | USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
#define | USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
#define | USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
#define | USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
#define | USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
#define | USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
#define | USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
#define | USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
#define | USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
#define | USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
#define | USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
#define | USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
#define | USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
#define | USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
#define | USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
#define | USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
#define | USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
#define | USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
#define | USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
#define | USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
#define | USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
#define | USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
#define | USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
#define | USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
#define | USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
#define | USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
#define | USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
#define | USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
#define | USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
#define | USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
#define | USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
#define | USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
#define | USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
#define | USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
#define | USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
#define | USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
#define | USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
#define | USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
#define | USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
#define | USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
#define | USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
#define | USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
#define | USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
#define | USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
#define | USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
#define | USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
#define | USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
#define | USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
#define | USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
#define | USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
#define | USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
#define | USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
#define | USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
#define | USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
#define | USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
#define | USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
#define | USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
#define | USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
#define | USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
#define | USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
#define | USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
#define | USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
#define | USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
#define | USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
#define | USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
#define | USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
#define | USBHS_Type USB_Type
#define | USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE }
#define | USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
#define | USBHS_IRQHandler USB_OTG1_IRQHandler
#define | USBNC1_BASE (0x402E0000u)
#define | USBNC1 ((USBNC_Type *)USBNC1_BASE)
#define | USBNC2_BASE (0x402E0004u)
#define | USBNC2 ((USBNC_Type *)USBNC2_BASE)
#define | USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }
#define | USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }
#define | USBPHY1_BASE (0x400D9000u)
#define | USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
#define | USBPHY2_BASE (0x400DA000u)
#define | USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
#define | USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
#define | USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
#define | USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
#define | USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define | USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define | USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define | USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
#define | USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
#define | USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
#define | USB_ANALOG_VBUS_DETECT_COUNT (2U)
#define | USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)
#define | USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)
#define | USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)
#define | USB_ANALOG_CHRG_DETECT_COUNT (2U)
#define | USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)
#define | USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)
#define | USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)
#define | USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)
#define | USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)
#define | USB_ANALOG_LOOPBACK_COUNT (2U)
#define | USB_ANALOG_LOOPBACK_SET_COUNT (2U)
#define | USB_ANALOG_LOOPBACK_CLR_COUNT (2U)
#define | USB_ANALOG_LOOPBACK_TOG_COUNT (2U)
#define | USB_ANALOG_MISC_COUNT (2U)
#define | USB_ANALOG_MISC_SET_COUNT (2U)
#define | USB_ANALOG_MISC_CLR_COUNT (2U)
#define | USB_ANALOG_MISC_TOG_COUNT (2U)
#define | USB_ANALOG_BASE (0x400D8000u)
#define | USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)
#define | USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }
#define | USB_ANALOG_BASE_PTRS { USB_ANALOG }
#define | USDHC1_BASE (0x402C0000u)
#define | USDHC1 ((USDHC_Type *)USDHC1_BASE)
#define | USDHC2_BASE (0x402C4000u)
#define | USDHC2 ((USDHC_Type *)USDHC2_BASE)
#define | USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
#define | USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
#define | USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
#define | WDOG1_BASE (0x400B8000u)
#define | WDOG1 ((WDOG_Type *)WDOG1_BASE)
#define | WDOG2_BASE (0x400D0000u)
#define | WDOG2 ((WDOG_Type *)WDOG2_BASE)
#define | WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
#define | WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
#define | WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
#define | XBARA1_BASE (0x403BC000u)
#define | XBARA1 ((XBARA_Type *)XBARA1_BASE)
#define | XBARA_BASE_ADDRS { XBARA1_BASE }
#define | XBARA_BASE_PTRS { XBARA1 }
#define | XBARB2_BASE (0x403C0000u)
#define | XBARB2 ((XBARB_Type *)XBARB2_BASE)
#define | XBARB3_BASE (0x403C4000u)
#define | XBARB3 ((XBARB_Type *)XBARB3_BASE)
#define | XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
#define | XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
#define | XTALOSC24M_BASE (0x400D8000u)
#define | XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)
#define | XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }
#define | XTALOSC24M_BASE_PTRS { XTALOSC24M }
#define | NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
| Mask and left-shift a bit field value for use in a register bit range. More...
#define | NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
| Mask and right-shift a register value to extract a bit field value. More...
HC - Control register for hardware triggers
#define | ADC_HC_ADCH_MASK (0x1FU)
#define | ADC_HC_ADCH_SHIFT (0U)
#define | ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
#define | ADC_HC_AIEN_MASK (0x80U)
#define | ADC_HC_AIEN_SHIFT (7U)
#define | ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
HS - Status register for HW triggers
#define | ADC_HS_COCO0_MASK (0x1U)
#define | ADC_HS_COCO0_SHIFT (0U)
#define | ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
R - Data result register for HW triggers
#define | ADC_R_CDATA_MASK (0xFFFU)
#define | ADC_R_CDATA_SHIFT (0U)
#define | ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
CFG - Configuration register
#define | ADC_CFG_ADICLK_MASK (0x3U)
#define | ADC_CFG_ADICLK_SHIFT (0U)
#define | ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
#define | ADC_CFG_MODE_MASK (0xCU)
#define | ADC_CFG_MODE_SHIFT (2U)
#define | ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
#define | ADC_CFG_ADLSMP_MASK (0x10U)
#define | ADC_CFG_ADLSMP_SHIFT (4U)
#define | ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
#define | ADC_CFG_ADIV_MASK (0x60U)
#define | ADC_CFG_ADIV_SHIFT (5U)
#define | ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
#define | ADC_CFG_ADLPC_MASK (0x80U)
#define | ADC_CFG_ADLPC_SHIFT (7U)
#define | ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
#define | ADC_CFG_ADSTS_MASK (0x300U)
#define | ADC_CFG_ADSTS_SHIFT (8U)
#define | ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
#define | ADC_CFG_ADHSC_MASK (0x400U)
#define | ADC_CFG_ADHSC_SHIFT (10U)
#define | ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
#define | ADC_CFG_REFSEL_MASK (0x1800U)
#define | ADC_CFG_REFSEL_SHIFT (11U)
#define | ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define | ADC_CFG_ADTRG_MASK (0x2000U)
#define | ADC_CFG_ADTRG_SHIFT (13U)
#define | ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
#define | ADC_CFG_AVGS_MASK (0xC000U)
#define | ADC_CFG_AVGS_SHIFT (14U)
#define | ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
#define | ADC_CFG_OVWREN_MASK (0x10000U)
#define | ADC_CFG_OVWREN_SHIFT (16U)
#define | ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
GC - General control register
#define | ADC_GC_ADACKEN_MASK (0x1U)
#define | ADC_GC_ADACKEN_SHIFT (0U)
#define | ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
#define | ADC_GC_DMAEN_MASK (0x2U)
#define | ADC_GC_DMAEN_SHIFT (1U)
#define | ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
#define | ADC_GC_ACREN_MASK (0x4U)
#define | ADC_GC_ACREN_SHIFT (2U)
#define | ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
#define | ADC_GC_ACFGT_MASK (0x8U)
#define | ADC_GC_ACFGT_SHIFT (3U)
#define | ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
#define | ADC_GC_ACFE_MASK (0x10U)
#define | ADC_GC_ACFE_SHIFT (4U)
#define | ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
#define | ADC_GC_AVGE_MASK (0x20U)
#define | ADC_GC_AVGE_SHIFT (5U)
#define | ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
#define | ADC_GC_ADCO_MASK (0x40U)
#define | ADC_GC_ADCO_SHIFT (6U)
#define | ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
#define | ADC_GC_CAL_MASK (0x80U)
#define | ADC_GC_CAL_SHIFT (7U)
#define | ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
GS - General status register
#define | ADC_GS_ADACT_MASK (0x1U)
#define | ADC_GS_ADACT_SHIFT (0U)
#define | ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
#define | ADC_GS_CALF_MASK (0x2U)
#define | ADC_GS_CALF_SHIFT (1U)
#define | ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
#define | ADC_GS_AWKST_MASK (0x4U)
#define | ADC_GS_AWKST_SHIFT (2U)
#define | ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
CV - Compare value register
#define | ADC_CV_CV1_MASK (0xFFFU)
#define | ADC_CV_CV1_SHIFT (0U)
#define | ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
#define | ADC_CV_CV2_MASK (0xFFF0000U)
#define | ADC_CV_CV2_SHIFT (16U)
#define | ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
OFS - Offset correction value register
#define | ADC_OFS_OFS_MASK (0xFFFU)
#define | ADC_OFS_OFS_SHIFT (0U)
#define | ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
#define | ADC_OFS_SIGN_MASK (0x1000U)
#define | ADC_OFS_SIGN_SHIFT (12U)
#define | ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
CAL - Calibration value register
#define | ADC_CAL_CAL_CODE_MASK (0xFU)
#define | ADC_CAL_CAL_CODE_SHIFT (0U)
#define | ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
CTRL - ADC_ETC Global Control Register
#define | ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
#define | ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
#define | ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
#define | ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
#define | ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
#define | ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
#define | ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
#define | ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
#define | ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
#define | ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
#define | ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
#define | ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
#define | ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
#define | ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
#define | ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
#define | ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
#define | ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
#define | ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
#define | ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
#define | ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
#define | ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
#define | ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
#define | ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
#define | ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
#define | ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
#define | ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
#define | ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
#define | ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
DMA_CTRL - ETC DMA control Register
#define | ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
#define | ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
#define | ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
#define | ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
#define | ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
#define | ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
#define | ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
#define | ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
#define | ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
#define | ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
#define | ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
#define | ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
#define | ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
#define | ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
#define | ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
#define | ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
#define | ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
#define | ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
#define | ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
#define | ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
#define | ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
#define | ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
#define | ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
#define | ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
#define | ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
#define | ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
#define | ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
#define | ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
#define | ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
#define | ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
#define | ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
#define | ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
#define | ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
#define | ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register
#define | ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
#define | ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
#define | ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
#define | ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
#define | ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
#define | ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
#define | ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
#define | ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
#define | ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
#define | ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
#define | ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
#define | ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
#define | ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
#define | ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
#define | ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register
#define | ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
#define | ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
#define | ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
#define | ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
#define | ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
#define | ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
MPR - Master Priviledge Registers
#define | AIPSTZ_MPR_MPROT5_MASK (0xF00U)
#define | AIPSTZ_MPR_MPROT5_SHIFT (8U)
#define | AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
#define | AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
#define | AIPSTZ_MPR_MPROT3_SHIFT (16U)
#define | AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
#define | AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
#define | AIPSTZ_MPR_MPROT2_SHIFT (20U)
#define | AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
#define | AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
#define | AIPSTZ_MPR_MPROT1_SHIFT (24U)
#define | AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
#define | AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
#define | AIPSTZ_MPR_MPROT0_SHIFT (28U)
#define | AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
OPACR - Off-Platform Peripheral Access Control Registers
#define | AIPSTZ_OPACR_OPAC7_MASK (0xFU)
#define | AIPSTZ_OPACR_OPAC7_SHIFT (0U)
#define | AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
#define | AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
#define | AIPSTZ_OPACR_OPAC6_SHIFT (4U)
#define | AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
#define | AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
#define | AIPSTZ_OPACR_OPAC5_SHIFT (8U)
#define | AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
#define | AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
#define | AIPSTZ_OPACR_OPAC4_SHIFT (12U)
#define | AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
#define | AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
#define | AIPSTZ_OPACR_OPAC3_SHIFT (16U)
#define | AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
#define | AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
#define | AIPSTZ_OPACR_OPAC2_SHIFT (20U)
#define | AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
#define | AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
#define | AIPSTZ_OPACR_OPAC1_SHIFT (24U)
#define | AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
#define | AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
#define | AIPSTZ_OPACR_OPAC0_SHIFT (28U)
#define | AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
OPACR1 - Off-Platform Peripheral Access Control Registers
#define | AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
#define | AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
#define | AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
#define | AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
#define | AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
#define | AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
#define | AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
#define | AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
#define | AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
#define | AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
#define | AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
#define | AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
#define | AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
#define | AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
#define | AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
#define | AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
#define | AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
#define | AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
#define | AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
#define | AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
#define | AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
#define | AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
#define | AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
#define | AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
OPACR2 - Off-Platform Peripheral Access Control Registers
#define | AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
#define | AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
#define | AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
#define | AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
#define | AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
#define | AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
#define | AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
#define | AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
#define | AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
#define | AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
#define | AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
#define | AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
#define | AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
#define | AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
#define | AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
#define | AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
#define | AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
#define | AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
#define | AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
#define | AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
#define | AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
#define | AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
#define | AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
#define | AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
OPACR3 - Off-Platform Peripheral Access Control Registers
#define | AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
#define | AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
#define | AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
#define | AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
#define | AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
#define | AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
#define | AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
#define | AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
#define | AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
#define | AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
#define | AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
#define | AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
#define | AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
#define | AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
#define | AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
#define | AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
#define | AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
#define | AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
#define | AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
#define | AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
#define | AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
#define | AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
#define | AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
#define | AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
OPACR4 - Off-Platform Peripheral Access Control Registers
#define | AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
#define | AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
#define | AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
#define | AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
#define | AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
#define | AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn
#define | AOI_BFCRT01_PT1_DC_MASK (0x3U)
#define | AOI_BFCRT01_PT1_DC_SHIFT (0U)
#define | AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
#define | AOI_BFCRT01_PT1_CC_MASK (0xCU)
#define | AOI_BFCRT01_PT1_CC_SHIFT (2U)
#define | AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
#define | AOI_BFCRT01_PT1_BC_MASK (0x30U)
#define | AOI_BFCRT01_PT1_BC_SHIFT (4U)
#define | AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
#define | AOI_BFCRT01_PT1_AC_MASK (0xC0U)
#define | AOI_BFCRT01_PT1_AC_SHIFT (6U)
#define | AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
#define | AOI_BFCRT01_PT0_DC_MASK (0x300U)
#define | AOI_BFCRT01_PT0_DC_SHIFT (8U)
#define | AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
#define | AOI_BFCRT01_PT0_CC_MASK (0xC00U)
#define | AOI_BFCRT01_PT0_CC_SHIFT (10U)
#define | AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
#define | AOI_BFCRT01_PT0_BC_MASK (0x3000U)
#define | AOI_BFCRT01_PT0_BC_SHIFT (12U)
#define | AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
#define | AOI_BFCRT01_PT0_AC_MASK (0xC000U)
#define | AOI_BFCRT01_PT0_AC_SHIFT (14U)
#define | AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn
#define | AOI_BFCRT23_PT3_DC_MASK (0x3U)
#define | AOI_BFCRT23_PT3_DC_SHIFT (0U)
#define | AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
#define | AOI_BFCRT23_PT3_CC_MASK (0xCU)
#define | AOI_BFCRT23_PT3_CC_SHIFT (2U)
#define | AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
#define | AOI_BFCRT23_PT3_BC_MASK (0x30U)
#define | AOI_BFCRT23_PT3_BC_SHIFT (4U)
#define | AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
#define | AOI_BFCRT23_PT3_AC_MASK (0xC0U)
#define | AOI_BFCRT23_PT3_AC_SHIFT (6U)
#define | AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
#define | AOI_BFCRT23_PT2_DC_MASK (0x300U)
#define | AOI_BFCRT23_PT2_DC_SHIFT (8U)
#define | AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
#define | AOI_BFCRT23_PT2_CC_MASK (0xC00U)
#define | AOI_BFCRT23_PT2_CC_SHIFT (10U)
#define | AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
#define | AOI_BFCRT23_PT2_BC_MASK (0x3000U)
#define | AOI_BFCRT23_PT2_BC_SHIFT (12U)
#define | AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
#define | AOI_BFCRT23_PT2_AC_MASK (0xC000U)
#define | AOI_BFCRT23_PT2_AC_SHIFT (14U)
#define | AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
CTRL - Control Register
#define | BEE_CTRL_BEE_ENABLE_MASK (0x1U)
#define | BEE_CTRL_BEE_ENABLE_SHIFT (0U)
#define | BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
#define | BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
#define | BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
#define | BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
#define | BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
#define | BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
#define | BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
#define | BEE_CTRL_KEY_VALID_MASK (0x10U)
#define | BEE_CTRL_KEY_VALID_SHIFT (4U)
#define | BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
#define | BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
#define | BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
#define | BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
#define | BEE_CTRL_AC_PROT_EN_MASK (0x40U)
#define | BEE_CTRL_AC_PROT_EN_SHIFT (6U)
#define | BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
#define | BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
#define | BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
#define | BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
#define | BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
#define | BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
#define | BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
#define | BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
#define | BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
#define | BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
#define | BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
#define | BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
#define | BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
#define | BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
#define | BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
#define | BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
#define | BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
#define | BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
#define | BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
#define | BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
#define | BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
#define | BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
#define | BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
#define | BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
#define | BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
#define | BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
#define | BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
#define | BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
#define | BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
#define | BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
#define | BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
#define | BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
#define | BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
#define | BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
#define | BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
#define | BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
#define | BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
#define | BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
#define | BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
#define | BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
#define | BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
#define | BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
#define | BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
#define | BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
#define | BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
#define | BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
#define | BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
#define | BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
#define | BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
#define | BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
#define | BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
#define | BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
#define | BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
#define | BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
#define | BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
#define | BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
#define | BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
#define | BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
#define | ENC_CTRL_CMPIE_MASK (0x1U)
#define | ENC_CTRL_CMPIE_SHIFT (0U)
#define | ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
#define | ENC_CTRL_CMPIRQ_MASK (0x2U)
#define | ENC_CTRL_CMPIRQ_SHIFT (1U)
#define | ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
#define | ENC_CTRL_WDE_MASK (0x4U)
#define | ENC_CTRL_WDE_SHIFT (2U)
#define | ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
#define | ENC_CTRL_DIE_MASK (0x8U)
#define | ENC_CTRL_DIE_SHIFT (3U)
#define | ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
#define | ENC_CTRL_DIRQ_MASK (0x10U)
#define | ENC_CTRL_DIRQ_SHIFT (4U)
#define | ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
#define | ENC_CTRL_XNE_MASK (0x20U)
#define | ENC_CTRL_XNE_SHIFT (5U)
#define | ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
#define | ENC_CTRL_XIP_MASK (0x40U)
#define | ENC_CTRL_XIP_SHIFT (6U)
#define | ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
#define | ENC_CTRL_XIE_MASK (0x80U)
#define | ENC_CTRL_XIE_SHIFT (7U)
#define | ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
#define | ENC_CTRL_XIRQ_MASK (0x100U)
#define | ENC_CTRL_XIRQ_SHIFT (8U)
#define | ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
#define | ENC_CTRL_PH1_MASK (0x200U)
#define | ENC_CTRL_PH1_SHIFT (9U)
#define | ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
#define | ENC_CTRL_REV_MASK (0x400U)
#define | ENC_CTRL_REV_SHIFT (10U)
#define | ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
#define | ENC_CTRL_SWIP_MASK (0x800U)
#define | ENC_CTRL_SWIP_SHIFT (11U)
#define | ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
#define | ENC_CTRL_HNE_MASK (0x1000U)
#define | ENC_CTRL_HNE_SHIFT (12U)
#define | ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
#define | ENC_CTRL_HIP_MASK (0x2000U)
#define | ENC_CTRL_HIP_SHIFT (13U)
#define | ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
#define | ENC_CTRL_HIE_MASK (0x4000U)
#define | ENC_CTRL_HIE_SHIFT (14U)
#define | ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
#define | ENC_CTRL_HIRQ_MASK (0x8000U)
#define | ENC_CTRL_HIRQ_SHIFT (15U)
#define | ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
#define | EWM_CTRL_EWMEN_MASK (0x1U)
#define | EWM_CTRL_EWMEN_SHIFT (0U)
#define | EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
#define | EWM_CTRL_ASSIN_MASK (0x2U)
#define | EWM_CTRL_ASSIN_SHIFT (1U)
#define | EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
#define | EWM_CTRL_INEN_MASK (0x4U)
#define | EWM_CTRL_INEN_SHIFT (2U)
#define | EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
#define | EWM_CTRL_INTEN_MASK (0x8U)
#define | EWM_CTRL_INTEN_SHIFT (3U)
#define | EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
#define | PWM_CTRL_DBLEN_MASK (0x1U)
#define | PWM_CTRL_DBLEN_SHIFT (0U)
#define | PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
#define | PWM_CTRL_DBLX_MASK (0x2U)
#define | PWM_CTRL_DBLX_SHIFT (1U)
#define | PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
#define | PWM_CTRL_LDMOD_MASK (0x4U)
#define | PWM_CTRL_LDMOD_SHIFT (2U)
#define | PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
#define | PWM_CTRL_SPLIT_MASK (0x8U)
#define | PWM_CTRL_SPLIT_SHIFT (3U)
#define | PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
#define | PWM_CTRL_PRSC_MASK (0x70U)
#define | PWM_CTRL_PRSC_SHIFT (4U)
#define | PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
#define | PWM_CTRL_COMPMODE_MASK (0x80U)
#define | PWM_CTRL_COMPMODE_SHIFT (7U)
#define | PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
#define | PWM_CTRL_DT_MASK (0x300U)
#define | PWM_CTRL_DT_SHIFT (8U)
#define | PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
#define | PWM_CTRL_FULL_MASK (0x400U)
#define | PWM_CTRL_FULL_SHIFT (10U)
#define | PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
#define | PWM_CTRL_HALF_MASK (0x800U)
#define | PWM_CTRL_HALF_SHIFT (11U)
#define | PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
#define | PWM_CTRL_LDFQ_MASK (0xF000U)
#define | PWM_CTRL_LDFQ_SHIFT (12U)
#define | PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
ADDR_OFFSET0 - Offset region 0 Register
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
#define | BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
ADDR_OFFSET1 - Offset region 1 Register
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
#define | BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
AES_KEY0_W0 - AES Key 0 Register
#define | BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
#define | BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
#define | BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
AES_KEY0_W1 - AES Key 1 Register
#define | BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
#define | BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
#define | BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
AES_KEY0_W2 - AES Key 2 Register
#define | BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
#define | BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
#define | BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
AES_KEY0_W3 - AES Key 3 Register
#define | BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
#define | BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
#define | BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
STATUS - Status Register
#define | BEE_STATUS_IRQ_VEC_MASK (0xFFU)
#define | BEE_STATUS_IRQ_VEC_SHIFT (0U)
#define | BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
#define | BEE_STATUS_BEE_IDLE_MASK (0x100U)
#define | BEE_STATUS_BEE_IDLE_SHIFT (8U)
#define | BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
#define | TRNG_STATUS_TF1BR0_MASK (0x1U)
#define | TRNG_STATUS_TF1BR0_SHIFT (0U)
#define | TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
#define | TRNG_STATUS_TF1BR1_MASK (0x2U)
#define | TRNG_STATUS_TF1BR1_SHIFT (1U)
#define | TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
#define | TRNG_STATUS_TF2BR0_MASK (0x4U)
#define | TRNG_STATUS_TF2BR0_SHIFT (2U)
#define | TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
#define | TRNG_STATUS_TF2BR1_MASK (0x8U)
#define | TRNG_STATUS_TF2BR1_SHIFT (3U)
#define | TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
#define | TRNG_STATUS_TF3BR0_MASK (0x10U)
#define | TRNG_STATUS_TF3BR0_SHIFT (4U)
#define | TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
#define | TRNG_STATUS_TF3BR1_MASK (0x20U)
#define | TRNG_STATUS_TF3BR1_SHIFT (5U)
#define | TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
#define | TRNG_STATUS_TF4BR0_MASK (0x40U)
#define | TRNG_STATUS_TF4BR0_SHIFT (6U)
#define | TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
#define | TRNG_STATUS_TF4BR1_MASK (0x80U)
#define | TRNG_STATUS_TF4BR1_SHIFT (7U)
#define | TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
#define | TRNG_STATUS_TF5BR0_MASK (0x100U)
#define | TRNG_STATUS_TF5BR0_SHIFT (8U)
#define | TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
#define | TRNG_STATUS_TF5BR1_MASK (0x200U)
#define | TRNG_STATUS_TF5BR1_SHIFT (9U)
#define | TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
#define | TRNG_STATUS_TF6PBR0_MASK (0x400U)
#define | TRNG_STATUS_TF6PBR0_SHIFT (10U)
#define | TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
#define | TRNG_STATUS_TF6PBR1_MASK (0x800U)
#define | TRNG_STATUS_TF6PBR1_SHIFT (11U)
#define | TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
#define | TRNG_STATUS_TFSB_MASK (0x1000U)
#define | TRNG_STATUS_TFSB_SHIFT (12U)
#define | TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
#define | TRNG_STATUS_TFLR_MASK (0x2000U)
#define | TRNG_STATUS_TFLR_SHIFT (13U)
#define | TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
#define | TRNG_STATUS_TFP_MASK (0x4000U)
#define | TRNG_STATUS_TFP_SHIFT (14U)
#define | TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
#define | TRNG_STATUS_TFMB_MASK (0x8000U)
#define | TRNG_STATUS_TFMB_SHIFT (15U)
#define | TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
#define | TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
#define | TRNG_STATUS_RETRY_CT_SHIFT (16U)
#define | TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
CTR_NONCE0_W0 - NONCE00 Register
#define | BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
#define | BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
CTR_NONCE0_W1 - NONCE01 Register
#define | BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
#define | BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
CTR_NONCE0_W2 - NONCE02 Register
#define | BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
#define | BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
CTR_NONCE0_W3 - NONCE03 Register
#define | BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
#define | BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
CTR_NONCE1_W0 - NONCE10 Register
#define | BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
#define | BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
CTR_NONCE1_W1 - NONCE11 Register
#define | BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
#define | BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
CTR_NONCE1_W2 - NONCE12 Register
#define | BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
#define | BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
CTR_NONCE1_W3 - NONCE13 Register
#define | BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
#define | BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
#define | BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
REGION1_TOP - Region1 Top Address Register
#define | BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
#define | BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
#define | BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
REGION1_BOT - Region1 Bottom Address Register
#define | BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
#define | BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
#define | BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
MCR - Module Configuration Register
#define | CAN_MCR_MAXMB_MASK (0x7FU)
#define | CAN_MCR_MAXMB_SHIFT (0U)
#define | CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
#define | CAN_MCR_IDAM_MASK (0x300U)
#define | CAN_MCR_IDAM_SHIFT (8U)
#define | CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
#define | CAN_MCR_FDEN_MASK (0x800U)
#define | CAN_MCR_FDEN_SHIFT (11U)
#define | CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
#define | CAN_MCR_AEN_MASK (0x1000U)
#define | CAN_MCR_AEN_SHIFT (12U)
#define | CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
#define | CAN_MCR_LPRIOEN_MASK (0x2000U)
#define | CAN_MCR_LPRIOEN_SHIFT (13U)
#define | CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
#define | CAN_MCR_DMA_MASK (0x8000U)
#define | CAN_MCR_DMA_SHIFT (15U)
#define | CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
#define | CAN_MCR_IRMQ_MASK (0x10000U)
#define | CAN_MCR_IRMQ_SHIFT (16U)
#define | CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
#define | CAN_MCR_SRXDIS_MASK (0x20000U)
#define | CAN_MCR_SRXDIS_SHIFT (17U)
#define | CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
#define | CAN_MCR_DOZE_MASK (0x40000U)
#define | CAN_MCR_DOZE_SHIFT (18U)
#define | CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
#define | CAN_MCR_WAKSRC_MASK (0x80000U)
#define | CAN_MCR_WAKSRC_SHIFT (19U)
#define | CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
#define | CAN_MCR_LPMACK_MASK (0x100000U)
#define | CAN_MCR_LPMACK_SHIFT (20U)
#define | CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
#define | CAN_MCR_WRNEN_MASK (0x200000U)
#define | CAN_MCR_WRNEN_SHIFT (21U)
#define | CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
#define | CAN_MCR_SLFWAK_MASK (0x400000U)
#define | CAN_MCR_SLFWAK_SHIFT (22U)
#define | CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
#define | CAN_MCR_SUPV_MASK (0x800000U)
#define | CAN_MCR_SUPV_SHIFT (23U)
#define | CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
#define | CAN_MCR_FRZACK_MASK (0x1000000U)
#define | CAN_MCR_FRZACK_SHIFT (24U)
#define | CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
#define | CAN_MCR_SOFTRST_MASK (0x2000000U)
#define | CAN_MCR_SOFTRST_SHIFT (25U)
#define | CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
#define | CAN_MCR_WAKMSK_MASK (0x4000000U)
#define | CAN_MCR_WAKMSK_SHIFT (26U)
#define | CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
#define | CAN_MCR_NOTRDY_MASK (0x8000000U)
#define | CAN_MCR_NOTRDY_SHIFT (27U)
#define | CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
#define | CAN_MCR_HALT_MASK (0x10000000U)
#define | CAN_MCR_HALT_SHIFT (28U)
#define | CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
#define | CAN_MCR_RFEN_MASK (0x20000000U)
#define | CAN_MCR_RFEN_SHIFT (29U)
#define | CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
#define | CAN_MCR_FRZ_MASK (0x40000000U)
#define | CAN_MCR_FRZ_SHIFT (30U)
#define | CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
#define | CAN_MCR_MDIS_MASK (0x80000000U)
#define | CAN_MCR_MDIS_SHIFT (31U)
#define | CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
CTRL1 - Control 1 Register..Control 1 register
#define | CAN_CTRL1_PROPSEG_MASK (0x7U)
#define | CAN_CTRL1_PROPSEG_SHIFT (0U)
#define | CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
#define | CAN_CTRL1_LOM_MASK (0x8U)
#define | CAN_CTRL1_LOM_SHIFT (3U)
#define | CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
#define | CAN_CTRL1_LBUF_MASK (0x10U)
#define | CAN_CTRL1_LBUF_SHIFT (4U)
#define | CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
#define | CAN_CTRL1_TSYN_MASK (0x20U)
#define | CAN_CTRL1_TSYN_SHIFT (5U)
#define | CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
#define | CAN_CTRL1_BOFFREC_MASK (0x40U)
#define | CAN_CTRL1_BOFFREC_SHIFT (6U)
#define | CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
#define | CAN_CTRL1_SMP_MASK (0x80U)
#define | CAN_CTRL1_SMP_SHIFT (7U)
#define | CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
#define | CAN_CTRL1_RWRNMSK_MASK (0x400U)
#define | CAN_CTRL1_RWRNMSK_SHIFT (10U)
#define | CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
#define | CAN_CTRL1_TWRNMSK_MASK (0x800U)
#define | CAN_CTRL1_TWRNMSK_SHIFT (11U)
#define | CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
#define | CAN_CTRL1_LPB_MASK (0x1000U)
#define | CAN_CTRL1_LPB_SHIFT (12U)
#define | CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
#define | CAN_CTRL1_CLKSRC_MASK (0x2000U)
#define | CAN_CTRL1_CLKSRC_SHIFT (13U)
#define | CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
#define | CAN_CTRL1_ERRMSK_MASK (0x4000U)
#define | CAN_CTRL1_ERRMSK_SHIFT (14U)
#define | CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
#define | CAN_CTRL1_BOFFMSK_MASK (0x8000U)
#define | CAN_CTRL1_BOFFMSK_SHIFT (15U)
#define | CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
#define | CAN_CTRL1_PSEG2_MASK (0x70000U)
#define | CAN_CTRL1_PSEG2_SHIFT (16U)
#define | CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
#define | CAN_CTRL1_PSEG1_MASK (0x380000U)
#define | CAN_CTRL1_PSEG1_SHIFT (19U)
#define | CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
#define | CAN_CTRL1_RJW_MASK (0xC00000U)
#define | CAN_CTRL1_RJW_SHIFT (22U)
#define | CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
#define | CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
#define | CAN_CTRL1_PRESDIV_SHIFT (24U)
#define | CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
TIMER - Free Running Timer Register..Free Running Timer
#define | CAN_TIMER_TIMER_MASK (0xFFFFU)
#define | CAN_TIMER_TIMER_SHIFT (0U)
#define | CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
RXMGMASK - Rx Mailboxes Global Mask Register
#define | CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
#define | CAN_RXMGMASK_MG_SHIFT (0U)
#define | CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
RX14MASK - Rx Buffer 14 Mask Register..Rx 14 Mask register
#define | CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
#define | CAN_RX14MASK_RX14M_SHIFT (0U)
#define | CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
RX15MASK - Rx Buffer 15 Mask Register..Rx 15 Mask register
#define | CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
#define | CAN_RX15MASK_RX15M_SHIFT (0U)
#define | CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
ECR - Error Counter Register..Error Counter
#define | CAN_ECR_TXERRCNT_MASK (0xFFU)
#define | CAN_ECR_TXERRCNT_SHIFT (0U)
#define | CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
#define | CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
#define | CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
#define | CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
#define | CAN_ECR_RXERRCNT_MASK (0xFF00U)
#define | CAN_ECR_RXERRCNT_SHIFT (8U)
#define | CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
#define | CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
#define | CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
#define | CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
#define | CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
#define | CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
#define | CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
#define | CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
#define | CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
#define | CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
ESR1 - Error and Status 1 Register..Error and Status 1 register
#define | CAN_ESR1_WAKINT_MASK (0x1U)
#define | CAN_ESR1_WAKINT_SHIFT (0U)
#define | CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
#define | CAN_ESR1_ERRINT_MASK (0x2U)
#define | CAN_ESR1_ERRINT_SHIFT (1U)
#define | CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
#define | CAN_ESR1_BOFFINT_MASK (0x4U)
#define | CAN_ESR1_BOFFINT_SHIFT (2U)
#define | CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
#define | CAN_ESR1_RX_MASK (0x8U)
#define | CAN_ESR1_RX_SHIFT (3U)
#define | CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
#define | CAN_ESR1_FLTCONF_MASK (0x30U)
#define | CAN_ESR1_FLTCONF_SHIFT (4U)
#define | CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
#define | CAN_ESR1_TX_MASK (0x40U)
#define | CAN_ESR1_TX_SHIFT (6U)
#define | CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
#define | CAN_ESR1_IDLE_MASK (0x80U)
#define | CAN_ESR1_IDLE_SHIFT (7U)
#define | CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
#define | CAN_ESR1_RXWRN_MASK (0x100U)
#define | CAN_ESR1_RXWRN_SHIFT (8U)
#define | CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
#define | CAN_ESR1_TXWRN_MASK (0x200U)
#define | CAN_ESR1_TXWRN_SHIFT (9U)
#define | CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
#define | CAN_ESR1_STFERR_MASK (0x400U)
#define | CAN_ESR1_STFERR_SHIFT (10U)
#define | CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
#define | CAN_ESR1_FRMERR_MASK (0x800U)
#define | CAN_ESR1_FRMERR_SHIFT (11U)
#define | CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
#define | CAN_ESR1_CRCERR_MASK (0x1000U)
#define | CAN_ESR1_CRCERR_SHIFT (12U)
#define | CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
#define | CAN_ESR1_ACKERR_MASK (0x2000U)
#define | CAN_ESR1_ACKERR_SHIFT (13U)
#define | CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
#define | CAN_ESR1_BIT0ERR_MASK (0x4000U)
#define | CAN_ESR1_BIT0ERR_SHIFT (14U)
#define | CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
#define | CAN_ESR1_BIT1ERR_MASK (0x8000U)
#define | CAN_ESR1_BIT1ERR_SHIFT (15U)
#define | CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
#define | CAN_ESR1_RWRNINT_MASK (0x10000U)
#define | CAN_ESR1_RWRNINT_SHIFT (16U)
#define | CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
#define | CAN_ESR1_TWRNINT_MASK (0x20000U)
#define | CAN_ESR1_TWRNINT_SHIFT (17U)
#define | CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
#define | CAN_ESR1_SYNCH_MASK (0x40000U)
#define | CAN_ESR1_SYNCH_SHIFT (18U)
#define | CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
#define | CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
#define | CAN_ESR1_BOFFDONEINT_SHIFT (19U)
#define | CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
#define | CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
#define | CAN_ESR1_ERRINT_FAST_SHIFT (20U)
#define | CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
#define | CAN_ESR1_ERROVR_MASK (0x200000U)
#define | CAN_ESR1_ERROVR_SHIFT (21U)
#define | CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
#define | CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
#define | CAN_ESR1_STFERR_FAST_SHIFT (26U)
#define | CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
#define | CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
#define | CAN_ESR1_FRMERR_FAST_SHIFT (27U)
#define | CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
#define | CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
#define | CAN_ESR1_CRCERR_FAST_SHIFT (28U)
#define | CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
#define | CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
#define | CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
#define | CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
#define | CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
#define | CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
#define | CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
IMASK2 - Interrupt Masks 2 Register..Interrupt Masks 2 register
#define | CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
#define | CAN_IMASK2_BUF63TO32M_SHIFT (0U)
#define | CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
#define | CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
#define | CAN_IMASK2_BUFHM_SHIFT (0U)
#define | CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
IMASK1 - Interrupt Masks 1 Register..Interrupt Masks 1 register
#define | CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
#define | CAN_IMASK1_BUF31TO0M_SHIFT (0U)
#define | CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
#define | CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
#define | CAN_IMASK1_BUFLM_SHIFT (0U)
#define | CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
IFLAG2 - Interrupt Flags 2 Register..Interrupt Flags 2 register
#define | CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
#define | CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
#define | CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
#define | CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
#define | CAN_IFLAG2_BUFHI_SHIFT (0U)
#define | CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
IFLAG1 - Interrupt Flags 1 Register..Interrupt Flags 1 register
#define | CAN_IFLAG1_BUF0I_MASK (0x1U)
#define | CAN_IFLAG1_BUF0I_SHIFT (0U)
#define | CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
#define | CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
#define | CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
#define | CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
#define | CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
#define | CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
#define | CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
#define | CAN_IFLAG1_BUF5I_MASK (0x20U)
#define | CAN_IFLAG1_BUF5I_SHIFT (5U)
#define | CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
#define | CAN_IFLAG1_BUF6I_MASK (0x40U)
#define | CAN_IFLAG1_BUF6I_SHIFT (6U)
#define | CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
#define | CAN_IFLAG1_BUF7I_MASK (0x80U)
#define | CAN_IFLAG1_BUF7I_SHIFT (7U)
#define | CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
#define | CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
#define | CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
#define | CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
CTRL2 - Control 2 Register..Control 2 register
#define | CAN_CTRL2_TSTAMPCAP_MASK (0xC0U)
#define | CAN_CTRL2_TSTAMPCAP_SHIFT (6U)
#define | CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK)
#define | CAN_CTRL2_MBTSBASE_MASK (0x300U)
#define | CAN_CTRL2_MBTSBASE_SHIFT (8U)
#define | CAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK)
#define | CAN_CTRL2_EDFLTDIS_MASK (0x800U)
#define | CAN_CTRL2_EDFLTDIS_SHIFT (11U)
#define | CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
#define | CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
#define | CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
#define | CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
#define | CAN_CTRL2_BTE_MASK (0x2000U)
#define | CAN_CTRL2_BTE_SHIFT (13U)
#define | CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)
#define | CAN_CTRL2_PREXCEN_MASK (0x4000U)
#define | CAN_CTRL2_PREXCEN_SHIFT (14U)
#define | CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
#define | CAN_CTRL2_TIMER_SRC_MASK (0x8000U)
#define | CAN_CTRL2_TIMER_SRC_SHIFT (15U)
#define | CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
#define | CAN_CTRL2_EACEN_MASK (0x10000U)
#define | CAN_CTRL2_EACEN_SHIFT (16U)
#define | CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
#define | CAN_CTRL2_RRS_MASK (0x20000U)
#define | CAN_CTRL2_RRS_SHIFT (17U)
#define | CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
#define | CAN_CTRL2_MRP_MASK (0x40000U)
#define | CAN_CTRL2_MRP_SHIFT (18U)
#define | CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
#define | CAN_CTRL2_TASD_MASK (0xF80000U)
#define | CAN_CTRL2_TASD_SHIFT (19U)
#define | CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
#define | CAN_CTRL2_RFFN_MASK (0xF000000U)
#define | CAN_CTRL2_RFFN_SHIFT (24U)
#define | CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
#define | CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
#define | CAN_CTRL2_WRMFRZ_SHIFT (28U)
#define | CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
#define | CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
#define | CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
#define | CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
#define | CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
#define | CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
#define | CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
ESR2 - Error and Status 2 Register..Error and Status 2 register
#define | CAN_ESR2_IMB_MASK (0x2000U)
#define | CAN_ESR2_IMB_SHIFT (13U)
#define | CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
#define | CAN_ESR2_VPS_MASK (0x4000U)
#define | CAN_ESR2_VPS_SHIFT (14U)
#define | CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
#define | CAN_ESR2_LPTM_MASK (0x7F0000U)
#define | CAN_ESR2_LPTM_SHIFT (16U)
#define | CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
CRCR - CRC Register
#define | CAN_CRCR_TXCRC_MASK (0x7FFFU)
#define | CAN_CRCR_TXCRC_SHIFT (0U)
#define | CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
#define | CAN_CRCR_MBCRC_MASK (0x7F0000U)
#define | CAN_CRCR_MBCRC_SHIFT (16U)
#define | CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
RXFGMASK - Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register
#define | CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
#define | CAN_RXFGMASK_FGM_SHIFT (0U)
#define | CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
RXFIR - Rx FIFO Information Register..Legacy Rx FIFO Information Register
#define | CAN_RXFIR_IDHIT_MASK (0x1FFU)
#define | CAN_RXFIR_IDHIT_SHIFT (0U)
#define | CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
CBT - CAN Bit Timing Register
#define | CAN_CBT_EPSEG2_MASK (0x1FU)
#define | CAN_CBT_EPSEG2_SHIFT (0U)
#define | CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
#define | CAN_CBT_EPSEG1_MASK (0x3E0U)
#define | CAN_CBT_EPSEG1_SHIFT (5U)
#define | CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
#define | CAN_CBT_EPROPSEG_MASK (0xFC00U)
#define | CAN_CBT_EPROPSEG_SHIFT (10U)
#define | CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
#define | CAN_CBT_ERJW_MASK (0x1F0000U)
#define | CAN_CBT_ERJW_SHIFT (16U)
#define | CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
#define | CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
#define | CAN_CBT_EPRESDIV_SHIFT (21U)
#define | CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
#define | CAN_CBT_BTF_MASK (0x80000000U)
#define | CAN_CBT_BTF_SHIFT (31U)
#define | CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
DBG1 - Debug 1 register
#define | CAN_DBG1_CFSM_MASK (0x3FU)
#define | CAN_DBG1_CFSM_SHIFT (0U)
#define | CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
#define | CAN_DBG1_CBN_MASK (0x1F000000U)
#define | CAN_DBG1_CBN_SHIFT (24U)
#define | CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
DBG2 - Debug 2 register
#define | CAN_DBG2_RMP_MASK (0x7FU)
#define | CAN_DBG2_RMP_SHIFT (0U)
#define | CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
#define | CAN_DBG2_MPP_MASK (0x80U)
#define | CAN_DBG2_MPP_SHIFT (7U)
#define | CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
#define | CAN_DBG2_TAP_MASK (0x7F00U)
#define | CAN_DBG2_TAP_SHIFT (8U)
#define | CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
#define | CAN_DBG2_APP_MASK (0x8000U)
#define | CAN_DBG2_APP_SHIFT (15U)
#define | CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
CS - Message Buffer 0 CS Register..Message Buffer 13 CS Register
#define | CAN_CS_TIME_STAMP_MASK (0xFFFFU)
#define | CAN_CS_TIME_STAMP_SHIFT (0U)
#define | CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
#define | CAN_CS_DLC_MASK (0xF0000U)
#define | CAN_CS_DLC_SHIFT (16U)
#define | CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
#define | CAN_CS_RTR_MASK (0x100000U)
#define | CAN_CS_RTR_SHIFT (20U)
#define | CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
#define | CAN_CS_IDE_MASK (0x200000U)
#define | CAN_CS_IDE_SHIFT (21U)
#define | CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
#define | CAN_CS_SRR_MASK (0x400000U)
#define | CAN_CS_SRR_SHIFT (22U)
#define | CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
#define | CAN_CS_CODE_MASK (0xF000000U)
#define | CAN_CS_CODE_SHIFT (24U)
#define | CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
#define | CAN_CS_ESI_MASK (0x20000000U)
#define | CAN_CS_ESI_SHIFT (29U)
#define | CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
#define | CAN_CS_BRS_MASK (0x40000000U)
#define | CAN_CS_BRS_SHIFT (30U)
#define | CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
#define | CAN_CS_EDL_MASK (0x80000000U)
#define | CAN_CS_EDL_SHIFT (31U)
#define | CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
ID - Message Buffer 0 ID Register..Message Buffer 13 ID Register
#define | CAN_ID_EXT_MASK (0x3FFFFU)
#define | CAN_ID_EXT_SHIFT (0U)
#define | CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
#define | CAN_ID_STD_MASK (0x1FFC0000U)
#define | CAN_ID_STD_SHIFT (18U)
#define | CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
#define | CAN_ID_PRIO_MASK (0xE0000000U)
#define | CAN_ID_PRIO_SHIFT (29U)
#define | CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
WORD - Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register
#define | CAN_WORD_DATA_BYTE_3_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_3_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
#define | CAN_WORD_DATA_BYTE_7_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_7_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
#define | CAN_WORD_DATA_BYTE_11_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_11_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
#define | CAN_WORD_DATA_BYTE_15_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_15_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
#define | CAN_WORD_DATA_BYTE_19_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_19_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
#define | CAN_WORD_DATA_BYTE_23_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_23_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
#define | CAN_WORD_DATA_BYTE_27_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_27_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
#define | CAN_WORD_DATA_BYTE_31_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_31_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
#define | CAN_WORD_DATA_BYTE_35_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_35_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
#define | CAN_WORD_DATA_BYTE_39_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_39_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
#define | CAN_WORD_DATA_BYTE_43_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_43_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
#define | CAN_WORD_DATA_BYTE_47_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_47_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
#define | CAN_WORD_DATA_BYTE_51_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_51_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
#define | CAN_WORD_DATA_BYTE_55_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_55_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
#define | CAN_WORD_DATA_BYTE_59_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_59_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
#define | CAN_WORD_DATA_BYTE_63_MASK (0xFFU)
#define | CAN_WORD_DATA_BYTE_63_SHIFT (0U)
#define | CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
#define | CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_2_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
#define | CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_6_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
#define | CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_10_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
#define | CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_14_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
#define | CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_18_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
#define | CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_22_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
#define | CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_26_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
#define | CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_30_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
#define | CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_34_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
#define | CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_38_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
#define | CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_42_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
#define | CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_46_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
#define | CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_50_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
#define | CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_54_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
#define | CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_58_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
#define | CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)
#define | CAN_WORD_DATA_BYTE_62_SHIFT (8U)
#define | CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
#define | CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_1_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
#define | CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_5_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
#define | CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_9_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
#define | CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_13_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
#define | CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_17_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
#define | CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_21_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
#define | CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_25_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
#define | CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_29_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
#define | CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_33_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
#define | CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_37_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
#define | CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_41_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
#define | CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_45_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
#define | CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_49_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
#define | CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_53_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
#define | CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_57_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
#define | CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)
#define | CAN_WORD_DATA_BYTE_61_SHIFT (16U)
#define | CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
#define | CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_0_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
#define | CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_4_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
#define | CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_8_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
#define | CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_12_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
#define | CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_16_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
#define | CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_20_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
#define | CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_24_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
#define | CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_28_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
#define | CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_32_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
#define | CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_36_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
#define | CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_40_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
#define | CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_44_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
#define | CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_48_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
#define | CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_52_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
#define | CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_56_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
#define | CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)
#define | CAN_WORD_DATA_BYTE_60_SHIFT (24U)
#define | CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register
#define | CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
#define | CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
#define | CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
#define | CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
#define | CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
#define | CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
#define | CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
#define | CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
#define | CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
#define | CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
#define | CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
#define | CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register
#define | CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
#define | CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
#define | CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
#define | CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
#define | CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
#define | CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
#define | CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
#define | CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
#define | CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
#define | CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
#define | CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
#define | CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
RXIMR - Rx Individual Mask Registers
#define | CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
#define | CAN_RXIMR_MI_SHIFT (0U)
#define | CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
GFWR - Glitch Filter Width Registers
#define | CAN_GFWR_GFWR_MASK (0xFFU)
#define | CAN_GFWR_GFWR_SHIFT (0U)
#define | CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
EPRS - Enhanced CAN Bit Timing Prescalers
#define | CAN_EPRS_ENPRESDIV_MASK (0x3FFU)
#define | CAN_EPRS_ENPRESDIV_SHIFT (0U)
#define | CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)
#define | CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U)
#define | CAN_EPRS_EDPRESDIV_SHIFT (16U)
#define | CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
ENCBT - Enhanced Nominal CAN Bit Timing
#define | CAN_ENCBT_NTSEG1_MASK (0xFFU)
#define | CAN_ENCBT_NTSEG1_SHIFT (0U)
#define | CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)
#define | CAN_ENCBT_NTSEG2_MASK (0x7F000U)
#define | CAN_ENCBT_NTSEG2_SHIFT (12U)
#define | CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)
#define | CAN_ENCBT_NRJW_MASK (0x1FC00000U)
#define | CAN_ENCBT_NRJW_SHIFT (22U)
#define | CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
EDCBT - Enhanced Data Phase CAN bit Timing
#define | CAN_EDCBT_DTSEG1_MASK (0x1FU)
#define | CAN_EDCBT_DTSEG1_SHIFT (0U)
#define | CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)
#define | CAN_EDCBT_DTSEG2_MASK (0xF000U)
#define | CAN_EDCBT_DTSEG2_SHIFT (12U)
#define | CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)
#define | CAN_EDCBT_DRJW_MASK (0x3C00000U)
#define | CAN_EDCBT_DRJW_SHIFT (22U)
#define | CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
ETDC - Enhanced Transceiver Delay Compensation
#define | CAN_ETDC_ETDCVAL_MASK (0xFFU)
#define | CAN_ETDC_ETDCVAL_SHIFT (0U)
#define | CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)
#define | CAN_ETDC_ETDCOFF_MASK (0x7F0000U)
#define | CAN_ETDC_ETDCOFF_SHIFT (16U)
#define | CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)
#define | CAN_ETDC_TDMDIS_MASK (0x80000000U)
#define | CAN_ETDC_TDMDIS_SHIFT (31U)
#define | CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)
FDCTRL - CAN FD Control Register
#define | CAN_FDCTRL_TDCVAL_MASK (0x3FU)
#define | CAN_FDCTRL_TDCVAL_SHIFT (0U)
#define | CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
#define | CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
#define | CAN_FDCTRL_TDCOFF_SHIFT (8U)
#define | CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
#define | CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
#define | CAN_FDCTRL_TDCFAIL_SHIFT (14U)
#define | CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
#define | CAN_FDCTRL_TDCEN_MASK (0x8000U)
#define | CAN_FDCTRL_TDCEN_SHIFT (15U)
#define | CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
#define | CAN_FDCTRL_MBDSR0_MASK (0x30000U)
#define | CAN_FDCTRL_MBDSR0_SHIFT (16U)
#define | CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
#define | CAN_FDCTRL_MBDSR1_MASK (0x180000U)
#define | CAN_FDCTRL_MBDSR1_SHIFT (19U)
#define | CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
#define | CAN_FDCTRL_FDRATE_MASK (0x80000000U)
#define | CAN_FDCTRL_FDRATE_SHIFT (31U)
#define | CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
FDCBT - CAN FD Bit Timing Register
#define | CAN_FDCBT_FPSEG2_MASK (0x7U)
#define | CAN_FDCBT_FPSEG2_SHIFT (0U)
#define | CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
#define | CAN_FDCBT_FPSEG1_MASK (0xE0U)
#define | CAN_FDCBT_FPSEG1_SHIFT (5U)
#define | CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
#define | CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
#define | CAN_FDCBT_FPROPSEG_SHIFT (10U)
#define | CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
#define | CAN_FDCBT_FRJW_MASK (0x70000U)
#define | CAN_FDCBT_FRJW_SHIFT (16U)
#define | CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
#define | CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
#define | CAN_FDCBT_FPRESDIV_SHIFT (20U)
#define | CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
FDCRC - CAN FD CRC Register
#define | CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
#define | CAN_FDCRC_FD_TXCRC_SHIFT (0U)
#define | CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
#define | CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
#define | CAN_FDCRC_FD_MBCRC_SHIFT (24U)
#define | CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
ERFCR - Enhanced Rx FIFO Control Register
#define | CAN_ERFCR_ERFWM_MASK (0x1FU)
#define | CAN_ERFCR_ERFWM_SHIFT (0U)
#define | CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)
#define | CAN_ERFCR_NFE_MASK (0x3F00U)
#define | CAN_ERFCR_NFE_SHIFT (8U)
#define | CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)
#define | CAN_ERFCR_NEXIF_MASK (0x7F0000U)
#define | CAN_ERFCR_NEXIF_SHIFT (16U)
#define | CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)
#define | CAN_ERFCR_DMALW_MASK (0x7C000000U)
#define | CAN_ERFCR_DMALW_SHIFT (26U)
#define | CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)
#define | CAN_ERFCR_ERFEN_MASK (0x80000000U)
#define | CAN_ERFCR_ERFEN_SHIFT (31U)
#define | CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
ERFIER - Enhanced Rx FIFO Interrupt Enable register
#define | CAN_ERFIER_ERFDAIE_MASK (0x10000000U)
#define | CAN_ERFIER_ERFDAIE_SHIFT (28U)
#define | CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)
#define | CAN_ERFIER_ERFWMIIE_MASK (0x20000000U)
#define | CAN_ERFIER_ERFWMIIE_SHIFT (29U)
#define | CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)
#define | CAN_ERFIER_ERFOVFIE_MASK (0x40000000U)
#define | CAN_ERFIER_ERFOVFIE_SHIFT (30U)
#define | CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)
#define | CAN_ERFIER_ERFUFWIE_MASK (0x80000000U)
#define | CAN_ERFIER_ERFUFWIE_SHIFT (31U)
#define | CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
ERFSR - Enhanced Rx FIFO Status Register
#define | CAN_ERFSR_ERFEL_MASK (0x3FU)
#define | CAN_ERFSR_ERFEL_SHIFT (0U)
#define | CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)
#define | CAN_ERFSR_ERFF_MASK (0x10000U)
#define | CAN_ERFSR_ERFF_SHIFT (16U)
#define | CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)
#define | CAN_ERFSR_ERFE_MASK (0x20000U)
#define | CAN_ERFSR_ERFE_SHIFT (17U)
#define | CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)
#define | CAN_ERFSR_ERFCLR_MASK (0x8000000U)
#define | CAN_ERFSR_ERFCLR_SHIFT (27U)
#define | CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)
#define | CAN_ERFSR_ERFDA_MASK (0x10000000U)
#define | CAN_ERFSR_ERFDA_SHIFT (28U)
#define | CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)
#define | CAN_ERFSR_ERFWMI_MASK (0x20000000U)
#define | CAN_ERFSR_ERFWMI_SHIFT (29U)
#define | CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
#define | CAN_ERFSR_ERFOVF_MASK (0x40000000U)
#define | CAN_ERFSR_ERFOVF_SHIFT (30U)
#define | CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)
#define | CAN_ERFSR_ERFUFW_MASK (0x80000000U)
#define | CAN_ERFSR_ERFUFW_SHIFT (31U)
#define | CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
HR_TIME_STAMP - High Resolution Time Stamp
#define | CAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU)
#define | CAN_HR_TIME_STAMP_TS_SHIFT (0U)
#define | CAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK)
ERFFEL - Enhanced Rx FIFO Filter Element
#define | CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU)
#define | CAN_ERFFEL_FEL_SHIFT (0U)
#define | CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
CCR - CCM Control Register
#define | CCM_CCR_OSCNT_MASK (0xFFU)
#define | CCM_CCR_OSCNT_SHIFT (0U)
#define | CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
#define | CCM_CCR_COSC_EN_MASK (0x1000U)
#define | CCM_CCR_COSC_EN_SHIFT (12U)
#define | CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
#define | CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
#define | CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
#define | CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
#define | CCM_CCR_RBC_EN_MASK (0x8000000U)
#define | CCM_CCR_RBC_EN_SHIFT (27U)
#define | CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
CSR - CCM Status Register
#define | CCM_CSR_REF_EN_B_MASK (0x1U)
#define | CCM_CSR_REF_EN_B_SHIFT (0U)
#define | CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
#define | CCM_CSR_CAMP2_READY_MASK (0x8U)
#define | CCM_CSR_CAMP2_READY_SHIFT (3U)
#define | CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
#define | CCM_CSR_COSC_READY_MASK (0x20U)
#define | CCM_CSR_COSC_READY_SHIFT (5U)
#define | CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
CCSR - CCM Clock Switcher Register
#define | CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
#define | CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
#define | CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
CACRR - CCM Arm Clock Root Register
#define | CCM_CACRR_ARM_PODF_MASK (0x7U)
#define | CCM_CACRR_ARM_PODF_SHIFT (0U)
#define | CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
CBCDR - CCM Bus Clock Divider Register
#define | CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
#define | CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
#define | CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
#define | CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
#define | CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
#define | CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
#define | CCM_CBCDR_IPG_PODF_MASK (0x300U)
#define | CCM_CBCDR_IPG_PODF_SHIFT (8U)
#define | CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
#define | CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
#define | CCM_CBCDR_AHB_PODF_SHIFT (10U)
#define | CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
#define | CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
#define | CCM_CBCDR_SEMC_PODF_SHIFT (16U)
#define | CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
#define | CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
#define | CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
#define | CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
#define | CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
#define | CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
#define | CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
CBCMR - CCM Bus Clock Multiplexer Register
#define | CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
#define | CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
#define | CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
#define | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK (0x300U)
#define | CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT (8U)
#define | CCM_CBCMR_FLEXSPI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT)) & CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK)
#define | CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
#define | CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
#define | CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
#define | CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
#define | CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
#define | CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
#define | CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
#define | CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
#define | CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
#define | CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
#define | CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
#define | CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
#define | CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
#define | CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
#define | CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
#define | CCM_CBCMR_FLEXSPI2_PODF_MASK (0xE0000000U)
#define | CCM_CBCMR_FLEXSPI2_PODF_SHIFT (29U)
#define | CCM_CBCMR_FLEXSPI2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_PODF_SHIFT)) & CCM_CBCMR_FLEXSPI2_PODF_MASK)
CSCMR1 - CCM Serial Clock Multiplexer Register 1
#define | CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
#define | CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
#define | CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
#define | CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
#define | CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
#define | CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
#define | CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
#define | CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
#define | CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
#define | CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
#define | CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
#define | CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
#define | CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
#define | CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
#define | CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
#define | CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
#define | CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
#define | CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
#define | CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
#define | CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
#define | CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
#define | CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
#define | CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
#define | CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
#define | CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
#define | CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
#define | CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
CSCMR2 - CCM Serial Clock Multiplexer Register 2
#define | CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
#define | CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
#define | CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
#define | CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
#define | CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
#define | CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
#define | CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
#define | CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
#define | CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
CSCDR1 - CCM Serial Clock Divider Register 1
#define | CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
#define | CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
#define | CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
#define | CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
#define | CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
#define | CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
#define | CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
#define | CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
#define | CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
#define | CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
#define | CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
#define | CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
#define | CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
#define | CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
#define | CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
CS1CDR - CCM Clock Divider Register
#define | CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
#define | CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
#define | CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
#define | CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
#define | CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
#define | CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
#define | CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
#define | CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
#define | CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
#define | CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
#define | CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
#define | CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
#define | CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
#define | CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
#define | CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
#define | CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
#define | CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
#define | CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
CS2CDR - CCM Clock Divider Register
#define | CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
#define | CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
#define | CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
#define | CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
#define | CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
#define | CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
CDCDR - CCM D1 Clock Divider Register
#define | CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
#define | CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
#define | CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
#define | CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
#define | CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
#define | CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
#define | CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
#define | CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
#define | CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
#define | CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
#define | CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
#define | CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
#define | CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
#define | CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
#define | CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
#define | CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
#define | CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
#define | CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
CSCDR2 - CCM Serial Clock Divider Register 2
#define | CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
#define | CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
#define | CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
#define | CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
#define | CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
#define | CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
#define | CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
#define | CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
#define | CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
#define | CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
#define | CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
#define | CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
CSCDR3 - CCM Serial Clock Divider Register 3
#define | CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
#define | CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
#define | CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
#define | CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
#define | CCM_CSCDR3_CSI_PODF_SHIFT (11U)
#define | CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
CDHIPR - CCM Divider Handshake In-Process Register
#define | CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
#define | CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
#define | CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
#define | CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
#define | CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
#define | CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
#define | CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
#define | CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
#define | CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
#define | CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
#define | CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
#define | CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
#define | CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
#define | CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
#define | CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
CLPCR - CCM Low Power Control Register
#define | CCM_CLPCR_LPM_MASK (0x3U)
#define | CCM_CLPCR_LPM_SHIFT (0U)
#define | CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
#define | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
#define | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
#define | CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
#define | CCM_CLPCR_SBYOS_MASK (0x40U)
#define | CCM_CLPCR_SBYOS_SHIFT (6U)
#define | CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
#define | CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
#define | CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
#define | CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
#define | CCM_CLPCR_VSTBY_MASK (0x100U)
#define | CCM_CLPCR_VSTBY_SHIFT (8U)
#define | CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
#define | CCM_CLPCR_STBY_COUNT_MASK (0x600U)
#define | CCM_CLPCR_STBY_COUNT_SHIFT (9U)
#define | CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
#define | CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
#define | CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
#define | CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
#define | CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
#define | CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
#define | CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
#define | CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
#define | CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
#define | CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
#define | CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
#define | CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
#define | CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
#define | CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
#define | CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
#define | CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
#define | CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
#define | CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
#define | CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
CISR - CCM Interrupt Status Register
#define | CCM_CISR_LRF_PLL_MASK (0x1U)
#define | CCM_CISR_LRF_PLL_SHIFT (0U)
#define | CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
#define | CCM_CISR_COSC_READY_MASK (0x40U)
#define | CCM_CISR_COSC_READY_SHIFT (6U)
#define | CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
#define | CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
#define | CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
#define | CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
#define | CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
#define | CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
#define | CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
#define | CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
#define | CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
#define | CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
#define | CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
#define | CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
#define | CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
#define | CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
#define | CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
#define | CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
CIMR - CCM Interrupt Mask Register
#define | CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
#define | CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
#define | CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
#define | CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
#define | CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
#define | CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
#define | CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
#define | CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
#define | CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
#define | CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
#define | CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
#define | CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
#define | CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
#define | CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
#define | CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
#define | CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
#define | CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
#define | CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
#define | CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
#define | CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
#define | CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
CCOSR - CCM Clock Output Source Register
#define | CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
#define | CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
#define | CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
#define | CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
#define | CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
#define | CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
#define | CCM_CCOSR_CLKO1_EN_MASK (0x80U)
#define | CCM_CCOSR_CLKO1_EN_SHIFT (7U)
#define | CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
#define | CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
#define | CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
#define | CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
#define | CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
#define | CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
#define | CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
#define | CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
#define | CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
#define | CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
#define | CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
#define | CCM_CCOSR_CLKO2_EN_SHIFT (24U)
#define | CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
CGPR - CCM General Purpose Register
#define | CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
#define | CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
#define | CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
#define | CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
#define | CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
#define | CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
#define | CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
#define | CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
#define | CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
#define | CCM_CGPR_FPL_MASK (0x10000U)
#define | CCM_CGPR_FPL_SHIFT (16U)
#define | CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
#define | CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
#define | CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
#define | CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
CCGR0 - CCM Clock Gating Register 0
#define | CCM_CCGR0_CG0_MASK (0x3U)
#define | CCM_CCGR0_CG0_SHIFT (0U)
#define | CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
#define | CCM_CCGR0_CG1_MASK (0xCU)
#define | CCM_CCGR0_CG1_SHIFT (2U)
#define | CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
#define | CCM_CCGR0_CG2_MASK (0x30U)
#define | CCM_CCGR0_CG2_SHIFT (4U)
#define | CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
#define | CCM_CCGR0_CG3_MASK (0xC0U)
#define | CCM_CCGR0_CG3_SHIFT (6U)
#define | CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
#define | CCM_CCGR0_CG4_MASK (0x300U)
#define | CCM_CCGR0_CG4_SHIFT (8U)
#define | CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
#define | CCM_CCGR0_CG5_MASK (0xC00U)
#define | CCM_CCGR0_CG5_SHIFT (10U)
#define | CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
#define | CCM_CCGR0_CG6_MASK (0x3000U)
#define | CCM_CCGR0_CG6_SHIFT (12U)
#define | CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
#define | CCM_CCGR0_CG7_MASK (0xC000U)
#define | CCM_CCGR0_CG7_SHIFT (14U)
#define | CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
#define | CCM_CCGR0_CG8_MASK (0x30000U)
#define | CCM_CCGR0_CG8_SHIFT (16U)
#define | CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
#define | CCM_CCGR0_CG9_MASK (0xC0000U)
#define | CCM_CCGR0_CG9_SHIFT (18U)
#define | CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
#define | CCM_CCGR0_CG10_MASK (0x300000U)
#define | CCM_CCGR0_CG10_SHIFT (20U)
#define | CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
#define | CCM_CCGR0_CG11_MASK (0xC00000U)
#define | CCM_CCGR0_CG11_SHIFT (22U)
#define | CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
#define | CCM_CCGR0_CG12_MASK (0x3000000U)
#define | CCM_CCGR0_CG12_SHIFT (24U)
#define | CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
#define | CCM_CCGR0_CG13_MASK (0xC000000U)
#define | CCM_CCGR0_CG13_SHIFT (26U)
#define | CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
#define | CCM_CCGR0_CG14_MASK (0x30000000U)
#define | CCM_CCGR0_CG14_SHIFT (28U)
#define | CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
#define | CCM_CCGR0_CG15_MASK (0xC0000000U)
#define | CCM_CCGR0_CG15_SHIFT (30U)
#define | CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
CCGR1 - CCM Clock Gating Register 1
#define | CCM_CCGR1_CG0_MASK (0x3U)
#define | CCM_CCGR1_CG0_SHIFT (0U)
#define | CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
#define | CCM_CCGR1_CG1_MASK (0xCU)
#define | CCM_CCGR1_CG1_SHIFT (2U)
#define | CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
#define | CCM_CCGR1_CG2_MASK (0x30U)
#define | CCM_CCGR1_CG2_SHIFT (4U)
#define | CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
#define | CCM_CCGR1_CG3_MASK (0xC0U)
#define | CCM_CCGR1_CG3_SHIFT (6U)
#define | CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
#define | CCM_CCGR1_CG4_MASK (0x300U)
#define | CCM_CCGR1_CG4_SHIFT (8U)
#define | CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
#define | CCM_CCGR1_CG5_MASK (0xC00U)
#define | CCM_CCGR1_CG5_SHIFT (10U)
#define | CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
#define | CCM_CCGR1_CG6_MASK (0x3000U)
#define | CCM_CCGR1_CG6_SHIFT (12U)
#define | CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
#define | CCM_CCGR1_CG7_MASK (0xC000U)
#define | CCM_CCGR1_CG7_SHIFT (14U)
#define | CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
#define | CCM_CCGR1_CG8_MASK (0x30000U)
#define | CCM_CCGR1_CG8_SHIFT (16U)
#define | CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
#define | CCM_CCGR1_CG9_MASK (0xC0000U)
#define | CCM_CCGR1_CG9_SHIFT (18U)
#define | CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
#define | CCM_CCGR1_CG10_MASK (0x300000U)
#define | CCM_CCGR1_CG10_SHIFT (20U)
#define | CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
#define | CCM_CCGR1_CG11_MASK (0xC00000U)
#define | CCM_CCGR1_CG11_SHIFT (22U)
#define | CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
#define | CCM_CCGR1_CG12_MASK (0x3000000U)
#define | CCM_CCGR1_CG12_SHIFT (24U)
#define | CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
#define | CCM_CCGR1_CG13_MASK (0xC000000U)
#define | CCM_CCGR1_CG13_SHIFT (26U)
#define | CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
#define | CCM_CCGR1_CG14_MASK (0x30000000U)
#define | CCM_CCGR1_CG14_SHIFT (28U)
#define | CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
#define | CCM_CCGR1_CG15_MASK (0xC0000000U)
#define | CCM_CCGR1_CG15_SHIFT (30U)
#define | CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
CCGR2 - CCM Clock Gating Register 2
#define | CCM_CCGR2_CG0_MASK (0x3U)
#define | CCM_CCGR2_CG0_SHIFT (0U)
#define | CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
#define | CCM_CCGR2_CG1_MASK (0xCU)
#define | CCM_CCGR2_CG1_SHIFT (2U)
#define | CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
#define | CCM_CCGR2_CG2_MASK (0x30U)
#define | CCM_CCGR2_CG2_SHIFT (4U)
#define | CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
#define | CCM_CCGR2_CG3_MASK (0xC0U)
#define | CCM_CCGR2_CG3_SHIFT (6U)
#define | CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
#define | CCM_CCGR2_CG4_MASK (0x300U)
#define | CCM_CCGR2_CG4_SHIFT (8U)
#define | CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
#define | CCM_CCGR2_CG5_MASK (0xC00U)
#define | CCM_CCGR2_CG5_SHIFT (10U)
#define | CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
#define | CCM_CCGR2_CG6_MASK (0x3000U)
#define | CCM_CCGR2_CG6_SHIFT (12U)
#define | CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
#define | CCM_CCGR2_CG7_MASK (0xC000U)
#define | CCM_CCGR2_CG7_SHIFT (14U)
#define | CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
#define | CCM_CCGR2_CG8_MASK (0x30000U)
#define | CCM_CCGR2_CG8_SHIFT (16U)
#define | CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
#define | CCM_CCGR2_CG9_MASK (0xC0000U)
#define | CCM_CCGR2_CG9_SHIFT (18U)
#define | CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
#define | CCM_CCGR2_CG10_MASK (0x300000U)
#define | CCM_CCGR2_CG10_SHIFT (20U)
#define | CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
#define | CCM_CCGR2_CG11_MASK (0xC00000U)
#define | CCM_CCGR2_CG11_SHIFT (22U)
#define | CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
#define | CCM_CCGR2_CG12_MASK (0x3000000U)
#define | CCM_CCGR2_CG12_SHIFT (24U)
#define | CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
#define | CCM_CCGR2_CG13_MASK (0xC000000U)
#define | CCM_CCGR2_CG13_SHIFT (26U)
#define | CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
#define | CCM_CCGR2_CG14_MASK (0x30000000U)
#define | CCM_CCGR2_CG14_SHIFT (28U)
#define | CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
#define | CCM_CCGR2_CG15_MASK (0xC0000000U)
#define | CCM_CCGR2_CG15_SHIFT (30U)
#define | CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
CCGR3 - CCM Clock Gating Register 3
#define | CCM_CCGR3_CG0_MASK (0x3U)
#define | CCM_CCGR3_CG0_SHIFT (0U)
#define | CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
#define | CCM_CCGR3_CG1_MASK (0xCU)
#define | CCM_CCGR3_CG1_SHIFT (2U)
#define | CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
#define | CCM_CCGR3_CG2_MASK (0x30U)
#define | CCM_CCGR3_CG2_SHIFT (4U)
#define | CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
#define | CCM_CCGR3_CG3_MASK (0xC0U)
#define | CCM_CCGR3_CG3_SHIFT (6U)
#define | CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
#define | CCM_CCGR3_CG4_MASK (0x300U)
#define | CCM_CCGR3_CG4_SHIFT (8U)
#define | CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
#define | CCM_CCGR3_CG5_MASK (0xC00U)
#define | CCM_CCGR3_CG5_SHIFT (10U)
#define | CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
#define | CCM_CCGR3_CG6_MASK (0x3000U)
#define | CCM_CCGR3_CG6_SHIFT (12U)
#define | CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
#define | CCM_CCGR3_CG7_MASK (0xC000U)
#define | CCM_CCGR3_CG7_SHIFT (14U)
#define | CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
#define | CCM_CCGR3_CG8_MASK (0x30000U)
#define | CCM_CCGR3_CG8_SHIFT (16U)
#define | CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
#define | CCM_CCGR3_CG9_MASK (0xC0000U)
#define | CCM_CCGR3_CG9_SHIFT (18U)
#define | CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
#define | CCM_CCGR3_CG10_MASK (0x300000U)
#define | CCM_CCGR3_CG10_SHIFT (20U)
#define | CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
#define | CCM_CCGR3_CG11_MASK (0xC00000U)
#define | CCM_CCGR3_CG11_SHIFT (22U)
#define | CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
#define | CCM_CCGR3_CG12_MASK (0x3000000U)
#define | CCM_CCGR3_CG12_SHIFT (24U)
#define | CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
#define | CCM_CCGR3_CG13_MASK (0xC000000U)
#define | CCM_CCGR3_CG13_SHIFT (26U)
#define | CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
#define | CCM_CCGR3_CG14_MASK (0x30000000U)
#define | CCM_CCGR3_CG14_SHIFT (28U)
#define | CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
#define | CCM_CCGR3_CG15_MASK (0xC0000000U)
#define | CCM_CCGR3_CG15_SHIFT (30U)
#define | CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
CCGR4 - CCM Clock Gating Register 4
#define | CCM_CCGR4_CG0_MASK (0x3U)
#define | CCM_CCGR4_CG0_SHIFT (0U)
#define | CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
#define | CCM_CCGR4_CG1_MASK (0xCU)
#define | CCM_CCGR4_CG1_SHIFT (2U)
#define | CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
#define | CCM_CCGR4_CG2_MASK (0x30U)
#define | CCM_CCGR4_CG2_SHIFT (4U)
#define | CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
#define | CCM_CCGR4_CG3_MASK (0xC0U)
#define | CCM_CCGR4_CG3_SHIFT (6U)
#define | CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
#define | CCM_CCGR4_CG4_MASK (0x300U)
#define | CCM_CCGR4_CG4_SHIFT (8U)
#define | CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
#define | CCM_CCGR4_CG5_MASK (0xC00U)
#define | CCM_CCGR4_CG5_SHIFT (10U)
#define | CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
#define | CCM_CCGR4_CG6_MASK (0x3000U)
#define | CCM_CCGR4_CG6_SHIFT (12U)
#define | CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
#define | CCM_CCGR4_CG7_MASK (0xC000U)
#define | CCM_CCGR4_CG7_SHIFT (14U)
#define | CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
#define | CCM_CCGR4_CG8_MASK (0x30000U)
#define | CCM_CCGR4_CG8_SHIFT (16U)
#define | CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
#define | CCM_CCGR4_CG9_MASK (0xC0000U)
#define | CCM_CCGR4_CG9_SHIFT (18U)
#define | CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
#define | CCM_CCGR4_CG10_MASK (0x300000U)
#define | CCM_CCGR4_CG10_SHIFT (20U)
#define | CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
#define | CCM_CCGR4_CG11_MASK (0xC00000U)
#define | CCM_CCGR4_CG11_SHIFT (22U)
#define | CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
#define | CCM_CCGR4_CG12_MASK (0x3000000U)
#define | CCM_CCGR4_CG12_SHIFT (24U)
#define | CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
#define | CCM_CCGR4_CG13_MASK (0xC000000U)
#define | CCM_CCGR4_CG13_SHIFT (26U)
#define | CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
#define | CCM_CCGR4_CG14_MASK (0x30000000U)
#define | CCM_CCGR4_CG14_SHIFT (28U)
#define | CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
#define | CCM_CCGR4_CG15_MASK (0xC0000000U)
#define | CCM_CCGR4_CG15_SHIFT (30U)
#define | CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
CCGR5 - CCM Clock Gating Register 5
#define | CCM_CCGR5_CG0_MASK (0x3U)
#define | CCM_CCGR5_CG0_SHIFT (0U)
#define | CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
#define | CCM_CCGR5_CG1_MASK (0xCU)
#define | CCM_CCGR5_CG1_SHIFT (2U)
#define | CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
#define | CCM_CCGR5_CG2_MASK (0x30U)
#define | CCM_CCGR5_CG2_SHIFT (4U)
#define | CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
#define | CCM_CCGR5_CG3_MASK (0xC0U)
#define | CCM_CCGR5_CG3_SHIFT (6U)
#define | CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
#define | CCM_CCGR5_CG4_MASK (0x300U)
#define | CCM_CCGR5_CG4_SHIFT (8U)
#define | CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
#define | CCM_CCGR5_CG5_MASK (0xC00U)
#define | CCM_CCGR5_CG5_SHIFT (10U)
#define | CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
#define | CCM_CCGR5_CG6_MASK (0x3000U)
#define | CCM_CCGR5_CG6_SHIFT (12U)
#define | CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
#define | CCM_CCGR5_CG7_MASK (0xC000U)
#define | CCM_CCGR5_CG7_SHIFT (14U)
#define | CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
#define | CCM_CCGR5_CG8_MASK (0x30000U)
#define | CCM_CCGR5_CG8_SHIFT (16U)
#define | CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
#define | CCM_CCGR5_CG9_MASK (0xC0000U)
#define | CCM_CCGR5_CG9_SHIFT (18U)
#define | CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
#define | CCM_CCGR5_CG10_MASK (0x300000U)
#define | CCM_CCGR5_CG10_SHIFT (20U)
#define | CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
#define | CCM_CCGR5_CG11_MASK (0xC00000U)
#define | CCM_CCGR5_CG11_SHIFT (22U)
#define | CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
#define | CCM_CCGR5_CG12_MASK (0x3000000U)
#define | CCM_CCGR5_CG12_SHIFT (24U)
#define | CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
#define | CCM_CCGR5_CG13_MASK (0xC000000U)
#define | CCM_CCGR5_CG13_SHIFT (26U)
#define | CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
#define | CCM_CCGR5_CG14_MASK (0x30000000U)
#define | CCM_CCGR5_CG14_SHIFT (28U)
#define | CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
#define | CCM_CCGR5_CG15_MASK (0xC0000000U)
#define | CCM_CCGR5_CG15_SHIFT (30U)
#define | CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
CCGR6 - CCM Clock Gating Register 6
#define | CCM_CCGR6_CG0_MASK (0x3U)
#define | CCM_CCGR6_CG0_SHIFT (0U)
#define | CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
#define | CCM_CCGR6_CG1_MASK (0xCU)
#define | CCM_CCGR6_CG1_SHIFT (2U)
#define | CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
#define | CCM_CCGR6_CG2_MASK (0x30U)
#define | CCM_CCGR6_CG2_SHIFT (4U)
#define | CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
#define | CCM_CCGR6_CG3_MASK (0xC0U)
#define | CCM_CCGR6_CG3_SHIFT (6U)
#define | CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
#define | CCM_CCGR6_CG4_MASK (0x300U)
#define | CCM_CCGR6_CG4_SHIFT (8U)
#define | CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
#define | CCM_CCGR6_CG5_MASK (0xC00U)
#define | CCM_CCGR6_CG5_SHIFT (10U)
#define | CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
#define | CCM_CCGR6_CG6_MASK (0x3000U)
#define | CCM_CCGR6_CG6_SHIFT (12U)
#define | CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
#define | CCM_CCGR6_CG7_MASK (0xC000U)
#define | CCM_CCGR6_CG7_SHIFT (14U)
#define | CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
#define | CCM_CCGR6_CG8_MASK (0x30000U)
#define | CCM_CCGR6_CG8_SHIFT (16U)
#define | CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
#define | CCM_CCGR6_CG9_MASK (0xC0000U)
#define | CCM_CCGR6_CG9_SHIFT (18U)
#define | CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
#define | CCM_CCGR6_CG10_MASK (0x300000U)
#define | CCM_CCGR6_CG10_SHIFT (20U)
#define | CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
#define | CCM_CCGR6_CG11_MASK (0xC00000U)
#define | CCM_CCGR6_CG11_SHIFT (22U)
#define | CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
#define | CCM_CCGR6_CG12_MASK (0x3000000U)
#define | CCM_CCGR6_CG12_SHIFT (24U)
#define | CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
#define | CCM_CCGR6_CG13_MASK (0xC000000U)
#define | CCM_CCGR6_CG13_SHIFT (26U)
#define | CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
#define | CCM_CCGR6_CG14_MASK (0x30000000U)
#define | CCM_CCGR6_CG14_SHIFT (28U)
#define | CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
#define | CCM_CCGR6_CG15_MASK (0xC0000000U)
#define | CCM_CCGR6_CG15_SHIFT (30U)
#define | CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
CCGR7 - CCM Clock Gating Register 7
#define | CCM_CCGR7_CG0_MASK (0x3U)
#define | CCM_CCGR7_CG0_SHIFT (0U)
#define | CCM_CCGR7_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG0_SHIFT)) & CCM_CCGR7_CG0_MASK)
#define | CCM_CCGR7_CG1_MASK (0xCU)
#define | CCM_CCGR7_CG1_SHIFT (2U)
#define | CCM_CCGR7_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG1_SHIFT)) & CCM_CCGR7_CG1_MASK)
#define | CCM_CCGR7_CG2_MASK (0x30U)
#define | CCM_CCGR7_CG2_SHIFT (4U)
#define | CCM_CCGR7_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG2_SHIFT)) & CCM_CCGR7_CG2_MASK)
#define | CCM_CCGR7_CG3_MASK (0xC0U)
#define | CCM_CCGR7_CG3_SHIFT (6U)
#define | CCM_CCGR7_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG3_SHIFT)) & CCM_CCGR7_CG3_MASK)
#define | CCM_CCGR7_CG4_MASK (0x300U)
#define | CCM_CCGR7_CG4_SHIFT (8U)
#define | CCM_CCGR7_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG4_SHIFT)) & CCM_CCGR7_CG4_MASK)
#define | CCM_CCGR7_CG5_MASK (0xC00U)
#define | CCM_CCGR7_CG5_SHIFT (10U)
#define | CCM_CCGR7_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG5_SHIFT)) & CCM_CCGR7_CG5_MASK)
#define | CCM_CCGR7_CG6_MASK (0x3000U)
#define | CCM_CCGR7_CG6_SHIFT (12U)
#define | CCM_CCGR7_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG6_SHIFT)) & CCM_CCGR7_CG6_MASK)
CMEOR - CCM Module Enable Overide Register
#define | CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
#define | CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
#define | CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
#define | CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
#define | CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
#define | CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
#define | CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
#define | CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
#define | CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
#define | CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
#define | CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
#define | CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
#define | CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK (0x400U)
#define | CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT (10U)
#define | CCM_CMEOR_MOD_EN_OV_CANFD_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK)
#define | CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
#define | CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
#define | CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
#define | CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
#define | CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
#define | CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
PLL_ARM - Analog ARM PLL control Register
#define | CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
#define | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
#define | CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
#define | CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
#define | CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
#define | CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
PLL_ARM_SET - Analog ARM PLL control Register
#define | CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
#define | CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
#define | CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
#define | CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
#define | CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
#define | CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
PLL_ARM_CLR - Analog ARM PLL control Register
#define | CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
#define | CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
#define | CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
#define | CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
#define | CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
#define | CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
PLL_ARM_TOG - Analog ARM PLL control Register
#define | CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
#define | CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
#define | CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
#define | CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
#define | CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
#define | CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
PLL_USB1 - Analog USB1 480MHz PLL Control Register
#define | CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
#define | CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
#define | CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
#define | CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
#define | CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
#define | CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
#define | CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
#define | CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
#define | CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
#define | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
#define | CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
PLL_USB1_SET - Analog USB1 480MHz PLL Control Register
#define | CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
#define | CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
#define | CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
#define | CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
#define | CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
#define | CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
#define | CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
#define | CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
#define | CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
#define | CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
#define | CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register
#define | CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
#define | CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
#define | CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
#define | CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
#define | CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
#define | CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
#define | CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
#define | CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
#define | CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
#define | CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
#define | CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register
#define | CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
#define | CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
#define | CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
#define | CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
#define | CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
#define | CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
#define | CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
#define | CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
#define | CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
#define | CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
#define | CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
PLL_USB2 - Analog USB2 480MHz PLL Control Register
#define | CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
#define | CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
#define | CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
#define | CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
#define | CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
#define | CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
#define | CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
#define | CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
#define | CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
#define | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
#define | CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
PLL_USB2_SET - Analog USB2 480MHz PLL Control Register
#define | CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
#define | CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
#define | CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
#define | CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
#define | CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
#define | CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
#define | CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
#define | CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
#define | CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
#define | CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
#define | CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register
#define | CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
#define | CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
#define | CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
#define | CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
#define | CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
#define | CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
#define | CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
#define | CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
#define | CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
#define | CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
#define | CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register
#define | CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
#define | CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
#define | CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
#define | CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
#define | CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
#define | CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
#define | CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
#define | CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
#define | CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
#define | CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
#define | CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
PLL_SYS - Analog System PLL Control Register
#define | CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
#define | CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
#define | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
#define | CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
PLL_SYS_SET - Analog System PLL Control Register
#define | CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
#define | CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
#define | CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
#define | CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
PLL_SYS_CLR - Analog System PLL Control Register
#define | CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
#define | CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
#define | CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
#define | CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
PLL_SYS_TOG - Analog System PLL Control Register
#define | CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
#define | CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
#define | CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
#define | CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register
#define | CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
#define | CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
#define | CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
#define | CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
#define | CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
#define | CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
#define | CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
#define | CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
#define | CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register
#define | CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
#define | CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
#define | CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register
#define | CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
#define | CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
#define | CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
PLL_AUDIO - Analog Audio PLL control Register
#define | CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
#define | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
#define | CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
#define | CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
#define | CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
PLL_AUDIO_SET - Analog Audio PLL control Register
#define | CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
#define | CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
#define | CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
#define | CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
#define | CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
PLL_AUDIO_CLR - Analog Audio PLL control Register
#define | CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
#define | CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
#define | CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
PLL_AUDIO_TOG - Analog Audio PLL control Register
#define | CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
#define | CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
#define | CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register
#define | CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
#define | CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
#define | CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register
#define | CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
#define | CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
#define | CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
PLL_VIDEO - Analog Video PLL control Register
#define | CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
#define | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
#define | CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
#define | CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
#define | CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
PLL_VIDEO_SET - Analog Video PLL control Register
#define | CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
#define | CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
#define | CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
#define | CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
#define | CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
PLL_VIDEO_CLR - Analog Video PLL control Register
#define | CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
#define | CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
#define | CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
PLL_VIDEO_TOG - Analog Video PLL control Register
#define | CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
#define | CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
#define | CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
#define | CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register
#define | CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
#define | CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
#define | CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register
#define | CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
#define | CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
#define | CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
PLL_ENET - Analog ENET PLL Control Register
#define | CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
#define | CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK (0xCU)
#define | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT (2U)
#define | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
#define | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
#define | CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK (0x100000U)
#define | CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT (20U)
#define | CCM_ANALOG_PLL_ENET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK)
#define | CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
#define | CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
#define | CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
#define | CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
PLL_ENET_SET - Analog ENET PLL Control Register
#define | CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
#define | CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK (0xCU)
#define | CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT (2U)
#define | CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
#define | CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
#define | CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK (0x100000U)
#define | CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT (20U)
#define | CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK)
#define | CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
#define | CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
#define | CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
#define | CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
PLL_ENET_CLR - Analog ENET PLL Control Register
#define | CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
#define | CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK (0xCU)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT (2U)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
#define | CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK (0x100000U)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT (20U)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
#define | CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
#define | CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
PLL_ENET_TOG - Analog ENET PLL Control Register
#define | CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
#define | CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
#define | CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK (0xCU)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT (2U)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK)
#define | CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
#define | CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
#define | CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
#define | CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
#define | CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
#define | CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
#define | CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define | CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define | CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
#define | CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
#define | CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
#define | CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK (0x100000U)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT (20U)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
#define | CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
#define | CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
#define | CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
#define | CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register
#define | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
#define | CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
#define | CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
#define | CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
#define | CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
#define | CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
#define | CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
#define | CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
#define | CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
#define | CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
#define | CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
#define | CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
#define | CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
#define | CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
#define | CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
#define | CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
#define | CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
#define | CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
#define | CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
#define | CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
#define | CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
#define | CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
#define | CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
#define | CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
#define | CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register
#define | CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
#define | CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
#define | CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
#define | CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
#define | CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
#define | CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
#define | CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
#define | CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
#define | CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
#define | CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
#define | CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
#define | CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
#define | CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
#define | CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
#define | CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
#define | CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
#define | CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
#define | CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
#define | CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
#define | CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
#define | CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
#define | CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
#define | CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
#define | CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
#define | CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register
#define | CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
#define | CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
#define | CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
#define | CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
#define | CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
#define | CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
#define | CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
#define | CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
#define | CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
#define | CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register
#define | CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
#define | CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
#define | CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
#define | CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
#define | CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
#define | CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
#define | CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
#define | CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
#define | CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
#define | CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register
#define | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
#define | CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
#define | CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
#define | CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
#define | CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
#define | CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
#define | CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
#define | CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
#define | CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
#define | CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
#define | CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
#define | CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
#define | CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
#define | CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
#define | CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
#define | CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
#define | CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
#define | CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
#define | CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
#define | CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
#define | CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
#define | CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
#define | CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
#define | CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
#define | CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register
#define | CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
#define | CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
#define | CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
#define | CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
#define | CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
#define | CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
#define | CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
#define | CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
#define | CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
#define | CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
#define | CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
#define | CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
#define | CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
#define | CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
#define | CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
#define | CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
#define | CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
#define | CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
#define | CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
#define | CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
#define | CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
#define | CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
#define | CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
#define | CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
#define | CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register
#define | CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
#define | CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
#define | CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
#define | CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
#define | CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
#define | CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
#define | CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
#define | CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
#define | CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
#define | CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register
#define | CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
#define | CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
#define | CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
#define | CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
#define | CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
#define | CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
#define | CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
#define | CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
#define | CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
#define | CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
MISC0 - Miscellaneous Register 0
#define | CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
#define | CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
#define | CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
#define | CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
#define | CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
#define | CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
#define | CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
#define | CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
#define | CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
#define | CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
#define | CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
#define | CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
#define | CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
#define | CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
#define | CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
#define | CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
#define | CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
#define | CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
#define | CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
#define | CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
#define | CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
#define | CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
#define | CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
#define | CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
#define | CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
#define | CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
#define | CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
#define | CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
#define | CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
#define | CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
#define | CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
#define | CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
#define | CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
#define | CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
#define | CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_REFTOP_PWD_MASK (0x1U)
#define | PMU_MISC0_REFTOP_PWD_SHIFT (0U)
#define | PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
#define | PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
#define | PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
#define | PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
#define | PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
#define | PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
#define | PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
#define | PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
#define | PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
#define | PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
#define | PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
#define | PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
#define | PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
#define | PMU_MISC0_OSC_I_MASK (0x6000U)
#define | PMU_MISC0_OSC_I_SHIFT (13U)
#define | PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
#define | PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
#define | PMU_MISC0_OSC_XTALOK_SHIFT (15U)
#define | PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
#define | PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
#define | PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
#define | PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
#define | PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
#define | PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
#define | PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
#define | PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
#define | PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
#define | PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
#define | PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
#define | PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
#define | PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
#define | PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
#define | PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
#define | PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)
#define | PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
#define | XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
#define | XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
#define | XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
#define | XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
#define | XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
#define | XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
#define | XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
#define | XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
#define | XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
#define | XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
#define | XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
#define | XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
#define | XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
#define | XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
#define | XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
#define | XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
#define | XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
#define | XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
#define | XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
#define | XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
#define | XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
#define | XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
#define | XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
#define | XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
#define | XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
#define | XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
#define | XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
#define | XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
#define | XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
#define | XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
#define | XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
#define | XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
#define | XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
#define | XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
#define | XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
#define | XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
#define | XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
#define | XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
MISC0_SET - Miscellaneous Register 0
#define | CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
#define | CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
#define | CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
#define | CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
#define | CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
#define | CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
#define | CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
#define | CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
#define | CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
#define | CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
#define | CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
#define | CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
#define | CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
#define | CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
#define | CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
#define | CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
#define | CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
#define | CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
#define | CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
#define | CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
#define | CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
#define | CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
#define | CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
#define | CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
#define | CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
#define | CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
#define | CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
#define | CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
#define | CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
#define | CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
#define | CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
#define | CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
#define | CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
#define | CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
#define | CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
#define | PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
#define | PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
#define | PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
#define | PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
#define | PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
#define | PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
#define | PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
#define | PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
#define | PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
#define | PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
#define | PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
#define | PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
#define | PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
#define | PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
#define | PMU_MISC0_SET_OSC_I_MASK (0x6000U)
#define | PMU_MISC0_SET_OSC_I_SHIFT (13U)
#define | PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
#define | PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
#define | PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
#define | PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
#define | PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
#define | PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
#define | PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
#define | PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
#define | PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
#define | PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
#define | PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
#define | PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
#define | PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
#define | PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
#define | PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
#define | PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
#define | PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
#define | PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
#define | PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
#define | PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
#define | XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
#define | XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
#define | XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
#define | XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
#define | XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
#define | XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
#define | XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
#define | XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
#define | XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
#define | XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
#define | XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
#define | XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
#define | XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
#define | XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
#define | XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
#define | XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
#define | XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
#define | XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
#define | XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
#define | XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
#define | XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
#define | XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
#define | XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
#define | XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
#define | XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
#define | XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
#define | XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
#define | XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
#define | XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
#define | XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
#define | XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
#define | XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
#define | XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
#define | XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
#define | XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
#define | XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
#define | XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
#define | XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
MISC0_CLR - Miscellaneous Register 0
#define | CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
#define | CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
#define | CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
#define | CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
#define | CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
#define | CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
#define | CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
#define | CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
#define | CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
#define | CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
#define | CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
#define | CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
#define | CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
#define | CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
#define | CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
#define | CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
#define | CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
#define | CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
#define | CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
#define | CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
#define | CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
#define | CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
#define | CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
#define | CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
#define | CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
#define | CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
#define | CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
#define | PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
#define | PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
#define | PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
#define | PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
#define | PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
#define | PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
#define | PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
#define | PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
#define | PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
#define | PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
#define | PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
#define | PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
#define | PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
#define | PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
#define | PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
#define | PMU_MISC0_CLR_OSC_I_SHIFT (13U)
#define | PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
#define | PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
#define | PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
#define | PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
#define | PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
#define | PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
#define | PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
#define | PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
#define | PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
#define | PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
#define | PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
#define | PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
#define | PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
#define | PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
#define | PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
#define | PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
#define | PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
#define | PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
#define | PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
#define | PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
#define | XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
#define | XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
#define | XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
#define | XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
#define | XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
#define | XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
#define | XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
#define | XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
#define | XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
#define | XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
#define | XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
#define | XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
#define | XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
#define | XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
#define | XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
#define | XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
#define | XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
#define | XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
#define | XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
#define | XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
#define | XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
#define | XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
#define | XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
#define | XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
#define | XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
#define | XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
#define | XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
#define | XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
#define | XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
#define | XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
#define | XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
#define | XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
#define | XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
#define | XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
#define | XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
#define | XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
#define | XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
#define | XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
MISC0_TOG - Miscellaneous Register 0
#define | CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
#define | CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
#define | CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
#define | CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
#define | CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
#define | CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
#define | CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
#define | CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
#define | CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
#define | CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
#define | CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
#define | CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
#define | CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
#define | CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
#define | CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
#define | CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
#define | CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
#define | CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
#define | CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
#define | CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
#define | CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
#define | CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
#define | CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
#define | CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
#define | CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
#define | CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
#define | CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
#define | PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
#define | PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
#define | PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
#define | PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
#define | PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
#define | PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
#define | PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
#define | PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
#define | PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
#define | PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
#define | PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
#define | PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
#define | PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
#define | PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
#define | PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
#define | PMU_MISC0_TOG_OSC_I_SHIFT (13U)
#define | PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
#define | PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
#define | PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
#define | PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
#define | PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
#define | PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
#define | PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
#define | PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
#define | PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
#define | PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
#define | PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
#define | PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
#define | PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
#define | PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
#define | PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
#define | PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
#define | PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
#define | PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
#define | PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
#define | PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
#define | PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
#define | XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
#define | XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
#define | XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
#define | XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
#define | XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
#define | XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
#define | XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
#define | XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
#define | XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
#define | XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
#define | XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
#define | XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
#define | XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
#define | XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
#define | XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
#define | XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
#define | XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
#define | XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
#define | XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
#define | XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
#define | XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
#define | XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
#define | XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
#define | XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
#define | XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
#define | XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
#define | XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
#define | XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
#define | XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
#define | XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
#define | XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
#define | XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
#define | XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
#define | XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define | XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
#define | XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
#define | XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
#define | XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
#define | XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
#define | XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
#define | XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
#define | XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
MISC1 - Miscellaneous Register 1
#define | CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
#define | CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
#define | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
#define | CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
#define | CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
#define | CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
#define | CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
#define | CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
#define | CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
#define | CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
#define | CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
#define | CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
#define | CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
#define | CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
#define | CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
#define | CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
#define | CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
#define | CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
#define | CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
#define | CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
#define | CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
#define | CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
#define | CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
#define | CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
#define | PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
#define | PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
#define | PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
#define | PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)
#define | PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)
#define | PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
#define | PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
#define | PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
#define | PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
#define | PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)
#define | PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)
#define | PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
#define | PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
#define | PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
#define | PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
#define | PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)
#define | PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)
#define | PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
#define | PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
#define | PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
#define | PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
#define | PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
#define | PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
#define | PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
#define | PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
#define | PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
#define | PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
#define | PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
#define | PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
#define | PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
#define | PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
#define | PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
#define | PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
MISC1_SET - Miscellaneous Register 1
#define | CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
#define | CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
#define | CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
#define | CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
#define | CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
#define | CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
#define | CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
#define | CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
#define | CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
#define | CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
#define | CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
#define | CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
#define | CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
#define | CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
#define | CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
#define | CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
#define | CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
#define | CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
#define | PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
#define | PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
#define | PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
#define | PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)
#define | PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)
#define | PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
#define | PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
#define | PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
#define | PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
#define | PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)
#define | PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)
#define | PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
#define | PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
#define | PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
#define | PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
#define | PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)
#define | PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)
#define | PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
#define | PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
#define | PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
#define | PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
#define | PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
#define | PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
#define | PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
#define | PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
#define | PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
#define | PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
#define | PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
#define | PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
#define | PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
#define | PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
#define | PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
#define | PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
MISC1_CLR - Miscellaneous Register 1
#define | CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
#define | CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
#define | CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
#define | CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
#define | CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
#define | CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
#define | CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
#define | CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
#define | CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
#define | CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
#define | CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
#define | CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
#define | CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
#define | CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
#define | PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
#define | PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
#define | PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
#define | PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)
#define | PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)
#define | PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
#define | PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
#define | PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
#define | PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
#define | PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)
#define | PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)
#define | PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
#define | PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
#define | PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
#define | PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
#define | PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)
#define | PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)
#define | PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
#define | PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
#define | PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
#define | PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
#define | PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
#define | PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
#define | PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
#define | PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
#define | PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
#define | PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
#define | PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
#define | PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
#define | PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
#define | PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
#define | PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
#define | PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
MISC1_TOG - Miscellaneous Register 1
#define | CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
#define | CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
#define | CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
#define | CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
#define | CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
#define | CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
#define | CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
#define | CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
#define | CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
#define | CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
#define | CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
#define | CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
#define | CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
#define | CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
#define | PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
#define | PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
#define | PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
#define | PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)
#define | PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)
#define | PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
#define | PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
#define | PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
#define | PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
#define | PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)
#define | PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)
#define | PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
#define | PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
#define | PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
#define | PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
#define | PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)
#define | PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)
#define | PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
#define | PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define | PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define | PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
#define | PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define | PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define | PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
#define | PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
#define | PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
#define | PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
#define | PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
#define | PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
#define | PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
#define | PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
#define | PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
#define | PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
#define | PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
#define | PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
#define | PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
#define | PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
#define | PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
#define | PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
MISC2 - Miscellaneous Register 2
#define | CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
#define | CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
#define | CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
#define | CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
#define | CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
#define | CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
#define | CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
#define | CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
#define | CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
#define | CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U)
#define | CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U)
#define | CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)
#define | CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
#define | CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
#define | CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
#define | CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
#define | CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
#define | CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
#define | CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
#define | CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
#define | CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
#define | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
#define | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
#define | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
#define | CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
#define | CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
#define | CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
#define | CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
#define | CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
#define | CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
#define | CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
#define | CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
#define | CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
#define | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
#define | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
#define | CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
#define | CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
#define | CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
#define | CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
#define | CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
#define | CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
#define | CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
#define | CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
#define | CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
#define | CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
MISC2_SET - Miscellaneous Register 2
#define | CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
#define | CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
#define | CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
#define | CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
#define | CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
#define | CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
#define | CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
#define | CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
#define | CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
#define | CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)
#define | CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)
#define | CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)
#define | CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
#define | CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
#define | CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
#define | CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
#define | CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
#define | CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
#define | CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
#define | CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
#define | CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
#define | CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
#define | CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
#define | CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
#define | CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
#define | CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
#define | CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
#define | CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
#define | CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
#define | CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
#define | CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
#define | CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
#define | CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
#define | CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
#define | CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
#define | CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
#define | CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
#define | CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
#define | CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
#define | CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
#define | CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
#define | CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
#define | CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
#define | CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
#define | CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
MISC2_CLR - Miscellaneous Register 2
#define | CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
#define | CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
#define | CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
#define | CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
#define | CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
#define | CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
#define | CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
#define | CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
#define | CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
#define | CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)
#define | CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)
#define | CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
#define | CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
#define | CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
#define | CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
#define | CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
#define | CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
#define | CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
#define | CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
#define | CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
#define | CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
#define | CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
#define | CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
#define | CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
#define | CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
#define | CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
#define | CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
#define | CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
#define | CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
#define | CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
#define | CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
#define | CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
#define | CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
#define | CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
#define | CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
#define | CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
#define | CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
#define | CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
#define | CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
#define | CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
#define | CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
#define | CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
MISC2_TOG - Miscellaneous Register 2
#define | CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
#define | CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
#define | CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
#define | CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
#define | CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
#define | CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
#define | CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
#define | CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
#define | CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
#define | CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)
#define | CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)
#define | CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
#define | CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
#define | CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
#define | CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
#define | CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
#define | CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
#define | CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
#define | CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
#define | CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
#define | CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
#define | CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
#define | CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
#define | CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
#define | CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
#define | CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
#define | CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
#define | CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
#define | CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
#define | CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
#define | CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
#define | CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
#define | CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
#define | CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
#define | CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
#define | CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
#define | CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
#define | CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
#define | CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
#define | CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
#define | CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
#define | CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
#define | CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
CR0 - CMP Control Register 0
#define | CMP_CR0_HYSTCTR_MASK (0x3U)
#define | CMP_CR0_HYSTCTR_SHIFT (0U)
#define | CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define | CMP_CR0_FILTER_CNT_MASK (0x70U)
#define | CMP_CR0_FILTER_CNT_SHIFT (4U)
#define | CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
CR1 - CMP Control Register 1
#define | CMP_CR1_EN_MASK (0x1U)
#define | CMP_CR1_EN_SHIFT (0U)
#define | CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define | CMP_CR1_OPE_MASK (0x2U)
#define | CMP_CR1_OPE_SHIFT (1U)
#define | CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define | CMP_CR1_COS_MASK (0x4U)
#define | CMP_CR1_COS_SHIFT (2U)
#define | CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define | CMP_CR1_INV_MASK (0x8U)
#define | CMP_CR1_INV_SHIFT (3U)
#define | CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define | CMP_CR1_PMODE_MASK (0x10U)
#define | CMP_CR1_PMODE_SHIFT (4U)
#define | CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define | CMP_CR1_WE_MASK (0x40U)
#define | CMP_CR1_WE_SHIFT (6U)
#define | CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define | CMP_CR1_SE_MASK (0x80U)
#define | CMP_CR1_SE_SHIFT (7U)
#define | CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
FPR - CMP Filter Period Register
#define | CMP_FPR_FILT_PER_MASK (0xFFU)
#define | CMP_FPR_FILT_PER_SHIFT (0U)
#define | CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
SCR - CMP Status and Control Register
#define | CMP_SCR_COUT_MASK (0x1U)
#define | CMP_SCR_COUT_SHIFT (0U)
#define | CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define | CMP_SCR_CFF_MASK (0x2U)
#define | CMP_SCR_CFF_SHIFT (1U)
#define | CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define | CMP_SCR_CFR_MASK (0x4U)
#define | CMP_SCR_CFR_SHIFT (2U)
#define | CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define | CMP_SCR_IEF_MASK (0x8U)
#define | CMP_SCR_IEF_SHIFT (3U)
#define | CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define | CMP_SCR_IER_MASK (0x10U)
#define | CMP_SCR_IER_SHIFT (4U)
#define | CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
#define | CMP_SCR_DMAEN_MASK (0x40U)
#define | CMP_SCR_DMAEN_SHIFT (6U)
#define | CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
DACCR - DAC Control Register
#define | CMP_DACCR_VOSEL_MASK (0x3FU)
#define | CMP_DACCR_VOSEL_SHIFT (0U)
#define | CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define | CMP_DACCR_VRSEL_MASK (0x40U)
#define | CMP_DACCR_VRSEL_SHIFT (6U)
#define | CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define | CMP_DACCR_DACEN_MASK (0x80U)
#define | CMP_DACCR_DACEN_SHIFT (7U)
#define | CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
MUXCR - MUX Control Register
#define | CMP_MUXCR_MSEL_MASK (0x7U)
#define | CMP_MUXCR_MSEL_SHIFT (0U)
#define | CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define | CMP_MUXCR_PSEL_MASK (0x38U)
#define | CMP_MUXCR_PSEL_SHIFT (3U)
#define | CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
CSICR1 - CSI Control Register 1
#define | CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
#define | CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
#define | CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
#define | CSI_CSICR1_REDGE_MASK (0x2U)
#define | CSI_CSICR1_REDGE_SHIFT (1U)
#define | CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
#define | CSI_CSICR1_INV_PCLK_MASK (0x4U)
#define | CSI_CSICR1_INV_PCLK_SHIFT (2U)
#define | CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
#define | CSI_CSICR1_INV_DATA_MASK (0x8U)
#define | CSI_CSICR1_INV_DATA_SHIFT (3U)
#define | CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
#define | CSI_CSICR1_GCLK_MODE_MASK (0x10U)
#define | CSI_CSICR1_GCLK_MODE_SHIFT (4U)
#define | CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
#define | CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
#define | CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
#define | CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
#define | CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
#define | CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
#define | CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
#define | CSI_CSICR1_PACK_DIR_MASK (0x80U)
#define | CSI_CSICR1_PACK_DIR_SHIFT (7U)
#define | CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
#define | CSI_CSICR1_FCC_MASK (0x100U)
#define | CSI_CSICR1_FCC_SHIFT (8U)
#define | CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
#define | CSI_CSICR1_CCIR_EN_MASK (0x400U)
#define | CSI_CSICR1_CCIR_EN_SHIFT (10U)
#define | CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
#define | CSI_CSICR1_HSYNC_POL_MASK (0x800U)
#define | CSI_CSICR1_HSYNC_POL_SHIFT (11U)
#define | CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
#define | CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
#define | CSI_CSICR1_SOF_INTEN_SHIFT (16U)
#define | CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
#define | CSI_CSICR1_SOF_POL_MASK (0x20000U)
#define | CSI_CSICR1_SOF_POL_SHIFT (17U)
#define | CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
#define | CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
#define | CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
#define | CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
#define | CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
#define | CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
#define | CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
#define | CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
#define | CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
#define | CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
#define | CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
#define | CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
#define | CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
#define | CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
#define | CSI_CSICR1_COF_INT_EN_SHIFT (26U)
#define | CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
#define | CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)
#define | CSI_CSICR1_CCIR_MODE_SHIFT (27U)
#define | CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
#define | CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
#define | CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
#define | CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
#define | CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
#define | CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
#define | CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
#define | CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
#define | CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
#define | CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
#define | CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
#define | CSI_CSICR1_SWAP16_EN_SHIFT (31U)
#define | CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
CSICR2 - CSI Control Register 2
#define | CSI_CSICR2_HSC_MASK (0xFFU)
#define | CSI_CSICR2_HSC_SHIFT (0U)
#define | CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
#define | CSI_CSICR2_VSC_MASK (0xFF00U)
#define | CSI_CSICR2_VSC_SHIFT (8U)
#define | CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
#define | CSI_CSICR2_LVRM_MASK (0x70000U)
#define | CSI_CSICR2_LVRM_SHIFT (16U)
#define | CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
#define | CSI_CSICR2_BTS_MASK (0x180000U)
#define | CSI_CSICR2_BTS_SHIFT (19U)
#define | CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
#define | CSI_CSICR2_SCE_MASK (0x800000U)
#define | CSI_CSICR2_SCE_SHIFT (23U)
#define | CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
#define | CSI_CSICR2_AFS_MASK (0x3000000U)
#define | CSI_CSICR2_AFS_SHIFT (24U)
#define | CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
#define | CSI_CSICR2_DRM_MASK (0x4000000U)
#define | CSI_CSICR2_DRM_SHIFT (26U)
#define | CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
CSICR3 - CSI Control Register 3
#define | CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
#define | CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
#define | CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
#define | CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
#define | CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
#define | CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
#define | CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
#define | CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
#define | CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
#define | CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
#define | CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
#define | CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
#define | CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
#define | CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
#define | CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
#define | CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
#define | CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
#define | CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
#define | CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
#define | CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
#define | CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
#define | CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
#define | CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
#define | CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
#define | CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
#define | CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
#define | CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
#define | CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
#define | CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
#define | CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
#define | CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
#define | CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
#define | CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
#define | CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
#define | CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
#define | CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
#define | CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
#define | CSI_CSICR3_FRMCNT_SHIFT (16U)
#define | CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
CSISTATFIFO - CSI Statistic FIFO Register
#define | CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
#define | CSI_CSISTATFIFO_STAT_SHIFT (0U)
#define | CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
CSIRFIFO - CSI RX FIFO Register
#define | CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
#define | CSI_CSIRFIFO_IMAGE_SHIFT (0U)
#define | CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
CSIRXCNT - CSI RX Count Register
#define | CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
#define | CSI_CSIRXCNT_RXCNT_SHIFT (0U)
#define | CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
CSISR - CSI Status Register
#define | CSI_CSISR_DRDY_MASK (0x1U)
#define | CSI_CSISR_DRDY_SHIFT (0U)
#define | CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
#define | CSI_CSISR_ECC_INT_MASK (0x2U)
#define | CSI_CSISR_ECC_INT_SHIFT (1U)
#define | CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
#define | CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
#define | CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
#define | CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
#define | CSI_CSISR_COF_INT_MASK (0x2000U)
#define | CSI_CSISR_COF_INT_SHIFT (13U)
#define | CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
#define | CSI_CSISR_F1_INT_MASK (0x4000U)
#define | CSI_CSISR_F1_INT_SHIFT (14U)
#define | CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
#define | CSI_CSISR_F2_INT_MASK (0x8000U)
#define | CSI_CSISR_F2_INT_SHIFT (15U)
#define | CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
#define | CSI_CSISR_SOF_INT_MASK (0x10000U)
#define | CSI_CSISR_SOF_INT_SHIFT (16U)
#define | CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
#define | CSI_CSISR_EOF_INT_MASK (0x20000U)
#define | CSI_CSISR_EOF_INT_SHIFT (17U)
#define | CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
#define | CSI_CSISR_RxFF_INT_MASK (0x40000U)
#define | CSI_CSISR_RxFF_INT_SHIFT (18U)
#define | CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
#define | CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
#define | CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
#define | CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
#define | CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
#define | CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
#define | CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
#define | CSI_CSISR_STATFF_INT_MASK (0x200000U)
#define | CSI_CSISR_STATFF_INT_SHIFT (21U)
#define | CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
#define | CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
#define | CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
#define | CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
#define | CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
#define | CSI_CSISR_RF_OR_INT_SHIFT (24U)
#define | CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
#define | CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
#define | CSI_CSISR_SF_OR_INT_SHIFT (25U)
#define | CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
#define | CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
#define | CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
#define | CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
#define | CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
#define | CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
#define | CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO
#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO
#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1
#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2
#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
CSIFBUF_PARA - CSI Frame Buffer Parameter Register
#define | CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
#define | CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
#define | CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
CSIIMAG_PARA - CSI Image Parameter Register
#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
CSICR18 - CSI Control Register 18
#define | CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
#define | CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
#define | CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
#define | CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
#define | CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
#define | CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
#define | CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
#define | CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
#define | CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
#define | CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
#define | CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
#define | CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
#define | CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
#define | CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
#define | CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
#define | CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
#define | CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
#define | CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
#define | CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
#define | CSI_CSICR18_AHB_HPROT_SHIFT (12U)
#define | CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
#define | CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
#define | CSI_CSICR18_MASK_OPTION_SHIFT (18U)
#define | CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
#define | CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
#define | CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
#define | CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
CSICR19 - CSI Control Register 19
#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
CSL - Config security level register
#define | CSU_CSL_SUR_S2_MASK (0x1U)
#define | CSU_CSL_SUR_S2_SHIFT (0U)
#define | CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
#define | CSU_CSL_SSR_S2_MASK (0x2U)
#define | CSU_CSL_SSR_S2_SHIFT (1U)
#define | CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
#define | CSU_CSL_NUR_S2_MASK (0x4U)
#define | CSU_CSL_NUR_S2_SHIFT (2U)
#define | CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
#define | CSU_CSL_NSR_S2_MASK (0x8U)
#define | CSU_CSL_NSR_S2_SHIFT (3U)
#define | CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
#define | CSU_CSL_SUW_S2_MASK (0x10U)
#define | CSU_CSL_SUW_S2_SHIFT (4U)
#define | CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
#define | CSU_CSL_SSW_S2_MASK (0x20U)
#define | CSU_CSL_SSW_S2_SHIFT (5U)
#define | CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
#define | CSU_CSL_NUW_S2_MASK (0x40U)
#define | CSU_CSL_NUW_S2_SHIFT (6U)
#define | CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
#define | CSU_CSL_NSW_S2_MASK (0x80U)
#define | CSU_CSL_NSW_S2_SHIFT (7U)
#define | CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
#define | CSU_CSL_LOCK_S2_MASK (0x100U)
#define | CSU_CSL_LOCK_S2_SHIFT (8U)
#define | CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
#define | CSU_CSL_SUR_S1_MASK (0x10000U)
#define | CSU_CSL_SUR_S1_SHIFT (16U)
#define | CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
#define | CSU_CSL_SSR_S1_MASK (0x20000U)
#define | CSU_CSL_SSR_S1_SHIFT (17U)
#define | CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
#define | CSU_CSL_NUR_S1_MASK (0x40000U)
#define | CSU_CSL_NUR_S1_SHIFT (18U)
#define | CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
#define | CSU_CSL_NSR_S1_MASK (0x80000U)
#define | CSU_CSL_NSR_S1_SHIFT (19U)
#define | CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
#define | CSU_CSL_SUW_S1_MASK (0x100000U)
#define | CSU_CSL_SUW_S1_SHIFT (20U)
#define | CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
#define | CSU_CSL_SSW_S1_MASK (0x200000U)
#define | CSU_CSL_SSW_S1_SHIFT (21U)
#define | CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
#define | CSU_CSL_NUW_S1_MASK (0x400000U)
#define | CSU_CSL_NUW_S1_SHIFT (22U)
#define | CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
#define | CSU_CSL_NSW_S1_MASK (0x800000U)
#define | CSU_CSL_NSW_S1_SHIFT (23U)
#define | CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
#define | CSU_CSL_LOCK_S1_MASK (0x1000000U)
#define | CSU_CSL_LOCK_S1_SHIFT (24U)
#define | CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
HP0 - HP0 register
#define | CSU_HP0_HP_DMA_MASK (0x4U)
#define | CSU_HP0_HP_DMA_SHIFT (2U)
#define | CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
#define | CSU_HP0_L_DMA_MASK (0x8U)
#define | CSU_HP0_L_DMA_SHIFT (3U)
#define | CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
#define | CSU_HP0_HP_LCDIF_MASK (0x10U)
#define | CSU_HP0_HP_LCDIF_SHIFT (4U)
#define | CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
#define | CSU_HP0_L_LCDIF_MASK (0x20U)
#define | CSU_HP0_L_LCDIF_SHIFT (5U)
#define | CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
#define | CSU_HP0_HP_CSI_MASK (0x40U)
#define | CSU_HP0_HP_CSI_SHIFT (6U)
#define | CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
#define | CSU_HP0_L_CSI_MASK (0x80U)
#define | CSU_HP0_L_CSI_SHIFT (7U)
#define | CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
#define | CSU_HP0_HP_PXP_MASK (0x100U)
#define | CSU_HP0_HP_PXP_SHIFT (8U)
#define | CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
#define | CSU_HP0_L_PXP_MASK (0x200U)
#define | CSU_HP0_L_PXP_SHIFT (9U)
#define | CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
#define | CSU_HP0_HP_DCP_MASK (0x400U)
#define | CSU_HP0_HP_DCP_SHIFT (10U)
#define | CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
#define | CSU_HP0_L_DCP_MASK (0x800U)
#define | CSU_HP0_L_DCP_SHIFT (11U)
#define | CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
#define | CSU_HP0_HP_ENET_MASK (0x4000U)
#define | CSU_HP0_HP_ENET_SHIFT (14U)
#define | CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
#define | CSU_HP0_L_ENET_MASK (0x8000U)
#define | CSU_HP0_L_ENET_SHIFT (15U)
#define | CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
#define | CSU_HP0_HP_USDHC1_MASK (0x10000U)
#define | CSU_HP0_HP_USDHC1_SHIFT (16U)
#define | CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
#define | CSU_HP0_L_USDHC1_MASK (0x20000U)
#define | CSU_HP0_L_USDHC1_SHIFT (17U)
#define | CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
#define | CSU_HP0_HP_USDHC2_MASK (0x40000U)
#define | CSU_HP0_HP_USDHC2_SHIFT (18U)
#define | CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
#define | CSU_HP0_L_USDHC2_MASK (0x80000U)
#define | CSU_HP0_L_USDHC2_SHIFT (19U)
#define | CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
#define | CSU_HP0_HP_TPSMP_MASK (0x100000U)
#define | CSU_HP0_HP_TPSMP_SHIFT (20U)
#define | CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
#define | CSU_HP0_L_TPSMP_MASK (0x200000U)
#define | CSU_HP0_L_TPSMP_SHIFT (21U)
#define | CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
#define | CSU_HP0_HP_USB_MASK (0x400000U)
#define | CSU_HP0_HP_USB_SHIFT (22U)
#define | CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
#define | CSU_HP0_L_USB_MASK (0x800000U)
#define | CSU_HP0_L_USB_SHIFT (23U)
#define | CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
SA - Secure access register
#define | CSU_SA_NSA_DMA_MASK (0x4U)
#define | CSU_SA_NSA_DMA_SHIFT (2U)
#define | CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
#define | CSU_SA_L_DMA_MASK (0x8U)
#define | CSU_SA_L_DMA_SHIFT (3U)
#define | CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
#define | CSU_SA_NSA_LCDIF_MASK (0x10U)
#define | CSU_SA_NSA_LCDIF_SHIFT (4U)
#define | CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
#define | CSU_SA_L_LCDIF_MASK (0x20U)
#define | CSU_SA_L_LCDIF_SHIFT (5U)
#define | CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
#define | CSU_SA_NSA_CSI_MASK (0x40U)
#define | CSU_SA_NSA_CSI_SHIFT (6U)
#define | CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
#define | CSU_SA_L_CSI_MASK (0x80U)
#define | CSU_SA_L_CSI_SHIFT (7U)
#define | CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
#define | CSU_SA_NSA_PXP_MASK (0x100U)
#define | CSU_SA_NSA_PXP_SHIFT (8U)
#define | CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
#define | CSU_SA_L_PXP_MASK (0x200U)
#define | CSU_SA_L_PXP_SHIFT (9U)
#define | CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
#define | CSU_SA_NSA_DCP_MASK (0x400U)
#define | CSU_SA_NSA_DCP_SHIFT (10U)
#define | CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
#define | CSU_SA_L_DCP_MASK (0x800U)
#define | CSU_SA_L_DCP_SHIFT (11U)
#define | CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
#define | CSU_SA_NSA_ENET_MASK (0x4000U)
#define | CSU_SA_NSA_ENET_SHIFT (14U)
#define | CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
#define | CSU_SA_L_ENET_MASK (0x8000U)
#define | CSU_SA_L_ENET_SHIFT (15U)
#define | CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
#define | CSU_SA_NSA_USDHC1_MASK (0x10000U)
#define | CSU_SA_NSA_USDHC1_SHIFT (16U)
#define | CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
#define | CSU_SA_L_USDHC1_MASK (0x20000U)
#define | CSU_SA_L_USDHC1_SHIFT (17U)
#define | CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
#define | CSU_SA_NSA_USDHC2_MASK (0x40000U)
#define | CSU_SA_NSA_USDHC2_SHIFT (18U)
#define | CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
#define | CSU_SA_L_USDHC2_MASK (0x80000U)
#define | CSU_SA_L_USDHC2_SHIFT (19U)
#define | CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
#define | CSU_SA_NSA_TPSMP_MASK (0x100000U)
#define | CSU_SA_NSA_TPSMP_SHIFT (20U)
#define | CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
#define | CSU_SA_L_TPSMP_MASK (0x200000U)
#define | CSU_SA_L_TPSMP_SHIFT (21U)
#define | CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
#define | CSU_SA_NSA_USB_MASK (0x400000U)
#define | CSU_SA_NSA_USB_SHIFT (22U)
#define | CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
#define | CSU_SA_L_USB_MASK (0x800000U)
#define | CSU_SA_L_USB_SHIFT (23U)
#define | CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
HPCONTROL0 - HPCONTROL0 register
#define | CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
#define | CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
#define | CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
#define | CSU_HPCONTROL0_L_DMA_MASK (0x8U)
#define | CSU_HPCONTROL0_L_DMA_SHIFT (3U)
#define | CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
#define | CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
#define | CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
#define | CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
#define | CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
#define | CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
#define | CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
#define | CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
#define | CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
#define | CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
#define | CSU_HPCONTROL0_L_CSI_MASK (0x80U)
#define | CSU_HPCONTROL0_L_CSI_SHIFT (7U)
#define | CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
#define | CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
#define | CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
#define | CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
#define | CSU_HPCONTROL0_L_PXP_MASK (0x200U)
#define | CSU_HPCONTROL0_L_PXP_SHIFT (9U)
#define | CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
#define | CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
#define | CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
#define | CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
#define | CSU_HPCONTROL0_L_DCP_MASK (0x800U)
#define | CSU_HPCONTROL0_L_DCP_SHIFT (11U)
#define | CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
#define | CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
#define | CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
#define | CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
#define | CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
#define | CSU_HPCONTROL0_L_ENET_SHIFT (15U)
#define | CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
#define | CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
#define | CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
#define | CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
#define | CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
#define | CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
#define | CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
#define | CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
#define | CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
#define | CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
#define | CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
#define | CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
#define | CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
#define | CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
#define | CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
#define | CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
#define | CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
#define | CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
#define | CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
#define | CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
#define | CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
#define | CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
#define | CSU_HPCONTROL0_L_USB_MASK (0x800000U)
#define | CSU_HPCONTROL0_L_USB_SHIFT (23U)
#define | CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
REG0 - DCDC Register 0
#define | DCDC_REG0_PWD_ZCD_MASK (0x1U)
#define | DCDC_REG0_PWD_ZCD_SHIFT (0U)
#define | DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
#define | DCDC_REG0_SEL_CLK_MASK (0x4U)
#define | DCDC_REG0_SEL_CLK_SHIFT (2U)
#define | DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
#define | DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
#define | DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
#define | DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
#define | DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
#define | DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
#define | DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
#define | DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
#define | DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
#define | DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
#define | DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
#define | DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
#define | DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
#define | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
#define | DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
#define | DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
#define | DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
#define | DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
#define | DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
#define | DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)
#define | DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)
#define | DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)
#define | DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
#define | DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
#define | DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
#define | DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
#define | DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
#define | DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
#define | DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
#define | DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
#define | DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
#define | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
#define | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
#define | DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
#define | DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
#define | DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
#define | DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
#define | DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
#define | DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
#define | DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
#define | DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
#define | DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
#define | DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
#define | DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
#define | DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
#define | DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
#define | DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
#define | DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
#define | DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
#define | DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
#define | DCDC_REG0_STS_DC_OK_SHIFT (31U)
#define | DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
REG1 - DCDC Register 1
#define | DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
#define | DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
#define | DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
#define | DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
#define | DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
#define | DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
#define | DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
#define | DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
#define | DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
#define | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
#define | DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
#define | DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
#define | DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
#define | DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
#define | DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
#define | DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
#define | DCDC_REG1_VBG_TRIM_SHIFT (24U)
#define | DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
REG2 - DCDC Register 2
#define | DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
#define | DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
#define | DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
#define | DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
#define | DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
#define | DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
#define | DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
#define | DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
#define | DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
#define | DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
#define | DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
#define | DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
#define | DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
#define | DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
#define | DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
REG3 - DCDC Register 3
#define | DCDC_REG3_TRG_MASK (0x1FU)
#define | DCDC_REG3_TRG_SHIFT (0U)
#define | DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
#define | DCDC_REG3_TARGET_LP_MASK (0x700U)
#define | DCDC_REG3_TARGET_LP_SHIFT (8U)
#define | DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
#define | DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
#define | DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
#define | DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
#define | DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
#define | DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
#define | DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
#define | DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)
#define | DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)
#define | DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)
#define | DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
#define | DCDC_REG3_DISABLE_STEP_SHIFT (30U)
#define | DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)
CTRL - DCP control register 0
#define | DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
#define | DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
#define | DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
#define | DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
#define | DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
#define | DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
#define | DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
#define | DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
#define | DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
#define | DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
#define | DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
#define | DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
#define | DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
#define | DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
#define | DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
#define | DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
#define | DCP_CTRL_PRESENT_SHA_SHIFT (28U)
#define | DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
#define | DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
#define | DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
#define | DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
#define | DCP_CTRL_CLKGATE_MASK (0x40000000U)
#define | DCP_CTRL_CLKGATE_SHIFT (30U)
#define | DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
#define | DCP_CTRL_SFTRST_MASK (0x80000000U)
#define | DCP_CTRL_SFTRST_SHIFT (31U)
#define | DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
CTRL_SET - DCP control register 0
#define | DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
#define | DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
#define | DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
#define | DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
#define | DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
#define | DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
#define | DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
#define | DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
#define | DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
#define | DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
#define | DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
#define | DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
#define | DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
#define | DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
#define | DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
#define | DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U)
#define | DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U)
#define | DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
#define | DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U)
#define | DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U)
#define | DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
#define | DCP_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define | DCP_CTRL_SET_CLKGATE_SHIFT (30U)
#define | DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
#define | DCP_CTRL_SET_SFTRST_MASK (0x80000000U)
#define | DCP_CTRL_SET_SFTRST_SHIFT (31U)
#define | DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
CTRL_CLR - DCP control register 0
#define | DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
#define | DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
#define | DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
#define | DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
#define | DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
#define | DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
#define | DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
#define | DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
#define | DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
#define | DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
#define | DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
#define | DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
#define | DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
#define | DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
#define | DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
#define | DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U)
#define | DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U)
#define | DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
#define | DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U)
#define | DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U)
#define | DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
#define | DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define | DCP_CTRL_CLR_CLKGATE_SHIFT (30U)
#define | DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
#define | DCP_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define | DCP_CTRL_CLR_SFTRST_SHIFT (31U)
#define | DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
CTRL_TOG - DCP control register 0
#define | DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
#define | DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
#define | DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
#define | DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
#define | DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
#define | DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
#define | DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
#define | DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
#define | DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
#define | DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
#define | DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
#define | DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
#define | DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
#define | DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
#define | DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
#define | DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U)
#define | DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U)
#define | DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
#define | DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U)
#define | DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U)
#define | DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
#define | DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define | DCP_CTRL_TOG_CLKGATE_SHIFT (30U)
#define | DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
#define | DCP_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define | DCP_CTRL_TOG_SFTRST_SHIFT (31U)
#define | DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
STAT - DCP status register
#define | DCP_STAT_IRQ_MASK (0xFU)
#define | DCP_STAT_IRQ_SHIFT (0U)
#define | DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
#define | DCP_STAT_RSVD_IRQ_MASK (0x100U)
#define | DCP_STAT_RSVD_IRQ_SHIFT (8U)
#define | DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
#define | DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
#define | DCP_STAT_READY_CHANNELS_SHIFT (16U)
#define | DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
#define | DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
#define | DCP_STAT_CUR_CHANNEL_SHIFT (24U)
#define | DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
#define | DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
#define | DCP_STAT_OTP_KEY_READY_SHIFT (28U)
#define | DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
STAT_SET - DCP status register
#define | DCP_STAT_SET_IRQ_MASK (0xFU)
#define | DCP_STAT_SET_IRQ_SHIFT (0U)
#define | DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
#define | DCP_STAT_SET_RSVD_IRQ_MASK (0x100U)
#define | DCP_STAT_SET_RSVD_IRQ_SHIFT (8U)
#define | DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
#define | DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U)
#define | DCP_STAT_SET_READY_CHANNELS_SHIFT (16U)
#define | DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
#define | DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U)
#define | DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U)
#define | DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
#define | DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U)
#define | DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U)
#define | DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
STAT_CLR - DCP status register
#define | DCP_STAT_CLR_IRQ_MASK (0xFU)
#define | DCP_STAT_CLR_IRQ_SHIFT (0U)
#define | DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
#define | DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U)
#define | DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U)
#define | DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
#define | DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U)
#define | DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U)
#define | DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
#define | DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U)
#define | DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U)
#define | DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
#define | DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U)
#define | DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U)
#define | DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
STAT_TOG - DCP status register
#define | DCP_STAT_TOG_IRQ_MASK (0xFU)
#define | DCP_STAT_TOG_IRQ_SHIFT (0U)
#define | DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
#define | DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U)
#define | DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U)
#define | DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
#define | DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U)
#define | DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U)
#define | DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
#define | DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U)
#define | DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U)
#define | DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
#define | DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U)
#define | DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U)
#define | DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
CHANNELCTRL - DCP channel control register
#define | DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
#define | DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
#define | DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
#define | DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
#define | DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
#define | DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
#define | DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
#define | DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
#define | DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
#define | DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
#define | DCP_CHANNELCTRL_RSVD_SHIFT (17U)
#define | DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
CHANNELCTRL_SET - DCP channel control register
#define | DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU)
#define | DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
#define | DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
#define | DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
#define | DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
#define | DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
#define | DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U)
#define | DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
#define | DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
#define | DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U)
#define | DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U)
#define | DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
CHANNELCTRL_CLR - DCP channel control register
#define | DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU)
#define | DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
#define | DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
#define | DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
#define | DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
#define | DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
#define | DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U)
#define | DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
#define | DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
#define | DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U)
#define | DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U)
#define | DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
CHANNELCTRL_TOG - DCP channel control register
#define | DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU)
#define | DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
#define | DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
#define | DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
#define | DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
#define | DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
#define | DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U)
#define | DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
#define | DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
#define | DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U)
#define | DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U)
#define | DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
CAPABILITY0 - DCP capability 0 register
#define | DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
#define | DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
#define | DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
#define | DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
#define | DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
#define | DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
#define | DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
#define | DCP_CAPABILITY0_RSVD_SHIFT (12U)
#define | DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
#define | DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
#define | DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
#define | DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
#define | DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
#define | DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
#define | DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
CAPABILITY1 - DCP capability 1 register
#define | DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
#define | DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
#define | DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
#define | DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
#define | DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
#define | DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
CONTEXT - DCP context buffer pointer
#define | DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_CONTEXT_ADDR_SHIFT (0U)
#define | DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
KEY - DCP key index
#define | DCP_KEY_SUBWORD_MASK (0x3U)
#define | DCP_KEY_SUBWORD_SHIFT (0U)
#define | DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
#define | DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
#define | DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
#define | DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
#define | DCP_KEY_INDEX_MASK (0x30U)
#define | DCP_KEY_INDEX_SHIFT (4U)
#define | DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
#define | DCP_KEY_RSVD_INDEX_MASK (0xC0U)
#define | DCP_KEY_RSVD_INDEX_SHIFT (6U)
#define | DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
#define | DCP_KEY_RSVD_MASK (0xFFFFFF00U)
#define | DCP_KEY_RSVD_SHIFT (8U)
#define | DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
KEYDATA - DCP key data
#define | DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
#define | DCP_KEYDATA_DATA_SHIFT (0U)
#define | DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
PACKET0 - DCP work packet 0 status register
#define | DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_PACKET0_ADDR_SHIFT (0U)
#define | DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
PACKET1 - DCP work packet 1 status register
#define | DCP_PACKET1_INTERRUPT_MASK (0x1U)
#define | DCP_PACKET1_INTERRUPT_SHIFT (0U)
#define | DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
#define | DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
#define | DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
#define | DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
#define | DCP_PACKET1_CHAIN_MASK (0x4U)
#define | DCP_PACKET1_CHAIN_SHIFT (2U)
#define | DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
#define | DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
#define | DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
#define | DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
#define | DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
#define | DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
#define | DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
#define | DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
#define | DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
#define | DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
#define | DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
#define | DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
#define | DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
#define | DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
#define | DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
#define | DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
#define | DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
#define | DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
#define | DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
#define | DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
#define | DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
#define | DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
#define | DCP_PACKET1_OTP_KEY_MASK (0x400U)
#define | DCP_PACKET1_OTP_KEY_SHIFT (10U)
#define | DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
#define | DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
#define | DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
#define | DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
#define | DCP_PACKET1_HASH_INIT_MASK (0x1000U)
#define | DCP_PACKET1_HASH_INIT_SHIFT (12U)
#define | DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
#define | DCP_PACKET1_HASH_TERM_MASK (0x2000U)
#define | DCP_PACKET1_HASH_TERM_SHIFT (13U)
#define | DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
#define | DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
#define | DCP_PACKET1_CHECK_HASH_SHIFT (14U)
#define | DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
#define | DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
#define | DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
#define | DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
#define | DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
#define | DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
#define | DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
#define | DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
#define | DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
#define | DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
#define | DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
#define | DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
#define | DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
#define | DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
#define | DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
#define | DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
#define | DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
#define | DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
#define | DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
#define | DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
#define | DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
#define | DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
#define | DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
#define | DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
#define | DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
#define | DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
#define | DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
#define | DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
#define | DCP_PACKET1_TAG_MASK (0xFF000000U)
#define | DCP_PACKET1_TAG_SHIFT (24U)
#define | DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
PACKET2 - DCP work packet 2 status register
#define | DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
#define | DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
#define | DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
#define | DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
#define | DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
#define | DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
#define | DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
#define | DCP_PACKET2_KEY_SELECT_SHIFT (8U)
#define | DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
#define | DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
#define | DCP_PACKET2_HASH_SELECT_SHIFT (16U)
#define | DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
#define | DCP_PACKET2_RSVD_MASK (0xF00000U)
#define | DCP_PACKET2_RSVD_SHIFT (20U)
#define | DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
#define | DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
#define | DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
#define | DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
PACKET3 - DCP work packet 3 status register
#define | DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_PACKET3_ADDR_SHIFT (0U)
#define | DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
PACKET4 - DCP work packet 4 status register
#define | DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_PACKET4_ADDR_SHIFT (0U)
#define | DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
PACKET5 - DCP work packet 5 status register
#define | DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
#define | DCP_PACKET5_COUNT_SHIFT (0U)
#define | DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
PACKET6 - DCP work packet 6 status register
#define | DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_PACKET6_ADDR_SHIFT (0U)
#define | DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
CH0CMDPTR - DCP channel 0 command pointer address register
#define | DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_CH0CMDPTR_ADDR_SHIFT (0U)
#define | DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
CH0SEMA - DCP channel 0 semaphore register
#define | DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
#define | DCP_CH0SEMA_INCREMENT_SHIFT (0U)
#define | DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
#define | DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
#define | DCP_CH0SEMA_VALUE_SHIFT (16U)
#define | DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
CH0STAT - DCP channel 0 status register
#define | DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
#define | DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
#define | DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
#define | DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
#define | DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
#define | DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
#define | DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
#define | DCP_CH0STAT_ERROR_DST_MASK (0x20U)
#define | DCP_CH0STAT_ERROR_DST_SHIFT (5U)
#define | DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
#define | DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
#define | DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
#define | DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
#define | DCP_CH0STAT_TAG_MASK (0xFF000000U)
#define | DCP_CH0STAT_TAG_SHIFT (24U)
#define | DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
CH0STAT_SET - DCP channel 0 status register
#define | DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
#define | DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
#define | DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
#define | DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
#define | DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U)
#define | DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U)
#define | DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
#define | DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U)
#define | DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U)
#define | DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
#define | DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
#define | DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U)
#define | DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
#define | DCP_CH0STAT_SET_TAG_MASK (0xFF000000U)
#define | DCP_CH0STAT_SET_TAG_SHIFT (24U)
#define | DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
CH0STAT_CLR - DCP channel 0 status register
#define | DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
#define | DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
#define | DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
#define | DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
#define | DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U)
#define | DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U)
#define | DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
#define | DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U)
#define | DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U)
#define | DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
#define | DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
#define | DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U)
#define | DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
#define | DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U)
#define | DCP_CH0STAT_CLR_TAG_SHIFT (24U)
#define | DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
CH0STAT_TOG - DCP channel 0 status register
#define | DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
#define | DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
#define | DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
#define | DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
#define | DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U)
#define | DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U)
#define | DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
#define | DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U)
#define | DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U)
#define | DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
#define | DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
#define | DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U)
#define | DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
#define | DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U)
#define | DCP_CH0STAT_TOG_TAG_SHIFT (24U)
#define | DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
CH0OPTS - DCP channel 0 options register
#define | DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
#define | DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH0OPTS_RSVD_SHIFT (16U)
#define | DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
CH0OPTS_SET - DCP channel 0 options register
#define | DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
#define | DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH0OPTS_SET_RSVD_SHIFT (16U)
#define | DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
CH0OPTS_CLR - DCP channel 0 options register
#define | DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
#define | DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH0OPTS_CLR_RSVD_SHIFT (16U)
#define | DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
CH0OPTS_TOG - DCP channel 0 options register
#define | DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
#define | DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH0OPTS_TOG_RSVD_SHIFT (16U)
#define | DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
CH1CMDPTR - DCP channel 1 command pointer address register
#define | DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_CH1CMDPTR_ADDR_SHIFT (0U)
#define | DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
CH1SEMA - DCP channel 1 semaphore register
#define | DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
#define | DCP_CH1SEMA_INCREMENT_SHIFT (0U)
#define | DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
#define | DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
#define | DCP_CH1SEMA_VALUE_SHIFT (16U)
#define | DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
CH1STAT - DCP channel 1 status register
#define | DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
#define | DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
#define | DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
#define | DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
#define | DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
#define | DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
#define | DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
#define | DCP_CH1STAT_ERROR_DST_MASK (0x20U)
#define | DCP_CH1STAT_ERROR_DST_SHIFT (5U)
#define | DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
#define | DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
#define | DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
#define | DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
#define | DCP_CH1STAT_TAG_MASK (0xFF000000U)
#define | DCP_CH1STAT_TAG_SHIFT (24U)
#define | DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
CH1STAT_SET - DCP channel 1 status register
#define | DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
#define | DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
#define | DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
#define | DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
#define | DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U)
#define | DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U)
#define | DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
#define | DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U)
#define | DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U)
#define | DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
#define | DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
#define | DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U)
#define | DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
#define | DCP_CH1STAT_SET_TAG_MASK (0xFF000000U)
#define | DCP_CH1STAT_SET_TAG_SHIFT (24U)
#define | DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
CH1STAT_CLR - DCP channel 1 status register
#define | DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
#define | DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
#define | DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
#define | DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
#define | DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U)
#define | DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U)
#define | DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
#define | DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U)
#define | DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U)
#define | DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
#define | DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
#define | DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U)
#define | DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
#define | DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U)
#define | DCP_CH1STAT_CLR_TAG_SHIFT (24U)
#define | DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
CH1STAT_TOG - DCP channel 1 status register
#define | DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
#define | DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
#define | DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
#define | DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
#define | DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U)
#define | DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U)
#define | DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
#define | DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U)
#define | DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U)
#define | DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
#define | DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
#define | DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U)
#define | DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
#define | DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U)
#define | DCP_CH1STAT_TOG_TAG_SHIFT (24U)
#define | DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
CH1OPTS - DCP channel 1 options register
#define | DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
#define | DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH1OPTS_RSVD_SHIFT (16U)
#define | DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
CH1OPTS_SET - DCP channel 1 options register
#define | DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
#define | DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH1OPTS_SET_RSVD_SHIFT (16U)
#define | DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
CH1OPTS_CLR - DCP channel 1 options register
#define | DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
#define | DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH1OPTS_CLR_RSVD_SHIFT (16U)
#define | DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
CH1OPTS_TOG - DCP channel 1 options register
#define | DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
#define | DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH1OPTS_TOG_RSVD_SHIFT (16U)
#define | DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
CH2CMDPTR - DCP channel 2 command pointer address register
#define | DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_CH2CMDPTR_ADDR_SHIFT (0U)
#define | DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
CH2SEMA - DCP channel 2 semaphore register
#define | DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
#define | DCP_CH2SEMA_INCREMENT_SHIFT (0U)
#define | DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
#define | DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
#define | DCP_CH2SEMA_VALUE_SHIFT (16U)
#define | DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
CH2STAT - DCP channel 2 status register
#define | DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
#define | DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
#define | DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
#define | DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
#define | DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
#define | DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
#define | DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
#define | DCP_CH2STAT_ERROR_DST_MASK (0x20U)
#define | DCP_CH2STAT_ERROR_DST_SHIFT (5U)
#define | DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
#define | DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
#define | DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
#define | DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
#define | DCP_CH2STAT_TAG_MASK (0xFF000000U)
#define | DCP_CH2STAT_TAG_SHIFT (24U)
#define | DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
CH2STAT_SET - DCP channel 2 status register
#define | DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
#define | DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
#define | DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
#define | DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
#define | DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U)
#define | DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U)
#define | DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
#define | DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U)
#define | DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U)
#define | DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
#define | DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
#define | DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U)
#define | DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
#define | DCP_CH2STAT_SET_TAG_MASK (0xFF000000U)
#define | DCP_CH2STAT_SET_TAG_SHIFT (24U)
#define | DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
CH2STAT_CLR - DCP channel 2 status register
#define | DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
#define | DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
#define | DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
#define | DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
#define | DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U)
#define | DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U)
#define | DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
#define | DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U)
#define | DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U)
#define | DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
#define | DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
#define | DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U)
#define | DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
#define | DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U)
#define | DCP_CH2STAT_CLR_TAG_SHIFT (24U)
#define | DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
CH2STAT_TOG - DCP channel 2 status register
#define | DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
#define | DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
#define | DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
#define | DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
#define | DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U)
#define | DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U)
#define | DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
#define | DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U)
#define | DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U)
#define | DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
#define | DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
#define | DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U)
#define | DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
#define | DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U)
#define | DCP_CH2STAT_TOG_TAG_SHIFT (24U)
#define | DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
CH2OPTS - DCP channel 2 options register
#define | DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
#define | DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH2OPTS_RSVD_SHIFT (16U)
#define | DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
CH2OPTS_SET - DCP channel 2 options register
#define | DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
#define | DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH2OPTS_SET_RSVD_SHIFT (16U)
#define | DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
CH2OPTS_CLR - DCP channel 2 options register
#define | DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
#define | DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH2OPTS_CLR_RSVD_SHIFT (16U)
#define | DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
CH2OPTS_TOG - DCP channel 2 options register
#define | DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
#define | DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH2OPTS_TOG_RSVD_SHIFT (16U)
#define | DCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)
CH3CMDPTR - DCP channel 3 command pointer address register
#define | DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)
#define | DCP_CH3CMDPTR_ADDR_SHIFT (0U)
#define | DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
CH3SEMA - DCP channel 3 semaphore register
#define | DCP_CH3SEMA_INCREMENT_MASK (0xFFU)
#define | DCP_CH3SEMA_INCREMENT_SHIFT (0U)
#define | DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
#define | DCP_CH3SEMA_VALUE_MASK (0xFF0000U)
#define | DCP_CH3SEMA_VALUE_SHIFT (16U)
#define | DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
CH3STAT - DCP channel 3 status register
#define | DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
#define | DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
#define | DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
#define | DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
#define | DCP_CH3STAT_ERROR_SRC_MASK (0x10U)
#define | DCP_CH3STAT_ERROR_SRC_SHIFT (4U)
#define | DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
#define | DCP_CH3STAT_ERROR_DST_MASK (0x20U)
#define | DCP_CH3STAT_ERROR_DST_SHIFT (5U)
#define | DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
#define | DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
#define | DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH3STAT_ERROR_CODE_SHIFT (16U)
#define | DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
#define | DCP_CH3STAT_TAG_MASK (0xFF000000U)
#define | DCP_CH3STAT_TAG_SHIFT (24U)
#define | DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
CH3STAT_SET - DCP channel 3 status register
#define | DCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)
#define | DCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)
#define | DCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)
#define | DCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)
#define | DCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U)
#define | DCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U)
#define | DCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)
#define | DCP_CH3STAT_SET_ERROR_DST_MASK (0x20U)
#define | DCP_CH3STAT_SET_ERROR_DST_SHIFT (5U)
#define | DCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)
#define | DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)
#define | DCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U)
#define | DCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)
#define | DCP_CH3STAT_SET_TAG_MASK (0xFF000000U)
#define | DCP_CH3STAT_SET_TAG_SHIFT (24U)
#define | DCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)
CH3STAT_CLR - DCP channel 3 status register
#define | DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)
#define | DCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)
#define | DCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)
#define | DCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)
#define | DCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U)
#define | DCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U)
#define | DCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)
#define | DCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U)
#define | DCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U)
#define | DCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)
#define | DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)
#define | DCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U)
#define | DCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)
#define | DCP_CH3STAT_CLR_TAG_MASK (0xFF000000U)
#define | DCP_CH3STAT_CLR_TAG_SHIFT (24U)
#define | DCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)
CH3STAT_TOG - DCP channel 3 status register
#define | DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
#define | DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
#define | DCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)
#define | DCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U)
#define | DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U)
#define | DCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)
#define | DCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U)
#define | DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U)
#define | DCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)
#define | DCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U)
#define | DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U)
#define | DCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)
#define | DCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U)
#define | DCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U)
#define | DCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)
#define | DCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U)
#define | DCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U)
#define | DCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)
#define | DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
#define | DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
#define | DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)
#define | DCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
#define | DCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U)
#define | DCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)
#define | DCP_CH3STAT_TOG_TAG_MASK (0xFF000000U)
#define | DCP_CH3STAT_TOG_TAG_SHIFT (24U)
#define | DCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)
CH3OPTS - DCP channel 3 options register
#define | DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
#define | DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH3OPTS_RSVD_SHIFT (16U)
#define | DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
CH3OPTS_SET - DCP channel 3 options register
#define | DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)
#define | DCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH3OPTS_SET_RSVD_SHIFT (16U)
#define | DCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)
CH3OPTS_CLR - DCP channel 3 options register
#define | DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)
#define | DCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH3OPTS_CLR_RSVD_SHIFT (16U)
#define | DCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)
CH3OPTS_TOG - DCP channel 3 options register
#define | DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
#define | DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
#define | DCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)
#define | DCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U)
#define | DCP_CH3OPTS_TOG_RSVD_SHIFT (16U)
#define | DCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)
DBGSELECT - DCP debug select register
#define | DCP_DBGSELECT_INDEX_MASK (0xFFU)
#define | DCP_DBGSELECT_INDEX_SHIFT (0U)
#define | DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
#define | DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)
#define | DCP_DBGSELECT_RSVD_SHIFT (8U)
#define | DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
DBGDATA - DCP debug data register
#define | DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)
#define | DCP_DBGDATA_DATA_SHIFT (0U)
#define | DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
PAGETABLE - DCP page table register
#define | DCP_PAGETABLE_ENABLE_MASK (0x1U)
#define | DCP_PAGETABLE_ENABLE_SHIFT (0U)
#define | DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
#define | DCP_PAGETABLE_FLUSH_MASK (0x2U)
#define | DCP_PAGETABLE_FLUSH_SHIFT (1U)
#define | DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
#define | DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)
#define | DCP_PAGETABLE_BASE_SHIFT (2U)
#define | DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
VERSION - DCP version register
#define | DCP_VERSION_STEP_MASK (0xFFFFU)
#define | DCP_VERSION_STEP_SHIFT (0U)
#define | DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
#define | DCP_VERSION_MINOR_MASK (0xFF0000U)
#define | DCP_VERSION_MINOR_SHIFT (16U)
#define | DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
#define | DCP_VERSION_MAJOR_MASK (0xFF000000U)
#define | DCP_VERSION_MAJOR_SHIFT (24U)
#define | DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)
CR - Control Register
#define | DMA_CR_EDBG_MASK (0x2U)
#define | DMA_CR_EDBG_SHIFT (1U)
#define | DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
#define | DMA_CR_ERCA_MASK (0x4U)
#define | DMA_CR_ERCA_SHIFT (2U)
#define | DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
#define | DMA_CR_ERGA_MASK (0x8U)
#define | DMA_CR_ERGA_SHIFT (3U)
#define | DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
#define | DMA_CR_HOE_MASK (0x10U)
#define | DMA_CR_HOE_SHIFT (4U)
#define | DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
#define | DMA_CR_HALT_MASK (0x20U)
#define | DMA_CR_HALT_SHIFT (5U)
#define | DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
#define | DMA_CR_CLM_MASK (0x40U)
#define | DMA_CR_CLM_SHIFT (6U)
#define | DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
#define | DMA_CR_EMLM_MASK (0x80U)
#define | DMA_CR_EMLM_SHIFT (7U)
#define | DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
#define | DMA_CR_GRP0PRI_MASK (0x100U)
#define | DMA_CR_GRP0PRI_SHIFT (8U)
#define | DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
#define | DMA_CR_GRP1PRI_MASK (0x400U)
#define | DMA_CR_GRP1PRI_SHIFT (10U)
#define | DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
#define | DMA_CR_ECX_MASK (0x10000U)
#define | DMA_CR_ECX_SHIFT (16U)
#define | DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
#define | DMA_CR_CX_MASK (0x20000U)
#define | DMA_CR_CX_SHIFT (17U)
#define | DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
#define | DMA_CR_ACTIVE_MASK (0x80000000U)
#define | DMA_CR_ACTIVE_SHIFT (31U)
#define | DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
#define | LPSPI_CR_MEN_MASK (0x1U)
#define | LPSPI_CR_MEN_SHIFT (0U)
#define | LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
#define | LPSPI_CR_RST_MASK (0x2U)
#define | LPSPI_CR_RST_SHIFT (1U)
#define | LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
#define | LPSPI_CR_DOZEN_MASK (0x4U)
#define | LPSPI_CR_DOZEN_SHIFT (2U)
#define | LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
#define | LPSPI_CR_DBGEN_MASK (0x8U)
#define | LPSPI_CR_DBGEN_SHIFT (3U)
#define | LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
#define | LPSPI_CR_RTF_MASK (0x100U)
#define | LPSPI_CR_RTF_SHIFT (8U)
#define | LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
#define | LPSPI_CR_RRF_MASK (0x200U)
#define | LPSPI_CR_RRF_SHIFT (9U)
#define | LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
ES - Error Status Register
#define | DMA_ES_DBE_MASK (0x1U)
#define | DMA_ES_DBE_SHIFT (0U)
#define | DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
#define | DMA_ES_SBE_MASK (0x2U)
#define | DMA_ES_SBE_SHIFT (1U)
#define | DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
#define | DMA_ES_SGE_MASK (0x4U)
#define | DMA_ES_SGE_SHIFT (2U)
#define | DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
#define | DMA_ES_NCE_MASK (0x8U)
#define | DMA_ES_NCE_SHIFT (3U)
#define | DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
#define | DMA_ES_DOE_MASK (0x10U)
#define | DMA_ES_DOE_SHIFT (4U)
#define | DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
#define | DMA_ES_DAE_MASK (0x20U)
#define | DMA_ES_DAE_SHIFT (5U)
#define | DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
#define | DMA_ES_SOE_MASK (0x40U)
#define | DMA_ES_SOE_SHIFT (6U)
#define | DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
#define | DMA_ES_SAE_MASK (0x80U)
#define | DMA_ES_SAE_SHIFT (7U)
#define | DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
#define | DMA_ES_ERRCHN_MASK (0x1F00U)
#define | DMA_ES_ERRCHN_SHIFT (8U)
#define | DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
#define | DMA_ES_CPE_MASK (0x4000U)
#define | DMA_ES_CPE_SHIFT (14U)
#define | DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
#define | DMA_ES_GPE_MASK (0x8000U)
#define | DMA_ES_GPE_SHIFT (15U)
#define | DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
#define | DMA_ES_ECX_MASK (0x10000U)
#define | DMA_ES_ECX_SHIFT (16U)
#define | DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
#define | DMA_ES_VLD_MASK (0x80000000U)
#define | DMA_ES_VLD_SHIFT (31U)
#define | DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
ERQ - Enable Request Register
#define | DMA_ERQ_ERQ0_MASK (0x1U)
#define | DMA_ERQ_ERQ0_SHIFT (0U)
#define | DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
#define | DMA_ERQ_ERQ1_MASK (0x2U)
#define | DMA_ERQ_ERQ1_SHIFT (1U)
#define | DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
#define | DMA_ERQ_ERQ2_MASK (0x4U)
#define | DMA_ERQ_ERQ2_SHIFT (2U)
#define | DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
#define | DMA_ERQ_ERQ3_MASK (0x8U)
#define | DMA_ERQ_ERQ3_SHIFT (3U)
#define | DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
#define | DMA_ERQ_ERQ4_MASK (0x10U)
#define | DMA_ERQ_ERQ4_SHIFT (4U)
#define | DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
#define | DMA_ERQ_ERQ5_MASK (0x20U)
#define | DMA_ERQ_ERQ5_SHIFT (5U)
#define | DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
#define | DMA_ERQ_ERQ6_MASK (0x40U)
#define | DMA_ERQ_ERQ6_SHIFT (6U)
#define | DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
#define | DMA_ERQ_ERQ7_MASK (0x80U)
#define | DMA_ERQ_ERQ7_SHIFT (7U)
#define | DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
#define | DMA_ERQ_ERQ8_MASK (0x100U)
#define | DMA_ERQ_ERQ8_SHIFT (8U)
#define | DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
#define | DMA_ERQ_ERQ9_MASK (0x200U)
#define | DMA_ERQ_ERQ9_SHIFT (9U)
#define | DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
#define | DMA_ERQ_ERQ10_MASK (0x400U)
#define | DMA_ERQ_ERQ10_SHIFT (10U)
#define | DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
#define | DMA_ERQ_ERQ11_MASK (0x800U)
#define | DMA_ERQ_ERQ11_SHIFT (11U)
#define | DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
#define | DMA_ERQ_ERQ12_MASK (0x1000U)
#define | DMA_ERQ_ERQ12_SHIFT (12U)
#define | DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
#define | DMA_ERQ_ERQ13_MASK (0x2000U)
#define | DMA_ERQ_ERQ13_SHIFT (13U)
#define | DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
#define | DMA_ERQ_ERQ14_MASK (0x4000U)
#define | DMA_ERQ_ERQ14_SHIFT (14U)
#define | DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
#define | DMA_ERQ_ERQ15_MASK (0x8000U)
#define | DMA_ERQ_ERQ15_SHIFT (15U)
#define | DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
#define | DMA_ERQ_ERQ16_MASK (0x10000U)
#define | DMA_ERQ_ERQ16_SHIFT (16U)
#define | DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
#define | DMA_ERQ_ERQ17_MASK (0x20000U)
#define | DMA_ERQ_ERQ17_SHIFT (17U)
#define | DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
#define | DMA_ERQ_ERQ18_MASK (0x40000U)
#define | DMA_ERQ_ERQ18_SHIFT (18U)
#define | DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
#define | DMA_ERQ_ERQ19_MASK (0x80000U)
#define | DMA_ERQ_ERQ19_SHIFT (19U)
#define | DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
#define | DMA_ERQ_ERQ20_MASK (0x100000U)
#define | DMA_ERQ_ERQ20_SHIFT (20U)
#define | DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
#define | DMA_ERQ_ERQ21_MASK (0x200000U)
#define | DMA_ERQ_ERQ21_SHIFT (21U)
#define | DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
#define | DMA_ERQ_ERQ22_MASK (0x400000U)
#define | DMA_ERQ_ERQ22_SHIFT (22U)
#define | DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
#define | DMA_ERQ_ERQ23_MASK (0x800000U)
#define | DMA_ERQ_ERQ23_SHIFT (23U)
#define | DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
#define | DMA_ERQ_ERQ24_MASK (0x1000000U)
#define | DMA_ERQ_ERQ24_SHIFT (24U)
#define | DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
#define | DMA_ERQ_ERQ25_MASK (0x2000000U)
#define | DMA_ERQ_ERQ25_SHIFT (25U)
#define | DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
#define | DMA_ERQ_ERQ26_MASK (0x4000000U)
#define | DMA_ERQ_ERQ26_SHIFT (26U)
#define | DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
#define | DMA_ERQ_ERQ27_MASK (0x8000000U)
#define | DMA_ERQ_ERQ27_SHIFT (27U)
#define | DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
#define | DMA_ERQ_ERQ28_MASK (0x10000000U)
#define | DMA_ERQ_ERQ28_SHIFT (28U)
#define | DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
#define | DMA_ERQ_ERQ29_MASK (0x20000000U)
#define | DMA_ERQ_ERQ29_SHIFT (29U)
#define | DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
#define | DMA_ERQ_ERQ30_MASK (0x40000000U)
#define | DMA_ERQ_ERQ30_SHIFT (30U)
#define | DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
#define | DMA_ERQ_ERQ31_MASK (0x80000000U)
#define | DMA_ERQ_ERQ31_SHIFT (31U)
#define | DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
EEI - Enable Error Interrupt Register
#define | DMA_EEI_EEI0_MASK (0x1U)
#define | DMA_EEI_EEI0_SHIFT (0U)
#define | DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
#define | DMA_EEI_EEI1_MASK (0x2U)
#define | DMA_EEI_EEI1_SHIFT (1U)
#define | DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
#define | DMA_EEI_EEI2_MASK (0x4U)
#define | DMA_EEI_EEI2_SHIFT (2U)
#define | DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
#define | DMA_EEI_EEI3_MASK (0x8U)
#define | DMA_EEI_EEI3_SHIFT (3U)
#define | DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
#define | DMA_EEI_EEI4_MASK (0x10U)
#define | DMA_EEI_EEI4_SHIFT (4U)
#define | DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
#define | DMA_EEI_EEI5_MASK (0x20U)
#define | DMA_EEI_EEI5_SHIFT (5U)
#define | DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
#define | DMA_EEI_EEI6_MASK (0x40U)
#define | DMA_EEI_EEI6_SHIFT (6U)
#define | DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
#define | DMA_EEI_EEI7_MASK (0x80U)
#define | DMA_EEI_EEI7_SHIFT (7U)
#define | DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
#define | DMA_EEI_EEI8_MASK (0x100U)
#define | DMA_EEI_EEI8_SHIFT (8U)
#define | DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
#define | DMA_EEI_EEI9_MASK (0x200U)
#define | DMA_EEI_EEI9_SHIFT (9U)
#define | DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
#define | DMA_EEI_EEI10_MASK (0x400U)
#define | DMA_EEI_EEI10_SHIFT (10U)
#define | DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
#define | DMA_EEI_EEI11_MASK (0x800U)
#define | DMA_EEI_EEI11_SHIFT (11U)
#define | DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
#define | DMA_EEI_EEI12_MASK (0x1000U)
#define | DMA_EEI_EEI12_SHIFT (12U)
#define | DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
#define | DMA_EEI_EEI13_MASK (0x2000U)
#define | DMA_EEI_EEI13_SHIFT (13U)
#define | DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
#define | DMA_EEI_EEI14_MASK (0x4000U)
#define | DMA_EEI_EEI14_SHIFT (14U)
#define | DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
#define | DMA_EEI_EEI15_MASK (0x8000U)
#define | DMA_EEI_EEI15_SHIFT (15U)
#define | DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
#define | DMA_EEI_EEI16_MASK (0x10000U)
#define | DMA_EEI_EEI16_SHIFT (16U)
#define | DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
#define | DMA_EEI_EEI17_MASK (0x20000U)
#define | DMA_EEI_EEI17_SHIFT (17U)
#define | DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
#define | DMA_EEI_EEI18_MASK (0x40000U)
#define | DMA_EEI_EEI18_SHIFT (18U)
#define | DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
#define | DMA_EEI_EEI19_MASK (0x80000U)
#define | DMA_EEI_EEI19_SHIFT (19U)
#define | DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
#define | DMA_EEI_EEI20_MASK (0x100000U)
#define | DMA_EEI_EEI20_SHIFT (20U)
#define | DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
#define | DMA_EEI_EEI21_MASK (0x200000U)
#define | DMA_EEI_EEI21_SHIFT (21U)
#define | DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
#define | DMA_EEI_EEI22_MASK (0x400000U)
#define | DMA_EEI_EEI22_SHIFT (22U)
#define | DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
#define | DMA_EEI_EEI23_MASK (0x800000U)
#define | DMA_EEI_EEI23_SHIFT (23U)
#define | DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
#define | DMA_EEI_EEI24_MASK (0x1000000U)
#define | DMA_EEI_EEI24_SHIFT (24U)
#define | DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
#define | DMA_EEI_EEI25_MASK (0x2000000U)
#define | DMA_EEI_EEI25_SHIFT (25U)
#define | DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
#define | DMA_EEI_EEI26_MASK (0x4000000U)
#define | DMA_EEI_EEI26_SHIFT (26U)
#define | DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
#define | DMA_EEI_EEI27_MASK (0x8000000U)
#define | DMA_EEI_EEI27_SHIFT (27U)
#define | DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
#define | DMA_EEI_EEI28_MASK (0x10000000U)
#define | DMA_EEI_EEI28_SHIFT (28U)
#define | DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
#define | DMA_EEI_EEI29_MASK (0x20000000U)
#define | DMA_EEI_EEI29_SHIFT (29U)
#define | DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
#define | DMA_EEI_EEI30_MASK (0x40000000U)
#define | DMA_EEI_EEI30_SHIFT (30U)
#define | DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
#define | DMA_EEI_EEI31_MASK (0x80000000U)
#define | DMA_EEI_EEI31_SHIFT (31U)
#define | DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
CEEI - Clear Enable Error Interrupt Register
#define | DMA_CEEI_CEEI_MASK (0x1FU)
#define | DMA_CEEI_CEEI_SHIFT (0U)
#define | DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
#define | DMA_CEEI_CAEE_MASK (0x40U)
#define | DMA_CEEI_CAEE_SHIFT (6U)
#define | DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
#define | DMA_CEEI_NOP_MASK (0x80U)
#define | DMA_CEEI_NOP_SHIFT (7U)
#define | DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
SEEI - Set Enable Error Interrupt Register
#define | DMA_SEEI_SEEI_MASK (0x1FU)
#define | DMA_SEEI_SEEI_SHIFT (0U)
#define | DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
#define | DMA_SEEI_SAEE_MASK (0x40U)
#define | DMA_SEEI_SAEE_SHIFT (6U)
#define | DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
#define | DMA_SEEI_NOP_MASK (0x80U)
#define | DMA_SEEI_NOP_SHIFT (7U)
#define | DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
CERQ - Clear Enable Request Register
#define | DMA_CERQ_CERQ_MASK (0x1FU)
#define | DMA_CERQ_CERQ_SHIFT (0U)
#define | DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
#define | DMA_CERQ_CAER_MASK (0x40U)
#define | DMA_CERQ_CAER_SHIFT (6U)
#define | DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
#define | DMA_CERQ_NOP_MASK (0x80U)
#define | DMA_CERQ_NOP_SHIFT (7U)
#define | DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
SERQ - Set Enable Request Register
#define | DMA_SERQ_SERQ_MASK (0x1FU)
#define | DMA_SERQ_SERQ_SHIFT (0U)
#define | DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
#define | DMA_SERQ_SAER_MASK (0x40U)
#define | DMA_SERQ_SAER_SHIFT (6U)
#define | DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
#define | DMA_SERQ_NOP_MASK (0x80U)
#define | DMA_SERQ_NOP_SHIFT (7U)
#define | DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
CDNE - Clear DONE Status Bit Register
#define | DMA_CDNE_CDNE_MASK (0x1FU)
#define | DMA_CDNE_CDNE_SHIFT (0U)
#define | DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
#define | DMA_CDNE_CADN_MASK (0x40U)
#define | DMA_CDNE_CADN_SHIFT (6U)
#define | DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
#define | DMA_CDNE_NOP_MASK (0x80U)
#define | DMA_CDNE_NOP_SHIFT (7U)
#define | DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
SSRT - Set START Bit Register
#define | DMA_SSRT_SSRT_MASK (0x1FU)
#define | DMA_SSRT_SSRT_SHIFT (0U)
#define | DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
#define | DMA_SSRT_SAST_MASK (0x40U)
#define | DMA_SSRT_SAST_SHIFT (6U)
#define | DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
#define | DMA_SSRT_NOP_MASK (0x80U)
#define | DMA_SSRT_NOP_SHIFT (7U)
#define | DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
CERR - Clear Error Register
#define | DMA_CERR_CERR_MASK (0x1FU)
#define | DMA_CERR_CERR_SHIFT (0U)
#define | DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
#define | DMA_CERR_CAEI_MASK (0x40U)
#define | DMA_CERR_CAEI_SHIFT (6U)
#define | DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
#define | DMA_CERR_NOP_MASK (0x80U)
#define | DMA_CERR_NOP_SHIFT (7U)
#define | DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
CINT - Clear Interrupt Request Register
#define | DMA_CINT_CINT_MASK (0x1FU)
#define | DMA_CINT_CINT_SHIFT (0U)
#define | DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
#define | DMA_CINT_CAIR_MASK (0x40U)
#define | DMA_CINT_CAIR_SHIFT (6U)
#define | DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
#define | DMA_CINT_NOP_MASK (0x80U)
#define | DMA_CINT_NOP_SHIFT (7U)
#define | DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
INT - Interrupt Request Register
#define | DMA_INT_INT0_MASK (0x1U)
#define | DMA_INT_INT0_SHIFT (0U)
#define | DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
#define | DMA_INT_INT1_MASK (0x2U)
#define | DMA_INT_INT1_SHIFT (1U)
#define | DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
#define | DMA_INT_INT2_MASK (0x4U)
#define | DMA_INT_INT2_SHIFT (2U)
#define | DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
#define | DMA_INT_INT3_MASK (0x8U)
#define | DMA_INT_INT3_SHIFT (3U)
#define | DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
#define | DMA_INT_INT4_MASK (0x10U)
#define | DMA_INT_INT4_SHIFT (4U)
#define | DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
#define | DMA_INT_INT5_MASK (0x20U)
#define | DMA_INT_INT5_SHIFT (5U)
#define | DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
#define | DMA_INT_INT6_MASK (0x40U)
#define | DMA_INT_INT6_SHIFT (6U)
#define | DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
#define | DMA_INT_INT7_MASK (0x80U)
#define | DMA_INT_INT7_SHIFT (7U)
#define | DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
#define | DMA_INT_INT8_MASK (0x100U)
#define | DMA_INT_INT8_SHIFT (8U)
#define | DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
#define | DMA_INT_INT9_MASK (0x200U)
#define | DMA_INT_INT9_SHIFT (9U)
#define | DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
#define | DMA_INT_INT10_MASK (0x400U)
#define | DMA_INT_INT10_SHIFT (10U)
#define | DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
#define | DMA_INT_INT11_MASK (0x800U)
#define | DMA_INT_INT11_SHIFT (11U)
#define | DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
#define | DMA_INT_INT12_MASK (0x1000U)
#define | DMA_INT_INT12_SHIFT (12U)
#define | DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
#define | DMA_INT_INT13_MASK (0x2000U)
#define | DMA_INT_INT13_SHIFT (13U)
#define | DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
#define | DMA_INT_INT14_MASK (0x4000U)
#define | DMA_INT_INT14_SHIFT (14U)
#define | DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
#define | DMA_INT_INT15_MASK (0x8000U)
#define | DMA_INT_INT15_SHIFT (15U)
#define | DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
#define | DMA_INT_INT16_MASK (0x10000U)
#define | DMA_INT_INT16_SHIFT (16U)
#define | DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
#define | DMA_INT_INT17_MASK (0x20000U)
#define | DMA_INT_INT17_SHIFT (17U)
#define | DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
#define | DMA_INT_INT18_MASK (0x40000U)
#define | DMA_INT_INT18_SHIFT (18U)
#define | DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
#define | DMA_INT_INT19_MASK (0x80000U)
#define | DMA_INT_INT19_SHIFT (19U)
#define | DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
#define | DMA_INT_INT20_MASK (0x100000U)
#define | DMA_INT_INT20_SHIFT (20U)
#define | DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
#define | DMA_INT_INT21_MASK (0x200000U)
#define | DMA_INT_INT21_SHIFT (21U)
#define | DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
#define | DMA_INT_INT22_MASK (0x400000U)
#define | DMA_INT_INT22_SHIFT (22U)
#define | DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
#define | DMA_INT_INT23_MASK (0x800000U)
#define | DMA_INT_INT23_SHIFT (23U)
#define | DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
#define | DMA_INT_INT24_MASK (0x1000000U)
#define | DMA_INT_INT24_SHIFT (24U)
#define | DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
#define | DMA_INT_INT25_MASK (0x2000000U)
#define | DMA_INT_INT25_SHIFT (25U)
#define | DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
#define | DMA_INT_INT26_MASK (0x4000000U)
#define | DMA_INT_INT26_SHIFT (26U)
#define | DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
#define | DMA_INT_INT27_MASK (0x8000000U)
#define | DMA_INT_INT27_SHIFT (27U)
#define | DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
#define | DMA_INT_INT28_MASK (0x10000000U)
#define | DMA_INT_INT28_SHIFT (28U)
#define | DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
#define | DMA_INT_INT29_MASK (0x20000000U)
#define | DMA_INT_INT29_SHIFT (29U)
#define | DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
#define | DMA_INT_INT30_MASK (0x40000000U)
#define | DMA_INT_INT30_SHIFT (30U)
#define | DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
#define | DMA_INT_INT31_MASK (0x80000000U)
#define | DMA_INT_INT31_SHIFT (31U)
#define | DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
ERR - Error Register
#define | DMA_ERR_ERR0_MASK (0x1U)
#define | DMA_ERR_ERR0_SHIFT (0U)
#define | DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
#define | DMA_ERR_ERR1_MASK (0x2U)
#define | DMA_ERR_ERR1_SHIFT (1U)
#define | DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
#define | DMA_ERR_ERR2_MASK (0x4U)
#define | DMA_ERR_ERR2_SHIFT (2U)
#define | DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
#define | DMA_ERR_ERR3_MASK (0x8U)
#define | DMA_ERR_ERR3_SHIFT (3U)
#define | DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
#define | DMA_ERR_ERR4_MASK (0x10U)
#define | DMA_ERR_ERR4_SHIFT (4U)
#define | DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
#define | DMA_ERR_ERR5_MASK (0x20U)
#define | DMA_ERR_ERR5_SHIFT (5U)
#define | DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
#define | DMA_ERR_ERR6_MASK (0x40U)
#define | DMA_ERR_ERR6_SHIFT (6U)
#define | DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
#define | DMA_ERR_ERR7_MASK (0x80U)
#define | DMA_ERR_ERR7_SHIFT (7U)
#define | DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
#define | DMA_ERR_ERR8_MASK (0x100U)
#define | DMA_ERR_ERR8_SHIFT (8U)
#define | DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
#define | DMA_ERR_ERR9_MASK (0x200U)
#define | DMA_ERR_ERR9_SHIFT (9U)
#define | DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
#define | DMA_ERR_ERR10_MASK (0x400U)
#define | DMA_ERR_ERR10_SHIFT (10U)
#define | DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
#define | DMA_ERR_ERR11_MASK (0x800U)
#define | DMA_ERR_ERR11_SHIFT (11U)
#define | DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
#define | DMA_ERR_ERR12_MASK (0x1000U)
#define | DMA_ERR_ERR12_SHIFT (12U)
#define | DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
#define | DMA_ERR_ERR13_MASK (0x2000U)
#define | DMA_ERR_ERR13_SHIFT (13U)
#define | DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
#define | DMA_ERR_ERR14_MASK (0x4000U)
#define | DMA_ERR_ERR14_SHIFT (14U)
#define | DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
#define | DMA_ERR_ERR15_MASK (0x8000U)
#define | DMA_ERR_ERR15_SHIFT (15U)
#define | DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
#define | DMA_ERR_ERR16_MASK (0x10000U)
#define | DMA_ERR_ERR16_SHIFT (16U)
#define | DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
#define | DMA_ERR_ERR17_MASK (0x20000U)
#define | DMA_ERR_ERR17_SHIFT (17U)
#define | DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
#define | DMA_ERR_ERR18_MASK (0x40000U)
#define | DMA_ERR_ERR18_SHIFT (18U)
#define | DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
#define | DMA_ERR_ERR19_MASK (0x80000U)
#define | DMA_ERR_ERR19_SHIFT (19U)
#define | DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
#define | DMA_ERR_ERR20_MASK (0x100000U)
#define | DMA_ERR_ERR20_SHIFT (20U)
#define | DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
#define | DMA_ERR_ERR21_MASK (0x200000U)
#define | DMA_ERR_ERR21_SHIFT (21U)
#define | DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
#define | DMA_ERR_ERR22_MASK (0x400000U)
#define | DMA_ERR_ERR22_SHIFT (22U)
#define | DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
#define | DMA_ERR_ERR23_MASK (0x800000U)
#define | DMA_ERR_ERR23_SHIFT (23U)
#define | DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
#define | DMA_ERR_ERR24_MASK (0x1000000U)
#define | DMA_ERR_ERR24_SHIFT (24U)
#define | DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
#define | DMA_ERR_ERR25_MASK (0x2000000U)
#define | DMA_ERR_ERR25_SHIFT (25U)
#define | DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
#define | DMA_ERR_ERR26_MASK (0x4000000U)
#define | DMA_ERR_ERR26_SHIFT (26U)
#define | DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
#define | DMA_ERR_ERR27_MASK (0x8000000U)
#define | DMA_ERR_ERR27_SHIFT (27U)
#define | DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
#define | DMA_ERR_ERR28_MASK (0x10000000U)
#define | DMA_ERR_ERR28_SHIFT (28U)
#define | DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
#define | DMA_ERR_ERR29_MASK (0x20000000U)
#define | DMA_ERR_ERR29_SHIFT (29U)
#define | DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
#define | DMA_ERR_ERR30_MASK (0x40000000U)
#define | DMA_ERR_ERR30_SHIFT (30U)
#define | DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
#define | DMA_ERR_ERR31_MASK (0x80000000U)
#define | DMA_ERR_ERR31_SHIFT (31U)
#define | DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
HRS - Hardware Request Status Register
#define | DMA_HRS_HRS0_MASK (0x1U)
#define | DMA_HRS_HRS0_SHIFT (0U)
#define | DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
#define | DMA_HRS_HRS1_MASK (0x2U)
#define | DMA_HRS_HRS1_SHIFT (1U)
#define | DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
#define | DMA_HRS_HRS2_MASK (0x4U)
#define | DMA_HRS_HRS2_SHIFT (2U)
#define | DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
#define | DMA_HRS_HRS3_MASK (0x8U)
#define | DMA_HRS_HRS3_SHIFT (3U)
#define | DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
#define | DMA_HRS_HRS4_MASK (0x10U)
#define | DMA_HRS_HRS4_SHIFT (4U)
#define | DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
#define | DMA_HRS_HRS5_MASK (0x20U)
#define | DMA_HRS_HRS5_SHIFT (5U)
#define | DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
#define | DMA_HRS_HRS6_MASK (0x40U)
#define | DMA_HRS_HRS6_SHIFT (6U)
#define | DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
#define | DMA_HRS_HRS7_MASK (0x80U)
#define | DMA_HRS_HRS7_SHIFT (7U)
#define | DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
#define | DMA_HRS_HRS8_MASK (0x100U)
#define | DMA_HRS_HRS8_SHIFT (8U)
#define | DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
#define | DMA_HRS_HRS9_MASK (0x200U)
#define | DMA_HRS_HRS9_SHIFT (9U)
#define | DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
#define | DMA_HRS_HRS10_MASK (0x400U)
#define | DMA_HRS_HRS10_SHIFT (10U)
#define | DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
#define | DMA_HRS_HRS11_MASK (0x800U)
#define | DMA_HRS_HRS11_SHIFT (11U)
#define | DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
#define | DMA_HRS_HRS12_MASK (0x1000U)
#define | DMA_HRS_HRS12_SHIFT (12U)
#define | DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
#define | DMA_HRS_HRS13_MASK (0x2000U)
#define | DMA_HRS_HRS13_SHIFT (13U)
#define | DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
#define | DMA_HRS_HRS14_MASK (0x4000U)
#define | DMA_HRS_HRS14_SHIFT (14U)
#define | DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
#define | DMA_HRS_HRS15_MASK (0x8000U)
#define | DMA_HRS_HRS15_SHIFT (15U)
#define | DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
#define | DMA_HRS_HRS16_MASK (0x10000U)
#define | DMA_HRS_HRS16_SHIFT (16U)
#define | DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
#define | DMA_HRS_HRS17_MASK (0x20000U)
#define | DMA_HRS_HRS17_SHIFT (17U)
#define | DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
#define | DMA_HRS_HRS18_MASK (0x40000U)
#define | DMA_HRS_HRS18_SHIFT (18U)
#define | DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
#define | DMA_HRS_HRS19_MASK (0x80000U)
#define | DMA_HRS_HRS19_SHIFT (19U)
#define | DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
#define | DMA_HRS_HRS20_MASK (0x100000U)
#define | DMA_HRS_HRS20_SHIFT (20U)
#define | DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
#define | DMA_HRS_HRS21_MASK (0x200000U)
#define | DMA_HRS_HRS21_SHIFT (21U)
#define | DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
#define | DMA_HRS_HRS22_MASK (0x400000U)
#define | DMA_HRS_HRS22_SHIFT (22U)
#define | DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
#define | DMA_HRS_HRS23_MASK (0x800000U)
#define | DMA_HRS_HRS23_SHIFT (23U)
#define | DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
#define | DMA_HRS_HRS24_MASK (0x1000000U)
#define | DMA_HRS_HRS24_SHIFT (24U)
#define | DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
#define | DMA_HRS_HRS25_MASK (0x2000000U)
#define | DMA_HRS_HRS25_SHIFT (25U)
#define | DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
#define | DMA_HRS_HRS26_MASK (0x4000000U)
#define | DMA_HRS_HRS26_SHIFT (26U)
#define | DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
#define | DMA_HRS_HRS27_MASK (0x8000000U)
#define | DMA_HRS_HRS27_SHIFT (27U)
#define | DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
#define | DMA_HRS_HRS28_MASK (0x10000000U)
#define | DMA_HRS_HRS28_SHIFT (28U)
#define | DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
#define | DMA_HRS_HRS29_MASK (0x20000000U)
#define | DMA_HRS_HRS29_SHIFT (29U)
#define | DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
#define | DMA_HRS_HRS30_MASK (0x40000000U)
#define | DMA_HRS_HRS30_SHIFT (30U)
#define | DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
#define | DMA_HRS_HRS31_MASK (0x80000000U)
#define | DMA_HRS_HRS31_SHIFT (31U)
#define | DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
EARS - Enable Asynchronous Request in Stop Register
#define | DMA_EARS_EDREQ_0_MASK (0x1U)
#define | DMA_EARS_EDREQ_0_SHIFT (0U)
#define | DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
#define | DMA_EARS_EDREQ_1_MASK (0x2U)
#define | DMA_EARS_EDREQ_1_SHIFT (1U)
#define | DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
#define | DMA_EARS_EDREQ_2_MASK (0x4U)
#define | DMA_EARS_EDREQ_2_SHIFT (2U)
#define | DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
#define | DMA_EARS_EDREQ_3_MASK (0x8U)
#define | DMA_EARS_EDREQ_3_SHIFT (3U)
#define | DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
#define | DMA_EARS_EDREQ_4_MASK (0x10U)
#define | DMA_EARS_EDREQ_4_SHIFT (4U)
#define | DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
#define | DMA_EARS_EDREQ_5_MASK (0x20U)
#define | DMA_EARS_EDREQ_5_SHIFT (5U)
#define | DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
#define | DMA_EARS_EDREQ_6_MASK (0x40U)
#define | DMA_EARS_EDREQ_6_SHIFT (6U)
#define | DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
#define | DMA_EARS_EDREQ_7_MASK (0x80U)
#define | DMA_EARS_EDREQ_7_SHIFT (7U)
#define | DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
#define | DMA_EARS_EDREQ_8_MASK (0x100U)
#define | DMA_EARS_EDREQ_8_SHIFT (8U)
#define | DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
#define | DMA_EARS_EDREQ_9_MASK (0x200U)
#define | DMA_EARS_EDREQ_9_SHIFT (9U)
#define | DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
#define | DMA_EARS_EDREQ_10_MASK (0x400U)
#define | DMA_EARS_EDREQ_10_SHIFT (10U)
#define | DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
#define | DMA_EARS_EDREQ_11_MASK (0x800U)
#define | DMA_EARS_EDREQ_11_SHIFT (11U)
#define | DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
#define | DMA_EARS_EDREQ_12_MASK (0x1000U)
#define | DMA_EARS_EDREQ_12_SHIFT (12U)
#define | DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
#define | DMA_EARS_EDREQ_13_MASK (0x2000U)
#define | DMA_EARS_EDREQ_13_SHIFT (13U)
#define | DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
#define | DMA_EARS_EDREQ_14_MASK (0x4000U)
#define | DMA_EARS_EDREQ_14_SHIFT (14U)
#define | DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
#define | DMA_EARS_EDREQ_15_MASK (0x8000U)
#define | DMA_EARS_EDREQ_15_SHIFT (15U)
#define | DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
#define | DMA_EARS_EDREQ_16_MASK (0x10000U)
#define | DMA_EARS_EDREQ_16_SHIFT (16U)
#define | DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
#define | DMA_EARS_EDREQ_17_MASK (0x20000U)
#define | DMA_EARS_EDREQ_17_SHIFT (17U)
#define | DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
#define | DMA_EARS_EDREQ_18_MASK (0x40000U)
#define | DMA_EARS_EDREQ_18_SHIFT (18U)
#define | DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
#define | DMA_EARS_EDREQ_19_MASK (0x80000U)
#define | DMA_EARS_EDREQ_19_SHIFT (19U)
#define | DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
#define | DMA_EARS_EDREQ_20_MASK (0x100000U)
#define | DMA_EARS_EDREQ_20_SHIFT (20U)
#define | DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
#define | DMA_EARS_EDREQ_21_MASK (0x200000U)
#define | DMA_EARS_EDREQ_21_SHIFT (21U)
#define | DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
#define | DMA_EARS_EDREQ_22_MASK (0x400000U)
#define | DMA_EARS_EDREQ_22_SHIFT (22U)
#define | DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
#define | DMA_EARS_EDREQ_23_MASK (0x800000U)
#define | DMA_EARS_EDREQ_23_SHIFT (23U)
#define | DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
#define | DMA_EARS_EDREQ_24_MASK (0x1000000U)
#define | DMA_EARS_EDREQ_24_SHIFT (24U)
#define | DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
#define | DMA_EARS_EDREQ_25_MASK (0x2000000U)
#define | DMA_EARS_EDREQ_25_SHIFT (25U)
#define | DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
#define | DMA_EARS_EDREQ_26_MASK (0x4000000U)
#define | DMA_EARS_EDREQ_26_SHIFT (26U)
#define | DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
#define | DMA_EARS_EDREQ_27_MASK (0x8000000U)
#define | DMA_EARS_EDREQ_27_SHIFT (27U)
#define | DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
#define | DMA_EARS_EDREQ_28_MASK (0x10000000U)
#define | DMA_EARS_EDREQ_28_SHIFT (28U)
#define | DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
#define | DMA_EARS_EDREQ_29_MASK (0x20000000U)
#define | DMA_EARS_EDREQ_29_SHIFT (29U)
#define | DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
#define | DMA_EARS_EDREQ_30_MASK (0x40000000U)
#define | DMA_EARS_EDREQ_30_SHIFT (30U)
#define | DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
#define | DMA_EARS_EDREQ_31_MASK (0x80000000U)
#define | DMA_EARS_EDREQ_31_SHIFT (31U)
#define | DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
DCHPRI3 - Channel n Priority Register
#define | DMA_DCHPRI3_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI3_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
#define | DMA_DCHPRI3_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI3_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
#define | DMA_DCHPRI3_DPA_MASK (0x40U)
#define | DMA_DCHPRI3_DPA_SHIFT (6U)
#define | DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
#define | DMA_DCHPRI3_ECP_MASK (0x80U)
#define | DMA_DCHPRI3_ECP_SHIFT (7U)
#define | DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
DCHPRI2 - Channel n Priority Register
#define | DMA_DCHPRI2_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI2_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
#define | DMA_DCHPRI2_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI2_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
#define | DMA_DCHPRI2_DPA_MASK (0x40U)
#define | DMA_DCHPRI2_DPA_SHIFT (6U)
#define | DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
#define | DMA_DCHPRI2_ECP_MASK (0x80U)
#define | DMA_DCHPRI2_ECP_SHIFT (7U)
#define | DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
DCHPRI1 - Channel n Priority Register
#define | DMA_DCHPRI1_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI1_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
#define | DMA_DCHPRI1_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI1_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
#define | DMA_DCHPRI1_DPA_MASK (0x40U)
#define | DMA_DCHPRI1_DPA_SHIFT (6U)
#define | DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
#define | DMA_DCHPRI1_ECP_MASK (0x80U)
#define | DMA_DCHPRI1_ECP_SHIFT (7U)
#define | DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
DCHPRI0 - Channel n Priority Register
#define | DMA_DCHPRI0_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI0_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
#define | DMA_DCHPRI0_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI0_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
#define | DMA_DCHPRI0_DPA_MASK (0x40U)
#define | DMA_DCHPRI0_DPA_SHIFT (6U)
#define | DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
#define | DMA_DCHPRI0_ECP_MASK (0x80U)
#define | DMA_DCHPRI0_ECP_SHIFT (7U)
#define | DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
DCHPRI7 - Channel n Priority Register
#define | DMA_DCHPRI7_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI7_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
#define | DMA_DCHPRI7_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI7_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
#define | DMA_DCHPRI7_DPA_MASK (0x40U)
#define | DMA_DCHPRI7_DPA_SHIFT (6U)
#define | DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
#define | DMA_DCHPRI7_ECP_MASK (0x80U)
#define | DMA_DCHPRI7_ECP_SHIFT (7U)
#define | DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
DCHPRI6 - Channel n Priority Register
#define | DMA_DCHPRI6_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI6_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
#define | DMA_DCHPRI6_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI6_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
#define | DMA_DCHPRI6_DPA_MASK (0x40U)
#define | DMA_DCHPRI6_DPA_SHIFT (6U)
#define | DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
#define | DMA_DCHPRI6_ECP_MASK (0x80U)
#define | DMA_DCHPRI6_ECP_SHIFT (7U)
#define | DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
DCHPRI5 - Channel n Priority Register
#define | DMA_DCHPRI5_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI5_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
#define | DMA_DCHPRI5_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI5_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
#define | DMA_DCHPRI5_DPA_MASK (0x40U)
#define | DMA_DCHPRI5_DPA_SHIFT (6U)
#define | DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
#define | DMA_DCHPRI5_ECP_MASK (0x80U)
#define | DMA_DCHPRI5_ECP_SHIFT (7U)
#define | DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
DCHPRI4 - Channel n Priority Register
#define | DMA_DCHPRI4_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI4_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
#define | DMA_DCHPRI4_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI4_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
#define | DMA_DCHPRI4_DPA_MASK (0x40U)
#define | DMA_DCHPRI4_DPA_SHIFT (6U)
#define | DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
#define | DMA_DCHPRI4_ECP_MASK (0x80U)
#define | DMA_DCHPRI4_ECP_SHIFT (7U)
#define | DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
DCHPRI11 - Channel n Priority Register
#define | DMA_DCHPRI11_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI11_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
#define | DMA_DCHPRI11_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI11_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
#define | DMA_DCHPRI11_DPA_MASK (0x40U)
#define | DMA_DCHPRI11_DPA_SHIFT (6U)
#define | DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
#define | DMA_DCHPRI11_ECP_MASK (0x80U)
#define | DMA_DCHPRI11_ECP_SHIFT (7U)
#define | DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
DCHPRI10 - Channel n Priority Register
#define | DMA_DCHPRI10_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI10_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
#define | DMA_DCHPRI10_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI10_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
#define | DMA_DCHPRI10_DPA_MASK (0x40U)
#define | DMA_DCHPRI10_DPA_SHIFT (6U)
#define | DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
#define | DMA_DCHPRI10_ECP_MASK (0x80U)
#define | DMA_DCHPRI10_ECP_SHIFT (7U)
#define | DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
DCHPRI9 - Channel n Priority Register
#define | DMA_DCHPRI9_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI9_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
#define | DMA_DCHPRI9_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI9_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
#define | DMA_DCHPRI9_DPA_MASK (0x40U)
#define | DMA_DCHPRI9_DPA_SHIFT (6U)
#define | DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
#define | DMA_DCHPRI9_ECP_MASK (0x80U)
#define | DMA_DCHPRI9_ECP_SHIFT (7U)
#define | DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
DCHPRI8 - Channel n Priority Register
#define | DMA_DCHPRI8_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI8_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
#define | DMA_DCHPRI8_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI8_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
#define | DMA_DCHPRI8_DPA_MASK (0x40U)
#define | DMA_DCHPRI8_DPA_SHIFT (6U)
#define | DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
#define | DMA_DCHPRI8_ECP_MASK (0x80U)
#define | DMA_DCHPRI8_ECP_SHIFT (7U)
#define | DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
DCHPRI15 - Channel n Priority Register
#define | DMA_DCHPRI15_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI15_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
#define | DMA_DCHPRI15_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI15_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
#define | DMA_DCHPRI15_DPA_MASK (0x40U)
#define | DMA_DCHPRI15_DPA_SHIFT (6U)
#define | DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
#define | DMA_DCHPRI15_ECP_MASK (0x80U)
#define | DMA_DCHPRI15_ECP_SHIFT (7U)
#define | DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
DCHPRI14 - Channel n Priority Register
#define | DMA_DCHPRI14_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI14_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
#define | DMA_DCHPRI14_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI14_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
#define | DMA_DCHPRI14_DPA_MASK (0x40U)
#define | DMA_DCHPRI14_DPA_SHIFT (6U)
#define | DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
#define | DMA_DCHPRI14_ECP_MASK (0x80U)
#define | DMA_DCHPRI14_ECP_SHIFT (7U)
#define | DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
DCHPRI13 - Channel n Priority Register
#define | DMA_DCHPRI13_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI13_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
#define | DMA_DCHPRI13_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI13_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
#define | DMA_DCHPRI13_DPA_MASK (0x40U)
#define | DMA_DCHPRI13_DPA_SHIFT (6U)
#define | DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
#define | DMA_DCHPRI13_ECP_MASK (0x80U)
#define | DMA_DCHPRI13_ECP_SHIFT (7U)
#define | DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
DCHPRI12 - Channel n Priority Register
#define | DMA_DCHPRI12_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI12_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
#define | DMA_DCHPRI12_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI12_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
#define | DMA_DCHPRI12_DPA_MASK (0x40U)
#define | DMA_DCHPRI12_DPA_SHIFT (6U)
#define | DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
#define | DMA_DCHPRI12_ECP_MASK (0x80U)
#define | DMA_DCHPRI12_ECP_SHIFT (7U)
#define | DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
DCHPRI19 - Channel n Priority Register
#define | DMA_DCHPRI19_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI19_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
#define | DMA_DCHPRI19_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI19_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
#define | DMA_DCHPRI19_DPA_MASK (0x40U)
#define | DMA_DCHPRI19_DPA_SHIFT (6U)
#define | DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
#define | DMA_DCHPRI19_ECP_MASK (0x80U)
#define | DMA_DCHPRI19_ECP_SHIFT (7U)
#define | DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
DCHPRI18 - Channel n Priority Register
#define | DMA_DCHPRI18_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI18_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
#define | DMA_DCHPRI18_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI18_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
#define | DMA_DCHPRI18_DPA_MASK (0x40U)
#define | DMA_DCHPRI18_DPA_SHIFT (6U)
#define | DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
#define | DMA_DCHPRI18_ECP_MASK (0x80U)
#define | DMA_DCHPRI18_ECP_SHIFT (7U)
#define | DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
DCHPRI17 - Channel n Priority Register
#define | DMA_DCHPRI17_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI17_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
#define | DMA_DCHPRI17_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI17_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
#define | DMA_DCHPRI17_DPA_MASK (0x40U)
#define | DMA_DCHPRI17_DPA_SHIFT (6U)
#define | DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
#define | DMA_DCHPRI17_ECP_MASK (0x80U)
#define | DMA_DCHPRI17_ECP_SHIFT (7U)
#define | DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
DCHPRI16 - Channel n Priority Register
#define | DMA_DCHPRI16_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI16_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
#define | DMA_DCHPRI16_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI16_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
#define | DMA_DCHPRI16_DPA_MASK (0x40U)
#define | DMA_DCHPRI16_DPA_SHIFT (6U)
#define | DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
#define | DMA_DCHPRI16_ECP_MASK (0x80U)
#define | DMA_DCHPRI16_ECP_SHIFT (7U)
#define | DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
DCHPRI23 - Channel n Priority Register
#define | DMA_DCHPRI23_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI23_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
#define | DMA_DCHPRI23_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI23_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
#define | DMA_DCHPRI23_DPA_MASK (0x40U)
#define | DMA_DCHPRI23_DPA_SHIFT (6U)
#define | DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
#define | DMA_DCHPRI23_ECP_MASK (0x80U)
#define | DMA_DCHPRI23_ECP_SHIFT (7U)
#define | DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
DCHPRI22 - Channel n Priority Register
#define | DMA_DCHPRI22_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI22_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
#define | DMA_DCHPRI22_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI22_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
#define | DMA_DCHPRI22_DPA_MASK (0x40U)
#define | DMA_DCHPRI22_DPA_SHIFT (6U)
#define | DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
#define | DMA_DCHPRI22_ECP_MASK (0x80U)
#define | DMA_DCHPRI22_ECP_SHIFT (7U)
#define | DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
DCHPRI21 - Channel n Priority Register
#define | DMA_DCHPRI21_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI21_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
#define | DMA_DCHPRI21_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI21_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
#define | DMA_DCHPRI21_DPA_MASK (0x40U)
#define | DMA_DCHPRI21_DPA_SHIFT (6U)
#define | DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
#define | DMA_DCHPRI21_ECP_MASK (0x80U)
#define | DMA_DCHPRI21_ECP_SHIFT (7U)
#define | DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
DCHPRI20 - Channel n Priority Register
#define | DMA_DCHPRI20_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI20_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
#define | DMA_DCHPRI20_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI20_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
#define | DMA_DCHPRI20_DPA_MASK (0x40U)
#define | DMA_DCHPRI20_DPA_SHIFT (6U)
#define | DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
#define | DMA_DCHPRI20_ECP_MASK (0x80U)
#define | DMA_DCHPRI20_ECP_SHIFT (7U)
#define | DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
DCHPRI27 - Channel n Priority Register
#define | DMA_DCHPRI27_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI27_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
#define | DMA_DCHPRI27_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI27_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
#define | DMA_DCHPRI27_DPA_MASK (0x40U)
#define | DMA_DCHPRI27_DPA_SHIFT (6U)
#define | DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
#define | DMA_DCHPRI27_ECP_MASK (0x80U)
#define | DMA_DCHPRI27_ECP_SHIFT (7U)
#define | DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
DCHPRI26 - Channel n Priority Register
#define | DMA_DCHPRI26_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI26_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
#define | DMA_DCHPRI26_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI26_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
#define | DMA_DCHPRI26_DPA_MASK (0x40U)
#define | DMA_DCHPRI26_DPA_SHIFT (6U)
#define | DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
#define | DMA_DCHPRI26_ECP_MASK (0x80U)
#define | DMA_DCHPRI26_ECP_SHIFT (7U)
#define | DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
DCHPRI25 - Channel n Priority Register
#define | DMA_DCHPRI25_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI25_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
#define | DMA_DCHPRI25_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI25_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
#define | DMA_DCHPRI25_DPA_MASK (0x40U)
#define | DMA_DCHPRI25_DPA_SHIFT (6U)
#define | DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
#define | DMA_DCHPRI25_ECP_MASK (0x80U)
#define | DMA_DCHPRI25_ECP_SHIFT (7U)
#define | DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
DCHPRI24 - Channel n Priority Register
#define | DMA_DCHPRI24_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI24_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
#define | DMA_DCHPRI24_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI24_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
#define | DMA_DCHPRI24_DPA_MASK (0x40U)
#define | DMA_DCHPRI24_DPA_SHIFT (6U)
#define | DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
#define | DMA_DCHPRI24_ECP_MASK (0x80U)
#define | DMA_DCHPRI24_ECP_SHIFT (7U)
#define | DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
DCHPRI31 - Channel n Priority Register
#define | DMA_DCHPRI31_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI31_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
#define | DMA_DCHPRI31_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI31_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
#define | DMA_DCHPRI31_DPA_MASK (0x40U)
#define | DMA_DCHPRI31_DPA_SHIFT (6U)
#define | DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
#define | DMA_DCHPRI31_ECP_MASK (0x80U)
#define | DMA_DCHPRI31_ECP_SHIFT (7U)
#define | DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
DCHPRI30 - Channel n Priority Register
#define | DMA_DCHPRI30_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI30_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
#define | DMA_DCHPRI30_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI30_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
#define | DMA_DCHPRI30_DPA_MASK (0x40U)
#define | DMA_DCHPRI30_DPA_SHIFT (6U)
#define | DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
#define | DMA_DCHPRI30_ECP_MASK (0x80U)
#define | DMA_DCHPRI30_ECP_SHIFT (7U)
#define | DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
DCHPRI29 - Channel n Priority Register
#define | DMA_DCHPRI29_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI29_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
#define | DMA_DCHPRI29_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI29_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
#define | DMA_DCHPRI29_DPA_MASK (0x40U)
#define | DMA_DCHPRI29_DPA_SHIFT (6U)
#define | DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
#define | DMA_DCHPRI29_ECP_MASK (0x80U)
#define | DMA_DCHPRI29_ECP_SHIFT (7U)
#define | DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
DCHPRI28 - Channel n Priority Register
#define | DMA_DCHPRI28_CHPRI_MASK (0xFU)
#define | DMA_DCHPRI28_CHPRI_SHIFT (0U)
#define | DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
#define | DMA_DCHPRI28_GRPPRI_MASK (0x30U)
#define | DMA_DCHPRI28_GRPPRI_SHIFT (4U)
#define | DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
#define | DMA_DCHPRI28_DPA_MASK (0x40U)
#define | DMA_DCHPRI28_DPA_SHIFT (6U)
#define | DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
#define | DMA_DCHPRI28_ECP_MASK (0x80U)
#define | DMA_DCHPRI28_ECP_SHIFT (7U)
#define | DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
SADDR - TCD Source Address
#define | DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define | DMA_SADDR_SADDR_SHIFT (0U)
#define | DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
SOFF - TCD Signed Source Address Offset
#define | DMA_SOFF_SOFF_MASK (0xFFFFU)
#define | DMA_SOFF_SOFF_SHIFT (0U)
#define | DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
ATTR - TCD Transfer Attributes
#define | DMA_ATTR_DSIZE_MASK (0x7U)
#define | DMA_ATTR_DSIZE_SHIFT (0U)
#define | DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
#define | DMA_ATTR_DMOD_MASK (0xF8U)
#define | DMA_ATTR_DMOD_SHIFT (3U)
#define | DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
#define | DMA_ATTR_SSIZE_MASK (0x700U)
#define | DMA_ATTR_SSIZE_SHIFT (8U)
#define | DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
#define | DMA_ATTR_SMOD_MASK (0xF800U)
#define | DMA_ATTR_SMOD_SHIFT (11U)
#define | DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)
#define | DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
#define | DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
#define | DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
#define | DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define | DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
#define | DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define | DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define | DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
#define | DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
#define | DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define | DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
#define | DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
#define | DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define | DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
#define | DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define | DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define | DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
#define | DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define | DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define | DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
#define | DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
#define | DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define | DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
#define | DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
SLAST - TCD Last Source Address Adjustment
#define | DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
#define | DMA_SLAST_SLAST_SHIFT (0U)
#define | DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
DADDR - TCD Destination Address
#define | DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define | DMA_DADDR_DADDR_SHIFT (0U)
#define | DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
DOFF - TCD Signed Destination Address Offset
#define | DMA_DOFF_DOFF_MASK (0xFFFFU)
#define | DMA_DOFF_DOFF_SHIFT (0U)
#define | DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define | DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define | DMA_CITER_ELINKNO_CITER_SHIFT (0U)
#define | DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
#define | DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define | DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
#define | DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define | DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define | DMA_CITER_ELINKYES_CITER_SHIFT (0U)
#define | DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
#define | DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define | DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
#define | DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
#define | DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define | DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
#define | DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
#define | DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
#define | DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
#define | DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
CSR - TCD Control and Status
#define | DMA_CSR_START_MASK (0x1U)
#define | DMA_CSR_START_SHIFT (0U)
#define | DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
#define | DMA_CSR_INTMAJOR_MASK (0x2U)
#define | DMA_CSR_INTMAJOR_SHIFT (1U)
#define | DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
#define | DMA_CSR_INTHALF_MASK (0x4U)
#define | DMA_CSR_INTHALF_SHIFT (2U)
#define | DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
#define | DMA_CSR_DREQ_MASK (0x8U)
#define | DMA_CSR_DREQ_SHIFT (3U)
#define | DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
#define | DMA_CSR_ESG_MASK (0x10U)
#define | DMA_CSR_ESG_SHIFT (4U)
#define | DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
#define | DMA_CSR_MAJORELINK_MASK (0x20U)
#define | DMA_CSR_MAJORELINK_SHIFT (5U)
#define | DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
#define | DMA_CSR_ACTIVE_MASK (0x40U)
#define | DMA_CSR_ACTIVE_SHIFT (6U)
#define | DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
#define | DMA_CSR_DONE_MASK (0x80U)
#define | DMA_CSR_DONE_SHIFT (7U)
#define | DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
#define | DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
#define | DMA_CSR_MAJORLINKCH_SHIFT (8U)
#define | DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
#define | DMA_CSR_BWC_MASK (0xC000U)
#define | DMA_CSR_BWC_SHIFT (14U)
#define | DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define | DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define | DMA_BITER_ELINKNO_BITER_SHIFT (0U)
#define | DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
#define | DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define | DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
#define | DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define | DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define | DMA_BITER_ELINKYES_BITER_SHIFT (0U)
#define | DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
#define | DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define | DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
#define | DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
#define | DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define | DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
#define | DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register
#define | DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
#define | DMAMUX_CHCFG_SOURCE_SHIFT (0U)
#define | DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
#define | DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
#define | DMAMUX_CHCFG_A_ON_SHIFT (29U)
#define | DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
#define | DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
#define | DMAMUX_CHCFG_TRIG_SHIFT (30U)
#define | DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
#define | DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
#define | DMAMUX_CHCFG_ENBL_SHIFT (31U)
#define | DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
FILT - Input Filter Register
#define | ENC_FILT_FILT_PER_MASK (0xFFU)
#define | ENC_FILT_FILT_PER_SHIFT (0U)
#define | ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
#define | ENC_FILT_FILT_CNT_MASK (0x700U)
#define | ENC_FILT_FILT_CNT_SHIFT (8U)
#define | ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
WTR - Watchdog Timeout Register
#define | ENC_WTR_WDOG_MASK (0xFFFFU)
#define | ENC_WTR_WDOG_SHIFT (0U)
#define | ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
POSD - Position Difference Counter Register
#define | ENC_POSD_POSD_MASK (0xFFFFU)
#define | ENC_POSD_POSD_SHIFT (0U)
#define | ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
POSDH - Position Difference Hold Register
#define | ENC_POSDH_POSDH_MASK (0xFFFFU)
#define | ENC_POSDH_POSDH_SHIFT (0U)
#define | ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
REV - Revolution Counter Register
#define | ENC_REV_REV_MASK (0xFFFFU)
#define | ENC_REV_REV_SHIFT (0U)
#define | ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
REVH - Revolution Hold Register
#define | ENC_REVH_REVH_MASK (0xFFFFU)
#define | ENC_REVH_REVH_SHIFT (0U)
#define | ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
UPOS - Upper Position Counter Register
#define | ENC_UPOS_POS_MASK (0xFFFFU)
#define | ENC_UPOS_POS_SHIFT (0U)
#define | ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
LPOS - Lower Position Counter Register
#define | ENC_LPOS_POS_MASK (0xFFFFU)
#define | ENC_LPOS_POS_SHIFT (0U)
#define | ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
UPOSH - Upper Position Hold Register
#define | ENC_UPOSH_POSH_MASK (0xFFFFU)
#define | ENC_UPOSH_POSH_SHIFT (0U)
#define | ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
LPOSH - Lower Position Hold Register
#define | ENC_LPOSH_POSH_MASK (0xFFFFU)
#define | ENC_LPOSH_POSH_SHIFT (0U)
#define | ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
UINIT - Upper Initialization Register
#define | ENC_UINIT_INIT_MASK (0xFFFFU)
#define | ENC_UINIT_INIT_SHIFT (0U)
#define | ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
LINIT - Lower Initialization Register
#define | ENC_LINIT_INIT_MASK (0xFFFFU)
#define | ENC_LINIT_INIT_SHIFT (0U)
#define | ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
IMR - Input Monitor Register
#define | ENC_IMR_HOME_MASK (0x1U)
#define | ENC_IMR_HOME_SHIFT (0U)
#define | ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
#define | ENC_IMR_INDEX_MASK (0x2U)
#define | ENC_IMR_INDEX_SHIFT (1U)
#define | ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
#define | ENC_IMR_PHB_MASK (0x4U)
#define | ENC_IMR_PHB_SHIFT (2U)
#define | ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
#define | ENC_IMR_PHA_MASK (0x8U)
#define | ENC_IMR_PHA_SHIFT (3U)
#define | ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
#define | ENC_IMR_FHOM_MASK (0x10U)
#define | ENC_IMR_FHOM_SHIFT (4U)
#define | ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
#define | ENC_IMR_FIND_MASK (0x20U)
#define | ENC_IMR_FIND_SHIFT (5U)
#define | ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
#define | ENC_IMR_FPHB_MASK (0x40U)
#define | ENC_IMR_FPHB_SHIFT (6U)
#define | ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
#define | ENC_IMR_FPHA_MASK (0x80U)
#define | ENC_IMR_FPHA_SHIFT (7U)
#define | ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
TST - Test Register
#define | ENC_TST_TEST_COUNT_MASK (0xFFU)
#define | ENC_TST_TEST_COUNT_SHIFT (0U)
#define | ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
#define | ENC_TST_TEST_PERIOD_MASK (0x1F00U)
#define | ENC_TST_TEST_PERIOD_SHIFT (8U)
#define | ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
#define | ENC_TST_QDN_MASK (0x2000U)
#define | ENC_TST_QDN_SHIFT (13U)
#define | ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
#define | ENC_TST_TCE_MASK (0x4000U)
#define | ENC_TST_TCE_SHIFT (14U)
#define | ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
#define | ENC_TST_TEN_MASK (0x8000U)
#define | ENC_TST_TEN_SHIFT (15U)
#define | ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
CTRL2 - Control 2 Register
#define | ENC_CTRL2_UPDHLD_MASK (0x1U)
#define | ENC_CTRL2_UPDHLD_SHIFT (0U)
#define | ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
#define | ENC_CTRL2_UPDPOS_MASK (0x2U)
#define | ENC_CTRL2_UPDPOS_SHIFT (1U)
#define | ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
#define | ENC_CTRL2_MOD_MASK (0x4U)
#define | ENC_CTRL2_MOD_SHIFT (2U)
#define | ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
#define | ENC_CTRL2_DIR_MASK (0x8U)
#define | ENC_CTRL2_DIR_SHIFT (3U)
#define | ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
#define | ENC_CTRL2_RUIE_MASK (0x10U)
#define | ENC_CTRL2_RUIE_SHIFT (4U)
#define | ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
#define | ENC_CTRL2_RUIRQ_MASK (0x20U)
#define | ENC_CTRL2_RUIRQ_SHIFT (5U)
#define | ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
#define | ENC_CTRL2_ROIE_MASK (0x40U)
#define | ENC_CTRL2_ROIE_SHIFT (6U)
#define | ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
#define | ENC_CTRL2_ROIRQ_MASK (0x80U)
#define | ENC_CTRL2_ROIRQ_SHIFT (7U)
#define | ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
#define | ENC_CTRL2_REVMOD_MASK (0x100U)
#define | ENC_CTRL2_REVMOD_SHIFT (8U)
#define | ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
#define | ENC_CTRL2_OUTCTL_MASK (0x200U)
#define | ENC_CTRL2_OUTCTL_SHIFT (9U)
#define | ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
#define | ENC_CTRL2_SABIE_MASK (0x400U)
#define | ENC_CTRL2_SABIE_SHIFT (10U)
#define | ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
#define | ENC_CTRL2_SABIRQ_MASK (0x800U)
#define | ENC_CTRL2_SABIRQ_SHIFT (11U)
#define | ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
#define | PWM_CTRL2_CLK_SEL_MASK (0x3U)
#define | PWM_CTRL2_CLK_SEL_SHIFT (0U)
#define | PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
#define | PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
#define | PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
#define | PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
#define | PWM_CTRL2_FORCE_SEL_MASK (0x38U)
#define | PWM_CTRL2_FORCE_SEL_SHIFT (3U)
#define | PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
#define | PWM_CTRL2_FORCE_MASK (0x40U)
#define | PWM_CTRL2_FORCE_SHIFT (6U)
#define | PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
#define | PWM_CTRL2_FRCEN_MASK (0x80U)
#define | PWM_CTRL2_FRCEN_SHIFT (7U)
#define | PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
#define | PWM_CTRL2_INIT_SEL_MASK (0x300U)
#define | PWM_CTRL2_INIT_SEL_SHIFT (8U)
#define | PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
#define | PWM_CTRL2_PWMX_INIT_MASK (0x400U)
#define | PWM_CTRL2_PWMX_INIT_SHIFT (10U)
#define | PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
#define | PWM_CTRL2_PWM45_INIT_MASK (0x800U)
#define | PWM_CTRL2_PWM45_INIT_SHIFT (11U)
#define | PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
#define | PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
#define | PWM_CTRL2_PWM23_INIT_SHIFT (12U)
#define | PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
#define | PWM_CTRL2_INDEP_MASK (0x2000U)
#define | PWM_CTRL2_INDEP_SHIFT (13U)
#define | PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
#define | PWM_CTRL2_WAITEN_MASK (0x4000U)
#define | PWM_CTRL2_WAITEN_SHIFT (14U)
#define | PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
#define | PWM_CTRL2_DBGEN_MASK (0x8000U)
#define | PWM_CTRL2_DBGEN_SHIFT (15U)
#define | PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
UMOD - Upper Modulus Register
#define | ENC_UMOD_MOD_MASK (0xFFFFU)
#define | ENC_UMOD_MOD_SHIFT (0U)
#define | ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
LMOD - Lower Modulus Register
#define | ENC_LMOD_MOD_MASK (0xFFFFU)
#define | ENC_LMOD_MOD_SHIFT (0U)
#define | ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
UCOMP - Upper Position Compare Register
#define | ENC_UCOMP_COMP_MASK (0xFFFFU)
#define | ENC_UCOMP_COMP_SHIFT (0U)
#define | ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
LCOMP - Lower Position Compare Register
#define | ENC_LCOMP_COMP_MASK (0xFFFFU)
#define | ENC_LCOMP_COMP_SHIFT (0U)
#define | ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
EIR - Interrupt Event Register
#define | ENET_EIR_TS_TIMER_MASK (0x8000U)
#define | ENET_EIR_TS_TIMER_SHIFT (15U)
#define | ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define | ENET_EIR_TS_AVAIL_MASK (0x10000U)
#define | ENET_EIR_TS_AVAIL_SHIFT (16U)
#define | ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define | ENET_EIR_WAKEUP_MASK (0x20000U)
#define | ENET_EIR_WAKEUP_SHIFT (17U)
#define | ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define | ENET_EIR_PLR_MASK (0x40000U)
#define | ENET_EIR_PLR_SHIFT (18U)
#define | ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define | ENET_EIR_UN_MASK (0x80000U)
#define | ENET_EIR_UN_SHIFT (19U)
#define | ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define | ENET_EIR_RL_MASK (0x100000U)
#define | ENET_EIR_RL_SHIFT (20U)
#define | ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define | ENET_EIR_LC_MASK (0x200000U)
#define | ENET_EIR_LC_SHIFT (21U)
#define | ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define | ENET_EIR_EBERR_MASK (0x400000U)
#define | ENET_EIR_EBERR_SHIFT (22U)
#define | ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define | ENET_EIR_MII_MASK (0x800000U)
#define | ENET_EIR_MII_SHIFT (23U)
#define | ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define | ENET_EIR_RXB_MASK (0x1000000U)
#define | ENET_EIR_RXB_SHIFT (24U)
#define | ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define | ENET_EIR_RXF_MASK (0x2000000U)
#define | ENET_EIR_RXF_SHIFT (25U)
#define | ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define | ENET_EIR_TXB_MASK (0x4000000U)
#define | ENET_EIR_TXB_SHIFT (26U)
#define | ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define | ENET_EIR_TXF_MASK (0x8000000U)
#define | ENET_EIR_TXF_SHIFT (27U)
#define | ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define | ENET_EIR_GRA_MASK (0x10000000U)
#define | ENET_EIR_GRA_SHIFT (28U)
#define | ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define | ENET_EIR_BABT_MASK (0x20000000U)
#define | ENET_EIR_BABT_SHIFT (29U)
#define | ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define | ENET_EIR_BABR_MASK (0x40000000U)
#define | ENET_EIR_BABR_SHIFT (30U)
#define | ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
EIMR - Interrupt Mask Register
#define | ENET_EIMR_TS_TIMER_MASK (0x8000U)
#define | ENET_EIMR_TS_TIMER_SHIFT (15U)
#define | ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define | ENET_EIMR_TS_AVAIL_MASK (0x10000U)
#define | ENET_EIMR_TS_AVAIL_SHIFT (16U)
#define | ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define | ENET_EIMR_WAKEUP_MASK (0x20000U)
#define | ENET_EIMR_WAKEUP_SHIFT (17U)
#define | ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define | ENET_EIMR_PLR_MASK (0x40000U)
#define | ENET_EIMR_PLR_SHIFT (18U)
#define | ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define | ENET_EIMR_UN_MASK (0x80000U)
#define | ENET_EIMR_UN_SHIFT (19U)
#define | ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define | ENET_EIMR_RL_MASK (0x100000U)
#define | ENET_EIMR_RL_SHIFT (20U)
#define | ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define | ENET_EIMR_LC_MASK (0x200000U)
#define | ENET_EIMR_LC_SHIFT (21U)
#define | ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define | ENET_EIMR_EBERR_MASK (0x400000U)
#define | ENET_EIMR_EBERR_SHIFT (22U)
#define | ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define | ENET_EIMR_MII_MASK (0x800000U)
#define | ENET_EIMR_MII_SHIFT (23U)
#define | ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define | ENET_EIMR_RXB_MASK (0x1000000U)
#define | ENET_EIMR_RXB_SHIFT (24U)
#define | ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define | ENET_EIMR_RXF_MASK (0x2000000U)
#define | ENET_EIMR_RXF_SHIFT (25U)
#define | ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define | ENET_EIMR_TXB_MASK (0x4000000U)
#define | ENET_EIMR_TXB_SHIFT (26U)
#define | ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define | ENET_EIMR_TXF_MASK (0x8000000U)
#define | ENET_EIMR_TXF_SHIFT (27U)
#define | ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define | ENET_EIMR_GRA_MASK (0x10000000U)
#define | ENET_EIMR_GRA_SHIFT (28U)
#define | ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define | ENET_EIMR_BABT_MASK (0x20000000U)
#define | ENET_EIMR_BABT_SHIFT (29U)
#define | ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define | ENET_EIMR_BABR_MASK (0x40000000U)
#define | ENET_EIMR_BABR_SHIFT (30U)
#define | ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
RDAR - Receive Descriptor Active Register
#define | ENET_RDAR_RDAR_MASK (0x1000000U)
#define | ENET_RDAR_RDAR_SHIFT (24U)
#define | ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
TDAR - Transmit Descriptor Active Register
#define | ENET_TDAR_TDAR_MASK (0x1000000U)
#define | ENET_TDAR_TDAR_SHIFT (24U)
#define | ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
ECR - Ethernet Control Register
#define | ENET_ECR_RESET_MASK (0x1U)
#define | ENET_ECR_RESET_SHIFT (0U)
#define | ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define | ENET_ECR_ETHEREN_MASK (0x2U)
#define | ENET_ECR_ETHEREN_SHIFT (1U)
#define | ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define | ENET_ECR_MAGICEN_MASK (0x4U)
#define | ENET_ECR_MAGICEN_SHIFT (2U)
#define | ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define | ENET_ECR_SLEEP_MASK (0x8U)
#define | ENET_ECR_SLEEP_SHIFT (3U)
#define | ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define | ENET_ECR_EN1588_MASK (0x10U)
#define | ENET_ECR_EN1588_SHIFT (4U)
#define | ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define | ENET_ECR_DBGEN_MASK (0x40U)
#define | ENET_ECR_DBGEN_SHIFT (6U)
#define | ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define | ENET_ECR_DBSWP_MASK (0x100U)
#define | ENET_ECR_DBSWP_SHIFT (8U)
#define | ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
MMFR - MII Management Frame Register
#define | ENET_MMFR_DATA_MASK (0xFFFFU)
#define | ENET_MMFR_DATA_SHIFT (0U)
#define | ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define | ENET_MMFR_TA_MASK (0x30000U)
#define | ENET_MMFR_TA_SHIFT (16U)
#define | ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define | ENET_MMFR_RA_MASK (0x7C0000U)
#define | ENET_MMFR_RA_SHIFT (18U)
#define | ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define | ENET_MMFR_PA_MASK (0xF800000U)
#define | ENET_MMFR_PA_SHIFT (23U)
#define | ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define | ENET_MMFR_OP_MASK (0x30000000U)
#define | ENET_MMFR_OP_SHIFT (28U)
#define | ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define | ENET_MMFR_ST_MASK (0xC0000000U)
#define | ENET_MMFR_ST_SHIFT (30U)
#define | ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
MSCR - MII Speed Control Register
#define | ENET_MSCR_MII_SPEED_MASK (0x7EU)
#define | ENET_MSCR_MII_SPEED_SHIFT (1U)
#define | ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define | ENET_MSCR_DIS_PRE_MASK (0x80U)
#define | ENET_MSCR_DIS_PRE_SHIFT (7U)
#define | ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define | ENET_MSCR_HOLDTIME_MASK (0x700U)
#define | ENET_MSCR_HOLDTIME_SHIFT (8U)
#define | ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
MIBC - MIB Control Register
#define | ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
#define | ENET_MIBC_MIB_CLEAR_SHIFT (29U)
#define | ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define | ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
#define | ENET_MIBC_MIB_IDLE_SHIFT (30U)
#define | ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define | ENET_MIBC_MIB_DIS_MASK (0x80000000U)
#define | ENET_MIBC_MIB_DIS_SHIFT (31U)
#define | ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
RCR - Receive Control Register
#define | ENET_RCR_LOOP_MASK (0x1U)
#define | ENET_RCR_LOOP_SHIFT (0U)
#define | ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define | ENET_RCR_DRT_MASK (0x2U)
#define | ENET_RCR_DRT_SHIFT (1U)
#define | ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define | ENET_RCR_MII_MODE_MASK (0x4U)
#define | ENET_RCR_MII_MODE_SHIFT (2U)
#define | ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define | ENET_RCR_PROM_MASK (0x8U)
#define | ENET_RCR_PROM_SHIFT (3U)
#define | ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define | ENET_RCR_BC_REJ_MASK (0x10U)
#define | ENET_RCR_BC_REJ_SHIFT (4U)
#define | ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define | ENET_RCR_FCE_MASK (0x20U)
#define | ENET_RCR_FCE_SHIFT (5U)
#define | ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define | ENET_RCR_RMII_MODE_MASK (0x100U)
#define | ENET_RCR_RMII_MODE_SHIFT (8U)
#define | ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define | ENET_RCR_RMII_10T_MASK (0x200U)
#define | ENET_RCR_RMII_10T_SHIFT (9U)
#define | ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define | ENET_RCR_PADEN_MASK (0x1000U)
#define | ENET_RCR_PADEN_SHIFT (12U)
#define | ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define | ENET_RCR_PAUFWD_MASK (0x2000U)
#define | ENET_RCR_PAUFWD_SHIFT (13U)
#define | ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define | ENET_RCR_CRCFWD_MASK (0x4000U)
#define | ENET_RCR_CRCFWD_SHIFT (14U)
#define | ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define | ENET_RCR_CFEN_MASK (0x8000U)
#define | ENET_RCR_CFEN_SHIFT (15U)
#define | ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define | ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
#define | ENET_RCR_MAX_FL_SHIFT (16U)
#define | ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define | ENET_RCR_NLC_MASK (0x40000000U)
#define | ENET_RCR_NLC_SHIFT (30U)
#define | ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define | ENET_RCR_GRS_MASK (0x80000000U)
#define | ENET_RCR_GRS_SHIFT (31U)
#define | ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
TCR - Transmit Control Register
#define | ENET_TCR_GTS_MASK (0x1U)
#define | ENET_TCR_GTS_SHIFT (0U)
#define | ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define | ENET_TCR_FDEN_MASK (0x4U)
#define | ENET_TCR_FDEN_SHIFT (2U)
#define | ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define | ENET_TCR_TFC_PAUSE_MASK (0x8U)
#define | ENET_TCR_TFC_PAUSE_SHIFT (3U)
#define | ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define | ENET_TCR_RFC_PAUSE_MASK (0x10U)
#define | ENET_TCR_RFC_PAUSE_SHIFT (4U)
#define | ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define | ENET_TCR_ADDSEL_MASK (0xE0U)
#define | ENET_TCR_ADDSEL_SHIFT (5U)
#define | ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define | ENET_TCR_ADDINS_MASK (0x100U)
#define | ENET_TCR_ADDINS_SHIFT (8U)
#define | ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define | ENET_TCR_CRCFWD_MASK (0x200U)
#define | ENET_TCR_CRCFWD_SHIFT (9U)
#define | ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
PALR - Physical Address Lower Register
#define | ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
#define | ENET_PALR_PADDR1_SHIFT (0U)
#define | ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
PAUR - Physical Address Upper Register
#define | ENET_PAUR_TYPE_MASK (0xFFFFU)
#define | ENET_PAUR_TYPE_SHIFT (0U)
#define | ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define | ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
#define | ENET_PAUR_PADDR2_SHIFT (16U)
#define | ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
OPD - Opcode/Pause Duration Register
#define | ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
#define | ENET_OPD_PAUSE_DUR_SHIFT (0U)
#define | ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define | ENET_OPD_OPCODE_MASK (0xFFFF0000U)
#define | ENET_OPD_OPCODE_SHIFT (16U)
#define | ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
TXIC - Transmit Interrupt Coalescing Register
#define | ENET_TXIC_ICTT_MASK (0xFFFFU)
#define | ENET_TXIC_ICTT_SHIFT (0U)
#define | ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
#define | ENET_TXIC_ICFT_MASK (0xFF00000U)
#define | ENET_TXIC_ICFT_SHIFT (20U)
#define | ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
#define | ENET_TXIC_ICCS_MASK (0x40000000U)
#define | ENET_TXIC_ICCS_SHIFT (30U)
#define | ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
#define | ENET_TXIC_ICEN_MASK (0x80000000U)
#define | ENET_TXIC_ICEN_SHIFT (31U)
#define | ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
RXIC - Receive Interrupt Coalescing Register
#define | ENET_RXIC_ICTT_MASK (0xFFFFU)
#define | ENET_RXIC_ICTT_SHIFT (0U)
#define | ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
#define | ENET_RXIC_ICFT_MASK (0xFF00000U)
#define | ENET_RXIC_ICFT_SHIFT (20U)
#define | ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
#define | ENET_RXIC_ICCS_MASK (0x40000000U)
#define | ENET_RXIC_ICCS_SHIFT (30U)
#define | ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
#define | ENET_RXIC_ICEN_MASK (0x80000000U)
#define | ENET_RXIC_ICEN_SHIFT (31U)
#define | ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
IAUR - Descriptor Individual Upper Address Register
#define | ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
#define | ENET_IAUR_IADDR1_SHIFT (0U)
#define | ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
IALR - Descriptor Individual Lower Address Register
#define | ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
#define | ENET_IALR_IADDR2_SHIFT (0U)
#define | ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
GAUR - Descriptor Group Upper Address Register
#define | ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
#define | ENET_GAUR_GADDR1_SHIFT (0U)
#define | ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
GALR - Descriptor Group Lower Address Register
#define | ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
#define | ENET_GALR_GADDR2_SHIFT (0U)
#define | ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
TFWR - Transmit FIFO Watermark Register
#define | ENET_TFWR_TFWR_MASK (0x3FU)
#define | ENET_TFWR_TFWR_SHIFT (0U)
#define | ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define | ENET_TFWR_STRFWD_MASK (0x100U)
#define | ENET_TFWR_STRFWD_SHIFT (8U)
#define | ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
RDSR - Receive Descriptor Ring Start Register
#define | ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
#define | ENET_RDSR_R_DES_START_SHIFT (3U)
#define | ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
TDSR - Transmit Buffer Descriptor Ring Start Register
#define | ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
#define | ENET_TDSR_X_DES_START_SHIFT (3U)
#define | ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
MRBR - Maximum Receive Buffer Size Register
#define | ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
#define | ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
#define | ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
RSFL - Receive FIFO Section Full Threshold
#define | ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
#define | ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
#define | ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
RSEM - Receive FIFO Section Empty Threshold
#define | ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
#define | ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
#define | ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define | ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
#define | ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
#define | ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
RAEM - Receive FIFO Almost Empty Threshold
#define | ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
#define | ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
#define | ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
RAFL - Receive FIFO Almost Full Threshold
#define | ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
#define | ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
#define | ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
TSEM - Transmit FIFO Section Empty Threshold
#define | ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
#define | ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
#define | ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
TAEM - Transmit FIFO Almost Empty Threshold
#define | ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
#define | ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
#define | ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
TAFL - Transmit FIFO Almost Full Threshold
#define | ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
#define | ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
#define | ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
TIPG - Transmit Inter-Packet Gap
#define | ENET_TIPG_IPG_MASK (0x1FU)
#define | ENET_TIPG_IPG_SHIFT (0U)
#define | ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
FTRL - Frame Truncation Length
#define | ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
#define | ENET_FTRL_TRUNC_FL_SHIFT (0U)
#define | ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
TACC - Transmit Accelerator Function Configuration
#define | ENET_TACC_SHIFT16_MASK (0x1U)
#define | ENET_TACC_SHIFT16_SHIFT (0U)
#define | ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define | ENET_TACC_IPCHK_MASK (0x8U)
#define | ENET_TACC_IPCHK_SHIFT (3U)
#define | ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define | ENET_TACC_PROCHK_MASK (0x10U)
#define | ENET_TACC_PROCHK_SHIFT (4U)
#define | ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
RACC - Receive Accelerator Function Configuration
#define | ENET_RACC_PADREM_MASK (0x1U)
#define | ENET_RACC_PADREM_SHIFT (0U)
#define | ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define | ENET_RACC_IPDIS_MASK (0x2U)
#define | ENET_RACC_IPDIS_SHIFT (1U)
#define | ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define | ENET_RACC_PRODIS_MASK (0x4U)
#define | ENET_RACC_PRODIS_SHIFT (2U)
#define | ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define | ENET_RACC_LINEDIS_MASK (0x40U)
#define | ENET_RACC_LINEDIS_SHIFT (6U)
#define | ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define | ENET_RACC_SHIFT16_MASK (0x80U)
#define | ENET_RACC_SHIFT16_SHIFT (7U)
#define | ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
RMON_T_PACKETS - Tx Packet Count Statistic Register
#define | ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
#define | ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
#define | ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
#define | ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
#define | ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
#define | ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define | ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
#define | ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
RMON_T_COL - Tx Collision Count Statistic Register
#define | ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
RMON_T_P64 - Tx 64-Byte Packets Statistic Register
#define | ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
#define | ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
#define | ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
#define | ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
#define | ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
#define | ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
#define | ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
#define | ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
#define | ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
RMON_T_OCTETS - Tx Octets Statistic Register
#define | ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
#define | ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
#define | ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
#define | ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
#define | ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
#define | ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
#define | ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
#define | ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
#define | ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
#define | ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
#define | ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
IEEE_T_SQE - Reserved Statistic Register
#define | ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
#define | ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
#define | ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
#define | ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
#define | ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
RMON_R_PACKETS - Rx Packet Count Statistic Register
#define | ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
#define | ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
#define | ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
#define | ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
#define | ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
#define | ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
#define | ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
#define | ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
#define | ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
#define | ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
#define | ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
#define | ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define | ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
#define | ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
#define | ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_JAB_COUNT_SHIFT (0U)
#define | ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
RMON_R_P64 - Rx 64-Byte Packets Statistic Register
#define | ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_P64_COUNT_SHIFT (0U)
#define | ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
#define | ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
#define | ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
#define | ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
#define | ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
#define | ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
#define | ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
#define | ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
#define | ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
#define | ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
#define | ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
#define | ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
#define | ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
#define | ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
RMON_R_OCTETS - Rx Octets Statistic Register
#define | ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
#define | ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
#define | ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
IEEE_R_DROP - Frames not Counted Correctly Statistic Register
#define | ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
#define | ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
IEEE_R_FRAME_OK - Frames Received OK Statistic Register
#define | ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
#define | ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
IEEE_R_CRC - Frames Received with CRC Error Statistic Register
#define | ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
#define | ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
#define | ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
#define | ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
#define | ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
#define | ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
#define | ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
#define | ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
#define | ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
#define | ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
#define | ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
#define | ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
ATCR - Adjustable Timer Control Register
#define | ENET_ATCR_EN_MASK (0x1U)
#define | ENET_ATCR_EN_SHIFT (0U)
#define | ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define | ENET_ATCR_OFFEN_MASK (0x4U)
#define | ENET_ATCR_OFFEN_SHIFT (2U)
#define | ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define | ENET_ATCR_OFFRST_MASK (0x8U)
#define | ENET_ATCR_OFFRST_SHIFT (3U)
#define | ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define | ENET_ATCR_PEREN_MASK (0x10U)
#define | ENET_ATCR_PEREN_SHIFT (4U)
#define | ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define | ENET_ATCR_PINPER_MASK (0x80U)
#define | ENET_ATCR_PINPER_SHIFT (7U)
#define | ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define | ENET_ATCR_RESTART_MASK (0x200U)
#define | ENET_ATCR_RESTART_SHIFT (9U)
#define | ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define | ENET_ATCR_CAPTURE_MASK (0x800U)
#define | ENET_ATCR_CAPTURE_SHIFT (11U)
#define | ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define | ENET_ATCR_SLAVE_MASK (0x2000U)
#define | ENET_ATCR_SLAVE_SHIFT (13U)
#define | ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
ATVR - Timer Value Register
#define | ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
#define | ENET_ATVR_ATIME_SHIFT (0U)
#define | ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
ATOFF - Timer Offset Register
#define | ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
#define | ENET_ATOFF_OFFSET_SHIFT (0U)
#define | ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
ATPER - Timer Period Register
#define | ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
#define | ENET_ATPER_PERIOD_SHIFT (0U)
#define | ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
ATCOR - Timer Correction Register
#define | ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
#define | ENET_ATCOR_COR_SHIFT (0U)
#define | ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
ATINC - Time-Stamping Clock Period Register
#define | ENET_ATINC_INC_MASK (0x7FU)
#define | ENET_ATINC_INC_SHIFT (0U)
#define | ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define | ENET_ATINC_INC_CORR_MASK (0x7F00U)
#define | ENET_ATINC_INC_CORR_SHIFT (8U)
#define | ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
ATSTMP - Timestamp of Last Transmitted Frame
#define | ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
#define | ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
#define | ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
TGSR - Timer Global Status Register
#define | ENET_TGSR_TF0_MASK (0x1U)
#define | ENET_TGSR_TF0_SHIFT (0U)
#define | ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define | ENET_TGSR_TF1_MASK (0x2U)
#define | ENET_TGSR_TF1_SHIFT (1U)
#define | ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define | ENET_TGSR_TF2_MASK (0x4U)
#define | ENET_TGSR_TF2_SHIFT (2U)
#define | ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define | ENET_TGSR_TF3_MASK (0x8U)
#define | ENET_TGSR_TF3_SHIFT (3U)
#define | ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
TCSR - Timer Control Status Register
#define | ENET_TCSR_TDRE_MASK (0x1U)
#define | ENET_TCSR_TDRE_SHIFT (0U)
#define | ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define | ENET_TCSR_TMODE_MASK (0x3CU)
#define | ENET_TCSR_TMODE_SHIFT (2U)
#define | ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define | ENET_TCSR_TIE_MASK (0x40U)
#define | ENET_TCSR_TIE_SHIFT (6U)
#define | ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define | ENET_TCSR_TF_MASK (0x80U)
#define | ENET_TCSR_TF_SHIFT (7U)
#define | ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
#define | ENET_TCSR_TPWC_MASK (0xF800U)
#define | ENET_TCSR_TPWC_SHIFT (11U)
#define | ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
TCCR - Timer Compare Capture Register
#define | ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
#define | ENET_TCCR_TCC_SHIFT (0U)
#define | ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
SERV - Service Register
#define | EWM_SERV_SERVICE_MASK (0xFFU)
#define | EWM_SERV_SERVICE_SHIFT (0U)
#define | EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
CMPL - Compare Low Register
#define | EWM_CMPL_COMPAREL_MASK (0xFFU)
#define | EWM_CMPL_COMPAREL_SHIFT (0U)
#define | EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
CMPH - Compare High Register
#define | EWM_CMPH_COMPAREH_MASK (0xFFU)
#define | EWM_CMPH_COMPAREH_SHIFT (0U)
#define | EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
CLKCTRL - Clock Control Register
#define | EWM_CLKCTRL_CLKSEL_MASK (0x3U)
#define | EWM_CLKCTRL_CLKSEL_SHIFT (0U)
#define | EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
CLKPRESCALER - Clock Prescaler Register
#define | EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
#define | EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
#define | EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
VERID - Version ID Register
#define | FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
#define | FLEXIO_VERID_FEATURE_SHIFT (0U)
#define | FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define | FLEXIO_VERID_MINOR_MASK (0xFF0000U)
#define | FLEXIO_VERID_MINOR_SHIFT (16U)
#define | FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define | FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
#define | FLEXIO_VERID_MAJOR_SHIFT (24U)
#define | FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
#define | I2S_VERID_FEATURE_MASK (0xFFFFU)
#define | I2S_VERID_FEATURE_SHIFT (0U)
#define | I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
#define | I2S_VERID_MINOR_MASK (0xFF0000U)
#define | I2S_VERID_MINOR_SHIFT (16U)
#define | I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
#define | I2S_VERID_MAJOR_MASK (0xFF000000U)
#define | I2S_VERID_MAJOR_SHIFT (24U)
#define | I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
#define | LPI2C_VERID_FEATURE_MASK (0xFFFFU)
#define | LPI2C_VERID_FEATURE_SHIFT (0U)
#define | LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define | LPI2C_VERID_MINOR_MASK (0xFF0000U)
#define | LPI2C_VERID_MINOR_SHIFT (16U)
#define | LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define | LPI2C_VERID_MAJOR_MASK (0xFF000000U)
#define | LPI2C_VERID_MAJOR_SHIFT (24U)
#define | LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
#define | LPSPI_VERID_FEATURE_MASK (0xFFFFU)
#define | LPSPI_VERID_FEATURE_SHIFT (0U)
#define | LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define | LPSPI_VERID_MINOR_MASK (0xFF0000U)
#define | LPSPI_VERID_MINOR_SHIFT (16U)
#define | LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define | LPSPI_VERID_MAJOR_MASK (0xFF000000U)
#define | LPSPI_VERID_MAJOR_SHIFT (24U)
#define | LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
#define | LPUART_VERID_FEATURE_MASK (0xFFFFU)
#define | LPUART_VERID_FEATURE_SHIFT (0U)
#define | LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
#define | LPUART_VERID_MINOR_MASK (0xFF0000U)
#define | LPUART_VERID_MINOR_SHIFT (16U)
#define | LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
#define | LPUART_VERID_MAJOR_MASK (0xFF000000U)
#define | LPUART_VERID_MAJOR_SHIFT (24U)
#define | LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
PARAM - Parameter Register
#define | FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
#define | FLEXIO_PARAM_SHIFTER_SHIFT (0U)
#define | FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define | FLEXIO_PARAM_TIMER_MASK (0xFF00U)
#define | FLEXIO_PARAM_TIMER_SHIFT (8U)
#define | FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define | FLEXIO_PARAM_PIN_MASK (0xFF0000U)
#define | FLEXIO_PARAM_PIN_SHIFT (16U)
#define | FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define | FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
#define | FLEXIO_PARAM_TRIGGER_SHIFT (24U)
#define | FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
#define | I2S_PARAM_DATALINE_MASK (0xFU)
#define | I2S_PARAM_DATALINE_SHIFT (0U)
#define | I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
#define | I2S_PARAM_FIFO_MASK (0xF00U)
#define | I2S_PARAM_FIFO_SHIFT (8U)
#define | I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
#define | I2S_PARAM_FRAME_MASK (0xF0000U)
#define | I2S_PARAM_FRAME_SHIFT (16U)
#define | I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
#define | LPI2C_PARAM_MTXFIFO_MASK (0xFU)
#define | LPI2C_PARAM_MTXFIFO_SHIFT (0U)
#define | LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define | LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
#define | LPI2C_PARAM_MRXFIFO_SHIFT (8U)
#define | LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
#define | LPSPI_PARAM_TXFIFO_MASK (0xFFU)
#define | LPSPI_PARAM_TXFIFO_SHIFT (0U)
#define | LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define | LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
#define | LPSPI_PARAM_RXFIFO_SHIFT (8U)
#define | LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
#define | LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
#define | LPSPI_PARAM_PCSNUM_SHIFT (16U)
#define | LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
#define | LPUART_PARAM_TXFIFO_MASK (0xFFU)
#define | LPUART_PARAM_TXFIFO_SHIFT (0U)
#define | LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
#define | LPUART_PARAM_RXFIFO_MASK (0xFF00U)
#define | LPUART_PARAM_RXFIFO_SHIFT (8U)
#define | LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
CTRL - FlexIO Control Register
#define | FLEXIO_CTRL_FLEXEN_MASK (0x1U)
#define | FLEXIO_CTRL_FLEXEN_SHIFT (0U)
#define | FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
#define | FLEXIO_CTRL_SWRST_MASK (0x2U)
#define | FLEXIO_CTRL_SWRST_SHIFT (1U)
#define | FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
#define | FLEXIO_CTRL_FASTACC_MASK (0x4U)
#define | FLEXIO_CTRL_FASTACC_SHIFT (2U)
#define | FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
#define | FLEXIO_CTRL_DBGE_MASK (0x40000000U)
#define | FLEXIO_CTRL_DBGE_SHIFT (30U)
#define | FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
#define | FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
#define | FLEXIO_CTRL_DOZEN_SHIFT (31U)
#define | FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
PIN - Pin State Register
#define | FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
#define | FLEXIO_PIN_PDI_SHIFT (0U)
#define | FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
SHIFTSTAT - Shifter Status Register
#define | FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
#define | FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
#define | FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
SHIFTERR - Shifter Error Register
#define | FLEXIO_SHIFTERR_SEF_MASK (0xFU)
#define | FLEXIO_SHIFTERR_SEF_SHIFT (0U)
#define | FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
TIMSTAT - Timer Status Register
#define | FLEXIO_TIMSTAT_TSF_MASK (0xFU)
#define | FLEXIO_TIMSTAT_TSF_SHIFT (0U)
#define | FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
SHIFTSIEN - Shifter Status Interrupt Enable
#define | FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
#define | FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
#define | FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
SHIFTEIEN - Shifter Error Interrupt Enable
#define | FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
#define | FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
#define | FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
TIMIEN - Timer Interrupt Enable Register
#define | FLEXIO_TIMIEN_TEIE_MASK (0xFU)
#define | FLEXIO_TIMIEN_TEIE_SHIFT (0U)
#define | FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
SHIFTSDEN - Shifter Status DMA Enable
#define | FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
#define | FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
#define | FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
SHIFTSTATE - Shifter State Register
#define | FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
#define | FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
#define | FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
SHIFTCTL - Shifter Control N Register
#define | FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
#define | FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
#define | FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
#define | FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
#define | FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
#define | FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
#define | FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define | FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
#define | FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define | FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
#define | FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
#define | FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
#define | FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
#define | FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
#define | FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define | FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
#define | FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
#define | FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
SHIFTCFG - Shifter Configuration N Register
#define | FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
#define | FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
#define | FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
#define | FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
#define | FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
#define | FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
#define | FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
#define | FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
#define | FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
#define | FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define | FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
#define | FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
SHIFTBUF - Shifter Buffer N Register
#define | FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
#define | FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
#define | FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register
#define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
#define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
#define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register
#define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
#define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
#define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register
#define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
#define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
#define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
TIMCTL - Timer Control N Register
#define | FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
#define | FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
#define | FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
#define | FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
#define | FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
#define | FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
#define | FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define | FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
#define | FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define | FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
#define | FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
#define | FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
#define | FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
#define | FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
#define | FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
#define | FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
#define | FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
#define | FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
#define | FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
#define | FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
#define | FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
TIMCFG - Timer Configuration N Register
#define | FLEXIO_TIMCFG_TSTART_MASK (0x2U)
#define | FLEXIO_TIMCFG_TSTART_SHIFT (1U)
#define | FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
#define | FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
#define | FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
#define | FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
#define | FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
#define | FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
#define | FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
#define | FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
#define | FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
#define | FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
#define | FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
#define | FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
#define | FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
#define | FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
#define | FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
#define | FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
#define | FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
#define | FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
#define | FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
TIMCMP - Timer Compare N Register
#define | FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
#define | FLEXIO_TIMCMP_CMP_SHIFT (0U)
#define | FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register
#define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
#define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
#define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register
#define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
#define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
#define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register
#define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
#define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
#define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
TCM_CTRL - TCM CRTL Register
#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
INT_STATUS - Interrupt Status Register
#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
#define | TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
#define | TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
#define | TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
#define | TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
#define | TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
#define | TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
#define | TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
#define | TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
#define | TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
INT_STAT_EN - Interrupt Status Enable Register
#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
INT_SIG_EN - Interrupt Enable Register
#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
MCR0 - Module Control Register 0
#define | FLEXSPI_MCR0_SWRESET_MASK (0x1U)
#define | FLEXSPI_MCR0_SWRESET_SHIFT (0U)
#define | FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
#define | FLEXSPI_MCR0_MDIS_MASK (0x2U)
#define | FLEXSPI_MCR0_MDIS_SHIFT (1U)
#define | FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
#define | FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
#define | FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
#define | FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
#define | FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
#define | FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
#define | FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
#define | FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
#define | FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
#define | FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
#define | FLEXSPI_MCR0_HSEN_MASK (0x800U)
#define | FLEXSPI_MCR0_HSEN_SHIFT (11U)
#define | FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
#define | FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
#define | FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
#define | FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
#define | FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
#define | FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
#define | FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
#define | FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
#define | FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
#define | FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
#define | FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
#define | FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
#define | FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
#define | FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
#define | FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
#define | FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
MCR1 - Module Control Register 1
#define | FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
#define | FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
#define | FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
#define | FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
#define | FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
#define | FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
MCR2 - Module Control Register 2
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
#define | FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
#define | FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
#define | FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
#define | FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
#define | FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
#define | FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
#define | FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
#define | FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
#define | FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
#define | FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
#define | FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
#define | FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
#define | FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
AHBCR - AHB Bus Control Register
#define | FLEXSPI_AHBCR_APAREN_MASK (0x1U)
#define | FLEXSPI_AHBCR_APAREN_SHIFT (0U)
#define | FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
#define | FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
#define | FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
#define | FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
#define | FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
#define | FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
#define | FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
#define | FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
#define | FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
#define | FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
#define | FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
#define | FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
#define | FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
INTEN - Interrupt Enable Register
#define | FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
#define | FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
#define | FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
#define | FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
#define | FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
#define | FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
#define | FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
#define | FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
#define | FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
#define | FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
#define | FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
#define | FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
#define | FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
#define | FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
#define | FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
#define | FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
#define | FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
#define | FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
#define | FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
#define | FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
#define | FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
#define | FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
#define | FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
#define | FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
#define | FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
#define | FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
#define | PWM_INTEN_CMPIE_MASK (0x3FU)
#define | PWM_INTEN_CMPIE_SHIFT (0U)
#define | PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
#define | PWM_INTEN_CX0IE_MASK (0x40U)
#define | PWM_INTEN_CX0IE_SHIFT (6U)
#define | PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
#define | PWM_INTEN_CX1IE_MASK (0x80U)
#define | PWM_INTEN_CX1IE_SHIFT (7U)
#define | PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
#define | PWM_INTEN_CB0IE_MASK (0x100U)
#define | PWM_INTEN_CB0IE_SHIFT (8U)
#define | PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
#define | PWM_INTEN_CB1IE_MASK (0x200U)
#define | PWM_INTEN_CB1IE_SHIFT (9U)
#define | PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
#define | PWM_INTEN_CA0IE_MASK (0x400U)
#define | PWM_INTEN_CA0IE_SHIFT (10U)
#define | PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
#define | PWM_INTEN_CA1IE_MASK (0x800U)
#define | PWM_INTEN_CA1IE_SHIFT (11U)
#define | PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
#define | PWM_INTEN_RIE_MASK (0x1000U)
#define | PWM_INTEN_RIE_SHIFT (12U)
#define | PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
#define | PWM_INTEN_REIE_MASK (0x2000U)
#define | PWM_INTEN_REIE_SHIFT (13U)
#define | PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U)
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U)
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U)
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U)
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
INTR - Interrupt Register
#define | FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
#define | FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
#define | FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
#define | FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
#define | FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
#define | FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
#define | FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
#define | FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
#define | FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
#define | FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
#define | FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
#define | FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
#define | FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
#define | FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
#define | FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
#define | FLEXSPI_INTR_IPRXWA_MASK (0x20U)
#define | FLEXSPI_INTR_IPRXWA_SHIFT (5U)
#define | FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
#define | FLEXSPI_INTR_IPTXWE_MASK (0x40U)
#define | FLEXSPI_INTR_IPTXWE_SHIFT (6U)
#define | FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
#define | FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
#define | FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
#define | FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
#define | FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
#define | FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
#define | FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
#define | FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
#define | FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
#define | FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
#define | FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
#define | FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
#define | FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
LUTKEY - LUT Key Register
#define | FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
#define | FLEXSPI_LUTKEY_KEY_SHIFT (0U)
#define | FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
LUTCR - LUT Control Register
#define | FLEXSPI_LUTCR_LOCK_MASK (0x1U)
#define | FLEXSPI_LUTCR_LOCK_SHIFT (0U)
#define | FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
#define | FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
#define | FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
#define | FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
#define | FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0
#define | FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
#define | FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
#define | FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1
#define | FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
#define | FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
#define | FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
#define | FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
#define | FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
#define | FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
#define | FLEXSPI_FLSHCR1_WA_MASK (0x400U)
#define | FLEXSPI_FLSHCR1_WA_SHIFT (10U)
#define | FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
#define | FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
#define | FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
#define | FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
#define | FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
#define | FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
#define | FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2
#define | FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
#define | FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
#define | FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
#define | FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
#define | FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
#define | FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
#define | FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
#define | FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
#define | FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
#define | FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
#define | FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
FLSHCR4 - Flash Control Register 4
#define | FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
#define | FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
#define | FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
#define | FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
#define | FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
#define | FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
#define | FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
#define | FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
#define | FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
IPCR0 - IP Control Register 0
#define | FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
#define | FLEXSPI_IPCR0_SFAR_SHIFT (0U)
#define | FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
IPCR1 - IP Control Register 1
#define | FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
#define | FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
#define | FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
#define | FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
#define | FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
#define | FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
#define | FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
#define | FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
#define | FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
#define | FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
#define | FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
#define | FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
IPCMD - IP Command register
#define | FLEXSPI_IPCMD_TRG_MASK (0x1U)
#define | FLEXSPI_IPCMD_TRG_SHIFT (0U)
#define | FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
#define | SEMC_IPCMD_CMD_MASK (0xFFFFU)
#define | SEMC_IPCMD_CMD_SHIFT (0U)
#define | SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
#define | SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
#define | SEMC_IPCMD_KEY_SHIFT (16U)
#define | SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
IPRXFCR - IP RX FIFO Control Register
#define | FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
#define | FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
#define | FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
#define | FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
#define | FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
#define | FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
#define | FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)
#define | FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
#define | FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
IPTXFCR - IP TX FIFO Control Register
#define | FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
#define | FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
#define | FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
#define | FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
#define | FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
#define | FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
#define | FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)
#define | FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
#define | FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
DLLCR - DLL Control Register 0
#define | FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
#define | FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
#define | FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
#define | FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
#define | FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
#define | FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
#define | FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
#define | FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
#define | FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
#define | FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
#define | FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
#define | FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
#define | FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
#define | FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
#define | FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
STS0 - Status register 0
#define | FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
#define | FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
#define | FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
#define | FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
#define | FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
#define | FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
#define | FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
#define | FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
#define | FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
#define | SEMC_STS0_IDLE_MASK (0x1U)
#define | SEMC_STS0_IDLE_SHIFT (0U)
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
#define | SEMC_STS0_NARDY_MASK (0x2U)
#define | SEMC_STS0_NARDY_SHIFT (1U)
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
STS1 - Status Register 1
#define | FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
#define | FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
#define | FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
#define | FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
#define | FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
#define | FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
#define | FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
#define | FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
#define | FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
#define | FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
#define | FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
#define | FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
STS2 - Status register 2
#define | FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
#define | FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
#define | FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
#define | FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
#define | FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
#define | FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
#define | FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
#define | FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
#define | FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
#define | FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
#define | FLEXSPI_STS2_AREFSEL_SHIFT (8U)
#define | FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
#define | FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
#define | FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
#define | FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
#define | FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
#define | FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
#define | FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
#define | FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
#define | FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
#define | FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
#define | FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
#define | FLEXSPI_STS2_BREFSEL_SHIFT (24U)
#define | FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
#define | SEMC_STS2_NDWRPEND_MASK (0x8U)
#define | SEMC_STS2_NDWRPEND_SHIFT (3U)
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
AHBSPNDSTS - AHB Suspend Status Register
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
#define | FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
#define | FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
#define | FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
#define | FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
#define | FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
#define | FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
#define | FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
IPRXFSTS - IP RX FIFO Status Register
#define | FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
#define | FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
#define | FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
#define | FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
#define | FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
#define | FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
IPTXFSTS - IP TX FIFO Status Register
#define | FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
#define | FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
#define | FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
#define | FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
#define | FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
#define | FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31
#define | FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
#define | FLEXSPI_RFDR_RXDATA_SHIFT (0U)
#define | FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31
#define | FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
#define | FLEXSPI_TFDR_TXDATA_SHIFT (0U)
#define | FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
LUT - LUT 0..LUT 63
#define | FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
#define | FLEXSPI_LUT_OPERAND0_SHIFT (0U)
#define | FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define | FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
#define | FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
#define | FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
#define | FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
#define | FLEXSPI_LUT_OPCODE0_SHIFT (10U)
#define | FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
#define | FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
#define | FLEXSPI_LUT_OPERAND1_SHIFT (16U)
#define | FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
#define | FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
#define | FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
#define | FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
#define | FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
#define | FLEXSPI_LUT_OPCODE1_SHIFT (26U)
#define | FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
CNTR - GPC Interface control register
#define | GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
#define | GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
#define | GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
#define | GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
#define | GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
#define | GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
#define | GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
#define | GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
#define | GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
IMR - IRQ masking register 1..IRQ masking register 4
#define | GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
#define | GPC_IMR_IMR1_SHIFT (0U)
#define | GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
#define | GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
#define | GPC_IMR_IMR2_SHIFT (0U)
#define | GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
#define | GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
#define | GPC_IMR_IMR3_SHIFT (0U)
#define | GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
#define | GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
#define | GPC_IMR_IMR4_SHIFT (0U)
#define | GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
ISR - IRQ status resister 1..IRQ status resister 4
#define | GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
#define | GPC_ISR_ISR1_SHIFT (0U)
#define | GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
#define | GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
#define | GPC_ISR_ISR2_SHIFT (0U)
#define | GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
#define | GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
#define | GPC_ISR_ISR3_SHIFT (0U)
#define | GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
#define | GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
#define | GPC_ISR_ISR4_SHIFT (0U)
#define | GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
IMR5 - IRQ masking register 5
#define | GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
#define | GPC_IMR5_IMR5_SHIFT (0U)
#define | GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
ISR5 - IRQ status resister 5
#define | GPC_ISR5_ISR4_MASK (0xFFFFFFFFU)
#define | GPC_ISR5_ISR4_SHIFT (0U)
#define | GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)
DR - GPIO data register
#define | GPIO_DR_DR_MASK (0xFFFFFFFFU)
#define | GPIO_DR_DR_SHIFT (0U)
#define | GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
GDIR - GPIO direction register
#define | GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
#define | GPIO_GDIR_GDIR_SHIFT (0U)
#define | GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
PSR - GPIO pad status register
#define | GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
#define | GPIO_PSR_PSR_SHIFT (0U)
#define | GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
ICR1 - GPIO interrupt configuration register1
#define | GPIO_ICR1_ICR0_MASK (0x3U)
#define | GPIO_ICR1_ICR0_SHIFT (0U)
#define | GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
#define | GPIO_ICR1_ICR1_MASK (0xCU)
#define | GPIO_ICR1_ICR1_SHIFT (2U)
#define | GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
#define | GPIO_ICR1_ICR2_MASK (0x30U)
#define | GPIO_ICR1_ICR2_SHIFT (4U)
#define | GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
#define | GPIO_ICR1_ICR3_MASK (0xC0U)
#define | GPIO_ICR1_ICR3_SHIFT (6U)
#define | GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
#define | GPIO_ICR1_ICR4_MASK (0x300U)
#define | GPIO_ICR1_ICR4_SHIFT (8U)
#define | GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
#define | GPIO_ICR1_ICR5_MASK (0xC00U)
#define | GPIO_ICR1_ICR5_SHIFT (10U)
#define | GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
#define | GPIO_ICR1_ICR6_MASK (0x3000U)
#define | GPIO_ICR1_ICR6_SHIFT (12U)
#define | GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
#define | GPIO_ICR1_ICR7_MASK (0xC000U)
#define | GPIO_ICR1_ICR7_SHIFT (14U)
#define | GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
#define | GPIO_ICR1_ICR8_MASK (0x30000U)
#define | GPIO_ICR1_ICR8_SHIFT (16U)
#define | GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
#define | GPIO_ICR1_ICR9_MASK (0xC0000U)
#define | GPIO_ICR1_ICR9_SHIFT (18U)
#define | GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
#define | GPIO_ICR1_ICR10_MASK (0x300000U)
#define | GPIO_ICR1_ICR10_SHIFT (20U)
#define | GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
#define | GPIO_ICR1_ICR11_MASK (0xC00000U)
#define | GPIO_ICR1_ICR11_SHIFT (22U)
#define | GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
#define | GPIO_ICR1_ICR12_MASK (0x3000000U)
#define | GPIO_ICR1_ICR12_SHIFT (24U)
#define | GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
#define | GPIO_ICR1_ICR13_MASK (0xC000000U)
#define | GPIO_ICR1_ICR13_SHIFT (26U)
#define | GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
#define | GPIO_ICR1_ICR14_MASK (0x30000000U)
#define | GPIO_ICR1_ICR14_SHIFT (28U)
#define | GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
#define | GPIO_ICR1_ICR15_MASK (0xC0000000U)
#define | GPIO_ICR1_ICR15_SHIFT (30U)
#define | GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
ICR2 - GPIO interrupt configuration register2
#define | GPIO_ICR2_ICR16_MASK (0x3U)
#define | GPIO_ICR2_ICR16_SHIFT (0U)
#define | GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
#define | GPIO_ICR2_ICR17_MASK (0xCU)
#define | GPIO_ICR2_ICR17_SHIFT (2U)
#define | GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
#define | GPIO_ICR2_ICR18_MASK (0x30U)
#define | GPIO_ICR2_ICR18_SHIFT (4U)
#define | GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
#define | GPIO_ICR2_ICR19_MASK (0xC0U)
#define | GPIO_ICR2_ICR19_SHIFT (6U)
#define | GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
#define | GPIO_ICR2_ICR20_MASK (0x300U)
#define | GPIO_ICR2_ICR20_SHIFT (8U)
#define | GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
#define | GPIO_ICR2_ICR21_MASK (0xC00U)
#define | GPIO_ICR2_ICR21_SHIFT (10U)
#define | GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
#define | GPIO_ICR2_ICR22_MASK (0x3000U)
#define | GPIO_ICR2_ICR22_SHIFT (12U)
#define | GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
#define | GPIO_ICR2_ICR23_MASK (0xC000U)
#define | GPIO_ICR2_ICR23_SHIFT (14U)
#define | GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
#define | GPIO_ICR2_ICR24_MASK (0x30000U)
#define | GPIO_ICR2_ICR24_SHIFT (16U)
#define | GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
#define | GPIO_ICR2_ICR25_MASK (0xC0000U)
#define | GPIO_ICR2_ICR25_SHIFT (18U)
#define | GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
#define | GPIO_ICR2_ICR26_MASK (0x300000U)
#define | GPIO_ICR2_ICR26_SHIFT (20U)
#define | GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
#define | GPIO_ICR2_ICR27_MASK (0xC00000U)
#define | GPIO_ICR2_ICR27_SHIFT (22U)
#define | GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
#define | GPIO_ICR2_ICR28_MASK (0x3000000U)
#define | GPIO_ICR2_ICR28_SHIFT (24U)
#define | GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
#define | GPIO_ICR2_ICR29_MASK (0xC000000U)
#define | GPIO_ICR2_ICR29_SHIFT (26U)
#define | GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
#define | GPIO_ICR2_ICR30_MASK (0x30000000U)
#define | GPIO_ICR2_ICR30_SHIFT (28U)
#define | GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
#define | GPIO_ICR2_ICR31_MASK (0xC0000000U)
#define | GPIO_ICR2_ICR31_SHIFT (30U)
#define | GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
IMR - GPIO interrupt mask register
#define | GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
#define | GPIO_IMR_IMR_SHIFT (0U)
#define | GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
ISR - GPIO interrupt status register
#define | GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
#define | GPIO_ISR_ISR_SHIFT (0U)
#define | GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
EDGE_SEL - GPIO edge select register
#define | GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
#define | GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
#define | GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
DR_SET - GPIO data register SET
#define | GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
#define | GPIO_DR_SET_DR_SET_SHIFT (0U)
#define | GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
DR_CLEAR - GPIO data register CLEAR
#define | GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
#define | GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
#define | GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
DR_TOGGLE - GPIO data register TOGGLE
#define | GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
#define | GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
#define | GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
CR - GPT Control Register
#define | GPT_CR_EN_MASK (0x1U)
#define | GPT_CR_EN_SHIFT (0U)
#define | GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
#define | GPT_CR_ENMOD_MASK (0x2U)
#define | GPT_CR_ENMOD_SHIFT (1U)
#define | GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
#define | GPT_CR_DBGEN_MASK (0x4U)
#define | GPT_CR_DBGEN_SHIFT (2U)
#define | GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
#define | GPT_CR_WAITEN_MASK (0x8U)
#define | GPT_CR_WAITEN_SHIFT (3U)
#define | GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
#define | GPT_CR_DOZEEN_MASK (0x10U)
#define | GPT_CR_DOZEEN_SHIFT (4U)
#define | GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
#define | GPT_CR_STOPEN_MASK (0x20U)
#define | GPT_CR_STOPEN_SHIFT (5U)
#define | GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
#define | GPT_CR_CLKSRC_MASK (0x1C0U)
#define | GPT_CR_CLKSRC_SHIFT (6U)
#define | GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
#define | GPT_CR_FRR_MASK (0x200U)
#define | GPT_CR_FRR_SHIFT (9U)
#define | GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
#define | GPT_CR_EN_24M_MASK (0x400U)
#define | GPT_CR_EN_24M_SHIFT (10U)
#define | GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
#define | GPT_CR_SWR_MASK (0x8000U)
#define | GPT_CR_SWR_SHIFT (15U)
#define | GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
#define | GPT_CR_IM1_MASK (0x30000U)
#define | GPT_CR_IM1_SHIFT (16U)
#define | GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
#define | GPT_CR_IM2_MASK (0xC0000U)
#define | GPT_CR_IM2_SHIFT (18U)
#define | GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
#define | GPT_CR_OM1_MASK (0x700000U)
#define | GPT_CR_OM1_SHIFT (20U)
#define | GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
#define | GPT_CR_OM2_MASK (0x3800000U)
#define | GPT_CR_OM2_SHIFT (23U)
#define | GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
#define | GPT_CR_OM3_MASK (0x1C000000U)
#define | GPT_CR_OM3_SHIFT (26U)
#define | GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
#define | GPT_CR_FO1_MASK (0x20000000U)
#define | GPT_CR_FO1_SHIFT (29U)
#define | GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
#define | GPT_CR_FO2_MASK (0x40000000U)
#define | GPT_CR_FO2_SHIFT (30U)
#define | GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
#define | GPT_CR_FO3_MASK (0x80000000U)
#define | GPT_CR_FO3_SHIFT (31U)
#define | GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
PR - GPT Prescaler Register
#define | GPT_PR_PRESCALER_MASK (0xFFFU)
#define | GPT_PR_PRESCALER_SHIFT (0U)
#define | GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
#define | GPT_PR_PRESCALER24M_MASK (0xF000U)
#define | GPT_PR_PRESCALER24M_SHIFT (12U)
#define | GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
SR - GPT Status Register
#define | GPT_SR_OF1_MASK (0x1U)
#define | GPT_SR_OF1_SHIFT (0U)
#define | GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
#define | GPT_SR_OF2_MASK (0x2U)
#define | GPT_SR_OF2_SHIFT (1U)
#define | GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
#define | GPT_SR_OF3_MASK (0x4U)
#define | GPT_SR_OF3_SHIFT (2U)
#define | GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
#define | GPT_SR_IF1_MASK (0x8U)
#define | GPT_SR_IF1_SHIFT (3U)
#define | GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
#define | GPT_SR_IF2_MASK (0x10U)
#define | GPT_SR_IF2_SHIFT (4U)
#define | GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
#define | GPT_SR_ROV_MASK (0x20U)
#define | GPT_SR_ROV_SHIFT (5U)
#define | GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
IR - GPT Interrupt Register
#define | GPT_IR_OF1IE_MASK (0x1U)
#define | GPT_IR_OF1IE_SHIFT (0U)
#define | GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
#define | GPT_IR_OF2IE_MASK (0x2U)
#define | GPT_IR_OF2IE_SHIFT (1U)
#define | GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
#define | GPT_IR_OF3IE_MASK (0x4U)
#define | GPT_IR_OF3IE_SHIFT (2U)
#define | GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
#define | GPT_IR_IF1IE_MASK (0x8U)
#define | GPT_IR_IF1IE_SHIFT (3U)
#define | GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
#define | GPT_IR_IF2IE_MASK (0x10U)
#define | GPT_IR_IF2IE_SHIFT (4U)
#define | GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
#define | GPT_IR_ROVIE_MASK (0x20U)
#define | GPT_IR_ROVIE_SHIFT (5U)
#define | GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
OCR - GPT Output Compare Register 1..GPT Output Compare Register 3
#define | GPT_OCR_COMP_MASK (0xFFFFFFFFU)
#define | GPT_OCR_COMP_SHIFT (0U)
#define | GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
ICR - GPT Input Capture Register 1..GPT Input Capture Register 2
#define | GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
#define | GPT_ICR_CAPT_SHIFT (0U)
#define | GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
CNT - GPT Counter Register
#define | GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
#define | GPT_CNT_COUNT_SHIFT (0U)
#define | GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
TCSR - SAI Transmit Control Register
#define | I2S_TCSR_FRDE_MASK (0x1U)
#define | I2S_TCSR_FRDE_SHIFT (0U)
#define | I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define | I2S_TCSR_FWDE_MASK (0x2U)
#define | I2S_TCSR_FWDE_SHIFT (1U)
#define | I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define | I2S_TCSR_FRIE_MASK (0x100U)
#define | I2S_TCSR_FRIE_SHIFT (8U)
#define | I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define | I2S_TCSR_FWIE_MASK (0x200U)
#define | I2S_TCSR_FWIE_SHIFT (9U)
#define | I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define | I2S_TCSR_FEIE_MASK (0x400U)
#define | I2S_TCSR_FEIE_SHIFT (10U)
#define | I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define | I2S_TCSR_SEIE_MASK (0x800U)
#define | I2S_TCSR_SEIE_SHIFT (11U)
#define | I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define | I2S_TCSR_WSIE_MASK (0x1000U)
#define | I2S_TCSR_WSIE_SHIFT (12U)
#define | I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define | I2S_TCSR_FRF_MASK (0x10000U)
#define | I2S_TCSR_FRF_SHIFT (16U)
#define | I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define | I2S_TCSR_FWF_MASK (0x20000U)
#define | I2S_TCSR_FWF_SHIFT (17U)
#define | I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define | I2S_TCSR_FEF_MASK (0x40000U)
#define | I2S_TCSR_FEF_SHIFT (18U)
#define | I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define | I2S_TCSR_SEF_MASK (0x80000U)
#define | I2S_TCSR_SEF_SHIFT (19U)
#define | I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define | I2S_TCSR_WSF_MASK (0x100000U)
#define | I2S_TCSR_WSF_SHIFT (20U)
#define | I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define | I2S_TCSR_SR_MASK (0x1000000U)
#define | I2S_TCSR_SR_SHIFT (24U)
#define | I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define | I2S_TCSR_FR_MASK (0x2000000U)
#define | I2S_TCSR_FR_SHIFT (25U)
#define | I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define | I2S_TCSR_BCE_MASK (0x10000000U)
#define | I2S_TCSR_BCE_SHIFT (28U)
#define | I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define | I2S_TCSR_DBGE_MASK (0x20000000U)
#define | I2S_TCSR_DBGE_SHIFT (29U)
#define | I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define | I2S_TCSR_STOPE_MASK (0x40000000U)
#define | I2S_TCSR_STOPE_SHIFT (30U)
#define | I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define | I2S_TCSR_TE_MASK (0x80000000U)
#define | I2S_TCSR_TE_SHIFT (31U)
#define | I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
TCR1 - SAI Transmit Configuration 1 Register
#define | I2S_TCR1_TFW_MASK (0x1FU)
#define | I2S_TCR1_TFW_SHIFT (0U)
#define | I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
TCR2 - SAI Transmit Configuration 2 Register
#define | I2S_TCR2_DIV_MASK (0xFFU)
#define | I2S_TCR2_DIV_SHIFT (0U)
#define | I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define | I2S_TCR2_BCD_MASK (0x1000000U)
#define | I2S_TCR2_BCD_SHIFT (24U)
#define | I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define | I2S_TCR2_BCP_MASK (0x2000000U)
#define | I2S_TCR2_BCP_SHIFT (25U)
#define | I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define | I2S_TCR2_MSEL_MASK (0xC000000U)
#define | I2S_TCR2_MSEL_SHIFT (26U)
#define | I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define | I2S_TCR2_BCI_MASK (0x10000000U)
#define | I2S_TCR2_BCI_SHIFT (28U)
#define | I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define | I2S_TCR2_BCS_MASK (0x20000000U)
#define | I2S_TCR2_BCS_SHIFT (29U)
#define | I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define | I2S_TCR2_SYNC_MASK (0xC0000000U)
#define | I2S_TCR2_SYNC_SHIFT (30U)
#define | I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
TCR3 - SAI Transmit Configuration 3 Register
#define | I2S_TCR3_WDFL_MASK (0x1FU)
#define | I2S_TCR3_WDFL_SHIFT (0U)
#define | I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define | I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define | I2S_TCR3_TCE_SHIFT (16U)
#define | I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define | I2S_TCR3_CFR_MASK (0xF000000U)
#define | I2S_TCR3_CFR_SHIFT (24U)
#define | I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
TCR4 - SAI Transmit Configuration 4 Register
#define | I2S_TCR4_FSD_MASK (0x1U)
#define | I2S_TCR4_FSD_SHIFT (0U)
#define | I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define | I2S_TCR4_FSP_MASK (0x2U)
#define | I2S_TCR4_FSP_SHIFT (1U)
#define | I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define | I2S_TCR4_ONDEM_MASK (0x4U)
#define | I2S_TCR4_ONDEM_SHIFT (2U)
#define | I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define | I2S_TCR4_FSE_MASK (0x8U)
#define | I2S_TCR4_FSE_SHIFT (3U)
#define | I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define | I2S_TCR4_MF_MASK (0x10U)
#define | I2S_TCR4_MF_SHIFT (4U)
#define | I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define | I2S_TCR4_CHMOD_MASK (0x20U)
#define | I2S_TCR4_CHMOD_SHIFT (5U)
#define | I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
#define | I2S_TCR4_SYWD_MASK (0x1F00U)
#define | I2S_TCR4_SYWD_SHIFT (8U)
#define | I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define | I2S_TCR4_FRSZ_MASK (0x1F0000U)
#define | I2S_TCR4_FRSZ_SHIFT (16U)
#define | I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define | I2S_TCR4_FPACK_MASK (0x3000000U)
#define | I2S_TCR4_FPACK_SHIFT (24U)
#define | I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define | I2S_TCR4_FCOMB_MASK (0xC000000U)
#define | I2S_TCR4_FCOMB_SHIFT (26U)
#define | I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define | I2S_TCR4_FCONT_MASK (0x10000000U)
#define | I2S_TCR4_FCONT_SHIFT (28U)
#define | I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
TCR5 - SAI Transmit Configuration 5 Register
#define | I2S_TCR5_FBT_MASK (0x1F00U)
#define | I2S_TCR5_FBT_SHIFT (8U)
#define | I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define | I2S_TCR5_W0W_MASK (0x1F0000U)
#define | I2S_TCR5_W0W_SHIFT (16U)
#define | I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define | I2S_TCR5_WNW_MASK (0x1F000000U)
#define | I2S_TCR5_WNW_SHIFT (24U)
#define | I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
TDR - SAI Transmit Data Register
#define | I2S_TDR_TDR_MASK (0xFFFFFFFFU)
#define | I2S_TDR_TDR_SHIFT (0U)
#define | I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
TFR - SAI Transmit FIFO Register
#define | I2S_TFR_RFP_MASK (0x3FU)
#define | I2S_TFR_RFP_SHIFT (0U)
#define | I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define | I2S_TFR_WFP_MASK (0x3F0000U)
#define | I2S_TFR_WFP_SHIFT (16U)
#define | I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define | I2S_TFR_WCP_MASK (0x80000000U)
#define | I2S_TFR_WCP_SHIFT (31U)
#define | I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
TMR - SAI Transmit Mask Register
#define | I2S_TMR_TWM_MASK (0xFFFFFFFFU)
#define | I2S_TMR_TWM_SHIFT (0U)
#define | I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
RCSR - SAI Receive Control Register
#define | I2S_RCSR_FRDE_MASK (0x1U)
#define | I2S_RCSR_FRDE_SHIFT (0U)
#define | I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define | I2S_RCSR_FWDE_MASK (0x2U)
#define | I2S_RCSR_FWDE_SHIFT (1U)
#define | I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define | I2S_RCSR_FRIE_MASK (0x100U)
#define | I2S_RCSR_FRIE_SHIFT (8U)
#define | I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define | I2S_RCSR_FWIE_MASK (0x200U)
#define | I2S_RCSR_FWIE_SHIFT (9U)
#define | I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define | I2S_RCSR_FEIE_MASK (0x400U)
#define | I2S_RCSR_FEIE_SHIFT (10U)
#define | I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define | I2S_RCSR_SEIE_MASK (0x800U)
#define | I2S_RCSR_SEIE_SHIFT (11U)
#define | I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define | I2S_RCSR_WSIE_MASK (0x1000U)
#define | I2S_RCSR_WSIE_SHIFT (12U)
#define | I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define | I2S_RCSR_FRF_MASK (0x10000U)
#define | I2S_RCSR_FRF_SHIFT (16U)
#define | I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define | I2S_RCSR_FWF_MASK (0x20000U)
#define | I2S_RCSR_FWF_SHIFT (17U)
#define | I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define | I2S_RCSR_FEF_MASK (0x40000U)
#define | I2S_RCSR_FEF_SHIFT (18U)
#define | I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define | I2S_RCSR_SEF_MASK (0x80000U)
#define | I2S_RCSR_SEF_SHIFT (19U)
#define | I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define | I2S_RCSR_WSF_MASK (0x100000U)
#define | I2S_RCSR_WSF_SHIFT (20U)
#define | I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define | I2S_RCSR_SR_MASK (0x1000000U)
#define | I2S_RCSR_SR_SHIFT (24U)
#define | I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define | I2S_RCSR_FR_MASK (0x2000000U)
#define | I2S_RCSR_FR_SHIFT (25U)
#define | I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define | I2S_RCSR_BCE_MASK (0x10000000U)
#define | I2S_RCSR_BCE_SHIFT (28U)
#define | I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define | I2S_RCSR_DBGE_MASK (0x20000000U)
#define | I2S_RCSR_DBGE_SHIFT (29U)
#define | I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define | I2S_RCSR_STOPE_MASK (0x40000000U)
#define | I2S_RCSR_STOPE_SHIFT (30U)
#define | I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define | I2S_RCSR_RE_MASK (0x80000000U)
#define | I2S_RCSR_RE_SHIFT (31U)
#define | I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
RCR1 - SAI Receive Configuration 1 Register
#define | I2S_RCR1_RFW_MASK (0x1FU)
#define | I2S_RCR1_RFW_SHIFT (0U)
#define | I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
RCR2 - SAI Receive Configuration 2 Register
#define | I2S_RCR2_DIV_MASK (0xFFU)
#define | I2S_RCR2_DIV_SHIFT (0U)
#define | I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define | I2S_RCR2_BCD_MASK (0x1000000U)
#define | I2S_RCR2_BCD_SHIFT (24U)
#define | I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define | I2S_RCR2_BCP_MASK (0x2000000U)
#define | I2S_RCR2_BCP_SHIFT (25U)
#define | I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define | I2S_RCR2_MSEL_MASK (0xC000000U)
#define | I2S_RCR2_MSEL_SHIFT (26U)
#define | I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define | I2S_RCR2_BCI_MASK (0x10000000U)
#define | I2S_RCR2_BCI_SHIFT (28U)
#define | I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define | I2S_RCR2_BCS_MASK (0x20000000U)
#define | I2S_RCR2_BCS_SHIFT (29U)
#define | I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define | I2S_RCR2_SYNC_MASK (0xC0000000U)
#define | I2S_RCR2_SYNC_SHIFT (30U)
#define | I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
RCR3 - SAI Receive Configuration 3 Register
#define | I2S_RCR3_WDFL_MASK (0x1FU)
#define | I2S_RCR3_WDFL_SHIFT (0U)
#define | I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define | I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define | I2S_RCR3_RCE_SHIFT (16U)
#define | I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define | I2S_RCR3_CFR_MASK (0xF000000U)
#define | I2S_RCR3_CFR_SHIFT (24U)
#define | I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
RCR4 - SAI Receive Configuration 4 Register
#define | I2S_RCR4_FSD_MASK (0x1U)
#define | I2S_RCR4_FSD_SHIFT (0U)
#define | I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define | I2S_RCR4_FSP_MASK (0x2U)
#define | I2S_RCR4_FSP_SHIFT (1U)
#define | I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define | I2S_RCR4_ONDEM_MASK (0x4U)
#define | I2S_RCR4_ONDEM_SHIFT (2U)
#define | I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define | I2S_RCR4_FSE_MASK (0x8U)
#define | I2S_RCR4_FSE_SHIFT (3U)
#define | I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define | I2S_RCR4_MF_MASK (0x10U)
#define | I2S_RCR4_MF_SHIFT (4U)
#define | I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define | I2S_RCR4_SYWD_MASK (0x1F00U)
#define | I2S_RCR4_SYWD_SHIFT (8U)
#define | I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define | I2S_RCR4_FRSZ_MASK (0x1F0000U)
#define | I2S_RCR4_FRSZ_SHIFT (16U)
#define | I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define | I2S_RCR4_FPACK_MASK (0x3000000U)
#define | I2S_RCR4_FPACK_SHIFT (24U)
#define | I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define | I2S_RCR4_FCOMB_MASK (0xC000000U)
#define | I2S_RCR4_FCOMB_SHIFT (26U)
#define | I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define | I2S_RCR4_FCONT_MASK (0x10000000U)
#define | I2S_RCR4_FCONT_SHIFT (28U)
#define | I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
RCR5 - SAI Receive Configuration 5 Register
#define | I2S_RCR5_FBT_MASK (0x1F00U)
#define | I2S_RCR5_FBT_SHIFT (8U)
#define | I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define | I2S_RCR5_W0W_MASK (0x1F0000U)
#define | I2S_RCR5_W0W_SHIFT (16U)
#define | I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define | I2S_RCR5_WNW_MASK (0x1F000000U)
#define | I2S_RCR5_WNW_SHIFT (24U)
#define | I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
RDR - SAI Receive Data Register
#define | I2S_RDR_RDR_MASK (0xFFFFFFFFU)
#define | I2S_RDR_RDR_SHIFT (0U)
#define | I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
RFR - SAI Receive FIFO Register
#define | I2S_RFR_RFP_MASK (0x3FU)
#define | I2S_RFR_RFP_SHIFT (0U)
#define | I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define | I2S_RFR_RCP_MASK (0x8000U)
#define | I2S_RFR_RCP_SHIFT (15U)
#define | I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define | I2S_RFR_WFP_MASK (0x3F0000U)
#define | I2S_RFR_WFP_SHIFT (16U)
#define | I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
RMR - SAI Receive Mask Register
#define | I2S_RMR_RWM_MASK (0xFFFFFFFFU)
#define | I2S_RMR_RWM_SHIFT (0U)
#define | I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register
#define | IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
#define | IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
#define | IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
#define | IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
#define | IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
#define | IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register
#define | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
#define | IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
#define | IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)
#define | IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)
#define | IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)
#define | IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)
#define | IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)
#define | IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)
#define | IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)
#define | IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)
#define | IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)
#define | IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)
#define | IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)
#define | IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)
#define | IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)
#define | IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)
#define | IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register
#define | IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
#define | IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
#define | IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
SW_MUX_CTL_PAD_1 - SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register
#define | IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK (0x7U)
#define | IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT (0U)
#define | IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK)
#define | IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK (0x10U)
#define | IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT (4U)
#define | IOMUXC_SW_MUX_CTL_PAD_1_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK)
SW_PAD_CTL_PAD_1 - SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register
#define | IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK (0x1U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT (0U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK (0x38U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT (3U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK (0xC0U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT (6U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK (0x800U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT (11U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK (0x1000U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT (12U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK (0x2000U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT (13U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK (0xC000U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT (14U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK)
#define | IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK (0x10000U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT (16U)
#define | IOMUXC_SW_PAD_CTL_PAD_1_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK)
SELECT_INPUT_1 - ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register..CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register
#define | IOMUXC_SELECT_INPUT_1_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
#define | IOMUXC_SELECT_INPUT_1_DAISY_SHIFT (0U)
#define | IOMUXC_SELECT_INPUT_1_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_1_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_1_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
GPR1 - GPR1 General Purpose Register
#define | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
#define | IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
#define | IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
#define | IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
#define | IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)
#define | IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)
#define | IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
#define | IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U)
#define | IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U)
#define | IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK)
#define | IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)
#define | IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)
#define | IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
#define | IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)
#define | IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)
#define | IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U)
#define | IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U)
#define | IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
#define | IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
#define | IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
#define | IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
#define | IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
#define | IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
#define | IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)
#define | IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)
#define | IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
#define | IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
#define | IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
GPR2 - GPR2 General Purpose Register
#define | IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK (0x1U)
#define | IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT (0U)
#define | IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK (0x2U)
#define | IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT (1U)
#define | IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK (0x4U)
#define | IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT (2U)
#define | IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK (0x8U)
#define | IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT (3U)
#define | IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK (0x10U)
#define | IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT (4U)
#define | IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK)
#define | IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK (0x20U)
#define | IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT (5U)
#define | IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK)
#define | IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK (0x40U)
#define | IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT (6U)
#define | IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK)
#define | IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
#define | IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
#define | IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
#define | IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U)
#define | IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U)
#define | IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK)
#define | IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
#define | IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
#define | IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
#define | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
#define | IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
#define | IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
#define | IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
#define | IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
#define | IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
#define | IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
#define | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
#define | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
#define | IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
#define | IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
#define | IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
#define | IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
#define | IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
#define | IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
#define | IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
#define | IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
GPR3 - GPR3 General Purpose Register
#define | IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)
#define | IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)
#define | IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
#define | IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
#define | IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
#define | IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
#define | IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK (0xF00U)
#define | IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT (8U)
#define | IOMUXC_GPR_GPR3_OCRAM2_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK (0x8000U)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT (15U)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK)
#define | IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)
#define | IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)
#define | IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
#define | IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK (0xF000000U)
#define | IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT (24U)
#define | IOMUXC_GPR_GPR3_OCRAM2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT (31U)
#define | IOMUXC_GPR_GPR3_AXBS_L_HALTED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
#define | IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
#define | IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
#define | IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
GPR4 - GPR4 General Purpose Register
#define | IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
#define | IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
#define | IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x100U)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (8U)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
#define | IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
#define | IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK (0x4000U)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT (14U)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK (0x8000U)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT (15U)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
#define | IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
#define | IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
#define | IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
#define | IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
#define | IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
#define | IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
#define | IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
#define | IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
#define | IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (24U)
#define | IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
#define | IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
#define | IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
#define | IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
#define | IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)
#define | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT (30U)
#define | IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT (31U)
#define | IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK)
GPR5 - GPR5 General Purpose Register
#define | IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
#define | IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
#define | IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
#define | IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
#define | IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
#define | IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U)
#define | IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK)
#define | IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
#define | IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
#define | IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U)
#define | IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
#define | IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
GPR6 - GPR6 General Purpose Register
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
#define | IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
#define | IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
#define | IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
#define | IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
#define | IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
GPR7 - GPR7 General Purpose Register
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
#define | IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
#define | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
#define | IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
#define | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
#define | IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
#define | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
#define | IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
#define | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
#define | IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
#define | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
#define | IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
#define | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
#define | IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
#define | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
#define | IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
#define | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
GPR8 - GPR8 General Purpose Register
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
#define | IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
#define | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
#define | IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
#define | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
#define | IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
#define | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
#define | IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
#define | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
#define | IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
#define | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
#define | IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
#define | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
#define | IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
#define | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
#define | IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
#define | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
GPR10 - GPR10 General Purpose Register
#define | IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
#define | IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
#define | IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
#define | IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
#define | IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
#define | IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
#define | IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
#define | IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
#define | IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
#define | IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
#define | IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
#define | IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
#define | IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
#define | IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
#define | IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
#define | IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
#define | IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
#define | IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
#define | IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
#define | IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
#define | IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
#define | IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
GPR11 - GPR11 General Purpose Register
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
#define | IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
#define | IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
#define | IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
#define | IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
GPR12 - GPR12 General Purpose Register
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
#define | IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)
#define | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
#define | IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
#define | IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
#define | IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK (0x20U)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT (5U)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK (0x40U)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT (6U)
#define | IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK)
GPR13 - GPR13 General Purpose Register
#define | IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
#define | IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
#define | IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
#define | IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
#define | IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
#define | IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK (0x10U)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT (4U)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK)
#define | IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
#define | IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
#define | IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
#define | IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
#define | IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
#define | IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK (0x100000U)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT (20U)
#define | IOMUXC_GPR_GPR13_CANFD_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK)
GPR14 - GPR14 General Purpose Register
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
#define | IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
#define | IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
#define | IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
#define | IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
#define | IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
#define | IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
#define | IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
#define | IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
#define | IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
#define | IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
#define | IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
#define | IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
#define | IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
#define | IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
#define | IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)
#define | IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)
#define | IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
#define | IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)
#define | IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)
#define | IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
GPR16 - GPR16 General Purpose Register
#define | IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)
#define | IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)
#define | IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
#define | IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)
#define | IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)
#define | IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
GPR17 - GPR17 General Purpose Register
#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
GPR18 - GPR18 General Purpose Register
#define | IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
#define | IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
#define | IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
#define | IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
#define | IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
GPR19 - GPR19 General Purpose Register
#define | IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
#define | IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
#define | IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
#define | IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
#define | IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
GPR20 - GPR20 General Purpose Register
#define | IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
#define | IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
#define | IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
#define | IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
#define | IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
GPR21 - GPR21 General Purpose Register
#define | IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
#define | IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
#define | IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
#define | IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
#define | IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
GPR22 - GPR22 General Purpose Register
#define | IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
#define | IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
#define | IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
#define | IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
#define | IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
GPR23 - GPR23 General Purpose Register
#define | IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
#define | IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
#define | IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
#define | IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
#define | IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
GPR24 - GPR24 General Purpose Register
#define | IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
#define | IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
#define | IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
#define | IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)
#define | IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
GPR25 - GPR25 General Purpose Register
#define | IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
#define | IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
#define | IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
#define | IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
#define | IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
#define | IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
GPR26 - GPR26 General Purpose Register
#define | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)
GPR27 - GPR27 General Purpose Register
#define | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)
GPR28 - GPR28 General Purpose Register
#define | IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK)
GPR29 - GPR29 General Purpose Register
#define | IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK (0xFFFFFFFFU)
#define | IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK)
GPR30 - GPR30 General Purpose Register
#define | IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK (0xFFFFF000U)
#define | IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT (12U)
#define | IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT)) & IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK)
GPR31 - GPR31 General Purpose Register
#define | IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK (0xFFFFF000U)
#define | IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT (12U)
#define | IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT)) & IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK)
GPR32 - GPR32 General Purpose Register
#define | IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK (0xFFFFF000U)
#define | IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT (12U)
#define | IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT)) & IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK)
GPR33 - GPR33 General Purpose Register
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK (0x1U)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT (0U)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK (0xFEU)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT (1U)
#define | IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK (0x10000U)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT (16U)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK (0xFE0000U)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT (17U)
#define | IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK)
GPR34 - GPR34 General Purpose Register
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK (0xFFU)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT (0U)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK (0x100U)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT (8U)
#define | IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK)
SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)
KPCR - Keypad Control Register
#define | KPP_KPCR_KRE_MASK (0xFFU)
#define | KPP_KPCR_KRE_SHIFT (0U)
#define | KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
#define | KPP_KPCR_KCO_MASK (0xFF00U)
#define | KPP_KPCR_KCO_SHIFT (8U)
#define | KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
KPSR - Keypad Status Register
#define | KPP_KPSR_KPKD_MASK (0x1U)
#define | KPP_KPSR_KPKD_SHIFT (0U)
#define | KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
#define | KPP_KPSR_KPKR_MASK (0x2U)
#define | KPP_KPSR_KPKR_SHIFT (1U)
#define | KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
#define | KPP_KPSR_KDSC_MASK (0x4U)
#define | KPP_KPSR_KDSC_SHIFT (2U)
#define | KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
#define | KPP_KPSR_KRSS_MASK (0x8U)
#define | KPP_KPSR_KRSS_SHIFT (3U)
#define | KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
#define | KPP_KPSR_KDIE_MASK (0x100U)
#define | KPP_KPSR_KDIE_SHIFT (8U)
#define | KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
#define | KPP_KPSR_KRIE_MASK (0x200U)
#define | KPP_KPSR_KRIE_SHIFT (9U)
#define | KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
KDDR - Keypad Data Direction Register
#define | KPP_KDDR_KRDD_MASK (0xFFU)
#define | KPP_KDDR_KRDD_SHIFT (0U)
#define | KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
#define | KPP_KDDR_KCDD_MASK (0xFF00U)
#define | KPP_KDDR_KCDD_SHIFT (8U)
#define | KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
KPDR - Keypad Data Register
#define | KPP_KPDR_KRD_MASK (0xFFU)
#define | KPP_KPDR_KRD_SHIFT (0U)
#define | KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
#define | KPP_KPDR_KCD_MASK (0xFF00U)
#define | KPP_KPDR_KCD_SHIFT (8U)
#define | KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
CTRL - LCDIF General Control Register
#define | LCDIF_CTRL_RUN_MASK (0x1U)
#define | LCDIF_CTRL_RUN_SHIFT (0U)
#define | LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
#define | LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
#define | LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
#define | LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
#define | LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
#define | LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
#define | LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
#define | LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
#define | LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
#define | LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
#define | LCDIF_CTRL_RSRVD0_MASK (0x10U)
#define | LCDIF_CTRL_RSRVD0_SHIFT (4U)
#define | LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
#define | LCDIF_CTRL_MASTER_MASK (0x20U)
#define | LCDIF_CTRL_MASTER_SHIFT (5U)
#define | LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
#define | LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define | LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define | LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
#define | LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
#define | LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
#define | LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
#define | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define | LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
#define | LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
#define | LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define | LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
#define | LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
#define | LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define | LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
#define | LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
#define | LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
#define | LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
#define | LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
#define | LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
#define | LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
#define | LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
#define | LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define | LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
#define | LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
#define | LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
#define | LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
#define | LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
#define | LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
#define | LCDIF_CTRL_CLKGATE_SHIFT (30U)
#define | LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
#define | LCDIF_CTRL_SFTRST_MASK (0x80000000U)
#define | LCDIF_CTRL_SFTRST_SHIFT (31U)
#define | LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
CTRL_SET - LCDIF General Control Register
#define | LCDIF_CTRL_SET_RUN_MASK (0x1U)
#define | LCDIF_CTRL_SET_RUN_SHIFT (0U)
#define | LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
#define | LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
#define | LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
#define | LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
#define | LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
#define | LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
#define | LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
#define | LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
#define | LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
#define | LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
#define | LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
#define | LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
#define | LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
#define | LCDIF_CTRL_SET_MASTER_MASK (0x20U)
#define | LCDIF_CTRL_SET_MASTER_SHIFT (5U)
#define | LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
#define | LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define | LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define | LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
#define | LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
#define | LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
#define | LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
#define | LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define | LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
#define | LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
#define | LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define | LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
#define | LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
#define | LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define | LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
#define | LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
#define | LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
#define | LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
#define | LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
#define | LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
#define | LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
#define | LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
#define | LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define | LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
#define | LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
#define | LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
#define | LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
#define | LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
#define | LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define | LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
#define | LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
#define | LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
#define | LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
#define | LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
CTRL_CLR - LCDIF General Control Register
#define | LCDIF_CTRL_CLR_RUN_MASK (0x1U)
#define | LCDIF_CTRL_CLR_RUN_SHIFT (0U)
#define | LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
#define | LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
#define | LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
#define | LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
#define | LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
#define | LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
#define | LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
#define | LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
#define | LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define | LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define | LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
#define | LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
#define | LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
#define | LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
#define | LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define | LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
#define | LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
#define | LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define | LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
#define | LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
#define | LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define | LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
#define | LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
#define | LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
#define | LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
#define | LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
#define | LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
#define | LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
#define | LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
#define | LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define | LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
#define | LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
#define | LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
#define | LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
#define | LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
#define | LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define | LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
#define | LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
#define | LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define | LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
#define | LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
CTRL_TOG - LCDIF General Control Register
#define | LCDIF_CTRL_TOG_RUN_MASK (0x1U)
#define | LCDIF_CTRL_TOG_RUN_SHIFT (0U)
#define | LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
#define | LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
#define | LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
#define | LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
#define | LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
#define | LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
#define | LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
#define | LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
#define | LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define | LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define | LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
#define | LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
#define | LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
#define | LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
#define | LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define | LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
#define | LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
#define | LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define | LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
#define | LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
#define | LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define | LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
#define | LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
#define | LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
#define | LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
#define | LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
#define | LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
#define | LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
#define | LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
#define | LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define | LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
#define | LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
#define | LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
#define | LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
#define | LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
#define | LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define | LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
#define | LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
#define | LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define | LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
#define | LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
CTRL1 - LCDIF General Control1 Register
#define | LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
#define | LCDIF_CTRL1_RSRVD0_SHIFT (3U)
#define | LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
#define | LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
#define | LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
#define | LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
#define | LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
#define | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define | LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
#define | LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
#define | LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define | LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
#define | LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
#define | LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define | LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define | LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define | LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
#define | LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
#define | LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
#define | LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define | LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define | LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define | LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
#define | LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
#define | LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
#define | LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define | LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define | LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
#define | LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
#define | LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
#define | LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
#define | LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define | LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
#define | LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
#define | LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)
#define | LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)
#define | LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
#define | LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define | LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)
#define | LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
CTRL1_SET - LCDIF General Control1 Register
#define | LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
#define | LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
#define | LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
#define | LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define | LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
#define | LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
#define | LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define | LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define | LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define | LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
#define | LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
#define | LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
#define | LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define | LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define | LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define | LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
#define | LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
#define | LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
#define | LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define | LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define | LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
#define | LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)
#define | LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)
#define | LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
#define | LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define | LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)
#define | LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
CTRL1_CLR - LCDIF General Control1 Register
#define | LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
#define | LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
#define | LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
#define | LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define | LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
#define | LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
#define | LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define | LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define | LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define | LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
#define | LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
#define | LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
#define | LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define | LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define | LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define | LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
#define | LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
#define | LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
#define | LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define | LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define | LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
#define | LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)
#define | LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)
#define | LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
#define | LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define | LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)
#define | LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
CTRL1_TOG - LCDIF General Control1 Register
#define | LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
#define | LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
#define | LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
#define | LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define | LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
#define | LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
#define | LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define | LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define | LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define | LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
#define | LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
#define | LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
#define | LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define | LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define | LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define | LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
#define | LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
#define | LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
#define | LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define | LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define | LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
#define | LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)
#define | LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)
#define | LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
#define | LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define | LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)
#define | LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
CTRL2 - LCDIF General Control2 Register
#define | LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)
#define | LCDIF_CTRL2_RSRVD0_SHIFT (0U)
#define | LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
#define | LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
#define | LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
#define | LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
#define | LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
#define | LCDIF_CTRL2_RSRVD3_SHIFT (15U)
#define | LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
#define | LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
#define | LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
#define | LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
#define | LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
#define | LCDIF_CTRL2_RSRVD4_SHIFT (19U)
#define | LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
#define | LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
#define | LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
#define | LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
#define | LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
#define | LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
#define | LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
#define | LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
#define | LCDIF_CTRL2_RSRVD5_SHIFT (24U)
#define | LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
CTRL2_SET - LCDIF General Control2 Register
#define | LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)
#define | LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
#define | LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
#define | LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
#define | LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
#define | LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
#define | LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
#define | LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
#define | LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
#define | LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
#define | LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
#define | LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
#define | LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
#define | LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
#define | LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
#define | LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
#define | LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
#define | LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
#define | LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
#define | LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
#define | LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
#define | LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
#define | LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
#define | LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
CTRL2_CLR - LCDIF General Control2 Register
#define | LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)
#define | LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
#define | LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
#define | LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
#define | LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
#define | LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
#define | LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
#define | LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
#define | LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
#define | LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
#define | LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
#define | LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
#define | LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
#define | LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
#define | LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
#define | LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
#define | LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
#define | LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
#define | LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
#define | LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
#define | LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
#define | LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
#define | LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
#define | LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
CTRL2_TOG - LCDIF General Control2 Register
#define | LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)
#define | LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
#define | LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
#define | LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
#define | LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
#define | LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
#define | LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
#define | LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
#define | LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
#define | LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
#define | LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
#define | LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
#define | LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
#define | LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
#define | LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
#define | LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
#define | LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
#define | LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
#define | LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
#define | LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
#define | LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
#define | LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
#define | LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
#define | LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register
#define | LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
#define | LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
#define | LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
#define | LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
#define | LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
#define | LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
CUR_BUF - LCD Interface Current Buffer Address Register
#define | LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
#define | LCDIF_CUR_BUF_ADDR_SHIFT (0U)
#define | LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
NEXT_BUF - LCD Interface Next Buffer Address Register
#define | LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
#define | LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
#define | LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
#define | LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
#define | LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
#define | LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
#define | LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
#define | LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
#define | LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
#define | LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
#define | LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
#define | LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
#define | LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
#define | LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
#define | LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
#define | LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
#define | LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
#define | LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
#define | LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
#define | LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
#define | LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
#define | LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
#define | LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
#define | LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
#define | LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
#define | LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
#define | LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
#define | LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)
#define | LCDIF_VDCTRL0_RSRVD2_SHIFT (29U)
#define | LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
#define | LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
#define | LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
#define | LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
#define | LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
#define | LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
#define | LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define | LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define | LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define | LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
#define | LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
#define | LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
#define | LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
#define | LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
#define | LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
#define | LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
#define | LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
#define | LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
#define | LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
#define | LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
#define | LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
#define | LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
#define | LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
#define | LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
#define | LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
#define | LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
#define | LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
#define | LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
#define | LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)
#define | LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)
#define | LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
#define | LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define | LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define | LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define | LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
#define | LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
#define | LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
#define | LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
#define | LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
#define | LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
#define | LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
#define | LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
#define | LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
#define | LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
#define | LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
#define | LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
#define | LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
#define | LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
#define | LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
#define | LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
#define | LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
#define | LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
#define | LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
#define | LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)
#define | LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)
#define | LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
#define | LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define | LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define | LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define | LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
#define | LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
#define | LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
#define | LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
#define | LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
#define | LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
#define | LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
#define | LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
#define | LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
#define | LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
#define | LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
#define | LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
#define | LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
#define | LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
#define | LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
#define | LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
#define | LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
#define | LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
#define | LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
#define | LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)
#define | LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)
#define | LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1
#define | LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
#define | LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
#define | LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2
#define | LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
#define | LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
#define | LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
#define | LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
#define | LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
#define | LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3
#define | LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
#define | LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
#define | LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
#define | LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
#define | LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
#define | LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
#define | LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
#define | LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
#define | LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
#define | LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
#define | LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
#define | LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
#define | LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
#define | LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
#define | LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4
#define | LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
#define | LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
#define | LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
#define | LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
#define | LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
#define | LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
#define | LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
#define | LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
#define | LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
#define | LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
#define | LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
#define | LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
BM_ERROR_STAT - Bus Master Error Status Register
#define | LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
#define | LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
#define | LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
CRC_STAT - CRC Status Register
#define | LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
#define | LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
#define | LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
STAT - LCD Interface Status Register
#define | LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
#define | LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
#define | LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
#define | LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)
#define | LCDIF_STAT_RSRVD0_SHIFT (9U)
#define | LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
#define | LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
#define | LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
#define | LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
#define | LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
#define | LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
#define | LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
#define | LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
#define | LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
#define | LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
#define | LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
#define | LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
#define | LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
#define | LCDIF_STAT_DMA_REQ_MASK (0x40000000U)
#define | LCDIF_STAT_DMA_REQ_SHIFT (30U)
#define | LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
#define | LCDIF_STAT_PRESENT_MASK (0x80000000U)
#define | LCDIF_STAT_PRESENT_SHIFT (31U)
#define | LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register
#define | LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
#define | LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
#define | LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
#define | LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
#define | LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
#define | LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register
#define | LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
#define | LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
#define | LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
#define | LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
#define | LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
#define | LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register
#define | LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
#define | LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
#define | LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
#define | LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
#define | LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
#define | LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register
#define | LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
#define | LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
#define | LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
#define | LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
#define | LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
#define | LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register
#define | LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
#define | LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
#define | LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
#define | LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
#define | LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
#define | LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
PIGEON_0 - Panel Interface Signal Generator Register
#define | LCDIF_PIGEON_0_EN_MASK (0x1U)
#define | LCDIF_PIGEON_0_EN_SHIFT (0U)
#define | LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
#define | LCDIF_PIGEON_0_POL_MASK (0x2U)
#define | LCDIF_PIGEON_0_POL_SHIFT (1U)
#define | LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
#define | LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)
#define | LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)
#define | LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
#define | LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)
#define | LCDIF_PIGEON_0_OFFSET_SHIFT (4U)
#define | LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
#define | LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
#define | LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
#define | LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
#define | LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)
#define | LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)
#define | LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
#define | LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)
#define | LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)
#define | LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
PIGEON_1 - Panel Interface Signal Generator Register
#define | LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)
#define | LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)
#define | LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
#define | LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)
#define | LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)
#define | LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
PIGEON_2 - Panel Interface Signal Generator Register
#define | LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)
#define | LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)
#define | LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
#define | LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)
#define | LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
#define | LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
#define | LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)
#define | LCDIF_PIGEON_2_RSVD_SHIFT (9U)
#define | LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
LUT_CTRL - Lookup Table Data Register.
#define | LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)
#define | LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)
#define | LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
LUT0_ADDR - Lookup Table Control Register.
#define | LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)
#define | LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)
#define | LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
LUT0_DATA - Lookup Table Data Register.
#define | LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)
#define | LCDIF_LUT0_DATA_DATA_SHIFT (0U)
#define | LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
LUT1_ADDR - Lookup Table Control Register.
#define | LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)
#define | LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)
#define | LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
LUT1_DATA - Lookup Table Data Register.
#define | LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)
#define | LCDIF_LUT1_DATA_DATA_SHIFT (0U)
#define | LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
MCR - Master Control Register
#define | LPI2C_MCR_MEN_MASK (0x1U)
#define | LPI2C_MCR_MEN_SHIFT (0U)
#define | LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
#define | LPI2C_MCR_RST_MASK (0x2U)
#define | LPI2C_MCR_RST_SHIFT (1U)
#define | LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
#define | LPI2C_MCR_DOZEN_MASK (0x4U)
#define | LPI2C_MCR_DOZEN_SHIFT (2U)
#define | LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
#define | LPI2C_MCR_DBGEN_MASK (0x8U)
#define | LPI2C_MCR_DBGEN_SHIFT (3U)
#define | LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
#define | LPI2C_MCR_RTF_MASK (0x100U)
#define | LPI2C_MCR_RTF_SHIFT (8U)
#define | LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
#define | LPI2C_MCR_RRF_MASK (0x200U)
#define | LPI2C_MCR_RRF_SHIFT (9U)
#define | LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
MSR - Master Status Register
#define | LPI2C_MSR_TDF_MASK (0x1U)
#define | LPI2C_MSR_TDF_SHIFT (0U)
#define | LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
#define | LPI2C_MSR_RDF_MASK (0x2U)
#define | LPI2C_MSR_RDF_SHIFT (1U)
#define | LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
#define | LPI2C_MSR_EPF_MASK (0x100U)
#define | LPI2C_MSR_EPF_SHIFT (8U)
#define | LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
#define | LPI2C_MSR_SDF_MASK (0x200U)
#define | LPI2C_MSR_SDF_SHIFT (9U)
#define | LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
#define | LPI2C_MSR_NDF_MASK (0x400U)
#define | LPI2C_MSR_NDF_SHIFT (10U)
#define | LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
#define | LPI2C_MSR_ALF_MASK (0x800U)
#define | LPI2C_MSR_ALF_SHIFT (11U)
#define | LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
#define | LPI2C_MSR_FEF_MASK (0x1000U)
#define | LPI2C_MSR_FEF_SHIFT (12U)
#define | LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
#define | LPI2C_MSR_PLTF_MASK (0x2000U)
#define | LPI2C_MSR_PLTF_SHIFT (13U)
#define | LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
#define | LPI2C_MSR_DMF_MASK (0x4000U)
#define | LPI2C_MSR_DMF_SHIFT (14U)
#define | LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
#define | LPI2C_MSR_MBF_MASK (0x1000000U)
#define | LPI2C_MSR_MBF_SHIFT (24U)
#define | LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
#define | LPI2C_MSR_BBF_MASK (0x2000000U)
#define | LPI2C_MSR_BBF_SHIFT (25U)
#define | LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
MIER - Master Interrupt Enable Register
#define | LPI2C_MIER_TDIE_MASK (0x1U)
#define | LPI2C_MIER_TDIE_SHIFT (0U)
#define | LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
#define | LPI2C_MIER_RDIE_MASK (0x2U)
#define | LPI2C_MIER_RDIE_SHIFT (1U)
#define | LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
#define | LPI2C_MIER_EPIE_MASK (0x100U)
#define | LPI2C_MIER_EPIE_SHIFT (8U)
#define | LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
#define | LPI2C_MIER_SDIE_MASK (0x200U)
#define | LPI2C_MIER_SDIE_SHIFT (9U)
#define | LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
#define | LPI2C_MIER_NDIE_MASK (0x400U)
#define | LPI2C_MIER_NDIE_SHIFT (10U)
#define | LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
#define | LPI2C_MIER_ALIE_MASK (0x800U)
#define | LPI2C_MIER_ALIE_SHIFT (11U)
#define | LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
#define | LPI2C_MIER_FEIE_MASK (0x1000U)
#define | LPI2C_MIER_FEIE_SHIFT (12U)
#define | LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
#define | LPI2C_MIER_PLTIE_MASK (0x2000U)
#define | LPI2C_MIER_PLTIE_SHIFT (13U)
#define | LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
#define | LPI2C_MIER_DMIE_MASK (0x4000U)
#define | LPI2C_MIER_DMIE_SHIFT (14U)
#define | LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
MDER - Master DMA Enable Register
#define | LPI2C_MDER_TDDE_MASK (0x1U)
#define | LPI2C_MDER_TDDE_SHIFT (0U)
#define | LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
#define | LPI2C_MDER_RDDE_MASK (0x2U)
#define | LPI2C_MDER_RDDE_SHIFT (1U)
#define | LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
MCFGR0 - Master Configuration Register 0
#define | LPI2C_MCFGR0_HREN_MASK (0x1U)
#define | LPI2C_MCFGR0_HREN_SHIFT (0U)
#define | LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
#define | LPI2C_MCFGR0_HRPOL_MASK (0x2U)
#define | LPI2C_MCFGR0_HRPOL_SHIFT (1U)
#define | LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
#define | LPI2C_MCFGR0_HRSEL_MASK (0x4U)
#define | LPI2C_MCFGR0_HRSEL_SHIFT (2U)
#define | LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
#define | LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
#define | LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
#define | LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
#define | LPI2C_MCFGR0_RDMO_MASK (0x200U)
#define | LPI2C_MCFGR0_RDMO_SHIFT (9U)
#define | LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
MCFGR1 - Master Configuration Register 1
#define | LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
#define | LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
#define | LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
#define | LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
#define | LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
#define | LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
#define | LPI2C_MCFGR1_IGNACK_MASK (0x200U)
#define | LPI2C_MCFGR1_IGNACK_SHIFT (9U)
#define | LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
#define | LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
#define | LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
#define | LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
#define | LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
#define | LPI2C_MCFGR1_MATCFG_SHIFT (16U)
#define | LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
#define | LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
#define | LPI2C_MCFGR1_PINCFG_SHIFT (24U)
#define | LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
MCFGR2 - Master Configuration Register 2
#define | LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
#define | LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
#define | LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
#define | LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
#define | LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
#define | LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
#define | LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
#define | LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
#define | LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
MCFGR3 - Master Configuration Register 3
#define | LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
#define | LPI2C_MCFGR3_PINLOW_SHIFT (8U)
#define | LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
MDMR - Master Data Match Register
#define | LPI2C_MDMR_MATCH0_MASK (0xFFU)
#define | LPI2C_MDMR_MATCH0_SHIFT (0U)
#define | LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
#define | LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
#define | LPI2C_MDMR_MATCH1_SHIFT (16U)
#define | LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
MCCR0 - Master Clock Configuration Register 0
#define | LPI2C_MCCR0_CLKLO_MASK (0x3FU)
#define | LPI2C_MCCR0_CLKLO_SHIFT (0U)
#define | LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
#define | LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
#define | LPI2C_MCCR0_CLKHI_SHIFT (8U)
#define | LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
#define | LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
#define | LPI2C_MCCR0_SETHOLD_SHIFT (16U)
#define | LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
#define | LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
#define | LPI2C_MCCR0_DATAVD_SHIFT (24U)
#define | LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
MCCR1 - Master Clock Configuration Register 1
#define | LPI2C_MCCR1_CLKLO_MASK (0x3FU)
#define | LPI2C_MCCR1_CLKLO_SHIFT (0U)
#define | LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
#define | LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
#define | LPI2C_MCCR1_CLKHI_SHIFT (8U)
#define | LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
#define | LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
#define | LPI2C_MCCR1_SETHOLD_SHIFT (16U)
#define | LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
#define | LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
#define | LPI2C_MCCR1_DATAVD_SHIFT (24U)
#define | LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
MFCR - Master FIFO Control Register
#define | LPI2C_MFCR_TXWATER_MASK (0x3U)
#define | LPI2C_MFCR_TXWATER_SHIFT (0U)
#define | LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
#define | LPI2C_MFCR_RXWATER_MASK (0x30000U)
#define | LPI2C_MFCR_RXWATER_SHIFT (16U)
#define | LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
MFSR - Master FIFO Status Register
#define | LPI2C_MFSR_TXCOUNT_MASK (0x7U)
#define | LPI2C_MFSR_TXCOUNT_SHIFT (0U)
#define | LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
#define | LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
#define | LPI2C_MFSR_RXCOUNT_SHIFT (16U)
#define | LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
MTDR - Master Transmit Data Register
#define | LPI2C_MTDR_DATA_MASK (0xFFU)
#define | LPI2C_MTDR_DATA_SHIFT (0U)
#define | LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
#define | LPI2C_MTDR_CMD_MASK (0x700U)
#define | LPI2C_MTDR_CMD_SHIFT (8U)
#define | LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
MRDR - Master Receive Data Register
#define | LPI2C_MRDR_DATA_MASK (0xFFU)
#define | LPI2C_MRDR_DATA_SHIFT (0U)
#define | LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
#define | LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
#define | LPI2C_MRDR_RXEMPTY_SHIFT (14U)
#define | LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
SCR - Slave Control Register
#define | LPI2C_SCR_SEN_MASK (0x1U)
#define | LPI2C_SCR_SEN_SHIFT (0U)
#define | LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
#define | LPI2C_SCR_RST_MASK (0x2U)
#define | LPI2C_SCR_RST_SHIFT (1U)
#define | LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
#define | LPI2C_SCR_FILTEN_MASK (0x10U)
#define | LPI2C_SCR_FILTEN_SHIFT (4U)
#define | LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
#define | LPI2C_SCR_FILTDZ_MASK (0x20U)
#define | LPI2C_SCR_FILTDZ_SHIFT (5U)
#define | LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
#define | LPI2C_SCR_RTF_MASK (0x100U)
#define | LPI2C_SCR_RTF_SHIFT (8U)
#define | LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
#define | LPI2C_SCR_RRF_MASK (0x200U)
#define | LPI2C_SCR_RRF_SHIFT (9U)
#define | LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
SSR - Slave Status Register
#define | LPI2C_SSR_TDF_MASK (0x1U)
#define | LPI2C_SSR_TDF_SHIFT (0U)
#define | LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
#define | LPI2C_SSR_RDF_MASK (0x2U)
#define | LPI2C_SSR_RDF_SHIFT (1U)
#define | LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
#define | LPI2C_SSR_AVF_MASK (0x4U)
#define | LPI2C_SSR_AVF_SHIFT (2U)
#define | LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
#define | LPI2C_SSR_TAF_MASK (0x8U)
#define | LPI2C_SSR_TAF_SHIFT (3U)
#define | LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
#define | LPI2C_SSR_RSF_MASK (0x100U)
#define | LPI2C_SSR_RSF_SHIFT (8U)
#define | LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
#define | LPI2C_SSR_SDF_MASK (0x200U)
#define | LPI2C_SSR_SDF_SHIFT (9U)
#define | LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
#define | LPI2C_SSR_BEF_MASK (0x400U)
#define | LPI2C_SSR_BEF_SHIFT (10U)
#define | LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
#define | LPI2C_SSR_FEF_MASK (0x800U)
#define | LPI2C_SSR_FEF_SHIFT (11U)
#define | LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
#define | LPI2C_SSR_AM0F_MASK (0x1000U)
#define | LPI2C_SSR_AM0F_SHIFT (12U)
#define | LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
#define | LPI2C_SSR_AM1F_MASK (0x2000U)
#define | LPI2C_SSR_AM1F_SHIFT (13U)
#define | LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
#define | LPI2C_SSR_GCF_MASK (0x4000U)
#define | LPI2C_SSR_GCF_SHIFT (14U)
#define | LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
#define | LPI2C_SSR_SARF_MASK (0x8000U)
#define | LPI2C_SSR_SARF_SHIFT (15U)
#define | LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
#define | LPI2C_SSR_SBF_MASK (0x1000000U)
#define | LPI2C_SSR_SBF_SHIFT (24U)
#define | LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
#define | LPI2C_SSR_BBF_MASK (0x2000000U)
#define | LPI2C_SSR_BBF_SHIFT (25U)
#define | LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
SIER - Slave Interrupt Enable Register
#define | LPI2C_SIER_TDIE_MASK (0x1U)
#define | LPI2C_SIER_TDIE_SHIFT (0U)
#define | LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
#define | LPI2C_SIER_RDIE_MASK (0x2U)
#define | LPI2C_SIER_RDIE_SHIFT (1U)
#define | LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
#define | LPI2C_SIER_AVIE_MASK (0x4U)
#define | LPI2C_SIER_AVIE_SHIFT (2U)
#define | LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
#define | LPI2C_SIER_TAIE_MASK (0x8U)
#define | LPI2C_SIER_TAIE_SHIFT (3U)
#define | LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
#define | LPI2C_SIER_RSIE_MASK (0x100U)
#define | LPI2C_SIER_RSIE_SHIFT (8U)
#define | LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
#define | LPI2C_SIER_SDIE_MASK (0x200U)
#define | LPI2C_SIER_SDIE_SHIFT (9U)
#define | LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
#define | LPI2C_SIER_BEIE_MASK (0x400U)
#define | LPI2C_SIER_BEIE_SHIFT (10U)
#define | LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
#define | LPI2C_SIER_FEIE_MASK (0x800U)
#define | LPI2C_SIER_FEIE_SHIFT (11U)
#define | LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
#define | LPI2C_SIER_AM0IE_MASK (0x1000U)
#define | LPI2C_SIER_AM0IE_SHIFT (12U)
#define | LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
#define | LPI2C_SIER_AM1F_MASK (0x2000U)
#define | LPI2C_SIER_AM1F_SHIFT (13U)
#define | LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
#define | LPI2C_SIER_GCIE_MASK (0x4000U)
#define | LPI2C_SIER_GCIE_SHIFT (14U)
#define | LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
#define | LPI2C_SIER_SARIE_MASK (0x8000U)
#define | LPI2C_SIER_SARIE_SHIFT (15U)
#define | LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
SDER - Slave DMA Enable Register
#define | LPI2C_SDER_TDDE_MASK (0x1U)
#define | LPI2C_SDER_TDDE_SHIFT (0U)
#define | LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
#define | LPI2C_SDER_RDDE_MASK (0x2U)
#define | LPI2C_SDER_RDDE_SHIFT (1U)
#define | LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
#define | LPI2C_SDER_AVDE_MASK (0x4U)
#define | LPI2C_SDER_AVDE_SHIFT (2U)
#define | LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
SCFGR1 - Slave Configuration Register 1
#define | LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
#define | LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
#define | LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
#define | LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
#define | LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
#define | LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
#define | LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
#define | LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
#define | LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
#define | LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
#define | LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
#define | LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
#define | LPI2C_SCFGR1_GCEN_MASK (0x100U)
#define | LPI2C_SCFGR1_GCEN_SHIFT (8U)
#define | LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
#define | LPI2C_SCFGR1_SAEN_MASK (0x200U)
#define | LPI2C_SCFGR1_SAEN_SHIFT (9U)
#define | LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
#define | LPI2C_SCFGR1_TXCFG_MASK (0x400U)
#define | LPI2C_SCFGR1_TXCFG_SHIFT (10U)
#define | LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
#define | LPI2C_SCFGR1_RXCFG_MASK (0x800U)
#define | LPI2C_SCFGR1_RXCFG_SHIFT (11U)
#define | LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
#define | LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
#define | LPI2C_SCFGR1_IGNACK_SHIFT (12U)
#define | LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
#define | LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
#define | LPI2C_SCFGR1_HSMEN_SHIFT (13U)
#define | LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
#define | LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
#define | LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
#define | LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
SCFGR2 - Slave Configuration Register 2
#define | LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
#define | LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
#define | LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
#define | LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
#define | LPI2C_SCFGR2_DATAVD_SHIFT (8U)
#define | LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
#define | LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
#define | LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
#define | LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
#define | LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
#define | LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
#define | LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
SAMR - Slave Address Match Register
#define | LPI2C_SAMR_ADDR0_MASK (0x7FEU)
#define | LPI2C_SAMR_ADDR0_SHIFT (1U)
#define | LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
#define | LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
#define | LPI2C_SAMR_ADDR1_SHIFT (17U)
#define | LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
SASR - Slave Address Status Register
#define | LPI2C_SASR_RADDR_MASK (0x7FFU)
#define | LPI2C_SASR_RADDR_SHIFT (0U)
#define | LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
#define | LPI2C_SASR_ANV_MASK (0x4000U)
#define | LPI2C_SASR_ANV_SHIFT (14U)
#define | LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
STAR - Slave Transmit ACK Register
#define | LPI2C_STAR_TXNACK_MASK (0x1U)
#define | LPI2C_STAR_TXNACK_SHIFT (0U)
#define | LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
STDR - Slave Transmit Data Register
#define | LPI2C_STDR_DATA_MASK (0xFFU)
#define | LPI2C_STDR_DATA_SHIFT (0U)
#define | LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
SRDR - Slave Receive Data Register
#define | LPI2C_SRDR_DATA_MASK (0xFFU)
#define | LPI2C_SRDR_DATA_SHIFT (0U)
#define | LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
#define | LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
#define | LPI2C_SRDR_RXEMPTY_SHIFT (14U)
#define | LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
#define | LPI2C_SRDR_SOF_MASK (0x8000U)
#define | LPI2C_SRDR_SOF_SHIFT (15U)
#define | LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
SR - Status Register
#define | LPSPI_SR_TDF_MASK (0x1U)
#define | LPSPI_SR_TDF_SHIFT (0U)
#define | LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
#define | LPSPI_SR_RDF_MASK (0x2U)
#define | LPSPI_SR_RDF_SHIFT (1U)
#define | LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
#define | LPSPI_SR_WCF_MASK (0x100U)
#define | LPSPI_SR_WCF_SHIFT (8U)
#define | LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
#define | LPSPI_SR_FCF_MASK (0x200U)
#define | LPSPI_SR_FCF_SHIFT (9U)
#define | LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
#define | LPSPI_SR_TCF_MASK (0x400U)
#define | LPSPI_SR_TCF_SHIFT (10U)
#define | LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
#define | LPSPI_SR_TEF_MASK (0x800U)
#define | LPSPI_SR_TEF_SHIFT (11U)
#define | LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
#define | LPSPI_SR_REF_MASK (0x1000U)
#define | LPSPI_SR_REF_SHIFT (12U)
#define | LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
#define | LPSPI_SR_DMF_MASK (0x2000U)
#define | LPSPI_SR_DMF_SHIFT (13U)
#define | LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
#define | LPSPI_SR_MBF_MASK (0x1000000U)
#define | LPSPI_SR_MBF_SHIFT (24U)
#define | LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
IER - Interrupt Enable Register
#define | LPSPI_IER_TDIE_MASK (0x1U)
#define | LPSPI_IER_TDIE_SHIFT (0U)
#define | LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
#define | LPSPI_IER_RDIE_MASK (0x2U)
#define | LPSPI_IER_RDIE_SHIFT (1U)
#define | LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
#define | LPSPI_IER_WCIE_MASK (0x100U)
#define | LPSPI_IER_WCIE_SHIFT (8U)
#define | LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
#define | LPSPI_IER_FCIE_MASK (0x200U)
#define | LPSPI_IER_FCIE_SHIFT (9U)
#define | LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
#define | LPSPI_IER_TCIE_MASK (0x400U)
#define | LPSPI_IER_TCIE_SHIFT (10U)
#define | LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
#define | LPSPI_IER_TEIE_MASK (0x800U)
#define | LPSPI_IER_TEIE_SHIFT (11U)
#define | LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
#define | LPSPI_IER_REIE_MASK (0x1000U)
#define | LPSPI_IER_REIE_SHIFT (12U)
#define | LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
#define | LPSPI_IER_DMIE_MASK (0x2000U)
#define | LPSPI_IER_DMIE_SHIFT (13U)
#define | LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
DER - DMA Enable Register
#define | LPSPI_DER_TDDE_MASK (0x1U)
#define | LPSPI_DER_TDDE_SHIFT (0U)
#define | LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
#define | LPSPI_DER_RDDE_MASK (0x2U)
#define | LPSPI_DER_RDDE_SHIFT (1U)
#define | LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
CFGR0 - Configuration Register 0
#define | LPSPI_CFGR0_HREN_MASK (0x1U)
#define | LPSPI_CFGR0_HREN_SHIFT (0U)
#define | LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
#define | LPSPI_CFGR0_HRPOL_MASK (0x2U)
#define | LPSPI_CFGR0_HRPOL_SHIFT (1U)
#define | LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
#define | LPSPI_CFGR0_HRSEL_MASK (0x4U)
#define | LPSPI_CFGR0_HRSEL_SHIFT (2U)
#define | LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
#define | LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
#define | LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
#define | LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
#define | LPSPI_CFGR0_RDMO_MASK (0x200U)
#define | LPSPI_CFGR0_RDMO_SHIFT (9U)
#define | LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
CFGR1 - Configuration Register 1
#define | LPSPI_CFGR1_MASTER_MASK (0x1U)
#define | LPSPI_CFGR1_MASTER_SHIFT (0U)
#define | LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
#define | LPSPI_CFGR1_SAMPLE_MASK (0x2U)
#define | LPSPI_CFGR1_SAMPLE_SHIFT (1U)
#define | LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
#define | LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
#define | LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
#define | LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
#define | LPSPI_CFGR1_NOSTALL_MASK (0x8U)
#define | LPSPI_CFGR1_NOSTALL_SHIFT (3U)
#define | LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
#define | LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
#define | LPSPI_CFGR1_PCSPOL_SHIFT (8U)
#define | LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
#define | LPSPI_CFGR1_MATCFG_MASK (0x70000U)
#define | LPSPI_CFGR1_MATCFG_SHIFT (16U)
#define | LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
#define | LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
#define | LPSPI_CFGR1_PINCFG_SHIFT (24U)
#define | LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
#define | LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
#define | LPSPI_CFGR1_OUTCFG_SHIFT (26U)
#define | LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
#define | LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
#define | LPSPI_CFGR1_PCSCFG_SHIFT (27U)
#define | LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
DMR0 - Data Match Register 0
#define | LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
#define | LPSPI_DMR0_MATCH0_SHIFT (0U)
#define | LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
DMR1 - Data Match Register 1
#define | LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
#define | LPSPI_DMR1_MATCH1_SHIFT (0U)
#define | LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
CCR - Clock Configuration Register
#define | LPSPI_CCR_SCKDIV_MASK (0xFFU)
#define | LPSPI_CCR_SCKDIV_SHIFT (0U)
#define | LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
#define | LPSPI_CCR_DBT_MASK (0xFF00U)
#define | LPSPI_CCR_DBT_SHIFT (8U)
#define | LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
#define | LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
#define | LPSPI_CCR_PCSSCK_SHIFT (16U)
#define | LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
#define | LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
#define | LPSPI_CCR_SCKPCS_SHIFT (24U)
#define | LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
FCR - FIFO Control Register
#define | LPSPI_FCR_TXWATER_MASK (0xFU)
#define | LPSPI_FCR_TXWATER_SHIFT (0U)
#define | LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
#define | LPSPI_FCR_RXWATER_MASK (0xF0000U)
#define | LPSPI_FCR_RXWATER_SHIFT (16U)
#define | LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
FSR - FIFO Status Register
#define | LPSPI_FSR_TXCOUNT_MASK (0x1FU)
#define | LPSPI_FSR_TXCOUNT_SHIFT (0U)
#define | LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
#define | LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
#define | LPSPI_FSR_RXCOUNT_SHIFT (16U)
#define | LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
TCR - Transmit Command Register
#define | LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
#define | LPSPI_TCR_FRAMESZ_SHIFT (0U)
#define | LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
#define | LPSPI_TCR_WIDTH_MASK (0x30000U)
#define | LPSPI_TCR_WIDTH_SHIFT (16U)
#define | LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
#define | LPSPI_TCR_TXMSK_MASK (0x40000U)
#define | LPSPI_TCR_TXMSK_SHIFT (18U)
#define | LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
#define | LPSPI_TCR_RXMSK_MASK (0x80000U)
#define | LPSPI_TCR_RXMSK_SHIFT (19U)
#define | LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
#define | LPSPI_TCR_CONTC_MASK (0x100000U)
#define | LPSPI_TCR_CONTC_SHIFT (20U)
#define | LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
#define | LPSPI_TCR_CONT_MASK (0x200000U)
#define | LPSPI_TCR_CONT_SHIFT (21U)
#define | LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
#define | LPSPI_TCR_BYSW_MASK (0x400000U)
#define | LPSPI_TCR_BYSW_SHIFT (22U)
#define | LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
#define | LPSPI_TCR_LSBF_MASK (0x800000U)
#define | LPSPI_TCR_LSBF_SHIFT (23U)
#define | LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
#define | LPSPI_TCR_PCS_MASK (0x3000000U)
#define | LPSPI_TCR_PCS_SHIFT (24U)
#define | LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
#define | LPSPI_TCR_PRESCALE_MASK (0x38000000U)
#define | LPSPI_TCR_PRESCALE_SHIFT (27U)
#define | LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
#define | LPSPI_TCR_CPHA_MASK (0x40000000U)
#define | LPSPI_TCR_CPHA_SHIFT (30U)
#define | LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
#define | LPSPI_TCR_CPOL_MASK (0x80000000U)
#define | LPSPI_TCR_CPOL_SHIFT (31U)
#define | LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
TDR - Transmit Data Register
#define | LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
#define | LPSPI_TDR_DATA_SHIFT (0U)
#define | LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
RSR - Receive Status Register
#define | LPSPI_RSR_SOF_MASK (0x1U)
#define | LPSPI_RSR_SOF_SHIFT (0U)
#define | LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
#define | LPSPI_RSR_RXEMPTY_MASK (0x2U)
#define | LPSPI_RSR_RXEMPTY_SHIFT (1U)
#define | LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
RDR - Receive Data Register
#define | LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
#define | LPSPI_RDR_DATA_SHIFT (0U)
#define | LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
GLOBAL - LPUART Global Register
#define | LPUART_GLOBAL_RST_MASK (0x2U)
#define | LPUART_GLOBAL_RST_SHIFT (1U)
#define | LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
PINCFG - LPUART Pin Configuration Register
#define | LPUART_PINCFG_TRGSEL_MASK (0x3U)
#define | LPUART_PINCFG_TRGSEL_SHIFT (0U)
#define | LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
BAUD - LPUART Baud Rate Register
#define | LPUART_BAUD_SBR_MASK (0x1FFFU)
#define | LPUART_BAUD_SBR_SHIFT (0U)
#define | LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
#define | LPUART_BAUD_SBNS_MASK (0x2000U)
#define | LPUART_BAUD_SBNS_SHIFT (13U)
#define | LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
#define | LPUART_BAUD_RXEDGIE_MASK (0x4000U)
#define | LPUART_BAUD_RXEDGIE_SHIFT (14U)
#define | LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
#define | LPUART_BAUD_LBKDIE_MASK (0x8000U)
#define | LPUART_BAUD_LBKDIE_SHIFT (15U)
#define | LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
#define | LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
#define | LPUART_BAUD_RESYNCDIS_SHIFT (16U)
#define | LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
#define | LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
#define | LPUART_BAUD_BOTHEDGE_SHIFT (17U)
#define | LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
#define | LPUART_BAUD_MATCFG_MASK (0xC0000U)
#define | LPUART_BAUD_MATCFG_SHIFT (18U)
#define | LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
#define | LPUART_BAUD_RIDMAE_MASK (0x100000U)
#define | LPUART_BAUD_RIDMAE_SHIFT (20U)
#define | LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
#define | LPUART_BAUD_RDMAE_MASK (0x200000U)
#define | LPUART_BAUD_RDMAE_SHIFT (21U)
#define | LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
#define | LPUART_BAUD_TDMAE_MASK (0x800000U)
#define | LPUART_BAUD_TDMAE_SHIFT (23U)
#define | LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
#define | LPUART_BAUD_OSR_MASK (0x1F000000U)
#define | LPUART_BAUD_OSR_SHIFT (24U)
#define | LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
#define | LPUART_BAUD_M10_MASK (0x20000000U)
#define | LPUART_BAUD_M10_SHIFT (29U)
#define | LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
#define | LPUART_BAUD_MAEN2_MASK (0x40000000U)
#define | LPUART_BAUD_MAEN2_SHIFT (30U)
#define | LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
#define | LPUART_BAUD_MAEN1_MASK (0x80000000U)
#define | LPUART_BAUD_MAEN1_SHIFT (31U)
#define | LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
STAT - LPUART Status Register
#define | LPUART_STAT_MA2F_MASK (0x4000U)
#define | LPUART_STAT_MA2F_SHIFT (14U)
#define | LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
#define | LPUART_STAT_MA1F_MASK (0x8000U)
#define | LPUART_STAT_MA1F_SHIFT (15U)
#define | LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
#define | LPUART_STAT_PF_MASK (0x10000U)
#define | LPUART_STAT_PF_SHIFT (16U)
#define | LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
#define | LPUART_STAT_FE_MASK (0x20000U)
#define | LPUART_STAT_FE_SHIFT (17U)
#define | LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
#define | LPUART_STAT_NF_MASK (0x40000U)
#define | LPUART_STAT_NF_SHIFT (18U)
#define | LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
#define | LPUART_STAT_OR_MASK (0x80000U)
#define | LPUART_STAT_OR_SHIFT (19U)
#define | LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
#define | LPUART_STAT_IDLE_MASK (0x100000U)
#define | LPUART_STAT_IDLE_SHIFT (20U)
#define | LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
#define | LPUART_STAT_RDRF_MASK (0x200000U)
#define | LPUART_STAT_RDRF_SHIFT (21U)
#define | LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
#define | LPUART_STAT_TC_MASK (0x400000U)
#define | LPUART_STAT_TC_SHIFT (22U)
#define | LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
#define | LPUART_STAT_TDRE_MASK (0x800000U)
#define | LPUART_STAT_TDRE_SHIFT (23U)
#define | LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
#define | LPUART_STAT_RAF_MASK (0x1000000U)
#define | LPUART_STAT_RAF_SHIFT (24U)
#define | LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
#define | LPUART_STAT_LBKDE_MASK (0x2000000U)
#define | LPUART_STAT_LBKDE_SHIFT (25U)
#define | LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
#define | LPUART_STAT_BRK13_MASK (0x4000000U)
#define | LPUART_STAT_BRK13_SHIFT (26U)
#define | LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
#define | LPUART_STAT_RWUID_MASK (0x8000000U)
#define | LPUART_STAT_RWUID_SHIFT (27U)
#define | LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
#define | LPUART_STAT_RXINV_MASK (0x10000000U)
#define | LPUART_STAT_RXINV_SHIFT (28U)
#define | LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
#define | LPUART_STAT_MSBF_MASK (0x20000000U)
#define | LPUART_STAT_MSBF_SHIFT (29U)
#define | LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
#define | LPUART_STAT_RXEDGIF_MASK (0x40000000U)
#define | LPUART_STAT_RXEDGIF_SHIFT (30U)
#define | LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
#define | LPUART_STAT_LBKDIF_MASK (0x80000000U)
#define | LPUART_STAT_LBKDIF_SHIFT (31U)
#define | LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
CTRL - LPUART Control Register
#define | LPUART_CTRL_PT_MASK (0x1U)
#define | LPUART_CTRL_PT_SHIFT (0U)
#define | LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
#define | LPUART_CTRL_PE_MASK (0x2U)
#define | LPUART_CTRL_PE_SHIFT (1U)
#define | LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
#define | LPUART_CTRL_ILT_MASK (0x4U)
#define | LPUART_CTRL_ILT_SHIFT (2U)
#define | LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
#define | LPUART_CTRL_WAKE_MASK (0x8U)
#define | LPUART_CTRL_WAKE_SHIFT (3U)
#define | LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
#define | LPUART_CTRL_M_MASK (0x10U)
#define | LPUART_CTRL_M_SHIFT (4U)
#define | LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
#define | LPUART_CTRL_RSRC_MASK (0x20U)
#define | LPUART_CTRL_RSRC_SHIFT (5U)
#define | LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
#define | LPUART_CTRL_DOZEEN_MASK (0x40U)
#define | LPUART_CTRL_DOZEEN_SHIFT (6U)
#define | LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
#define | LPUART_CTRL_LOOPS_MASK (0x80U)
#define | LPUART_CTRL_LOOPS_SHIFT (7U)
#define | LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
#define | LPUART_CTRL_IDLECFG_MASK (0x700U)
#define | LPUART_CTRL_IDLECFG_SHIFT (8U)
#define | LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
#define | LPUART_CTRL_M7_MASK (0x800U)
#define | LPUART_CTRL_M7_SHIFT (11U)
#define | LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
#define | LPUART_CTRL_MA2IE_MASK (0x4000U)
#define | LPUART_CTRL_MA2IE_SHIFT (14U)
#define | LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
#define | LPUART_CTRL_MA1IE_MASK (0x8000U)
#define | LPUART_CTRL_MA1IE_SHIFT (15U)
#define | LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
#define | LPUART_CTRL_SBK_MASK (0x10000U)
#define | LPUART_CTRL_SBK_SHIFT (16U)
#define | LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
#define | LPUART_CTRL_RWU_MASK (0x20000U)
#define | LPUART_CTRL_RWU_SHIFT (17U)
#define | LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
#define | LPUART_CTRL_RE_MASK (0x40000U)
#define | LPUART_CTRL_RE_SHIFT (18U)
#define | LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
#define | LPUART_CTRL_TE_MASK (0x80000U)
#define | LPUART_CTRL_TE_SHIFT (19U)
#define | LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
#define | LPUART_CTRL_ILIE_MASK (0x100000U)
#define | LPUART_CTRL_ILIE_SHIFT (20U)
#define | LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
#define | LPUART_CTRL_RIE_MASK (0x200000U)
#define | LPUART_CTRL_RIE_SHIFT (21U)
#define | LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
#define | LPUART_CTRL_TCIE_MASK (0x400000U)
#define | LPUART_CTRL_TCIE_SHIFT (22U)
#define | LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
#define | LPUART_CTRL_TIE_MASK (0x800000U)
#define | LPUART_CTRL_TIE_SHIFT (23U)
#define | LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
#define | LPUART_CTRL_PEIE_MASK (0x1000000U)
#define | LPUART_CTRL_PEIE_SHIFT (24U)
#define | LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
#define | LPUART_CTRL_FEIE_MASK (0x2000000U)
#define | LPUART_CTRL_FEIE_SHIFT (25U)
#define | LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
#define | LPUART_CTRL_NEIE_MASK (0x4000000U)
#define | LPUART_CTRL_NEIE_SHIFT (26U)
#define | LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
#define | LPUART_CTRL_ORIE_MASK (0x8000000U)
#define | LPUART_CTRL_ORIE_SHIFT (27U)
#define | LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
#define | LPUART_CTRL_TXINV_MASK (0x10000000U)
#define | LPUART_CTRL_TXINV_SHIFT (28U)
#define | LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
#define | LPUART_CTRL_TXDIR_MASK (0x20000000U)
#define | LPUART_CTRL_TXDIR_SHIFT (29U)
#define | LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
#define | LPUART_CTRL_R9T8_MASK (0x40000000U)
#define | LPUART_CTRL_R9T8_SHIFT (30U)
#define | LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
#define | LPUART_CTRL_R8T9_MASK (0x80000000U)
#define | LPUART_CTRL_R8T9_SHIFT (31U)
#define | LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
DATA - LPUART Data Register
#define | LPUART_DATA_R0T0_MASK (0x1U)
#define | LPUART_DATA_R0T0_SHIFT (0U)
#define | LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
#define | LPUART_DATA_R1T1_MASK (0x2U)
#define | LPUART_DATA_R1T1_SHIFT (1U)
#define | LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
#define | LPUART_DATA_R2T2_MASK (0x4U)
#define | LPUART_DATA_R2T2_SHIFT (2U)
#define | LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
#define | LPUART_DATA_R3T3_MASK (0x8U)
#define | LPUART_DATA_R3T3_SHIFT (3U)
#define | LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
#define | LPUART_DATA_R4T4_MASK (0x10U)
#define | LPUART_DATA_R4T4_SHIFT (4U)
#define | LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
#define | LPUART_DATA_R5T5_MASK (0x20U)
#define | LPUART_DATA_R5T5_SHIFT (5U)
#define | LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
#define | LPUART_DATA_R6T6_MASK (0x40U)
#define | LPUART_DATA_R6T6_SHIFT (6U)
#define | LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
#define | LPUART_DATA_R7T7_MASK (0x80U)
#define | LPUART_DATA_R7T7_SHIFT (7U)
#define | LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
#define | LPUART_DATA_R8T8_MASK (0x100U)
#define | LPUART_DATA_R8T8_SHIFT (8U)
#define | LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
#define | LPUART_DATA_R9T9_MASK (0x200U)
#define | LPUART_DATA_R9T9_SHIFT (9U)
#define | LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
#define | LPUART_DATA_IDLINE_MASK (0x800U)
#define | LPUART_DATA_IDLINE_SHIFT (11U)
#define | LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
#define | LPUART_DATA_RXEMPT_MASK (0x1000U)
#define | LPUART_DATA_RXEMPT_SHIFT (12U)
#define | LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
#define | LPUART_DATA_FRETSC_MASK (0x2000U)
#define | LPUART_DATA_FRETSC_SHIFT (13U)
#define | LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
#define | LPUART_DATA_PARITYE_MASK (0x4000U)
#define | LPUART_DATA_PARITYE_SHIFT (14U)
#define | LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
#define | LPUART_DATA_NOISY_MASK (0x8000U)
#define | LPUART_DATA_NOISY_SHIFT (15U)
#define | LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
MATCH - LPUART Match Address Register
#define | LPUART_MATCH_MA1_MASK (0x3FFU)
#define | LPUART_MATCH_MA1_SHIFT (0U)
#define | LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
#define | LPUART_MATCH_MA2_MASK (0x3FF0000U)
#define | LPUART_MATCH_MA2_SHIFT (16U)
#define | LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
MODIR - LPUART Modem IrDA Register
#define | LPUART_MODIR_TXCTSE_MASK (0x1U)
#define | LPUART_MODIR_TXCTSE_SHIFT (0U)
#define | LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
#define | LPUART_MODIR_TXRTSE_MASK (0x2U)
#define | LPUART_MODIR_TXRTSE_SHIFT (1U)
#define | LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
#define | LPUART_MODIR_TXRTSPOL_MASK (0x4U)
#define | LPUART_MODIR_TXRTSPOL_SHIFT (2U)
#define | LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
#define | LPUART_MODIR_RXRTSE_MASK (0x8U)
#define | LPUART_MODIR_RXRTSE_SHIFT (3U)
#define | LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
#define | LPUART_MODIR_TXCTSC_MASK (0x10U)
#define | LPUART_MODIR_TXCTSC_SHIFT (4U)
#define | LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
#define | LPUART_MODIR_TXCTSSRC_MASK (0x20U)
#define | LPUART_MODIR_TXCTSSRC_SHIFT (5U)
#define | LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
#define | LPUART_MODIR_RTSWATER_MASK (0x300U)
#define | LPUART_MODIR_RTSWATER_SHIFT (8U)
#define | LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
#define | LPUART_MODIR_TNP_MASK (0x30000U)
#define | LPUART_MODIR_TNP_SHIFT (16U)
#define | LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
#define | LPUART_MODIR_IREN_MASK (0x40000U)
#define | LPUART_MODIR_IREN_SHIFT (18U)
#define | LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
FIFO - LPUART FIFO Register
#define | LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
#define | LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
#define | LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
#define | LPUART_FIFO_RXFE_MASK (0x8U)
#define | LPUART_FIFO_RXFE_SHIFT (3U)
#define | LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
#define | LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
#define | LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
#define | LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
#define | LPUART_FIFO_TXFE_MASK (0x80U)
#define | LPUART_FIFO_TXFE_SHIFT (7U)
#define | LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
#define | LPUART_FIFO_RXUFE_MASK (0x100U)
#define | LPUART_FIFO_RXUFE_SHIFT (8U)
#define | LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
#define | LPUART_FIFO_TXOFE_MASK (0x200U)
#define | LPUART_FIFO_TXOFE_SHIFT (9U)
#define | LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
#define | LPUART_FIFO_RXIDEN_MASK (0x1C00U)
#define | LPUART_FIFO_RXIDEN_SHIFT (10U)
#define | LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
#define | LPUART_FIFO_RXFLUSH_MASK (0x4000U)
#define | LPUART_FIFO_RXFLUSH_SHIFT (14U)
#define | LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
#define | LPUART_FIFO_TXFLUSH_MASK (0x8000U)
#define | LPUART_FIFO_TXFLUSH_SHIFT (15U)
#define | LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
#define | LPUART_FIFO_RXUF_MASK (0x10000U)
#define | LPUART_FIFO_RXUF_SHIFT (16U)
#define | LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
#define | LPUART_FIFO_TXOF_MASK (0x20000U)
#define | LPUART_FIFO_TXOF_SHIFT (17U)
#define | LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
#define | LPUART_FIFO_RXEMPT_MASK (0x400000U)
#define | LPUART_FIFO_RXEMPT_SHIFT (22U)
#define | LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
#define | LPUART_FIFO_TXEMPT_MASK (0x800000U)
#define | LPUART_FIFO_TXEMPT_SHIFT (23U)
#define | LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
WATER - LPUART Watermark Register
#define | LPUART_WATER_TXWATER_MASK (0x3U)
#define | LPUART_WATER_TXWATER_SHIFT (0U)
#define | LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
#define | LPUART_WATER_TXCOUNT_MASK (0x700U)
#define | LPUART_WATER_TXCOUNT_SHIFT (8U)
#define | LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
#define | LPUART_WATER_RXWATER_MASK (0x30000U)
#define | LPUART_WATER_RXWATER_SHIFT (16U)
#define | LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
#define | LPUART_WATER_RXCOUNT_MASK (0x7000000U)
#define | LPUART_WATER_RXCOUNT_SHIFT (24U)
#define | LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
CTRL - OTP Controller Control Register
#define | OCOTP_CTRL_ADDR_MASK (0x3FU)
#define | OCOTP_CTRL_ADDR_SHIFT (0U)
#define | OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
#define | OCOTP_CTRL_RSVD0_MASK (0xC0U)
#define | OCOTP_CTRL_RSVD0_SHIFT (6U)
#define | OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD0_SHIFT)) & OCOTP_CTRL_RSVD0_MASK)
#define | OCOTP_CTRL_BUSY_MASK (0x100U)
#define | OCOTP_CTRL_BUSY_SHIFT (8U)
#define | OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
#define | OCOTP_CTRL_ERROR_MASK (0x200U)
#define | OCOTP_CTRL_ERROR_SHIFT (9U)
#define | OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
#define | OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
#define | OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
#define | OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
#define | OCOTP_CTRL_CRC_TEST_MASK (0x800U)
#define | OCOTP_CTRL_CRC_TEST_SHIFT (11U)
#define | OCOTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_CTRL_CRC_TEST_MASK)
#define | OCOTP_CTRL_CRC_FAIL_MASK (0x1000U)
#define | OCOTP_CTRL_CRC_FAIL_SHIFT (12U)
#define | OCOTP_CTRL_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CRC_FAIL_MASK)
#define | OCOTP_CTRL_RSVD1_MASK (0xE000U)
#define | OCOTP_CTRL_RSVD1_SHIFT (13U)
#define | OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD1_SHIFT)) & OCOTP_CTRL_RSVD1_MASK)
#define | OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
#define | OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
#define | OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
CTRL_SET - OTP Controller Control Register
#define | OCOTP_CTRL_SET_ADDR_MASK (0x3FU)
#define | OCOTP_CTRL_SET_ADDR_SHIFT (0U)
#define | OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
#define | OCOTP_CTRL_SET_RSVD0_MASK (0xC0U)
#define | OCOTP_CTRL_SET_RSVD0_SHIFT (6U)
#define | OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD0_SHIFT)) & OCOTP_CTRL_SET_RSVD0_MASK)
#define | OCOTP_CTRL_SET_BUSY_MASK (0x100U)
#define | OCOTP_CTRL_SET_BUSY_SHIFT (8U)
#define | OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
#define | OCOTP_CTRL_SET_ERROR_MASK (0x200U)
#define | OCOTP_CTRL_SET_ERROR_SHIFT (9U)
#define | OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
#define | OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
#define | OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
#define | OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
#define | OCOTP_CTRL_SET_CRC_TEST_MASK (0x800U)
#define | OCOTP_CTRL_SET_CRC_TEST_SHIFT (11U)
#define | OCOTP_CTRL_SET_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_TEST_SHIFT)) & OCOTP_CTRL_SET_CRC_TEST_MASK)
#define | OCOTP_CTRL_SET_CRC_FAIL_MASK (0x1000U)
#define | OCOTP_CTRL_SET_CRC_FAIL_SHIFT (12U)
#define | OCOTP_CTRL_SET_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_FAIL_SHIFT)) & OCOTP_CTRL_SET_CRC_FAIL_MASK)
#define | OCOTP_CTRL_SET_RSVD1_MASK (0xE000U)
#define | OCOTP_CTRL_SET_RSVD1_SHIFT (13U)
#define | OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD1_SHIFT)) & OCOTP_CTRL_SET_RSVD1_MASK)
#define | OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
#define | OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
#define | OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
CTRL_CLR - OTP Controller Control Register
#define | OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)
#define | OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
#define | OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
#define | OCOTP_CTRL_CLR_RSVD0_MASK (0xC0U)
#define | OCOTP_CTRL_CLR_RSVD0_SHIFT (6U)
#define | OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD0_SHIFT)) & OCOTP_CTRL_CLR_RSVD0_MASK)
#define | OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
#define | OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
#define | OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
#define | OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
#define | OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
#define | OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
#define | OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
#define | OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
#define | OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
#define | OCOTP_CTRL_CLR_CRC_TEST_MASK (0x800U)
#define | OCOTP_CTRL_CLR_CRC_TEST_SHIFT (11U)
#define | OCOTP_CTRL_CLR_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_TEST_SHIFT)) & OCOTP_CTRL_CLR_CRC_TEST_MASK)
#define | OCOTP_CTRL_CLR_CRC_FAIL_MASK (0x1000U)
#define | OCOTP_CTRL_CLR_CRC_FAIL_SHIFT (12U)
#define | OCOTP_CTRL_CLR_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CLR_CRC_FAIL_MASK)
#define | OCOTP_CTRL_CLR_RSVD1_MASK (0xE000U)
#define | OCOTP_CTRL_CLR_RSVD1_SHIFT (13U)
#define | OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD1_SHIFT)) & OCOTP_CTRL_CLR_RSVD1_MASK)
#define | OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
#define | OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
#define | OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
CTRL_TOG - OTP Controller Control Register
#define | OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)
#define | OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
#define | OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
#define | OCOTP_CTRL_TOG_RSVD0_MASK (0xC0U)
#define | OCOTP_CTRL_TOG_RSVD0_SHIFT (6U)
#define | OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD0_SHIFT)) & OCOTP_CTRL_TOG_RSVD0_MASK)
#define | OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
#define | OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
#define | OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
#define | OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
#define | OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
#define | OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
#define | OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
#define | OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
#define | OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
#define | OCOTP_CTRL_TOG_CRC_TEST_MASK (0x800U)
#define | OCOTP_CTRL_TOG_CRC_TEST_SHIFT (11U)
#define | OCOTP_CTRL_TOG_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_TEST_SHIFT)) & OCOTP_CTRL_TOG_CRC_TEST_MASK)
#define | OCOTP_CTRL_TOG_CRC_FAIL_MASK (0x1000U)
#define | OCOTP_CTRL_TOG_CRC_FAIL_SHIFT (12U)
#define | OCOTP_CTRL_TOG_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_FAIL_SHIFT)) & OCOTP_CTRL_TOG_CRC_FAIL_MASK)
#define | OCOTP_CTRL_TOG_RSVD1_MASK (0xE000U)
#define | OCOTP_CTRL_TOG_RSVD1_SHIFT (13U)
#define | OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD1_SHIFT)) & OCOTP_CTRL_TOG_RSVD1_MASK)
#define | OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
#define | OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
#define | OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
TIMING - OTP Controller Timing Register
#define | OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
#define | OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
#define | OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
#define | OCOTP_TIMING_RELAX_MASK (0xF000U)
#define | OCOTP_TIMING_RELAX_SHIFT (12U)
#define | OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
#define | OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
#define | OCOTP_TIMING_STROBE_READ_SHIFT (16U)
#define | OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
#define | OCOTP_TIMING_WAIT_MASK (0xFC00000U)
#define | OCOTP_TIMING_WAIT_SHIFT (22U)
#define | OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
#define | OCOTP_TIMING_RSRVD0_MASK (0xF0000000U)
#define | OCOTP_TIMING_RSRVD0_SHIFT (28U)
#define | OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK)
DATA - OTP Controller Write Data Register
#define | OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
#define | OCOTP_DATA_DATA_SHIFT (0U)
#define | OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
READ_CTRL - OTP Controller Write Data Register
#define | OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
#define | OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
#define | OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
#define | OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU)
#define | OCOTP_READ_CTRL_RSVD0_SHIFT (1U)
#define | OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK)
READ_FUSE_DATA - OTP Controller Read Data Register
#define | OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
#define | OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
#define | OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
SW_STICKY - Sticky bit Register
#define | OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)
#define | OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)
#define | OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)
#define | OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
#define | OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
#define | OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
#define | OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
#define | OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
#define | OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
#define | OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)
#define | OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)
#define | OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)
#define | OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)
#define | OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)
#define | OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)
#define | OCOTP_SW_STICKY_RSVD0_MASK (0xFFFFFFE0U)
#define | OCOTP_SW_STICKY_RSVD0_SHIFT (5U)
#define | OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK)
SCS - Software Controllable Signals Register
#define | OCOTP_SCS_HAB_JDE_MASK (0x1U)
#define | OCOTP_SCS_HAB_JDE_SHIFT (0U)
#define | OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
#define | OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
#define | OCOTP_SCS_SPARE_SHIFT (1U)
#define | OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
#define | OCOTP_SCS_LOCK_MASK (0x80000000U)
#define | OCOTP_SCS_LOCK_SHIFT (31U)
#define | OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
SCS_SET - Software Controllable Signals Register
#define | OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
#define | OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
#define | OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
#define | OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
#define | OCOTP_SCS_SET_SPARE_SHIFT (1U)
#define | OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
#define | OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
#define | OCOTP_SCS_SET_LOCK_SHIFT (31U)
#define | OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
SCS_CLR - Software Controllable Signals Register
#define | OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
#define | OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
#define | OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
#define | OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
#define | OCOTP_SCS_CLR_SPARE_SHIFT (1U)
#define | OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
#define | OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
#define | OCOTP_SCS_CLR_LOCK_SHIFT (31U)
#define | OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
SCS_TOG - Software Controllable Signals Register
#define | OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
#define | OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
#define | OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
#define | OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
#define | OCOTP_SCS_TOG_SPARE_SHIFT (1U)
#define | OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
#define | OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
#define | OCOTP_SCS_TOG_LOCK_SHIFT (31U)
#define | OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
CRC_ADDR - OTP Controller CRC test address
#define | OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xFFU)
#define | OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0U)
#define | OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_START_ADDR_MASK)
#define | OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xFF00U)
#define | OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8U)
#define | OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_END_ADDR_MASK)
#define | OCOTP_CRC_ADDR_CRC_ADDR_MASK (0xFF0000U)
#define | OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16U)
#define | OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)) & OCOTP_CRC_ADDR_CRC_ADDR_MASK)
#define | OCOTP_CRC_ADDR_OTPMK_CRC_MASK (0x1000000U)
#define | OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT (24U)
#define | OCOTP_CRC_ADDR_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT)) & OCOTP_CRC_ADDR_OTPMK_CRC_MASK)
#define | OCOTP_CRC_ADDR_RSVD0_MASK (0xFE000000U)
#define | OCOTP_CRC_ADDR_RSVD0_SHIFT (25U)
#define | OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_RSVD0_SHIFT)) & OCOTP_CRC_ADDR_RSVD0_MASK)
CRC_VALUE - OTP Controller CRC Value Register
#define | OCOTP_CRC_VALUE_DATA_MASK (0xFFFFFFFFU)
#define | OCOTP_CRC_VALUE_DATA_SHIFT (0U)
#define | OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_VALUE_DATA_SHIFT)) & OCOTP_CRC_VALUE_DATA_MASK)
VERSION - OTP Controller Version Register
#define | OCOTP_VERSION_STEP_MASK (0xFFFFU)
#define | OCOTP_VERSION_STEP_SHIFT (0U)
#define | OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
#define | OCOTP_VERSION_MINOR_MASK (0xFF0000U)
#define | OCOTP_VERSION_MINOR_SHIFT (16U)
#define | OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
#define | OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
#define | OCOTP_VERSION_MAJOR_SHIFT (24U)
#define | OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
TIMING2 - OTP Controller Timing Register
#define | OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)
#define | OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)
#define | OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
#define | OCOTP_TIMING2_RSRVD0_MASK (0xF000U)
#define | OCOTP_TIMING2_RSRVD0_SHIFT (12U)
#define | OCOTP_TIMING2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RSRVD0_SHIFT)) & OCOTP_TIMING2_RSRVD0_MASK)
#define | OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)
#define | OCOTP_TIMING2_RELAX_READ_SHIFT (16U)
#define | OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
#define | OCOTP_TIMING2_RSRVD1_MASK (0xFFC00000U)
#define | OCOTP_TIMING2_RSRVD1_SHIFT (22U)
#define | OCOTP_TIMING2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RSRVD1_SHIFT)) & OCOTP_TIMING2_RSRVD1_MASK)
LOCK - Value of OTP Bank0 Word0 (Lock controls)
#define | OCOTP_LOCK_TESTER_MASK (0x3U)
#define | OCOTP_LOCK_TESTER_SHIFT (0U)
#define | OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)
#define | OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
#define | OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
#define | OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
#define | OCOTP_LOCK_MEM_TRIM_MASK (0x30U)
#define | OCOTP_LOCK_MEM_TRIM_SHIFT (4U)
#define | OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)
#define | OCOTP_LOCK_SJC_RESP_MASK (0x40U)
#define | OCOTP_LOCK_SJC_RESP_SHIFT (6U)
#define | OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
#define | OCOTP_LOCK_GP4_RLOCK_MASK (0x80U)
#define | OCOTP_LOCK_GP4_RLOCK_SHIFT (7U)
#define | OCOTP_LOCK_GP4_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_RLOCK_SHIFT)) & OCOTP_LOCK_GP4_RLOCK_MASK)
#define | OCOTP_LOCK_MAC_ADDR_MASK (0x300U)
#define | OCOTP_LOCK_MAC_ADDR_SHIFT (8U)
#define | OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
#define | OCOTP_LOCK_GP1_MASK (0xC00U)
#define | OCOTP_LOCK_GP1_SHIFT (10U)
#define | OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
#define | OCOTP_LOCK_GP2_MASK (0x3000U)
#define | OCOTP_LOCK_GP2_SHIFT (12U)
#define | OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
#define | OCOTP_LOCK_ROM_PATCH_MASK (0x8000U)
#define | OCOTP_LOCK_ROM_PATCH_SHIFT (15U)
#define | OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK)
#define | OCOTP_LOCK_SW_GP1_MASK (0x10000U)
#define | OCOTP_LOCK_SW_GP1_SHIFT (16U)
#define | OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
#define | OCOTP_LOCK_OTPMK_MASK (0x20000U)
#define | OCOTP_LOCK_OTPMK_SHIFT (17U)
#define | OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK)
#define | OCOTP_LOCK_ANALOG_MASK (0xC0000U)
#define | OCOTP_LOCK_ANALOG_SHIFT (18U)
#define | OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
#define | OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)
#define | OCOTP_LOCK_OTPMK_CRC_SHIFT (20U)
#define | OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)
#define | OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)
#define | OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)
#define | OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
#define | OCOTP_LOCK_MISC_CONF_MASK (0x400000U)
#define | OCOTP_LOCK_MISC_CONF_SHIFT (22U)
#define | OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
#define | OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)
#define | OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)
#define | OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
#define | OCOTP_LOCK_GP4_MASK (0x3000000U)
#define | OCOTP_LOCK_GP4_SHIFT (24U)
#define | OCOTP_LOCK_GP4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_SHIFT)) & OCOTP_LOCK_GP4_MASK)
#define | OCOTP_LOCK_GP3_MASK (0xC000000U)
#define | OCOTP_LOCK_GP3_SHIFT (26U)
#define | OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
#define | OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)
#define | OCOTP_LOCK_FIELD_RETURN_SHIFT (28U)
#define | OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)
#define | OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_CFG0_BITS_SHIFT (0U)
#define | OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)
#define | OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_CFG1_BITS_SHIFT (0U)
#define | OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)
#define | OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_CFG2_BITS_SHIFT (0U)
#define | OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)
#define | OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_CFG3_BITS_SHIFT (0U)
#define | OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)
#define | OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_CFG4_BITS_SHIFT (0U)
#define | OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)
#define | OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_CFG5_BITS_SHIFT (0U)
#define | OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)
#define | OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_CFG6_BITS_SHIFT (0U)
#define | OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.)
#define | OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MEM0_BITS_SHIFT (0U)
#define | OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.)
#define | OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MEM1_BITS_SHIFT (0U)
#define | OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.)
#define | OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MEM2_BITS_SHIFT (0U)
#define | OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.)
#define | OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MEM3_BITS_SHIFT (0U)
#define | OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.)
#define | OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MEM4_BITS_SHIFT (0U)
#define | OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.)
#define | OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ANA0_BITS_SHIFT (0U)
#define | OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.)
#define | OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ANA1_BITS_SHIFT (0U)
#define | OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)
#define | OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ANA2_BITS_SHIFT (0U)
#define | OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
OTPMK0 - Value of OTP Bank2 Word0 (OTPMK Key)
#define | OCOTP_OTPMK0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK0_BITS_SHIFT (0U)
#define | OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK0_BITS_SHIFT)) & OCOTP_OTPMK0_BITS_MASK)
OTPMK1 - Value of OTP Bank2 Word1 (OTPMK Key)
#define | OCOTP_OTPMK1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK1_BITS_SHIFT (0U)
#define | OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK1_BITS_SHIFT)) & OCOTP_OTPMK1_BITS_MASK)
OTPMK2 - Value of OTP Bank2 Word2 (OTPMK Key)
#define | OCOTP_OTPMK2_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK2_BITS_SHIFT (0U)
#define | OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK2_BITS_SHIFT)) & OCOTP_OTPMK2_BITS_MASK)
OTPMK3 - Value of OTP Bank2 Word3 (OTPMK Key)
#define | OCOTP_OTPMK3_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK3_BITS_SHIFT (0U)
#define | OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK3_BITS_SHIFT)) & OCOTP_OTPMK3_BITS_MASK)
OTPMK4 - Value of OTP Bank2 Word4 (OTPMK Key)
#define | OCOTP_OTPMK4_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK4_BITS_SHIFT (0U)
#define | OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK4_BITS_SHIFT)) & OCOTP_OTPMK4_BITS_MASK)
OTPMK5 - Value of OTP Bank2 Word5 (OTPMK Key)
#define | OCOTP_OTPMK5_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK5_BITS_SHIFT (0U)
#define | OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK5_BITS_SHIFT)) & OCOTP_OTPMK5_BITS_MASK)
OTPMK6 - Value of OTP Bank2 Word6 (OTPMK Key)
#define | OCOTP_OTPMK6_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK6_BITS_SHIFT (0U)
#define | OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK6_BITS_SHIFT)) & OCOTP_OTPMK6_BITS_MASK)
OTPMK7 - Value of OTP Bank2 Word7 (OTPMK Key)
#define | OCOTP_OTPMK7_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK7_BITS_SHIFT (0U)
#define | OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK7_BITS_SHIFT)) & OCOTP_OTPMK7_BITS_MASK)
SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash)
#define | OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK0_BITS_SHIFT (0U)
#define | OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash)
#define | OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK1_BITS_SHIFT (0U)
#define | OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash)
#define | OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK2_BITS_SHIFT (0U)
#define | OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash)
#define | OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK3_BITS_SHIFT (0U)
#define | OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash)
#define | OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK4_BITS_SHIFT (0U)
#define | OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash)
#define | OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK5_BITS_SHIFT (0U)
#define | OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash)
#define | OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK6_BITS_SHIFT (0U)
#define | OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash)
#define | OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK7_BITS_SHIFT (0U)
#define | OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field)
#define | OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SJC_RESP0_BITS_SHIFT (0U)
#define | OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field)
#define | OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SJC_RESP1_BITS_SHIFT (0U)
#define | OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
MAC0 - Value of OTP Bank4 Word2 (MAC Address)
#define | OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MAC0_BITS_SHIFT (0U)
#define | OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
MAC1 - Value of OTP Bank4 Word3 (MAC Address)
#define | OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MAC1_BITS_SHIFT (0U)
#define | OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
MAC2 - Value of OTP Bank4 Word4 (MAC2 Address)
#define | OCOTP_MAC2_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MAC2_BITS_SHIFT (0U)
#define | OCOTP_MAC2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC2_BITS_SHIFT)) & OCOTP_MAC2_BITS_MASK)
OTPMK_CRC32 - Value of OTP Bank4 Word5 (CRC Key)
#define | OCOTP_OTPMK_CRC32_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_OTPMK_CRC32_BITS_SHIFT (0U)
#define | OCOTP_OTPMK_CRC32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK_CRC32_BITS_SHIFT)) & OCOTP_OTPMK_CRC32_BITS_MASK)
GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)
#define | OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP1_BITS_SHIFT (0U)
#define | OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)
#define | OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP2_BITS_SHIFT (0U)
#define | OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
SW_GP1 - Value of OTP Bank5 Word0 (SW GP1)
#define | OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SW_GP1_BITS_SHIFT (0U)
#define | OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
SW_GP20 - Value of OTP Bank5 Word1 (SW GP2)
#define | OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SW_GP20_BITS_SHIFT (0U)
#define | OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
SW_GP21 - Value of OTP Bank5 Word2 (SW GP2)
#define | OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SW_GP21_BITS_SHIFT (0U)
#define | OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
SW_GP22 - Value of OTP Bank5 Word3 (SW GP2)
#define | OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SW_GP22_BITS_SHIFT (0U)
#define | OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
SW_GP23 - Value of OTP Bank5 Word4 (SW GP2)
#define | OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SW_GP23_BITS_SHIFT (0U)
#define | OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf)
#define | OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MISC_CONF0_BITS_SHIFT (0U)
#define | OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf)
#define | OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_MISC_CONF1_BITS_SHIFT (0U)
#define | OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke)
#define | OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
#define | OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)
ROM_PATCH0 - Value of OTP Bank6 Word0 (ROM Patch)
#define | OCOTP_ROM_PATCH0_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ROM_PATCH0_BITS_SHIFT (0U)
#define | OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH0_BITS_SHIFT)) & OCOTP_ROM_PATCH0_BITS_MASK)
ROM_PATCH1 - Value of OTP Bank6 Word1 (ROM Patch)
#define | OCOTP_ROM_PATCH1_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ROM_PATCH1_BITS_SHIFT (0U)
#define | OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH1_BITS_SHIFT)) & OCOTP_ROM_PATCH1_BITS_MASK)
ROM_PATCH2 - Value of OTP Bank6 Word2 (ROM Patch)
#define | OCOTP_ROM_PATCH2_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ROM_PATCH2_BITS_SHIFT (0U)
#define | OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH2_BITS_SHIFT)) & OCOTP_ROM_PATCH2_BITS_MASK)
ROM_PATCH3 - Value of OTP Bank6 Word3 (ROM Patch)
#define | OCOTP_ROM_PATCH3_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ROM_PATCH3_BITS_SHIFT (0U)
#define | OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH3_BITS_SHIFT)) & OCOTP_ROM_PATCH3_BITS_MASK)
ROM_PATCH4 - Value of OTP Bank6 Word4 (ROM Patch)
#define | OCOTP_ROM_PATCH4_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ROM_PATCH4_BITS_SHIFT (0U)
#define | OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH4_BITS_SHIFT)) & OCOTP_ROM_PATCH4_BITS_MASK)
ROM_PATCH5 - Value of OTP Bank6 Word5 (ROM Patch)
#define | OCOTP_ROM_PATCH5_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ROM_PATCH5_BITS_SHIFT (0U)
#define | OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH5_BITS_SHIFT)) & OCOTP_ROM_PATCH5_BITS_MASK)
ROM_PATCH6 - Value of OTP Bank6 Word6 (ROM Patch)
#define | OCOTP_ROM_PATCH6_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ROM_PATCH6_BITS_SHIFT (0U)
#define | OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH6_BITS_SHIFT)) & OCOTP_ROM_PATCH6_BITS_MASK)
ROM_PATCH7 - Value of OTP Bank6 Word7 (ROM Patch)
#define | OCOTP_ROM_PATCH7_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_ROM_PATCH7_BITS_SHIFT (0U)
#define | OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH7_BITS_SHIFT)) & OCOTP_ROM_PATCH7_BITS_MASK)
GP30 - Value of OTP Bank7 Word0 (GP3)
#define | OCOTP_GP30_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP30_BITS_SHIFT (0U)
#define | OCOTP_GP30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP30_BITS_SHIFT)) & OCOTP_GP30_BITS_MASK)
GP31 - Value of OTP Bank7 Word1 (GP3)
#define | OCOTP_GP31_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP31_BITS_SHIFT (0U)
#define | OCOTP_GP31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP31_BITS_SHIFT)) & OCOTP_GP31_BITS_MASK)
GP32 - Value of OTP Bank7 Word2 (GP3)
#define | OCOTP_GP32_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP32_BITS_SHIFT (0U)
#define | OCOTP_GP32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP32_BITS_SHIFT)) & OCOTP_GP32_BITS_MASK)
GP33 - Value of OTP Bank7 Word3 (GP3)
#define | OCOTP_GP33_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP33_BITS_SHIFT (0U)
#define | OCOTP_GP33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP33_BITS_SHIFT)) & OCOTP_GP33_BITS_MASK)
GP40 - Value of OTP Bank7 Word4 (GP4)
#define | OCOTP_GP40_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP40_BITS_SHIFT (0U)
#define | OCOTP_GP40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP40_BITS_SHIFT)) & OCOTP_GP40_BITS_MASK)
GP41 - Value of OTP Bank7 Word5 (GP4)
#define | OCOTP_GP41_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP41_BITS_SHIFT (0U)
#define | OCOTP_GP41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP41_BITS_SHIFT)) & OCOTP_GP41_BITS_MASK)
GP42 - Value of OTP Bank7 Word6 (GP4)
#define | OCOTP_GP42_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP42_BITS_SHIFT (0U)
#define | OCOTP_GP42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP42_BITS_SHIFT)) & OCOTP_GP42_BITS_MASK)
GP43 - Value of OTP Bank7 Word7 (GP4)
#define | OCOTP_GP43_BITS_MASK (0xFFFFFFFFU)
#define | OCOTP_GP43_BITS_SHIFT (0U)
#define | OCOTP_GP43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP43_BITS_SHIFT)) & OCOTP_GP43_BITS_MASK)
MEGA_CTRL - PGC Mega Control Register
#define | PGC_MEGA_CTRL_PCR_MASK (0x1U)
#define | PGC_MEGA_CTRL_PCR_SHIFT (0U)
#define | PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register
#define | PGC_MEGA_PUPSCR_SW_MASK (0x3FU)
#define | PGC_MEGA_PUPSCR_SW_SHIFT (0U)
#define | PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
#define | PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)
#define | PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)
#define | PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register
#define | PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)
#define | PGC_MEGA_PDNSCR_ISO_SHIFT (0U)
#define | PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
#define | PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)
#define | PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)
#define | PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
MEGA_SR - PGC Mega Power Gating Controller Status Register
#define | PGC_MEGA_SR_PSR_MASK (0x1U)
#define | PGC_MEGA_SR_PSR_SHIFT (0U)
#define | PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
CPU_CTRL - PGC CPU Control Register
#define | PGC_CPU_CTRL_PCR_MASK (0x1U)
#define | PGC_CPU_CTRL_PCR_SHIFT (0U)
#define | PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
CPU_PUPSCR - PGC CPU Power Up Sequence Control Register
#define | PGC_CPU_PUPSCR_SW_MASK (0x3FU)
#define | PGC_CPU_PUPSCR_SW_SHIFT (0U)
#define | PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
#define | PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)
#define | PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)
#define | PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register
#define | PGC_CPU_PDNSCR_ISO_MASK (0x3FU)
#define | PGC_CPU_PDNSCR_ISO_SHIFT (0U)
#define | PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
#define | PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)
#define | PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)
#define | PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
CPU_SR - PGC CPU Power Gating Controller Status Register
#define | PGC_CPU_SR_PSR_MASK (0x1U)
#define | PGC_CPU_SR_PSR_SHIFT (0U)
#define | PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)
MCR - PIT Module Control Register
#define | PIT_MCR_FRZ_MASK (0x1U)
#define | PIT_MCR_FRZ_SHIFT (0U)
#define | PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
#define | PIT_MCR_MDIS_MASK (0x2U)
#define | PIT_MCR_MDIS_SHIFT (1U)
#define | PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
LTMR64H - PIT Upper Lifetime Timer Register
#define | PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
#define | PIT_LTMR64H_LTH_SHIFT (0U)
#define | PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
LTMR64L - PIT Lower Lifetime Timer Register
#define | PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
#define | PIT_LTMR64L_LTL_SHIFT (0U)
#define | PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
LDVAL - Timer Load Value Register
#define | PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
#define | PIT_LDVAL_TSV_SHIFT (0U)
#define | PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
CVAL - Current Timer Value Register
#define | PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
#define | PIT_CVAL_TVL_SHIFT (0U)
#define | PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
TCTRL - Timer Control Register
#define | PIT_TCTRL_TEN_MASK (0x1U)
#define | PIT_TCTRL_TEN_SHIFT (0U)
#define | PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
#define | PIT_TCTRL_TIE_MASK (0x2U)
#define | PIT_TCTRL_TIE_SHIFT (1U)
#define | PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
#define | PIT_TCTRL_CHN_MASK (0x4U)
#define | PIT_TCTRL_CHN_SHIFT (2U)
#define | PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
TFLG - Timer Flag Register
#define | PIT_TFLG_TIF_MASK (0x1U)
#define | PIT_TFLG_TIF_SHIFT (0U)
#define | PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
REG_1P1 - Regulator 1P1 Register
#define | PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
#define | PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
#define | PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
#define | PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
#define | PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
#define | PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
#define | PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
#define | PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
#define | PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
#define | PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
#define | PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
#define | PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
#define | PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
#define | PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
#define | PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
REG_1P1_SET - Regulator 1P1 Register
#define | PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
#define | PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
#define | PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
#define | PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
#define | PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
#define | PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
#define | PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
#define | PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
#define | PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
#define | PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
#define | PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
#define | PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
#define | PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
#define | PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
#define | PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
REG_1P1_CLR - Regulator 1P1 Register
#define | PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
#define | PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
#define | PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
#define | PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
#define | PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
#define | PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
#define | PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
#define | PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
#define | PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
#define | PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
#define | PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
#define | PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
#define | PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
#define | PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
#define | PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
REG_1P1_TOG - Regulator 1P1 Register
#define | PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
#define | PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
#define | PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
#define | PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
#define | PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
#define | PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
#define | PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
#define | PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
#define | PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
#define | PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
#define | PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
#define | PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
#define | PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
#define | PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
#define | PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
REG_3P0 - Regulator 3P0 Register
#define | PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
#define | PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
#define | PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
#define | PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
#define | PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
#define | PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
#define | PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
#define | PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
#define | PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
#define | PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
#define | PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
#define | PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
#define | PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
#define | PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
REG_3P0_SET - Regulator 3P0 Register
#define | PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
#define | PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
#define | PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
#define | PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
#define | PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
#define | PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
#define | PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
#define | PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
#define | PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
#define | PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
#define | PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
#define | PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
#define | PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
#define | PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
REG_3P0_CLR - Regulator 3P0 Register
#define | PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
#define | PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
#define | PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
#define | PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
#define | PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
#define | PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
#define | PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
#define | PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
#define | PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
#define | PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
#define | PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
#define | PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
#define | PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
#define | PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
REG_3P0_TOG - Regulator 3P0 Register
#define | PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
#define | PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
#define | PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
#define | PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
#define | PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
#define | PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
#define | PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
#define | PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
#define | PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
#define | PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
#define | PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
#define | PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
#define | PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
#define | PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
REG_2P5 - Regulator 2P5 Register
#define | PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
#define | PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
#define | PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
#define | PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
#define | PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
#define | PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
#define | PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
#define | PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
#define | PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
#define | PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
#define | PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
#define | PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
REG_2P5_SET - Regulator 2P5 Register
#define | PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
#define | PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
#define | PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
#define | PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
#define | PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
#define | PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
#define | PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
#define | PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
#define | PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
#define | PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
#define | PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
#define | PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
REG_2P5_CLR - Regulator 2P5 Register
#define | PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
#define | PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
#define | PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
#define | PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
#define | PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
#define | PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
#define | PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
#define | PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
#define | PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
#define | PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
#define | PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
#define | PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
REG_2P5_TOG - Regulator 2P5 Register
#define | PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
#define | PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
#define | PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
#define | PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
#define | PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
#define | PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
#define | PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define | PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define | PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
#define | PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
#define | PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
#define | PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
#define | PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
#define | PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
#define | PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
#define | PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define | PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
#define | PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
#define | PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
#define | PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
#define | PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
#define | PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
#define | PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
#define | PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
#define | PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define | PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
#define | PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
REG_CORE - Digital Regulator Core Register
#define | PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
#define | PMU_REG_CORE_REG0_TARG_SHIFT (0U)
#define | PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
#define | PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
#define | PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
#define | PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
#define | PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
#define | PMU_REG_CORE_REG1_TARG_SHIFT (9U)
#define | PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
#define | PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
#define | PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
#define | PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
#define | PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
#define | PMU_REG_CORE_REG2_TARG_SHIFT (18U)
#define | PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
#define | PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
#define | PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
#define | PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
#define | PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
#define | PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
#define | PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
#define | PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
#define | PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
#define | PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
REG_CORE_SET - Digital Regulator Core Register
#define | PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
#define | PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
#define | PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
#define | PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
#define | PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
#define | PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
#define | PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
#define | PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
#define | PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
#define | PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
#define | PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
#define | PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
#define | PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
#define | PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
#define | PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
#define | PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
#define | PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
#define | PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
#define | PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
#define | PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
#define | PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
#define | PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
#define | PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
#define | PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
REG_CORE_CLR - Digital Regulator Core Register
#define | PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
#define | PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
#define | PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
#define | PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
#define | PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
#define | PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
#define | PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
#define | PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
#define | PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
#define | PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
#define | PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
#define | PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
#define | PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
#define | PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
#define | PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
#define | PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
#define | PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
#define | PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
#define | PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
#define | PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
#define | PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
#define | PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
#define | PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
#define | PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
REG_CORE_TOG - Digital Regulator Core Register
#define | PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
#define | PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
#define | PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
#define | PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
#define | PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
#define | PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
#define | PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
#define | PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
#define | PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
#define | PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
#define | PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
#define | PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
#define | PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
#define | PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
#define | PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
#define | PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
#define | PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
#define | PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
#define | PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
#define | PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
#define | PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
#define | PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
#define | PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
#define | PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
MISC2 - Miscellaneous Control Register
#define | PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
#define | PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
#define | PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
#define | PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
#define | PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
#define | PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
#define | PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
#define | PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
#define | PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
#define | PMU_MISC2_PLL3_disable_MASK (0x80U)
#define | PMU_MISC2_PLL3_disable_SHIFT (7U)
#define | PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
#define | PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
#define | PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
#define | PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
#define | PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
#define | PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
#define | PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
#define | PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
#define | PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
#define | PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
#define | PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
#define | PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
#define | PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
#define | PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
#define | PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
#define | PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
#define | PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
#define | PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
#define | PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
#define | PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
#define | PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
#define | PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
#define | PMU_MISC2_REG2_OK_MASK (0x400000U)
#define | PMU_MISC2_REG2_OK_SHIFT (22U)
#define | PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
#define | PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
#define | PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
#define | PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
#define | PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
#define | PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
#define | PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
#define | PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
#define | PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
#define | PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
#define | PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
#define | PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
#define | PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
#define | PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)
#define | PMU_MISC2_VIDEO_DIV_SHIFT (30U)
#define | PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
MISC2_SET - Miscellaneous Control Register
#define | PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
#define | PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
#define | PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
#define | PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
#define | PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
#define | PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
#define | PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
#define | PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
#define | PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
#define | PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
#define | PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
#define | PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
#define | PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
#define | PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
#define | PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
#define | PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
#define | PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
#define | PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
#define | PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
#define | PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
#define | PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
#define | PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
#define | PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
#define | PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
#define | PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
#define | PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
#define | PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
#define | PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
#define | PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
#define | PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
#define | PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
#define | PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
#define | PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
#define | PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
#define | PMU_MISC2_SET_REG2_OK_SHIFT (22U)
#define | PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
#define | PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
#define | PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
#define | PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
#define | PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
#define | PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
#define | PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
#define | PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
#define | PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
#define | PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
#define | PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
#define | PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
#define | PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
#define | PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
#define | PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)
#define | PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
MISC2_CLR - Miscellaneous Control Register
#define | PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
#define | PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
#define | PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
#define | PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
#define | PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
#define | PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
#define | PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
#define | PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
#define | PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
#define | PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
#define | PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
#define | PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
#define | PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
#define | PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
#define | PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
#define | PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
#define | PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
#define | PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
#define | PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
#define | PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
#define | PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
#define | PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
#define | PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
#define | PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
#define | PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
#define | PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
#define | PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
#define | PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
#define | PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
#define | PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
#define | PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
#define | PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
#define | PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
#define | PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
#define | PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
#define | PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
#define | PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
#define | PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
#define | PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
#define | PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
#define | PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
#define | PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
#define | PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
#define | PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
#define | PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
#define | PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
#define | PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
#define | PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
#define | PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
#define | PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
#define | PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
MISC2_TOG - Miscellaneous Control Register
#define | PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
#define | PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
#define | PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
#define | PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
#define | PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
#define | PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
#define | PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
#define | PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
#define | PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
#define | PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
#define | PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
#define | PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
#define | PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
#define | PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
#define | PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
#define | PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
#define | PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
#define | PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
#define | PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
#define | PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
#define | PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
#define | PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
#define | PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
#define | PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
#define | PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
#define | PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
#define | PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
#define | PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
#define | PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
#define | PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
#define | PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
#define | PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
#define | PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
#define | PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
#define | PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
#define | PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
#define | PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
#define | PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
#define | PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
#define | PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
#define | PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
#define | PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
#define | PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
#define | PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
#define | PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
#define | PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
#define | PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
#define | PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
#define | PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
#define | PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
#define | PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)
CNT - Counter Register
#define | PWM_CNT_CNT_MASK (0xFFFFU)
#define | PWM_CNT_CNT_SHIFT (0U)
#define | PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
INIT - Initial Count Register
#define | PWM_INIT_INIT_MASK (0xFFFFU)
#define | PWM_INIT_INIT_SHIFT (0U)
#define | PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
VAL0 - Value Register 0
#define | PWM_VAL0_VAL0_MASK (0xFFFFU)
#define | PWM_VAL0_VAL0_SHIFT (0U)
#define | PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
FRACVAL1 - Fractional Value Register 1
#define | PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
#define | PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
#define | PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
VAL1 - Value Register 1
#define | PWM_VAL1_VAL1_MASK (0xFFFFU)
#define | PWM_VAL1_VAL1_SHIFT (0U)
#define | PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
FRACVAL2 - Fractional Value Register 2
#define | PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
#define | PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
#define | PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
VAL2 - Value Register 2
#define | PWM_VAL2_VAL2_MASK (0xFFFFU)
#define | PWM_VAL2_VAL2_SHIFT (0U)
#define | PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
FRACVAL3 - Fractional Value Register 3
#define | PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
#define | PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
#define | PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
VAL3 - Value Register 3
#define | PWM_VAL3_VAL3_MASK (0xFFFFU)
#define | PWM_VAL3_VAL3_SHIFT (0U)
#define | PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
FRACVAL4 - Fractional Value Register 4
#define | PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
#define | PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
#define | PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
VAL4 - Value Register 4
#define | PWM_VAL4_VAL4_MASK (0xFFFFU)
#define | PWM_VAL4_VAL4_SHIFT (0U)
#define | PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
FRACVAL5 - Fractional Value Register 5
#define | PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
#define | PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
#define | PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
VAL5 - Value Register 5
#define | PWM_VAL5_VAL5_MASK (0xFFFFU)
#define | PWM_VAL5_VAL5_SHIFT (0U)
#define | PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
FRCTRL - Fractional Control Register
#define | PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
#define | PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
#define | PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
#define | PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
#define | PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
#define | PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
#define | PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
#define | PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
#define | PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
#define | PWM_FRCTRL_FRAC_PU_MASK (0x100U)
#define | PWM_FRCTRL_FRAC_PU_SHIFT (8U)
#define | PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
#define | PWM_FRCTRL_TEST_MASK (0x8000U)
#define | PWM_FRCTRL_TEST_SHIFT (15U)
#define | PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
OCTRL - Output Control Register
#define | PWM_OCTRL_PWMXFS_MASK (0x3U)
#define | PWM_OCTRL_PWMXFS_SHIFT (0U)
#define | PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
#define | PWM_OCTRL_PWMBFS_MASK (0xCU)
#define | PWM_OCTRL_PWMBFS_SHIFT (2U)
#define | PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
#define | PWM_OCTRL_PWMAFS_MASK (0x30U)
#define | PWM_OCTRL_PWMAFS_SHIFT (4U)
#define | PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
#define | PWM_OCTRL_POLX_MASK (0x100U)
#define | PWM_OCTRL_POLX_SHIFT (8U)
#define | PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
#define | PWM_OCTRL_POLB_MASK (0x200U)
#define | PWM_OCTRL_POLB_SHIFT (9U)
#define | PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
#define | PWM_OCTRL_POLA_MASK (0x400U)
#define | PWM_OCTRL_POLA_SHIFT (10U)
#define | PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
#define | PWM_OCTRL_PWMX_IN_MASK (0x2000U)
#define | PWM_OCTRL_PWMX_IN_SHIFT (13U)
#define | PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
#define | PWM_OCTRL_PWMB_IN_MASK (0x4000U)
#define | PWM_OCTRL_PWMB_IN_SHIFT (14U)
#define | PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
#define | PWM_OCTRL_PWMA_IN_MASK (0x8000U)
#define | PWM_OCTRL_PWMA_IN_SHIFT (15U)
#define | PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
STS - Status Register
#define | PWM_STS_CMPF_MASK (0x3FU)
#define | PWM_STS_CMPF_SHIFT (0U)
#define | PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
#define | PWM_STS_CFX0_MASK (0x40U)
#define | PWM_STS_CFX0_SHIFT (6U)
#define | PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
#define | PWM_STS_CFX1_MASK (0x80U)
#define | PWM_STS_CFX1_SHIFT (7U)
#define | PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
#define | PWM_STS_CFB0_MASK (0x100U)
#define | PWM_STS_CFB0_SHIFT (8U)
#define | PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
#define | PWM_STS_CFB1_MASK (0x200U)
#define | PWM_STS_CFB1_SHIFT (9U)
#define | PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
#define | PWM_STS_CFA0_MASK (0x400U)
#define | PWM_STS_CFA0_SHIFT (10U)
#define | PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
#define | PWM_STS_CFA1_MASK (0x800U)
#define | PWM_STS_CFA1_SHIFT (11U)
#define | PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
#define | PWM_STS_RF_MASK (0x1000U)
#define | PWM_STS_RF_SHIFT (12U)
#define | PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
#define | PWM_STS_REF_MASK (0x2000U)
#define | PWM_STS_REF_SHIFT (13U)
#define | PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
#define | PWM_STS_RUF_MASK (0x4000U)
#define | PWM_STS_RUF_SHIFT (14U)
#define | PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
DMAEN - DMA Enable Register
#define | PWM_DMAEN_CX0DE_MASK (0x1U)
#define | PWM_DMAEN_CX0DE_SHIFT (0U)
#define | PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
#define | PWM_DMAEN_CX1DE_MASK (0x2U)
#define | PWM_DMAEN_CX1DE_SHIFT (1U)
#define | PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
#define | PWM_DMAEN_CB0DE_MASK (0x4U)
#define | PWM_DMAEN_CB0DE_SHIFT (2U)
#define | PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
#define | PWM_DMAEN_CB1DE_MASK (0x8U)
#define | PWM_DMAEN_CB1DE_SHIFT (3U)
#define | PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
#define | PWM_DMAEN_CA0DE_MASK (0x10U)
#define | PWM_DMAEN_CA0DE_SHIFT (4U)
#define | PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
#define | PWM_DMAEN_CA1DE_MASK (0x20U)
#define | PWM_DMAEN_CA1DE_SHIFT (5U)
#define | PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
#define | PWM_DMAEN_CAPTDE_MASK (0xC0U)
#define | PWM_DMAEN_CAPTDE_SHIFT (6U)
#define | PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
#define | PWM_DMAEN_FAND_MASK (0x100U)
#define | PWM_DMAEN_FAND_SHIFT (8U)
#define | PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
#define | PWM_DMAEN_VALDE_MASK (0x200U)
#define | PWM_DMAEN_VALDE_SHIFT (9U)
#define | PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
TCTRL - Output Trigger Control Register
#define | PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
#define | PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
#define | PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
#define | PWM_TCTRL_TRGFRQ_MASK (0x1000U)
#define | PWM_TCTRL_TRGFRQ_SHIFT (12U)
#define | PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
#define | PWM_TCTRL_PWBOT1_MASK (0x4000U)
#define | PWM_TCTRL_PWBOT1_SHIFT (14U)
#define | PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
#define | PWM_TCTRL_PWAOT0_MASK (0x8000U)
#define | PWM_TCTRL_PWAOT0_SHIFT (15U)
#define | PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1
#define | PWM_DISMAP_DIS0A_MASK (0xFU)
#define | PWM_DISMAP_DIS0A_SHIFT (0U)
#define | PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
#define | PWM_DISMAP_DIS1A_MASK (0xFU)
#define | PWM_DISMAP_DIS1A_SHIFT (0U)
#define | PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
#define | PWM_DISMAP_DIS0B_MASK (0xF0U)
#define | PWM_DISMAP_DIS0B_SHIFT (4U)
#define | PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
#define | PWM_DISMAP_DIS1B_MASK (0xF0U)
#define | PWM_DISMAP_DIS1B_SHIFT (4U)
#define | PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
#define | PWM_DISMAP_DIS0X_MASK (0xF00U)
#define | PWM_DISMAP_DIS0X_SHIFT (8U)
#define | PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
#define | PWM_DISMAP_DIS1X_MASK (0xF00U)
#define | PWM_DISMAP_DIS1X_SHIFT (8U)
#define | PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
DTCNT0 - Deadtime Count Register 0
#define | PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
#define | PWM_DTCNT0_DTCNT0_SHIFT (0U)
#define | PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
DTCNT1 - Deadtime Count Register 1
#define | PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
#define | PWM_DTCNT1_DTCNT1_SHIFT (0U)
#define | PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
CAPTCTRLA - Capture Control A Register
#define | PWM_CAPTCTRLA_ARMA_MASK (0x1U)
#define | PWM_CAPTCTRLA_ARMA_SHIFT (0U)
#define | PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
#define | PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
#define | PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
#define | PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
#define | PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
#define | PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
#define | PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
#define | PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
#define | PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
#define | PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
#define | PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
#define | PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
#define | PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
#define | PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
#define | PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
#define | PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
#define | PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
#define | PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
#define | PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
#define | PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
#define | PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
#define | PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
#define | PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
#define | PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
#define | PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
CAPTCOMPA - Capture Compare A Register
#define | PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
#define | PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
#define | PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
#define | PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
#define | PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
#define | PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
CAPTCTRLB - Capture Control B Register
#define | PWM_CAPTCTRLB_ARMB_MASK (0x1U)
#define | PWM_CAPTCTRLB_ARMB_SHIFT (0U)
#define | PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
#define | PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
#define | PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
#define | PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
#define | PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
#define | PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
#define | PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
#define | PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
#define | PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
#define | PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
#define | PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
#define | PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
#define | PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
#define | PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
#define | PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
#define | PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
#define | PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
#define | PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
#define | PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
#define | PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
#define | PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
#define | PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
#define | PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
#define | PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
#define | PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
CAPTCOMPB - Capture Compare B Register
#define | PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
#define | PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
#define | PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
#define | PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
#define | PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
#define | PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
CAPTCTRLX - Capture Control X Register
#define | PWM_CAPTCTRLX_ARMX_MASK (0x1U)
#define | PWM_CAPTCTRLX_ARMX_SHIFT (0U)
#define | PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
#define | PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
#define | PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
#define | PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
#define | PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
#define | PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
#define | PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
#define | PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
#define | PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
#define | PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
#define | PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
#define | PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
#define | PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
#define | PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
#define | PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
#define | PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
#define | PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
#define | PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
#define | PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
#define | PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
#define | PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
#define | PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
#define | PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
#define | PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
#define | PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
CAPTCOMPX - Capture Compare X Register
#define | PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
#define | PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
#define | PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
#define | PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
#define | PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
#define | PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
CVAL0 - Capture Value 0 Register
#define | PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
#define | PWM_CVAL0_CAPTVAL0_SHIFT (0U)
#define | PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
CVAL0CYC - Capture Value 0 Cycle Register
#define | PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
#define | PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
#define | PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
CVAL1 - Capture Value 1 Register
#define | PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
#define | PWM_CVAL1_CAPTVAL1_SHIFT (0U)
#define | PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
CVAL1CYC - Capture Value 1 Cycle Register
#define | PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
#define | PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
#define | PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
CVAL2 - Capture Value 2 Register
#define | PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
#define | PWM_CVAL2_CAPTVAL2_SHIFT (0U)
#define | PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
CVAL2CYC - Capture Value 2 Cycle Register
#define | PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
#define | PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
#define | PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
CVAL3 - Capture Value 3 Register
#define | PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
#define | PWM_CVAL3_CAPTVAL3_SHIFT (0U)
#define | PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
CVAL3CYC - Capture Value 3 Cycle Register
#define | PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
#define | PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
#define | PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
CVAL4 - Capture Value 4 Register
#define | PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
#define | PWM_CVAL4_CAPTVAL4_SHIFT (0U)
#define | PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
CVAL4CYC - Capture Value 4 Cycle Register
#define | PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
#define | PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
#define | PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
CVAL5 - Capture Value 5 Register
#define | PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
#define | PWM_CVAL5_CAPTVAL5_SHIFT (0U)
#define | PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
CVAL5CYC - Capture Value 5 Cycle Register
#define | PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
#define | PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
#define | PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
OUTEN - Output Enable Register
#define | PWM_OUTEN_PWMX_EN_MASK (0xFU)
#define | PWM_OUTEN_PWMX_EN_SHIFT (0U)
#define | PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
#define | PWM_OUTEN_PWMB_EN_MASK (0xF0U)
#define | PWM_OUTEN_PWMB_EN_SHIFT (4U)
#define | PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
#define | PWM_OUTEN_PWMA_EN_MASK (0xF00U)
#define | PWM_OUTEN_PWMA_EN_SHIFT (8U)
#define | PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
MASK - Mask Register
#define | PWM_MASK_MASKX_MASK (0xFU)
#define | PWM_MASK_MASKX_SHIFT (0U)
#define | PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
#define | PWM_MASK_MASKB_MASK (0xF0U)
#define | PWM_MASK_MASKB_SHIFT (4U)
#define | PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
#define | PWM_MASK_MASKA_MASK (0xF00U)
#define | PWM_MASK_MASKA_SHIFT (8U)
#define | PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
#define | PWM_MASK_UPDATE_MASK_MASK (0xF000U)
#define | PWM_MASK_UPDATE_MASK_SHIFT (12U)
#define | PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
SWCOUT - Software Controlled Output Register
#define | PWM_SWCOUT_SM0OUT45_MASK (0x1U)
#define | PWM_SWCOUT_SM0OUT45_SHIFT (0U)
#define | PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
#define | PWM_SWCOUT_SM0OUT23_MASK (0x2U)
#define | PWM_SWCOUT_SM0OUT23_SHIFT (1U)
#define | PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
#define | PWM_SWCOUT_SM1OUT45_MASK (0x4U)
#define | PWM_SWCOUT_SM1OUT45_SHIFT (2U)
#define | PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
#define | PWM_SWCOUT_SM1OUT23_MASK (0x8U)
#define | PWM_SWCOUT_SM1OUT23_SHIFT (3U)
#define | PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
#define | PWM_SWCOUT_SM2OUT45_MASK (0x10U)
#define | PWM_SWCOUT_SM2OUT45_SHIFT (4U)
#define | PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
#define | PWM_SWCOUT_SM2OUT23_MASK (0x20U)
#define | PWM_SWCOUT_SM2OUT23_SHIFT (5U)
#define | PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
#define | PWM_SWCOUT_SM3OUT45_MASK (0x40U)
#define | PWM_SWCOUT_SM3OUT45_SHIFT (6U)
#define | PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
#define | PWM_SWCOUT_SM3OUT23_MASK (0x80U)
#define | PWM_SWCOUT_SM3OUT23_SHIFT (7U)
#define | PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
DTSRCSEL - PWM Source Select Register
#define | PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
#define | PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
#define | PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
#define | PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
#define | PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
#define | PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
#define | PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
#define | PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
#define | PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
#define | PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
#define | PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
#define | PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
#define | PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
#define | PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
#define | PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
#define | PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
#define | PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
#define | PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
#define | PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
#define | PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
#define | PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
#define | PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
#define | PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
#define | PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
MCTRL - Master Control Register
#define | PWM_MCTRL_LDOK_MASK (0xFU)
#define | PWM_MCTRL_LDOK_SHIFT (0U)
#define | PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
#define | PWM_MCTRL_CLDOK_MASK (0xF0U)
#define | PWM_MCTRL_CLDOK_SHIFT (4U)
#define | PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
#define | PWM_MCTRL_RUN_MASK (0xF00U)
#define | PWM_MCTRL_RUN_SHIFT (8U)
#define | PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
#define | PWM_MCTRL_IPOL_MASK (0xF000U)
#define | PWM_MCTRL_IPOL_SHIFT (12U)
#define | PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
MCTRL2 - Master Control 2 Register
#define | PWM_MCTRL2_MONPLL_MASK (0x3U)
#define | PWM_MCTRL2_MONPLL_SHIFT (0U)
#define | PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
FCTRL - Fault Control Register
#define | PWM_FCTRL_FIE_MASK (0xFU)
#define | PWM_FCTRL_FIE_SHIFT (0U)
#define | PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
#define | PWM_FCTRL_FSAFE_MASK (0xF0U)
#define | PWM_FCTRL_FSAFE_SHIFT (4U)
#define | PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
#define | PWM_FCTRL_FAUTO_MASK (0xF00U)
#define | PWM_FCTRL_FAUTO_SHIFT (8U)
#define | PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
#define | PWM_FCTRL_FLVL_MASK (0xF000U)
#define | PWM_FCTRL_FLVL_SHIFT (12U)
#define | PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
FSTS - Fault Status Register
#define | PWM_FSTS_FFLAG_MASK (0xFU)
#define | PWM_FSTS_FFLAG_SHIFT (0U)
#define | PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
#define | PWM_FSTS_FFULL_MASK (0xF0U)
#define | PWM_FSTS_FFULL_SHIFT (4U)
#define | PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
#define | PWM_FSTS_FFPIN_MASK (0xF00U)
#define | PWM_FSTS_FFPIN_SHIFT (8U)
#define | PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
#define | PWM_FSTS_FHALF_MASK (0xF000U)
#define | PWM_FSTS_FHALF_SHIFT (12U)
#define | PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
FFILT - Fault Filter Register
#define | PWM_FFILT_FILT_PER_MASK (0xFFU)
#define | PWM_FFILT_FILT_PER_SHIFT (0U)
#define | PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
#define | PWM_FFILT_FILT_CNT_MASK (0x700U)
#define | PWM_FFILT_FILT_CNT_SHIFT (8U)
#define | PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
#define | PWM_FFILT_GSTR_MASK (0x8000U)
#define | PWM_FFILT_GSTR_SHIFT (15U)
#define | PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
FTST - Fault Test Register
#define | PWM_FTST_FTEST_MASK (0x1U)
#define | PWM_FTST_FTEST_SHIFT (0U)
#define | PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
FCTRL2 - Fault Control 2 Register
#define | PWM_FCTRL2_NOCOMB_MASK (0xFU)
#define | PWM_FCTRL2_NOCOMB_SHIFT (0U)
#define | PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
CTRL - Control Register 0
#define | PXP_CTRL_ENABLE_MASK (0x1U)
#define | PXP_CTRL_ENABLE_SHIFT (0U)
#define | PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
#define | PXP_CTRL_IRQ_ENABLE_MASK (0x2U)
#define | PXP_CTRL_IRQ_ENABLE_SHIFT (1U)
#define | PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
#define | PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)
#define | PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)
#define | PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
#define | PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define | PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define | PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
#define | PXP_CTRL_RSVD0_MASK (0xE0U)
#define | PXP_CTRL_RSVD0_SHIFT (5U)
#define | PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)
#define | PXP_CTRL_ROTATE_MASK (0x300U)
#define | PXP_CTRL_ROTATE_SHIFT (8U)
#define | PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
#define | PXP_CTRL_HFLIP_MASK (0x400U)
#define | PXP_CTRL_HFLIP_SHIFT (10U)
#define | PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
#define | PXP_CTRL_VFLIP_MASK (0x800U)
#define | PXP_CTRL_VFLIP_SHIFT (11U)
#define | PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
#define | PXP_CTRL_RSVD1_MASK (0x3FF000U)
#define | PXP_CTRL_RSVD1_SHIFT (12U)
#define | PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK)
#define | PXP_CTRL_ROT_POS_MASK (0x400000U)
#define | PXP_CTRL_ROT_POS_SHIFT (22U)
#define | PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
#define | PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)
#define | PXP_CTRL_BLOCK_SIZE_SHIFT (23U)
#define | PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
#define | PXP_CTRL_RSVD3_MASK (0xF000000U)
#define | PXP_CTRL_RSVD3_SHIFT (24U)
#define | PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK)
#define | PXP_CTRL_EN_REPEAT_MASK (0x10000000U)
#define | PXP_CTRL_EN_REPEAT_SHIFT (28U)
#define | PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
#define | PXP_CTRL_RSVD4_MASK (0x20000000U)
#define | PXP_CTRL_RSVD4_SHIFT (29U)
#define | PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK)
#define | PXP_CTRL_CLKGATE_MASK (0x40000000U)
#define | PXP_CTRL_CLKGATE_SHIFT (30U)
#define | PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
#define | PXP_CTRL_SFTRST_MASK (0x80000000U)
#define | PXP_CTRL_SFTRST_SHIFT (31U)
#define | PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
CTRL_SET - Control Register 0
#define | PXP_CTRL_SET_ENABLE_MASK (0x1U)
#define | PXP_CTRL_SET_ENABLE_SHIFT (0U)
#define | PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
#define | PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)
#define | PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)
#define | PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
#define | PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)
#define | PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)
#define | PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
#define | PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define | PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define | PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
#define | PXP_CTRL_SET_RSVD0_MASK (0xE0U)
#define | PXP_CTRL_SET_RSVD0_SHIFT (5U)
#define | PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)
#define | PXP_CTRL_SET_ROTATE_MASK (0x300U)
#define | PXP_CTRL_SET_ROTATE_SHIFT (8U)
#define | PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
#define | PXP_CTRL_SET_HFLIP_MASK (0x400U)
#define | PXP_CTRL_SET_HFLIP_SHIFT (10U)
#define | PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
#define | PXP_CTRL_SET_VFLIP_MASK (0x800U)
#define | PXP_CTRL_SET_VFLIP_SHIFT (11U)
#define | PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
#define | PXP_CTRL_SET_RSVD1_MASK (0x3FF000U)
#define | PXP_CTRL_SET_RSVD1_SHIFT (12U)
#define | PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK)
#define | PXP_CTRL_SET_ROT_POS_MASK (0x400000U)
#define | PXP_CTRL_SET_ROT_POS_SHIFT (22U)
#define | PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
#define | PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)
#define | PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)
#define | PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
#define | PXP_CTRL_SET_RSVD3_MASK (0xF000000U)
#define | PXP_CTRL_SET_RSVD3_SHIFT (24U)
#define | PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK)
#define | PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)
#define | PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)
#define | PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
#define | PXP_CTRL_SET_RSVD4_MASK (0x20000000U)
#define | PXP_CTRL_SET_RSVD4_SHIFT (29U)
#define | PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK)
#define | PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define | PXP_CTRL_SET_CLKGATE_SHIFT (30U)
#define | PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
#define | PXP_CTRL_SET_SFTRST_MASK (0x80000000U)
#define | PXP_CTRL_SET_SFTRST_SHIFT (31U)
#define | PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
CTRL_CLR - Control Register 0
#define | PXP_CTRL_CLR_ENABLE_MASK (0x1U)
#define | PXP_CTRL_CLR_ENABLE_SHIFT (0U)
#define | PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
#define | PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)
#define | PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)
#define | PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
#define | PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)
#define | PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)
#define | PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
#define | PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define | PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define | PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
#define | PXP_CTRL_CLR_RSVD0_MASK (0xE0U)
#define | PXP_CTRL_CLR_RSVD0_SHIFT (5U)
#define | PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)
#define | PXP_CTRL_CLR_ROTATE_MASK (0x300U)
#define | PXP_CTRL_CLR_ROTATE_SHIFT (8U)
#define | PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
#define | PXP_CTRL_CLR_HFLIP_MASK (0x400U)
#define | PXP_CTRL_CLR_HFLIP_SHIFT (10U)
#define | PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
#define | PXP_CTRL_CLR_VFLIP_MASK (0x800U)
#define | PXP_CTRL_CLR_VFLIP_SHIFT (11U)
#define | PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
#define | PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U)
#define | PXP_CTRL_CLR_RSVD1_SHIFT (12U)
#define | PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK)
#define | PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)
#define | PXP_CTRL_CLR_ROT_POS_SHIFT (22U)
#define | PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
#define | PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)
#define | PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)
#define | PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
#define | PXP_CTRL_CLR_RSVD3_MASK (0xF000000U)
#define | PXP_CTRL_CLR_RSVD3_SHIFT (24U)
#define | PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK)
#define | PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)
#define | PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)
#define | PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
#define | PXP_CTRL_CLR_RSVD4_MASK (0x20000000U)
#define | PXP_CTRL_CLR_RSVD4_SHIFT (29U)
#define | PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK)
#define | PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define | PXP_CTRL_CLR_CLKGATE_SHIFT (30U)
#define | PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
#define | PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define | PXP_CTRL_CLR_SFTRST_SHIFT (31U)
#define | PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
CTRL_TOG - Control Register 0
#define | PXP_CTRL_TOG_ENABLE_MASK (0x1U)
#define | PXP_CTRL_TOG_ENABLE_SHIFT (0U)
#define | PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
#define | PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)
#define | PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)
#define | PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
#define | PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)
#define | PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)
#define | PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
#define | PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define | PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define | PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
#define | PXP_CTRL_TOG_RSVD0_MASK (0xE0U)
#define | PXP_CTRL_TOG_RSVD0_SHIFT (5U)
#define | PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)
#define | PXP_CTRL_TOG_ROTATE_MASK (0x300U)
#define | PXP_CTRL_TOG_ROTATE_SHIFT (8U)
#define | PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
#define | PXP_CTRL_TOG_HFLIP_MASK (0x400U)
#define | PXP_CTRL_TOG_HFLIP_SHIFT (10U)
#define | PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
#define | PXP_CTRL_TOG_VFLIP_MASK (0x800U)
#define | PXP_CTRL_TOG_VFLIP_SHIFT (11U)
#define | PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
#define | PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U)
#define | PXP_CTRL_TOG_RSVD1_SHIFT (12U)
#define | PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK)
#define | PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)
#define | PXP_CTRL_TOG_ROT_POS_SHIFT (22U)
#define | PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
#define | PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)
#define | PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)
#define | PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
#define | PXP_CTRL_TOG_RSVD3_MASK (0xF000000U)
#define | PXP_CTRL_TOG_RSVD3_SHIFT (24U)
#define | PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK)
#define | PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)
#define | PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)
#define | PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
#define | PXP_CTRL_TOG_RSVD4_MASK (0x20000000U)
#define | PXP_CTRL_TOG_RSVD4_SHIFT (29U)
#define | PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK)
#define | PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define | PXP_CTRL_TOG_CLKGATE_SHIFT (30U)
#define | PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
#define | PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define | PXP_CTRL_TOG_SFTRST_SHIFT (31U)
#define | PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
STAT - Status Register
#define | PXP_STAT_IRQ_MASK (0x1U)
#define | PXP_STAT_IRQ_SHIFT (0U)
#define | PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
#define | PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)
#define | PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)
#define | PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
#define | PXP_STAT_AXI_READ_ERROR_MASK (0x4U)
#define | PXP_STAT_AXI_READ_ERROR_SHIFT (2U)
#define | PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
#define | PXP_STAT_NEXT_IRQ_MASK (0x8U)
#define | PXP_STAT_NEXT_IRQ_SHIFT (3U)
#define | PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
#define | PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)
#define | PXP_STAT_AXI_ERROR_ID_SHIFT (4U)
#define | PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
#define | PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define | PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
#define | PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define | PXP_STAT_RSVD2_MASK (0xFE00U)
#define | PXP_STAT_RSVD2_SHIFT (9U)
#define | PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK)
#define | PXP_STAT_BLOCKY_MASK (0xFF0000U)
#define | PXP_STAT_BLOCKY_SHIFT (16U)
#define | PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
#define | PXP_STAT_BLOCKX_MASK (0xFF000000U)
#define | PXP_STAT_BLOCKX_SHIFT (24U)
#define | PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
STAT_SET - Status Register
#define | PXP_STAT_SET_IRQ_MASK (0x1U)
#define | PXP_STAT_SET_IRQ_SHIFT (0U)
#define | PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
#define | PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)
#define | PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)
#define | PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
#define | PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)
#define | PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)
#define | PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
#define | PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)
#define | PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)
#define | PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
#define | PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)
#define | PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)
#define | PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
#define | PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define | PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
#define | PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define | PXP_STAT_SET_RSVD2_MASK (0xFE00U)
#define | PXP_STAT_SET_RSVD2_SHIFT (9U)
#define | PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK)
#define | PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)
#define | PXP_STAT_SET_BLOCKY_SHIFT (16U)
#define | PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
#define | PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)
#define | PXP_STAT_SET_BLOCKX_SHIFT (24U)
#define | PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
STAT_CLR - Status Register
#define | PXP_STAT_CLR_IRQ_MASK (0x1U)
#define | PXP_STAT_CLR_IRQ_SHIFT (0U)
#define | PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
#define | PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)
#define | PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)
#define | PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
#define | PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)
#define | PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)
#define | PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
#define | PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)
#define | PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)
#define | PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
#define | PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)
#define | PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)
#define | PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
#define | PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define | PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
#define | PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define | PXP_STAT_CLR_RSVD2_MASK (0xFE00U)
#define | PXP_STAT_CLR_RSVD2_SHIFT (9U)
#define | PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK)
#define | PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)
#define | PXP_STAT_CLR_BLOCKY_SHIFT (16U)
#define | PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
#define | PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)
#define | PXP_STAT_CLR_BLOCKX_SHIFT (24U)
#define | PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
STAT_TOG - Status Register
#define | PXP_STAT_TOG_IRQ_MASK (0x1U)
#define | PXP_STAT_TOG_IRQ_SHIFT (0U)
#define | PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
#define | PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)
#define | PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)
#define | PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
#define | PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)
#define | PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)
#define | PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
#define | PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)
#define | PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)
#define | PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
#define | PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)
#define | PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)
#define | PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
#define | PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define | PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
#define | PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define | PXP_STAT_TOG_RSVD2_MASK (0xFE00U)
#define | PXP_STAT_TOG_RSVD2_SHIFT (9U)
#define | PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK)
#define | PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)
#define | PXP_STAT_TOG_BLOCKY_SHIFT (16U)
#define | PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
#define | PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)
#define | PXP_STAT_TOG_BLOCKX_SHIFT (24U)
#define | PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
OUT_CTRL - Output Buffer Control Register
#define | PXP_OUT_CTRL_FORMAT_MASK (0x1FU)
#define | PXP_OUT_CTRL_FORMAT_SHIFT (0U)
#define | PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
#define | PXP_OUT_CTRL_RSVD0_MASK (0xE0U)
#define | PXP_OUT_CTRL_RSVD0_SHIFT (5U)
#define | PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)
#define | PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)
#define | PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)
#define | PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
#define | PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U)
#define | PXP_OUT_CTRL_RSVD1_SHIFT (10U)
#define | PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK)
#define | PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)
#define | PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)
#define | PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
#define | PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)
#define | PXP_OUT_CTRL_ALPHA_SHIFT (24U)
#define | PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
OUT_CTRL_SET - Output Buffer Control Register
#define | PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)
#define | PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)
#define | PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
#define | PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U)
#define | PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U)
#define | PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)
#define | PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)
#define | PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
#define | PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
#define | PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U)
#define | PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U)
#define | PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK)
#define | PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)
#define | PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)
#define | PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
#define | PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)
#define | PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)
#define | PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
OUT_CTRL_CLR - Output Buffer Control Register
#define | PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)
#define | PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)
#define | PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
#define | PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U)
#define | PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U)
#define | PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)
#define | PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)
#define | PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
#define | PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
#define | PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U)
#define | PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U)
#define | PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK)
#define | PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)
#define | PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)
#define | PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
#define | PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)
#define | PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)
#define | PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
OUT_CTRL_TOG - Output Buffer Control Register
#define | PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)
#define | PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)
#define | PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
#define | PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U)
#define | PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U)
#define | PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)
#define | PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)
#define | PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
#define | PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
#define | PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U)
#define | PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U)
#define | PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK)
#define | PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)
#define | PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)
#define | PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
#define | PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)
#define | PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)
#define | PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
OUT_BUF - Output Frame Buffer Pointer
#define | PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)
#define | PXP_OUT_BUF_ADDR_SHIFT (0U)
#define | PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
OUT_BUF2 - Output Frame Buffer Pointer #2
#define | PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)
#define | PXP_OUT_BUF2_ADDR_SHIFT (0U)
#define | PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
OUT_PITCH - Output Buffer Pitch
#define | PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)
#define | PXP_OUT_PITCH_PITCH_SHIFT (0U)
#define | PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
#define | PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U)
#define | PXP_OUT_PITCH_RSVD_SHIFT (16U)
#define | PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK)
OUT_LRC - Output Surface Lower Right Coordinate
#define | PXP_OUT_LRC_Y_MASK (0x3FFFU)
#define | PXP_OUT_LRC_Y_SHIFT (0U)
#define | PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
#define | PXP_OUT_LRC_RSVD0_MASK (0xC000U)
#define | PXP_OUT_LRC_RSVD0_SHIFT (14U)
#define | PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK)
#define | PXP_OUT_LRC_X_MASK (0x3FFF0000U)
#define | PXP_OUT_LRC_X_SHIFT (16U)
#define | PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
#define | PXP_OUT_LRC_RSVD1_MASK (0xC0000000U)
#define | PXP_OUT_LRC_RSVD1_SHIFT (30U)
#define | PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK)
OUT_PS_ULC - Processed Surface Upper Left Coordinate
#define | PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)
#define | PXP_OUT_PS_ULC_Y_SHIFT (0U)
#define | PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
#define | PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U)
#define | PXP_OUT_PS_ULC_RSVD0_SHIFT (14U)
#define | PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK)
#define | PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)
#define | PXP_OUT_PS_ULC_X_SHIFT (16U)
#define | PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
#define | PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U)
#define | PXP_OUT_PS_ULC_RSVD1_SHIFT (30U)
#define | PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK)
OUT_PS_LRC - Processed Surface Lower Right Coordinate
#define | PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)
#define | PXP_OUT_PS_LRC_Y_SHIFT (0U)
#define | PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
#define | PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U)
#define | PXP_OUT_PS_LRC_RSVD0_SHIFT (14U)
#define | PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK)
#define | PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)
#define | PXP_OUT_PS_LRC_X_SHIFT (16U)
#define | PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
#define | PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U)
#define | PXP_OUT_PS_LRC_RSVD1_SHIFT (30U)
#define | PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK)
OUT_AS_ULC - Alpha Surface Upper Left Coordinate
#define | PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)
#define | PXP_OUT_AS_ULC_Y_SHIFT (0U)
#define | PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
#define | PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U)
#define | PXP_OUT_AS_ULC_RSVD0_SHIFT (14U)
#define | PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK)
#define | PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)
#define | PXP_OUT_AS_ULC_X_SHIFT (16U)
#define | PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
#define | PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U)
#define | PXP_OUT_AS_ULC_RSVD1_SHIFT (30U)
#define | PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK)
OUT_AS_LRC - Alpha Surface Lower Right Coordinate
#define | PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)
#define | PXP_OUT_AS_LRC_Y_SHIFT (0U)
#define | PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
#define | PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U)
#define | PXP_OUT_AS_LRC_RSVD0_SHIFT (14U)
#define | PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK)
#define | PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)
#define | PXP_OUT_AS_LRC_X_SHIFT (16U)
#define | PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
#define | PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U)
#define | PXP_OUT_AS_LRC_RSVD1_SHIFT (30U)
#define | PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK)
PS_CTRL - Processed Surface (PS) Control Register
#define | PXP_PS_CTRL_FORMAT_MASK (0x1FU)
#define | PXP_PS_CTRL_FORMAT_SHIFT (0U)
#define | PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
#define | PXP_PS_CTRL_WB_SWAP_MASK (0x20U)
#define | PXP_PS_CTRL_WB_SWAP_SHIFT (5U)
#define | PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
#define | PXP_PS_CTRL_RSVD0_MASK (0xC0U)
#define | PXP_PS_CTRL_RSVD0_SHIFT (6U)
#define | PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)
#define | PXP_PS_CTRL_DECY_MASK (0x300U)
#define | PXP_PS_CTRL_DECY_SHIFT (8U)
#define | PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
#define | PXP_PS_CTRL_DECX_MASK (0xC00U)
#define | PXP_PS_CTRL_DECX_SHIFT (10U)
#define | PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
#define | PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U)
#define | PXP_PS_CTRL_RSVD1_SHIFT (12U)
#define | PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK)
PS_CTRL_SET - Processed Surface (PS) Control Register
#define | PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU)
#define | PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)
#define | PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
#define | PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U)
#define | PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U)
#define | PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
#define | PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U)
#define | PXP_PS_CTRL_SET_RSVD0_SHIFT (6U)
#define | PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)
#define | PXP_PS_CTRL_SET_DECY_MASK (0x300U)
#define | PXP_PS_CTRL_SET_DECY_SHIFT (8U)
#define | PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
#define | PXP_PS_CTRL_SET_DECX_MASK (0xC00U)
#define | PXP_PS_CTRL_SET_DECX_SHIFT (10U)
#define | PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
#define | PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U)
#define | PXP_PS_CTRL_SET_RSVD1_SHIFT (12U)
#define | PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK)
PS_CTRL_CLR - Processed Surface (PS) Control Register
#define | PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU)
#define | PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)
#define | PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
#define | PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U)
#define | PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U)
#define | PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
#define | PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U)
#define | PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U)
#define | PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)
#define | PXP_PS_CTRL_CLR_DECY_MASK (0x300U)
#define | PXP_PS_CTRL_CLR_DECY_SHIFT (8U)
#define | PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
#define | PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)
#define | PXP_PS_CTRL_CLR_DECX_SHIFT (10U)
#define | PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
#define | PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U)
#define | PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U)
#define | PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK)
PS_CTRL_TOG - Processed Surface (PS) Control Register
#define | PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU)
#define | PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)
#define | PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
#define | PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U)
#define | PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U)
#define | PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
#define | PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U)
#define | PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U)
#define | PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)
#define | PXP_PS_CTRL_TOG_DECY_MASK (0x300U)
#define | PXP_PS_CTRL_TOG_DECY_SHIFT (8U)
#define | PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
#define | PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)
#define | PXP_PS_CTRL_TOG_DECX_SHIFT (10U)
#define | PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
#define | PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U)
#define | PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U)
#define | PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK)
PS_BUF - PS Input Buffer Address
#define | PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)
#define | PXP_PS_BUF_ADDR_SHIFT (0U)
#define | PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address
#define | PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)
#define | PXP_PS_UBUF_ADDR_SHIFT (0U)
#define | PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
PS_VBUF - PS V/Cr Input Buffer Address
#define | PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)
#define | PXP_PS_VBUF_ADDR_SHIFT (0U)
#define | PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
PS_PITCH - Processed Surface Pitch
#define | PXP_PS_PITCH_PITCH_MASK (0xFFFFU)
#define | PXP_PS_PITCH_PITCH_SHIFT (0U)
#define | PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
#define | PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U)
#define | PXP_PS_PITCH_RSVD_SHIFT (16U)
#define | PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK)
PS_BACKGROUND - PS Background Color
#define | PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)
#define | PXP_PS_BACKGROUND_COLOR_SHIFT (0U)
#define | PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
#define | PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U)
#define | PXP_PS_BACKGROUND_RSVD_SHIFT (24U)
#define | PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK)
PS_SCALE - PS Scale Factor Register
#define | PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)
#define | PXP_PS_SCALE_XSCALE_SHIFT (0U)
#define | PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
#define | PXP_PS_SCALE_RSVD1_MASK (0x8000U)
#define | PXP_PS_SCALE_RSVD1_SHIFT (15U)
#define | PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK)
#define | PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)
#define | PXP_PS_SCALE_YSCALE_SHIFT (16U)
#define | PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
#define | PXP_PS_SCALE_RSVD2_MASK (0x80000000U)
#define | PXP_PS_SCALE_RSVD2_SHIFT (31U)
#define | PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK)
PS_OFFSET - PS Scale Offset Register
#define | PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)
#define | PXP_PS_OFFSET_XOFFSET_SHIFT (0U)
#define | PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
#define | PXP_PS_OFFSET_RSVD1_MASK (0xF000U)
#define | PXP_PS_OFFSET_RSVD1_SHIFT (12U)
#define | PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK)
#define | PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)
#define | PXP_PS_OFFSET_YOFFSET_SHIFT (16U)
#define | PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
#define | PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U)
#define | PXP_PS_OFFSET_RSVD2_SHIFT (28U)
#define | PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK)
PS_CLRKEYLOW - PS Color Key Low
#define | PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
#define | PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)
#define | PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
#define | PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
#define | PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U)
#define | PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK)
PS_CLRKEYHIGH - PS Color Key High
#define | PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
#define | PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)
#define | PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
#define | PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
#define | PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U)
#define | PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK)
AS_CTRL - Alpha Surface Control
#define | PXP_AS_CTRL_RSVD0_MASK (0x1U)
#define | PXP_AS_CTRL_RSVD0_SHIFT (0U)
#define | PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)
#define | PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
#define | PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
#define | PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
#define | PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
#define | PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
#define | PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
#define | PXP_AS_CTRL_FORMAT_MASK (0xF0U)
#define | PXP_AS_CTRL_FORMAT_SHIFT (4U)
#define | PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
#define | PXP_AS_CTRL_ALPHA_MASK (0xFF00U)
#define | PXP_AS_CTRL_ALPHA_SHIFT (8U)
#define | PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
#define | PXP_AS_CTRL_ROP_MASK (0xF0000U)
#define | PXP_AS_CTRL_ROP_SHIFT (16U)
#define | PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
#define | PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
#define | PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
#define | PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
#define | PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U)
#define | PXP_AS_CTRL_RSVD1_SHIFT (21U)
#define | PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK)
AS_BUF - Alpha Surface Buffer Pointer
#define | PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
#define | PXP_AS_BUF_ADDR_SHIFT (0U)
#define | PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
AS_PITCH - Alpha Surface Pitch
#define | PXP_AS_PITCH_PITCH_MASK (0xFFFFU)
#define | PXP_AS_PITCH_PITCH_SHIFT (0U)
#define | PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
#define | PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U)
#define | PXP_AS_PITCH_RSVD_SHIFT (16U)
#define | PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK)
AS_CLRKEYLOW - Overlay Color Key Low
#define | PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
#define | PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
#define | PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
#define | PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
#define | PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U)
#define | PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK)
AS_CLRKEYHIGH - Overlay Color Key High
#define | PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
#define | PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
#define | PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
#define | PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
#define | PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)
#define | PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK)
CSC1_COEF0 - Color Space Conversion Coefficient Register 0
#define | PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)
#define | PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)
#define | PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
#define | PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)
#define | PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)
#define | PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
#define | PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)
#define | PXP_CSC1_COEF0_C0_SHIFT (18U)
#define | PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
#define | PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U)
#define | PXP_CSC1_COEF0_RSVD1_SHIFT (29U)
#define | PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK)
#define | PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)
#define | PXP_CSC1_COEF0_BYPASS_SHIFT (30U)
#define | PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
#define | PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)
#define | PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)
#define | PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
CSC1_COEF1 - Color Space Conversion Coefficient Register 1
#define | PXP_CSC1_COEF1_C4_MASK (0x7FFU)
#define | PXP_CSC1_COEF1_C4_SHIFT (0U)
#define | PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
#define | PXP_CSC1_COEF1_RSVD0_MASK (0xF800U)
#define | PXP_CSC1_COEF1_RSVD0_SHIFT (11U)
#define | PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK)
#define | PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)
#define | PXP_CSC1_COEF1_C1_SHIFT (16U)
#define | PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
#define | PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U)
#define | PXP_CSC1_COEF1_RSVD1_SHIFT (27U)
#define | PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK)
CSC1_COEF2 - Color Space Conversion Coefficient Register 2
#define | PXP_CSC1_COEF2_C3_MASK (0x7FFU)
#define | PXP_CSC1_COEF2_C3_SHIFT (0U)
#define | PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
#define | PXP_CSC1_COEF2_RSVD0_MASK (0xF800U)
#define | PXP_CSC1_COEF2_RSVD0_SHIFT (11U)
#define | PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK)
#define | PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)
#define | PXP_CSC1_COEF2_C2_SHIFT (16U)
#define | PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
#define | PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U)
#define | PXP_CSC1_COEF2_RSVD1_SHIFT (27U)
#define | PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK)
POWER - PXP Power Control Register
#define | PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)
#define | PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)
#define | PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
#define | PXP_POWER_CTRL_MASK (0xFFFFF000U)
#define | PXP_POWER_CTRL_SHIFT (12U)
#define | PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)
NEXT - Next Frame Pointer
#define | PXP_NEXT_ENABLED_MASK (0x1U)
#define | PXP_NEXT_ENABLED_SHIFT (0U)
#define | PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
#define | PXP_NEXT_RSVD_MASK (0x2U)
#define | PXP_NEXT_RSVD_SHIFT (1U)
#define | PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK)
#define | PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)
#define | PXP_NEXT_POINTER_SHIFT (2U)
#define | PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register.
#define | PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U)
#define | PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U)
#define | PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
#define | PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
#define | PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)
#define | PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
#define | PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)
#define | PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
#define | PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
#define | PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
#define | PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)
#define | PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
#define | PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)
#define | PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
#define | PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
ROMPATCHD - ROMC Data Registers
#define | ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)
#define | ROMC_ROMPATCHD_DATAX_SHIFT (0U)
#define | ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
ROMPATCHCNTL - ROMC Control Register
#define | ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)
#define | ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)
#define | ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
#define | ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)
#define | ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)
#define | ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
ROMPATCHENL - ROMC Enable Register Low
#define | ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)
#define | ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)
#define | ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
ROMPATCHA - ROMC Address Registers
#define | ROMC_ROMPATCHA_THUMBX_MASK (0x1U)
#define | ROMC_ROMPATCHA_THUMBX_SHIFT (0U)
#define | ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
#define | ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)
#define | ROMC_ROMPATCHA_ADDRX_SHIFT (1U)
#define | ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
ROMPATCHSR - ROMC Status Register
#define | ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)
#define | ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)
#define | ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
#define | ROMC_ROMPATCHSR_SW_MASK (0x20000U)
#define | ROMC_ROMPATCHSR_SW_SHIFT (17U)
#define | ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
CS - Watchdog Control and Status Register
#define | RTWDOG_CS_STOP_MASK (0x1U)
#define | RTWDOG_CS_STOP_SHIFT (0U)
#define | RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
#define | RTWDOG_CS_WAIT_MASK (0x2U)
#define | RTWDOG_CS_WAIT_SHIFT (1U)
#define | RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
#define | RTWDOG_CS_DBG_MASK (0x4U)
#define | RTWDOG_CS_DBG_SHIFT (2U)
#define | RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
#define | RTWDOG_CS_TST_MASK (0x18U)
#define | RTWDOG_CS_TST_SHIFT (3U)
#define | RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
#define | RTWDOG_CS_UPDATE_MASK (0x20U)
#define | RTWDOG_CS_UPDATE_SHIFT (5U)
#define | RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
#define | RTWDOG_CS_INT_MASK (0x40U)
#define | RTWDOG_CS_INT_SHIFT (6U)
#define | RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
#define | RTWDOG_CS_EN_MASK (0x80U)
#define | RTWDOG_CS_EN_SHIFT (7U)
#define | RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
#define | RTWDOG_CS_CLK_MASK (0x300U)
#define | RTWDOG_CS_CLK_SHIFT (8U)
#define | RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
#define | RTWDOG_CS_RCS_MASK (0x400U)
#define | RTWDOG_CS_RCS_SHIFT (10U)
#define | RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
#define | RTWDOG_CS_ULK_MASK (0x800U)
#define | RTWDOG_CS_ULK_SHIFT (11U)
#define | RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
#define | RTWDOG_CS_PRES_MASK (0x1000U)
#define | RTWDOG_CS_PRES_SHIFT (12U)
#define | RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
#define | RTWDOG_CS_CMD32EN_MASK (0x2000U)
#define | RTWDOG_CS_CMD32EN_SHIFT (13U)
#define | RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
#define | RTWDOG_CS_FLG_MASK (0x4000U)
#define | RTWDOG_CS_FLG_SHIFT (14U)
#define | RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
#define | RTWDOG_CS_WIN_MASK (0x8000U)
#define | RTWDOG_CS_WIN_SHIFT (15U)
#define | RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
CNT - Watchdog Counter Register
#define | RTWDOG_CNT_CNTLOW_MASK (0xFFU)
#define | RTWDOG_CNT_CNTLOW_SHIFT (0U)
#define | RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
#define | RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
#define | RTWDOG_CNT_CNTHIGH_SHIFT (8U)
#define | RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
TOVAL - Watchdog Timeout Value Register
#define | RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
#define | RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
#define | RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
#define | RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
#define | RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
#define | RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
WIN - Watchdog Window Register
#define | RTWDOG_WIN_WINLOW_MASK (0xFFU)
#define | RTWDOG_WIN_WINLOW_SHIFT (0U)
#define | RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
#define | RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
#define | RTWDOG_WIN_WINHIGH_SHIFT (8U)
#define | RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
MCR - Module Control Register
#define | SEMC_MCR_SWRST_MASK (0x1U)
#define | SEMC_MCR_SWRST_SHIFT (0U)
#define | SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
#define | SEMC_MCR_MDIS_MASK (0x2U)
#define | SEMC_MCR_MDIS_SHIFT (1U)
#define | SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
#define | SEMC_MCR_DQSMD_MASK (0x4U)
#define | SEMC_MCR_DQSMD_SHIFT (2U)
#define | SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
#define | SEMC_MCR_WPOL0_MASK (0x40U)
#define | SEMC_MCR_WPOL0_SHIFT (6U)
#define | SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
#define | SEMC_MCR_WPOL1_MASK (0x80U)
#define | SEMC_MCR_WPOL1_SHIFT (7U)
#define | SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
#define | SEMC_MCR_DQSSEL_MASK (0x400U)
#define | SEMC_MCR_DQSSEL_SHIFT (10U)
#define | SEMC_MCR_DQSSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSSEL_SHIFT)) & SEMC_MCR_DQSSEL_MASK)
#define | SEMC_MCR_DLLSEL_MASK (0x800U)
#define | SEMC_MCR_DLLSEL_SHIFT (11U)
#define | SEMC_MCR_DLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DLLSEL_SHIFT)) & SEMC_MCR_DLLSEL_MASK)
#define | SEMC_MCR_CTO_MASK (0xFF0000U)
#define | SEMC_MCR_CTO_SHIFT (16U)
#define | SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
#define | SEMC_MCR_BTO_MASK (0x1F000000U)
#define | SEMC_MCR_BTO_SHIFT (24U)
#define | SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
IOCR - IO Mux Control Register
#define | SEMC_IOCR_MUX_A8_MASK (0x7U)
#define | SEMC_IOCR_MUX_A8_SHIFT (0U)
#define | SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
#define | SEMC_IOCR_MUX_CSX0_MASK (0x38U)
#define | SEMC_IOCR_MUX_CSX0_SHIFT (3U)
#define | SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
#define | SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
#define | SEMC_IOCR_MUX_CSX1_SHIFT (6U)
#define | SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
#define | SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
#define | SEMC_IOCR_MUX_CSX2_SHIFT (9U)
#define | SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
#define | SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
#define | SEMC_IOCR_MUX_CSX3_SHIFT (12U)
#define | SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
#define | SEMC_IOCR_MUX_RDY_MASK (0x38000U)
#define | SEMC_IOCR_MUX_RDY_SHIFT (15U)
#define | SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
#define | SEMC_IOCR_MUX_CLKX0_MASK (0x1000000U)
#define | SEMC_IOCR_MUX_CLKX0_SHIFT (24U)
#define | SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
#define | SEMC_IOCR_MUX_CLKX1_MASK (0x2000000U)
#define | SEMC_IOCR_MUX_CLKX1_SHIFT (25U)
#define | SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)
BMCR0 - Master Bus (AXI) Control Register 0
#define | SEMC_BMCR0_WQOS_MASK (0xFU)
#define | SEMC_BMCR0_WQOS_SHIFT (0U)
#define | SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
#define | SEMC_BMCR0_WAGE_MASK (0xF0U)
#define | SEMC_BMCR0_WAGE_SHIFT (4U)
#define | SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
#define | SEMC_BMCR0_WSH_MASK (0xFF00U)
#define | SEMC_BMCR0_WSH_SHIFT (8U)
#define | SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
#define | SEMC_BMCR0_WRWS_MASK (0xFF0000U)
#define | SEMC_BMCR0_WRWS_SHIFT (16U)
#define | SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
BMCR1 - Master Bus (AXI) Control Register 1
#define | SEMC_BMCR1_WQOS_MASK (0xFU)
#define | SEMC_BMCR1_WQOS_SHIFT (0U)
#define | SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
#define | SEMC_BMCR1_WAGE_MASK (0xF0U)
#define | SEMC_BMCR1_WAGE_SHIFT (4U)
#define | SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
#define | SEMC_BMCR1_WPH_MASK (0xFF00U)
#define | SEMC_BMCR1_WPH_SHIFT (8U)
#define | SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
#define | SEMC_BMCR1_WRWS_MASK (0xFF0000U)
#define | SEMC_BMCR1_WRWS_SHIFT (16U)
#define | SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
#define | SEMC_BMCR1_WBR_MASK (0xFF000000U)
#define | SEMC_BMCR1_WBR_SHIFT (24U)
#define | SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device)
#define | SEMC_BR_VLD_MASK (0x1U)
#define | SEMC_BR_VLD_SHIFT (0U)
#define | SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
#define | SEMC_BR_MS_MASK (0x3EU)
#define | SEMC_BR_MS_SHIFT (1U)
#define | SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
#define | SEMC_BR_BA_MASK (0xFFFFF000U)
#define | SEMC_BR_BA_SHIFT (12U)
#define | SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
DLLCR - DLL Control Register
#define | SEMC_DLLCR_DLLEN_MASK (0x1U)
#define | SEMC_DLLCR_DLLEN_SHIFT (0U)
#define | SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
#define | SEMC_DLLCR_DLLRESET_MASK (0x2U)
#define | SEMC_DLLCR_DLLRESET_SHIFT (1U)
#define | SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
#define | SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U)
#define | SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U)
#define | SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
#define | SEMC_DLLCR_OVRDEN_MASK (0x100U)
#define | SEMC_DLLCR_OVRDEN_SHIFT (8U)
#define | SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
#define | SEMC_DLLCR_OVRDVAL_MASK (0x7E00U)
#define | SEMC_DLLCR_OVRDVAL_SHIFT (9U)
#define | SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)
INTR - Interrupt Enable Register
#define | SEMC_INTR_IPCMDDONE_MASK (0x1U)
#define | SEMC_INTR_IPCMDDONE_SHIFT (0U)
#define | SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
#define | SEMC_INTR_IPCMDERR_MASK (0x2U)
#define | SEMC_INTR_IPCMDERR_SHIFT (1U)
#define | SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
#define | SEMC_INTR_AXICMDERR_MASK (0x4U)
#define | SEMC_INTR_AXICMDERR_SHIFT (2U)
#define | SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
#define | SEMC_INTR_AXIBUSERR_MASK (0x8U)
#define | SEMC_INTR_AXIBUSERR_SHIFT (3U)
#define | SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
#define | SEMC_INTR_NDPAGEEND_MASK (0x10U)
#define | SEMC_INTR_NDPAGEEND_SHIFT (4U)
#define | SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
#define | SEMC_INTR_NDNOPEND_MASK (0x20U)
#define | SEMC_INTR_NDNOPEND_SHIFT (5U)
#define | SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
SDRAMCR0 - SDRAM control register 0
#define | SEMC_SDRAMCR0_PS_MASK (0x1U)
#define | SEMC_SDRAMCR0_PS_SHIFT (0U)
#define | SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
#define | SEMC_SDRAMCR0_BL_MASK (0x70U)
#define | SEMC_SDRAMCR0_BL_SHIFT (4U)
#define | SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
#define | SEMC_SDRAMCR0_COL8_MASK (0x80U)
#define | SEMC_SDRAMCR0_COL8_SHIFT (7U)
#define | SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
#define | SEMC_SDRAMCR0_COL_MASK (0x300U)
#define | SEMC_SDRAMCR0_COL_SHIFT (8U)
#define | SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
#define | SEMC_SDRAMCR0_CL_MASK (0xC00U)
#define | SEMC_SDRAMCR0_CL_SHIFT (10U)
#define | SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
#define | SEMC_SDRAMCR0_BANK2_MASK (0x4000U)
#define | SEMC_SDRAMCR0_BANK2_SHIFT (14U)
#define | SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)
SDRAMCR1 - SDRAM control register 1
#define | SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
#define | SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
#define | SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
#define | SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
#define | SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
#define | SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
#define | SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
#define | SEMC_SDRAMCR1_RFRC_SHIFT (8U)
#define | SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
#define | SEMC_SDRAMCR1_WRC_MASK (0xE000U)
#define | SEMC_SDRAMCR1_WRC_SHIFT (13U)
#define | SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
#define | SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
#define | SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
#define | SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
#define | SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
#define | SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
#define | SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
SDRAMCR2 - SDRAM control register 2
#define | SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
#define | SEMC_SDRAMCR2_SRRC_SHIFT (0U)
#define | SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
#define | SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
#define | SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
#define | SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
#define | SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
#define | SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
#define | SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
#define | SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
#define | SEMC_SDRAMCR2_ITO_SHIFT (24U)
#define | SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
SDRAMCR3 - SDRAM control register 3
#define | SEMC_SDRAMCR3_REN_MASK (0x1U)
#define | SEMC_SDRAMCR3_REN_SHIFT (0U)
#define | SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
#define | SEMC_SDRAMCR3_REBL_MASK (0xEU)
#define | SEMC_SDRAMCR3_REBL_SHIFT (1U)
#define | SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
#define | SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
#define | SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
#define | SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
#define | SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
#define | SEMC_SDRAMCR3_RT_SHIFT (16U)
#define | SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
#define | SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
#define | SEMC_SDRAMCR3_UT_SHIFT (24U)
#define | SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
NANDCR0 - NAND control register 0
#define | SEMC_NANDCR0_PS_MASK (0x1U)
#define | SEMC_NANDCR0_PS_SHIFT (0U)
#define | SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
#define | SEMC_NANDCR0_SYNCEN_MASK (0x2U)
#define | SEMC_NANDCR0_SYNCEN_SHIFT (1U)
#define | SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
#define | SEMC_NANDCR0_BL_MASK (0x70U)
#define | SEMC_NANDCR0_BL_SHIFT (4U)
#define | SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
#define | SEMC_NANDCR0_EDO_MASK (0x80U)
#define | SEMC_NANDCR0_EDO_SHIFT (7U)
#define | SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
#define | SEMC_NANDCR0_COL_MASK (0x700U)
#define | SEMC_NANDCR0_COL_SHIFT (8U)
#define | SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
NANDCR1 - NAND control register 1
#define | SEMC_NANDCR1_CES_MASK (0xFU)
#define | SEMC_NANDCR1_CES_SHIFT (0U)
#define | SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
#define | SEMC_NANDCR1_CEH_MASK (0xF0U)
#define | SEMC_NANDCR1_CEH_SHIFT (4U)
#define | SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
#define | SEMC_NANDCR1_WEL_MASK (0xF00U)
#define | SEMC_NANDCR1_WEL_SHIFT (8U)
#define | SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
#define | SEMC_NANDCR1_WEH_MASK (0xF000U)
#define | SEMC_NANDCR1_WEH_SHIFT (12U)
#define | SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
#define | SEMC_NANDCR1_REL_MASK (0xF0000U)
#define | SEMC_NANDCR1_REL_SHIFT (16U)
#define | SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
#define | SEMC_NANDCR1_REH_MASK (0xF00000U)
#define | SEMC_NANDCR1_REH_SHIFT (20U)
#define | SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
#define | SEMC_NANDCR1_TA_MASK (0xF000000U)
#define | SEMC_NANDCR1_TA_SHIFT (24U)
#define | SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
#define | SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
#define | SEMC_NANDCR1_CEITV_SHIFT (28U)
#define | SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
NANDCR2 - NAND control register 2
#define | SEMC_NANDCR2_TWHR_MASK (0x3FU)
#define | SEMC_NANDCR2_TWHR_SHIFT (0U)
#define | SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
#define | SEMC_NANDCR2_TRHW_MASK (0xFC0U)
#define | SEMC_NANDCR2_TRHW_SHIFT (6U)
#define | SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
#define | SEMC_NANDCR2_TADL_MASK (0x3F000U)
#define | SEMC_NANDCR2_TADL_SHIFT (12U)
#define | SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
#define | SEMC_NANDCR2_TRR_MASK (0xFC0000U)
#define | SEMC_NANDCR2_TRR_SHIFT (18U)
#define | SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
#define | SEMC_NANDCR2_TWB_MASK (0x3F000000U)
#define | SEMC_NANDCR2_TWB_SHIFT (24U)
#define | SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
NANDCR3 - NAND control register 3
#define | SEMC_NANDCR3_NDOPT1_MASK (0x1U)
#define | SEMC_NANDCR3_NDOPT1_SHIFT (0U)
#define | SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
#define | SEMC_NANDCR3_NDOPT2_MASK (0x2U)
#define | SEMC_NANDCR3_NDOPT2_SHIFT (1U)
#define | SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
#define | SEMC_NANDCR3_NDOPT3_MASK (0x4U)
#define | SEMC_NANDCR3_NDOPT3_SHIFT (2U)
#define | SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
#define | SEMC_NANDCR3_CLE_MASK (0x8U)
#define | SEMC_NANDCR3_CLE_SHIFT (3U)
#define | SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
#define | SEMC_NANDCR3_RDS_MASK (0xF0000U)
#define | SEMC_NANDCR3_RDS_SHIFT (16U)
#define | SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
#define | SEMC_NANDCR3_RDH_MASK (0xF00000U)
#define | SEMC_NANDCR3_RDH_SHIFT (20U)
#define | SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
#define | SEMC_NANDCR3_WDS_MASK (0xF000000U)
#define | SEMC_NANDCR3_WDS_SHIFT (24U)
#define | SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
#define | SEMC_NANDCR3_WDH_MASK (0xF0000000U)
#define | SEMC_NANDCR3_WDH_SHIFT (28U)
#define | SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)
NORCR0 - NOR control register 0
#define | SEMC_NORCR0_PS_MASK (0x1U)
#define | SEMC_NORCR0_PS_SHIFT (0U)
#define | SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
#define | SEMC_NORCR0_SYNCEN_MASK (0x2U)
#define | SEMC_NORCR0_SYNCEN_SHIFT (1U)
#define | SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
#define | SEMC_NORCR0_BL_MASK (0x70U)
#define | SEMC_NORCR0_BL_SHIFT (4U)
#define | SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
#define | SEMC_NORCR0_AM_MASK (0x300U)
#define | SEMC_NORCR0_AM_SHIFT (8U)
#define | SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
#define | SEMC_NORCR0_ADVP_MASK (0x400U)
#define | SEMC_NORCR0_ADVP_SHIFT (10U)
#define | SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
#define | SEMC_NORCR0_ADVH_MASK (0x800U)
#define | SEMC_NORCR0_ADVH_SHIFT (11U)
#define | SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
#define | SEMC_NORCR0_COL_MASK (0xF000U)
#define | SEMC_NORCR0_COL_SHIFT (12U)
#define | SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
NORCR1 - NOR control register 1
#define | SEMC_NORCR1_CES_MASK (0xFU)
#define | SEMC_NORCR1_CES_SHIFT (0U)
#define | SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
#define | SEMC_NORCR1_CEH_MASK (0xF0U)
#define | SEMC_NORCR1_CEH_SHIFT (4U)
#define | SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
#define | SEMC_NORCR1_AS_MASK (0xF00U)
#define | SEMC_NORCR1_AS_SHIFT (8U)
#define | SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
#define | SEMC_NORCR1_AH_MASK (0xF000U)
#define | SEMC_NORCR1_AH_SHIFT (12U)
#define | SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
#define | SEMC_NORCR1_WEL_MASK (0xF0000U)
#define | SEMC_NORCR1_WEL_SHIFT (16U)
#define | SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
#define | SEMC_NORCR1_WEH_MASK (0xF00000U)
#define | SEMC_NORCR1_WEH_SHIFT (20U)
#define | SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
#define | SEMC_NORCR1_REL_MASK (0xF000000U)
#define | SEMC_NORCR1_REL_SHIFT (24U)
#define | SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
#define | SEMC_NORCR1_REH_MASK (0xF0000000U)
#define | SEMC_NORCR1_REH_SHIFT (28U)
#define | SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
NORCR2 - NOR control register 2
#define | SEMC_NORCR2_TA_MASK (0xF00U)
#define | SEMC_NORCR2_TA_SHIFT (8U)
#define | SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
#define | SEMC_NORCR2_AWDH_MASK (0xF000U)
#define | SEMC_NORCR2_AWDH_SHIFT (12U)
#define | SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
#define | SEMC_NORCR2_LC_MASK (0xF0000U)
#define | SEMC_NORCR2_LC_SHIFT (16U)
#define | SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
#define | SEMC_NORCR2_RD_MASK (0xF00000U)
#define | SEMC_NORCR2_RD_SHIFT (20U)
#define | SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
#define | SEMC_NORCR2_CEITV_MASK (0xF000000U)
#define | SEMC_NORCR2_CEITV_SHIFT (24U)
#define | SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
#define | SEMC_NORCR2_RDH_MASK (0xF0000000U)
#define | SEMC_NORCR2_RDH_SHIFT (28U)
#define | SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
NORCR3 - NOR control register 3
#define | SEMC_NORCR3_ASSR_MASK (0xFU)
#define | SEMC_NORCR3_ASSR_SHIFT (0U)
#define | SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
#define | SEMC_NORCR3_AHSR_MASK (0xF0U)
#define | SEMC_NORCR3_AHSR_SHIFT (4U)
#define | SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)
SRAMCR0 - SRAM control register 0
#define | SEMC_SRAMCR0_PS_MASK (0x1U)
#define | SEMC_SRAMCR0_PS_SHIFT (0U)
#define | SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
#define | SEMC_SRAMCR0_SYNCEN_MASK (0x2U)
#define | SEMC_SRAMCR0_SYNCEN_SHIFT (1U)
#define | SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
#define | SEMC_SRAMCR0_BL_MASK (0x70U)
#define | SEMC_SRAMCR0_BL_SHIFT (4U)
#define | SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
#define | SEMC_SRAMCR0_AM_MASK (0x300U)
#define | SEMC_SRAMCR0_AM_SHIFT (8U)
#define | SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
#define | SEMC_SRAMCR0_ADVP_MASK (0x400U)
#define | SEMC_SRAMCR0_ADVP_SHIFT (10U)
#define | SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
#define | SEMC_SRAMCR0_ADVH_MASK (0x800U)
#define | SEMC_SRAMCR0_ADVH_SHIFT (11U)
#define | SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
#define | SEMC_SRAMCR0_COL_MASK (0xF000U)
#define | SEMC_SRAMCR0_COL_SHIFT (12U)
#define | SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
SRAMCR1 - SRAM control register 1
#define | SEMC_SRAMCR1_CES_MASK (0xFU)
#define | SEMC_SRAMCR1_CES_SHIFT (0U)
#define | SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
#define | SEMC_SRAMCR1_CEH_MASK (0xF0U)
#define | SEMC_SRAMCR1_CEH_SHIFT (4U)
#define | SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
#define | SEMC_SRAMCR1_AS_MASK (0xF00U)
#define | SEMC_SRAMCR1_AS_SHIFT (8U)
#define | SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
#define | SEMC_SRAMCR1_AH_MASK (0xF000U)
#define | SEMC_SRAMCR1_AH_SHIFT (12U)
#define | SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
#define | SEMC_SRAMCR1_WEL_MASK (0xF0000U)
#define | SEMC_SRAMCR1_WEL_SHIFT (16U)
#define | SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
#define | SEMC_SRAMCR1_WEH_MASK (0xF00000U)
#define | SEMC_SRAMCR1_WEH_SHIFT (20U)
#define | SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
#define | SEMC_SRAMCR1_REL_MASK (0xF000000U)
#define | SEMC_SRAMCR1_REL_SHIFT (24U)
#define | SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
#define | SEMC_SRAMCR1_REH_MASK (0xF0000000U)
#define | SEMC_SRAMCR1_REH_SHIFT (28U)
#define | SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
SRAMCR2 - SRAM control register 2
#define | SEMC_SRAMCR2_WDS_MASK (0xFU)
#define | SEMC_SRAMCR2_WDS_SHIFT (0U)
#define | SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
#define | SEMC_SRAMCR2_WDH_MASK (0xF0U)
#define | SEMC_SRAMCR2_WDH_SHIFT (4U)
#define | SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
#define | SEMC_SRAMCR2_TA_MASK (0xF00U)
#define | SEMC_SRAMCR2_TA_SHIFT (8U)
#define | SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
#define | SEMC_SRAMCR2_AWDH_MASK (0xF000U)
#define | SEMC_SRAMCR2_AWDH_SHIFT (12U)
#define | SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
#define | SEMC_SRAMCR2_LC_MASK (0xF0000U)
#define | SEMC_SRAMCR2_LC_SHIFT (16U)
#define | SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
#define | SEMC_SRAMCR2_RD_MASK (0xF00000U)
#define | SEMC_SRAMCR2_RD_SHIFT (20U)
#define | SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
#define | SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
#define | SEMC_SRAMCR2_CEITV_SHIFT (24U)
#define | SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
#define | SEMC_SRAMCR2_RDH_MASK (0xF0000000U)
#define | SEMC_SRAMCR2_RDH_SHIFT (28U)
#define | SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)
DBICR0 - DBI-B control register 0
#define | SEMC_DBICR0_PS_MASK (0x1U)
#define | SEMC_DBICR0_PS_SHIFT (0U)
#define | SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
#define | SEMC_DBICR0_BL_MASK (0x70U)
#define | SEMC_DBICR0_BL_SHIFT (4U)
#define | SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
#define | SEMC_DBICR0_COL_MASK (0xF000U)
#define | SEMC_DBICR0_COL_SHIFT (12U)
#define | SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
DBICR1 - DBI-B control register 1
#define | SEMC_DBICR1_CES_MASK (0xFU)
#define | SEMC_DBICR1_CES_SHIFT (0U)
#define | SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
#define | SEMC_DBICR1_CEH_MASK (0xF0U)
#define | SEMC_DBICR1_CEH_SHIFT (4U)
#define | SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
#define | SEMC_DBICR1_WEL_MASK (0xF00U)
#define | SEMC_DBICR1_WEL_SHIFT (8U)
#define | SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
#define | SEMC_DBICR1_WEH_MASK (0xF000U)
#define | SEMC_DBICR1_WEH_SHIFT (12U)
#define | SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
#define | SEMC_DBICR1_REL_MASK (0x3F0000U)
#define | SEMC_DBICR1_REL_SHIFT (16U)
#define | SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
#define | SEMC_DBICR1_REH_MASK (0xFC00000U)
#define | SEMC_DBICR1_REH_SHIFT (22U)
#define | SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
#define | SEMC_DBICR1_CEITV_MASK (0xF0000000U)
#define | SEMC_DBICR1_CEITV_SHIFT (28U)
#define | SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
IPCR0 - IP Command control register 0
#define | SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
#define | SEMC_IPCR0_SA_SHIFT (0U)
#define | SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
IPCR1 - IP Command control register 1
#define | SEMC_IPCR1_DATSZ_MASK (0x7U)
#define | SEMC_IPCR1_DATSZ_SHIFT (0U)
#define | SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
#define | SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U)
#define | SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U)
#define | SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)
IPCR2 - IP Command control register 2
#define | SEMC_IPCR2_BM0_MASK (0x1U)
#define | SEMC_IPCR2_BM0_SHIFT (0U)
#define | SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
#define | SEMC_IPCR2_BM1_MASK (0x2U)
#define | SEMC_IPCR2_BM1_SHIFT (1U)
#define | SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
#define | SEMC_IPCR2_BM2_MASK (0x4U)
#define | SEMC_IPCR2_BM2_SHIFT (2U)
#define | SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
#define | SEMC_IPCR2_BM3_MASK (0x8U)
#define | SEMC_IPCR2_BM3_SHIFT (3U)
#define | SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
IPTXDAT - TX DATA register (for IP Command)
#define | SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
#define | SEMC_IPTXDAT_DAT_SHIFT (0U)
#define | SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
IPRXDAT - RX DATA register (for IP Command)
#define | SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
#define | SEMC_IPRXDAT_DAT_SHIFT (0U)
#define | SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
STS12 - Status register 12
#define | SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
#define | SEMC_STS12_NDADDR_SHIFT (0U)
#define | SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
STS13 - Status register 13
#define | SEMC_STS13_SLVLOCK_MASK (0x1U)
#define | SEMC_STS13_SLVLOCK_SHIFT (0U)
#define | SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
#define | SEMC_STS13_REFLOCK_MASK (0x2U)
#define | SEMC_STS13_REFLOCK_SHIFT (1U)
#define | SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
#define | SEMC_STS13_SLVSEL_MASK (0xFCU)
#define | SEMC_STS13_SLVSEL_SHIFT (2U)
#define | SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
#define | SEMC_STS13_REFSEL_MASK (0x3F00U)
#define | SEMC_STS13_REFSEL_SHIFT (8U)
#define | SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)
HPLR - SNVS_HP Lock Register
#define | SNVS_HPLR_ZMK_WSL_MASK (0x1U)
#define | SNVS_HPLR_ZMK_WSL_SHIFT (0U)
#define | SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
#define | SNVS_HPLR_ZMK_RSL_MASK (0x2U)
#define | SNVS_HPLR_ZMK_RSL_SHIFT (1U)
#define | SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
#define | SNVS_HPLR_SRTC_SL_MASK (0x4U)
#define | SNVS_HPLR_SRTC_SL_SHIFT (2U)
#define | SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
#define | SNVS_HPLR_LPCALB_SL_MASK (0x8U)
#define | SNVS_HPLR_LPCALB_SL_SHIFT (3U)
#define | SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
#define | SNVS_HPLR_MC_SL_MASK (0x10U)
#define | SNVS_HPLR_MC_SL_SHIFT (4U)
#define | SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
#define | SNVS_HPLR_GPR_SL_MASK (0x20U)
#define | SNVS_HPLR_GPR_SL_SHIFT (5U)
#define | SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
#define | SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
#define | SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
#define | SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
#define | SNVS_HPLR_LPTDCR_SL_MASK (0x100U)
#define | SNVS_HPLR_LPTDCR_SL_SHIFT (8U)
#define | SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)
#define | SNVS_HPLR_MKS_SL_MASK (0x200U)
#define | SNVS_HPLR_MKS_SL_SHIFT (9U)
#define | SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
#define | SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
#define | SNVS_HPLR_HPSVCR_L_SHIFT (16U)
#define | SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
#define | SNVS_HPLR_HPSICR_L_MASK (0x20000U)
#define | SNVS_HPLR_HPSICR_L_SHIFT (17U)
#define | SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
#define | SNVS_HPLR_HAC_L_MASK (0x40000U)
#define | SNVS_HPLR_HAC_L_SHIFT (18U)
#define | SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
HPCOMR - SNVS_HP Command Register
#define | SNVS_HPCOMR_SSM_ST_MASK (0x1U)
#define | SNVS_HPCOMR_SSM_ST_SHIFT (0U)
#define | SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
#define | SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
#define | SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
#define | SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
#define | SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
#define | SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
#define | SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
#define | SNVS_HPCOMR_LP_SWR_MASK (0x10U)
#define | SNVS_HPCOMR_LP_SWR_SHIFT (4U)
#define | SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
#define | SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
#define | SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
#define | SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
#define | SNVS_HPCOMR_SW_SV_MASK (0x100U)
#define | SNVS_HPCOMR_SW_SV_SHIFT (8U)
#define | SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
#define | SNVS_HPCOMR_SW_FSV_MASK (0x200U)
#define | SNVS_HPCOMR_SW_FSV_SHIFT (9U)
#define | SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
#define | SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
#define | SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
#define | SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
#define | SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
#define | SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
#define | SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
#define | SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
#define | SNVS_HPCOMR_MKS_EN_SHIFT (13U)
#define | SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
#define | SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
#define | SNVS_HPCOMR_HAC_EN_SHIFT (16U)
#define | SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
#define | SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
#define | SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
#define | SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
#define | SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
#define | SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
#define | SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
#define | SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
#define | SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
#define | SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
#define | SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
#define | SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
#define | SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
HPCR - SNVS_HP Control Register
#define | SNVS_HPCR_RTC_EN_MASK (0x1U)
#define | SNVS_HPCR_RTC_EN_SHIFT (0U)
#define | SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
#define | SNVS_HPCR_HPTA_EN_MASK (0x2U)
#define | SNVS_HPCR_HPTA_EN_SHIFT (1U)
#define | SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
#define | SNVS_HPCR_DIS_PI_MASK (0x4U)
#define | SNVS_HPCR_DIS_PI_SHIFT (2U)
#define | SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
#define | SNVS_HPCR_PI_EN_MASK (0x8U)
#define | SNVS_HPCR_PI_EN_SHIFT (3U)
#define | SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
#define | SNVS_HPCR_PI_FREQ_MASK (0xF0U)
#define | SNVS_HPCR_PI_FREQ_SHIFT (4U)
#define | SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
#define | SNVS_HPCR_HPCALB_EN_MASK (0x100U)
#define | SNVS_HPCR_HPCALB_EN_SHIFT (8U)
#define | SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
#define | SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
#define | SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
#define | SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
#define | SNVS_HPCR_HP_TS_MASK (0x10000U)
#define | SNVS_HPCR_HP_TS_SHIFT (16U)
#define | SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
#define | SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
#define | SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
#define | SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
#define | SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
#define | SNVS_HPCR_BTN_MASK_SHIFT (27U)
#define | SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
HPSICR - SNVS_HP Security Interrupt Control Register
#define | SNVS_HPSICR_SV0_EN_MASK (0x1U)
#define | SNVS_HPSICR_SV0_EN_SHIFT (0U)
#define | SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
#define | SNVS_HPSICR_SV1_EN_MASK (0x2U)
#define | SNVS_HPSICR_SV1_EN_SHIFT (1U)
#define | SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
#define | SNVS_HPSICR_SV2_EN_MASK (0x4U)
#define | SNVS_HPSICR_SV2_EN_SHIFT (2U)
#define | SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
#define | SNVS_HPSICR_SV3_EN_MASK (0x8U)
#define | SNVS_HPSICR_SV3_EN_SHIFT (3U)
#define | SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
#define | SNVS_HPSICR_SV4_EN_MASK (0x10U)
#define | SNVS_HPSICR_SV4_EN_SHIFT (4U)
#define | SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
#define | SNVS_HPSICR_SV5_EN_MASK (0x20U)
#define | SNVS_HPSICR_SV5_EN_SHIFT (5U)
#define | SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
#define | SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
#define | SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
#define | SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
HPSVCR - SNVS_HP Security Violation Control Register
#define | SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
#define | SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
#define | SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
#define | SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
#define | SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
#define | SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
#define | SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
#define | SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
#define | SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
#define | SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
#define | SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
#define | SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
#define | SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
#define | SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
#define | SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
#define | SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
#define | SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
#define | SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
#define | SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
#define | SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
#define | SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
HPSR - SNVS_HP Status Register
#define | SNVS_HPSR_HPTA_MASK (0x1U)
#define | SNVS_HPSR_HPTA_SHIFT (0U)
#define | SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
#define | SNVS_HPSR_PI_MASK (0x2U)
#define | SNVS_HPSR_PI_SHIFT (1U)
#define | SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
#define | SNVS_HPSR_LPDIS_MASK (0x10U)
#define | SNVS_HPSR_LPDIS_SHIFT (4U)
#define | SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
#define | SNVS_HPSR_BTN_MASK (0x40U)
#define | SNVS_HPSR_BTN_SHIFT (6U)
#define | SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
#define | SNVS_HPSR_BI_MASK (0x80U)
#define | SNVS_HPSR_BI_SHIFT (7U)
#define | SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
#define | SNVS_HPSR_SSM_STATE_MASK (0xF00U)
#define | SNVS_HPSR_SSM_STATE_SHIFT (8U)
#define | SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
#define | SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)
#define | SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)
#define | SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)
#define | SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
#define | SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
#define | SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
#define | SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
#define | SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
#define | SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
#define | SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
#define | SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
#define | SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
HPSVSR - SNVS_HP Security Violation Status Register
#define | SNVS_HPSVSR_SV0_MASK (0x1U)
#define | SNVS_HPSVSR_SV0_SHIFT (0U)
#define | SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
#define | SNVS_HPSVSR_SV1_MASK (0x2U)
#define | SNVS_HPSVSR_SV1_SHIFT (1U)
#define | SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
#define | SNVS_HPSVSR_SV2_MASK (0x4U)
#define | SNVS_HPSVSR_SV2_SHIFT (2U)
#define | SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
#define | SNVS_HPSVSR_SV3_MASK (0x8U)
#define | SNVS_HPSVSR_SV3_SHIFT (3U)
#define | SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
#define | SNVS_HPSVSR_SV4_MASK (0x10U)
#define | SNVS_HPSVSR_SV4_SHIFT (4U)
#define | SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
#define | SNVS_HPSVSR_SV5_MASK (0x20U)
#define | SNVS_HPSVSR_SV5_SHIFT (5U)
#define | SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
#define | SNVS_HPSVSR_SW_SV_MASK (0x2000U)
#define | SNVS_HPSVSR_SW_SV_SHIFT (13U)
#define | SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
#define | SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
#define | SNVS_HPSVSR_SW_FSV_SHIFT (14U)
#define | SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
#define | SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
#define | SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
#define | SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
#define | SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
#define | SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
#define | SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
#define | SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
#define | SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
#define | SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
#define | SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
#define | SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
#define | SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
HPHACIVR - SNVS_HP High Assurance Counter IV Register
#define | SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
#define | SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
#define | SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
HPHACR - SNVS_HP High Assurance Counter Register
#define | SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
#define | SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
#define | SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
HPRTCMR - SNVS_HP Real Time Counter MSB Register
#define | SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
#define | SNVS_HPRTCMR_RTC_SHIFT (0U)
#define | SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
HPRTCLR - SNVS_HP Real Time Counter LSB Register
#define | SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
#define | SNVS_HPRTCLR_RTC_SHIFT (0U)
#define | SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
HPTAMR - SNVS_HP Time Alarm MSB Register
#define | SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
#define | SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
#define | SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
HPTALR - SNVS_HP Time Alarm LSB Register
#define | SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
#define | SNVS_HPTALR_HPTA_LS_SHIFT (0U)
#define | SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
LPLR - SNVS_LP Lock Register
#define | SNVS_LPLR_ZMK_WHL_MASK (0x1U)
#define | SNVS_LPLR_ZMK_WHL_SHIFT (0U)
#define | SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
#define | SNVS_LPLR_ZMK_RHL_MASK (0x2U)
#define | SNVS_LPLR_ZMK_RHL_SHIFT (1U)
#define | SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
#define | SNVS_LPLR_SRTC_HL_MASK (0x4U)
#define | SNVS_LPLR_SRTC_HL_SHIFT (2U)
#define | SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
#define | SNVS_LPLR_LPCALB_HL_MASK (0x8U)
#define | SNVS_LPLR_LPCALB_HL_SHIFT (3U)
#define | SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
#define | SNVS_LPLR_MC_HL_MASK (0x10U)
#define | SNVS_LPLR_MC_HL_SHIFT (4U)
#define | SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
#define | SNVS_LPLR_GPR_HL_MASK (0x20U)
#define | SNVS_LPLR_GPR_HL_SHIFT (5U)
#define | SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
#define | SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
#define | SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
#define | SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
#define | SNVS_LPLR_LPTDCR_HL_MASK (0x100U)
#define | SNVS_LPLR_LPTDCR_HL_SHIFT (8U)
#define | SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)
#define | SNVS_LPLR_MKS_HL_MASK (0x200U)
#define | SNVS_LPLR_MKS_HL_SHIFT (9U)
#define | SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
LPCR - SNVS_LP Control Register
#define | SNVS_LPCR_SRTC_ENV_MASK (0x1U)
#define | SNVS_LPCR_SRTC_ENV_SHIFT (0U)
#define | SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
#define | SNVS_LPCR_LPTA_EN_MASK (0x2U)
#define | SNVS_LPCR_LPTA_EN_SHIFT (1U)
#define | SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
#define | SNVS_LPCR_MC_ENV_MASK (0x4U)
#define | SNVS_LPCR_MC_ENV_SHIFT (2U)
#define | SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
#define | SNVS_LPCR_LPWUI_EN_MASK (0x8U)
#define | SNVS_LPCR_LPWUI_EN_SHIFT (3U)
#define | SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
#define | SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
#define | SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
#define | SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
#define | SNVS_LPCR_DP_EN_MASK (0x20U)
#define | SNVS_LPCR_DP_EN_SHIFT (5U)
#define | SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
#define | SNVS_LPCR_TOP_MASK (0x40U)
#define | SNVS_LPCR_TOP_SHIFT (6U)
#define | SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
#define | SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)
#define | SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)
#define | SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
#define | SNVS_LPCR_LPCALB_EN_MASK (0x100U)
#define | SNVS_LPCR_LPCALB_EN_SHIFT (8U)
#define | SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
#define | SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
#define | SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
#define | SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
#define | SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
#define | SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
#define | SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
#define | SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
#define | SNVS_LPCR_DEBOUNCE_SHIFT (18U)
#define | SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
#define | SNVS_LPCR_ON_TIME_MASK (0x300000U)
#define | SNVS_LPCR_ON_TIME_SHIFT (20U)
#define | SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
#define | SNVS_LPCR_PK_EN_MASK (0x400000U)
#define | SNVS_LPCR_PK_EN_SHIFT (22U)
#define | SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
#define | SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
#define | SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
#define | SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
#define | SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
#define | SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
#define | SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
LPMKCR - SNVS_LP Master Key Control Register
#define | SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
#define | SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
#define | SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
#define | SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
#define | SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
#define | SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
#define | SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
#define | SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
#define | SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
#define | SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
#define | SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
#define | SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
#define | SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
#define | SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
#define | SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
LPSVCR - SNVS_LP Security Violation Control Register
#define | SNVS_LPSVCR_SV0_EN_MASK (0x1U)
#define | SNVS_LPSVCR_SV0_EN_SHIFT (0U)
#define | SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
#define | SNVS_LPSVCR_SV1_EN_MASK (0x2U)
#define | SNVS_LPSVCR_SV1_EN_SHIFT (1U)
#define | SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
#define | SNVS_LPSVCR_SV2_EN_MASK (0x4U)
#define | SNVS_LPSVCR_SV2_EN_SHIFT (2U)
#define | SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
#define | SNVS_LPSVCR_SV3_EN_MASK (0x8U)
#define | SNVS_LPSVCR_SV3_EN_SHIFT (3U)
#define | SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
#define | SNVS_LPSVCR_SV4_EN_MASK (0x10U)
#define | SNVS_LPSVCR_SV4_EN_SHIFT (4U)
#define | SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
#define | SNVS_LPSVCR_SV5_EN_MASK (0x20U)
#define | SNVS_LPSVCR_SV5_EN_SHIFT (5U)
#define | SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
LPTDCR - SNVS_LP Tamper Detectors Configuration Register
#define | SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
#define | SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
#define | SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
#define | SNVS_LPTDCR_MCR_EN_MASK (0x4U)
#define | SNVS_LPTDCR_MCR_EN_SHIFT (2U)
#define | SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
#define | SNVS_LPTDCR_ET1_EN_MASK (0x200U)
#define | SNVS_LPTDCR_ET1_EN_SHIFT (9U)
#define | SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
#define | SNVS_LPTDCR_ET1P_MASK (0x800U)
#define | SNVS_LPTDCR_ET1P_SHIFT (11U)
#define | SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
#define | SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
#define | SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
#define | SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
#define | SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
#define | SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
#define | SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
#define | SNVS_LPTDCR_OSCB_MASK (0x10000000U)
#define | SNVS_LPTDCR_OSCB_SHIFT (28U)
#define | SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
LPSR - SNVS_LP Status Register
#define | SNVS_LPSR_LPTA_MASK (0x1U)
#define | SNVS_LPSR_LPTA_SHIFT (0U)
#define | SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
#define | SNVS_LPSR_SRTCR_MASK (0x2U)
#define | SNVS_LPSR_SRTCR_SHIFT (1U)
#define | SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
#define | SNVS_LPSR_MCR_MASK (0x4U)
#define | SNVS_LPSR_MCR_SHIFT (2U)
#define | SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
#define | SNVS_LPSR_PGD_MASK (0x8U)
#define | SNVS_LPSR_PGD_SHIFT (3U)
#define | SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
#define | SNVS_LPSR_ET1D_MASK (0x200U)
#define | SNVS_LPSR_ET1D_SHIFT (9U)
#define | SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
#define | SNVS_LPSR_ESVD_MASK (0x10000U)
#define | SNVS_LPSR_ESVD_SHIFT (16U)
#define | SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
#define | SNVS_LPSR_EO_MASK (0x20000U)
#define | SNVS_LPSR_EO_SHIFT (17U)
#define | SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
#define | SNVS_LPSR_SPO_MASK (0x40000U)
#define | SNVS_LPSR_SPO_SHIFT (18U)
#define | SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)
#define | SNVS_LPSR_SED_MASK (0x100000U)
#define | SNVS_LPSR_SED_SHIFT (20U)
#define | SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)
#define | SNVS_LPSR_LPNS_MASK (0x40000000U)
#define | SNVS_LPSR_LPNS_SHIFT (30U)
#define | SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
#define | SNVS_LPSR_LPS_MASK (0x80000000U)
#define | SNVS_LPSR_LPS_SHIFT (31U)
#define | SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register
#define | SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
#define | SNVS_LPSRTCMR_SRTC_SHIFT (0U)
#define | SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register
#define | SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
#define | SNVS_LPSRTCLR_SRTC_SHIFT (0U)
#define | SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
LPTAR - SNVS_LP Time Alarm Register
#define | SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
#define | SNVS_LPTAR_LPTA_SHIFT (0U)
#define | SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register
#define | SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
#define | SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
#define | SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
#define | SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
#define | SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
#define | SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register
#define | SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
#define | SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
#define | SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
LPPGDR - SNVS_LP Power Glitch Detector Register
#define | SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
#define | SNVS_LPPGDR_PGD_SHIFT (0U)
#define | SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias)
#define | SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
#define | SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
#define | SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
LPZMKR - SNVS_LP Zeroizable Master Key Register
#define | SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
#define | SNVS_LPZMKR_ZMK_SHIFT (0U)
#define | SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3
#define | SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
#define | SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
#define | SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
LPGPR - SNVS_LP General Purpose Registers 0 .. 7
#define | SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
#define | SNVS_LPGPR_GPR_SHIFT (0U)
#define | SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
HPVIDR1 - SNVS_HP Version ID Register 1
#define | SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
#define | SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
#define | SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
#define | SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
#define | SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
#define | SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
#define | SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
#define | SNVS_HPVIDR1_IP_ID_SHIFT (16U)
#define | SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
HPVIDR2 - SNVS_HP Version ID Register 2
#define | SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
#define | SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
#define | SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
#define | SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
#define | SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
#define | SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
#define | SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
#define | SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
#define | SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
#define | SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
#define | SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
#define | SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
SCR - SPDIF Configuration Register
#define | SPDIF_SCR_USRC_SEL_MASK (0x3U)
#define | SPDIF_SCR_USRC_SEL_SHIFT (0U)
#define | SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
#define | SPDIF_SCR_TXSEL_MASK (0x1CU)
#define | SPDIF_SCR_TXSEL_SHIFT (2U)
#define | SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
#define | SPDIF_SCR_VALCTRL_MASK (0x20U)
#define | SPDIF_SCR_VALCTRL_SHIFT (5U)
#define | SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
#define | SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
#define | SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
#define | SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
#define | SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
#define | SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
#define | SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
#define | SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
#define | SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
#define | SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
#define | SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
#define | SPDIF_SCR_SOFT_RESET_SHIFT (12U)
#define | SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
#define | SPDIF_SCR_LOW_POWER_MASK (0x2000U)
#define | SPDIF_SCR_LOW_POWER_SHIFT (13U)
#define | SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
#define | SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
#define | SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
#define | SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
#define | SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
#define | SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
#define | SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
#define | SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
#define | SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
#define | SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
#define | SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
#define | SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
#define | SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
#define | SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
#define | SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
#define | SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
#define | SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
#define | SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
#define | SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
#define | SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
#define | SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
#define | SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
SRCD - CDText Control Register
#define | SPDIF_SRCD_USYNCMODE_MASK (0x2U)
#define | SPDIF_SRCD_USYNCMODE_SHIFT (1U)
#define | SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
SRPC - PhaseConfig Register
#define | SPDIF_SRPC_GAINSEL_MASK (0x38U)
#define | SPDIF_SRPC_GAINSEL_SHIFT (3U)
#define | SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
#define | SPDIF_SRPC_LOCK_MASK (0x40U)
#define | SPDIF_SRPC_LOCK_SHIFT (6U)
#define | SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
#define | SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
#define | SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
#define | SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
SIE - InterruptEn Register
#define | SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
#define | SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
#define | SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
#define | SPDIF_SIE_TXEM_MASK (0x2U)
#define | SPDIF_SIE_TXEM_SHIFT (1U)
#define | SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
#define | SPDIF_SIE_LOCKLOSS_MASK (0x4U)
#define | SPDIF_SIE_LOCKLOSS_SHIFT (2U)
#define | SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
#define | SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
#define | SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
#define | SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
#define | SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
#define | SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
#define | SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
#define | SPDIF_SIE_UQERR_MASK (0x20U)
#define | SPDIF_SIE_UQERR_SHIFT (5U)
#define | SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
#define | SPDIF_SIE_UQSYNC_MASK (0x40U)
#define | SPDIF_SIE_UQSYNC_SHIFT (6U)
#define | SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
#define | SPDIF_SIE_QRXOV_MASK (0x80U)
#define | SPDIF_SIE_QRXOV_SHIFT (7U)
#define | SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
#define | SPDIF_SIE_QRXFUL_MASK (0x100U)
#define | SPDIF_SIE_QRXFUL_SHIFT (8U)
#define | SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
#define | SPDIF_SIE_URXOV_MASK (0x200U)
#define | SPDIF_SIE_URXOV_SHIFT (9U)
#define | SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
#define | SPDIF_SIE_URXFUL_MASK (0x400U)
#define | SPDIF_SIE_URXFUL_SHIFT (10U)
#define | SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
#define | SPDIF_SIE_BITERR_MASK (0x4000U)
#define | SPDIF_SIE_BITERR_SHIFT (14U)
#define | SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
#define | SPDIF_SIE_SYMERR_MASK (0x8000U)
#define | SPDIF_SIE_SYMERR_SHIFT (15U)
#define | SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
#define | SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
#define | SPDIF_SIE_VALNOGOOD_SHIFT (16U)
#define | SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
#define | SPDIF_SIE_CNEW_MASK (0x20000U)
#define | SPDIF_SIE_CNEW_SHIFT (17U)
#define | SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
#define | SPDIF_SIE_TXRESYN_MASK (0x40000U)
#define | SPDIF_SIE_TXRESYN_SHIFT (18U)
#define | SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
#define | SPDIF_SIE_TXUNOV_MASK (0x80000U)
#define | SPDIF_SIE_TXUNOV_SHIFT (19U)
#define | SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
#define | SPDIF_SIE_LOCK_MASK (0x100000U)
#define | SPDIF_SIE_LOCK_SHIFT (20U)
#define | SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
SIC - InterruptClear Register
#define | SPDIF_SIC_LOCKLOSS_MASK (0x4U)
#define | SPDIF_SIC_LOCKLOSS_SHIFT (2U)
#define | SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
#define | SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
#define | SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
#define | SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
#define | SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
#define | SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
#define | SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
#define | SPDIF_SIC_UQERR_MASK (0x20U)
#define | SPDIF_SIC_UQERR_SHIFT (5U)
#define | SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
#define | SPDIF_SIC_UQSYNC_MASK (0x40U)
#define | SPDIF_SIC_UQSYNC_SHIFT (6U)
#define | SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
#define | SPDIF_SIC_QRXOV_MASK (0x80U)
#define | SPDIF_SIC_QRXOV_SHIFT (7U)
#define | SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
#define | SPDIF_SIC_URXOV_MASK (0x200U)
#define | SPDIF_SIC_URXOV_SHIFT (9U)
#define | SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
#define | SPDIF_SIC_BITERR_MASK (0x4000U)
#define | SPDIF_SIC_BITERR_SHIFT (14U)
#define | SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
#define | SPDIF_SIC_SYMERR_MASK (0x8000U)
#define | SPDIF_SIC_SYMERR_SHIFT (15U)
#define | SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
#define | SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
#define | SPDIF_SIC_VALNOGOOD_SHIFT (16U)
#define | SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
#define | SPDIF_SIC_CNEW_MASK (0x20000U)
#define | SPDIF_SIC_CNEW_SHIFT (17U)
#define | SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
#define | SPDIF_SIC_TXRESYN_MASK (0x40000U)
#define | SPDIF_SIC_TXRESYN_SHIFT (18U)
#define | SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
#define | SPDIF_SIC_TXUNOV_MASK (0x80000U)
#define | SPDIF_SIC_TXUNOV_SHIFT (19U)
#define | SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
#define | SPDIF_SIC_LOCK_MASK (0x100000U)
#define | SPDIF_SIC_LOCK_SHIFT (20U)
#define | SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
SIS - InterruptStat Register
#define | SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
#define | SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
#define | SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
#define | SPDIF_SIS_TXEM_MASK (0x2U)
#define | SPDIF_SIS_TXEM_SHIFT (1U)
#define | SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
#define | SPDIF_SIS_LOCKLOSS_MASK (0x4U)
#define | SPDIF_SIS_LOCKLOSS_SHIFT (2U)
#define | SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
#define | SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
#define | SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
#define | SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
#define | SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
#define | SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
#define | SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
#define | SPDIF_SIS_UQERR_MASK (0x20U)
#define | SPDIF_SIS_UQERR_SHIFT (5U)
#define | SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
#define | SPDIF_SIS_UQSYNC_MASK (0x40U)
#define | SPDIF_SIS_UQSYNC_SHIFT (6U)
#define | SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
#define | SPDIF_SIS_QRXOV_MASK (0x80U)
#define | SPDIF_SIS_QRXOV_SHIFT (7U)
#define | SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
#define | SPDIF_SIS_QRXFUL_MASK (0x100U)
#define | SPDIF_SIS_QRXFUL_SHIFT (8U)
#define | SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
#define | SPDIF_SIS_URXOV_MASK (0x200U)
#define | SPDIF_SIS_URXOV_SHIFT (9U)
#define | SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
#define | SPDIF_SIS_URXFUL_MASK (0x400U)
#define | SPDIF_SIS_URXFUL_SHIFT (10U)
#define | SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
#define | SPDIF_SIS_BITERR_MASK (0x4000U)
#define | SPDIF_SIS_BITERR_SHIFT (14U)
#define | SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
#define | SPDIF_SIS_SYMERR_MASK (0x8000U)
#define | SPDIF_SIS_SYMERR_SHIFT (15U)
#define | SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
#define | SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
#define | SPDIF_SIS_VALNOGOOD_SHIFT (16U)
#define | SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
#define | SPDIF_SIS_CNEW_MASK (0x20000U)
#define | SPDIF_SIS_CNEW_SHIFT (17U)
#define | SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
#define | SPDIF_SIS_TXRESYN_MASK (0x40000U)
#define | SPDIF_SIS_TXRESYN_SHIFT (18U)
#define | SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
#define | SPDIF_SIS_TXUNOV_MASK (0x80000U)
#define | SPDIF_SIS_TXUNOV_SHIFT (19U)
#define | SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
#define | SPDIF_SIS_LOCK_MASK (0x100000U)
#define | SPDIF_SIS_LOCK_SHIFT (20U)
#define | SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
SRL - SPDIFRxLeft Register
#define | SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
#define | SPDIF_SRL_RXDATALEFT_SHIFT (0U)
#define | SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
SRR - SPDIFRxRight Register
#define | SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
#define | SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
#define | SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
SRCSH - SPDIFRxCChannel_h Register
#define | SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
#define | SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
#define | SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
SRCSL - SPDIFRxCChannel_l Register
#define | SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
#define | SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
#define | SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
SRU - UchannelRx Register
#define | SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
#define | SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
#define | SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
SRQ - QchannelRx Register
#define | SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
#define | SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
#define | SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
STL - SPDIFTxLeft Register
#define | SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
#define | SPDIF_STL_TXDATALEFT_SHIFT (0U)
#define | SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
STR - SPDIFTxRight Register
#define | SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
#define | SPDIF_STR_TXDATARIGHT_SHIFT (0U)
#define | SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
STCSCH - SPDIFTxCChannelCons_h Register
#define | SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
#define | SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
#define | SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
STCSCL - SPDIFTxCChannelCons_l Register
#define | SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
#define | SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
#define | SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
SRFM - FreqMeas Register
#define | SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
#define | SPDIF_SRFM_FREQMEAS_SHIFT (0U)
#define | SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
STC - SPDIFTxClk Register
#define | SPDIF_STC_TXCLK_DF_MASK (0x7FU)
#define | SPDIF_STC_TXCLK_DF_SHIFT (0U)
#define | SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
#define | SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
#define | SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
#define | SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
#define | SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
#define | SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
#define | SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
#define | SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
#define | SPDIF_STC_SYSCLK_DF_SHIFT (11U)
#define | SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
SCR - SRC Control Register
#define | SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
#define | SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
#define | SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
#define | SRC_SCR_CORE0_RST_MASK (0x2000U)
#define | SRC_SCR_CORE0_RST_SHIFT (13U)
#define | SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
#define | SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
#define | SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
#define | SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
#define | SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
#define | SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
#define | SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
#define | SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
#define | SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
#define | SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
SBMR1 - SRC Boot Mode Register 1
#define | SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
#define | SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
#define | SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
#define | SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
#define | SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
#define | SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
#define | SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
#define | SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
#define | SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
#define | SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
#define | SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
#define | SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
SRSR - SRC Reset Status Register
#define | SRC_SRSR_IPP_RESET_B_MASK (0x1U)
#define | SRC_SRSR_IPP_RESET_B_SHIFT (0U)
#define | SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
#define | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)
#define | SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)
#define | SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
#define | SRC_SRSR_CSU_RESET_B_MASK (0x4U)
#define | SRC_SRSR_CSU_RESET_B_SHIFT (2U)
#define | SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
#define | SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
#define | SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
#define | SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
#define | SRC_SRSR_WDOG_RST_B_MASK (0x10U)
#define | SRC_SRSR_WDOG_RST_B_SHIFT (4U)
#define | SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
#define | SRC_SRSR_JTAG_RST_B_MASK (0x20U)
#define | SRC_SRSR_JTAG_RST_B_SHIFT (5U)
#define | SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
#define | SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
#define | SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
#define | SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
#define | SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
#define | SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
#define | SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
#define | SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
#define | SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
#define | SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
SBMR2 - SRC Boot Mode Register 2
#define | SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
#define | SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
#define | SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
#define | SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
#define | SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
#define | SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
#define | SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
#define | SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
#define | SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
#define | SRC_SBMR2_BMOD_MASK (0x3000000U)
#define | SRC_SBMR2_BMOD_SHIFT (24U)
#define | SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
GPR - SRC General Purpose Register 1..SRC General Purpose Register 10
#define | SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
#define | SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
#define | SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
#define | SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
#define | SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
#define | SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
TEMPSENSE0 - Tempsensor Control Register 0
#define | TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)
#define | TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)
#define | TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
#define | TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)
#define | TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)
#define | TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
#define | TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)
#define | TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)
#define | TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
#define | TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)
#define | TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)
#define | TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
#define | TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)
#define | TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)
#define | TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
TEMPSENSE0_SET - Tempsensor Control Register 0
#define | TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)
#define | TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)
#define | TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
#define | TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
#define | TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
#define | TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
#define | TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)
#define | TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)
#define | TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
#define | TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)
#define | TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)
#define | TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
#define | TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)
#define | TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
#define | TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
TEMPSENSE0_CLR - Tempsensor Control Register 0
#define | TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)
#define | TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)
#define | TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
#define | TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
#define | TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
#define | TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
#define | TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)
#define | TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)
#define | TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
#define | TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)
#define | TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)
#define | TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
#define | TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)
#define | TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
#define | TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
TEMPSENSE0_TOG - Tempsensor Control Register 0
#define | TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)
#define | TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)
#define | TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
#define | TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
#define | TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
#define | TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
#define | TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)
#define | TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)
#define | TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
#define | TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)
#define | TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)
#define | TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
#define | TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)
#define | TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
#define | TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
TEMPSENSE1 - Tempsensor Control Register 1
#define | TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)
#define | TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)
#define | TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
TEMPSENSE1_SET - Tempsensor Control Register 1
#define | TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
#define | TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
#define | TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
TEMPSENSE1_CLR - Tempsensor Control Register 1
#define | TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
#define | TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
#define | TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
TEMPSENSE1_TOG - Tempsensor Control Register 1
#define | TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
#define | TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
#define | TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
TEMPSENSE2 - Tempsensor Control Register 2
#define | TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)
#define | TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
#define | TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
#define | TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
#define | TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
#define | TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
TEMPSENSE2_SET - Tempsensor Control Register 2
#define | TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
#define | TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
#define | TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
#define | TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
#define | TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
#define | TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
TEMPSENSE2_CLR - Tempsensor Control Register 2
#define | TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
#define | TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
#define | TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
#define | TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
#define | TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
#define | TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
TEMPSENSE2_TOG - Tempsensor Control Register 2
#define | TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
#define | TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
#define | TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
#define | TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
#define | TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
#define | TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)
COMP1 - Timer Channel Compare Register 1
#define | TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
#define | TMR_COMP1_COMPARISON_1_SHIFT (0U)
#define | TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
COMP2 - Timer Channel Compare Register 2
#define | TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
#define | TMR_COMP2_COMPARISON_2_SHIFT (0U)
#define | TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
CAPT - Timer Channel Capture Register
#define | TMR_CAPT_CAPTURE_MASK (0xFFFFU)
#define | TMR_CAPT_CAPTURE_SHIFT (0U)
#define | TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
LOAD - Timer Channel Load Register
#define | TMR_LOAD_LOAD_MASK (0xFFFFU)
#define | TMR_LOAD_LOAD_SHIFT (0U)
#define | TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
HOLD - Timer Channel Hold Register
#define | TMR_HOLD_HOLD_MASK (0xFFFFU)
#define | TMR_HOLD_HOLD_SHIFT (0U)
#define | TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
CNTR - Timer Channel Counter Register
#define | TMR_CNTR_COUNTER_MASK (0xFFFFU)
#define | TMR_CNTR_COUNTER_SHIFT (0U)
#define | TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
CTRL - Timer Channel Control Register
#define | TMR_CTRL_OUTMODE_MASK (0x7U)
#define | TMR_CTRL_OUTMODE_SHIFT (0U)
#define | TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
#define | TMR_CTRL_COINIT_MASK (0x8U)
#define | TMR_CTRL_COINIT_SHIFT (3U)
#define | TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
#define | TMR_CTRL_DIR_MASK (0x10U)
#define | TMR_CTRL_DIR_SHIFT (4U)
#define | TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
#define | TMR_CTRL_LENGTH_MASK (0x20U)
#define | TMR_CTRL_LENGTH_SHIFT (5U)
#define | TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
#define | TMR_CTRL_ONCE_MASK (0x40U)
#define | TMR_CTRL_ONCE_SHIFT (6U)
#define | TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
#define | TMR_CTRL_SCS_MASK (0x180U)
#define | TMR_CTRL_SCS_SHIFT (7U)
#define | TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
#define | TMR_CTRL_PCS_MASK (0x1E00U)
#define | TMR_CTRL_PCS_SHIFT (9U)
#define | TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
#define | TMR_CTRL_CM_MASK (0xE000U)
#define | TMR_CTRL_CM_SHIFT (13U)
#define | TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
SCTRL - Timer Channel Status and Control Register
#define | TMR_SCTRL_OEN_MASK (0x1U)
#define | TMR_SCTRL_OEN_SHIFT (0U)
#define | TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
#define | TMR_SCTRL_OPS_MASK (0x2U)
#define | TMR_SCTRL_OPS_SHIFT (1U)
#define | TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
#define | TMR_SCTRL_FORCE_MASK (0x4U)
#define | TMR_SCTRL_FORCE_SHIFT (2U)
#define | TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
#define | TMR_SCTRL_VAL_MASK (0x8U)
#define | TMR_SCTRL_VAL_SHIFT (3U)
#define | TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
#define | TMR_SCTRL_EEOF_MASK (0x10U)
#define | TMR_SCTRL_EEOF_SHIFT (4U)
#define | TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
#define | TMR_SCTRL_MSTR_MASK (0x20U)
#define | TMR_SCTRL_MSTR_SHIFT (5U)
#define | TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
#define | TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
#define | TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
#define | TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
#define | TMR_SCTRL_INPUT_MASK (0x100U)
#define | TMR_SCTRL_INPUT_SHIFT (8U)
#define | TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
#define | TMR_SCTRL_IPS_MASK (0x200U)
#define | TMR_SCTRL_IPS_SHIFT (9U)
#define | TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
#define | TMR_SCTRL_IEFIE_MASK (0x400U)
#define | TMR_SCTRL_IEFIE_SHIFT (10U)
#define | TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
#define | TMR_SCTRL_IEF_MASK (0x800U)
#define | TMR_SCTRL_IEF_SHIFT (11U)
#define | TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
#define | TMR_SCTRL_TOFIE_MASK (0x1000U)
#define | TMR_SCTRL_TOFIE_SHIFT (12U)
#define | TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
#define | TMR_SCTRL_TOF_MASK (0x2000U)
#define | TMR_SCTRL_TOF_SHIFT (13U)
#define | TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
#define | TMR_SCTRL_TCFIE_MASK (0x4000U)
#define | TMR_SCTRL_TCFIE_SHIFT (14U)
#define | TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
#define | TMR_SCTRL_TCF_MASK (0x8000U)
#define | TMR_SCTRL_TCF_SHIFT (15U)
#define | TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
CMPLD1 - Timer Channel Comparator Load Register 1
#define | TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
#define | TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
#define | TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
CMPLD2 - Timer Channel Comparator Load Register 2
#define | TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
#define | TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
#define | TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
CSCTRL - Timer Channel Comparator Status and Control Register
#define | TMR_CSCTRL_CL1_MASK (0x3U)
#define | TMR_CSCTRL_CL1_SHIFT (0U)
#define | TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
#define | TMR_CSCTRL_CL2_MASK (0xCU)
#define | TMR_CSCTRL_CL2_SHIFT (2U)
#define | TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
#define | TMR_CSCTRL_TCF1_MASK (0x10U)
#define | TMR_CSCTRL_TCF1_SHIFT (4U)
#define | TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
#define | TMR_CSCTRL_TCF2_MASK (0x20U)
#define | TMR_CSCTRL_TCF2_SHIFT (5U)
#define | TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
#define | TMR_CSCTRL_TCF1EN_MASK (0x40U)
#define | TMR_CSCTRL_TCF1EN_SHIFT (6U)
#define | TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
#define | TMR_CSCTRL_TCF2EN_MASK (0x80U)
#define | TMR_CSCTRL_TCF2EN_SHIFT (7U)
#define | TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
#define | TMR_CSCTRL_UP_MASK (0x200U)
#define | TMR_CSCTRL_UP_SHIFT (9U)
#define | TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
#define | TMR_CSCTRL_TCI_MASK (0x400U)
#define | TMR_CSCTRL_TCI_SHIFT (10U)
#define | TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
#define | TMR_CSCTRL_ROC_MASK (0x800U)
#define | TMR_CSCTRL_ROC_SHIFT (11U)
#define | TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
#define | TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
#define | TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
#define | TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
#define | TMR_CSCTRL_FAULT_MASK (0x2000U)
#define | TMR_CSCTRL_FAULT_SHIFT (13U)
#define | TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
#define | TMR_CSCTRL_DBG_EN_MASK (0xC000U)
#define | TMR_CSCTRL_DBG_EN_SHIFT (14U)
#define | TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
FILT - Timer Channel Input Filter Register
#define | TMR_FILT_FILT_PER_MASK (0xFFU)
#define | TMR_FILT_FILT_PER_SHIFT (0U)
#define | TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
#define | TMR_FILT_FILT_CNT_MASK (0x700U)
#define | TMR_FILT_FILT_CNT_SHIFT (8U)
#define | TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
DMA - Timer Channel DMA Enable Register
#define | TMR_DMA_IEFDE_MASK (0x1U)
#define | TMR_DMA_IEFDE_SHIFT (0U)
#define | TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
#define | TMR_DMA_CMPLD1DE_MASK (0x2U)
#define | TMR_DMA_CMPLD1DE_SHIFT (1U)
#define | TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
#define | TMR_DMA_CMPLD2DE_MASK (0x4U)
#define | TMR_DMA_CMPLD2DE_SHIFT (2U)
#define | TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
ENBL - Timer Channel Enable Register
#define | TMR_ENBL_ENBL_MASK (0xFU)
#define | TMR_ENBL_ENBL_SHIFT (0U)
#define | TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
MCTL - Miscellaneous Control Register
#define | TRNG_MCTL_SAMP_MODE_MASK (0x3U)
#define | TRNG_MCTL_SAMP_MODE_SHIFT (0U)
#define | TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
#define | TRNG_MCTL_OSC_DIV_MASK (0xCU)
#define | TRNG_MCTL_OSC_DIV_SHIFT (2U)
#define | TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
#define | TRNG_MCTL_UNUSED4_MASK (0x10U)
#define | TRNG_MCTL_UNUSED4_SHIFT (4U)
#define | TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
#define | TRNG_MCTL_UNUSED5_MASK (0x20U)
#define | TRNG_MCTL_UNUSED5_SHIFT (5U)
#define | TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
#define | TRNG_MCTL_RST_DEF_MASK (0x40U)
#define | TRNG_MCTL_RST_DEF_SHIFT (6U)
#define | TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
#define | TRNG_MCTL_FOR_SCLK_MASK (0x80U)
#define | TRNG_MCTL_FOR_SCLK_SHIFT (7U)
#define | TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
#define | TRNG_MCTL_FCT_FAIL_MASK (0x100U)
#define | TRNG_MCTL_FCT_FAIL_SHIFT (8U)
#define | TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
#define | TRNG_MCTL_FCT_VAL_MASK (0x200U)
#define | TRNG_MCTL_FCT_VAL_SHIFT (9U)
#define | TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
#define | TRNG_MCTL_ENT_VAL_MASK (0x400U)
#define | TRNG_MCTL_ENT_VAL_SHIFT (10U)
#define | TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
#define | TRNG_MCTL_TST_OUT_MASK (0x800U)
#define | TRNG_MCTL_TST_OUT_SHIFT (11U)
#define | TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
#define | TRNG_MCTL_ERR_MASK (0x1000U)
#define | TRNG_MCTL_ERR_SHIFT (12U)
#define | TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
#define | TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
#define | TRNG_MCTL_TSTOP_OK_SHIFT (13U)
#define | TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
#define | TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
#define | TRNG_MCTL_LRUN_CONT_SHIFT (14U)
#define | TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
#define | TRNG_MCTL_PRGM_MASK (0x10000U)
#define | TRNG_MCTL_PRGM_SHIFT (16U)
#define | TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
SCMISC - Statistical Check Miscellaneous Register
#define | TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
#define | TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
#define | TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
#define | TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
#define | TRNG_SCMISC_RTY_CT_SHIFT (16U)
#define | TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
PKRRNG - Poker Range Register
#define | TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
#define | TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
#define | TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
PKRMAX - Poker Maximum Limit Register
#define | TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
#define | TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
#define | TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
PKRSQ - Poker Square Calculation Result Register
#define | TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
#define | TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
#define | TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
SDCTL - Seed Control Register
#define | TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
#define | TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
#define | TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
#define | TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
#define | TRNG_SDCTL_ENT_DLY_SHIFT (16U)
#define | TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
SBLIM - Sparse Bit Limit Register
#define | TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
#define | TRNG_SBLIM_SB_LIM_SHIFT (0U)
#define | TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
TOTSAM - Total Samples Register
#define | TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
#define | TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
#define | TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
FRQMIN - Frequency Count Minimum Limit Register
#define | TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
#define | TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
#define | TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
FRQCNT - Frequency Count Register
#define | TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
#define | TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
#define | TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
FRQMAX - Frequency Count Maximum Limit Register
#define | TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
#define | TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
#define | TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
SCMC - Statistical Check Monobit Count Register
#define | TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
#define | TRNG_SCMC_MONO_CT_SHIFT (0U)
#define | TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
SCML - Statistical Check Monobit Limit Register
#define | TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
#define | TRNG_SCML_MONO_MAX_SHIFT (0U)
#define | TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
#define | TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
#define | TRNG_SCML_MONO_RNG_SHIFT (16U)
#define | TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
SCR1C - Statistical Check Run Length 1 Count Register
#define | TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
#define | TRNG_SCR1C_R1_0_CT_SHIFT (0U)
#define | TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
#define | TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
#define | TRNG_SCR1C_R1_1_CT_SHIFT (16U)
#define | TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
SCR1L - Statistical Check Run Length 1 Limit Register
#define | TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
#define | TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
#define | TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
#define | TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
#define | TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
#define | TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
SCR2C - Statistical Check Run Length 2 Count Register
#define | TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
#define | TRNG_SCR2C_R2_0_CT_SHIFT (0U)
#define | TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
#define | TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
#define | TRNG_SCR2C_R2_1_CT_SHIFT (16U)
#define | TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
SCR2L - Statistical Check Run Length 2 Limit Register
#define | TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
#define | TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
#define | TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
#define | TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
#define | TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
#define | TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
SCR3C - Statistical Check Run Length 3 Count Register
#define | TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
#define | TRNG_SCR3C_R3_0_CT_SHIFT (0U)
#define | TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
#define | TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
#define | TRNG_SCR3C_R3_1_CT_SHIFT (16U)
#define | TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
SCR3L - Statistical Check Run Length 3 Limit Register
#define | TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
#define | TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
#define | TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
#define | TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
#define | TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
#define | TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
SCR4C - Statistical Check Run Length 4 Count Register
#define | TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
#define | TRNG_SCR4C_R4_0_CT_SHIFT (0U)
#define | TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
#define | TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
#define | TRNG_SCR4C_R4_1_CT_SHIFT (16U)
#define | TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
SCR4L - Statistical Check Run Length 4 Limit Register
#define | TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
#define | TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
#define | TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
#define | TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
#define | TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
#define | TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
SCR5C - Statistical Check Run Length 5 Count Register
#define | TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
#define | TRNG_SCR5C_R5_0_CT_SHIFT (0U)
#define | TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
#define | TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
#define | TRNG_SCR5C_R5_1_CT_SHIFT (16U)
#define | TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
SCR5L - Statistical Check Run Length 5 Limit Register
#define | TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
#define | TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
#define | TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
#define | TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
#define | TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
#define | TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
SCR6PC - Statistical Check Run Length 6+ Count Register
#define | TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
#define | TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
#define | TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
#define | TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
#define | TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
#define | TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
SCR6PL - Statistical Check Run Length 6+ Limit Register
#define | TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
#define | TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
#define | TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
#define | TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
#define | TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
#define | TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
ENT - Entropy Read Register
#define | TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
#define | TRNG_ENT_ENT_SHIFT (0U)
#define | TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
PKRCNT10 - Statistical Check Poker Count 1 and 0 Register
#define | TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
#define | TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
#define | TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
#define | TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
#define | TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
#define | TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
PKRCNT32 - Statistical Check Poker Count 3 and 2 Register
#define | TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
#define | TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
#define | TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
#define | TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
#define | TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
#define | TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
PKRCNT54 - Statistical Check Poker Count 5 and 4 Register
#define | TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
#define | TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
#define | TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
#define | TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
#define | TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
#define | TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
PKRCNT76 - Statistical Check Poker Count 7 and 6 Register
#define | TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
#define | TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
#define | TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
#define | TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
#define | TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
#define | TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
PKRCNT98 - Statistical Check Poker Count 9 and 8 Register
#define | TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
#define | TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
#define | TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
#define | TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
#define | TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
#define | TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
PKRCNTBA - Statistical Check Poker Count B and A Register
#define | TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
#define | TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
#define | TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
#define | TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
#define | TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
#define | TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
PKRCNTDC - Statistical Check Poker Count D and C Register
#define | TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
#define | TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
#define | TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
#define | TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
#define | TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
#define | TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
PKRCNTFE - Statistical Check Poker Count F and E Register
#define | TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
#define | TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
#define | TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
#define | TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
#define | TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
#define | TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
SEC_CFG - Security Configuration Register
#define | TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
#define | TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
#define | TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
#define | TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
#define | TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
#define | TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
#define | TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
#define | TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
#define | TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
INT_CTRL - Interrupt Control Register
#define | TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
#define | TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
#define | TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
#define | TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
#define | TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
#define | TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
#define | TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
#define | TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
#define | TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
#define | TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
#define | TRNG_INT_CTRL_UNUSED_SHIFT (3U)
#define | TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
INT_MASK - Mask Register
#define | TRNG_INT_MASK_HW_ERR_MASK (0x1U)
#define | TRNG_INT_MASK_HW_ERR_SHIFT (0U)
#define | TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
#define | TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
#define | TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
#define | TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
#define | TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
#define | TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
#define | TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
VID1 - Version ID Register (MS)
#define | TRNG_VID1_MIN_REV_MASK (0xFFU)
#define | TRNG_VID1_MIN_REV_SHIFT (0U)
#define | TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
#define | TRNG_VID1_MAJ_REV_MASK (0xFF00U)
#define | TRNG_VID1_MAJ_REV_SHIFT (8U)
#define | TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
#define | TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
#define | TRNG_VID1_IP_ID_SHIFT (16U)
#define | TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
VID2 - Version ID Register (LS)
#define | TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
#define | TRNG_VID2_CONFIG_OPT_SHIFT (0U)
#define | TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
#define | TRNG_VID2_ECO_REV_MASK (0xFF00U)
#define | TRNG_VID2_ECO_REV_SHIFT (8U)
#define | TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
#define | TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
#define | TRNG_VID2_INTG_OPT_SHIFT (16U)
#define | TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
#define | TRNG_VID2_ERA_MASK (0xFF000000U)
#define | TRNG_VID2_ERA_SHIFT (24U)
#define | TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
BASIC_SETTING - Basic Setting
#define | TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)
#define | TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)
#define | TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
#define | TSC_BASIC_SETTING_WIRE_4_5_MASK (0x10U)
#define | TSC_BASIC_SETTING_WIRE_4_5_SHIFT (4U)
#define | TSC_BASIC_SETTING_WIRE_4_5(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_WIRE_4_5_SHIFT)) & TSC_BASIC_SETTING_WIRE_4_5_MASK)
#define | TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
#define | TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
#define | TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)
PRE_CHARGE_TIME - Pre-charge Time
#define | TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)
#define | TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U)
#define | TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK)
FLOW_CONTROL - Flow Control
#define | TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)
#define | TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)
#define | TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
#define | TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)
#define | TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)
#define | TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
#define | TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)
#define | TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)
#define | TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
#define | TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)
#define | TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)
#define | TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
#define | TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)
#define | TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)
#define | TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
MEASEURE_VALUE - Measure Value
#define | TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)
#define | TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)
#define | TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)
#define | TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)
#define | TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)
#define | TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)
INT_EN - Interrupt Enable
#define | TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)
#define | TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)
#define | TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
#define | TSC_INT_EN_DETECT_INT_EN_MASK (0x10U)
#define | TSC_INT_EN_DETECT_INT_EN_SHIFT (4U)
#define | TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
#define | TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)
#define | TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)
#define | TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
INT_SIG_EN - Interrupt Signal Enable
#define | TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)
#define | TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)
#define | TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
#define | TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)
#define | TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)
#define | TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
#define | TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)
#define | TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)
#define | TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
#define | TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)
#define | TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)
#define | TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
INT_STATUS - Intterrupt Status
#define | TSC_INT_STATUS_MEASURE_MASK (0x1U)
#define | TSC_INT_STATUS_MEASURE_SHIFT (0U)
#define | TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
#define | TSC_INT_STATUS_DETECT_MASK (0x10U)
#define | TSC_INT_STATUS_DETECT_SHIFT (4U)
#define | TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
#define | TSC_INT_STATUS_VALID_MASK (0x100U)
#define | TSC_INT_STATUS_VALID_SHIFT (8U)
#define | TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
#define | TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)
#define | TSC_INT_STATUS_IDLE_SW_SHIFT (12U)
#define | TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
DEBUG_MODE - Debug Mode Register
#define | TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)
#define | TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)
#define | TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)
#define | TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)
#define | TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)
#define | TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)
#define | TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)
#define | TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)
#define | TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
#define | TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)
#define | TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)
#define | TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
#define | TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)
#define | TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)
#define | TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
#define | TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
#define | TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
#define | TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
#define | TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)
#define | TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)
#define | TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
DEBUG_MODE2 - Debug Mode Register 2
#define | TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)
#define | TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)
#define | TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
#define | TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)
#define | TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)
#define | TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)
#define | TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)
#define | TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)
#define | TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)
#define | TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
#define | TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)
#define | TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)
#define | TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)
#define | TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)
#define | TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)
#define | TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)
#define | TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
#define | TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)
#define | TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)
#define | TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)
#define | TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)
#define | TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)
#define | TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)
#define | TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
#define | TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)
#define | TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)
#define | TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)
#define | TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)
#define | TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)
#define | TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)
#define | TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
#define | TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)
#define | TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)
#define | TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)
#define | TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
#define | TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
#define | TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)
#define | TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)
#define | TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
#define | TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)
#define | TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)
#define | TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
#define | TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)
#define | TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)
#define | TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
#define | TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)
#define | TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)
#define | TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
#define | TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
#define | TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
#define | TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
#define | TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
#define | TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
#define | TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
#define | TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)
#define | TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)
#define | TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)
ID - Identification register
#define | USB_ID_ID_MASK (0x3FU)
#define | USB_ID_ID_SHIFT (0U)
#define | USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
#define | USB_ID_NID_MASK (0x3F00U)
#define | USB_ID_NID_SHIFT (8U)
#define | USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
#define | USB_ID_REVISION_MASK (0xFF0000U)
#define | USB_ID_REVISION_SHIFT (16U)
#define | USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
HWGENERAL - Hardware General
#define | USB_HWGENERAL_PHYW_MASK (0x30U)
#define | USB_HWGENERAL_PHYW_SHIFT (4U)
#define | USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
#define | USB_HWGENERAL_PHYM_MASK (0x1C0U)
#define | USB_HWGENERAL_PHYM_SHIFT (6U)
#define | USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
#define | USB_HWGENERAL_SM_MASK (0x600U)
#define | USB_HWGENERAL_SM_SHIFT (9U)
#define | USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
HWHOST - Host Hardware Parameters
#define | USB_HWHOST_HC_MASK (0x1U)
#define | USB_HWHOST_HC_SHIFT (0U)
#define | USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
#define | USB_HWHOST_NPORT_MASK (0xEU)
#define | USB_HWHOST_NPORT_SHIFT (1U)
#define | USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
HWDEVICE - Device Hardware Parameters
#define | USB_HWDEVICE_DC_MASK (0x1U)
#define | USB_HWDEVICE_DC_SHIFT (0U)
#define | USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
#define | USB_HWDEVICE_DEVEP_MASK (0x3EU)
#define | USB_HWDEVICE_DEVEP_SHIFT (1U)
#define | USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
HWTXBUF - TX Buffer Hardware Parameters
#define | USB_HWTXBUF_TXBURST_MASK (0xFFU)
#define | USB_HWTXBUF_TXBURST_SHIFT (0U)
#define | USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
#define | USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
#define | USB_HWTXBUF_TXCHANADD_SHIFT (16U)
#define | USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
HWRXBUF - RX Buffer Hardware Parameters
#define | USB_HWRXBUF_RXBURST_MASK (0xFFU)
#define | USB_HWRXBUF_RXBURST_SHIFT (0U)
#define | USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
#define | USB_HWRXBUF_RXADD_MASK (0xFF00U)
#define | USB_HWRXBUF_RXADD_SHIFT (8U)
#define | USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
GPTIMER0LD - General Purpose Timer #0 Load
#define | USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
#define | USB_GPTIMER0LD_GPTLD_SHIFT (0U)
#define | USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
GPTIMER0CTRL - General Purpose Timer #0 Controller
#define | USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
#define | USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
#define | USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
#define | USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
#define | USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
#define | USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
#define | USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
#define | USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
#define | USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
#define | USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
#define | USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
#define | USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
GPTIMER1LD - General Purpose Timer #1 Load
#define | USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
#define | USB_GPTIMER1LD_GPTLD_SHIFT (0U)
#define | USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
GPTIMER1CTRL - General Purpose Timer #1 Controller
#define | USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
#define | USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
#define | USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
#define | USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
#define | USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
#define | USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
#define | USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
#define | USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
#define | USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
#define | USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
#define | USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
#define | USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
SBUSCFG - System Bus Config
#define | USB_SBUSCFG_AHBBRST_MASK (0x7U)
#define | USB_SBUSCFG_AHBBRST_SHIFT (0U)
#define | USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
CAPLENGTH - Capability Registers Length
#define | USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
#define | USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
#define | USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
HCIVERSION - Host Controller Interface Version
#define | USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
#define | USB_HCIVERSION_HCIVERSION_SHIFT (0U)
#define | USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
HCSPARAMS - Host Controller Structural Parameters
#define | USB_HCSPARAMS_N_PORTS_MASK (0xFU)
#define | USB_HCSPARAMS_N_PORTS_SHIFT (0U)
#define | USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
#define | USB_HCSPARAMS_PPC_MASK (0x10U)
#define | USB_HCSPARAMS_PPC_SHIFT (4U)
#define | USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
#define | USB_HCSPARAMS_N_PCC_MASK (0xF00U)
#define | USB_HCSPARAMS_N_PCC_SHIFT (8U)
#define | USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
#define | USB_HCSPARAMS_N_CC_MASK (0xF000U)
#define | USB_HCSPARAMS_N_CC_SHIFT (12U)
#define | USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
#define | USB_HCSPARAMS_PI_MASK (0x10000U)
#define | USB_HCSPARAMS_PI_SHIFT (16U)
#define | USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
#define | USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
#define | USB_HCSPARAMS_N_PTT_SHIFT (20U)
#define | USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
#define | USB_HCSPARAMS_N_TT_MASK (0xF000000U)
#define | USB_HCSPARAMS_N_TT_SHIFT (24U)
#define | USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
HCCPARAMS - Host Controller Capability Parameters
#define | USB_HCCPARAMS_ADC_MASK (0x1U)
#define | USB_HCCPARAMS_ADC_SHIFT (0U)
#define | USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
#define | USB_HCCPARAMS_PFL_MASK (0x2U)
#define | USB_HCCPARAMS_PFL_SHIFT (1U)
#define | USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
#define | USB_HCCPARAMS_ASP_MASK (0x4U)
#define | USB_HCCPARAMS_ASP_SHIFT (2U)
#define | USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
#define | USB_HCCPARAMS_IST_MASK (0xF0U)
#define | USB_HCCPARAMS_IST_SHIFT (4U)
#define | USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
#define | USB_HCCPARAMS_EECP_MASK (0xFF00U)
#define | USB_HCCPARAMS_EECP_SHIFT (8U)
#define | USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
DCIVERSION - Device Controller Interface Version
#define | USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
#define | USB_DCIVERSION_DCIVERSION_SHIFT (0U)
#define | USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
DCCPARAMS - Device Controller Capability Parameters
#define | USB_DCCPARAMS_DEN_MASK (0x1FU)
#define | USB_DCCPARAMS_DEN_SHIFT (0U)
#define | USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
#define | USB_DCCPARAMS_DC_MASK (0x80U)
#define | USB_DCCPARAMS_DC_SHIFT (7U)
#define | USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
#define | USB_DCCPARAMS_HC_MASK (0x100U)
#define | USB_DCCPARAMS_HC_SHIFT (8U)
#define | USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
USBCMD - USB Command Register
#define | USB_USBCMD_RS_MASK (0x1U)
#define | USB_USBCMD_RS_SHIFT (0U)
#define | USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
#define | USB_USBCMD_RST_MASK (0x2U)
#define | USB_USBCMD_RST_SHIFT (1U)
#define | USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
#define | USB_USBCMD_FS_1_MASK (0xCU)
#define | USB_USBCMD_FS_1_SHIFT (2U)
#define | USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
#define | USB_USBCMD_PSE_MASK (0x10U)
#define | USB_USBCMD_PSE_SHIFT (4U)
#define | USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
#define | USB_USBCMD_ASE_MASK (0x20U)
#define | USB_USBCMD_ASE_SHIFT (5U)
#define | USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
#define | USB_USBCMD_IAA_MASK (0x40U)
#define | USB_USBCMD_IAA_SHIFT (6U)
#define | USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
#define | USB_USBCMD_ASP_MASK (0x300U)
#define | USB_USBCMD_ASP_SHIFT (8U)
#define | USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
#define | USB_USBCMD_ASPE_MASK (0x800U)
#define | USB_USBCMD_ASPE_SHIFT (11U)
#define | USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
#define | USB_USBCMD_ATDTW_MASK (0x1000U)
#define | USB_USBCMD_ATDTW_SHIFT (12U)
#define | USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
#define | USB_USBCMD_SUTW_MASK (0x2000U)
#define | USB_USBCMD_SUTW_SHIFT (13U)
#define | USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
#define | USB_USBCMD_FS_2_MASK (0x8000U)
#define | USB_USBCMD_FS_2_SHIFT (15U)
#define | USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
#define | USB_USBCMD_ITC_MASK (0xFF0000U)
#define | USB_USBCMD_ITC_SHIFT (16U)
#define | USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
USBSTS - USB Status Register
#define | USB_USBSTS_UI_MASK (0x1U)
#define | USB_USBSTS_UI_SHIFT (0U)
#define | USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
#define | USB_USBSTS_UEI_MASK (0x2U)
#define | USB_USBSTS_UEI_SHIFT (1U)
#define | USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
#define | USB_USBSTS_PCI_MASK (0x4U)
#define | USB_USBSTS_PCI_SHIFT (2U)
#define | USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
#define | USB_USBSTS_FRI_MASK (0x8U)
#define | USB_USBSTS_FRI_SHIFT (3U)
#define | USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
#define | USB_USBSTS_SEI_MASK (0x10U)
#define | USB_USBSTS_SEI_SHIFT (4U)
#define | USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
#define | USB_USBSTS_AAI_MASK (0x20U)
#define | USB_USBSTS_AAI_SHIFT (5U)
#define | USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
#define | USB_USBSTS_URI_MASK (0x40U)
#define | USB_USBSTS_URI_SHIFT (6U)
#define | USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
#define | USB_USBSTS_SRI_MASK (0x80U)
#define | USB_USBSTS_SRI_SHIFT (7U)
#define | USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
#define | USB_USBSTS_SLI_MASK (0x100U)
#define | USB_USBSTS_SLI_SHIFT (8U)
#define | USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
#define | USB_USBSTS_ULPII_MASK (0x400U)
#define | USB_USBSTS_ULPII_SHIFT (10U)
#define | USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
#define | USB_USBSTS_HCH_MASK (0x1000U)
#define | USB_USBSTS_HCH_SHIFT (12U)
#define | USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
#define | USB_USBSTS_RCL_MASK (0x2000U)
#define | USB_USBSTS_RCL_SHIFT (13U)
#define | USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
#define | USB_USBSTS_PS_MASK (0x4000U)
#define | USB_USBSTS_PS_SHIFT (14U)
#define | USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
#define | USB_USBSTS_AS_MASK (0x8000U)
#define | USB_USBSTS_AS_SHIFT (15U)
#define | USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
#define | USB_USBSTS_NAKI_MASK (0x10000U)
#define | USB_USBSTS_NAKI_SHIFT (16U)
#define | USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
#define | USB_USBSTS_TI0_MASK (0x1000000U)
#define | USB_USBSTS_TI0_SHIFT (24U)
#define | USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
#define | USB_USBSTS_TI1_MASK (0x2000000U)
#define | USB_USBSTS_TI1_SHIFT (25U)
#define | USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
USBINTR - Interrupt Enable Register
#define | USB_USBINTR_UE_MASK (0x1U)
#define | USB_USBINTR_UE_SHIFT (0U)
#define | USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
#define | USB_USBINTR_UEE_MASK (0x2U)
#define | USB_USBINTR_UEE_SHIFT (1U)
#define | USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
#define | USB_USBINTR_PCE_MASK (0x4U)
#define | USB_USBINTR_PCE_SHIFT (2U)
#define | USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
#define | USB_USBINTR_FRE_MASK (0x8U)
#define | USB_USBINTR_FRE_SHIFT (3U)
#define | USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
#define | USB_USBINTR_SEE_MASK (0x10U)
#define | USB_USBINTR_SEE_SHIFT (4U)
#define | USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
#define | USB_USBINTR_AAE_MASK (0x20U)
#define | USB_USBINTR_AAE_SHIFT (5U)
#define | USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
#define | USB_USBINTR_URE_MASK (0x40U)
#define | USB_USBINTR_URE_SHIFT (6U)
#define | USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
#define | USB_USBINTR_SRE_MASK (0x80U)
#define | USB_USBINTR_SRE_SHIFT (7U)
#define | USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
#define | USB_USBINTR_SLE_MASK (0x100U)
#define | USB_USBINTR_SLE_SHIFT (8U)
#define | USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
#define | USB_USBINTR_ULPIE_MASK (0x400U)
#define | USB_USBINTR_ULPIE_SHIFT (10U)
#define | USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
#define | USB_USBINTR_NAKE_MASK (0x10000U)
#define | USB_USBINTR_NAKE_SHIFT (16U)
#define | USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
#define | USB_USBINTR_UAIE_MASK (0x40000U)
#define | USB_USBINTR_UAIE_SHIFT (18U)
#define | USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
#define | USB_USBINTR_UPIE_MASK (0x80000U)
#define | USB_USBINTR_UPIE_SHIFT (19U)
#define | USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
#define | USB_USBINTR_TIE0_MASK (0x1000000U)
#define | USB_USBINTR_TIE0_SHIFT (24U)
#define | USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
#define | USB_USBINTR_TIE1_MASK (0x2000000U)
#define | USB_USBINTR_TIE1_SHIFT (25U)
#define | USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
FRINDEX - USB Frame Index
#define | USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
#define | USB_FRINDEX_FRINDEX_SHIFT (0U)
#define | USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
DEVICEADDR - Device Address
#define | USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
#define | USB_DEVICEADDR_USBADRA_SHIFT (24U)
#define | USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
#define | USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
#define | USB_DEVICEADDR_USBADR_SHIFT (25U)
#define | USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
PERIODICLISTBASE - Frame List Base Address
#define | USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
#define | USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
#define | USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
ASYNCLISTADDR - Next Asynch. Address
#define | USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
#define | USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
#define | USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
ENDPTLISTADDR - Endpoint List Address
#define | USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
#define | USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
#define | USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
BURSTSIZE - Programmable Burst Size
#define | USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
#define | USB_BURSTSIZE_RXPBURST_SHIFT (0U)
#define | USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
#define | USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
#define | USB_BURSTSIZE_TXPBURST_SHIFT (8U)
#define | USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
TXFILLTUNING - TX FIFO Fill Tuning
#define | USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
#define | USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
#define | USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
#define | USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
#define | USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
#define | USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
#define | USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
#define | USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
#define | USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
ENDPTNAK - Endpoint NAK
#define | USB_ENDPTNAK_EPRN_MASK (0xFFU)
#define | USB_ENDPTNAK_EPRN_SHIFT (0U)
#define | USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
#define | USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
#define | USB_ENDPTNAK_EPTN_SHIFT (16U)
#define | USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
ENDPTNAKEN - Endpoint NAK Enable
#define | USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
#define | USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
#define | USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
#define | USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
#define | USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
#define | USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
CONFIGFLAG - Configure Flag Register
#define | USB_CONFIGFLAG_CF_MASK (0x1U)
#define | USB_CONFIGFLAG_CF_SHIFT (0U)
#define | USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
PORTSC1 - Port Status & Control
#define | USB_PORTSC1_CCS_MASK (0x1U)
#define | USB_PORTSC1_CCS_SHIFT (0U)
#define | USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
#define | USB_PORTSC1_CSC_MASK (0x2U)
#define | USB_PORTSC1_CSC_SHIFT (1U)
#define | USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
#define | USB_PORTSC1_PE_MASK (0x4U)
#define | USB_PORTSC1_PE_SHIFT (2U)
#define | USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
#define | USB_PORTSC1_PEC_MASK (0x8U)
#define | USB_PORTSC1_PEC_SHIFT (3U)
#define | USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
#define | USB_PORTSC1_OCA_MASK (0x10U)
#define | USB_PORTSC1_OCA_SHIFT (4U)
#define | USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
#define | USB_PORTSC1_OCC_MASK (0x20U)
#define | USB_PORTSC1_OCC_SHIFT (5U)
#define | USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
#define | USB_PORTSC1_FPR_MASK (0x40U)
#define | USB_PORTSC1_FPR_SHIFT (6U)
#define | USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
#define | USB_PORTSC1_SUSP_MASK (0x80U)
#define | USB_PORTSC1_SUSP_SHIFT (7U)
#define | USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
#define | USB_PORTSC1_PR_MASK (0x100U)
#define | USB_PORTSC1_PR_SHIFT (8U)
#define | USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
#define | USB_PORTSC1_HSP_MASK (0x200U)
#define | USB_PORTSC1_HSP_SHIFT (9U)
#define | USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
#define | USB_PORTSC1_LS_MASK (0xC00U)
#define | USB_PORTSC1_LS_SHIFT (10U)
#define | USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
#define | USB_PORTSC1_PP_MASK (0x1000U)
#define | USB_PORTSC1_PP_SHIFT (12U)
#define | USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
#define | USB_PORTSC1_PO_MASK (0x2000U)
#define | USB_PORTSC1_PO_SHIFT (13U)
#define | USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
#define | USB_PORTSC1_PIC_MASK (0xC000U)
#define | USB_PORTSC1_PIC_SHIFT (14U)
#define | USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
#define | USB_PORTSC1_PTC_MASK (0xF0000U)
#define | USB_PORTSC1_PTC_SHIFT (16U)
#define | USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
#define | USB_PORTSC1_WKCN_MASK (0x100000U)
#define | USB_PORTSC1_WKCN_SHIFT (20U)
#define | USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
#define | USB_PORTSC1_WKDC_MASK (0x200000U)
#define | USB_PORTSC1_WKDC_SHIFT (21U)
#define | USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
#define | USB_PORTSC1_WKOC_MASK (0x400000U)
#define | USB_PORTSC1_WKOC_SHIFT (22U)
#define | USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
#define | USB_PORTSC1_PHCD_MASK (0x800000U)
#define | USB_PORTSC1_PHCD_SHIFT (23U)
#define | USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
#define | USB_PORTSC1_PFSC_MASK (0x1000000U)
#define | USB_PORTSC1_PFSC_SHIFT (24U)
#define | USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
#define | USB_PORTSC1_PTS_2_MASK (0x2000000U)
#define | USB_PORTSC1_PTS_2_SHIFT (25U)
#define | USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
#define | USB_PORTSC1_PSPD_MASK (0xC000000U)
#define | USB_PORTSC1_PSPD_SHIFT (26U)
#define | USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
#define | USB_PORTSC1_PTW_MASK (0x10000000U)
#define | USB_PORTSC1_PTW_SHIFT (28U)
#define | USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
#define | USB_PORTSC1_STS_MASK (0x20000000U)
#define | USB_PORTSC1_STS_SHIFT (29U)
#define | USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
#define | USB_PORTSC1_PTS_1_MASK (0xC0000000U)
#define | USB_PORTSC1_PTS_1_SHIFT (30U)
#define | USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
OTGSC - On-The-Go Status & control
#define | USB_OTGSC_VD_MASK (0x1U)
#define | USB_OTGSC_VD_SHIFT (0U)
#define | USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
#define | USB_OTGSC_VC_MASK (0x2U)
#define | USB_OTGSC_VC_SHIFT (1U)
#define | USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
#define | USB_OTGSC_OT_MASK (0x8U)
#define | USB_OTGSC_OT_SHIFT (3U)
#define | USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
#define | USB_OTGSC_DP_MASK (0x10U)
#define | USB_OTGSC_DP_SHIFT (4U)
#define | USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
#define | USB_OTGSC_IDPU_MASK (0x20U)
#define | USB_OTGSC_IDPU_SHIFT (5U)
#define | USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
#define | USB_OTGSC_ID_MASK (0x100U)
#define | USB_OTGSC_ID_SHIFT (8U)
#define | USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
#define | USB_OTGSC_AVV_MASK (0x200U)
#define | USB_OTGSC_AVV_SHIFT (9U)
#define | USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
#define | USB_OTGSC_ASV_MASK (0x400U)
#define | USB_OTGSC_ASV_SHIFT (10U)
#define | USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
#define | USB_OTGSC_BSV_MASK (0x800U)
#define | USB_OTGSC_BSV_SHIFT (11U)
#define | USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
#define | USB_OTGSC_BSE_MASK (0x1000U)
#define | USB_OTGSC_BSE_SHIFT (12U)
#define | USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
#define | USB_OTGSC_TOG_1MS_MASK (0x2000U)
#define | USB_OTGSC_TOG_1MS_SHIFT (13U)
#define | USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
#define | USB_OTGSC_DPS_MASK (0x4000U)
#define | USB_OTGSC_DPS_SHIFT (14U)
#define | USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
#define | USB_OTGSC_IDIS_MASK (0x10000U)
#define | USB_OTGSC_IDIS_SHIFT (16U)
#define | USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
#define | USB_OTGSC_AVVIS_MASK (0x20000U)
#define | USB_OTGSC_AVVIS_SHIFT (17U)
#define | USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
#define | USB_OTGSC_ASVIS_MASK (0x40000U)
#define | USB_OTGSC_ASVIS_SHIFT (18U)
#define | USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
#define | USB_OTGSC_BSVIS_MASK (0x80000U)
#define | USB_OTGSC_BSVIS_SHIFT (19U)
#define | USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
#define | USB_OTGSC_BSEIS_MASK (0x100000U)
#define | USB_OTGSC_BSEIS_SHIFT (20U)
#define | USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
#define | USB_OTGSC_STATUS_1MS_MASK (0x200000U)
#define | USB_OTGSC_STATUS_1MS_SHIFT (21U)
#define | USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
#define | USB_OTGSC_DPIS_MASK (0x400000U)
#define | USB_OTGSC_DPIS_SHIFT (22U)
#define | USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
#define | USB_OTGSC_IDIE_MASK (0x1000000U)
#define | USB_OTGSC_IDIE_SHIFT (24U)
#define | USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
#define | USB_OTGSC_AVVIE_MASK (0x2000000U)
#define | USB_OTGSC_AVVIE_SHIFT (25U)
#define | USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
#define | USB_OTGSC_ASVIE_MASK (0x4000000U)
#define | USB_OTGSC_ASVIE_SHIFT (26U)
#define | USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
#define | USB_OTGSC_BSVIE_MASK (0x8000000U)
#define | USB_OTGSC_BSVIE_SHIFT (27U)
#define | USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
#define | USB_OTGSC_BSEIE_MASK (0x10000000U)
#define | USB_OTGSC_BSEIE_SHIFT (28U)
#define | USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
#define | USB_OTGSC_EN_1MS_MASK (0x20000000U)
#define | USB_OTGSC_EN_1MS_SHIFT (29U)
#define | USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
#define | USB_OTGSC_DPIE_MASK (0x40000000U)
#define | USB_OTGSC_DPIE_SHIFT (30U)
#define | USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
USBMODE - USB Device Mode
#define | USB_USBMODE_CM_MASK (0x3U)
#define | USB_USBMODE_CM_SHIFT (0U)
#define | USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
#define | USB_USBMODE_ES_MASK (0x4U)
#define | USB_USBMODE_ES_SHIFT (2U)
#define | USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
#define | USB_USBMODE_SLOM_MASK (0x8U)
#define | USB_USBMODE_SLOM_SHIFT (3U)
#define | USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
#define | USB_USBMODE_SDIS_MASK (0x10U)
#define | USB_USBMODE_SDIS_SHIFT (4U)
#define | USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
ENDPTSETUPSTAT - Endpoint Setup Status
#define | USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
#define | USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
#define | USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
ENDPTPRIME - Endpoint Prime
#define | USB_ENDPTPRIME_PERB_MASK (0xFFU)
#define | USB_ENDPTPRIME_PERB_SHIFT (0U)
#define | USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
#define | USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
#define | USB_ENDPTPRIME_PETB_SHIFT (16U)
#define | USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
ENDPTFLUSH - Endpoint Flush
#define | USB_ENDPTFLUSH_FERB_MASK (0xFFU)
#define | USB_ENDPTFLUSH_FERB_SHIFT (0U)
#define | USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
#define | USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
#define | USB_ENDPTFLUSH_FETB_SHIFT (16U)
#define | USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
ENDPTSTAT - Endpoint Status
#define | USB_ENDPTSTAT_ERBR_MASK (0xFFU)
#define | USB_ENDPTSTAT_ERBR_SHIFT (0U)
#define | USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
#define | USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
#define | USB_ENDPTSTAT_ETBR_SHIFT (16U)
#define | USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
ENDPTCOMPLETE - Endpoint Complete
#define | USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
#define | USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
#define | USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
#define | USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
#define | USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
#define | USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
ENDPTCTRL0 - Endpoint Control0
#define | USB_ENDPTCTRL0_RXS_MASK (0x1U)
#define | USB_ENDPTCTRL0_RXS_SHIFT (0U)
#define | USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
#define | USB_ENDPTCTRL0_RXT_MASK (0xCU)
#define | USB_ENDPTCTRL0_RXT_SHIFT (2U)
#define | USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
#define | USB_ENDPTCTRL0_RXE_MASK (0x80U)
#define | USB_ENDPTCTRL0_RXE_SHIFT (7U)
#define | USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
#define | USB_ENDPTCTRL0_TXS_MASK (0x10000U)
#define | USB_ENDPTCTRL0_TXS_SHIFT (16U)
#define | USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
#define | USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
#define | USB_ENDPTCTRL0_TXT_SHIFT (18U)
#define | USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
#define | USB_ENDPTCTRL0_TXE_MASK (0x800000U)
#define | USB_ENDPTCTRL0_TXE_SHIFT (23U)
#define | USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
ENDPTCTRL - Endpoint Control 1..Endpoint Control 7
#define | USB_ENDPTCTRL_RXS_MASK (0x1U)
#define | USB_ENDPTCTRL_RXS_SHIFT (0U)
#define | USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
#define | USB_ENDPTCTRL_RXD_MASK (0x2U)
#define | USB_ENDPTCTRL_RXD_SHIFT (1U)
#define | USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
#define | USB_ENDPTCTRL_RXT_MASK (0xCU)
#define | USB_ENDPTCTRL_RXT_SHIFT (2U)
#define | USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
#define | USB_ENDPTCTRL_RXI_MASK (0x20U)
#define | USB_ENDPTCTRL_RXI_SHIFT (5U)
#define | USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
#define | USB_ENDPTCTRL_RXR_MASK (0x40U)
#define | USB_ENDPTCTRL_RXR_SHIFT (6U)
#define | USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
#define | USB_ENDPTCTRL_RXE_MASK (0x80U)
#define | USB_ENDPTCTRL_RXE_SHIFT (7U)
#define | USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
#define | USB_ENDPTCTRL_TXS_MASK (0x10000U)
#define | USB_ENDPTCTRL_TXS_SHIFT (16U)
#define | USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
#define | USB_ENDPTCTRL_TXD_MASK (0x20000U)
#define | USB_ENDPTCTRL_TXD_SHIFT (17U)
#define | USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
#define | USB_ENDPTCTRL_TXT_MASK (0xC0000U)
#define | USB_ENDPTCTRL_TXT_SHIFT (18U)
#define | USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
#define | USB_ENDPTCTRL_TXI_MASK (0x200000U)
#define | USB_ENDPTCTRL_TXI_SHIFT (21U)
#define | USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
#define | USB_ENDPTCTRL_TXR_MASK (0x400000U)
#define | USB_ENDPTCTRL_TXR_SHIFT (22U)
#define | USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
#define | USB_ENDPTCTRL_TXE_MASK (0x800000U)
#define | USB_ENDPTCTRL_TXE_SHIFT (23U)
#define | USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
#define | USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)
#define | USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)
#define | USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
#define | USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)
#define | USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)
#define | USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)
#define | USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
#define | USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)
#define | USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)
#define | USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
#define | USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)
#define | USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)
#define | USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
#define | USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)
#define | USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)
#define | USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
#define | USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)
#define | USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)
#define | USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register
#define | USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
#define | USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
#define | USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)
PWD - USB PHY Power-Down Register
#define | USBPHY_PWD_RSVD0_MASK (0x3FFU)
#define | USBPHY_PWD_RSVD0_SHIFT (0U)
#define | USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
#define | USBPHY_PWD_TXPWDFS_MASK (0x400U)
#define | USBPHY_PWD_TXPWDFS_SHIFT (10U)
#define | USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
#define | USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
#define | USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
#define | USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
#define | USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
#define | USBPHY_PWD_TXPWDV2I_SHIFT (12U)
#define | USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
#define | USBPHY_PWD_RSVD1_MASK (0x1E000U)
#define | USBPHY_PWD_RSVD1_SHIFT (13U)
#define | USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
#define | USBPHY_PWD_RXPWDENV_MASK (0x20000U)
#define | USBPHY_PWD_RXPWDENV_SHIFT (17U)
#define | USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
#define | USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
#define | USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
#define | USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
#define | USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
#define | USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
#define | USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
#define | USBPHY_PWD_RXPWDRX_MASK (0x100000U)
#define | USBPHY_PWD_RXPWDRX_SHIFT (20U)
#define | USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
#define | USBPHY_PWD_RSVD2_MASK (0xFFE00000U)
#define | USBPHY_PWD_RSVD2_SHIFT (21U)
#define | USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
PWD_SET - USB PHY Power-Down Register
#define | USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)
#define | USBPHY_PWD_SET_RSVD0_SHIFT (0U)
#define | USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
#define | USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
#define | USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
#define | USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
#define | USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
#define | USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
#define | USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
#define | USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
#define | USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
#define | USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
#define | USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)
#define | USBPHY_PWD_SET_RSVD1_SHIFT (13U)
#define | USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
#define | USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
#define | USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
#define | USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
#define | USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
#define | USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
#define | USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
#define | USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
#define | USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
#define | USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
#define | USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
#define | USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
#define | USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
#define | USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)
#define | USBPHY_PWD_SET_RSVD2_SHIFT (21U)
#define | USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
PWD_CLR - USB PHY Power-Down Register
#define | USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)
#define | USBPHY_PWD_CLR_RSVD0_SHIFT (0U)
#define | USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
#define | USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
#define | USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
#define | USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
#define | USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
#define | USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
#define | USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
#define | USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
#define | USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
#define | USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
#define | USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)
#define | USBPHY_PWD_CLR_RSVD1_SHIFT (13U)
#define | USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
#define | USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
#define | USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
#define | USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
#define | USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
#define | USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
#define | USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
#define | USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
#define | USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
#define | USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
#define | USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
#define | USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
#define | USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
#define | USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)
#define | USBPHY_PWD_CLR_RSVD2_SHIFT (21U)
#define | USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
PWD_TOG - USB PHY Power-Down Register
#define | USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)
#define | USBPHY_PWD_TOG_RSVD0_SHIFT (0U)
#define | USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
#define | USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
#define | USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
#define | USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
#define | USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
#define | USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
#define | USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
#define | USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
#define | USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
#define | USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
#define | USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)
#define | USBPHY_PWD_TOG_RSVD1_SHIFT (13U)
#define | USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
#define | USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
#define | USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
#define | USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
#define | USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
#define | USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
#define | USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
#define | USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
#define | USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
#define | USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
#define | USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
#define | USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
#define | USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
#define | USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)
#define | USBPHY_PWD_TOG_RSVD2_SHIFT (21U)
#define | USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
TX - USB PHY Transmitter Control Register
#define | USBPHY_TX_D_CAL_MASK (0xFU)
#define | USBPHY_TX_D_CAL_SHIFT (0U)
#define | USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
#define | USBPHY_TX_RSVD0_MASK (0xF0U)
#define | USBPHY_TX_RSVD0_SHIFT (4U)
#define | USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
#define | USBPHY_TX_TXCAL45DN_MASK (0xF00U)
#define | USBPHY_TX_TXCAL45DN_SHIFT (8U)
#define | USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
#define | USBPHY_TX_RSVD1_MASK (0xF000U)
#define | USBPHY_TX_RSVD1_SHIFT (12U)
#define | USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
#define | USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
#define | USBPHY_TX_TXCAL45DP_SHIFT (16U)
#define | USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
#define | USBPHY_TX_RSVD2_MASK (0x3F00000U)
#define | USBPHY_TX_RSVD2_SHIFT (20U)
#define | USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
#define | USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
#define | USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
#define | USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
#define | USBPHY_TX_RSVD5_MASK (0xE0000000U)
#define | USBPHY_TX_RSVD5_SHIFT (29U)
#define | USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
TX_SET - USB PHY Transmitter Control Register
#define | USBPHY_TX_SET_D_CAL_MASK (0xFU)
#define | USBPHY_TX_SET_D_CAL_SHIFT (0U)
#define | USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
#define | USBPHY_TX_SET_RSVD0_MASK (0xF0U)
#define | USBPHY_TX_SET_RSVD0_SHIFT (4U)
#define | USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
#define | USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
#define | USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
#define | USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
#define | USBPHY_TX_SET_RSVD1_MASK (0xF000U)
#define | USBPHY_TX_SET_RSVD1_SHIFT (12U)
#define | USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
#define | USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
#define | USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
#define | USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
#define | USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)
#define | USBPHY_TX_SET_RSVD2_SHIFT (20U)
#define | USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
#define | USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
#define | USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
#define | USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
#define | USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)
#define | USBPHY_TX_SET_RSVD5_SHIFT (29U)
#define | USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
TX_CLR - USB PHY Transmitter Control Register
#define | USBPHY_TX_CLR_D_CAL_MASK (0xFU)
#define | USBPHY_TX_CLR_D_CAL_SHIFT (0U)
#define | USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
#define | USBPHY_TX_CLR_RSVD0_MASK (0xF0U)
#define | USBPHY_TX_CLR_RSVD0_SHIFT (4U)
#define | USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
#define | USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
#define | USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
#define | USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
#define | USBPHY_TX_CLR_RSVD1_MASK (0xF000U)
#define | USBPHY_TX_CLR_RSVD1_SHIFT (12U)
#define | USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
#define | USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
#define | USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
#define | USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
#define | USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)
#define | USBPHY_TX_CLR_RSVD2_SHIFT (20U)
#define | USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
#define | USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
#define | USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
#define | USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
#define | USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)
#define | USBPHY_TX_CLR_RSVD5_SHIFT (29U)
#define | USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
TX_TOG - USB PHY Transmitter Control Register
#define | USBPHY_TX_TOG_D_CAL_MASK (0xFU)
#define | USBPHY_TX_TOG_D_CAL_SHIFT (0U)
#define | USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
#define | USBPHY_TX_TOG_RSVD0_MASK (0xF0U)
#define | USBPHY_TX_TOG_RSVD0_SHIFT (4U)
#define | USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
#define | USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
#define | USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
#define | USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
#define | USBPHY_TX_TOG_RSVD1_MASK (0xF000U)
#define | USBPHY_TX_TOG_RSVD1_SHIFT (12U)
#define | USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
#define | USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
#define | USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
#define | USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
#define | USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)
#define | USBPHY_TX_TOG_RSVD2_SHIFT (20U)
#define | USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
#define | USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
#define | USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
#define | USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
#define | USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)
#define | USBPHY_TX_TOG_RSVD5_SHIFT (29U)
#define | USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
RX - USB PHY Receiver Control Register
#define | USBPHY_RX_ENVADJ_MASK (0x7U)
#define | USBPHY_RX_ENVADJ_SHIFT (0U)
#define | USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
#define | USBPHY_RX_RSVD0_MASK (0x8U)
#define | USBPHY_RX_RSVD0_SHIFT (3U)
#define | USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
#define | USBPHY_RX_DISCONADJ_MASK (0x70U)
#define | USBPHY_RX_DISCONADJ_SHIFT (4U)
#define | USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
#define | USBPHY_RX_RSVD1_MASK (0x3FFF80U)
#define | USBPHY_RX_RSVD1_SHIFT (7U)
#define | USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
#define | USBPHY_RX_RXDBYPASS_MASK (0x400000U)
#define | USBPHY_RX_RXDBYPASS_SHIFT (22U)
#define | USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
#define | USBPHY_RX_RSVD2_MASK (0xFF800000U)
#define | USBPHY_RX_RSVD2_SHIFT (23U)
#define | USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
RX_SET - USB PHY Receiver Control Register
#define | USBPHY_RX_SET_ENVADJ_MASK (0x7U)
#define | USBPHY_RX_SET_ENVADJ_SHIFT (0U)
#define | USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
#define | USBPHY_RX_SET_RSVD0_MASK (0x8U)
#define | USBPHY_RX_SET_RSVD0_SHIFT (3U)
#define | USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
#define | USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
#define | USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
#define | USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
#define | USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)
#define | USBPHY_RX_SET_RSVD1_SHIFT (7U)
#define | USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
#define | USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
#define | USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
#define | USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
#define | USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)
#define | USBPHY_RX_SET_RSVD2_SHIFT (23U)
#define | USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
RX_CLR - USB PHY Receiver Control Register
#define | USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
#define | USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
#define | USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
#define | USBPHY_RX_CLR_RSVD0_MASK (0x8U)
#define | USBPHY_RX_CLR_RSVD0_SHIFT (3U)
#define | USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
#define | USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
#define | USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
#define | USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
#define | USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)
#define | USBPHY_RX_CLR_RSVD1_SHIFT (7U)
#define | USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
#define | USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
#define | USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
#define | USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
#define | USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)
#define | USBPHY_RX_CLR_RSVD2_SHIFT (23U)
#define | USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
RX_TOG - USB PHY Receiver Control Register
#define | USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
#define | USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
#define | USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
#define | USBPHY_RX_TOG_RSVD0_MASK (0x8U)
#define | USBPHY_RX_TOG_RSVD0_SHIFT (3U)
#define | USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
#define | USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
#define | USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
#define | USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
#define | USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)
#define | USBPHY_RX_TOG_RSVD1_SHIFT (7U)
#define | USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
#define | USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
#define | USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
#define | USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
#define | USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)
#define | USBPHY_RX_TOG_RSVD2_SHIFT (23U)
#define | USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
CTRL - USB PHY General Control Register
#define | USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define | USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
#define | USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
#define | USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
#define | USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
#define | USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
#define | USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
#define | USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
#define | USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
#define | USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define | USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
#define | USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
#define | USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
#define | USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
#define | USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
#define | USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
#define | USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
#define | USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
#define | USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
#define | USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
#define | USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
#define | USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
#define | USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
#define | USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
#define | USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
#define | USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
#define | USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
#define | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
#define | USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
#define | USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
#define | USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
#define | USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
#define | USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
#define | USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
#define | USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
#define | USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
#define | USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
#define | USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
#define | USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
#define | USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)
#define | USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)
#define | USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
#define | USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
#define | USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
#define | USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
#define | USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
#define | USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
#define | USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
#define | USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
#define | USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
#define | USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
#define | USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
#define | USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
#define | USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
#define | USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)
#define | USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)
#define | USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
#define | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define | USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
#define | USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
#define | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
#define | USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
#define | USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
#define | USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
#define | USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
#define | USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
#define | USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
#define | USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
#define | USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
#define | USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
#define | USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
#define | USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
#define | USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
#define | USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
#define | USBPHY_CTRL_RSVD1_MASK (0x6000000U)
#define | USBPHY_CTRL_RSVD1_SHIFT (25U)
#define | USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
#define | USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
#define | USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
#define | USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
#define | USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define | USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
#define | USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
#define | USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
#define | USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
#define | USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
#define | USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
#define | USBPHY_CTRL_CLKGATE_SHIFT (30U)
#define | USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
#define | USBPHY_CTRL_SFTRST_MASK (0x80000000U)
#define | USBPHY_CTRL_SFTRST_SHIFT (31U)
#define | USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
CTRL_SET - USB PHY General Control Register
#define | USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define | USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
#define | USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
#define | USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
#define | USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
#define | USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
#define | USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
#define | USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
#define | USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
#define | USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define | USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
#define | USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
#define | USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
#define | USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
#define | USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
#define | USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
#define | USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
#define | USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
#define | USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
#define | USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
#define | USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
#define | USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
#define | USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
#define | USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
#define | USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
#define | USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
#define | USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
#define | USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
#define | USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
#define | USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
#define | USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
#define | USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
#define | USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
#define | USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
#define | USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
#define | USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
#define | USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
#define | USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
#define | USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
#define | USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)
#define | USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)
#define | USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
#define | USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
#define | USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
#define | USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
#define | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
#define | USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
#define | USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
#define | USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
#define | USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
#define | USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
#define | USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
#define | USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
#define | USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
#define | USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)
#define | USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)
#define | USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
#define | USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define | USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
#define | USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
#define | USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define | USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
#define | USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
#define | USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
#define | USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
#define | USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
#define | USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
#define | USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
#define | USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
#define | USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
#define | USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
#define | USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
#define | USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
#define | USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
#define | USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
#define | USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)
#define | USBPHY_CTRL_SET_RSVD1_SHIFT (25U)
#define | USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
#define | USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
#define | USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
#define | USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
#define | USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define | USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
#define | USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
#define | USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
#define | USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
#define | USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
#define | USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define | USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
#define | USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
#define | USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
#define | USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
#define | USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
CTRL_CLR - USB PHY General Control Register
#define | USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define | USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
#define | USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
#define | USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
#define | USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
#define | USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
#define | USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
#define | USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
#define | USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
#define | USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define | USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
#define | USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
#define | USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
#define | USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
#define | USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
#define | USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
#define | USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
#define | USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
#define | USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
#define | USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
#define | USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
#define | USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
#define | USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
#define | USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
#define | USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
#define | USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
#define | USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
#define | USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
#define | USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
#define | USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
#define | USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
#define | USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
#define | USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
#define | USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
#define | USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
#define | USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
#define | USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
#define | USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
#define | USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
#define | USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)
#define | USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)
#define | USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
#define | USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
#define | USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
#define | USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
#define | USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
#define | USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
#define | USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
#define | USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
#define | USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
#define | USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
#define | USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
#define | USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
#define | USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
#define | USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)
#define | USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)
#define | USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
#define | USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define | USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
#define | USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
#define | USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define | USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
#define | USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
#define | USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
#define | USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
#define | USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
#define | USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
#define | USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
#define | USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
#define | USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
#define | USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
#define | USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
#define | USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
#define | USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
#define | USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
#define | USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)
#define | USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)
#define | USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
#define | USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
#define | USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
#define | USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
#define | USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define | USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
#define | USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
#define | USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
#define | USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
#define | USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
#define | USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define | USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
#define | USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
#define | USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define | USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
#define | USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
CTRL_TOG - USB PHY General Control Register
#define | USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define | USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
#define | USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
#define | USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
#define | USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
#define | USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
#define | USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
#define | USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
#define | USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
#define | USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define | USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
#define | USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
#define | USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
#define | USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
#define | USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
#define | USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
#define | USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
#define | USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
#define | USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
#define | USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
#define | USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
#define | USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
#define | USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
#define | USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
#define | USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
#define | USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
#define | USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
#define | USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
#define | USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
#define | USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
#define | USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
#define | USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
#define | USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
#define | USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
#define | USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
#define | USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
#define | USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
#define | USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
#define | USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
#define | USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)
#define | USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)
#define | USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
#define | USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
#define | USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
#define | USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
#define | USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
#define | USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
#define | USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
#define | USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
#define | USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
#define | USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
#define | USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
#define | USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
#define | USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
#define | USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)
#define | USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)
#define | USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
#define | USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define | USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
#define | USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
#define | USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define | USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
#define | USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
#define | USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
#define | USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
#define | USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
#define | USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
#define | USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
#define | USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
#define | USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
#define | USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
#define | USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
#define | USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
#define | USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
#define | USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
#define | USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)
#define | USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)
#define | USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
#define | USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
#define | USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
#define | USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
#define | USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define | USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
#define | USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
#define | USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
#define | USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
#define | USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
#define | USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define | USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
#define | USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
#define | USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define | USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
#define | USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
STATUS - USB PHY Status Register
#define | USBPHY_STATUS_RSVD0_MASK (0x7U)
#define | USBPHY_STATUS_RSVD0_SHIFT (0U)
#define | USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
#define | USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
#define | USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
#define | USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
#define | USBPHY_STATUS_RSVD1_MASK (0x30U)
#define | USBPHY_STATUS_RSVD1_SHIFT (4U)
#define | USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
#define | USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
#define | USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
#define | USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
#define | USBPHY_STATUS_RSVD2_MASK (0x80U)
#define | USBPHY_STATUS_RSVD2_SHIFT (7U)
#define | USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
#define | USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
#define | USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
#define | USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
#define | USBPHY_STATUS_RSVD3_MASK (0x200U)
#define | USBPHY_STATUS_RSVD3_SHIFT (9U)
#define | USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
#define | USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
#define | USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
#define | USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
#define | USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)
#define | USBPHY_STATUS_RSVD4_SHIFT (11U)
#define | USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
DEBUG - USB PHY Debug Register
#define | USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
#define | USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
#define | USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
#define | USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define | USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
#define | USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
#define | USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
#define | USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
#define | USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
#define | USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
#define | USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
#define | USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
#define | USBPHY_DEBUG_RSVD0_MASK (0xC0U)
#define | USBPHY_DEBUG_RSVD0_SHIFT (6U)
#define | USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
#define | USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
#define | USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
#define | USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
#define | USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
#define | USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
#define | USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
#define | USBPHY_DEBUG_RSVD1_MASK (0xE000U)
#define | USBPHY_DEBUG_RSVD1_SHIFT (13U)
#define | USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
#define | USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define | USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
#define | USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
#define | USBPHY_DEBUG_RSVD2_MASK (0xE00000U)
#define | USBPHY_DEBUG_RSVD2_SHIFT (21U)
#define | USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
#define | USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
#define | USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
#define | USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
#define | USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define | USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
#define | USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
#define | USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define | USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
#define | USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
#define | USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
#define | USBPHY_DEBUG_CLKGATE_SHIFT (30U)
#define | USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
#define | USBPHY_DEBUG_RSVD3_MASK (0x80000000U)
#define | USBPHY_DEBUG_RSVD3_SHIFT (31U)
#define | USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
DEBUG_SET - USB PHY Debug Register
#define | USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
#define | USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
#define | USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
#define | USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define | USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
#define | USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
#define | USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
#define | USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
#define | USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
#define | USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
#define | USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
#define | USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
#define | USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)
#define | USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)
#define | USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
#define | USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
#define | USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
#define | USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
#define | USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
#define | USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
#define | USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
#define | USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)
#define | USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)
#define | USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
#define | USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define | USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
#define | USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
#define | USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)
#define | USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)
#define | USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
#define | USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
#define | USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
#define | USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
#define | USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define | USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
#define | USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
#define | USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define | USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
#define | USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
#define | USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
#define | USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
#define | USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
#define | USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)
#define | USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)
#define | USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
DEBUG_CLR - USB PHY Debug Register
#define | USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
#define | USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
#define | USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
#define | USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define | USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
#define | USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
#define | USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
#define | USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
#define | USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
#define | USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
#define | USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
#define | USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
#define | USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)
#define | USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)
#define | USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
#define | USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
#define | USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
#define | USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
#define | USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
#define | USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
#define | USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
#define | USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)
#define | USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)
#define | USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
#define | USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define | USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
#define | USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
#define | USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)
#define | USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)
#define | USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
#define | USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
#define | USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
#define | USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
#define | USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define | USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
#define | USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
#define | USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define | USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
#define | USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
#define | USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
#define | USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
#define | USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
#define | USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)
#define | USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)
#define | USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
DEBUG_TOG - USB PHY Debug Register
#define | USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
#define | USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
#define | USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
#define | USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define | USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
#define | USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
#define | USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
#define | USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
#define | USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
#define | USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
#define | USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
#define | USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
#define | USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)
#define | USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)
#define | USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
#define | USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
#define | USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
#define | USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
#define | USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
#define | USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
#define | USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
#define | USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)
#define | USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)
#define | USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
#define | USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define | USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
#define | USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
#define | USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)
#define | USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)
#define | USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
#define | USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
#define | USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
#define | USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
#define | USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define | USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
#define | USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
#define | USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define | USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
#define | USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
#define | USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
#define | USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
#define | USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
#define | USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)
#define | USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)
#define | USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
DEBUG0_STATUS - UTMI Debug Status Register 0
#define | USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
#define | USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
#define | USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
#define | USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
#define | USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
#define | USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
#define | USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
#define | USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
#define | USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
DEBUG1 - UTMI Debug Status Register 1
#define | USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)
#define | USBPHY_DEBUG1_RSVD0_SHIFT (0U)
#define | USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
#define | USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
#define | USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
#define | USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
#define | USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)
#define | USBPHY_DEBUG1_RSVD1_SHIFT (15U)
#define | USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
DEBUG1_SET - UTMI Debug Status Register 1
#define | USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)
#define | USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)
#define | USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
#define | USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
#define | USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
#define | USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
#define | USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)
#define | USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)
#define | USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
DEBUG1_CLR - UTMI Debug Status Register 1
#define | USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)
#define | USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)
#define | USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
#define | USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
#define | USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
#define | USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
#define | USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)
#define | USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)
#define | USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
DEBUG1_TOG - UTMI Debug Status Register 1
#define | USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)
#define | USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)
#define | USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
#define | USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
#define | USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
#define | USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
#define | USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)
#define | USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)
#define | USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
VERSION - UTMI RTL Version
#define | USBPHY_VERSION_STEP_MASK (0xFFFFU)
#define | USBPHY_VERSION_STEP_SHIFT (0U)
#define | USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
#define | USBPHY_VERSION_MINOR_MASK (0xFF0000U)
#define | USBPHY_VERSION_MINOR_SHIFT (16U)
#define | USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
#define | USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
#define | USBPHY_VERSION_MAJOR_SHIFT (24U)
#define | USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
VBUS_DETECT - USB VBUS Detect Register
#define | USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
#define | USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
#define | USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
#define | USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
#define | USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
#define | USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
#define | USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
#define | USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
#define | USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
#define | USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)
#define | USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
#define | USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
VBUS_DETECT_SET - USB VBUS Detect Register
#define | USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
#define | USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
#define | USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
#define | USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
#define | USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
#define | USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
#define | USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
#define | USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
#define | USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
#define | USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
#define | USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
#define | USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
VBUS_DETECT_CLR - USB VBUS Detect Register
#define | USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
#define | USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
#define | USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
#define | USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
#define | USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
#define | USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
#define | USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
#define | USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
#define | USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
#define | USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
#define | USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
#define | USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
VBUS_DETECT_TOG - USB VBUS Detect Register
#define | USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
#define | USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
#define | USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
#define | USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
#define | USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
#define | USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
#define | USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
#define | USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
#define | USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
#define | USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
#define | USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
#define | USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
CHRG_DETECT - USB Charger Detect Register
#define | USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
#define | USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
#define | USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
#define | USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)
#define | USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
#define | USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
#define | USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)
#define | USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)
#define | USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
CHRG_DETECT_SET - USB Charger Detect Register
#define | USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
#define | USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
#define | USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
#define | USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
#define | USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
#define | USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
#define | USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)
#define | USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)
#define | USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
CHRG_DETECT_CLR - USB Charger Detect Register
#define | USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
#define | USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
#define | USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
#define | USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
#define | USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
#define | USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
#define | USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)
#define | USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)
#define | USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
CHRG_DETECT_TOG - USB Charger Detect Register
#define | USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
#define | USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
#define | USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
#define | USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
#define | USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
#define | USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
#define | USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)
#define | USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)
#define | USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
VBUS_DETECT_STAT - USB VBUS Detect Status Register
#define | USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
#define | USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
#define | USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
#define | USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)
#define | USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
#define | USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
#define | USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)
#define | USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
#define | USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
#define | USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
#define | USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
#define | USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
CHRG_DETECT_STAT - USB Charger Detect Status Register
#define | USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
#define | USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
#define | USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
#define | USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
#define | USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
#define | USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
#define | USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
#define | USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
#define | USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
#define | USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
#define | USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
#define | USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
LOOPBACK - USB Loopback Test Register
#define | USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
#define | USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
#define | USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
LOOPBACK_SET - USB Loopback Test Register
#define | USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
#define | USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
#define | USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
LOOPBACK_CLR - USB Loopback Test Register
#define | USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
#define | USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
#define | USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
LOOPBACK_TOG - USB Loopback Test Register
#define | USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
#define | USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
#define | USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
MISC - USB Misc Register
#define | USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)
#define | USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)
#define | USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
#define | USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)
#define | USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)
#define | USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
#define | USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)
#define | USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)
#define | USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
MISC_SET - USB Misc Register
#define | USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
#define | USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
#define | USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
#define | USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)
#define | USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)
#define | USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
#define | USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)
#define | USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)
#define | USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
MISC_CLR - USB Misc Register
#define | USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
#define | USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
#define | USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
#define | USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)
#define | USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)
#define | USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
#define | USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)
#define | USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)
#define | USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
MISC_TOG - USB Misc Register
#define | USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
#define | USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
#define | USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
#define | USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)
#define | USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)
#define | USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
#define | USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)
#define | USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)
#define | USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
DIGPROG - Chip Silicon Version
#define | USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
#define | USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
#define | USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)
DS_ADDR - DMA System Address
#define | USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
#define | USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
#define | USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
BLK_ATT - Block Attributes
#define | USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
#define | USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
#define | USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
#define | USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
#define | USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
#define | USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
CMD_ARG - Command Argument
#define | USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_ARG_CMDARG_SHIFT (0U)
#define | USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
CMD_XFR_TYP - Command Transfer Type
#define | USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
#define | USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
#define | USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
#define | USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
#define | USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
#define | USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
#define | USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
#define | USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
#define | USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
#define | USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
#define | USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
#define | USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
#define | USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
#define | USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
#define | USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
#define | USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
#define | USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
#define | USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
CMD_RSP0 - Command Response0
#define | USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
#define | USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
CMD_RSP1 - Command Response1
#define | USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
#define | USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
CMD_RSP2 - Command Response2
#define | USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
#define | USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
CMD_RSP3 - Command Response3
#define | USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
#define | USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
#define | USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
DATA_BUFF_ACC_PORT - Data Buffer Access Port
#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
PRES_STATE - Present State
#define | USDHC_PRES_STATE_CIHB_MASK (0x1U)
#define | USDHC_PRES_STATE_CIHB_SHIFT (0U)
#define | USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
#define | USDHC_PRES_STATE_CDIHB_MASK (0x2U)
#define | USDHC_PRES_STATE_CDIHB_SHIFT (1U)
#define | USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
#define | USDHC_PRES_STATE_DLA_MASK (0x4U)
#define | USDHC_PRES_STATE_DLA_SHIFT (2U)
#define | USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
#define | USDHC_PRES_STATE_SDSTB_MASK (0x8U)
#define | USDHC_PRES_STATE_SDSTB_SHIFT (3U)
#define | USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
#define | USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
#define | USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
#define | USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
#define | USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
#define | USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
#define | USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
#define | USDHC_PRES_STATE_PEROFF_MASK (0x40U)
#define | USDHC_PRES_STATE_PEROFF_SHIFT (6U)
#define | USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
#define | USDHC_PRES_STATE_SDOFF_MASK (0x80U)
#define | USDHC_PRES_STATE_SDOFF_SHIFT (7U)
#define | USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
#define | USDHC_PRES_STATE_WTA_MASK (0x100U)
#define | USDHC_PRES_STATE_WTA_SHIFT (8U)
#define | USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
#define | USDHC_PRES_STATE_RTA_MASK (0x200U)
#define | USDHC_PRES_STATE_RTA_SHIFT (9U)
#define | USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
#define | USDHC_PRES_STATE_BWEN_MASK (0x400U)
#define | USDHC_PRES_STATE_BWEN_SHIFT (10U)
#define | USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
#define | USDHC_PRES_STATE_BREN_MASK (0x800U)
#define | USDHC_PRES_STATE_BREN_SHIFT (11U)
#define | USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
#define | USDHC_PRES_STATE_RTR_MASK (0x1000U)
#define | USDHC_PRES_STATE_RTR_SHIFT (12U)
#define | USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
#define | USDHC_PRES_STATE_TSCD_MASK (0x8000U)
#define | USDHC_PRES_STATE_TSCD_SHIFT (15U)
#define | USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
#define | USDHC_PRES_STATE_CINST_MASK (0x10000U)
#define | USDHC_PRES_STATE_CINST_SHIFT (16U)
#define | USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
#define | USDHC_PRES_STATE_CDPL_MASK (0x40000U)
#define | USDHC_PRES_STATE_CDPL_SHIFT (18U)
#define | USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
#define | USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
#define | USDHC_PRES_STATE_WPSPL_SHIFT (19U)
#define | USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
#define | USDHC_PRES_STATE_CLSL_MASK (0x800000U)
#define | USDHC_PRES_STATE_CLSL_SHIFT (23U)
#define | USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
#define | USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
#define | USDHC_PRES_STATE_DLSL_SHIFT (24U)
#define | USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
PROT_CTRL - Protocol Control
#define | USDHC_PROT_CTRL_LCTL_MASK (0x1U)
#define | USDHC_PROT_CTRL_LCTL_SHIFT (0U)
#define | USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
#define | USDHC_PROT_CTRL_DTW_MASK (0x6U)
#define | USDHC_PROT_CTRL_DTW_SHIFT (1U)
#define | USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
#define | USDHC_PROT_CTRL_D3CD_MASK (0x8U)
#define | USDHC_PROT_CTRL_D3CD_SHIFT (3U)
#define | USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
#define | USDHC_PROT_CTRL_EMODE_MASK (0x30U)
#define | USDHC_PROT_CTRL_EMODE_SHIFT (4U)
#define | USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
#define | USDHC_PROT_CTRL_CDTL_MASK (0x40U)
#define | USDHC_PROT_CTRL_CDTL_SHIFT (6U)
#define | USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
#define | USDHC_PROT_CTRL_CDSS_MASK (0x80U)
#define | USDHC_PROT_CTRL_CDSS_SHIFT (7U)
#define | USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
#define | USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
#define | USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
#define | USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
#define | USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
#define | USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
#define | USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
#define | USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
#define | USDHC_PROT_CTRL_CREQ_SHIFT (17U)
#define | USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
#define | USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
#define | USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
#define | USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
#define | USDHC_PROT_CTRL_IABG_MASK (0x80000U)
#define | USDHC_PROT_CTRL_IABG_SHIFT (19U)
#define | USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
#define | USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
#define | USDHC_PROT_CTRL_WECINT_SHIFT (24U)
#define | USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
#define | USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
#define | USDHC_PROT_CTRL_WECINS_SHIFT (25U)
#define | USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
#define | USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
#define | USDHC_PROT_CTRL_WECRM_SHIFT (26U)
#define | USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
#define | USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
#define | USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
#define | USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
SYS_CTRL - System Control
#define | USDHC_SYS_CTRL_DVS_MASK (0xF0U)
#define | USDHC_SYS_CTRL_DVS_SHIFT (4U)
#define | USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
#define | USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
#define | USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
#define | USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
#define | USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
#define | USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
#define | USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
#define | USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
#define | USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
#define | USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
#define | USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
#define | USDHC_SYS_CTRL_RSTA_SHIFT (24U)
#define | USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
#define | USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
#define | USDHC_SYS_CTRL_RSTC_SHIFT (25U)
#define | USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
#define | USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
#define | USDHC_SYS_CTRL_RSTD_SHIFT (26U)
#define | USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
#define | USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
#define | USDHC_SYS_CTRL_INITA_SHIFT (27U)
#define | USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
#define | USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
#define | USDHC_SYS_CTRL_RSTT_SHIFT (28U)
#define | USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
INT_STATUS - Interrupt Status
#define | USDHC_INT_STATUS_CC_MASK (0x1U)
#define | USDHC_INT_STATUS_CC_SHIFT (0U)
#define | USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
#define | USDHC_INT_STATUS_TC_MASK (0x2U)
#define | USDHC_INT_STATUS_TC_SHIFT (1U)
#define | USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
#define | USDHC_INT_STATUS_BGE_MASK (0x4U)
#define | USDHC_INT_STATUS_BGE_SHIFT (2U)
#define | USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
#define | USDHC_INT_STATUS_DINT_MASK (0x8U)
#define | USDHC_INT_STATUS_DINT_SHIFT (3U)
#define | USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
#define | USDHC_INT_STATUS_BWR_MASK (0x10U)
#define | USDHC_INT_STATUS_BWR_SHIFT (4U)
#define | USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
#define | USDHC_INT_STATUS_BRR_MASK (0x20U)
#define | USDHC_INT_STATUS_BRR_SHIFT (5U)
#define | USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
#define | USDHC_INT_STATUS_CINS_MASK (0x40U)
#define | USDHC_INT_STATUS_CINS_SHIFT (6U)
#define | USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
#define | USDHC_INT_STATUS_CRM_MASK (0x80U)
#define | USDHC_INT_STATUS_CRM_SHIFT (7U)
#define | USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
#define | USDHC_INT_STATUS_CINT_MASK (0x100U)
#define | USDHC_INT_STATUS_CINT_SHIFT (8U)
#define | USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
#define | USDHC_INT_STATUS_RTE_MASK (0x1000U)
#define | USDHC_INT_STATUS_RTE_SHIFT (12U)
#define | USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
#define | USDHC_INT_STATUS_TP_MASK (0x4000U)
#define | USDHC_INT_STATUS_TP_SHIFT (14U)
#define | USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
#define | USDHC_INT_STATUS_CTOE_MASK (0x10000U)
#define | USDHC_INT_STATUS_CTOE_SHIFT (16U)
#define | USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
#define | USDHC_INT_STATUS_CCE_MASK (0x20000U)
#define | USDHC_INT_STATUS_CCE_SHIFT (17U)
#define | USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
#define | USDHC_INT_STATUS_CEBE_MASK (0x40000U)
#define | USDHC_INT_STATUS_CEBE_SHIFT (18U)
#define | USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
#define | USDHC_INT_STATUS_CIE_MASK (0x80000U)
#define | USDHC_INT_STATUS_CIE_SHIFT (19U)
#define | USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
#define | USDHC_INT_STATUS_DTOE_MASK (0x100000U)
#define | USDHC_INT_STATUS_DTOE_SHIFT (20U)
#define | USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
#define | USDHC_INT_STATUS_DCE_MASK (0x200000U)
#define | USDHC_INT_STATUS_DCE_SHIFT (21U)
#define | USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
#define | USDHC_INT_STATUS_DEBE_MASK (0x400000U)
#define | USDHC_INT_STATUS_DEBE_SHIFT (22U)
#define | USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
#define | USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
#define | USDHC_INT_STATUS_AC12E_SHIFT (24U)
#define | USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
#define | USDHC_INT_STATUS_TNE_MASK (0x4000000U)
#define | USDHC_INT_STATUS_TNE_SHIFT (26U)
#define | USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
#define | USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
#define | USDHC_INT_STATUS_DMAE_SHIFT (28U)
#define | USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
INT_STATUS_EN - Interrupt Status Enable
#define | USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
#define | USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
#define | USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
#define | USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
#define | USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
#define | USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
#define | USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
#define | USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
#define | USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
#define | USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
#define | USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
#define | USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
#define | USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
#define | USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
#define | USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
#define | USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
#define | USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
#define | USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
#define | USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
#define | USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
#define | USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
#define | USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
#define | USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
#define | USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
#define | USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
#define | USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
#define | USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
#define | USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
#define | USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
#define | USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
#define | USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
#define | USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
#define | USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
#define | USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
#define | USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
#define | USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
#define | USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
#define | USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
#define | USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
#define | USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
#define | USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
#define | USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
#define | USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
#define | USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
#define | USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
#define | USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
#define | USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
#define | USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
#define | USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
#define | USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
#define | USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
#define | USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
#define | USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
#define | USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
#define | USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
#define | USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
#define | USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
#define | USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
#define | USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
#define | USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
#define | USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
#define | USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
#define | USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
INT_SIGNAL_EN - Interrupt Signal Enable
#define | USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
#define | USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
#define | USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
#define | USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
#define | USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
#define | USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
#define | USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
#define | USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
#define | USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
#define | USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
#define | USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
#define | USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
#define | USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
#define | USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
#define | USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
#define | USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
#define | USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
#define | USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
#define | USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
#define | USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
#define | USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
#define | USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
#define | USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
#define | USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
#define | USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
#define | USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
#define | USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
#define | USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
#define | USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
#define | USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
#define | USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
#define | USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
#define | USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
#define | USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
#define | USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
#define | USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
#define | USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
#define | USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
#define | USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
#define | USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
#define | USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
#define | USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
#define | USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
#define | USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
HOST_CTRL_CAP - Host Controller Capabilities
#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
#define | USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
#define | USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
#define | USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
#define | USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
#define | USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
#define | USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
#define | USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
#define | USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
#define | USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
#define | USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
#define | USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
#define | USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
#define | USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
#define | USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
#define | USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
#define | USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
#define | USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
#define | USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
#define | USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
#define | USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
#define | USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
#define | USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
#define | USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
#define | USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
#define | USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
#define | USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
#define | USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
#define | USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
#define | USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
#define | USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
WTMK_LVL - Watermark Level
#define | USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
#define | USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
#define | USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
#define | USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
#define | USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
#define | USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
#define | USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
#define | USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
#define | USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
#define | USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
#define | USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
#define | USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
MIX_CTRL - Mixer Control
#define | USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
#define | USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
#define | USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
#define | USDHC_MIX_CTRL_BCEN_MASK (0x2U)
#define | USDHC_MIX_CTRL_BCEN_SHIFT (1U)
#define | USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
#define | USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
#define | USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
#define | USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
#define | USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
#define | USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
#define | USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
#define | USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
#define | USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
#define | USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
#define | USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
#define | USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
#define | USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
#define | USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
#define | USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
#define | USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
#define | USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
#define | USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
#define | USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
#define | USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
#define | USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
#define | USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
#define | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
#define | USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
#define | USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
#define | USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
#define | USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
#define | USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
FORCE_EVENT - Force Event
#define | USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
#define | USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
#define | USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
#define | USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
#define | USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
#define | USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
#define | USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
#define | USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
#define | USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
#define | USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
#define | USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
#define | USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
#define | USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
#define | USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
#define | USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
#define | USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
#define | USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
#define | USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
#define | USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
#define | USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
#define | USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
#define | USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
#define | USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
#define | USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
#define | USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
#define | USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
#define | USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
#define | USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
#define | USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
#define | USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
#define | USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
#define | USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
#define | USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
#define | USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
#define | USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
#define | USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
#define | USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
#define | USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
#define | USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
#define | USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
#define | USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
ADMA_ERR_STATUS - ADMA Error Status Register
#define | USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
#define | USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
#define | USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
#define | USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
#define | USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
#define | USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
#define | USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
#define | USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
#define | USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
ADMA_SYS_ADDR - ADMA System Address
#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
DLL_CTRL - DLL (Delay Line) Control
#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
DLL_STATUS - DLL Status
#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
VEND_SPEC - Vendor Specific Register
#define | USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
#define | USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
#define | USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
#define | USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
#define | USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
#define | USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
#define | USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
#define | USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
#define | USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
MMC_BOOT - MMC Boot Register
#define | USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
#define | USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
#define | USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
#define | USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
#define | USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
#define | USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
#define | USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
#define | USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
#define | USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
#define | USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
#define | USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
#define | USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
#define | USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
#define | USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
#define | USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
VEND_SPEC2 - Vendor Specific 2 Register
#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
#define | USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U)
#define | USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U)
#define | USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
#define | USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U)
#define | USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U)
#define | USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)
TUNING_CTRL - Tuning Control Register
#define | USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
#define | USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
#define | USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
#define | USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
#define | USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
#define | USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
#define | USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
#define | USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
#define | USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
#define | USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
#define | USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
#define | USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
#define | USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
#define | USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
#define | USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
WCR - Watchdog Control Register
#define | WDOG_WCR_WDZST_MASK (0x1U)
#define | WDOG_WCR_WDZST_SHIFT (0U)
#define | WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
#define | WDOG_WCR_WDBG_MASK (0x2U)
#define | WDOG_WCR_WDBG_SHIFT (1U)
#define | WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
#define | WDOG_WCR_WDE_MASK (0x4U)
#define | WDOG_WCR_WDE_SHIFT (2U)
#define | WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
#define | WDOG_WCR_WDT_MASK (0x8U)
#define | WDOG_WCR_WDT_SHIFT (3U)
#define | WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
#define | WDOG_WCR_SRS_MASK (0x10U)
#define | WDOG_WCR_SRS_SHIFT (4U)
#define | WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
#define | WDOG_WCR_WDA_MASK (0x20U)
#define | WDOG_WCR_WDA_SHIFT (5U)
#define | WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
#define | WDOG_WCR_SRE_MASK (0x40U)
#define | WDOG_WCR_SRE_SHIFT (6U)
#define | WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
#define | WDOG_WCR_WDW_MASK (0x80U)
#define | WDOG_WCR_WDW_SHIFT (7U)
#define | WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
#define | WDOG_WCR_WT_MASK (0xFF00U)
#define | WDOG_WCR_WT_SHIFT (8U)
#define | WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
WSR - Watchdog Service Register
#define | WDOG_WSR_WSR_MASK (0xFFFFU)
#define | WDOG_WSR_WSR_SHIFT (0U)
#define | WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
WRSR - Watchdog Reset Status Register
#define | WDOG_WRSR_SFTW_MASK (0x1U)
#define | WDOG_WRSR_SFTW_SHIFT (0U)
#define | WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
#define | WDOG_WRSR_TOUT_MASK (0x2U)
#define | WDOG_WRSR_TOUT_SHIFT (1U)
#define | WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
#define | WDOG_WRSR_POR_MASK (0x10U)
#define | WDOG_WRSR_POR_SHIFT (4U)
#define | WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
WICR - Watchdog Interrupt Control Register
#define | WDOG_WICR_WICT_MASK (0xFFU)
#define | WDOG_WICR_WICT_SHIFT (0U)
#define | WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
#define | WDOG_WICR_WTIS_MASK (0x4000U)
#define | WDOG_WICR_WTIS_SHIFT (14U)
#define | WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
#define | WDOG_WICR_WIE_MASK (0x8000U)
#define | WDOG_WICR_WIE_SHIFT (15U)
#define | WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
WMCR - Watchdog Miscellaneous Control Register
#define | WDOG_WMCR_PDE_MASK (0x1U)
#define | WDOG_WMCR_PDE_SHIFT (0U)
#define | WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
SEL0 - Crossbar A Select Register 0
#define | XBARA_SEL0_SEL0_MASK (0x7FU)
#define | XBARA_SEL0_SEL0_SHIFT (0U)
#define | XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
#define | XBARA_SEL0_SEL1_MASK (0x7F00U)
#define | XBARA_SEL0_SEL1_SHIFT (8U)
#define | XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
SEL1 - Crossbar A Select Register 1
#define | XBARA_SEL1_SEL2_MASK (0x7FU)
#define | XBARA_SEL1_SEL2_SHIFT (0U)
#define | XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
#define | XBARA_SEL1_SEL3_MASK (0x7F00U)
#define | XBARA_SEL1_SEL3_SHIFT (8U)
#define | XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
SEL2 - Crossbar A Select Register 2
#define | XBARA_SEL2_SEL4_MASK (0x7FU)
#define | XBARA_SEL2_SEL4_SHIFT (0U)
#define | XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
#define | XBARA_SEL2_SEL5_MASK (0x7F00U)
#define | XBARA_SEL2_SEL5_SHIFT (8U)
#define | XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
SEL3 - Crossbar A Select Register 3
#define | XBARA_SEL3_SEL6_MASK (0x7FU)
#define | XBARA_SEL3_SEL6_SHIFT (0U)
#define | XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
#define | XBARA_SEL3_SEL7_MASK (0x7F00U)
#define | XBARA_SEL3_SEL7_SHIFT (8U)
#define | XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
SEL4 - Crossbar A Select Register 4
#define | XBARA_SEL4_SEL8_MASK (0x7FU)
#define | XBARA_SEL4_SEL8_SHIFT (0U)
#define | XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
#define | XBARA_SEL4_SEL9_MASK (0x7F00U)
#define | XBARA_SEL4_SEL9_SHIFT (8U)
#define | XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
SEL5 - Crossbar A Select Register 5
#define | XBARA_SEL5_SEL10_MASK (0x7FU)
#define | XBARA_SEL5_SEL10_SHIFT (0U)
#define | XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
#define | XBARA_SEL5_SEL11_MASK (0x7F00U)
#define | XBARA_SEL5_SEL11_SHIFT (8U)
#define | XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
SEL6 - Crossbar A Select Register 6
#define | XBARA_SEL6_SEL12_MASK (0x7FU)
#define | XBARA_SEL6_SEL12_SHIFT (0U)
#define | XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
#define | XBARA_SEL6_SEL13_MASK (0x7F00U)
#define | XBARA_SEL6_SEL13_SHIFT (8U)
#define | XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
SEL7 - Crossbar A Select Register 7
#define | XBARA_SEL7_SEL14_MASK (0x7FU)
#define | XBARA_SEL7_SEL14_SHIFT (0U)
#define | XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
#define | XBARA_SEL7_SEL15_MASK (0x7F00U)
#define | XBARA_SEL7_SEL15_SHIFT (8U)
#define | XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
SEL8 - Crossbar A Select Register 8
#define | XBARA_SEL8_SEL16_MASK (0x7FU)
#define | XBARA_SEL8_SEL16_SHIFT (0U)
#define | XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
#define | XBARA_SEL8_SEL17_MASK (0x7F00U)
#define | XBARA_SEL8_SEL17_SHIFT (8U)
#define | XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
SEL9 - Crossbar A Select Register 9
#define | XBARA_SEL9_SEL18_MASK (0x7FU)
#define | XBARA_SEL9_SEL18_SHIFT (0U)
#define | XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
#define | XBARA_SEL9_SEL19_MASK (0x7F00U)
#define | XBARA_SEL9_SEL19_SHIFT (8U)
#define | XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
SEL10 - Crossbar A Select Register 10
#define | XBARA_SEL10_SEL20_MASK (0x7FU)
#define | XBARA_SEL10_SEL20_SHIFT (0U)
#define | XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
#define | XBARA_SEL10_SEL21_MASK (0x7F00U)
#define | XBARA_SEL10_SEL21_SHIFT (8U)
#define | XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
SEL11 - Crossbar A Select Register 11
#define | XBARA_SEL11_SEL22_MASK (0x7FU)
#define | XBARA_SEL11_SEL22_SHIFT (0U)
#define | XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
#define | XBARA_SEL11_SEL23_MASK (0x7F00U)
#define | XBARA_SEL11_SEL23_SHIFT (8U)
#define | XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
SEL12 - Crossbar A Select Register 12
#define | XBARA_SEL12_SEL24_MASK (0x7FU)
#define | XBARA_SEL12_SEL24_SHIFT (0U)
#define | XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
#define | XBARA_SEL12_SEL25_MASK (0x7F00U)
#define | XBARA_SEL12_SEL25_SHIFT (8U)
#define | XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
SEL13 - Crossbar A Select Register 13
#define | XBARA_SEL13_SEL26_MASK (0x7FU)
#define | XBARA_SEL13_SEL26_SHIFT (0U)
#define | XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
#define | XBARA_SEL13_SEL27_MASK (0x7F00U)
#define | XBARA_SEL13_SEL27_SHIFT (8U)
#define | XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
SEL14 - Crossbar A Select Register 14
#define | XBARA_SEL14_SEL28_MASK (0x7FU)
#define | XBARA_SEL14_SEL28_SHIFT (0U)
#define | XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
#define | XBARA_SEL14_SEL29_MASK (0x7F00U)
#define | XBARA_SEL14_SEL29_SHIFT (8U)
#define | XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
SEL15 - Crossbar A Select Register 15
#define | XBARA_SEL15_SEL30_MASK (0x7FU)
#define | XBARA_SEL15_SEL30_SHIFT (0U)
#define | XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
#define | XBARA_SEL15_SEL31_MASK (0x7F00U)
#define | XBARA_SEL15_SEL31_SHIFT (8U)
#define | XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
SEL16 - Crossbar A Select Register 16
#define | XBARA_SEL16_SEL32_MASK (0x7FU)
#define | XBARA_SEL16_SEL32_SHIFT (0U)
#define | XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
#define | XBARA_SEL16_SEL33_MASK (0x7F00U)
#define | XBARA_SEL16_SEL33_SHIFT (8U)
#define | XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
SEL17 - Crossbar A Select Register 17
#define | XBARA_SEL17_SEL34_MASK (0x7FU)
#define | XBARA_SEL17_SEL34_SHIFT (0U)
#define | XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
#define | XBARA_SEL17_SEL35_MASK (0x7F00U)
#define | XBARA_SEL17_SEL35_SHIFT (8U)
#define | XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
SEL18 - Crossbar A Select Register 18
#define | XBARA_SEL18_SEL36_MASK (0x7FU)
#define | XBARA_SEL18_SEL36_SHIFT (0U)
#define | XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
#define | XBARA_SEL18_SEL37_MASK (0x7F00U)
#define | XBARA_SEL18_SEL37_SHIFT (8U)
#define | XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
SEL19 - Crossbar A Select Register 19
#define | XBARA_SEL19_SEL38_MASK (0x7FU)
#define | XBARA_SEL19_SEL38_SHIFT (0U)
#define | XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
#define | XBARA_SEL19_SEL39_MASK (0x7F00U)
#define | XBARA_SEL19_SEL39_SHIFT (8U)
#define | XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
SEL20 - Crossbar A Select Register 20
#define | XBARA_SEL20_SEL40_MASK (0x7FU)
#define | XBARA_SEL20_SEL40_SHIFT (0U)
#define | XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
#define | XBARA_SEL20_SEL41_MASK (0x7F00U)
#define | XBARA_SEL20_SEL41_SHIFT (8U)
#define | XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
SEL21 - Crossbar A Select Register 21
#define | XBARA_SEL21_SEL42_MASK (0x7FU)
#define | XBARA_SEL21_SEL42_SHIFT (0U)
#define | XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
#define | XBARA_SEL21_SEL43_MASK (0x7F00U)
#define | XBARA_SEL21_SEL43_SHIFT (8U)
#define | XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
SEL22 - Crossbar A Select Register 22
#define | XBARA_SEL22_SEL44_MASK (0x7FU)
#define | XBARA_SEL22_SEL44_SHIFT (0U)
#define | XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
#define | XBARA_SEL22_SEL45_MASK (0x7F00U)
#define | XBARA_SEL22_SEL45_SHIFT (8U)
#define | XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
SEL23 - Crossbar A Select Register 23
#define | XBARA_SEL23_SEL46_MASK (0x7FU)
#define | XBARA_SEL23_SEL46_SHIFT (0U)
#define | XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
#define | XBARA_SEL23_SEL47_MASK (0x7F00U)
#define | XBARA_SEL23_SEL47_SHIFT (8U)
#define | XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
SEL24 - Crossbar A Select Register 24
#define | XBARA_SEL24_SEL48_MASK (0x7FU)
#define | XBARA_SEL24_SEL48_SHIFT (0U)
#define | XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
#define | XBARA_SEL24_SEL49_MASK (0x7F00U)
#define | XBARA_SEL24_SEL49_SHIFT (8U)
#define | XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
SEL25 - Crossbar A Select Register 25
#define | XBARA_SEL25_SEL50_MASK (0x7FU)
#define | XBARA_SEL25_SEL50_SHIFT (0U)
#define | XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
#define | XBARA_SEL25_SEL51_MASK (0x7F00U)
#define | XBARA_SEL25_SEL51_SHIFT (8U)
#define | XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
SEL26 - Crossbar A Select Register 26
#define | XBARA_SEL26_SEL52_MASK (0x7FU)
#define | XBARA_SEL26_SEL52_SHIFT (0U)
#define | XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
#define | XBARA_SEL26_SEL53_MASK (0x7F00U)
#define | XBARA_SEL26_SEL53_SHIFT (8U)
#define | XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
SEL27 - Crossbar A Select Register 27
#define | XBARA_SEL27_SEL54_MASK (0x7FU)
#define | XBARA_SEL27_SEL54_SHIFT (0U)
#define | XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
#define | XBARA_SEL27_SEL55_MASK (0x7F00U)
#define | XBARA_SEL27_SEL55_SHIFT (8U)
#define | XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
SEL28 - Crossbar A Select Register 28
#define | XBARA_SEL28_SEL56_MASK (0x7FU)
#define | XBARA_SEL28_SEL56_SHIFT (0U)
#define | XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
#define | XBARA_SEL28_SEL57_MASK (0x7F00U)
#define | XBARA_SEL28_SEL57_SHIFT (8U)
#define | XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
SEL29 - Crossbar A Select Register 29
#define | XBARA_SEL29_SEL58_MASK (0x7FU)
#define | XBARA_SEL29_SEL58_SHIFT (0U)
#define | XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
#define | XBARA_SEL29_SEL59_MASK (0x7F00U)
#define | XBARA_SEL29_SEL59_SHIFT (8U)
#define | XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
SEL30 - Crossbar A Select Register 30
#define | XBARA_SEL30_SEL60_MASK (0x7FU)
#define | XBARA_SEL30_SEL60_SHIFT (0U)
#define | XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
#define | XBARA_SEL30_SEL61_MASK (0x7F00U)
#define | XBARA_SEL30_SEL61_SHIFT (8U)
#define | XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
SEL31 - Crossbar A Select Register 31
#define | XBARA_SEL31_SEL62_MASK (0x7FU)
#define | XBARA_SEL31_SEL62_SHIFT (0U)
#define | XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
#define | XBARA_SEL31_SEL63_MASK (0x7F00U)
#define | XBARA_SEL31_SEL63_SHIFT (8U)
#define | XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
SEL32 - Crossbar A Select Register 32
#define | XBARA_SEL32_SEL64_MASK (0x7FU)
#define | XBARA_SEL32_SEL64_SHIFT (0U)
#define | XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
#define | XBARA_SEL32_SEL65_MASK (0x7F00U)
#define | XBARA_SEL32_SEL65_SHIFT (8U)
#define | XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
SEL33 - Crossbar A Select Register 33
#define | XBARA_SEL33_SEL66_MASK (0x7FU)
#define | XBARA_SEL33_SEL66_SHIFT (0U)
#define | XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
#define | XBARA_SEL33_SEL67_MASK (0x7F00U)
#define | XBARA_SEL33_SEL67_SHIFT (8U)
#define | XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
SEL34 - Crossbar A Select Register 34
#define | XBARA_SEL34_SEL68_MASK (0x7FU)
#define | XBARA_SEL34_SEL68_SHIFT (0U)
#define | XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
#define | XBARA_SEL34_SEL69_MASK (0x7F00U)
#define | XBARA_SEL34_SEL69_SHIFT (8U)
#define | XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
SEL35 - Crossbar A Select Register 35
#define | XBARA_SEL35_SEL70_MASK (0x7FU)
#define | XBARA_SEL35_SEL70_SHIFT (0U)
#define | XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
#define | XBARA_SEL35_SEL71_MASK (0x7F00U)
#define | XBARA_SEL35_SEL71_SHIFT (8U)
#define | XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
SEL36 - Crossbar A Select Register 36
#define | XBARA_SEL36_SEL72_MASK (0x7FU)
#define | XBARA_SEL36_SEL72_SHIFT (0U)
#define | XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
#define | XBARA_SEL36_SEL73_MASK (0x7F00U)
#define | XBARA_SEL36_SEL73_SHIFT (8U)
#define | XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
SEL37 - Crossbar A Select Register 37
#define | XBARA_SEL37_SEL74_MASK (0x7FU)
#define | XBARA_SEL37_SEL74_SHIFT (0U)
#define | XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
#define | XBARA_SEL37_SEL75_MASK (0x7F00U)
#define | XBARA_SEL37_SEL75_SHIFT (8U)
#define | XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
SEL38 - Crossbar A Select Register 38
#define | XBARA_SEL38_SEL76_MASK (0x7FU)
#define | XBARA_SEL38_SEL76_SHIFT (0U)
#define | XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
#define | XBARA_SEL38_SEL77_MASK (0x7F00U)
#define | XBARA_SEL38_SEL77_SHIFT (8U)
#define | XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
SEL39 - Crossbar A Select Register 39
#define | XBARA_SEL39_SEL78_MASK (0x7FU)
#define | XBARA_SEL39_SEL78_SHIFT (0U)
#define | XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
#define | XBARA_SEL39_SEL79_MASK (0x7F00U)
#define | XBARA_SEL39_SEL79_SHIFT (8U)
#define | XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
SEL40 - Crossbar A Select Register 40
#define | XBARA_SEL40_SEL80_MASK (0x7FU)
#define | XBARA_SEL40_SEL80_SHIFT (0U)
#define | XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
#define | XBARA_SEL40_SEL81_MASK (0x7F00U)
#define | XBARA_SEL40_SEL81_SHIFT (8U)
#define | XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
SEL41 - Crossbar A Select Register 41
#define | XBARA_SEL41_SEL82_MASK (0x7FU)
#define | XBARA_SEL41_SEL82_SHIFT (0U)
#define | XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
#define | XBARA_SEL41_SEL83_MASK (0x7F00U)
#define | XBARA_SEL41_SEL83_SHIFT (8U)
#define | XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
SEL42 - Crossbar A Select Register 42
#define | XBARA_SEL42_SEL84_MASK (0x7FU)
#define | XBARA_SEL42_SEL84_SHIFT (0U)
#define | XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
#define | XBARA_SEL42_SEL85_MASK (0x7F00U)
#define | XBARA_SEL42_SEL85_SHIFT (8U)
#define | XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
SEL43 - Crossbar A Select Register 43
#define | XBARA_SEL43_SEL86_MASK (0x7FU)
#define | XBARA_SEL43_SEL86_SHIFT (0U)
#define | XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
#define | XBARA_SEL43_SEL87_MASK (0x7F00U)
#define | XBARA_SEL43_SEL87_SHIFT (8U)
#define | XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
SEL44 - Crossbar A Select Register 44
#define | XBARA_SEL44_SEL88_MASK (0x7FU)
#define | XBARA_SEL44_SEL88_SHIFT (0U)
#define | XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
#define | XBARA_SEL44_SEL89_MASK (0x7F00U)
#define | XBARA_SEL44_SEL89_SHIFT (8U)
#define | XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
SEL45 - Crossbar A Select Register 45
#define | XBARA_SEL45_SEL90_MASK (0x7FU)
#define | XBARA_SEL45_SEL90_SHIFT (0U)
#define | XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
#define | XBARA_SEL45_SEL91_MASK (0x7F00U)
#define | XBARA_SEL45_SEL91_SHIFT (8U)
#define | XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
SEL46 - Crossbar A Select Register 46
#define | XBARA_SEL46_SEL92_MASK (0x7FU)
#define | XBARA_SEL46_SEL92_SHIFT (0U)
#define | XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
#define | XBARA_SEL46_SEL93_MASK (0x7F00U)
#define | XBARA_SEL46_SEL93_SHIFT (8U)
#define | XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
SEL47 - Crossbar A Select Register 47
#define | XBARA_SEL47_SEL94_MASK (0x7FU)
#define | XBARA_SEL47_SEL94_SHIFT (0U)
#define | XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
#define | XBARA_SEL47_SEL95_MASK (0x7F00U)
#define | XBARA_SEL47_SEL95_SHIFT (8U)
#define | XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
SEL48 - Crossbar A Select Register 48
#define | XBARA_SEL48_SEL96_MASK (0x7FU)
#define | XBARA_SEL48_SEL96_SHIFT (0U)
#define | XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
#define | XBARA_SEL48_SEL97_MASK (0x7F00U)
#define | XBARA_SEL48_SEL97_SHIFT (8U)
#define | XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
SEL49 - Crossbar A Select Register 49
#define | XBARA_SEL49_SEL98_MASK (0x7FU)
#define | XBARA_SEL49_SEL98_SHIFT (0U)
#define | XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
#define | XBARA_SEL49_SEL99_MASK (0x7F00U)
#define | XBARA_SEL49_SEL99_SHIFT (8U)
#define | XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
SEL50 - Crossbar A Select Register 50
#define | XBARA_SEL50_SEL100_MASK (0x7FU)
#define | XBARA_SEL50_SEL100_SHIFT (0U)
#define | XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
#define | XBARA_SEL50_SEL101_MASK (0x7F00U)
#define | XBARA_SEL50_SEL101_SHIFT (8U)
#define | XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
SEL51 - Crossbar A Select Register 51
#define | XBARA_SEL51_SEL102_MASK (0x7FU)
#define | XBARA_SEL51_SEL102_SHIFT (0U)
#define | XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
#define | XBARA_SEL51_SEL103_MASK (0x7F00U)
#define | XBARA_SEL51_SEL103_SHIFT (8U)
#define | XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
SEL52 - Crossbar A Select Register 52
#define | XBARA_SEL52_SEL104_MASK (0x7FU)
#define | XBARA_SEL52_SEL104_SHIFT (0U)
#define | XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
#define | XBARA_SEL52_SEL105_MASK (0x7F00U)
#define | XBARA_SEL52_SEL105_SHIFT (8U)
#define | XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
SEL53 - Crossbar A Select Register 53
#define | XBARA_SEL53_SEL106_MASK (0x7FU)
#define | XBARA_SEL53_SEL106_SHIFT (0U)
#define | XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
#define | XBARA_SEL53_SEL107_MASK (0x7F00U)
#define | XBARA_SEL53_SEL107_SHIFT (8U)
#define | XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
SEL54 - Crossbar A Select Register 54
#define | XBARA_SEL54_SEL108_MASK (0x7FU)
#define | XBARA_SEL54_SEL108_SHIFT (0U)
#define | XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
#define | XBARA_SEL54_SEL109_MASK (0x7F00U)
#define | XBARA_SEL54_SEL109_SHIFT (8U)
#define | XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
SEL55 - Crossbar A Select Register 55
#define | XBARA_SEL55_SEL110_MASK (0x7FU)
#define | XBARA_SEL55_SEL110_SHIFT (0U)
#define | XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
#define | XBARA_SEL55_SEL111_MASK (0x7F00U)
#define | XBARA_SEL55_SEL111_SHIFT (8U)
#define | XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
SEL56 - Crossbar A Select Register 56
#define | XBARA_SEL56_SEL112_MASK (0x7FU)
#define | XBARA_SEL56_SEL112_SHIFT (0U)
#define | XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
#define | XBARA_SEL56_SEL113_MASK (0x7F00U)
#define | XBARA_SEL56_SEL113_SHIFT (8U)
#define | XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
SEL57 - Crossbar A Select Register 57
#define | XBARA_SEL57_SEL114_MASK (0x7FU)
#define | XBARA_SEL57_SEL114_SHIFT (0U)
#define | XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
#define | XBARA_SEL57_SEL115_MASK (0x7F00U)
#define | XBARA_SEL57_SEL115_SHIFT (8U)
#define | XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
SEL58 - Crossbar A Select Register 58
#define | XBARA_SEL58_SEL116_MASK (0x7FU)
#define | XBARA_SEL58_SEL116_SHIFT (0U)
#define | XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
#define | XBARA_SEL58_SEL117_MASK (0x7F00U)
#define | XBARA_SEL58_SEL117_SHIFT (8U)
#define | XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
SEL59 - Crossbar A Select Register 59
#define | XBARA_SEL59_SEL118_MASK (0x7FU)
#define | XBARA_SEL59_SEL118_SHIFT (0U)
#define | XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
#define | XBARA_SEL59_SEL119_MASK (0x7F00U)
#define | XBARA_SEL59_SEL119_SHIFT (8U)
#define | XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
SEL60 - Crossbar A Select Register 60
#define | XBARA_SEL60_SEL120_MASK (0x7FU)
#define | XBARA_SEL60_SEL120_SHIFT (0U)
#define | XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
#define | XBARA_SEL60_SEL121_MASK (0x7F00U)
#define | XBARA_SEL60_SEL121_SHIFT (8U)
#define | XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
SEL61 - Crossbar A Select Register 61
#define | XBARA_SEL61_SEL122_MASK (0x7FU)
#define | XBARA_SEL61_SEL122_SHIFT (0U)
#define | XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
#define | XBARA_SEL61_SEL123_MASK (0x7F00U)
#define | XBARA_SEL61_SEL123_SHIFT (8U)
#define | XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
SEL62 - Crossbar A Select Register 62
#define | XBARA_SEL62_SEL124_MASK (0x7FU)
#define | XBARA_SEL62_SEL124_SHIFT (0U)
#define | XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
#define | XBARA_SEL62_SEL125_MASK (0x7F00U)
#define | XBARA_SEL62_SEL125_SHIFT (8U)
#define | XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
SEL63 - Crossbar A Select Register 63
#define | XBARA_SEL63_SEL126_MASK (0x7FU)
#define | XBARA_SEL63_SEL126_SHIFT (0U)
#define | XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
#define | XBARA_SEL63_SEL127_MASK (0x7F00U)
#define | XBARA_SEL63_SEL127_SHIFT (8U)
#define | XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
SEL64 - Crossbar A Select Register 64
#define | XBARA_SEL64_SEL128_MASK (0x7FU)
#define | XBARA_SEL64_SEL128_SHIFT (0U)
#define | XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
#define | XBARA_SEL64_SEL129_MASK (0x7F00U)
#define | XBARA_SEL64_SEL129_SHIFT (8U)
#define | XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
SEL65 - Crossbar A Select Register 65
#define | XBARA_SEL65_SEL130_MASK (0x7FU)
#define | XBARA_SEL65_SEL130_SHIFT (0U)
#define | XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
#define | XBARA_SEL65_SEL131_MASK (0x7F00U)
#define | XBARA_SEL65_SEL131_SHIFT (8U)
#define | XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
CTRL0 - Crossbar A Control Register 0
#define | XBARA_CTRL0_DEN0_MASK (0x1U)
#define | XBARA_CTRL0_DEN0_SHIFT (0U)
#define | XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
#define | XBARA_CTRL0_IEN0_MASK (0x2U)
#define | XBARA_CTRL0_IEN0_SHIFT (1U)
#define | XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
#define | XBARA_CTRL0_EDGE0_MASK (0xCU)
#define | XBARA_CTRL0_EDGE0_SHIFT (2U)
#define | XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
#define | XBARA_CTRL0_STS0_MASK (0x10U)
#define | XBARA_CTRL0_STS0_SHIFT (4U)
#define | XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
#define | XBARA_CTRL0_DEN1_MASK (0x100U)
#define | XBARA_CTRL0_DEN1_SHIFT (8U)
#define | XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
#define | XBARA_CTRL0_IEN1_MASK (0x200U)
#define | XBARA_CTRL0_IEN1_SHIFT (9U)
#define | XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
#define | XBARA_CTRL0_EDGE1_MASK (0xC00U)
#define | XBARA_CTRL0_EDGE1_SHIFT (10U)
#define | XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
#define | XBARA_CTRL0_STS1_MASK (0x1000U)
#define | XBARA_CTRL0_STS1_SHIFT (12U)
#define | XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
CTRL1 - Crossbar A Control Register 1
#define | XBARA_CTRL1_DEN2_MASK (0x1U)
#define | XBARA_CTRL1_DEN2_SHIFT (0U)
#define | XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
#define | XBARA_CTRL1_IEN2_MASK (0x2U)
#define | XBARA_CTRL1_IEN2_SHIFT (1U)
#define | XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
#define | XBARA_CTRL1_EDGE2_MASK (0xCU)
#define | XBARA_CTRL1_EDGE2_SHIFT (2U)
#define | XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
#define | XBARA_CTRL1_STS2_MASK (0x10U)
#define | XBARA_CTRL1_STS2_SHIFT (4U)
#define | XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
#define | XBARA_CTRL1_DEN3_MASK (0x100U)
#define | XBARA_CTRL1_DEN3_SHIFT (8U)
#define | XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
#define | XBARA_CTRL1_IEN3_MASK (0x200U)
#define | XBARA_CTRL1_IEN3_SHIFT (9U)
#define | XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
#define | XBARA_CTRL1_EDGE3_MASK (0xC00U)
#define | XBARA_CTRL1_EDGE3_SHIFT (10U)
#define | XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
#define | XBARA_CTRL1_STS3_MASK (0x1000U)
#define | XBARA_CTRL1_STS3_SHIFT (12U)
#define | XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
SEL0 - Crossbar B Select Register 0
#define | XBARB_SEL0_SEL0_MASK (0x3FU)
#define | XBARB_SEL0_SEL0_SHIFT (0U)
#define | XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
#define | XBARB_SEL0_SEL1_MASK (0x3F00U)
#define | XBARB_SEL0_SEL1_SHIFT (8U)
#define | XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
SEL1 - Crossbar B Select Register 1
#define | XBARB_SEL1_SEL2_MASK (0x3FU)
#define | XBARB_SEL1_SEL2_SHIFT (0U)
#define | XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
#define | XBARB_SEL1_SEL3_MASK (0x3F00U)
#define | XBARB_SEL1_SEL3_SHIFT (8U)
#define | XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
SEL2 - Crossbar B Select Register 2
#define | XBARB_SEL2_SEL4_MASK (0x3FU)
#define | XBARB_SEL2_SEL4_SHIFT (0U)
#define | XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
#define | XBARB_SEL2_SEL5_MASK (0x3F00U)
#define | XBARB_SEL2_SEL5_SHIFT (8U)
#define | XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
SEL3 - Crossbar B Select Register 3
#define | XBARB_SEL3_SEL6_MASK (0x3FU)
#define | XBARB_SEL3_SEL6_SHIFT (0U)
#define | XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
#define | XBARB_SEL3_SEL7_MASK (0x3F00U)
#define | XBARB_SEL3_SEL7_SHIFT (8U)
#define | XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
SEL4 - Crossbar B Select Register 4
#define | XBARB_SEL4_SEL8_MASK (0x3FU)
#define | XBARB_SEL4_SEL8_SHIFT (0U)
#define | XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
#define | XBARB_SEL4_SEL9_MASK (0x3F00U)
#define | XBARB_SEL4_SEL9_SHIFT (8U)
#define | XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
SEL5 - Crossbar B Select Register 5
#define | XBARB_SEL5_SEL10_MASK (0x3FU)
#define | XBARB_SEL5_SEL10_SHIFT (0U)
#define | XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
#define | XBARB_SEL5_SEL11_MASK (0x3F00U)
#define | XBARB_SEL5_SEL11_SHIFT (8U)
#define | XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
SEL6 - Crossbar B Select Register 6
#define | XBARB_SEL6_SEL12_MASK (0x3FU)
#define | XBARB_SEL6_SEL12_SHIFT (0U)
#define | XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
#define | XBARB_SEL6_SEL13_MASK (0x3F00U)
#define | XBARB_SEL6_SEL13_SHIFT (8U)
#define | XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
SEL7 - Crossbar B Select Register 7
#define | XBARB_SEL7_SEL14_MASK (0x3FU)
#define | XBARB_SEL7_SEL14_SHIFT (0U)
#define | XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
#define | XBARB_SEL7_SEL15_MASK (0x3F00U)
#define | XBARB_SEL7_SEL15_SHIFT (8U)
#define | XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
LOWPWR_CTRL - XTAL OSC (LP) Control Register
#define | XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
#define | XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
#define | XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
#define | XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
#define | XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
#define | XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
#define | XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
#define | XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
#define | XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
#define | XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
#define | XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
#define | XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
#define | XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
#define | XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
#define | XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
#define | XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
#define | XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
#define | XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
#define | XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define | XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define | XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define | XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define | XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define | XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define | XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
#define | XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
#define | XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
#define | XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
#define | XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register
#define | XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
#define | XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register
#define | XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
#define | XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register
#define | XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
#define | XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
OSC_CONFIG0 - XTAL OSC Configuration 0 Register
#define | XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
#define | XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
#define | XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
#define | XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
#define | XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
#define | XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
#define | XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
#define | XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
#define | XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
#define | XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
#define | XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
#define | XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
#define | XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
#define | XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
#define | XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
#define | XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
#define | XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
#define | XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define | XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
#define | XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register
#define | XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
#define | XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
#define | XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
#define | XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
#define | XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
#define | XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
#define | XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
#define | XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
#define | XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
#define | XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
#define | XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
#define | XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
#define | XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
#define | XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
#define | XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
#define | XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
#define | XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
#define | XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define | XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
#define | XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register
#define | XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
#define | XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
#define | XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
#define | XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
#define | XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
#define | XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register
#define | XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
#define | XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
#define | XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
#define | XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
#define | XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
#define | XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
#define | XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
OSC_CONFIG1 - XTAL OSC Configuration 1 Register
#define | XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
#define | XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
#define | XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
#define | XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
#define | XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register
#define | XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
#define | XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
#define | XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
#define | XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
#define | XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register
#define | XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
#define | XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
#define | XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
#define | XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
#define | XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register
#define | XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
#define | XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
#define | XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
#define | XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
#define | XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
OSC_CONFIG2 - XTAL OSC Configuration 2 Register
#define | XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
#define | XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
#define | XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
#define | XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
#define | XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
#define | XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
#define | XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
#define | XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
#define | XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
#define | XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
#define | XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register
#define | XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
#define | XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
#define | XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
#define | XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
#define | XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
#define | XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
#define | XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
#define | XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
#define | XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
#define | XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
#define | XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register
#define | XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
#define | XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
#define | XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
#define | XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
#define | XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
#define | XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
#define | XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
#define | XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
#define | XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
#define | XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
#define | XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register
#define | XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
#define | XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
#define | XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
#define | XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
#define | XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
#define | XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
#define | XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
#define | XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
#define | XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
#define | XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
#define | XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
#define | XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)

## Typedefs

typedef enum IRQn | IRQn_Type
typedef enum _dma_request_source | dma_request_source_t
| Structure for the DMA hardware request. More...
typedef enum _iomuxc_sw_mux_ctl_pad | iomuxc_sw_mux_ctl_pad_t
| Enumeration for the IOMUXC SW_MUX_CTL_PAD. More...
typedef enum _iomuxc_sw_mux_ctl_pad_1 | iomuxc_sw_mux_ctl_pad_1_t
| Enumeration for the IOMUXC SW_MUX_CTL_PAD_1. More...
typedef enum _iomuxc_sw_pad_ctl_pad | iomuxc_sw_pad_ctl_pad_t
| Enumeration for the IOMUXC SW_PAD_CTL_PAD. More...
typedef enum _iomuxc_sw_pad_ctl_pad_1 | iomuxc_sw_pad_ctl_pad_1_t
| Enumeration for the IOMUXC SW_PAD_CTL_PAD_1. More...
typedef enum _iomuxc_select_input | iomuxc_select_input_t
| Enumeration for the IOMUXC select input. More...
typedef enum _iomuxc_select_input_1 | iomuxc_select_input_1_t
| Enumeration for the IOMUXC select input. More...
typedef enum _xbar_input_signal | xbar_input_signal_t
typedef enum _xbar_output_signal | xbar_output_signal_t

## Enumerations

enum

IRQn {
NotAvail_IRQn = -128, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
PendSV_IRQn = -2, SysTick_IRQn = -1, DMA0_DMA16_IRQn = 0, DMA1_DMA17_IRQn = 1,
DMA2_DMA18_IRQn = 2, DMA3_DMA19_IRQn = 3, DMA4_DMA20_IRQn = 4, DMA5_DMA21_IRQn = 5,
DMA6_DMA22_IRQn = 6, DMA7_DMA23_IRQn = 7, DMA8_DMA24_IRQn = 8, DMA9_DMA25_IRQn = 9,
DMA10_DMA26_IRQn = 10, DMA11_DMA27_IRQn = 11, DMA12_DMA28_IRQn = 12, DMA13_DMA29_IRQn = 13,
DMA14_DMA30_IRQn = 14, DMA15_DMA31_IRQn = 15, DMA_ERROR_IRQn = 16, CTI0_ERROR_IRQn = 17,
CTI1_ERROR_IRQn = 18, CORE_IRQn = 19, LPUART1_IRQn = 20, LPUART2_IRQn = 21,
LPUART3_IRQn = 22, LPUART4_IRQn = 23, LPUART5_IRQn = 24, LPUART6_IRQn = 25,
LPUART7_IRQn = 26, LPUART8_IRQn = 27, LPI2C1_IRQn = 28, LPI2C2_IRQn = 29,
LPI2C3_IRQn = 30, LPI2C4_IRQn = 31, LPSPI1_IRQn = 32, LPSPI2_IRQn = 33,
LPSPI3_IRQn = 34, LPSPI4_IRQn = 35, CAN1_IRQn = 36, CAN2_IRQn = 37,
FLEXRAM_IRQn = 38, KPP_IRQn = 39, TSC_DIG_IRQn = 40, GPR_IRQ_IRQn = 41,
LCDIF_IRQn = 42, CSI_IRQn = 43, PXP_IRQn = 44, WDOG2_IRQn = 45,
SNVS_HP_WRAPPER_IRQn = 46, SNVS_HP_WRAPPER_TZ_IRQn = 47, SNVS_LP_WRAPPER_IRQn = 48, CSU_IRQn = 49,
DCP_IRQn = 50, DCP_VMI_IRQn = 51, Reserved68_IRQn = 52, TRNG_IRQn = 53,
SJC_IRQn = 54, BEE_IRQn = 55, SAI1_IRQn = 56, SAI2_IRQn = 57,
SAI3_RX_IRQn = 58, SAI3_TX_IRQn = 59, SPDIF_IRQn = 60, PMU_EVENT_IRQn = 61,
Reserved78_IRQn = 62, TEMP_LOW_HIGH_IRQn = 63, TEMP_PANIC_IRQn = 64, USB_PHY1_IRQn = 65,
USB_PHY2_IRQn = 66, ADC1_IRQn = 67, ADC2_IRQn = 68, DCDC_IRQn = 69,
Reserved86_IRQn = 70, Reserved87_IRQn = 71, GPIO1_INT0_IRQn = 72, GPIO1_INT1_IRQn = 73,
GPIO1_INT2_IRQn = 74, GPIO1_INT3_IRQn = 75, GPIO1_INT4_IRQn = 76, GPIO1_INT5_IRQn = 77,
GPIO1_INT6_IRQn = 78, GPIO1_INT7_IRQn = 79, GPIO1_Combined_0_15_IRQn = 80, GPIO1_Combined_16_31_IRQn = 81,
GPIO2_Combined_0_15_IRQn = 82, GPIO2_Combined_16_31_IRQn = 83, GPIO3_Combined_0_15_IRQn = 84, GPIO3_Combined_16_31_IRQn = 85,
GPIO4_Combined_0_15_IRQn = 86, GPIO4_Combined_16_31_IRQn = 87, GPIO5_Combined_0_15_IRQn = 88, GPIO5_Combined_16_31_IRQn = 89,
FLEXIO1_IRQn = 90, FLEXIO2_IRQn = 91, WDOG1_IRQn = 92, RTWDOG_IRQn = 93,
EWM_IRQn = 94, CCM_1_IRQn = 95, CCM_2_IRQn = 96, GPC_IRQn = 97,
SRC_IRQn = 98, Reserved115_IRQn = 99, GPT1_IRQn = 100, GPT2_IRQn = 101,
PWM1_0_IRQn = 102, PWM1_1_IRQn = 103, PWM1_2_IRQn = 104, PWM1_3_IRQn = 105,
PWM1_FAULT_IRQn = 106, FLEXSPI2_IRQn = 107, FLEXSPI_IRQn = 108, SEMC_IRQn = 109,
USDHC1_IRQn = 110, USDHC2_IRQn = 111, USB_OTG2_IRQn = 112, USB_OTG1_IRQn = 113,
ENET_IRQn = 114, ENET_1588_Timer_IRQn = 115, XBAR1_IRQ_0_1_IRQn = 116, XBAR1_IRQ_2_3_IRQn = 117,
ADC_ETC_IRQ0_IRQn = 118, ADC_ETC_IRQ1_IRQn = 119, ADC_ETC_IRQ2_IRQn = 120, ADC_ETC_ERROR_IRQ_IRQn = 121,
PIT_IRQn = 122, ACMP1_IRQn = 123, ACMP2_IRQn = 124, ACMP3_IRQn = 125,
ACMP4_IRQn = 126, Reserved143_IRQn = 127, Reserved144_IRQn = 128, ENC1_IRQn = 129,
ENC2_IRQn = 130, ENC3_IRQn = 131, ENC4_IRQn = 132, TMR1_IRQn = 133,
TMR2_IRQn = 134, TMR3_IRQn = 135, TMR4_IRQn = 136, PWM2_0_IRQn = 137,
PWM2_1_IRQn = 138, PWM2_2_IRQn = 139, PWM2_3_IRQn = 140, PWM2_FAULT_IRQn = 141,
PWM3_0_IRQn = 142, PWM3_1_IRQn = 143, PWM3_2_IRQn = 144, PWM3_3_IRQn = 145,
PWM3_FAULT_IRQn = 146, PWM4_0_IRQn = 147, PWM4_1_IRQn = 148, PWM4_2_IRQn = 149,
PWM4_3_IRQn = 150, PWM4_FAULT_IRQn = 151, ENET2_IRQn = 152, ENET2_1588_Timer_IRQn = 153,
CAN3_IRQn = 154, Reserved171_IRQn = 155, FLEXIO3_IRQn = 156, GPIO6_7_8_9_IRQn = 157
}

enum

_dma_request_source {
kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, kDmaRequestMuxLPUART1Tx = 2|0x100U, kDmaRequestMuxLPUART1Rx = 3|0x100U,
kDmaRequestMuxLPUART3Tx = 4|0x100U, kDmaRequestMuxLPUART3Rx = 5|0x100U, kDmaRequestMuxLPUART5Tx = 6|0x100U, kDmaRequestMuxLPUART5Rx = 7|0x100U,
kDmaRequestMuxLPUART7Tx = 8|0x100U, kDmaRequestMuxLPUART7Rx = 9|0x100U, kDmaRequestMuxCAN3 = 11|0x100U, kDmaRequestMuxCSI = 12|0x100U,
kDmaRequestMuxLPSPI1Rx = 13|0x100U, kDmaRequestMuxLPSPI1Tx = 14|0x100U, kDmaRequestMuxLPSPI3Rx = 15|0x100U, kDmaRequestMuxLPSPI3Tx = 16|0x100U,
kDmaRequestMuxLPI2C1 = 17|0x100U, kDmaRequestMuxLPI2C3 = 18|0x100U, kDmaRequestMuxSai1Rx = 19|0x100U, kDmaRequestMuxSai1Tx = 20|0x100U,
kDmaRequestMuxSai2Rx = 21|0x100U, kDmaRequestMuxSai2Tx = 22|0x100U, kDmaRequestMuxADC_ETC = 23|0x100U, kDmaRequestMuxADC1 = 24|0x100U,
kDmaRequestMuxACMP1 = 25|0x100U, kDmaRequestMuxACMP3 = 26|0x100U, kDmaRequestMuxFlexSPIRx = 28|0x100U, kDmaRequestMuxFlexSPITx = 29|0x100U,
kDmaRequestMuxXBAR1Request0 = 30|0x100U, kDmaRequestMuxXBAR1Request1 = 31|0x100U, kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U,
kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U,
kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U,
kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U,
kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,
kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U,
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U,
kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, kDmaRequestMuxFlexSPI2Rx = 60|0x100U, kDmaRequestMuxFlexSPI2Tx = 61|0x100U,
kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, kDmaRequestMuxLPUART2Tx = 66|0x100U, kDmaRequestMuxLPUART2Rx = 67|0x100U,
kDmaRequestMuxLPUART4Tx = 68|0x100U, kDmaRequestMuxLPUART4Rx = 69|0x100U, kDmaRequestMuxLPUART6Tx = 70|0x100U, kDmaRequestMuxLPUART6Rx = 71|0x100U,
kDmaRequestMuxLPUART8Tx = 72|0x100U, kDmaRequestMuxLPUART8Rx = 73|0x100U, kDmaRequestMuxPxp = 75|0x100U, kDmaRequestMuxLCDIF = 76|0x100U,
kDmaRequestMuxLPSPI2Rx = 77|0x100U, kDmaRequestMuxLPSPI2Tx = 78|0x100U, kDmaRequestMuxLPSPI4Rx = 79|0x100U, kDmaRequestMuxLPSPI4Tx = 80|0x100U,
kDmaRequestMuxLPI2C2 = 81|0x100U, kDmaRequestMuxLPI2C4 = 82|0x100U, kDmaRequestMuxSai3Rx = 83|0x100U, kDmaRequestMuxSai3Tx = 84|0x100U,
kDmaRequestMuxSpdifRx = 85|0x100U, kDmaRequestMuxSpdifTx = 86|0x100U, kDmaRequestMuxADC2 = 88|0x100U, kDmaRequestMuxACMP2 = 89|0x100U,
kDmaRequestMuxACMP4 = 90|0x100U, kDmaRequestMuxEnetTimer0 = 92|0x100U, kDmaRequestMuxEnetTimer1 = 93|0x100U, kDmaRequestMuxXBAR1Request2 = 94|0x100U,
kDmaRequestMuxXBAR1Request3 = 95|0x100U, kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U,
kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U,
kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U,
kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U,
kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,
kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U,
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U,
kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, kDmaRequestMuxEnet2Timer0 = 124|0x100U, kDmaRequestMuxEnet2Timer1 = 125|0x100U
}

| Structure for the DMA hardware request. More...

enum

_iomuxc_sw_mux_ctl_pad {
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U
}

| Enumeration for the IOMUXC SW_MUX_CTL_PAD. More...

enum

_iomuxc_sw_mux_ctl_pad_1 {
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00 = 0U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01 = 1U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02 = 2U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03 = 3U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04 = 4U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05 = 5U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06 = 6U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07 = 7U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08 = 8U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09 = 9U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10 = 10U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11 = 11U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12 = 12U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13 = 13U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00 = 14U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01 = 15U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02 = 16U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03 = 17U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04 = 18U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05 = 19U,
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06 = 20U, kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07 = 21U
}

| Enumeration for the IOMUXC SW_MUX_CTL_PAD_1. More...

enum

_iomuxc_sw_pad_ctl_pad {
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U
}

| Enumeration for the IOMUXC SW_PAD_CTL_PAD. More...

enum

_iomuxc_sw_pad_ctl_pad_1 {
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00 = 0U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01 = 1U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02 = 2U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03 = 3U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04 = 4U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05 = 5U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06 = 6U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07 = 7U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08 = 8U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09 = 9U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10 = 10U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11 = 11U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12 = 12U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13 = 13U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00 = 14U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01 = 15U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02 = 16U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03 = 17U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04 = 18U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05 = 19U,
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06 = 20U, kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07 = 21U
}

| Enumeration for the IOMUXC SW_PAD_CTL_PAD_1. More...

enum

_iomuxc_select_input {
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U,
kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U,
kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U,
kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U,
kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U,
kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U,
kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U,
kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U,
kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U,
kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U,
kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U,
kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U,
kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U,
kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U,
kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U,
kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U,
kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U,
kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U,
kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U,
kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U,
kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U,
kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U,
kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U,
kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, kIOMUXC_NMI_SELECT_INPUT = 93U, kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U,
kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U,
kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U,
kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U,
kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U,
kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U,
kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U,
kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U,
kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U,
kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U,
kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U,
kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U,
kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U,
kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U,
kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U,
kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U
}

| Enumeration for the IOMUXC select input. More...

enum

_iomuxc_select_input_1 {
kIOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT = 0U, kIOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT = 1U, kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 = 2U, kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 = 3U,
kIOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT = 4U, kIOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT = 5U, kIOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 = 6U, kIOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT = 7U,
kIOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT = 8U, kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 9U, kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 10U, kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 11U,
kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 12U, kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT = 13U, kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT = 14U, kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT = 15U,
kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT = 16U, kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT = 17U, kIOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT = 18U, kIOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT = 19U,
kIOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT = 20U, kIOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT = 21U, kIOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT = 22U, kIOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT = 23U,
kIOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT = 24U, kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 25U, kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 26U, kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 27U,
kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 28U, kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 29U, kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 30U, kIOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT = 31U,
kIOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT = 32U
}

| Enumeration for the IOMUXC select input. More...

enum

_xbar_input_signal {
kXBARA1_InputLogicLow = 0|0x100U, kXBARA1_InputLogicHigh = 1|0x100U, kXBARA1_InputIomuxXbarIn02 = 2|0x100U, kXBARA1_InputIomuxXbarIn03 = 3|0x100U,
kXBARA1_InputIomuxXbarInout04 = 4|0x100U, kXBARA1_InputIomuxXbarInout05 = 5|0x100U, kXBARA1_InputIomuxXbarInout06 = 6|0x100U, kXBARA1_InputIomuxXbarInout07 = 7|0x100U,
kXBARA1_InputIomuxXbarInout08 = 8|0x100U, kXBARA1_InputIomuxXbarInout09 = 9|0x100U, kXBARA1_InputIomuxXbarInout10 = 10|0x100U, kXBARA1_InputIomuxXbarInout11 = 11|0x100U,
kXBARA1_InputIomuxXbarInout12 = 12|0x100U, kXBARA1_InputIomuxXbarInout13 = 13|0x100U, kXBARA1_InputIomuxXbarInout14 = 14|0x100U, kXBARA1_InputIomuxXbarInout15 = 15|0x100U,
kXBARA1_InputIomuxXbarInout16 = 16|0x100U, kXBARA1_InputIomuxXbarInout17 = 17|0x100U, kXBARA1_InputIomuxXbarInout18 = 18|0x100U, kXBARA1_InputIomuxXbarInout19 = 19|0x100U,
kXBARA1_InputIomuxXbarIn20 = 20|0x100U, kXBARA1_InputIomuxXbarIn21 = 21|0x100U, kXBARA1_InputIomuxXbarIn22 = 22|0x100U, kXBARA1_InputIomuxXbarIn23 = 23|0x100U,
kXBARA1_InputIomuxXbarIn24 = 24|0x100U, kXBARA1_InputIomuxXbarIn25 = 25|0x100U, kXBARA1_InputAcmp1Out = 26|0x100U, kXBARA1_InputAcmp2Out = 27|0x100U,
kXBARA1_InputAcmp3Out = 28|0x100U, kXBARA1_InputAcmp4Out = 29|0x100U, kXBARA1_InputRESERVED30 = 30|0x100U, kXBARA1_InputRESERVED31 = 31|0x100U,
kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, kXBARA1_InputQtimer3Tmr3Output = 35|0x100U,
kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, kXBARA1_InputQtimer4Tmr3Output = 39|0x100U,
kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U,
kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U,
kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U,
kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U,
kXBARA1_InputPitTrigger0 = 56|0x100U, kXBARA1_InputPitTrigger1 = 57|0x100U, kXBARA1_InputPitTrigger2 = 58|0x100U, kXBARA1_InputPitTrigger3 = 59|0x100U,
kXBARA1_InputEnc1PosMatch = 60|0x100U, kXBARA1_InputEnc2PosMatch = 61|0x100U, kXBARA1_InputEnc3PosMatch = 62|0x100U, kXBARA1_InputEnc4PosMatch = 63|0x100U,
kXBARA1_InputDmaDone0 = 64|0x100U, kXBARA1_InputDmaDone1 = 65|0x100U, kXBARA1_InputDmaDone2 = 66|0x100U, kXBARA1_InputDmaDone3 = 67|0x100U,
kXBARA1_InputDmaDone4 = 68|0x100U, kXBARA1_InputDmaDone5 = 69|0x100U, kXBARA1_InputDmaDone6 = 70|0x100U, kXBARA1_InputDmaDone7 = 71|0x100U,
kXBARA1_InputAoi1Out0 = 72|0x100U, kXBARA1_InputAoi1Out1 = 73|0x100U, kXBARA1_InputAoi1Out2 = 74|0x100U, kXBARA1_InputAoi1Out3 = 75|0x100U,
kXBARA1_InputAoi2Out0 = 76|0x100U, kXBARA1_InputAoi2Out1 = 77|0x100U, kXBARA1_InputAoi2Out2 = 78|0x100U, kXBARA1_InputAoi2Out3 = 79|0x100U,
kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U,
kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U,
kXBARB2_InputLogicLow = 0|0x200U, kXBARB2_InputLogicHigh = 1|0x200U, kXBARB2_InputRESERVED2 = 2|0x200U, kXBARB2_InputRESERVED3 = 3|0x200U,
kXBARB2_InputRESERVED4 = 4|0x200U, kXBARB2_InputRESERVED5 = 5|0x200U, kXBARB2_InputAcmp1Out = 6|0x200U, kXBARB2_InputAcmp2Out = 7|0x200U,
kXBARB2_InputAcmp3Out = 8|0x200U, kXBARB2_InputAcmp4Out = 9|0x200U, kXBARB2_InputRESERVED10 = 10|0x200U, kXBARB2_InputRESERVED11 = 11|0x200U,
kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, kXBARB2_InputQtimer3Tmr3Output = 15|0x200U,
kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, kXBARB2_InputQtimer4Tmr3Output = 19|0x200U,
kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U,
kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U,
kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U,
kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U,
kXBARB2_InputPitTrigger0 = 36|0x200U, kXBARB2_InputPitTrigger1 = 37|0x200U, kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U,
kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U,
kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, kXBARB2_InputEnc1PosMatch = 46|0x200U, kXBARB2_InputEnc2PosMatch = 47|0x200U,
kXBARB2_InputEnc3PosMatch = 48|0x200U, kXBARB2_InputEnc4PosMatch = 49|0x200U, kXBARB2_InputDmaDone0 = 50|0x200U, kXBARB2_InputDmaDone1 = 51|0x200U,
kXBARB2_InputDmaDone2 = 52|0x200U, kXBARB2_InputDmaDone3 = 53|0x200U, kXBARB2_InputDmaDone4 = 54|0x200U, kXBARB2_InputDmaDone5 = 55|0x200U,
kXBARB2_InputDmaDone6 = 56|0x200U, kXBARB2_InputDmaDone7 = 57|0x200U, kXBARB3_InputLogicLow = 0|0x300U, kXBARB3_InputLogicHigh = 1|0x300U,
kXBARB3_InputRESERVED2 = 2|0x300U, kXBARB3_InputRESERVED3 = 3|0x300U, kXBARB3_InputRESERVED4 = 4|0x300U, kXBARB3_InputRESERVED5 = 5|0x300U,
kXBARB3_InputAcmp1Out = 6|0x300U, kXBARB3_InputAcmp2Out = 7|0x300U, kXBARB3_InputAcmp3Out = 8|0x300U, kXBARB3_InputAcmp4Out = 9|0x300U,
kXBARB3_InputRESERVED10 = 10|0x300U, kXBARB3_InputRESERVED11 = 11|0x300U, kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, kXBARB3_InputQtimer3Tmr1Output = 13|0x300U,
kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, kXBARB3_InputQtimer4Tmr1Output = 17|0x300U,
kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U,
kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U,
kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U,
kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U,
kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, kXBARB3_InputPitTrigger0 = 36|0x300U, kXBARB3_InputPitTrigger1 = 37|0x300U,
kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U,
kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U,
kXBARB3_InputEnc1PosMatch = 46|0x300U, kXBARB3_InputEnc2PosMatch = 47|0x300U, kXBARB3_InputEnc3PosMatch = 48|0x300U, kXBARB3_InputEnc4PosMatch = 49|0x300U,
kXBARB3_InputDmaDone0 = 50|0x300U, kXBARB3_InputDmaDone1 = 51|0x300U, kXBARB3_InputDmaDone2 = 52|0x300U, kXBARB3_InputDmaDone3 = 53|0x300U,
kXBARB3_InputDmaDone4 = 54|0x300U, kXBARB3_InputDmaDone5 = 55|0x300U, kXBARB3_InputDmaDone6 = 56|0x300U, kXBARB3_InputDmaDone7 = 57|0x300U
}

enum

_xbar_output_signal {
kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, kXBARA1_OutputDmaChMuxReq95 = 3|0x100U,
kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, kXBARA1_OutputIomuxXbarInout07 = 7|0x100U,
kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, kXBARA1_OutputIomuxXbarInout11 = 11|0x100U,
kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, kXBARA1_OutputIomuxXbarInout15 = 15|0x100U,
kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, kXBARA1_OutputIomuxXbarInout19 = 19|0x100U,
kXBARA1_OutputAcmp1Sample = 20|0x100U, kXBARA1_OutputAcmp2Sample = 21|0x100U, kXBARA1_OutputAcmp3Sample = 22|0x100U, kXBARA1_OutputAcmp4Sample = 23|0x100U,
kXBARA1_OutputRESERVED24 = 24|0x100U, kXBARA1_OutputRESERVED25 = 25|0x100U, kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U,
kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U,
kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U,
kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U,
kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U,
kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U,
kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U,
kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U,
kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U,
kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U,
kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, kXBARA1_OutputEnc1PhaseBInput = 67|0x100U,
kXBARA1_OutputEnc1Index = 68|0x100U, kXBARA1_OutputEnc1Home = 69|0x100U, kXBARA1_OutputEnc1Trigger = 70|0x100U, kXBARA1_OutputEnc2PhaseAInput = 71|0x100U,
kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, kXBARA1_OutputEnc2Index = 73|0x100U, kXBARA1_OutputEnc2Home = 74|0x100U, kXBARA1_OutputEnc2Trigger = 75|0x100U,
kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, kXBARA1_OutputEnc3Index = 78|0x100U, kXBARA1_OutputEnc3Home = 79|0x100U,
kXBARA1_OutputEnc3Trigger = 80|0x100U, kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, kXBARA1_OutputEnc4Index = 83|0x100U,
kXBARA1_OutputEnc4Home = 84|0x100U, kXBARA1_OutputEnc4Trigger = 85|0x100U, kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U,
kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U,
kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U,
kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U,
kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, kXBARA1_OutputEwmEwmIn = 102|0x100U, kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U,
kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U,
kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, kXBARA1_OutputLpi2c1TrgInput = 111|0x100U,
kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, kXBARA1_OutputLpspi1TrgInput = 115|0x100U,
kXBARA1_OutputLpspi2TrgInput = 116|0x100U, kXBARA1_OutputLpspi3TrgInput = 117|0x100U, kXBARA1_OutputLpspi4TrgInput = 118|0x100U, kXBARA1_OutputLpuart1TrgInput = 119|0x100U,
kXBARA1_OutputLpuart2TrgInput = 120|0x100U, kXBARA1_OutputLpuart3TrgInput = 121|0x100U, kXBARA1_OutputLpuart4TrgInput = 122|0x100U, kXBARA1_OutputLpuart5TrgInput = 123|0x100U,
kXBARA1_OutputLpuart6TrgInput = 124|0x100U, kXBARA1_OutputLpuart7TrgInput = 125|0x100U, kXBARA1_OutputLpuart8TrgInput = 126|0x100U, kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U,
kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, kXBARB2_OutputAoi1In00 = 0|0x200U,
kXBARB2_OutputAoi1In01 = 1|0x200U, kXBARB2_OutputAoi1In02 = 2|0x200U, kXBARB2_OutputAoi1In03 = 3|0x200U, kXBARB2_OutputAoi1In04 = 4|0x200U,
kXBARB2_OutputAoi1In05 = 5|0x200U, kXBARB2_OutputAoi1In06 = 6|0x200U, kXBARB2_OutputAoi1In07 = 7|0x200U, kXBARB2_OutputAoi1In08 = 8|0x200U,
kXBARB2_OutputAoi1In09 = 9|0x200U, kXBARB2_OutputAoi1In10 = 10|0x200U, kXBARB2_OutputAoi1In11 = 11|0x200U, kXBARB2_OutputAoi1In12 = 12|0x200U,
kXBARB2_OutputAoi1In13 = 13|0x200U, kXBARB2_OutputAoi1In14 = 14|0x200U, kXBARB2_OutputAoi1In15 = 15|0x200U, kXBARB3_OutputAoi2In00 = 0|0x300U,
kXBARB3_OutputAoi2In01 = 1|0x300U, kXBARB3_OutputAoi2In02 = 2|0x300U, kXBARB3_OutputAoi2In03 = 3|0x300U, kXBARB3_OutputAoi2In04 = 4|0x300U,
kXBARB3_OutputAoi2In05 = 5|0x300U, kXBARB3_OutputAoi2In06 = 6|0x300U, kXBARB3_OutputAoi2In07 = 7|0x300U, kXBARB3_OutputAoi2In08 = 8|0x300U,
kXBARB3_OutputAoi2In09 = 9|0x300U, kXBARB3_OutputAoi2In10 = 10|0x300U, kXBARB3_OutputAoi2In11 = 11|0x300U, kXBARB3_OutputAoi2In12 = 12|0x300U,
kXBARB3_OutputAoi2In13 = 13|0x300U, kXBARB3_OutputAoi2In14 = 14|0x300U, kXBARB3_OutputAoi2In15 = 15|0x300U
}

## Detailed Description

CMSIS Peripheral Access Layer for MIMXRT1062.

Version
  1.2

Date
  2019-04-29 CMSIS Peripheral Access Layer for MIMXRT1062

Definition in file MIMXRT1062.h.

## Macro Definition Documentation

## ◆ _MIMXRT1062_H_

#define _MIMXRT1062_H_

Symbol preventing repeated inclusion

Definition at line 53 of file MIMXRT1062.h.

## ◆ MCU_MEM_MAP_VERSION

#define MCU_MEM_MAP_VERSION 0x0100U

Memory map major version (memory maps with equal major version number are compatible)

Definition at line 57 of file MIMXRT1062.h.

## ◆ MCU_MEM_MAP_VERSION_MINOR

#define MCU_MEM_MAP_VERSION_MINOR 0x0002U

Memory map minor version

Definition at line 59 of file MIMXRT1062.h.