Callisto4Bootloader: Trace Port Interface (TPI)

Callisto4Bootloader

Modules | Data Structures
Trace Port Interface (TPI)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT)

Type definitions for the Trace Port Interface (TPI) More...

## Modules

| Floating Point Unit (FPU)
| Type definitions for the Floating Point Unit (FPU)

## Data Structures

struct | TPI_Type
| Structure type to access the Trace Port Interface Register (TPI). More...
#define | TPI_ACPR_PRESCALER_Pos 0U
#define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define | TPI_SPPR_TXMODE_Pos 0U
#define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define | TPI_FFSR_FtNonStop_Pos 3U
#define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define | TPI_FFSR_TCPresent_Pos 2U
#define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
#define | TPI_FFSR_FtStopped_Pos 1U
#define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
#define | TPI_FFSR_FlInProg_Pos 0U
#define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define | TPI_FFCR_TrigIn_Pos 8U
#define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
#define | TPI_FFCR_EnFCont_Pos 1U
#define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
#define | TPI_TRIGGER_TRIGGER_Pos 0U
#define | TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define | TPI_FIFO0_ITM_ATVALID_Pos 29U
#define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define | TPI_FIFO0_ITM_bytecount_Pos 27U
#define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define | TPI_FIFO0_ETM_ATVALID_Pos 26U
#define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define | TPI_FIFO0_ETM_bytecount_Pos 24U
#define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define | TPI_FIFO0_ETM2_Pos 16U
#define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define | TPI_FIFO0_ETM1_Pos 8U
#define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define | TPI_FIFO0_ETM0_Pos 0U
#define | TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define | TPI_ITATBCTR2_ATREADY_Pos 0U
#define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)
#define | TPI_FIFO1_ITM_ATVALID_Pos 29U
#define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define | TPI_FIFO1_ITM_bytecount_Pos 27U
#define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define | TPI_FIFO1_ETM_ATVALID_Pos 26U
#define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define | TPI_FIFO1_ETM_bytecount_Pos 24U
#define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define | TPI_FIFO1_ITM2_Pos 16U
#define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define | TPI_FIFO1_ITM1_Pos 8U
#define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define | TPI_FIFO1_ITM0_Pos 0U
#define | TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define | TPI_ITATBCTR0_ATREADY_Pos 0U
#define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)
#define | TPI_ITCTRL_Mode_Pos 0U
#define | TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define | TPI_DEVID_NRZVALID_Pos 11U
#define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define | TPI_DEVID_MANCVALID_Pos 10U
#define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define | TPI_DEVID_PTINVALID_Pos 9U
#define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define | TPI_DEVID_MinBufSz_Pos 6U
#define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define | TPI_DEVID_AsynClkIn_Pos 5U
#define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define | TPI_DEVID_NrTraceInput_Pos 0U
#define | TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define | TPI_DEVTYPE_MajorType_Pos 4U
#define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define | TPI_DEVTYPE_SubType_Pos 0U
#define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define | TPI_ACPR_SWOSCALER_Pos 0U
#define | TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define | TPI_SPPR_TXMODE_Pos 0U
#define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define | TPI_FFSR_FtNonStop_Pos 3U
#define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define | TPI_FFSR_TCPresent_Pos 2U
#define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
#define | TPI_FFSR_FtStopped_Pos 1U
#define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
#define | TPI_FFSR_FlInProg_Pos 0U
#define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define | TPI_FFCR_TrigIn_Pos 8U
#define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
#define | TPI_FFCR_FOnMan_Pos 6U
#define | TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
#define | TPI_FFCR_EnFCont_Pos 1U
#define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
#define | TPI_PSCR_PSCount_Pos 0U
#define | TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define | TPI_LSR_nTT_Pos 1U
#define | TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
#define | TPI_LSR_SLK_Pos 1U
#define | TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
#define | TPI_LSR_SLI_Pos 0U
#define | TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define | TPI_DEVID_NRZVALID_Pos 11U
#define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define | TPI_DEVID_MANCVALID_Pos 10U
#define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define | TPI_DEVID_PTINVALID_Pos 9U
#define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define | TPI_DEVID_FIFOSZ_Pos 6U
#define | TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define | TPI_DEVTYPE_SubType_Pos 4U
#define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define | TPI_DEVTYPE_MajorType_Pos 0U
#define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define | TPI_ACPR_SWOSCALER_Pos 0U
#define | TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define | TPI_SPPR_TXMODE_Pos 0U
#define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define | TPI_FFSR_FtNonStop_Pos 3U
#define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define | TPI_FFSR_TCPresent_Pos 2U
#define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
#define | TPI_FFSR_FtStopped_Pos 1U
#define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
#define | TPI_FFSR_FlInProg_Pos 0U
#define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define | TPI_FFCR_TrigIn_Pos 8U
#define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
#define | TPI_FFCR_FOnMan_Pos 6U
#define | TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
#define | TPI_FFCR_EnFCont_Pos 1U
#define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
#define | TPI_PSCR_PSCount_Pos 0U
#define | TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define | TPI_LSR_nTT_Pos 1U
#define | TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
#define | TPI_LSR_SLK_Pos 1U
#define | TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
#define | TPI_LSR_SLI_Pos 0U
#define | TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define | TPI_DEVID_NRZVALID_Pos 11U
#define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define | TPI_DEVID_MANCVALID_Pos 10U
#define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define | TPI_DEVID_PTINVALID_Pos 9U
#define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define | TPI_DEVID_FIFOSZ_Pos 6U
#define | TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define | TPI_DEVTYPE_SubType_Pos 4U
#define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define | TPI_DEVTYPE_MajorType_Pos 0U
#define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define | TPI_ACPR_PRESCALER_Pos 0U
#define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define | TPI_SPPR_TXMODE_Pos 0U
#define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define | TPI_FFSR_FtNonStop_Pos 3U
#define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define | TPI_FFSR_TCPresent_Pos 2U
#define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
#define | TPI_FFSR_FtStopped_Pos 1U
#define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
#define | TPI_FFSR_FlInProg_Pos 0U
#define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define | TPI_FFCR_TrigIn_Pos 8U
#define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
#define | TPI_FFCR_EnFCont_Pos 1U
#define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
#define | TPI_TRIGGER_TRIGGER_Pos 0U
#define | TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define | TPI_FIFO0_ITM_ATVALID_Pos 29U
#define | TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define | TPI_FIFO0_ITM_bytecount_Pos 27U
#define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define | TPI_FIFO0_ETM_ATVALID_Pos 26U
#define | TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define | TPI_FIFO0_ETM_bytecount_Pos 24U
#define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define | TPI_FIFO0_ETM2_Pos 16U
#define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define | TPI_FIFO0_ETM1_Pos 8U
#define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define | TPI_FIFO0_ETM0_Pos 0U
#define | TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define | TPI_ITATBCTR2_ATREADY2_Pos 0U
#define | TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
#define | TPI_ITATBCTR2_ATREADY1_Pos 0U
#define | TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
#define | TPI_FIFO1_ITM_ATVALID_Pos 29U
#define | TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define | TPI_FIFO1_ITM_bytecount_Pos 27U
#define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define | TPI_FIFO1_ETM_ATVALID_Pos 26U
#define | TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define | TPI_FIFO1_ETM_bytecount_Pos 24U
#define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define | TPI_FIFO1_ITM2_Pos 16U
#define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define | TPI_FIFO1_ITM1_Pos 8U
#define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define | TPI_FIFO1_ITM0_Pos 0U
#define | TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define | TPI_ITATBCTR0_ATREADY2_Pos 0U
#define | TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
#define | TPI_ITATBCTR0_ATREADY1_Pos 0U
#define | TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
#define | TPI_ITCTRL_Mode_Pos 0U
#define | TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define | TPI_DEVID_NRZVALID_Pos 11U
#define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define | TPI_DEVID_MANCVALID_Pos 10U
#define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define | TPI_DEVID_PTINVALID_Pos 9U
#define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define | TPI_DEVID_MinBufSz_Pos 6U
#define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define | TPI_DEVID_AsynClkIn_Pos 5U
#define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define | TPI_DEVID_NrTraceInput_Pos 0U
#define | TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define | TPI_DEVTYPE_SubType_Pos 4U
#define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define | TPI_DEVTYPE_MajorType_Pos 0U
#define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

## Detailed Description

Type definitions for the Trace Port Interface (TPI)

## Macro Definition Documentation

## ◆ TPI_ACPR_PRESCALER_Msk [1/2]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1297 of file core_cm7.h.

## ◆ TPI_ACPR_PRESCALER_Msk [2/2]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1417 of file core_armv81mml.h.

## ◆ TPI_ACPR_PRESCALER_Pos [1/2]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1296 of file core_cm7.h.

## ◆ TPI_ACPR_PRESCALER_Pos [2/2]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1416 of file core_armv81mml.h.

## ◆ TPI_ACPR_SWOSCALER_Msk [1/2]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 745 of file core_armv8mbl.h.

## ◆ TPI_ACPR_SWOSCALER_Msk [2/2]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1312 of file core_armv8mml.h.

## ◆ TPI_ACPR_SWOSCALER_Pos [1/2]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 744 of file core_armv8mbl.h.

## ◆ TPI_ACPR_SWOSCALER_Pos [2/2]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 1311 of file core_armv8mml.h.

## ◆ TPI_DEVID_AsynClkIn_Msk [1/2]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1403 of file core_cm7.h.

## ◆ TPI_DEVID_AsynClkIn_Msk [2/2]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1517 of file core_armv81mml.h.

## ◆ TPI_DEVID_AsynClkIn_Pos [1/2]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1402 of file core_cm7.h.

## ◆ TPI_DEVID_AsynClkIn_Pos [2/2]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1516 of file core_armv81mml.h.

## ◆ TPI_DEVID_FIFOSZ_Msk [1/2]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 799 of file core_armv8mbl.h.

## ◆ TPI_DEVID_FIFOSZ_Msk [2/2]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 1366 of file core_armv8mml.h.

## ◆ TPI_DEVID_FIFOSZ_Pos [1/2]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 798 of file core_armv8mbl.h.

## ◆ TPI_DEVID_FIFOSZ_Pos [2/2]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 1365 of file core_armv8mml.h.

## ◆ TPI_DEVID_MANCVALID_Msk [1/4]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 793 of file core_armv8mbl.h.

## ◆ TPI_DEVID_MANCVALID_Msk [2/4]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1360 of file core_armv8mml.h.

## ◆ TPI_DEVID_MANCVALID_Msk [3/4]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1394 of file core_cm7.h.

## ◆ TPI_DEVID_MANCVALID_Msk [4/4]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1508 of file core_armv81mml.h.

## ◆ TPI_DEVID_MANCVALID_Pos [1/4]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 792 of file core_armv8mbl.h.

## ◆ TPI_DEVID_MANCVALID_Pos [2/4]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1359 of file core_armv8mml.h.

## ◆ TPI_DEVID_MANCVALID_Pos [3/4]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1393 of file core_cm7.h.

## ◆ TPI_DEVID_MANCVALID_Pos [4/4]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1507 of file core_armv81mml.h.

## ◆ TPI_DEVID_MinBufSz_Msk [1/2]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1400 of file core_cm7.h.

## ◆ TPI_DEVID_MinBufSz_Msk [2/2]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1514 of file core_armv81mml.h.

## ◆ TPI_DEVID_MinBufSz_Pos [1/2]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1399 of file core_cm7.h.

## ◆ TPI_DEVID_MinBufSz_Pos [2/2]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1513 of file core_armv81mml.h.

## ◆ TPI_DEVID_NrTraceInput_Msk [1/2]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1406 of file core_cm7.h.

## ◆ TPI_DEVID_NrTraceInput_Msk [2/2]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1520 of file core_armv81mml.h.

## ◆ TPI_DEVID_NrTraceInput_Pos [1/2]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1405 of file core_cm7.h.

## ◆ TPI_DEVID_NrTraceInput_Pos [2/2]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1519 of file core_armv81mml.h.

## ◆ TPI_DEVID_NRZVALID_Msk [1/4]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 790 of file core_armv8mbl.h.

## ◆ TPI_DEVID_NRZVALID_Msk [2/4]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1357 of file core_armv8mml.h.

## ◆ TPI_DEVID_NRZVALID_Msk [3/4]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1391 of file core_cm7.h.

## ◆ TPI_DEVID_NRZVALID_Msk [4/4]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1505 of file core_armv81mml.h.

## ◆ TPI_DEVID_NRZVALID_Pos [1/4]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 789 of file core_armv8mbl.h.

## ◆ TPI_DEVID_NRZVALID_Pos [2/4]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1356 of file core_armv8mml.h.

## ◆ TPI_DEVID_NRZVALID_Pos [3/4]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1390 of file core_cm7.h.

## ◆ TPI_DEVID_NRZVALID_Pos [4/4]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1504 of file core_armv81mml.h.

## ◆ TPI_DEVID_PTINVALID_Msk [1/4]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 796 of file core_armv8mbl.h.

## ◆ TPI_DEVID_PTINVALID_Msk [2/4]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1363 of file core_armv8mml.h.

## ◆ TPI_DEVID_PTINVALID_Msk [3/4]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1397 of file core_cm7.h.

## ◆ TPI_DEVID_PTINVALID_Msk [4/4]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1511 of file core_armv81mml.h.

## ◆ TPI_DEVID_PTINVALID_Pos [1/4]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 795 of file core_armv8mbl.h.

## ◆ TPI_DEVID_PTINVALID_Pos [2/4]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1362 of file core_armv8mml.h.

## ◆ TPI_DEVID_PTINVALID_Pos [3/4]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1396 of file core_cm7.h.

## ◆ TPI_DEVID_PTINVALID_Pos [4/4]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1510 of file core_armv81mml.h.

## ◆ TPI_DEVTYPE_MajorType_Msk [1/4]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 806 of file core_armv8mbl.h.

## ◆ TPI_DEVTYPE_MajorType_Msk [2/4]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1373 of file core_armv8mml.h.

## ◆ TPI_DEVTYPE_MajorType_Msk [3/4]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1413 of file core_cm7.h.

## ◆ TPI_DEVTYPE_MajorType_Msk [4/4]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1524 of file core_armv81mml.h.

## ◆ TPI_DEVTYPE_MajorType_Pos [1/4]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position

Definition at line 805 of file core_armv8mbl.h.

## ◆ TPI_DEVTYPE_MajorType_Pos [2/4]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position

Definition at line 1372 of file core_armv8mml.h.

## ◆ TPI_DEVTYPE_MajorType_Pos [3/4]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position

Definition at line 1412 of file core_cm7.h.

## ◆ TPI_DEVTYPE_MajorType_Pos [4/4]

#define TPI_DEVTYPE_MajorType_Pos 4U

TPI DEVTYPE: MajorType Position

Definition at line 1523 of file core_armv81mml.h.

## ◆ TPI_DEVTYPE_SubType_Msk [1/4]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 803 of file core_armv8mbl.h.

## ◆ TPI_DEVTYPE_SubType_Msk [2/4]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1370 of file core_armv8mml.h.

## ◆ TPI_DEVTYPE_SubType_Msk [3/4]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1410 of file core_cm7.h.

## ◆ TPI_DEVTYPE_SubType_Msk [4/4]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1527 of file core_armv81mml.h.

## ◆ TPI_DEVTYPE_SubType_Pos [1/4]

#define TPI_DEVTYPE_SubType_Pos 4U

TPI DEVTYPE: SubType Position

Definition at line 802 of file core_armv8mbl.h.

## ◆ TPI_DEVTYPE_SubType_Pos [2/4]

#define TPI_DEVTYPE_SubType_Pos 4U

TPI DEVTYPE: SubType Position

Definition at line 1369 of file core_armv8mml.h.

## ◆ TPI_DEVTYPE_SubType_Pos [3/4]

#define TPI_DEVTYPE_SubType_Pos 4U

TPI DEVTYPE: SubType Position

Definition at line 1409 of file core_cm7.h.

## ◆ TPI_DEVTYPE_SubType_Pos [4/4]

#define TPI_DEVTYPE_SubType_Pos 0U

TPI DEVTYPE: SubType Position

Definition at line 1526 of file core_armv81mml.h.

## ◆ TPI_FFCR_EnFCont_Msk [1/4]

#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 772 of file core_armv8mbl.h.

## ◆ TPI_FFCR_EnFCont_Msk [2/4]

#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1321 of file core_cm7.h.

## ◆ TPI_FFCR_EnFCont_Msk [3/4]

#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1339 of file core_armv8mml.h.

## ◆ TPI_FFCR_EnFCont_Msk [4/4]

#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1441 of file core_armv81mml.h.

## ◆ TPI_FFCR_EnFCont_Pos [1/4]

#define TPI_FFCR_EnFCont_Pos 1U

TPI FFCR: EnFCont Position

Definition at line 771 of file core_armv8mbl.h.

## ◆ TPI_FFCR_EnFCont_Pos [2/4]

#define TPI_FFCR_EnFCont_Pos 1U

TPI FFCR: EnFCont Position

Definition at line 1320 of file core_cm7.h.

## ◆ TPI_FFCR_EnFCont_Pos [3/4]

#define TPI_FFCR_EnFCont_Pos 1U

TPI FFCR: EnFCont Position

Definition at line 1338 of file core_armv8mml.h.

## ◆ TPI_FFCR_EnFCont_Pos [4/4]

#define TPI_FFCR_EnFCont_Pos 1U

TPI FFCR: EnFCont Position

Definition at line 1440 of file core_armv81mml.h.

## ◆ TPI_FFCR_FOnMan_Msk [1/2]

#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 769 of file core_armv8mbl.h.

## ◆ TPI_FFCR_FOnMan_Msk [2/2]

#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1336 of file core_armv8mml.h.

## ◆ TPI_FFCR_FOnMan_Pos [1/2]

#define TPI_FFCR_FOnMan_Pos 6U

TPI FFCR: FOnMan Position

Definition at line 768 of file core_armv8mbl.h.

## ◆ TPI_FFCR_FOnMan_Pos [2/2]

#define TPI_FFCR_FOnMan_Pos 6U

TPI FFCR: FOnMan Position

Definition at line 1335 of file core_armv8mml.h.

## ◆ TPI_FFCR_TrigIn_Msk [1/4]

#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 766 of file core_armv8mbl.h.

## ◆ TPI_FFCR_TrigIn_Msk [2/4]

#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1318 of file core_cm7.h.

## ◆ TPI_FFCR_TrigIn_Msk [3/4]

#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1333 of file core_armv8mml.h.

## ◆ TPI_FFCR_TrigIn_Msk [4/4]

#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1438 of file core_armv81mml.h.

## ◆ TPI_FFCR_TrigIn_Pos [1/4]

#define TPI_FFCR_TrigIn_Pos 8U

TPI FFCR: TrigIn Position

Definition at line 765 of file core_armv8mbl.h.

## ◆ TPI_FFCR_TrigIn_Pos [2/4]

#define TPI_FFCR_TrigIn_Pos 8U

TPI FFCR: TrigIn Position

Definition at line 1317 of file core_cm7.h.

## ◆ TPI_FFCR_TrigIn_Pos [3/4]

#define TPI_FFCR_TrigIn_Pos 8U

TPI FFCR: TrigIn Position

Definition at line 1332 of file core_armv8mml.h.

## ◆ TPI_FFCR_TrigIn_Pos [4/4]

#define TPI_FFCR_TrigIn_Pos 8U

TPI FFCR: TrigIn Position

Definition at line 1437 of file core_armv81mml.h.

## ◆ TPI_FFSR_FlInProg_Msk [1/4]

#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 762 of file core_armv8mbl.h.

## ◆ TPI_FFSR_FlInProg_Msk [2/4]

#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1314 of file core_cm7.h.

## ◆ TPI_FFSR_FlInProg_Msk [3/4]

#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1329 of file core_armv8mml.h.

## ◆ TPI_FFSR_FlInProg_Msk [4/4]

#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1434 of file core_armv81mml.h.

## ◆ TPI_FFSR_FlInProg_Pos [1/4]

#define TPI_FFSR_FlInProg_Pos 0U

TPI FFSR: FlInProg Position

Definition at line 761 of file core_armv8mbl.h.

## ◆ TPI_FFSR_FlInProg_Pos [2/4]

#define TPI_FFSR_FlInProg_Pos 0U

TPI FFSR: FlInProg Position

Definition at line 1313 of file core_cm7.h.

## ◆ TPI_FFSR_FlInProg_Pos [3/4]

#define TPI_FFSR_FlInProg_Pos 0U

TPI FFSR: FlInProg Position

Definition at line 1328 of file core_armv8mml.h.

## ◆ TPI_FFSR_FlInProg_Pos [4/4]

#define TPI_FFSR_FlInProg_Pos 0U

TPI FFSR: FlInProg Position

Definition at line 1433 of file core_armv81mml.h.

## ◆ TPI_FFSR_FtNonStop_Msk [1/4]

#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 753 of file core_armv8mbl.h.

## ◆ TPI_FFSR_FtNonStop_Msk [2/4]

#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1305 of file core_cm7.h.

## ◆ TPI_FFSR_FtNonStop_Msk [3/4]

#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1320 of file core_armv8mml.h.

## ◆ TPI_FFSR_FtNonStop_Msk [4/4]

#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1425 of file core_armv81mml.h.

## ◆ TPI_FFSR_FtNonStop_Pos [1/4]

#define TPI_FFSR_FtNonStop_Pos 3U

TPI FFSR: FtNonStop Position

Definition at line 752 of file core_armv8mbl.h.

## ◆ TPI_FFSR_FtNonStop_Pos [2/4]

#define TPI_FFSR_FtNonStop_Pos 3U

TPI FFSR: FtNonStop Position

Definition at line 1304 of file core_cm7.h.

## ◆ TPI_FFSR_FtNonStop_Pos [3/4]

#define TPI_FFSR_FtNonStop_Pos 3U

TPI FFSR: FtNonStop Position

Definition at line 1319 of file core_armv8mml.h.

## ◆ TPI_FFSR_FtNonStop_Pos [4/4]

#define TPI_FFSR_FtNonStop_Pos 3U

TPI FFSR: FtNonStop Position

Definition at line 1424 of file core_armv81mml.h.

## ◆ TPI_FFSR_FtStopped_Msk [1/4]

#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 759 of file core_armv8mbl.h.

## ◆ TPI_FFSR_FtStopped_Msk [2/4]

#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1311 of file core_cm7.h.

## ◆ TPI_FFSR_FtStopped_Msk [3/4]

#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1326 of file core_armv8mml.h.

## ◆ TPI_FFSR_FtStopped_Msk [4/4]

#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1431 of file core_armv81mml.h.

## ◆ TPI_FFSR_FtStopped_Pos [1/4]

#define TPI_FFSR_FtStopped_Pos 1U

TPI FFSR: FtStopped Position

Definition at line 758 of file core_armv8mbl.h.

## ◆ TPI_FFSR_FtStopped_Pos [2/4]

#define TPI_FFSR_FtStopped_Pos 1U

TPI FFSR: FtStopped Position

Definition at line 1310 of file core_cm7.h.

## ◆ TPI_FFSR_FtStopped_Pos [3/4]

#define TPI_FFSR_FtStopped_Pos 1U

TPI FFSR: FtStopped Position

Definition at line 1325 of file core_armv8mml.h.

## ◆ TPI_FFSR_FtStopped_Pos [4/4]

#define TPI_FFSR_FtStopped_Pos 1U

TPI FFSR: FtStopped Position

Definition at line 1430 of file core_armv81mml.h.

## ◆ TPI_FFSR_TCPresent_Msk [1/4]

#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 756 of file core_armv8mbl.h.

## ◆ TPI_FFSR_TCPresent_Msk [2/4]

#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1308 of file core_cm7.h.

## ◆ TPI_FFSR_TCPresent_Msk [3/4]

#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1323 of file core_armv8mml.h.

## ◆ TPI_FFSR_TCPresent_Msk [4/4]

#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1428 of file core_armv81mml.h.

## ◆ TPI_FFSR_TCPresent_Pos [1/4]

#define TPI_FFSR_TCPresent_Pos 2U

TPI FFSR: TCPresent Position

Definition at line 755 of file core_armv8mbl.h.

## ◆ TPI_FFSR_TCPresent_Pos [2/4]

#define TPI_FFSR_TCPresent_Pos 2U

TPI FFSR: TCPresent Position

Definition at line 1307 of file core_cm7.h.

## ◆ TPI_FFSR_TCPresent_Pos [3/4]

#define TPI_FFSR_TCPresent_Pos 2U

TPI FFSR: TCPresent Position

Definition at line 1322 of file core_armv8mml.h.

## ◆ TPI_FFSR_TCPresent_Pos [4/4]

#define TPI_FFSR_TCPresent_Pos 2U

TPI FFSR: TCPresent Position

Definition at line 1427 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM0_Msk [1/2]

#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

Definition at line 1347 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM0_Msk [2/2]

#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

Definition at line 1467 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM0_Pos [1/2]

#define TPI_FIFO0_ETM0_Pos 0U

TPI FIFO0: ETM0 Position

Definition at line 1346 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM0_Pos [2/2]

#define TPI_FIFO0_ETM0_Pos 0U

TPI FIFO0: ETM0 Position

Definition at line 1466 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM1_Msk [1/2]

#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

Definition at line 1344 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM1_Msk [2/2]

#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

Definition at line 1464 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM1_Pos [1/2]

#define TPI_FIFO0_ETM1_Pos 8U

TPI FIFO0: ETM1 Position

Definition at line 1343 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM1_Pos [2/2]

#define TPI_FIFO0_ETM1_Pos 8U

TPI FIFO0: ETM1 Position

Definition at line 1463 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM2_Msk [1/2]

#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

Definition at line 1341 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM2_Msk [2/2]

#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

Definition at line 1461 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM2_Pos [1/2]

#define TPI_FIFO0_ETM2_Pos 16U

TPI FIFO0: ETM2 Position

Definition at line 1340 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM2_Pos [2/2]

#define TPI_FIFO0_ETM2_Pos 16U

TPI FIFO0: ETM2 Position

Definition at line 1460 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM_ATVALID_Msk [1/2]

#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

Definition at line 1335 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM_ATVALID_Msk [2/2]

#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

Definition at line 1455 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM_ATVALID_Pos [1/2]

#define TPI_FIFO0_ETM_ATVALID_Pos 26U

TPI FIFO0: ETM_ATVALID Position

Definition at line 1334 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM_ATVALID_Pos [2/2]

#define TPI_FIFO0_ETM_ATVALID_Pos 26U

TPI FIFO0: ETM_ATVALID Position

Definition at line 1454 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM_bytecount_Msk [1/2]

#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

Definition at line 1338 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM_bytecount_Msk [2/2]

#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

Definition at line 1458 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ETM_bytecount_Pos [1/2]

#define TPI_FIFO0_ETM_bytecount_Pos 24U

TPI FIFO0: ETM_bytecount Position

Definition at line 1337 of file core_cm7.h.

## ◆ TPI_FIFO0_ETM_bytecount_Pos [2/2]

#define TPI_FIFO0_ETM_bytecount_Pos 24U

TPI FIFO0: ETM_bytecount Position

Definition at line 1457 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ITM_ATVALID_Msk [1/2]

#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

Definition at line 1329 of file core_cm7.h.

## ◆ TPI_FIFO0_ITM_ATVALID_Msk [2/2]

#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

Definition at line 1449 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ITM_ATVALID_Pos [1/2]

#define TPI_FIFO0_ITM_ATVALID_Pos 29U

TPI FIFO0: ITM_ATVALID Position

Definition at line 1328 of file core_cm7.h.

## ◆ TPI_FIFO0_ITM_ATVALID_Pos [2/2]

#define TPI_FIFO0_ITM_ATVALID_Pos 29U

TPI FIFO0: ITM_ATVALID Position

Definition at line 1448 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ITM_bytecount_Msk [1/2]

#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

Definition at line 1332 of file core_cm7.h.

## ◆ TPI_FIFO0_ITM_bytecount_Msk [2/2]

#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

Definition at line 1452 of file core_armv81mml.h.

## ◆ TPI_FIFO0_ITM_bytecount_Pos [1/2]

#define TPI_FIFO0_ITM_bytecount_Pos 27U

TPI FIFO0: ITM_bytecount Position

Definition at line 1331 of file core_cm7.h.

## ◆ TPI_FIFO0_ITM_bytecount_Pos [2/2]

#define TPI_FIFO0_ITM_bytecount_Pos 27U

TPI FIFO0: ITM_bytecount Position

Definition at line 1451 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ETM_ATVALID_Msk [1/2]

#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

Definition at line 1364 of file core_cm7.h.

## ◆ TPI_FIFO1_ETM_ATVALID_Msk [2/2]

#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

Definition at line 1481 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ETM_ATVALID_Pos [1/2]

#define TPI_FIFO1_ETM_ATVALID_Pos 26U

TPI FIFO1: ETM_ATVALID Position

Definition at line 1363 of file core_cm7.h.

## ◆ TPI_FIFO1_ETM_ATVALID_Pos [2/2]

#define TPI_FIFO1_ETM_ATVALID_Pos 26U

TPI FIFO1: ETM_ATVALID Position

Definition at line 1480 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ETM_bytecount_Msk [1/2]

#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

Definition at line 1367 of file core_cm7.h.

## ◆ TPI_FIFO1_ETM_bytecount_Msk [2/2]

#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

Definition at line 1484 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ETM_bytecount_Pos [1/2]

#define TPI_FIFO1_ETM_bytecount_Pos 24U

TPI FIFO1: ETM_bytecount Position

Definition at line 1366 of file core_cm7.h.

## ◆ TPI_FIFO1_ETM_bytecount_Pos [2/2]

#define TPI_FIFO1_ETM_bytecount_Pos 24U

TPI FIFO1: ETM_bytecount Position

Definition at line 1483 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM0_Msk [1/2]

#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

Definition at line 1376 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM0_Msk [2/2]

#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

Definition at line 1493 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM0_Pos [1/2]

#define TPI_FIFO1_ITM0_Pos 0U

TPI FIFO1: ITM0 Position

Definition at line 1375 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM0_Pos [2/2]

#define TPI_FIFO1_ITM0_Pos 0U

TPI FIFO1: ITM0 Position

Definition at line 1492 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM1_Msk [1/2]

#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

Definition at line 1373 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM1_Msk [2/2]

#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

Definition at line 1490 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM1_Pos [1/2]

#define TPI_FIFO1_ITM1_Pos 8U

TPI FIFO1: ITM1 Position

Definition at line 1372 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM1_Pos [2/2]

#define TPI_FIFO1_ITM1_Pos 8U

TPI FIFO1: ITM1 Position

Definition at line 1489 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM2_Msk [1/2]

#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

Definition at line 1370 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM2_Msk [2/2]

#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

Definition at line 1487 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM2_Pos [1/2]

#define TPI_FIFO1_ITM2_Pos 16U

TPI FIFO1: ITM2 Position

Definition at line 1369 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM2_Pos [2/2]

#define TPI_FIFO1_ITM2_Pos 16U

TPI FIFO1: ITM2 Position

Definition at line 1486 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM_ATVALID_Msk [1/2]

#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

Definition at line 1358 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM_ATVALID_Msk [2/2]

#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

Definition at line 1475 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM_ATVALID_Pos [1/2]

#define TPI_FIFO1_ITM_ATVALID_Pos 29U

TPI FIFO1: ITM_ATVALID Position

Definition at line 1357 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM_ATVALID_Pos [2/2]

#define TPI_FIFO1_ITM_ATVALID_Pos 29U

TPI FIFO1: ITM_ATVALID Position

Definition at line 1474 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM_bytecount_Msk [1/2]

#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

Definition at line 1361 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM_bytecount_Msk [2/2]

#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

Definition at line 1478 of file core_armv81mml.h.

## ◆ TPI_FIFO1_ITM_bytecount_Pos [1/2]

#define TPI_FIFO1_ITM_bytecount_Pos 27U

TPI FIFO1: ITM_bytecount Position

Definition at line 1360 of file core_cm7.h.

## ◆ TPI_FIFO1_ITM_bytecount_Pos [2/2]

#define TPI_FIFO1_ITM_bytecount_Pos 27U

TPI FIFO1: ITM_bytecount Position

Definition at line 1477 of file core_armv81mml.h.

## ◆ TPI_ITATBCTR0_ATREADY1_Msk

#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

Definition at line 1383 of file core_cm7.h.

## ◆ TPI_ITATBCTR0_ATREADY1_Pos

#define TPI_ITATBCTR0_ATREADY1_Pos 0U

TPI ITATBCTR0: ATREADY1 Position

Definition at line 1382 of file core_cm7.h.

## ◆ TPI_ITATBCTR0_ATREADY2_Msk

#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

Definition at line 1380 of file core_cm7.h.

## ◆ TPI_ITATBCTR0_ATREADY2_Pos

#define TPI_ITATBCTR0_ATREADY2_Pos 0U

TPI ITATBCTR0: ATREADY2 Position

Definition at line 1379 of file core_cm7.h.

## ◆ TPI_ITATBCTR0_ATREADY_Msk

#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)

TPI ITATBCTR0: ATREADY Mask

Definition at line 1497 of file core_armv81mml.h.

## ◆ TPI_ITATBCTR0_ATREADY_Pos

#define TPI_ITATBCTR0_ATREADY_Pos 0U

TPI ITATBCTR0: ATREADY Position

Definition at line 1496 of file core_armv81mml.h.

## ◆ TPI_ITATBCTR2_ATREADY1_Msk

#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

Definition at line 1354 of file core_cm7.h.

## ◆ TPI_ITATBCTR2_ATREADY1_Pos

#define TPI_ITATBCTR2_ATREADY1_Pos 0U

TPI ITATBCTR2: ATREADY1 Position

Definition at line 1353 of file core_cm7.h.

## ◆ TPI_ITATBCTR2_ATREADY2_Msk

#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

Definition at line 1351 of file core_cm7.h.

## ◆ TPI_ITATBCTR2_ATREADY2_Pos

#define TPI_ITATBCTR2_ATREADY2_Pos 0U

TPI ITATBCTR2: ATREADY2 Position

Definition at line 1350 of file core_cm7.h.

## ◆ TPI_ITATBCTR2_ATREADY_Msk

#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)

TPI ITATBCTR2: ATREADY Mask

Definition at line 1471 of file core_armv81mml.h.

## ◆ TPI_ITATBCTR2_ATREADY_Pos

#define TPI_ITATBCTR2_ATREADY_Pos 0U

TPI ITATBCTR2: ATREADY Position

Definition at line 1470 of file core_armv81mml.h.

## ◆ TPI_ITCTRL_Mode_Msk [1/2]

#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1387 of file core_cm7.h.

## ◆ TPI_ITCTRL_Mode_Msk [2/2]

#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1501 of file core_armv81mml.h.

## ◆ TPI_ITCTRL_Mode_Pos [1/2]

#define TPI_ITCTRL_Mode_Pos 0U

TPI ITCTRL: Mode Position

Definition at line 1386 of file core_cm7.h.

## ◆ TPI_ITCTRL_Mode_Pos [2/2]

#define TPI_ITCTRL_Mode_Pos 0U

TPI ITCTRL: Mode Position

Definition at line 1500 of file core_armv81mml.h.

## ◆ TPI_LSR_nTT_Msk [1/2]

#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 780 of file core_armv8mbl.h.

## ◆ TPI_LSR_nTT_Msk [2/2]

#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1347 of file core_armv8mml.h.

## ◆ TPI_LSR_nTT_Pos [1/2]

#define TPI_LSR_nTT_Pos 1U

TPI LSR: Not thirty-two bit. Position

Definition at line 779 of file core_armv8mbl.h.

## ◆ TPI_LSR_nTT_Pos [2/2]

#define TPI_LSR_nTT_Pos 1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1346 of file core_armv8mml.h.

## ◆ TPI_LSR_SLI_Msk [1/2]

#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 786 of file core_armv8mbl.h.

## ◆ TPI_LSR_SLI_Msk [2/2]

#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1353 of file core_armv8mml.h.

## ◆ TPI_LSR_SLI_Pos [1/2]

#define TPI_LSR_SLI_Pos 0U

TPI LSR: Software Lock implemented Position

Definition at line 785 of file core_armv8mbl.h.

## ◆ TPI_LSR_SLI_Pos [2/2]

#define TPI_LSR_SLI_Pos 0U

TPI LSR: Software Lock implemented Position

Definition at line 1352 of file core_armv8mml.h.

## ◆ TPI_LSR_SLK_Msk [1/2]

#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 783 of file core_armv8mbl.h.

## ◆ TPI_LSR_SLK_Msk [2/2]

#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1350 of file core_armv8mml.h.

## ◆ TPI_LSR_SLK_Pos [1/2]

#define TPI_LSR_SLK_Pos 1U

TPI LSR: Software Lock status Position

Definition at line 782 of file core_armv8mbl.h.

## ◆ TPI_LSR_SLK_Pos [2/2]

#define TPI_LSR_SLK_Pos 1U

TPI LSR: Software Lock status Position

Definition at line 1349 of file core_armv8mml.h.

## ◆ TPI_PSCR_PSCount_Msk [1/2]

#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 776 of file core_armv8mbl.h.

## ◆ TPI_PSCR_PSCount_Msk [2/2]

#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1343 of file core_armv8mml.h.

## ◆ TPI_PSCR_PSCount_Pos [1/2]

#define TPI_PSCR_PSCount_Pos 0U

TPI PSCR: PSCount Position

Definition at line 775 of file core_armv8mbl.h.

## ◆ TPI_PSCR_PSCount_Pos [2/2]

#define TPI_PSCR_PSCount_Pos 0U

TPI PSCR: PSCount Position

Definition at line 1342 of file core_armv8mml.h.

## ◆ TPI_SPPR_TXMODE_Msk [1/4]

#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 749 of file core_armv8mbl.h.

## ◆ TPI_SPPR_TXMODE_Msk [2/4]

#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1301 of file core_cm7.h.

## ◆ TPI_SPPR_TXMODE_Msk [3/4]

#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1316 of file core_armv8mml.h.

## ◆ TPI_SPPR_TXMODE_Msk [4/4]

#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1421 of file core_armv81mml.h.

## ◆ TPI_SPPR_TXMODE_Pos [1/4]

#define TPI_SPPR_TXMODE_Pos 0U

TPI SPPR: TXMODE Position

Definition at line 748 of file core_armv8mbl.h.

## ◆ TPI_SPPR_TXMODE_Pos [2/4]

#define TPI_SPPR_TXMODE_Pos 0U

TPI SPPR: TXMODE Position

Definition at line 1300 of file core_cm7.h.

## ◆ TPI_SPPR_TXMODE_Pos [3/4]

#define TPI_SPPR_TXMODE_Pos 0U

TPI SPPR: TXMODE Position

Definition at line 1315 of file core_armv8mml.h.

## ◆ TPI_SPPR_TXMODE_Pos [4/4]

#define TPI_SPPR_TXMODE_Pos 0U

TPI SPPR: TXMODE Position

Definition at line 1420 of file core_armv81mml.h.

## ◆ TPI_TRIGGER_TRIGGER_Msk [1/2]

#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1325 of file core_cm7.h.

## ◆ TPI_TRIGGER_TRIGGER_Msk [2/2]

#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1445 of file core_armv81mml.h.

## ◆ TPI_TRIGGER_TRIGGER_Pos [1/2]

#define TPI_TRIGGER_TRIGGER_Pos 0U

TPI TRIGGER: TRIGGER Position

Definition at line 1324 of file core_cm7.h.

## ◆ TPI_TRIGGER_TRIGGER_Pos [2/2]

#define TPI_TRIGGER_TRIGGER_Pos 0U

TPI TRIGGER: TRIGGER Position

Definition at line 1444 of file core_armv81mml.h.