Callisto4Bootloader: IOMUXC_SNVS Register Masks

Callisto4Bootloader

IOMUXC_SNVS Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » IOMUXC_SNVS Peripheral Access Layer

## SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register

#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)

## SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register

#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)

## SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register

#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)

## SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register

#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)

## SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register

#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)

## SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register

#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)

## SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register

#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)

## SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register

#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)

## SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register

#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)

## Detailed Description

## Macro Definition Documentation

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5

Definition at line 24440 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)

Definition at line 24434 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)

Definition at line 24435 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad PMIC_ON_REQ 0b0..Input Path is determined by functionality

Definition at line 24447 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)

Definition at line 24441 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)

Definition at line 24442 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5

Definition at line 24458 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)

Definition at line 24452 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)

Definition at line 24453 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad PMIC_STBY_REQ 0b0..Input Path is determined by functionality

Definition at line 24465 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)

Definition at line 24459 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)

Definition at line 24460 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue

Definition at line 24422 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)

Definition at line 24416 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)

Definition at line 24417 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad WAKEUP 0b0..Input Path is determined by functionality

Definition at line 24429 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)

Definition at line 24423 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)

Definition at line 24424 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)

DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.nosp@m..8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7

Definition at line 24623 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)

Definition at line 24611 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)

Definition at line 24612 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled

Definition at line 24666 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)

Definition at line 24660 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)

Definition at line 24661 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled

Definition at line 24636 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)

Definition at line 24630 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)

Definition at line 24631 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

Definition at line 24643 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)

Definition at line 24637 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)

Definition at line 24638 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull

Definition at line 24650 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)

Definition at line 24644 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)

Definition at line 24645 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

Definition at line 24659 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)

Definition at line 24651 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)

Definition at line 24652 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)

SPEED - Speed Field 0b10..medium(100MHz)

Definition at line 24629 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)

Definition at line 24624 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)

Definition at line 24625 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

Definition at line 24610 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)

Definition at line 24604 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)

Definition at line 24605 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)

DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.nosp@m..8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7

Definition at line 24757 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)

Definition at line 24745 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)

Definition at line 24746 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled

Definition at line 24800 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)

Definition at line 24794 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)

Definition at line 24795 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled

Definition at line 24770 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)

Definition at line 24764 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)

Definition at line 24765 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

Definition at line 24777 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)

Definition at line 24771 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)

Definition at line 24772 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull

Definition at line 24784 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)

Definition at line 24778 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)

Definition at line 24779 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

Definition at line 24793 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)

Definition at line 24785 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)

Definition at line 24786 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)

SPEED - Speed Field 0b10..medium(100MHz)

Definition at line 24763 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)

Definition at line 24758 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)

Definition at line 24759 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

Definition at line 24744 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)

Definition at line 24738 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)

Definition at line 24739 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)

DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.nosp@m..8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7

Definition at line 24824 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)

Definition at line 24812 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)

Definition at line 24813 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled

Definition at line 24867 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)

Definition at line 24861 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)

Definition at line 24862 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled

Definition at line 24837 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)

Definition at line 24831 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)

Definition at line 24832 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

Definition at line 24844 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)

Definition at line 24838 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)

Definition at line 24839 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull

Definition at line 24851 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)

Definition at line 24845 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)

Definition at line 24846 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

Definition at line 24860 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)

Definition at line 24852 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)

Definition at line 24853 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)

SPEED - Speed Field 0b10..medium(100MHz)

Definition at line 24830 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)

Definition at line 24825 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)

Definition at line 24826 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

Definition at line 24811 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)

Definition at line 24805 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)

Definition at line 24806 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)

DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.nosp@m..8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7

Definition at line 24556 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)

Definition at line 24544 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)

Definition at line 24545 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled

Definition at line 24599 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)

Definition at line 24593 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)

Definition at line 24594 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled

Definition at line 24569 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)

Definition at line 24563 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)

Definition at line 24564 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

Definition at line 24576 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)

Definition at line 24570 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)

Definition at line 24571 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull

Definition at line 24583 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)

Definition at line 24577 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)

Definition at line 24578 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

Definition at line 24592 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)

Definition at line 24584 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)

Definition at line 24585 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)

SPEED - Speed Field 0b10..medium(100MHz)

Definition at line 24562 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)

Definition at line 24557 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)

Definition at line 24558 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

Definition at line 24543 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)

Definition at line 24537 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)

Definition at line 24538 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)

DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.nosp@m..8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7

Definition at line 24489 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)

Definition at line 24477 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)

Definition at line 24478 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled

Definition at line 24532 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)

Definition at line 24526 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)

Definition at line 24527 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled

Definition at line 24502 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)

Definition at line 24496 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)

Definition at line 24497 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

Definition at line 24509 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)

Definition at line 24503 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)

Definition at line 24504 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull

Definition at line 24516 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)

Definition at line 24510 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)

Definition at line 24511 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

Definition at line 24525 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)

Definition at line 24517 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)

Definition at line 24518 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)

SPEED - Speed Field 0b10..medium(100MHz)

Definition at line 24495 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)

Definition at line 24490 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)

Definition at line 24491 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

Definition at line 24476 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)

Definition at line 24470 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)

Definition at line 24471 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)

DSE - Drive Strength Field 0b000..output driver disabled; 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.nosp@m..8V, 240 Ohm for DDR) 0b010..R0/2 0b011..R0/3 0b100..R0/4 0b101..R0/5 0b110..R0/6 0b111..R0/7

Definition at line 24690 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)

Definition at line 24678 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)

Definition at line 24679 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled 0b1..Hysteresis Enabled

Definition at line 24733 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)

Definition at line 24727 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)

Definition at line 24728 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled 0b1..Open Drain Enabled

Definition at line 24703 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)

Definition at line 24697 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)

Definition at line 24698 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

Definition at line 24710 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)

Definition at line 24704 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)

Definition at line 24705 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Keeper 0b1..Pull

Definition at line 24717 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)

Definition at line 24711 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)

Definition at line 24712 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

Definition at line 24726 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)

Definition at line 24718 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)

Definition at line 24719 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)

SPEED - Speed Field 0b10..medium(100MHz)

Definition at line 24696 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)

Definition at line 24691 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)

Definition at line 24692 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE | ( |  | x | ) | (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

Definition at line 24677 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)

Definition at line 24671 of file MIMXRT1062.h.

## ◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)

Definition at line 24672 of file MIMXRT1062.h.