/* * Copyright (C) 2012 Freescale Semiconductor, Inc. * * Configuration settings for the Freescale i.MX6Q SabreSD board. * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MX6_HORIZON_COMMON_CONFIG_H #define __MX6_HORIZON_COMMON_CONFIG_H #include "mx6_common.h" #define CONFIG_IMX_THERMAL /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RMII #ifdef CONFIG_DM_ETH #define CONFIG_ETHPRIME "eth0" #else #define CONFIG_ETHPRIME "FEC" #endif #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC #define CONFIG_IPADDR 192.168.1.103 #define CONFIG_SERVERIP 192.168.1.101 #define CONFIG_NETMASK 255.255.255.0 #ifdef CONFIG_MX6S #define SYS_NOSMP "nosmp" #else #define SYS_NOSMP #endif /* Command definition */ #define CONFIG_CMD_BMODE #ifdef CONFIG_NAND_BOOT #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " #else #define MFG_NAND_PARTITION "" #endif #define CONFIG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs console=" CONSOLE_DEV ",115200 " \ "rdinit=/linuxrc " \ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ "g_mass_storage.iSerialNumber=\"\" "\ "enable_wait_mode=off "\ MFG_NAND_PARTITION \ "\0" \ "initrd_addr=0x12C00000\0" \ "initrd_high=0xffffffff\0" \ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ #ifdef CONFIG_SUPPORT_EMMC_BOOT #define EMMC_ENV \ "emmcdev=2\0" \ "update_emmc_firmware=" \ "if test ${ip_dyn} = yes; then " \ "setenv get_cmd dhcp; " \ "else " \ "setenv get_cmd tftp; " \ "fi; " \ "if ${get_cmd} ${update_sd_firmware_filename}; then " \ "if mmc dev ${emmcdev} 1; then " \ "setexpr fw_sz ${filesize} / 0x200; " \ "setexpr fw_sz ${fw_sz} + 1; " \ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ "fi; " \ "fi\0" #else #define EMMC_ENV "" #endif #ifdef CONFIG_CMD_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 3) #else #define BOOT_TARGET_DEVICES_MMC(func) #endif #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) #include #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #if defined(CONFIG_NAND_BOOT) /* * The dts also enables the WEIN NOR which is mtd0. * So the partions' layout for NAND is: * mtd1: 16M (uboot) * mtd2: 16M (kernel) * mtd3: 16M (dtb) * mtd4: left (rootfs) */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "bootargs=console=" CONSOLE_DEV ",115200 ubi.mtd=5 " \ "root=ubi0:rootfs rootfstype=ubifs " \ "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ "nand read ${fdt_addr} 0x5000000 0x100000;"\ "bootz ${loadaddr} - ${fdt_addr}\0" #elif defined(CONFIG_SATA_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ "bootargs=console=" CONSOLE_DEV ",115200 \0"\ "bootargs_sata=setenv bootargs ${bootargs} " \ "root=/dev/sda1 rootwait rw \0" \ "bootcmd_sata=run bootargs_sata; sata init; " \ "sata read ${loadaddr} 0x800 0x4000; " \ "sata read ${fdt_addr} 0x8000 0x800; " \ "bootz ${loadaddr} - ${fdt_addr} \0" \ "bootcmd=run bootcmd_sata \0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ "console=" CONSOLE_DEV "\0" \ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \ "scriptaddr=0x10000000\0" \ "fdt_addr_r=0x18000000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "script_size_f=0x80000\0" \ "ramdisk_addr_r=0x13000000\0" \ BOOTENV #endif #define CONFIG_ARP_TIMEOUT 200UL #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 //#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 //#define CONFIG_STACKSIZE (128 * 1024) /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment organization */ #define CONFIG_ENV_SIZE (8 * 1024) #if defined CONFIG_SPI_BOOT #define CONFIG_CMD_SF #define CONFIG_ENV_IS_IN_SPI_FLASH #elif defined CONFIG_NOR_BOOT #define CONFIG_MTD_NOR_FLASH #define CONFIG_ENV_IS_IN_FLASH #elif defined CONFIG_NAND_BOOT #define CONFIG_CMD_NAND #define CONFIG_ENV_IS_IN_NAND #elif defined CONFIG_SATA_BOOT #define CONFIG_ENV_IS_IN_SATA #define CONFIG_CMD_SATA #else #define CONFIG_ENV_IS_IN_MMC #endif #ifdef CONFIG_CMD_SATA #define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 #define CONFIG_LIBATA #endif #ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #define CONFIG_SF_DEFAULT_CS 0 #define IMX_CSPI_VER_2_3 1 #define MAX_SPI_BYTES 32 /*(64 * 4)*/ #endif #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #endif #ifdef CONFIG_CMD_NAND /* NAND flash command */ #define CONFIG_CMD_NAND_TRIMFFS /* NAND stuff */ #define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION /* DMA stuff, needed for GPMI/MXS NAND support */ #define CONFIG_APBH_DMA #define CONFIG_APBH_DMA_BURST #define CONFIG_APBH_DMA_BURST8 #endif #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_ENV_OFFSET (896 * 1024) #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) #define CONFIG_ENV_OFFSET (896 * 1024) #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #elif defined(CONFIG_ENV_IS_IN_FLASH) #undef CONFIG_ENV_SIZE #define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE) #elif defined(CONFIG_ENV_IS_IN_NAND) #undef CONFIG_ENV_SIZE #define CONFIG_ENV_OFFSET (60 << 20) #define CONFIG_ENV_SECT_SIZE (128 << 10) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #elif defined(CONFIG_ENV_IS_IN_SATA) #define CONFIG_ENV_OFFSET (896 * 1024) #define CONFIG_SYS_SATA_ENV_DEV 0 #define CONFIG_SYS_DCACHE_OFF /* remove when sata driver support cache */ #else #define CONFIG_ENV_IS_NOWHERE 1 #endif /* I2C Configs */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C #endif #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #endif /* PMIC */ #ifndef CONFIG_DM_PMIC #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* Framebuffer */ #ifdef CONFIG_VIDEO #define CONFIG_LCD #define CONFIG_VIDEO_IPUV3 #define CONFIG_IMX_VIDEO_SKIP //#define CONFIG_IPUV3_CLK 260000000 #define LCD_BPP LCD_COLOR16 #endif #ifndef CONFIG_SPL #define CONFIG_USBD_HS #define CONFIG_USB_FUNCTION_MASS_STORAGE #endif #endif /* __MX6_HORIZON_COMMON_CONFIG_H */