/*
 * Copyright 2017 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include "pin_mux.h"
#include "clock_config.h"
#include "board.h"
#include "fsl_debug_console.h"
#include "fsl_sai_sdma.h"
#include "music.h"
#include "fsl_codec_common.h"
#include "fsl_wm8960.h"
#include "fsl_common.h"
#include "fsl_gpio.h"
#include "fsl_iomuxc.h"
#include "fsl_codec_adapter.h"
#include "fsl_sai.h"
/*******************************************************************************
 * Definitions
 ******************************************************************************/
#define DEMO_SAI (I2S1)
#define DEMO_SAI_CLK_FREQ                                                                  \
    (CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootSai1)) / \
     (CLOCK_GetRootPostDivider(kCLOCK_RootSai1)))

#define I2C_RELEASE_SDA_GPIO  GPIO5
#define I2C_RELEASE_SDA_PIN   19U
#define I2C_RELEASE_SCL_GPIO  GPIO5
#define I2C_RELEASE_SCL_PIN   18U
#define I2C_RELEASE_BUS_COUNT 100U

#define DEMO_IRQn       I2S1_IRQn
#define EXAMPLE_DMA     SDMAARM3
#define EXAMPLE_CHANNEL (2)
#define SAI_RX_SOURCE   (0)
/*set Bclk source to Mclk clock*/
#define DEMO_SAI_CLOCK_SOURCE   (1U)
#define SDMA_FREQ_EQUALS_ARM    (1U)
#define DEMO_AUDIO_MASTER_CLOCK DEMO_SAI_CLK_FREQ
#define SAI_UserIRQHandler      I2S1_IRQHandler
#define OVER_SAMPLE_RATE (384U)
/* demo audio sample rate */
// #define DEMO_AUDIO_SAMPLE_RATE (kSAI_SampleRate384KHz)
#define DEMO_AUDIO_SAMPLE_RATE (768000)
/* demo audio master clock */
#if (defined FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER && FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) || \
    (defined FSL_FEATURE_PCC_HAS_SAI_DIVIDER && FSL_FEATURE_PCC_HAS_SAI_DIVIDER)
#define DEMO_AUDIO_MASTER_CLOCK OVER_SAMPLE_RATE *DEMO_AUDIO_SAMPLE_RATE
#else
#define DEMO_AUDIO_MASTER_CLOCK DEMO_SAI_CLK_FREQ
#endif
/* demo audio data channel */
#define DEMO_AUDIO_DATA_CHANNEL (2U)
/* demo audio bit width */
#define DEMO_AUDIO_BIT_WIDTH kSAI_WordWidth32bits
#define DEMO_DATA_CHANNLE_MASK kSAI_Channel0Mask|kSAI_Channel1Mask|kSAI_Channel2Mask|kSAI_Channel3Mask
// #define DEMO_DATA_CHANNLE_MASK kSAI_Channel0Mask
/*******************************************************************************
 * Prototypes
 ******************************************************************************/
void BOARD_I2C_ReleaseBus(void);
void BOARD_MASTER_CLOCK_CONFIG(void);
void print_sai_registers(I2S_Type *base);
static void callback(I2S_Type *base, sai_sdma_handle_t *handle, status_t status, void *userData);

uint8_t *g_data_test= (uint8_t *)(0x55800000);
const uint32_t TEST_SIZE = 2048;
/*******************************************************************************
 * Variables
 ******************************************************************************/
wm8960_config_t wm8960Config = {
    .i2cConfig = {.codecI2CInstance = BOARD_CODEC_I2C_INSTANCE, .codecI2CSourceClock = BOARD_CODEC_I2C_CLOCK_FREQ},
    .route     = kWM8960_RoutePlaybackandRecord,
    .rightInputSource = kWM8960_InputDifferentialMicInput2,
    .playSource       = kWM8960_PlaySourceDAC,
    .slaveAddress     = WM8960_I2C_ADDR,
    .bus              = kWM8960_BusI2S,
    .format           = {.mclk_HZ    = 24576000U,
               .sampleRate = kWM8960_AudioSampleRate16KHz,
               .bitWidth   = kWM8960_AudioBitWidth16bit},
    .master_slave     = false,
};
codec_config_t boardCodecConfig = {.codecDevType = kCODEC_WM8960, .codecDevConfig = &wm8960Config};
sai_master_clock_t mclkConfig;

AT_NONCACHEABLE_SECTION_ALIGN(sai_sdma_handle_t rxHandle, 4);
AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t dmaHandle, 4);
AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t context, 4);
volatile bool isFinished = false;
extern codec_config_t boardCodecConfig;
codec_handle_t codecHandle;

/*******************************************************************************
 * Code
 ******************************************************************************/

static void i2c_release_bus_delay(void)
{
    uint32_t i = 0;
    for (i = 0; i < I2C_RELEASE_BUS_COUNT; i++)
    {
        __NOP();
    }
}

void BOARD_I2C_ReleaseBus(void)
{
    uint8_t i                    = 0;
    gpio_pin_config_t pin_config = {kGPIO_DigitalOutput, 1, kGPIO_NoIntmode};

    IOMUXC_SetPinMux(IOMUXC_I2C3_SCL_GPIO5_IO18, 0U);
    IOMUXC_SetPinConfig(IOMUXC_I2C3_SCL_GPIO5_IO18, IOMUXC_SW_PAD_CTL_PAD_DSE(3U) | IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK |
                                                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
    IOMUXC_SetPinMux(IOMUXC_I2C3_SDA_GPIO5_IO19, 0U);
    IOMUXC_SetPinConfig(IOMUXC_I2C3_SDA_GPIO5_IO19, IOMUXC_SW_PAD_CTL_PAD_DSE(3U) | IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK |
                                                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
    GPIO_PinInit(I2C_RELEASE_SCL_GPIO, I2C_RELEASE_SCL_PIN, &pin_config);
    GPIO_PinInit(I2C_RELEASE_SDA_GPIO, I2C_RELEASE_SDA_PIN, &pin_config);

    /* Drive SDA low first to simulate a start */
    GPIO_PinWrite(I2C_RELEASE_SDA_GPIO, I2C_RELEASE_SDA_PIN, 0U);
    i2c_release_bus_delay();

    /* Send 9 pulses on SCL and keep SDA high */
    for (i = 0; i < 9; i++)
    {
        GPIO_PinWrite(I2C_RELEASE_SCL_GPIO, I2C_RELEASE_SCL_PIN, 0U);
        i2c_release_bus_delay();

        GPIO_PinWrite(I2C_RELEASE_SDA_GPIO, I2C_RELEASE_SDA_PIN, 1U);
        i2c_release_bus_delay();

        GPIO_PinWrite(I2C_RELEASE_SCL_GPIO, I2C_RELEASE_SCL_PIN, 1U);
        i2c_release_bus_delay();
        i2c_release_bus_delay();
    }

    /* Send stop */
    GPIO_PinWrite(I2C_RELEASE_SCL_GPIO, I2C_RELEASE_SCL_PIN, 0U);
    i2c_release_bus_delay();

    GPIO_PinWrite(I2C_RELEASE_SDA_GPIO, I2C_RELEASE_SDA_PIN, 0U);
    i2c_release_bus_delay();

    GPIO_PinWrite(I2C_RELEASE_SCL_GPIO, I2C_RELEASE_SCL_PIN, 1U);
    i2c_release_bus_delay();

    GPIO_PinWrite(I2C_RELEASE_SDA_GPIO, I2C_RELEASE_SDA_PIN, 1U);
    i2c_release_bus_delay();
}

void BOARD_MASTER_CLOCK_CONFIG(void)
{
    mclkConfig.mclkOutputEnable = true;
    mclkConfig.mclkHz           = DEMO_AUDIO_MASTER_CLOCK;
    mclkConfig.mclkSourceClkHz  = DEMO_SAI_CLK_FREQ;
    SAI_SetMasterClockConfig(DEMO_SAI, &mclkConfig);
}
static void callback(I2S_Type *base, sai_sdma_handle_t *handle, status_t status, void *userData)
{
    isFinished = true;
}

/*!
 * @brief Main function
 */
uint32_t g_error_count = 0;
int main(void)
{
    sai_transfer_t xfer;
    sdma_config_t dmaConfig = {0};
    uint32_t temp           = 0;
    sai_transceiver_t config;
    status_t error = kStatus_Success;
    uint8_t *testdata = g_data_test;

    /* M7 has its local cache and enabled by default,
     * need to set smart subsystems (0x28000000 ~ 0x3FFFFFFF)
     * non-cacheable before accessing this address region */
    BOARD_InitMemory();

    /* Board specific RDC settings */
    BOARD_RdcInit();

    BOARD_InitPins();
    BOARD_BootClockRUN();
    // BOARD_I2C_ReleaseBus();
    // BOARD_I2C_ConfigurePins();
    BOARD_InitDebugConsole();

    CLOCK_SetRootMux(kCLOCK_RootSai1, kCLOCK_SaiRootmuxAudioPll1); /* Set SAI source to AUDIO PLL1 393216000HZ*/
    //chengting
    CLOCK_SetRootDivider(kCLOCK_RootSai1, 1U, 1U);                /* Set root clock to 393216000HZ / 16 = 24.576MHz */
    // CLOCK_SetRootMux(kCLOCK_RootI2c3, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */
    // CLOCK_SetRootDivider(kCLOCK_RootI2c3, 1U, 10U);                  /* Set root clock to 160MHZ / 10 = 16MHZ */

    /* SAI bit clock source */
    AUDIOMIX_AttachClk(AUDIOMIX, kAUDIOMIX_Attach_SAI1_MCLK1_To_SAI1_ROOT);

    PRINTF("SAI SDMA example sai1 receive started!\n\r");
    /* Create SDMA handle */
    SDMA_GetDefaultConfig(&dmaConfig);
#ifdef SDMA_FREQ_EQUALS_ARM
    dmaConfig.ratio = kSDMA_ARMClockFreq;
#endif

    SDMA_Init(EXAMPLE_DMA, &dmaConfig);
    SDMA_CreateHandle(&dmaHandle, EXAMPLE_DMA, EXAMPLE_CHANNEL, &context);
    SDMA_SetChannelPriority(EXAMPLE_DMA, EXAMPLE_CHANNEL, 2);

    /* SAI init */
    SAI_Init(DEMO_SAI);
    SAI_TransferRxCreateHandleSDMA(DEMO_SAI, &rxHandle, callback, NULL, &dmaHandle, SAI_RX_SOURCE);

    /* I2S mode configurations */
    SAI_GetLeftJustifiedConfig(&config, DEMO_AUDIO_BIT_WIDTH, kSAI_Stereo, DEMO_DATA_CHANNLE_MASK);
    // SAI_GetLeftJustifiedConfig(&config, DEMO_AUDIO_BIT_WIDTH, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask);
    config.bitClock.bclkSource = (sai_bclk_source_t)DEMO_SAI_CLOCK_SOURCE;
    config.syncMode    = kSAI_ModeAsync;
    config.masterSlave = kSAI_Master;
    SAI_TransferRxSetConfigSDMA(DEMO_SAI, &rxHandle, &config);

    /* set bit clock divider */

    SAI_RxSetBitClockRate(DEMO_SAI, DEMO_AUDIO_MASTER_CLOCK, DEMO_AUDIO_SAMPLE_RATE, DEMO_AUDIO_BIT_WIDTH,
                          DEMO_AUDIO_DATA_CHANNEL);

    /* master clock configurations */
    BOARD_MASTER_CLOCK_CONFIG();

    // /* Use default setting to init codec */
    // if (CODEC_Init(&codecHandle, &boardCodecConfig) != kStatus_Success)
    // {
    //     assert(false);
    // }

    /* Enable SAI interrupt to clear the FIFO error */
    EnableIRQ(DEMO_IRQn);
    SAI_RxEnableInterrupts(DEMO_SAI, kSAI_FIFOErrorInterruptEnable);
    print_sai_registers(DEMO_SAI);
    PRINTF("\n\r SAI SDMA example begin!\n\r ");
    PRINTF("\n\r sdma event over = 0x%x , error=0x%x\n\r",SDMAARM3->EVTOVR, SDMAARM3->EVTERR);
    int i=0;
    status_t ret = 0;
    for(i=0; i<1; i++)
    {
        /*  xfer structure */
        temp          = (uint32_t)(testdata );
        xfer.data     = (uint8_t *)temp;
        xfer.dataSize = TEST_SIZE;
        memset(testdata, 0x11, TEST_SIZE);
        ret = SAI_TransferReceiveSDMA(DEMO_SAI, &rxHandle, &xfer);
        isFinished = false;
        /* Wait until finished */
        while (isFinished != true)
        {
        }

    }

    // error = CODEC_Deinit(&codecHandle);
    // if ((error != kStatus_CODEC_NotSupport) && (error != kStatus_Success))
    // {
    //     assert(false);
    // }

    for(int j=0; j<TEST_SIZE; j+=128)
    {
        PRINTF("\n\r testdata[%d] = 0x%x \n\r", j, testdata[j]);
    }
    

    PRINTF("\n\r SAI SDMA example finished! g_error_count =%d  received=%d Kbytes \n\r",g_error_count, i*TEST_SIZE/1000);
    PRINTF("\n\r sdma event over = 0x%x , error=0x%x\n\r",SDMAARM3->EVTOVR, SDMAARM3->EVTERR);
    while (1)
    {
    }
}

void SAI_UserIRQHandler(void)
{
    // PRINTF("\n\r error interrupt\n\r ");
    g_error_count++;
    SAI_RxClearStatusFlags(DEMO_SAI, kSAI_FIFOErrorFlag);
    __DSB();
}

void print_sai_registers(I2S_Type *base)
{
    PRINTF("!!!base =0x %x \r\n", base);
    PRINTF("===VERID =0x %x \r\n", base->VERID);
    PRINTF("===PARAM =0x %x \r\n", base->PARAM);
    int fifo_size = 1<< (((base->PARAM)& I2S_PARAM_FIFO_MASK) >> I2S_PARAM_FIFO_SHIFT);
    int frame_size = 1<< (((base->PARAM)& I2S_PARAM_FRAME_MASK) >> I2S_PARAM_FRAME_SHIFT);
    PRINTF("dataline =0x %x , fifo size=%d, framesize =%d \r\n", ((base->PARAM)& I2S_PARAM_DATALINE_MASK) >> I2S_PARAM_DATALINE_SHIFT,fifo_size,frame_size);
    PRINTF("===TCSR =0x %x \r\n", base->TCSR);
    PRINTF("===TCR1 =0x %x \r\n", base->TCR1);
    PRINTF("===TCR2 =0x %x \r\n", base->TCR2);
    PRINTF("===TCR3 =0x %x \r\n", base->TCR3);                                            
    PRINTF("===TCR4 =0x %x \r\n", base->TCR4);
    PRINTF("===TCR5 =0x %x \r\n", base->TCR5);
    PRINTF("===TDR[0] =0x%x, TDR[1] =0x%x,TDR[2] =0x %x,TDR[3] =0x %x, \r\n", base->TDR[0],base->TDR[1],base->TDR[2],base->TDR[3]);
    PRINTF("===TDR[4] =0x%x, TDR[5] =0x%x,TDR[6] =0x %x,TDR[7] =0x %x, \r\n", base->TDR[4],base->TDR[5],base->TDR[6],base->TDR[7]);
    PRINTF("===TFR[0] =0x%x, TFR[1] =0x%x,TFR[2] =0x %x,TFR[3] =0x %x, \r\n", base->TFR[0],base->TFR[1],base->TFR[2],base->TFR[3]);
    PRINTF("===TFR[4] =0x%x, TFR[5] =0x%x,TFR[6] =0x %x,TFR[7] =0x %x, \r\n", base->TFR[4],base->TFR[5],base->TFR[6],base->TFR[7]);    
    PRINTF("===TMR =0x %x \r\n", base->TMR);

    PRINTF("===TTCR =0x %x \r\n", base->TTCR);
    PRINTF("===TTSR =0x %x \r\n", base->TTSR);
    PRINTF("===TBCR =0x %x \r\n", base->TBCR);
    PRINTF("===TBCTR =0x %x \r\n", base->TBCTR);

    PRINTF("recevie part regisger ======\r\n");
    PRINTF("===RCSR =0x %x \r\n", base->RCSR);
    PRINTF("RE=0x%x, BCE=0x%x, FR=0x%x \r\n", ((base->RCSR)&I2S_RCSR_RE_MASK)>>I2S_RCSR_RE_SHIFT,
                ((base->RCSR)&I2S_RCSR_BCE_MASK)>>I2S_RCSR_BCE_SHIFT,((base->RCSR)&I2S_RCSR_FR_MASK)>>I2S_RCSR_FR_SHIFT);
    PRINTF("SR=0x%x, WSF=0x%x, SEF=0x%x \r\n", ((base->RCSR)&I2S_RCSR_SR_MASK)>>I2S_RCSR_SR_SHIFT,
                ((base->RCSR)&I2S_RCSR_WSF_MASK)>>I2S_RCSR_WSF_SHIFT,((base->RCSR)&I2S_RCSR_SEF_MASK)>>I2S_RCSR_SEF_SHIFT);
    PRINTF("FEF=0x%x, FWF=0x%x, FRF=0x%x \r\n", ((base->RCSR)&I2S_RCSR_FEF_MASK)>>I2S_RCSR_FEF_SHIFT,
                ((base->RCSR)&I2S_RCSR_FWF_MASK)>>I2S_RCSR_FWF_SHIFT,((base->RCSR)&I2S_RCSR_FRF_MASK)>>I2S_RCSR_FRF_SHIFT);
    PRINTF("WSIE=0x%x, SEIE=0x%x, FWIE=0x%x \r\n", ((base->RCSR)&I2S_RCSR_WSIE_MASK)>>I2S_RCSR_WSIE_SHIFT,
                ((base->RCSR)&I2S_RCSR_SEIE_MASK)>>I2S_RCSR_SEIE_SHIFT,((base->RCSR)&I2S_RCSR_FWIE_MASK)>>I2S_RCSR_FWIE_SHIFT);

    PRINTF("FRIE=0x%x, FWDE=0x%x, FRDE=0x%x\r\n", ((base->RCSR)&I2S_RCSR_FRIE_MASK)>>I2S_RCSR_FRIE_SHIFT,
                ((base->RCSR)&I2S_RCSR_FWDE_MASK)>>I2S_RCSR_FWDE_SHIFT,((base->RCSR)&I2S_RCSR_FRDE_MASK)>>I2S_RCSR_FRDE_SHIFT);
    PRINTF("FEIE=0x%x\r\n", ((base->RCSR)&I2S_RCSR_FEIE_MASK)>>I2S_RCSR_FEIE_SHIFT);

    PRINTF("===RCR1 =0x %x \r\n", base->RCR1);

    PRINTF("RFW fifo watermark= %d \r\n", ((base->RCR1)&I2S_RCR1_RFW_MASK)>>I2S_RCR1_RFW_SHIFT);
    PRINTF("===RCR2 =0x %x \r\n", base->RCR2);
    PRINTF("SYNC mode=0x%x, BCS=0x%x, BCI=0x%x \r\n", ((base->RCR2)&I2S_RCR2_SYNC_MASK)>>I2S_RCR2_SYNC_SHIFT,
                        ((base->RCR2)&I2S_RCR2_BCS_MASK)>>I2S_RCR2_BCS_SHIFT,((base->RCR2)&I2S_RCR2_BCI_MASK)>>I2S_RCR2_BCI_SHIFT);
    PRINTF("MSEL=0x%x, BCP=0x%x, BCD=0x%x\r\n", ((base->RCR2)&I2S_RCR2_MSEL_MASK)>>I2S_RCR2_MSEL_SHIFT,
                        ((base->RCR2)&I2S_RCR2_BCP_MASK)>>I2S_RCR2_BCP_SHIFT,((base->RCR2)&I2S_RCR2_BCD_MASK)>>I2S_RCR2_BCD_SHIFT);
    PRINTF("BYP=0x%x, DIV=%d \r\n", ((base->RCR2)&I2S_RCR2_BYP_MASK)>>I2S_RCR2_BYP_SHIFT,((((base->RCR2)&I2S_RCR2_DIV_MASK)>>I2S_RCR2_DIV_SHIFT)+1)*2);

    PRINTF("====RCR3 =0x %x \r\n", base->RCR3);
    PRINTF("CFR=0x%x, RCE=0x%x, WDFL=0x%x \r\n", ((base->RCR3)&I2S_RCR3_CFR_MASK)>>I2S_RCR3_CFR_SHIFT,
                    ((base->RCR3)&I2S_RCR3_RCE_MASK)>>I2S_RCR3_RCE_SHIFT,((base->RCR3)&I2S_RCR3_WDFL_MASK)>>I2S_RCR3_WDFL_SHIFT);
    PRINTF("====RCR4 =0x %x \r\n", base->RCR4);
    PRINTF("FSD=0x%x, FSP=0x%x, ONDEM=0x%x \r\n", ((base->RCR4)&I2S_RCR4_FSD_MASK)>>I2S_RCR4_FSD_SHIFT
                ,((base->RCR4)&I2S_RCR4_FSP_MASK)>>I2S_RCR4_FSP_SHIFT, ((base->RCR4)&I2S_RCR4_ONDEM_MASK)>>I2S_RCR4_ONDEM_SHIFT);
    PRINTF("FSE=0x%x, MF=0x%x, SYWD=0x%x \r\n", ((base->RCR4)&I2S_RCR4_FSE_MASK)>>I2S_RCR4_FSE_SHIFT
                ,((base->RCR4)&I2S_RCR4_MF_MASK)>>I2S_RCR4_MF_SHIFT, ((base->RCR4)&I2S_RCR4_SYWD_MASK)>>I2S_RCR4_SYWD_SHIFT);
    PRINTF("FRSZ=0x%x, FPACK=0x%x, FCOMB=0x%x \r\n", ((base->RCR4)&I2S_RCR4_FRSZ_MASK)>>I2S_RCR4_FRSZ_SHIFT
                ,((base->RCR4)&I2S_RCR4_FPACK_MASK)>>I2S_RCR4_FPACK_SHIFT, ((base->RCR4)&I2S_RCR4_FCOMB_MASK)>>I2S_RCR4_FCOMB_SHIFT);
    PRINTF("FCONT=0x%x \r\n", ((base->RCR4)&I2S_RCR4_FCONT_MASK)>>I2S_RCR4_FCONT_SHIFT);

    PRINTF("===RCR5 =0x %x \r\n", base->RCR5);
    PRINTF("FBT=0x%x, W0W=0x%x, WNW=0x%x \r\n", ((base->RCR5)&I2S_RCR5_FBT_MASK)>>I2S_RCR5_FBT_SHIFT,
                    ((base->RCR5)&I2S_RCR5_W0W_MASK)>>I2S_RCR5_W0W_SHIFT,((base->RCR5)&I2S_RCR5_WNW_MASK)>>I2S_RCR5_WNW_SHIFT);
    PRINTF("===RDR[0] =0x%x, RDR[1] =0x%x,RDR[2] =0x %x,RDR[3] =0x %x, \r\n", base->RDR[0],base->RDR[1],base->RDR[2],base->RDR[3]);
    PRINTF("===RDR[4] =0x%x, RDR[5] =0x%x,RDR[6] =0x %x,RDR[7] =0x %x, \r\n", base->RDR[4],base->RDR[5],base->RDR[6],base->RDR[7]);
    PRINTF("===RFR[0] =0x%x, RFR[1] =0x%x,RFR[2] =0x %x,RFR[3] =0x %x, \r\n", base->RFR[0],base->RFR[1],base->RFR[2],base->RFR[3]);
    PRINTF("===RFR[4] =0x%x, RFR[5] =0x%x,RFR[6] =0x %x,RFR[7] =0x %x, \r\n", base->RFR[4],base->RFR[5],base->RFR[6],base->RFR[7]);    
    
    PRINTF("===RMR =0x %x \r\n", base->RMR);

    PRINTF("===RTCR =0x %x \r\n", base->RTCR);
    PRINTF("TSEN=0x%x, TSINC=0x%x, RTSC=0x%x, RBC=0x%x \r\n", ((base->RTCR)&I2S_RTCR_TSEN_MASK)>>I2S_RTCR_TSEN_SHIFT,
                        ((base->RTCR)&I2S_RTCR_TSINC_MASK)>>I2S_RTCR_TSINC_SHIFT, ((base->RTCR)&I2S_RTCR_RTSC_MASK)>>I2S_RTCR_RTSC_SHIFT, ((base->RTCR)&I2S_RTCR_RBC_MASK)>>I2S_RTCR_RBC_SHIFT);
    PRINTF("===RTSR =0x %x \r\n", base->RTSR);
    PRINTF("===RBCR =0x %x \r\n", base->RBCR);
    PRINTF("===RBCTR =0x %x \r\n", base->RBCTR);
    PRINTF("===MCR =0x %x \r\n", base->MCR);
    uint32_t mclk_div = ((base->MCR)&I2S_MCR_DIV_MASK)>>I2S_MCR_DIV_SHIFT;
    mclk_div = (mclk_div +1)*2;
    PRINTF("DIV=%d, DIVEN=0x%x, MOE=0x%x\r\n", mclk_div,((base->MCR)&I2S_MCR_DIVEN_MASK)>>I2S_MCR_DIVEN_SHIFT,((base->MCR)&I2S_MCR_MOE_MASK)>>I2S_MCR_MOE_SHIFT);
    uint32_t mclk_hz, bclk_hz = 0;
    if(((base->MCR)&I2S_MCR_DIVEN_MASK)>>I2S_MCR_DIVEN_SHIFT == 0)//output on MCLK signal pin is the audio master clock
    {
        mclk_hz = DEMO_AUDIO_MASTER_CLOCK;
        
    }
    else
    {
        mclk_hz = DEMO_AUDIO_MASTER_CLOCK/mclk_div;
    }
    PRINTF("\r\n !!!mclk = %d Khz \r\n", mclk_hz/1000);
    if(((base->RCR2)&I2S_RCR2_BYP_MASK)>>I2S_RCR2_BYP_SHIFT ==0)
    {
        bclk_hz = mclk_hz/(((((base->RCR2)&I2S_RCR2_DIV_MASK)>>I2S_RCR2_DIV_SHIFT)+1)*2);
    }
    else
    {
        bclk_hz = mclk_hz;
    }
    PRINTF("\r\n !!!receive bclk = %d Khz \r\n", bclk_hz/1000);
    uint32_t rce = ((base->RCR3)&I2S_RCR3_RCE_MASK)>>I2S_RCR3_RCE_SHIFT;
    if(rce & 0x01)
    {
        PRINTF("\r\n !!!channel 0 enabled  \r\n");
    }
    if(rce & 0x02)
    {
        PRINTF("\r\n !!!channel 1 enabled  \r\n");
    }
    if(rce & 0x04)
    {
        PRINTF("\r\n !!!channel 2 enabled  \r\n");
    }
    if(rce & 0x08)
    {
        PRINTF("\r\n !!!channel 3 enabled  \r\n");
    }

    PRINTF("end of print register ======\r\n");
}