From 01945372fb732a83a051b03411f95d167b135fbc Mon Sep 17 00:00:00 2001
From: Khang Le Truong <khang.letruong@dynimlabs.com>
Date: Tue, 24 Jan 2023 21:02:16 +0700
Subject: [PATCH 1/2] Adapt iMX8MP-DDR4-EVK to VIPER board

---
 arch/arm/dts/imx8mp-ddr4-evk.dts         |   7 +-
 board/freescale/imx8mp_evk/ddr4_timing.c | 193 +++--------------------
 include/configs/imx8mp_evk.h             |  16 +-
 3 files changed, 33 insertions(+), 183 deletions(-)

diff --git a/arch/arm/dts/imx8mp-ddr4-evk.dts b/arch/arm/dts/imx8mp-ddr4-evk.dts
index 9ef9b2d598..91de4584ea 100644
--- a/arch/arm/dts/imx8mp-ddr4-evk.dts
+++ b/arch/arm/dts/imx8mp-ddr4-evk.dts
@@ -8,6 +8,11 @@
 
 / {
 	model = "NXP i.MX8MPlus DDR4 EVK board";
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0 0x40000000>;
+	};
 };
 
 &flexspi {
@@ -48,4 +53,4 @@
 			MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B		0x00000096
 		>;
 	};
-};
\ No newline at end of file
+};
diff --git a/board/freescale/imx8mp_evk/ddr4_timing.c b/board/freescale/imx8mp_evk/ddr4_timing.c
index 3e3cc01bcc..20d025da99 100644
--- a/board/freescale/imx8mp_evk/ddr4_timing.c
+++ b/board/freescale/imx8mp_evk/ddr4_timing.c
@@ -1,14 +1,14 @@
 /*
- * Copyright 2019 NXP
+ * Copyright 2023 Realtim-7 Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
  * Generated code from MX8M_DDR_tool
  *
  * Align with uboot version:
- * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
- * For imx_v2019.04_5.4.x and above version:
- * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
  */
 
 #include <linux/kernel.h>
@@ -18,7 +18,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	/** Initialize DDRC registers **/
 	{ 0x3d400304, 0x1 },
 	{ 0x3d400030, 0x1 },
-	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400000, 0xa1041010 },
 	{ 0x3d400030, 0xaa },
 	{ 0x3d400034, 0x221306 },
 	{ 0x3d400050, 0x210070 },
@@ -27,12 +27,8 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400064, 0xc30118 },
 	{ 0x3d4000c0, 0x0 },
 	{ 0x3d4000c4, 0x1000 },
-#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
-	{ 0x3d400070, 0x1027f54 },
-#else
-	{ 0x3d400070, 0x1027f10 },
-#endif
-	{ 0x3d400074, 0x7b0 },
+	{ 0x3d400070, 0x1027f90 },
+	{ 0x3d400074, 0x790 },
 	{ 0x3d4000d0, 0xc0030188 },
 	{ 0x3d4000d4, 0x9e0000 },
 	{ 0x3d4000dc, 0xc500501 },
@@ -43,10 +39,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d4000f0, 0x20 },
 	{ 0x3d4000f4, 0xec7 },
 	{ 0x3d400100, 0x1618361a },
-	{ 0x3d400104, 0x50626 },
+	{ 0x3d400104, 0x50625 },
 	{ 0x3d400108, 0x80b0610 },
 	{ 0x3d40010c, 0x400c },
-	{ 0x3d400110, 0xc04060d },
+	{ 0x3d400110, 0xb04060c },
 	{ 0x3d400114, 0x8080504 },
 	{ 0x3d40011c, 0x808 },
 	{ 0x3d400120, 0x6060d0a },
@@ -69,27 +65,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d4001c0, 0x1 },
 	{ 0x3d4001c4, 0x0 },
 	{ 0x3d400200, 0x1f },
-#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
-	{ 0x3d400204, 0x3f0505 },
-	{ 0x3d400208, 0x700 },
-	{ 0x3d40020c, 0x14141400 },
+	{ 0x3d400204, 0x3f0707 },
+	{ 0x3d400208, 0x0 },
+	{ 0x3d40020c, 0x1f000000 },
 	{ 0x3d400210, 0x1f1f },
-	{ 0x3d400214, 0x4040403 },
-	{ 0x3d400218, 0x4040404 },
-	{ 0x3d40021c, 0xf04 },
-#else
-	{ 0x3d400204, 0x3f0909 },
-	{ 0x3d400208, 0x700 },
-	{ 0x3d40020c, 0x0 },
-	{ 0x3d400210, 0x1f1f },
-	{ 0x3d400214, 0x7070707 },
-	{ 0x3d400218, 0x7070707 },
-	{ 0x3d40021c, 0xf07 },
-#endif
-	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400214, 0x6060606 },
+	{ 0x3d400218, 0x6060606 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400220, 0x3f09 },
 	{ 0x3d400240, 0x6000618 },
 	{ 0x3d400244, 0x1323 },
-	{ 0x3d400250, 0x00001a05 },
+	{ 0x3d400250, 0x1a05 },
 	{ 0x3d400254, 0x1f },
 	{ 0x3d40025c, 0x10000010 },
 	{ 0x3d400264, 0x100000ff },
@@ -102,31 +88,6 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400498, 0x620096 },
 	{ 0x3d40049c, 0x1100e07 },
 	{ 0x3d4004a0, 0xc8012c },
-	{ 0x3d402050, 0x210070 },
-	{ 0x3d402064, 0x40005e },
-	{ 0x3d4020dc, 0x40501 },
-	{ 0x3d4020e0, 0x0 },
-	{ 0x3d4020e8, 0x2000600 },
-	{ 0x3d4020ec, 0x10 },
-	{ 0x3d402100, 0xb081209 },
-	{ 0x3d402104, 0x2020d },
-	{ 0x3d402108, 0x5050309 },
-	{ 0x3d40210c, 0x400c },
-	{ 0x3d402110, 0x4030205 },
-	{ 0x3d402114, 0x3030202 },
-	{ 0x3d40211c, 0x303 },
-	{ 0x3d402120, 0x3030d04 },
-	{ 0x3d402124, 0x20208 },
-	{ 0x3d40212c, 0x1005010e },
-	{ 0x3d402130, 0x8 },
-	{ 0x3d40213c, 0x0 },
-	{ 0x3d402180, 0x1000040 },
-	{ 0x3d402190, 0x3858204 },
-	{ 0x3d402194, 0x2020303 },
-	{ 0x3d4021b4, 0x504 },
-	{ 0x3d4021b8, 0x4 },
-	{ 0x3d402240, 0x6000604 },
-	{ 0x3d4020f4, 0xec7 },
 };
 
 /* PHY Initialize Configuration */
@@ -135,18 +96,6 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{ 0x1015f, 0x2df },
 	{ 0x1105f, 0x2df },
 	{ 0x1115f, 0x2df },
-	{ 0x1205f, 0x2df },
-	{ 0x1215f, 0x2df },
-	{ 0x1305f, 0x2df },
-	{ 0x1315f, 0x2df },
-	{ 0x11005f, 0x2df },
-	{ 0x11015f, 0x2df },
-	{ 0x11105f, 0x2df },
-	{ 0x11115f, 0x2df },
-	{ 0x11205f, 0x2df },
-	{ 0x11215f, 0x2df },
-	{ 0x11305f, 0x2df },
-	{ 0x11315f, 0x2df },
 	{ 0x55, 0x355 },
 	{ 0x1055, 0x355 },
 	{ 0x2055, 0x355 },
@@ -158,47 +107,18 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{ 0x8055, 0x355 },
 	{ 0x9055, 0x355 },
 	{ 0x200c5, 0x19 },
-	{ 0x1200c5, 0x6 },
 	{ 0x2002e, 0x2 },
-	{ 0x12002e, 0x1 },
 	{ 0x20024, 0x8 },
 	{ 0x2003a, 0x2 },
-	{ 0x120024, 0x8 },
-	{ 0x2003a, 0x2 },
 	{ 0x20056, 0x7 },
-	{ 0x120056, 0xa },
 	{ 0x1004d, 0x1a },
 	{ 0x1014d, 0x1a },
 	{ 0x1104d, 0x1a },
 	{ 0x1114d, 0x1a },
-	{ 0x1204d, 0x1a },
-	{ 0x1214d, 0x1a },
-	{ 0x1304d, 0x1a },
-	{ 0x1314d, 0x1a },
-	{ 0x11004d, 0x1a },
-	{ 0x11014d, 0x1a },
-	{ 0x11104d, 0x1a },
-	{ 0x11114d, 0x1a },
-	{ 0x11204d, 0x1a },
-	{ 0x11214d, 0x1a },
-	{ 0x11304d, 0x1a },
-	{ 0x11314d, 0x1a },
 	{ 0x10049, 0xeba },
 	{ 0x10149, 0xeba },
 	{ 0x11049, 0xeba },
 	{ 0x11149, 0xeba },
-	{ 0x12049, 0xeba },
-	{ 0x12149, 0xeba },
-	{ 0x13049, 0xeba },
-	{ 0x13149, 0xeba },
-	{ 0x110049, 0xeba },
-	{ 0x110149, 0xeba },
-	{ 0x111049, 0xeba },
-	{ 0x111149, 0xeba },
-	{ 0x112049, 0xeba },
-	{ 0x112149, 0xeba },
-	{ 0x113049, 0xeba },
-	{ 0x113149, 0xeba },
 	{ 0x43, 0xe7 },
 	{ 0x1043, 0xe7 },
 	{ 0x2043, 0xe7 },
@@ -213,30 +133,14 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{ 0x20075, 0x2 },
 	{ 0x20050, 0x0 },
 	{ 0x20008, 0x320 },
-	{ 0x120008, 0x10a },
 	{ 0x20088, 0x9 },
 	{ 0x200b2, 0x248 },
 	{ 0x10043, 0x5b1 },
 	{ 0x10143, 0x5b1 },
 	{ 0x11043, 0x5b1 },
 	{ 0x11143, 0x5b1 },
-	{ 0x12043, 0x5b1 },
-	{ 0x12143, 0x5b1 },
-	{ 0x13043, 0x5b1 },
-	{ 0x13143, 0x5b1 },
-	{ 0x1200b2, 0x248 },
-	{ 0x110043, 0x5b1 },
-	{ 0x110143, 0x5b1 },
-	{ 0x111043, 0x5b1 },
-	{ 0x111143, 0x5b1 },
-	{ 0x112043, 0x5b1 },
-	{ 0x112143, 0x5b1 },
-	{ 0x113043, 0x5b1 },
-	{ 0x113143, 0x5b1 },
 	{ 0x200fa, 0x1 },
-	{ 0x1200fa, 0x1 },
 	{ 0x20019, 0x5 },
-	{ 0x120019, 0x5 },
 	{ 0x200f0, 0x5555 },
 	{ 0x200f1, 0x5555 },
 	{ 0x200f2, 0x5555 },
@@ -247,15 +151,10 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{ 0x200f7, 0xf000 },
 	{ 0x20025, 0x0 },
 	{ 0x2002d, 0x0 },
-	{ 0x12002d, 0x0 },
 	{ 0x2007d, 0x212 },
-	{ 0x12007d, 0x212 },
 	{ 0x2007c, 0x61 },
-	{ 0x12007c, 0x61 },
 	{ 0x1004a, 0x500 },
 	{ 0x1104a, 0x500 },
-	{ 0x1204a, 0x500 },
-	{ 0x1304a, 0x500 },
 	{ 0x2002c, 0x0 },
 };
 
@@ -988,7 +887,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0x54004, 0x2 },
 	{ 0x54005, 0x2230 },
 	{ 0x54006, 0x25b },
-	{ 0x54007, 0x2000 },
+	{ 0x54007, 0x1000 },
 	{ 0x54008, 0x101 },
 	{ 0x5400b, 0x31f },
 	{ 0x5400c, 0xc8 },
@@ -1008,32 +907,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
 };
 
 
-/* P1 message block paremeter for training firmware */
-struct dram_cfg_param ddr_fsp1_cfg[] = {
-	{ 0xd0000, 0x0 },
-	{ 0x54002, 0x1 },
-	{ 0x54003, 0x42a },
-	{ 0x54004, 0x2 },
-	{ 0x54005, 0x2230 },
-	{ 0x54006, 0x25b },
-	{ 0x54007, 0x2000 },
-	{ 0x54008, 0x101 },
-	{ 0x5400b, 0x21f },
-	{ 0x5400c, 0xc8 },
-	{ 0x5400d, 0x100 },
-	{ 0x54012, 0x1 },
-	{ 0x5402f, 0x4 },
-	{ 0x54030, 0x501 },
-	{ 0x54033, 0x200 },
-	{ 0x54034, 0x600 },
-	{ 0x54035, 0x10 },
-	{ 0x54036, 0x101 },
-	{ 0x5403f, 0x1221 },
-	{ 0x541fc, 0x100 },
-	{ 0xd0000, 0x1 },
-};
-
-
 /* P0 2D message block paremeter for training firmware */
 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0xd0000, 0x0 },
@@ -1041,7 +914,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54004, 0x2 },
 	{ 0x54005, 0x2230 },
 	{ 0x54006, 0x25b },
-	{ 0x54007, 0x2000 },
+	{ 0x54007, 0x1000 },
 	{ 0x54008, 0x101 },
 	{ 0x5400b, 0x61 },
 	{ 0x5400c, 0xc8 },
@@ -1235,14 +1108,10 @@ struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0xd00e7, 0x400 },
 	{ 0x90017, 0x0 },
 	{ 0x90026, 0x2a },
-	{ 0x2000b, 0x64 },
+	{ 0x2000b, 0x384 },
 	{ 0x2000c, 0xc8 },
 	{ 0x2000d, 0x7d0 },
 	{ 0x2000e, 0x2c },
-	{ 0x12000b, 0x21 },
-	{ 0x12000c, 0x42 },
-	{ 0x12000d, 0x29a },
-	{ 0x12000e, 0x21 },
 	{ 0x9000c, 0x0 },
 	{ 0x9000d, 0x173 },
 	{ 0x9000e, 0x60 },
@@ -1265,13 +1134,6 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 		.fsp_cfg = ddr_fsp0_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
 	},
-	{
-		/* P1 1066mts 1D */
-		.drate = 1066,
-		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = ddr_fsp1_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
-	},
 	{
 		/* P0 3200mts 2D */
 		.drate = 3200,
@@ -1293,19 +1155,6 @@ struct dram_timing_info dram_timing = {
 	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
 	.ddrphy_pie = ddr_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-	.fsp_table = { 3200, 1066, },
+	.fsp_table = { 3200, },
 };
 
-#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
-void board_dram_ecc_scrub(void)
-{
-	ddrc_inline_ecc_scrub(0x0,0x7ffffff);
-	ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
-	ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
-	ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
-	ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
-	ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
-	ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
-	ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
-}
-#endif
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 10e87f349d..2fb1eba924 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -53,9 +53,9 @@
 /* ENET1 */
 
 #if defined(CONFIG_CMD_NET)
-#define CONFIG_ETHPRIME                 "eth1" /* Set eqos to primary since we use its MDIO */
+#define CONFIG_ETHPRIME                 "eth0" /* Set fec to primary since we use its MDIO */
 
-#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_XCV_TYPE             RMII // 100 Base-tx reduced pin count interface
 #define CONFIG_FEC_MXC_PHYADDR          1
 
 #define DWC_NET_PHYADDR			1
@@ -209,16 +209,12 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		SZ_32M
 
-/* Totally 6GB DDR */
+/* Totally 1GB DDR */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
-#define PHYS_SDRAM_SIZE			0xC0000000	/* 3 GB */
-#define PHYS_SDRAM_2			0x100000000
-#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
-#define PHYS_SDRAM_2_SIZE		0x40000000	/* 1 GB */
-#else
-#define PHYS_SDRAM_2_SIZE		0xC0000000	/* 3 GB */
-#endif
+#define PHYS_SDRAM_SIZE			0x40000000	/* 1 GB */
+#define PHYS_SDRAM_2			0xC0000000
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
 
 #define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
 
-- 
2.17.1

