/dts-v1/;

/ {
	interrupt-parent = <0x1>;
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "s59-2200 i.MX8DXL";
	compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl";

	aliases {
		ethernet0 = "/bus@5b000000/ethernet@5b040000";
		ethernet1 = "/bus@5b000000/ethernet@5b050000";
		gpio0 = "/bus@5d000000/gpio@5d080000";
		gpio1 = "/bus@5d000000/gpio@5d090000";
		gpio2 = "/bus@5d000000/gpio@5d0a0000";
		gpio3 = "/bus@5d000000/gpio@5d0b0000";
		gpio4 = "/bus@5d000000/gpio@5d0c0000";
		gpio5 = "/bus@5d000000/gpio@5d0d0000";
		gpio6 = "/bus@5d000000/gpio@5d0e0000";
		gpio7 = "/bus@5d000000/gpio@5d0f0000";
		i2c2 = "/bus@5a000000/i2c@5a820000";
		i2c3 = "/bus@5a000000/i2c@5a830000";
		mu1 = "/bus@5d000000/mailbox@5d1c0000";
		serial0 = "/bus@5a000000/serial@5a060000";
		serial1 = "/bus@5a000000/serial@5a070000";
		serial2 = "/bus@5a000000/serial@5a080000";
		serial3 = "/bus@5a000000/serial@5a090000";
		serial4 = "/bus@34000000/serial@37220000";
		can0 = "/bus@5a000000/can@5a8d0000";
		can1 = "/bus@5a000000/can@5a8e0000";
		can2 = "/bus@5a000000/can@5a8f0000";
		mmc0 = "/bus@5b000000/mmc@5b010000";
		mmc1 = "/bus@5b000000/mmc@5b020000";
	};

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <0x2>;
			clocks = <0x3 0x1fb 0x2>;
			#cooling-cells = <0x2>;
			operating-points-v2 = <0x4>;
			phandle = <0x11>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <0x2>;
			clocks = <0x3 0x1fb 0x2>;
			#cooling-cells = <0x2>;
			operating-points-v2 = <0x4>;
			phandle = <0x12>;
		};

		l2-cache0 {
			compatible = "cache";
			phandle = <0x2>;
		};
	};

	opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		phandle = <0x4>;

		opp-900000000 {
			opp-hz = <0x0 0x35a4e900>;
			opp-microvolt = <0xf4240>;
			clock-latency-ns = <0x249f0>;
		};

		opp-1200000000 {
			opp-hz = <0x0 0x47868c00>;
			opp-microvolt = <0x10c8e0>;
			clock-latency-ns = <0x249f0>;
			opp-suspend;
		};
	};

	interrupt-controller@51a00000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x51a00000 0x0 0x10000 0x0 0x51b00000 0x0 0xc0000>;
		#interrupt-cells = <0x3>;
		interrupt-controller;
		interrupts = <0x1 0x9 0x4>;
		phandle = <0x1>;
	};

	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		dsp@92400000 {
			reg = <0x0 0x92400000 0x0 0x2000000>;
			no-map;
		};

		m4@0x88000000 {
			no-map;
			reg = <0x0 0x88000000 0x0 0x8000000>;
		};

		rpmsg@0x90200000 {
			no-map;
			reg = <0x0 0x90200000 0x0 0x200000>;
		};

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x14000000>;
			alloc-ranges = <0x0 0x98000000 0x0 0x14000000>;
			linux,cma-default;
		};

		vdev0vring0@90000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x90000000 0x0 0x8000>;
			no-map;
			phandle = <0x7>;
		};

		vdev0vring1@90008000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x90008000 0x0 0x8000>;
			no-map;
			phandle = <0x8>;
		};

		vdev1vring0@90010000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x90010000 0x0 0x8000>;
			no-map;
			phandle = <0x9>;
		};

		vdev1vring1@90018000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x90018000 0x0 0x8000>;
			no-map;
			phandle = <0xa>;
		};

		rsc-table {
			reg = <0x0 0x900ff000 0x0 0x1000>;
			no-map;
		};

		vdevbuffer {
			compatible = "shared-dma-pool";
			reg = <0x0 0x90400000 0x0 0x100000>;
			no-map;
			phandle = <0x6>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0x1 0x7 0x4>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	rpmsg {
		compatible = "fsl,imx8qxp-rpmsg";
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <0x5 0x0 0x1 0x5 0x1 0x1 0x5 0x3 0x1>;
		mub-partition = <0x3>;
		status = "disabled";
		vdev-nums = <0x2>;
		reg = <0x0 0x90000000 0x0 0x20000>;
		memory-region = <0x6>;
	};

	imx8dxl_cm4@0 {
		compatible = "fsl,imx8qxp-cm4";
		rsc-da = <0x90000000>;
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <0x5 0x0 0x1 0x5 0x1 0x1 0x5 0x3 0x1>;
		mub-partition = <0x3>;
		core-index = <0x0>;
		core-id = <0x116>;
		status = "okay";
		memory-region = <0x7 0x8 0x6 0x9 0xa>;
	};

	scu {
		compatible = "fsl,imx-scu";
		mbox-names = "tx0", "tx1", "tx2", "tx3", "rx0", "rx1", "rx2", "rx3", "gip3";
		mboxes = <0xb 0x0 0x0 0xb 0x0 0x1 0xb 0x0 0x2 0xb 0x0 0x3 0xb 0x1 0x0 0xb 0x1 0x1 0xb 0x1 0x2 0xb 0x1 0x3 0xb 0x3 0x3>;

		imx8dxl-pd {
			compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
			#power-domain-cells = <0x1>;
			wakeup-irq = <0xa0 0xa3 0xeb 0xec 0xed 0xe4 0xe5 0xe6 0xe7 0xee 0xef 0xf0 0xa6 0xa9>;
			phandle = <0x14>;
		};

		clock-controller {
			compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
			#clock-cells = <0x2>;
			clocks = <0xc 0xd>;
			clock-names = "xtal_32KHz", "xtal_24Mhz";
			phandle = <0x3>;
		};

		pinctrl {
			compatible = "fsl,imx8dxl-iomuxc";
			pinctrl-names = "default";
			pinctrl-0 = <0xe>;

			hoggrp {
				fsl,pins = <0x3c 0x0 0x514a0 0x49 0x0 0x14a0 0x6c 0x4 0x21 0x6b 0x4 0x21 0x2b 0x4 0x21 0x7c 0x4 0x21 0x7e 0x4 0x21 0x78 0x4 0x21 0x7b 0x4 0x21 0x7a 0x4 0x21 0x7d 0x4 0x21 0x84 0x4 0x21 0x3f 0x4 0x21 0x3d 0x4 0x21 0x40 0x4 0x21 0x3e 0x4 0x21 0x80 0x4 0x21 0x81 0x4 0x21 0x83 0x4 0x21 0x86 0x4 0x21>;
				phandle = <0xe>;
			};

			otg1 {
				fsl,pins = <0x4 0x1 0x21>;
				phandle = <0x4b>;
			};

			fec1grp {
				fsl,pins = <0x23 0x0 0x14a0 0x2a 0x0 0x14a0 0x2d 0x0 0x6000020 0x2c 0x0 0x6000020 0x1e 0x0 0x60 0x1d 0x0 0x60 0x1f 0x0 0x60 0x20 0x0 0x60 0x21 0x0 0x60 0x22 0x0 0x60 0x24 0x0 0x60 0x25 0x0 0x60 0x26 0x0 0x60 0x27 0x0 0x60 0x28 0x0 0x60 0x29 0x0 0x60>;
				phandle = <0x54>;
			};

			lpspi0grp {
				fsl,pins = <0x4a 0x0 0x600004c 0x4c 0x0 0x600004c 0x4b 0x0 0x600004c 0x4e 0x0 0x21 0x4d 0x0 0x21>;
				phandle = <0x30>;
			};

			lpspi2grp {
				fsl,pins = <0x16 0x2 0x600004c 0x17 0x2 0x600004c 0x19 0x2 0x600004c 0x1a 0x5 0x21>;
				phandle = <0x32>;
			};

			i2c2grp {
				fsl,pins = <0x73 0x2 0x6000021 0x74 0x2 0x6000021>;
				phandle = <0x41>;
			};

			lpuart0grp {
				fsl,pins = <0x5c 0x0 0x6000020 0x5d 0x0 0x6000020>;
				phandle = <0x36>;
			};

			lpuart2grp {
				fsl,pins = <0x5f 0x0 0x6000020 0x5e 0x0 0x6000020>;
				phandle = <0x39>;
			};

			lpuart1grp {
				fsl,pins = <0x45 0x0 0x6000020 0x46 0x0 0x6000020 0x47 0x0 0x6000020 0x48 0x0 0x6000020>;
			};

			flexcan1grp {
				fsl,pins = <0x57 0x0 0x21 0x56 0x0 0x21 0x5a 0x4 0x21>;
				phandle = <0x44>;
			};

			flexcan2grp {
				fsl,pins = <0x59 0x0 0x21 0x58 0x0 0x21 0x5b 0x4 0x21>;
				phandle = <0x46>;
			};

			usdhc1grp {
				fsl,pins = <0x9 0x0 0x6000041 0xa 0x0 0x21 0xb 0x0 0x21 0xc 0x0 0x21 0xd 0x0 0x21 0xe 0x0 0x21 0xf 0x0 0x21 0x10 0x0 0x21 0x11 0x0 0x21 0x12 0x0 0x21 0x13 0x0 0x41>;
				phandle = <0x4e>;
			};

			usdhc1grp100mhz {
				fsl,pins = <0x9 0x0 0x6000041 0xa 0x0 0x21 0xb 0x0 0x21 0xc 0x0 0x21 0xd 0x0 0x21 0xe 0x0 0x21 0xf 0x0 0x21 0x10 0x0 0x21 0x11 0x0 0x21 0x12 0x0 0x21 0x13 0x0 0x41>;
				phandle = <0x4f>;
			};

			usdhc1grp200mhz {
				fsl,pins = <0x9 0x0 0x6000041 0xa 0x0 0x21 0xb 0x0 0x21 0xc 0x0 0x21 0xd 0x0 0x21 0xe 0x0 0x21 0xf 0x0 0x21 0x10 0x0 0x21 0x11 0x0 0x21 0x12 0x0 0x21 0x13 0x0 0x41>;
				phandle = <0x50>;
			};
		};

		imx8qx-ocotp {
			compatible = "fsl,imx8qxp-scu-ocotp";
			#address-cells = <0x1>;
			#size-cells = <0x1>;

			mac@2c4 {
				reg = <0x2c4 0x6>;
				phandle = <0x56>;
			};

			mac@2c6 {
				reg = <0x2c6 0x6>;
			};
		};

		rtc {
			compatible = "fsl,imx8qxp-sc-rtc";
		};

		watchdog {
			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
			timeout-sec = <0x3c>;
		};

		thermal-sensor {
			compatible = "fsl,imx8qxp-sc-thermal";
			tsens-num = <0x2>;
			#thermal-sensor-cells = <0x1>;
			phandle = <0xf>;
		};
	};

	soc {
		compatible = "fsl,imx8qxp-soc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
	};

	thermal-zones {

		cpu-thermal0 {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x7d0>;
			thermal-sensors = <0xf 0x163>;

			trips {

				trip0 {
					temperature = <0x1a1f8>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x10>;
				};

				trip1 {
					temperature = <0x1f018>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0x10>;
					cooling-device = <0x11 0xffffffff 0xffffffff 0x12 0xffffffff 0xffffffff>;
				};
			};
		};

		pmic-thermal0 {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x7d0>;
			thermal-sensors = <0xf 0x1f1>;

			trips {

				trip0 {
					temperature = <0x1adb0>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x13>;
				};

				trip1 {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0x13>;
					cooling-device = <0x11 0xffffffff 0xffffffff 0x12 0xffffffff 0xffffffff>;
				};
			};
		};
	};

	clock-dummy {
		compatible = "fixed-clock";
		#clock-cells = <0x0>;
		clock-frequency = <0x0>;
		clock-output-names = "clk_dummy";
		phandle = <0x25>;
	};

	clock-xtal32k {
		compatible = "fixed-clock";
		#clock-cells = <0x0>;
		clock-frequency = <0x8000>;
		clock-output-names = "xtal_32KHz";
		phandle = <0xc>;
	};

	clock-xtal24m {
		compatible = "fixed-clock";
		#clock-cells = <0x0>;
		clock-frequency = <0x16e3600>;
		clock-output-names = "xtal_24MHz";
		phandle = <0xd>;
	};

	imx_ion {
		compatible = "fsl,mxc-ion";
		fsl,heap-id = <0x0>;
	};

	sc-powerkey {
		compatible = "fsl,imx8-pwrkey";
		linux,keycode = <0x74>;
		wakeup-source;
	};

	bus@2C000000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x2c000000 0x0 0x2c000000 0x50000>;

		mu@2C000000 {
			compatible = "fsl,imx8-mu-seco";
			reg = <0x2c000000 0x10000>;
			interrupts = <0x0 0x154 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0x1a>;
			status = "okay";
			phandle = <0x15>;
		};

		mu@2c010000 {
			compatible = "fsl,imx8-mu-seco";
			reg = <0x2c010000 0x10000>;
			interrupts = <0x0 0x156 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0x1b>;
			status = "okay";
			phandle = <0x16>;
		};

		mu@2c020000 {
			compatible = "fsl,imx8-mu-seco";
			reg = <0x2c020000 0x10000>;
			interrupts = <0x0 0x158 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0x1f>;
			status = "okay";
			phandle = <0x17>;
		};

		mu@2c030000 {
			compatible = "fsl,imx8-mu-seco";
			reg = <0x2c030000 0x10000>;
			interrupts = <0x0 0x15c 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0x28>;
			status = "okay";
			phandle = <0x18>;
		};

		mu@2c040000 {
			compatible = "fsl,imx8-mu-seco";
			reg = <0x2c040000 0x10000>;
			interrupts = <0x0 0x15e 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0x29>;
			status = "okay";
			phandle = <0x19>;
		};
	};

	v2x_mu_sv0 {
		compatible = "fsl,imx-seco-mu";
		mbox-names = "txdb", "rxdb";
		mboxes = <0x15 0x2 0x0 0x15 0x3 0x0>;
		fsl,seco_mu_id = <0x4>;
		fsl,seco_max_users = <0x2>;
		fsl,cmd_tag = [18];
		fsl,rsp_tag = [e2];
		status = "okay";
	};

	v2x_mu_sv1 {
		compatible = "fsl,imx-seco-mu";
		mbox-names = "txdb", "rxdb";
		mboxes = <0x16 0x2 0x0 0x16 0x3 0x0>;
		fsl,seco_mu_id = <0x5>;
		fsl,seco_max_users = <0x2>;
		fsl,cmd_tag = [19];
		fsl,rsp_tag = [e3];
		status = "okay";
	};

	v2x_mu_she {
		compatible = "fsl,imx-seco-mu";
		mbox-names = "txdb", "rxdb";
		mboxes = <0x17 0x2 0x0 0x17 0x3 0x0>;
		fsl,seco_mu_id = <0x6>;
		fsl,seco_max_users = <0x2>;
		fsl,cmd_tag = [1a];
		fsl,rsp_tag = [e4];
		status = "okay";
	};

	v2x_mu_sg0 {
		compatible = "fsl,imx-seco-mu";
		mbox-names = "txdb", "rxdb";
		mboxes = <0x18 0x2 0x0 0x18 0x3 0x0>;
		fsl,seco_mu_id = <0x7>;
		fsl,seco_max_users = <0x2>;
		fsl,cmd_tag = [1d];
		fsl,rsp_tag = [e7];
		status = "okay";
	};

	v2x_mu_sg1 {
		compatible = "fsl,imx-seco-mu";
		mbox-names = "txdb", "rxdb";
		mboxes = <0x19 0x2 0x0 0x19 0x3 0x0>;
		fsl,seco_mu_id = <0x8>;
		fsl,seco_max_users = <0x2>;
		fsl,cmd_tag = [1e];
		fsl,rsp_tag = [e8];
		status = "okay";
	};

	bus@31400000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x31400000 0x0 0x31400000 0x410000>;

		crypto@31400000 {
			compatible = "fsl,sec-v4.0";
			reg = <0x31400000 0x90000>;
			interrupts = <0x0 0x94 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x31400000 0x90000>;
			fsl,sec-era = <0x9>;
			power-domains = <0x14 0x1f5>;
			power-domain-names = "jr";

			jr@30000 {
				compatible = "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <0x0 0x143 0x4>;
				power-domains = <0x14 0x1f5>;
				power-domain-names = "jr";
			};

			jr@40000 {
				compatible = "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <0x0 0x144 0x4>;
				power-domains = <0x14 0x1f6>;
				power-domain-names = "jr";
			};
		};

		caam-sm@31800000 {
			compatible = "fsl,imx6q-caam-sm";
			reg = <0x31800000 0x10000>;
		};

		mu@31560000 {
			compatible = "fsl,imx8-mu-seco";
			reg = <0x31560000 0x10000>;
			interrupts = <0x0 0x13e 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0x1f7>;
			status = "okay";
			phandle = <0x1a>;
		};

		mu@31570000 {
			compatible = "fsl,imx8-mu-seco";
			reg = <0x31570000 0x10000>;
			interrupts = <0x0 0x13f 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0x1f8>;
			status = "okay";
			phandle = <0x1b>;
		};

		mu@31580000 {
			compatible = "fsl,imx8-mu-seco";
			reg = <0x31580000 0x10000>;
			interrupts = <0x0 0x140 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0x1f9>;
			status = "okay";
			phandle = <0x1c>;
		};
	};

	seco_mu1 {
		compatible = "fsl,imx-seco-mu";
		mbox-names = "txdb", "rxdb";
		mboxes = <0x1a 0x2 0x0 0x1a 0x3 0x0>;
		fsl,seco_mu_id = <0x1>;
		fsl,seco_max_users = <0x4>;
		status = "okay";
	};

	seco_mu2 {
		compatible = "fsl,imx-seco-mu";
		mbox-names = "txdb", "rxdb";
		mboxes = <0x1b 0x2 0x0 0x1b 0x3 0x0>;
		fsl,seco_mu_id = <0x2>;
		fsl,seco_max_users = <0x4>;
		status = "okay";
	};

	seco_mu3 {
		compatible = "fsl,imx-seco-mu";
		mbox-names = "txdb", "rxdb";
		mboxes = <0x1c 0x2 0x0 0x1c 0x3 0x0>;
		fsl,seco_mu_id = <0x3>;
		fsl,seco_max_users = <0x4>;
		status = "okay";
	};

	bus@34000000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x34000000 0x0 0x34000000 0x4000000>;

		clock-cm40-ipg {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x7de2900>;
			clock-output-names = "cm40_ipg_clk";
			phandle = <0x1f>;
		};

		i2c@37230000 {
			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
			reg = <0x37230000 0x1000>;
			interrupts = <0x9 0x4>;
			interrupt-parent = <0x1d>;
			clocks = <0x1e 0x0 0x1e 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x120 0x2>;
			assigned-clock-rates = <0x16e3600>;
			power-domains = <0x14 0x120>;
			status = "disabled";
		};

		clock-controller@37630000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x37630000 0x1000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x120 0x2 0x1f>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "cm40_lpcg_i2c_clk", "cm40_lpcg_i2c_ipg_clk";
			power-domains = <0x14 0x120>;
			phandle = <0x1e>;
		};

		intmux@37400000 {
			compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux";
			reg = <0x37400000 0x1000>;
			interrupts = <0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4 0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4>;
			interrupt-controller;
			interrupt-parent = <0x1>;
			#interrupt-cells = <0x2>;
			clocks = <0x1f>;
			clock-names = "ipg";
			power-domains = <0x14 0x121>;
			status = "okay";
			phandle = <0x1d>;
		};

		serial@37220000 {
			compatible = "fsl,imx8qxp-lpuart";
			reg = <0x37220000 0x1000>;
			interrupts = <0x7 0x4>;
			interrupt-parent = <0x1d>;
			clocks = <0x20 0x1 0x20 0x0>;
			clock-names = "ipg", "baud";
			assigned-clocks = <0x3 0x11f 0x2>;
			assigned-clock-rates = <0x16e3600>;
			power-domains = <0x14 0x11f>;
			status = "disabled";
		};

		clock-controller@37620000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x37620000 0x1000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x11f 0x2 0x1f>;
			bit-offset = <0x0 0x4>;
			clock-output-names = "cm40_lpcg_uart_clk", "cm40_lpcg_uart_ipg_clk";
			power-domains = <0x14 0x11f>;
			phandle = <0x20>;
		};
	};

	bus@59000000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x59000000 0x0 0x59000000 0x1000000>;

		clock-audio-ipg {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x9896800>;
			clock-output-names = "audio_ipg_clk";
			phandle = <0x28>;
		};

		dma-controller@591F0000 {
			compatible = "fsl,imx8qm-edma";
			reg = <0x59200000 0x10000 0x59210000 0x10000 0x59220000 0x10000 0x59230000 0x10000 0x59240000 0x10000 0x59250000 0x10000 0x59280000 0x10000 0x59290000 0x10000 0x592c0000 0x10000 0x592d0000 0x10000 0x592e0000 0x10000 0x592f0000 0x10000 0x59300000 0x10000 0x59310000 0x10000 0x59350000 0x10000 0x59360000 0x10000 0x59370000 0x10000 0x59380000 0x10000>;
			#dma-cells = <0x3>;
			shared-interrupt;
			dma-channels = <0x12>;
			interrupts = <0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4 0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x147 0x4 0x0 0x149 0x4 0x0 0xbd 0x4 0x0 0xbd 0x4 0x0 0xbf 0x4 0x0 0xbf 0x4 0x0 0xc1 0x4 0x0 0xc7 0x4 0x0 0x10c 0x4 0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4>;
			interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", "edma0-chan2-rx", "edma0-chan3-tx", "edma0-chan4-tx", "edma0-chan5-tx", "edma0-chan8-rx", "edma0-chan9-tx", "edma0-chan12-rx", "edma0-chan13-tx", "edma0-chan14-rx", "edma0-chan15-tx", "edma0-chan16-rx", "edma0-chan17-rx", "edma0-chan21-tx", "edma0-chan22-tx", "edma0-chan23-tx", "edma0-chan24-rx";
			power-domains = <0x14 0x40 0x14 0x41 0x14 0x42 0x14 0x43 0x14 0x44 0x14 0x45 0x14 0x48 0x14 0x49 0x14 0x4c 0x14 0x4d 0x14 0x4e 0x14 0x4f 0x14 0x50 0x14 0x51 0x14 0x55 0x14 0x56 0x14 0x57 0x14 0x58>;
			power-domain-names = "edma0-chan0", "edma0-chan1", "edma0-chan2", "edma0-chan3", "edma0-chan4", "edma0-chan5", "edma0-chan8", "edma0-chan9", "edma0-chan12", "edma0-chan13", "edma0-chan14", "edma0-chan15", "edma0-chan16", "edma0-chan17", "edma0-chan21", "edma0-chan22", "edma0-chan23", "edma0-chan24";
			status = "okay";
			phandle = <0x26>;
		};

		acm@59e00000 {
			compatible = "nxp,imx8dxl-acm";
			reg = <0x59e00000 0x1d0000>;
			#clock-cells = <0x1>;
			power-domains = <0x14 0x1ed 0x14 0x1ee 0x14 0x1ef 0x14 0x1f0 0x14 0x145 0x14 0x1ec 0x14 0x19e 0x14 0x13e 0x14 0x13f 0x14 0x140 0x14 0x1a2 0x14 0x1a0 0x14 0x1cb>;
			phandle = <0x24>;
		};

		asrc@59000000 {
			compatible = "fsl,imx8qm-asrc0";
			reg = <0x59000000 0x10000>;
			interrupts = <0x0 0x174 0x4 0x0 0x175 0x4>;
			clocks = <0x21 0x0 0x21 0x0 0x22 0x0 0x23 0x0 0x24 0x0 0x24 0x2 0x25 0x25 0x25 0x25 0x25 0x25 0x25 0x25 0x25 0x25 0x25 0x25 0x25>;
			clock-names = "ipg", "mem", "asrck_0", "asrck_1", "asrck_2", "asrck_3", "asrck_4", "asrck_5", "asrck_6", "asrck_7", "asrck_8", "asrck_9", "asrck_a", "asrck_b", "asrck_c", "asrck_d", "asrck_e", "asrck_f", "spba";
			dmas = <0x26 0x0 0x0 0x0 0x26 0x1 0x0 0x0 0x26 0x2 0x0 0x0 0x26 0x3 0x0 0x1 0x26 0x4 0x0 0x1 0x26 0x5 0x0 0x1>;
			dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
			fsl,asrc-rate = <0xbb80>;
			fsl,asrc-width = <0x10>;
			power-domains = <0x14 0x19e>;
			status = "okay";
		};

		spdif@59020000 {
			compatible = "fsl,imx8qm-spdif";
			reg = <0x59020000 0x10000>;
			interrupts = <0x0 0x146 0x4 0x0 0x148 0x4>;
			clocks = <0x27 0x1 0x25 0x27 0x0 0x25 0x25 0x25 0x28 0x25 0x25 0x25>;
			clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba";
			dmas = <0x26 0x8 0x0 0x5 0x26 0x9 0x0 0x4>;
			dma-names = "rx", "tx";
			power-domains = <0x14 0x1a0>;
			status = "disabled";
		};

		sai@59040000 {
			compatible = "fsl,imx8qm-sai";
			reg = <0x59040000 0x10000>;
			interrupts = <0x0 0xbc 0x4>;
			clocks = <0x29 0x1 0x25 0x29 0x0 0x25 0x25>;
			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
			dma-names = "rx", "tx";
			dmas = <0x26 0xc 0x0 0x1 0x26 0xd 0x0 0x0>;
			power-domains = <0x14 0x13e>;
			status = "disabled";
		};

		sai@59050000 {
			compatible = "fsl,imx8qm-sai";
			reg = <0x59050000 0x10000>;
			interrupts = <0x0 0xbe 0x4>;
			clocks = <0x2a 0x1 0x25 0x2a 0x0 0x25 0x25>;
			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
			dma-names = "rx", "tx";
			dmas = <0x26 0xe 0x0 0x1 0x26 0xf 0x0 0x0>;
			power-domains = <0x14 0x13f>;
			status = "disabled";
		};

		sai@59060000 {
			compatible = "fsl,imx8qm-sai";
			reg = <0x59060000 0x10000>;
			interrupts = <0x0 0xc0 0x4>;
			clocks = <0x2b 0x1 0x25 0x2b 0x0 0x25 0x25>;
			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
			dma-names = "rx";
			dmas = <0x26 0x10 0x0 0x1>;
			power-domains = <0x14 0x140>;
			status = "disabled";
		};

		sai@59070000 {
			compatible = "fsl,imx8qm-sai";
			reg = <0x59070000 0x10000>;
			interrupts = <0x0 0xc6 0x4>;
			clocks = <0x2c 0x1 0x25 0x2c 0x0 0x25 0x25>;
			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
			dma-names = "rx";
			dmas = <0x26 0x11 0x0 0x1>;
			power-domains = <0x14 0x1a2>;
			status = "disabled";
		};

		mqs@59850000 {
			compatible = "fsl,imx8qm-mqs";
			reg = <0x59850000 0x10000>;
			clocks = <0x2d 0x1 0x2d 0x0>;
			clock-names = "core", "mclk";
			power-domains = <0x14 0x1cb>;
			status = "disabled";
		};

		clock-controller@59400000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59400000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x28>;
			bit-offset = <0x10>;
			clock-output-names = "asrc0_lpcg_ipg_clk";
			power-domains = <0x14 0x19e>;
			phandle = <0x21>;
		};

		clock-controller@59420000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59420000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x24 0x13 0x28>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "spdif0_lpcg_tx_clk", "spdif0_lpcg_gclkw";
			power-domains = <0x14 0x1a0>;
			phandle = <0x27>;
		};

		clock-controller@59440000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59440000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x24 0xd 0x28>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "sai0_lpcg_mclk", "sai0_lpcg_ipg_clk";
			power-domains = <0x14 0x13e>;
			phandle = <0x29>;
		};

		clock-controller@59450000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59450000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x24 0xe 0x28>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "sai1_lpcg_mclk", "sai1_lpcg_ipg_clk";
			power-domains = <0x14 0x13f>;
			phandle = <0x2a>;
		};

		clock-controller@59460000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59460000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x24 0xf 0x28>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "sai2_lpcg_mclk", "sai2_lpcg_ipg_clk";
			power-domains = <0x14 0x140>;
			phandle = <0x2b>;
		};

		clock-controller@59470000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59470000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x24 0x10 0x28>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "sai3_lpcg_mclk", "sai3_lpcg_ipg_clk";
			power-domains = <0x14 0x1a2>;
			phandle = <0x2c>;
		};

		clock-controller@59c50000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59c50000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x24 0x14 0x28>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "mqs0_lpcg_mclk", "mqs0_lpcg_ipg_clk";
			power-domains = <0x14 0x1cb>;
			phandle = <0x2d>;
		};

		clock-controller@59d00000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59d00000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x145 0x1>;
			bit-offset = <0x0>;
			clock-output-names = "aud_rec_clk0_lpcg_clk";
			power-domains = <0x14 0x145>;
		};

		clock-controller@59d10000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59d10000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x1ec 0x1>;
			bit-offset = <0x0>;
			clock-output-names = "aud_rec_clk1_lpcg_clk";
			power-domains = <0x14 0x1ec>;
		};

		clock-controller@59d20000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59d20000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x145 0x0>;
			bit-offset = <0x0>;
			clock-output-names = "aud_pll_div_clk0_lpcg_clk";
			power-domains = <0x14 0x145>;
			phandle = <0x22>;
		};

		clock-controller@59d30000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59d30000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x1ec 0x0>;
			bit-offset = <0x0>;
			clock-output-names = "aud_pll_div_clk1_lpcg_clk";
			power-domains = <0x14 0x1ec>;
			phandle = <0x23>;
		};

		clock-controller@59d50000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59d50000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x24 0x4>;
			bit-offset = <0x0>;
			clock-output-names = "mclkout0_lpcg_clk";
			power-domains = <0x14 0x1ef>;
		};

		clock-controller@59d60000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x59d60000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x24 0x5>;
			bit-offset = <0x0>;
			clock-output-names = "mclkout1_lpcg_clk";
			power-domains = <0x14 0x1f0>;
		};
	};

	bus@5a000000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;

		clock-dma-ipg {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x9896800>;
			clock-output-names = "dma_ipg_clk";
			phandle = <0x3b>;
		};

		spi@5a000000 {
			compatible = "fsl,imx8dxl-spi", "fsl,IMX8DXL-spi", "fsl,imx7ulp-spi";
			reg = <0x5a000000 0x10000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			interrupts = <0x0 0x150 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x2e 0x0 0x2e 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x35 0x2>;
			assigned-clock-rates = <0x1312d00>;
			power-domains = <0x14 0x35>;
			dma-names = "tx", "rx";
			dmas = <0x2f 0x1 0x0 0x0 0x2f 0x0 0x0 0x1>;
			status = "okay";
			fsl,spi-num-chipselects = <0x1>;
			pinctrl-names = "default";
			pinctrl-0 = <0x30>;

			spi@0 {
				reg = <0x0>;
				compatible = "linux,spidev";
				spi-max-frequency = <0x1312d00>;
			};
		};

		spi@5a020000 {
			compatible = "fsl,imx8dxl-spi", "fsl,IMX8DXL-spi", "fsl,imx7ulp-spi";
			reg = <0x5a020000 0x10000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			interrupts = <0x0 0xdc 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x31 0x0 0x31 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x37 0x2>;
			assigned-clock-rates = <0x3938700>;
			power-domains = <0x14 0x37>;
			dma-names = "tx", "rx";
			dmas = <0x2f 0x5 0x0 0x0 0x2f 0x4 0x0 0x1>;
			status = "okay";
			fsl,spi-num-chipselects = <0x1>;
			pinctrl-names = "default";
			pinctrl-0 = <0x32>;
			cs-gpios = <0x33 0xb 0x1>;

			spi@0 {
				reg = <0x0>;
				compatible = "linux,spidev";
				spi-max-frequency = <0x1312d00>;
			};
		};

		spi@5a030000 {
			compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi";
			reg = <0x5a030000 0x10000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			interrupts = <0x0 0xdd 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x34 0x0 0x34 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x38 0x2>;
			assigned-clock-rates = <0x3938700>;
			power-domains = <0x14 0x38>;
			dma-names = "tx", "rx";
			dmas = <0x2f 0x7 0x0 0x0 0x2f 0x6 0x0 0x1>;
			status = "disabled";
		};

		serial@5a060000 {
			reg = <0x5a060000 0x1000>;
			interrupts = <0x0 0xe4 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x35 0x1 0x35 0x0>;
			clock-names = "ipg", "baud";
			assigned-clocks = <0x3 0x39 0x2>;
			assigned-clock-rates = <0x4c4b400>;
			power-domains = <0x14 0x39>;
			status = "okay";
			compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
			pinctrl-names = "default";
			pinctrl-0 = <0x36>;
		};

		serial@5a070000 {
			reg = <0x5a070000 0x1000>;
			interrupts = <0x0 0xe5 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x37 0x1 0x37 0x0>;
			clock-names = "ipg", "baud";
			assigned-clocks = <0x3 0x3a 0x2>;
			assigned-clock-rates = <0x4c4b400>;
			power-domains = <0x14 0x3a>;
			power-domain-names = "uart";
			dma-names = "tx", "rx";
			dmas = <0x2f 0xb 0x0 0x0 0x2f 0xa 0x0 0x1>;
			status = "disabled";
			compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
		};

		serial@5a080000 {
			reg = <0x5a080000 0x1000>;
			interrupts = <0x0 0xe6 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x38 0x1 0x38 0x0>;
			clock-names = "ipg", "baud";
			assigned-clocks = <0x3 0x3b 0x2>;
			assigned-clock-rates = <0x4c4b400>;
			power-domains = <0x14 0x3b>;
			power-domain-names = "uart";
			dma-names = "tx", "rx";
			dmas = <0x2f 0xd 0x0 0x0 0x2f 0xc 0x0 0x1>;
			status = "okay";
			compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
			pinctrl-names = "default";
			pinctrl-0 = <0x39>;
		};

		serial@5a090000 {
			reg = <0x5a090000 0x1000>;
			interrupts = <0x0 0xe7 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x3a 0x1 0x3a 0x0>;
			clock-names = "ipg", "baud";
			assigned-clocks = <0x3 0x3c 0x2>;
			assigned-clock-rates = <0x4c4b400>;
			power-domains = <0x14 0x3c>;
			power-domain-names = "uart";
			dma-names = "tx", "rx";
			dmas = <0x2f 0xf 0x0 0x0 0x2f 0xe 0x0 0x1>;
			status = "disabled";
			compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
		};

		dma-controller@5a1f0000 {
			compatible = "fsl,imx8qm-edma";
			reg = <0x5a200000 0x10000 0x5a210000 0x10000 0x5a220000 0x10000 0x5a230000 0x10000 0x5a240000 0x10000 0x5a250000 0x10000 0x5a260000 0x10000 0x5a270000 0x10000 0x5a280000 0x10000 0x5a290000 0x10000 0x5a2a0000 0x10000 0x5a2b0000 0x10000 0x5a2c0000 0x10000 0x5a2d0000 0x10000 0x5a2e0000 0x10000 0x5a2f0000 0x10000>;
			#dma-cells = <0x3>;
			dma-channels = <0x10>;
			interrupts = <0x0 0x120 0x4 0x0 0x121 0x4 0x0 0x122 0x4 0x0 0x123 0x4 0x0 0x124 0x4 0x0 0x125 0x4 0x0 0x126 0x4 0x0 0x127 0x4 0x0 0x134 0x4 0x0 0x135 0x4 0x0 0x136 0x4 0x0 0x137 0x4 0x0 0x138 0x4 0x0 0x139 0x4 0x0 0x13a 0x4 0x0 0x13b 0x4>;
			interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx", "edma2-chan2-rx", "edma2-chan3-tx", "edma2-chan4-rx", "edma2-chan5-tx", "edma2-chan6-rx", "edma2-chan7-tx", "edma2-chan8-rx", "edma2-chan9-tx", "edma2-chan10-rx", "edma2-chan11-tx", "edma2-chan12-rx", "edma2-chan13-tx", "edma2-chan14-rx", "edma2-chan15-tx";
			power-domains = <0x14 0xfe 0x14 0xff 0x14 0x100 0x14 0x101 0x14 0x102 0x14 0x1ab 0x14 0x1ac 0x14 0x1ad 0x14 0x1ae 0x14 0x1af 0x14 0x1b0 0x14 0x1b1 0x14 0x1b2 0x14 0x1b3 0x14 0x1b4 0x14 0x1b5>;
			power-domain-names = "edma2-chan0", "edma2-chan1", "edma2-chan2", "edma2-chan3", "edma2-chan4", "edma2-chan5", "edma2-chan6", "edma2-chan7", "edma2-chan8", "edma2-chan9", "edma2-chan10", "edma2-chan11", "edma2-chan12", "edma2-chan13", "edma2-chan14", "edma2-chan15";
			status = "okay";
			phandle = <0x2f>;
		};

		clock-controller@5a400000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a400000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x35 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "spi0_lpcg_clk", "spi0_lpcg_ipg_clk";
			power-domains = <0x14 0x35>;
			phandle = <0x2e>;
		};

		clock-controller@5a410000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a410000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x36 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "spi1_lpcg_clk", "spi1_lpcg_ipg_clk";
			power-domains = <0x14 0x36>;
		};

		clock-controller@5a420000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a420000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x37 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "spi2_lpcg_clk", "spi2_lpcg_ipg_clk";
			power-domains = <0x14 0x37>;
			phandle = <0x31>;
		};

		clock-controller@5a430000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a430000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x38 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "spi3_lpcg_clk", "spi3_lpcg_ipg_clk";
			power-domains = <0x14 0x38>;
			phandle = <0x34>;
		};

		clock-controller@5a460000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a460000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x39 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "uart0_lpcg_baud_clk", "uart0_lpcg_ipg_clk";
			power-domains = <0x14 0x39>;
			phandle = <0x35>;
		};

		clock-controller@5a470000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a470000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x3a 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "uart1_lpcg_baud_clk", "uart1_lpcg_ipg_clk";
			power-domains = <0x14 0x3a>;
			phandle = <0x37>;
		};

		clock-controller@5a480000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a480000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x3b 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "uart2_lpcg_baud_clk", "uart2_lpcg_ipg_clk";
			power-domains = <0x14 0x3b>;
			phandle = <0x38>;
		};

		clock-controller@5a490000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a490000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x3c 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "uart3_lpcg_baud_clk", "uart3_lpcg_ipg_clk";
			power-domains = <0x14 0x3c>;
			phandle = <0x3a>;
		};

		adc@5a880000 {
			compatible = "fsl,imx8qxp-adc";
			reg = <0x5a880000 0x10000>;
			interrupts = <0x0 0x92 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x3c 0x0 0x3c 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x65 0x2>;
			assigned-clock-rates = <0x16e3600>;
			power-domains = <0x14 0x65>;
			status = "okay";
			vref-supply = <0x3d>;
		};

		i2c@5a800000 {
			reg = <0x5a800000 0x4000>;
			interrupts = <0x0 0xde 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x3e 0x0 0x3e 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x60 0x2>;
			assigned-clock-rates = <0x16e3600>;
			power-domains = <0x14 0x60>;
			status = "disabled";
			compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
		};

		i2c@5a810000 {
			reg = <0x5a810000 0x4000>;
			interrupts = <0x0 0xdf 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x3f 0x0 0x3f 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x61 0x2>;
			assigned-clock-rates = <0x16e3600>;
			power-domains = <0x14 0x61>;
			status = "disabled";
			compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
		};

		i2c@5a820000 {
			reg = <0x5a820000 0x4000>;
			interrupts = <0x0 0xe0 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x40 0x0 0x40 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x62 0x2>;
			assigned-clock-rates = <0x16e3600>;
			power-domains = <0x14 0x62>;
			status = "okay";
			compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-frequency = <0x186a0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x41>;
		};

		i2c@5a830000 {
			reg = <0x5a830000 0x4000>;
			interrupts = <0x0 0xe1 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x42 0x0 0x42 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0x63 0x2>;
			assigned-clock-rates = <0x16e3600>;
			power-domains = <0x14 0x63>;
			status = "disabled";
			compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
		};

		can@5a8d0000 {
			compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
			reg = <0x5a8d0000 0x10000>;
			interrupts = <0x0 0xee 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x43 0x1 0x43 0x0>;
			clock-names = "ipg", "per";
			assigned-clocks = <0x3 0x69 0x2>;
			assigned-clock-rates = <0x2625a00>;
			power-domains = <0x14 0x69>;
			fsl,clk-source = <0x0>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x44>;
			xceiver-supply = <0x45>;
		};

		can@5a8e0000 {
			compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
			reg = <0x5a8e0000 0x10000>;
			interrupts = <0x0 0xef 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x43 0x1 0x43 0x0>;
			clock-names = "ipg", "per";
			assigned-clocks = <0x3 0x69 0x2>;
			assigned-clock-rates = <0x2625a00>;
			power-domains = <0x14 0x6a>;
			fsl,clk-source = <0x0>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x46>;
			xceiver-supply = <0x47>;
		};

		can@5a8f0000 {
			compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
			reg = <0x5a8f0000 0x10000>;
			interrupts = <0x0 0xf0 0x4>;
			interrupt-parent = <0x1>;
			clocks = <0x43 0x1 0x43 0x0>;
			clock-names = "ipg", "per";
			assigned-clocks = <0x3 0x69 0x2>;
			assigned-clock-rates = <0x2625a00>;
			power-domains = <0x14 0x6b>;
			fsl,clk-source = <0x0>;
			status = "disabled";
		};

		clock-controller@5ac80000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5ac80000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x65 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "adc0_lpcg_clk", "adc0_lpcg_ipg_clk";
			power-domains = <0x14 0x65>;
			phandle = <0x3c>;
		};

		clock-controller@5ac00000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5ac00000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x60 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "i2c0_lpcg_clk", "i2c0_lpcg_ipg_clk";
			power-domains = <0x14 0x60>;
			phandle = <0x3e>;
		};

		clock-controller@5ac10000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5ac10000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x61 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "i2c1_lpcg_clk", "i2c1_lpcg_ipg_clk";
			power-domains = <0x14 0x61>;
			phandle = <0x3f>;
		};

		clock-controller@5ac20000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5ac20000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x62 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "i2c2_lpcg_clk", "i2c2_lpcg_ipg_clk";
			power-domains = <0x14 0x62>;
			phandle = <0x40>;
		};

		clock-controller@5ac30000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5ac30000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x63 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "i2c3_lpcg_clk", "i2c3_lpcg_ipg_clk";
			power-domains = <0x14 0x63>;
			phandle = <0x42>;
		};

		clock-controller@5acd0000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5acd0000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x69 0x2 0x3b 0x3b>;
			bit-offset = <0x0 0x10 0x14>;
			clock-output-names = "can0_lpcg_pe_clk", "can0_lpcg_ipg_clk", "can0_lpcg_chi_clk";
			power-domains = <0x14 0x69>;
			phandle = <0x43>;
		};

		i2c-rpbus-0 {
			compatible = "fsl,i2c-rpbus";
			status = "disabled";
		};

		i2c-rpbus-1 {
			compatible = "fsl,i2c-rpbus";
			status = "disabled";
		};

		i2c-rpbus-5 {
			compatible = "fsl,i2c-rpbus";
			status = "disabled";
		};

		i2c-rpbus-12 {
			compatible = "fsl,i2c-rpbus";
			status = "disabled";
		};

		i2c-rpbus-13 {
			compatible = "fsl,i2c-rpbus";
			status = "disabled";
		};

		i2c-rpbus-14 {
			compatible = "fsl,i2c-rpbus";
			status = "disabled";
		};

		i2c-rpbus-15 {
			compatible = "fsl,i2c-rpbus";
			status = "disabled";
		};

		pwm@5a190000 {
			compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
			reg = <0x5a190000 0x1000>;
			clocks = <0x48 0x0 0x48 0x1>;
			clock-names = "per", "ipg";
			assigned-clocks = <0x3 0xbc 0x2>;
			assigned-clock-rates = <0x16e3600>;
			#pwm-cells = <0x2>;
			power-domains = <0x14 0xbc>;
			status = "disabled";
		};

		clock-controller@5a590000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a590000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xbc 0x2 0x3b>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "adma_pwm_lpcg_clk", "adma_pwm_lpcg_ipg_clk";
			power-domains = <0x14 0xbc>;
			status = "disabled";
			phandle = <0x48>;
		};
	};

	bus@5b000000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;

		clock-conn-axi {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x13de4355>;
			clock-output-names = "conn_axi_clk";
			phandle = <0x5b>;
		};

		clock-conn-ahb {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x9ef21aa>;
			clock-output-names = "conn_ahb_clk";
			phandle = <0x5d>;
		};

		clock-conn-ipg {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x4f790d5>;
			clock-output-names = "conn_ipg_clk";
			phandle = <0x5a>;
		};

		clock-conn-bch {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x17d78400>;
			clock-output-names = "conn_bch_clk";
		};

		usb@5b0d0000 {
			compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb";
			reg = <0x5b0d0000 0x200>;
			interrupt-parent = <0x1>;
			interrupts = <0x0 0xa9 0x4>;
			fsl,usbphy = <0x49>;
			fsl,usbmisc = <0x4a 0x0>;
			clocks = <0x25>;
			ahb-burst-config = <0x0>;
			tx-burst-size-dword = <0x10>;
			rx-burst-size-dword = <0x10>;
			power-domains = <0x14 0x103>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x4b>;
			srp-disable;
			hnp-disable;
			adp-disable;
			power-active-high;
			disable-over-current;
		};

		usbmisc@5b0d0200 {
			#index-cells = <0x1>;
			compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
			reg = <0x5b0d0200 0x200>;
			phandle = <0x4a>;
		};

		usbphy@0x5b100000 {
			compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
			reg = <0x5b100000 0x1000>;
			clocks = <0x4c 0x1>;
			power-domains = <0x14 0x105>;
			status = "okay";
			fsl,tx-d-cal = <0x72>;
			phandle = <0x49>;
		};

		mmc@5b010000 {
			interrupt-parent = <0x1>;
			interrupts = <0x0 0x8a 0x4>;
			reg = <0x5b010000 0x10000>;
			clocks = <0x4d 0x1 0x4d 0x0 0x4d 0x2>;
			clock-names = "ipg", "per", "ahb";
			assigned-clocks = <0x3 0xf8 0x2>;
			assigned-clock-rates = <0x17d78400>;
			power-domains = <0x14 0xf8>;
			fsl,tuning-start-tap = <0x14>;
			fsl,tuning-step = <0x2>;
			status = "okay";
			compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
			pinctrl-names = "default", "state_100mhz", "state_200mhz";
			pinctrl-0 = <0x4e>;
			pinctrl-1 = <0x4f>;
			pinctrl-2 = <0x50>;
			bus-width = <0x8>;
			no-sd;
			no-sdio;
			non-removable;
		};

		mmc@5b020000 {
			interrupt-parent = <0x1>;
			interrupts = <0x0 0x8b 0x4>;
			reg = <0x5b020000 0x10000>;
			clocks = <0x51 0x1 0x51 0x0 0x51 0x2>;
			clock-names = "ipg", "per", "ahb";
			assigned-clocks = <0x3 0xf9 0x2>;
			assigned-clock-rates = <0xbebc200>;
			power-domains = <0x14 0xf9>;
			fsl,tuning-start-tap = <0x14>;
			fsl,tuning-step = <0x2>;
			status = "disabled";
			compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
		};

		mmc@5b030000 {
			interrupt-parent = <0x1>;
			interrupts = <0x0 0x8c 0x4>;
			reg = <0x5b030000 0x10000>;
			clocks = <0x52 0x1 0x52 0x0 0x52 0x2>;
			clock-names = "ipg", "per", "ahb";
			assigned-clocks = <0x3 0xfa 0x2>;
			assigned-clock-rates = <0xbebc200>;
			power-domains = <0x14 0xfa>;
			fsl,tuning-start-tap = <0x14>;
			fsl,tuning-step = <0x2>;
			status = "disabled";
			compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
		};

		ethernet@5b040000 {
			reg = <0x5b040000 0x10000>;
			interrupts = <0x0 0xa0 0x4 0x0 0x9e 0x4 0x0 0x9f 0x4 0x0 0xa1 0x4>;
			clocks = <0x53 0x4 0x53 0x2 0x53 0x3 0x53 0x0 0x53 0x1>;
			clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
			assigned-clocks = <0x3 0xfb 0x19>;
			assigned-clock-rates = <0x7735940>;
			fsl,num-tx-queues = <0x3>;
			fsl,num-rx-queues = <0x3>;
			power-domains = <0x14 0xfb>;
			status = "okay";
			compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec";
			pinctrl-names = "default";
			pinctrl-0 = <0x54>;
			phy-mode = "rgmii-txid";
			phy-handle = <0x55>;
			fsl,magic-packet;
			fsl,rgmii_rxc_dly;
			nvmem-cells = <0x56>;
			nvmem-cell-names = "mac-address";

			mdio {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				ethernet-phy@1 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <0x1>;
					at803x,eee-disabled;
					at803x,vddio-1p8v;
					phandle = <0x55>;
				};
			};
		};

		ethernet@5b050000 {
			reg = <0x5b050000 0x10000>;
			interrupts = <0x0 0xa3 0x4 0x0 0xa2 0x4>;
			clocks = <0x57 0x2 0x57 0x4 0x57 0x0 0x57 0x3 0x57 0x1>;
			clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
			assigned-clocks = <0x3 0xfc 0x2>;
			assigned-clock-rates = <0x7735940>;
			power-domains = <0x14 0xfc>;
			status = "disabled";
			compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
			interrupt-parent = <0x1>;
			interrupt-names = "eth_wake_irq", "macirq";
			clk_csr = <0x0>;
		};

		usb3-phy {
			compatible = "usb-nop-xceiv";
			clocks = <0x58 0x4>;
			clock-names = "main_clk";
			power-domains = <0x14 0x107>;
			status = "disabled";
			phandle = <0x59>;
		};

		usb3@5b110000 {
			compatible = "Cadence,usb3";
			reg = <0x5b110000 0x10000 0x5b130000 0x10000 0x5b140000 0x10000 0x5b160000 0x40000 0x5b120000 0x10000>;
			interrupt-parent = <0x1>;
			interrupts = <0x0 0x10f 0x4>;
			clocks = <0x58 0x1 0x58 0x0 0x58 0x5 0x58 0x2 0x58 0x3>;
			clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", "usb3_ipg_clk", "usb3_core_pclk";
			assigned-clocks = <0x3 0x106 0x2 0x3 0x106 0x4 0x3 0x106 0x1>;
			assigned-clock-rates = <0x7735940 0xb71b00 0xee6b280>;
			power-domains = <0x14 0x106>;
			cdns3,usbphy = <0x59>;
			status = "disabled";
		};

		clock-controller@5b200000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b200000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xf8 0x2 0x5a 0x5b>;
			bit-offset = <0x0 0x10 0x14>;
			clock-output-names = "sdhc0_lpcg_per_clk", "sdhc0_lpcg_ipg_clk", "sdhc0_lpcg_ahb_clk";
			power-domains = <0x14 0xf8>;
			phandle = <0x4d>;
		};

		clock-controller@5b210000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b210000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xf9 0x2 0x5a 0x5b>;
			bit-offset = <0x0 0x10 0x14>;
			clock-output-names = "sdhc1_lpcg_per_clk", "sdhc1_lpcg_ipg_clk", "sdhc1_lpcg_ahb_clk";
			power-domains = <0x14 0xf9>;
			phandle = <0x51>;
		};

		clock-controller@5b220000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b220000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xfa 0x2 0x5a 0x5b>;
			bit-offset = <0x0 0x10 0x14>;
			clock-output-names = "sdhc2_lpcg_per_clk", "sdhc2_lpcg_ipg_clk", "sdhc2_lpcg_ahb_clk";
			power-domains = <0x14 0xfa>;
			phandle = <0x52>;
		};

		clock-controller@5b230000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b230000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x5c 0x5c 0x5b 0x3 0xfb 0x18 0x5a 0x5a>;
			bit-offset = <0x0 0x4 0x8 0xc 0x10 0x14>;
			clock-output-names = "enet0_lpcg_timer_clk", "enet0_lpcg_txc_sampling_clk", "enet0_lpcg_ahb_clk", "enet0_lpcg_rgmii_txc_clk", "enet0_lpcg_ipg_clk", "enet0_lpcg_ipg_s_clk";
			power-domains = <0x14 0xfb>;
			phandle = <0x53>;
		};

		clock-controller@5b240000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b240000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x5c 0x5b 0x5b 0x3 0xfc 0x2 0x5a>;
			bit-offset = <0x0 0x8 0x10 0x14 0x18>;
			clock-output-names = "eqos_ptp", "eqos_mem_clk", "eqos_aclk", "eqos_clk", "eqos_csr_clk";
			power-domains = <0x14 0xfc>;
			phandle = <0x57>;
		};

		clock-controller@5b270000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b270000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x5d 0x5a>;
			bit-offset = <0x18 0x1c>;
			clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
			power-domains = <0x14 0x105>;
			phandle = <0x4c>;
		};

		clock-controller@5b280000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b280000 0x10000>;
			#clock-cells = <0x1>;
			bit-offset = <0x1c>;
			clocks = <0x5a>;
			clock-output-names = "usboh3_2_phy_ipg_clk";
			power-domains = <0x14 0x18>;
			phandle = <0x58>;
		};

		clock-controller@5b290000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b290000 0x4>;
			#clock-cells = <0x1>;
			clocks = <0x3 0x109 0x2 0x3 0x109 0x1 0x5b 0x5b>;
			bit-offset = <0x0 0x4 0x10 0x14>;
			clock-output-names = "bch_clk", "gpmi_clk", "gpmi_apb_clk", "bch_apb_clk";
			power-domains = <0x14 0x109>;
			phandle = <0x5f>;
		};

		clock-controller@5b290004 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5b290004 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x5b>;
			bit-offset = <0x10>;
			clock-output-names = "apbhdma_hclk";
			power-domains = <0x14 0x109>;
			phandle = <0x5e>;
		};

		dma-apbh@5b810000 {
			compatible = "fsl,imx28-dma-apbh";
			reg = <0x5b810000 0x2000>;
			interrupts = <0x0 0xb0 0x4 0x0 0xb0 0x4 0x0 0xb0 0x4 0x0 0xb0 0x4>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <0x1>;
			dma-channels = <0x4>;
			clocks = <0x5e 0x0>;
			clock-names = "apbhdma_hclk";
			power-domains = <0x14 0x109>;
			phandle = <0x60>;
		};

		gpmi-nand@5b812000 {
			compatible = "fsl,imx8qxp-gpmi-nand";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			reg = <0x5b812000 0x2000 0x5b814000 0x2000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <0x0 0xae 0x4>;
			interrupt-names = "bch";
			clocks = <0x5f 0x1 0x5f 0x2 0x5f 0x0 0x5f 0x3>;
			clock-names = "gpmi_clk", "gpmi_apb_clk", "bch_clk", "bch_apb_clk";
			dmas = <0x60 0x0>;
			dma-names = "rx-tx";
			power-domains = <0x14 0x109>;
			assigned-clocks = <0x3 0x109 0x1>;
			assigned-clock-rates = <0x2faf080>;
			status = "disabled";
		};

		clock-conn-enet0-root {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0xee6b280>;
			clock-output-names = "conn_enet0_root_clk";
			phandle = <0x5c>;
		};

		usbphy@0x5b110000 {
			compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
			reg = <0x5b110000 0x1000>;
			clocks = <0x58 0x0>;
			power-domains = <0x14 0x18>;
			status = "disabled";
			phandle = <0x61>;
		};

		usb@5b0e0000 {
			compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb";
			reg = <0x5b0e0000 0x200>;
			interrupt-parent = <0x1>;
			interrupts = <0x0 0xa6 0x4>;
			fsl,usbphy = <0x61>;
			fsl,usbmisc = <0x62 0x0>;
			clocks = <0x25>;
			ahb-burst-config = <0x0>;
			tx-burst-size-dword = <0x10>;
			rx-burst-size-dword = <0x10>;
			#stream-id-cells = <0x1>;
			power-domains = <0x14 0x104>;
			status = "disabled";
		};

		usbmisc@5b0e0200 {
			#index-cells = <0x1>;
			compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
			reg = <0x5b0e0200 0x200>;
			phandle = <0x62>;
		};
	};

	bus@5c000000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;

		ddr-pmu@5c020000 {
			compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
			reg = <0x5c020000 0x10000>;
			interrupt-parent = <0x1>;
			interrupts = <0x0 0x47 0x4>;
		};

		clock-db-ipg {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x1b2e0200>;
			clock-output-names = "db_ipg_clk";
			phandle = <0x64>;
		};

		db-pmu@5ca40000 {
			compatible = "fsl,imx8dxl-db-pmu";
			reg = <0x5ca40000 0x10000>;
			interrupt-parent = <0x1>;
			interrupts = <0x0 0x152 0x4>;
			clocks = <0x63 0x1 0x63 0x0>;
			clock-names = "ipg", "cnt";
			power-domains = <0x14 0x17>;
		};

		clock-controller@5cae0000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5cae0000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x64 0x64>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "perf_lpcg_cnt_clk", "perf_lpcg_ipg_clk";
			power-domains = <0x14 0x17>;
			phandle = <0x63>;
		};
	};

	bus@5d000000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x5d000000 0x0 0x5d000000 0x1000000 0x8000000 0x0 0x8000000 0x10000000>;

		clock-lsio-mem {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0xbebc200>;
			clock-output-names = "lsio_mem_clk";
		};

		clock-lsio-bus {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x5f5e100>;
			clock-output-names = "lsio_bus_clk";
			phandle = <0x65>;
		};

		gpio@5d080000 {
			reg = <0x5d080000 0x10000>;
			interrupts = <0x0 0x4e 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			power-domains = <0x14 0xc7>;
			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
		};

		gpio@5d090000 {
			reg = <0x5d090000 0x10000>;
			interrupts = <0x0 0x4f 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			power-domains = <0x14 0xc8>;
			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
			phandle = <0x72>;
		};

		gpio@5d0a0000 {
			reg = <0x5d0a0000 0x10000>;
			interrupts = <0x0 0x50 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			power-domains = <0x14 0xc9>;
			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
		};

		gpio@5d0b0000 {
			reg = <0x5d0b0000 0x10000>;
			interrupts = <0x0 0x51 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			power-domains = <0x14 0xca>;
			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
		};

		gpio@5d0c0000 {
			reg = <0x5d0c0000 0x10000>;
			interrupts = <0x0 0x52 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			power-domains = <0x14 0xcb>;
			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
			status = "okay";
			phandle = <0x67>;
		};

		gpio@5d0d0000 {
			reg = <0x5d0d0000 0x10000>;
			interrupts = <0x0 0x53 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			power-domains = <0x14 0xcc>;
			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
			status = "okay";
		};

		gpio@5d0e0000 {
			reg = <0x5d0e0000 0x10000>;
			interrupts = <0x0 0x54 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			power-domains = <0x14 0xcd>;
			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
		};

		gpio@5d0f0000 {
			reg = <0x5d0f0000 0x10000>;
			interrupts = <0x0 0x55 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			power-domains = <0x14 0xce>;
			compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
			phandle = <0x33>;
		};

		spi@5d120000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "nxp,imx8dxl-fspi";
			reg = <0x5d120000 0x10000 0x8000000 0x10000000>;
			reg-names = "fspi_base", "fspi_mmap";
			interrupts = <0x0 0x22 0x4>;
			clocks = <0x3 0xed 0x2 0x3 0xed 0x2>;
			clock-names = "fspi", "fspi_en";
			power-domains = <0x14 0xed>;
			status = "disabled";
		};

		mailbox@5d1b0000 {
			reg = <0x5d1b0000 0x10000>;
			interrupts = <0x0 0x56 0x4>;
			#mbox-cells = <0x2>;
			status = "disabled";
			compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
		};

		mailbox@5d1c0000 {
			reg = <0x5d1c0000 0x10000>;
			interrupts = <0x0 0x57 0x4>;
			#mbox-cells = <0x2>;
			compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
			phandle = <0xb>;
		};

		mailbox@5d1d0000 {
			reg = <0x5d1d0000 0x10000>;
			interrupts = <0x0 0x58 0x4>;
			#mbox-cells = <0x2>;
			status = "disabled";
			compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
		};

		mailbox@5d1e0000 {
			reg = <0x5d1e0000 0x10000>;
			interrupts = <0x0 0x59 0x4>;
			#mbox-cells = <0x2>;
			status = "disabled";
			compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
		};

		mailbox@5d1f0000 {
			reg = <0x5d1f0000 0x10000>;
			interrupts = <0x0 0x5a 0x4>;
			#mbox-cells = <0x2>;
			status = "disabled";
			compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
		};

		mailbox@5d200000 {
			compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
			reg = <0x5d200000 0x10000>;
			interrupts = <0x0 0x5b 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0xda>;
			phandle = <0x5>;
		};

		mic_intr@5d230000 {
			compatible = "fsl,imx-mic-intr";
			reg = <0x5d230000 0x10000>;
			interrupts = <0x0 0xbb 0x4>;
			power-domains = <0x14 0xdd 0x14 0xe6>;
			power-domain-names = "pd_a", "pd_b";
			status = "disabled";
		};

		mailbox@5d280000 {
			compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu";
			reg = <0x5d280000 0x10000>;
			interrupts = <0x0 0xc0 0x4>;
			#mbox-cells = <0x2>;
			power-domains = <0x14 0xe2>;
			fsl,dsp_ap_mu_id = <0xd>;
		};

		clock-controller@5d400000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5d400000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xbf 0x2 0x3 0xbf 0x2 0x3 0xbf 0x2 0x65 0x3 0xbf 0x2>;
			bit-offset = <0x0 0x4 0x10 0x14 0x18>;
			clock-output-names = "pwm0_lpcg_ipg_clk", "pwm0_lpcg_ipg_hf_clk", "pwm0_lpcg_ipg_s_clk", "pwm0_lpcg_ipg_slv_clk", "pwm0_lpcg_ipg_mstr_clk";
			power-domains = <0x14 0xbf>;
		};

		clock-controller@5d410000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5d410000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xc0 0x2 0x3 0xc0 0x2 0x3 0xc0 0x2 0x65 0x3 0xc0 0x2>;
			bit-offset = <0x0 0x4 0x10 0x14 0x18>;
			clock-output-names = "pwm1_lpcg_ipg_clk", "pwm1_lpcg_ipg_hf_clk", "pwm1_lpcg_ipg_s_clk", "pwm1_lpcg_ipg_slv_clk", "pwm1_lpcg_ipg_mstr_clk";
			power-domains = <0x14 0xc0>;
		};

		clock-controller@5d420000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5d420000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xc1 0x2 0x3 0xc1 0x2 0x3 0xc1 0x2 0x65 0x3 0xc1 0x2>;
			bit-offset = <0x0 0x4 0x10 0x14 0x18>;
			clock-output-names = "pwm2_lpcg_ipg_clk", "pwm2_lpcg_ipg_hf_clk", "pwm2_lpcg_ipg_s_clk", "pwm2_lpcg_ipg_slv_clk", "pwm2_lpcg_ipg_mstr_clk";
			power-domains = <0x14 0xc1>;
		};

		clock-controller@5d430000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5d430000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xc2 0x2 0x3 0xc2 0x2 0x3 0xc2 0x2 0x65 0x3 0xc2 0x2>;
			bit-offset = <0x0 0x4 0x10 0x14 0x18>;
			clock-output-names = "pwm3_lpcg_ipg_clk", "pwm3_lpcg_ipg_hf_clk", "pwm3_lpcg_ipg_s_clk", "pwm3_lpcg_ipg_slv_clk", "pwm3_lpcg_ipg_mstr_clk";
			power-domains = <0x14 0xc2>;
		};

		clock-controller@5d440000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5d440000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xc3 0x2 0x3 0xc3 0x2 0x3 0xc3 0x2 0x65 0x3 0xc3 0x2>;
			bit-offset = <0x0 0x4 0x10 0x14 0x18>;
			clock-output-names = "pwm4_lpcg_ipg_clk", "pwm4_lpcg_ipg_hf_clk", "pwm4_lpcg_ipg_s_clk", "pwm4_lpcg_ipg_slv_clk", "pwm4_lpcg_ipg_mstr_clk";
			power-domains = <0x14 0xc3>;
		};

		clock-controller@5d450000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5d450000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xc4 0x2 0x3 0xc4 0x2 0x3 0xc4 0x2 0x65 0x3 0xc4 0x2>;
			bit-offset = <0x0 0x4 0x10 0x14 0x18>;
			clock-output-names = "pwm5_lpcg_ipg_clk", "pwm5_lpcg_ipg_hf_clk", "pwm5_lpcg_ipg_s_clk", "pwm5_lpcg_ipg_slv_clk", "pwm5_lpcg_ipg_mstr_clk";
			power-domains = <0x14 0xc4>;
		};

		clock-controller@5d460000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5d460000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xc5 0x2 0x3 0xc5 0x2 0x3 0xc5 0x2 0x65 0x3 0xc5 0x2>;
			bit-offset = <0x0 0x4 0x10 0x14 0x18>;
			clock-output-names = "pwm6_lpcg_ipg_clk", "pwm6_lpcg_ipg_hf_clk", "pwm6_lpcg_ipg_s_clk", "pwm6_lpcg_ipg_slv_clk", "pwm6_lpcg_ipg_mstr_clk";
			power-domains = <0x14 0xc5>;
		};

		clock-controller@5d470000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5d470000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xc6 0x2 0x3 0xc6 0x2 0x3 0xc6 0x2 0x65 0x3 0xc6 0x2>;
			bit-offset = <0x0 0x4 0x10 0x14 0x18>;
			clock-output-names = "pwm7_lpcg_ipg_clk", "pwm7_lpcg_ipg_hf_clk", "pwm7_lpcg_ipg_s_clk", "pwm7_lpcg_ipg_slv_clk", "pwm7_lpcg_ipg_mstr_clk";
			power-domains = <0x14 0xc6>;
		};
	};

	bus@5f000000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
		ranges = <0x5f000000 0x0 0x5f000000 0x21000000>;

		clock-xtal100m {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x5f5e100>;
			clock-output-names = "xtal_100MHz";
			phandle = <0x66>;
		};

		clock-hsio-refa {
			compatible = "gpio-gate-clock";
			clocks = <0x66>;
			#clock-cells = <0x0>;
			enable-gpios = <0x67 0x1b 0x1>;
		};

		clock-hsio-refb {
			compatible = "gpio-gate-clock";
			clocks = <0x66>;
			#clock-cells = <0x0>;
			enable-gpios = <0x67 0x1 0x1>;
			phandle = <0x6f>;
		};

		clock-hsio-axi {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x17d78400>;
			clock-output-names = "hsio_axi_clk";
			phandle = <0x68>;
		};

		clock-hsio-per {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x7f28155>;
			clock-output-names = "hsio_per_clk";
			phandle = <0x69>;
		};

		clock-controller@5f060000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5f060000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x68 0x68 0x68>;
			bit-offset = <0x10 0x14 0x18>;
			clock-output-names = "hsio_pcieb_mstr_axi_clk", "hsio_pcieb_slv_axi_clk", "hsio_pcieb_dbi_axi_clk";
			power-domains = <0x14 0xa9>;
			phandle = <0x6a>;
		};

		clock-controller@5f0b0000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5f0b0000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x69>;
			bit-offset = <0x10>;
			clock-output-names = "hsio_phyx1_per_clk";
			power-domains = <0x14 0xab>;
			phandle = <0x6c>;
		};

		clock-controller@5f0d0000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5f0d0000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x69>;
			bit-offset = <0x10>;
			clock-output-names = "hsio_pcieb_per_clk";
			power-domains = <0x14 0xa9>;
			phandle = <0x6d>;
		};

		clock-controller@5f0f0000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5f0f0000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x69>;
			bit-offset = <0x10>;
			clock-output-names = "hsio_misc_per_clk";
			power-domains = <0x14 0xac>;
			phandle = <0x6e>;
		};

		pcie@0x5f010000 {
			compatible = "fsl,imx8qxp-pcie", "snps,dw-pcie";
			reg = <0x5f010000 0x10000 0x7ff00000 0x80000 0x5f080000 0xf0000>;
			reg-names = "dbi", "config", "hsio";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			device_type = "pci";
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x0 0x7ff80000 0x0 0x10000 0x82000000 0x0 0x70000000 0x70000000 0x0 0xff00000>;
			num-lanes = <0x1>;
			num-viewport = <0x4>;
			interrupts = <0x0 0x2c 0x4 0x0 0x2e 0x4>;
			interrupt-names = "msi", "dma";
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x2f 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x30 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x31 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x32 0x4>;
			clocks = <0x6a 0x0 0x6a 0x1 0x6a 0x2 0x6b 0x0 0x6c 0x0 0x6d 0x0 0x6e 0x0>;
			clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", "pcie_phy", "phy_per", "pcie_per", "misc_per";
			power-domains = <0x14 0xa9 0x14 0xab 0x14 0xac>;
			power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
			fsl,max-link-speed = <0x3>;
			hsio-cfg = <0x3>;
			local-addr = <0x80000000>;
			status = "disabled";
		};

		pcie_ep@0x5f010000 {
			compatible = "fsl,imx8qxp-pcie-ep";
			reg = <0x5f010000 0x10000 0x5f080000 0xf0000 0x70000000 0x10000000>;
			reg-names = "regs", "hsio", "addr_space";
			num-lanes = <0x1>;
			interrupts = <0x0 0x2e 0x4>;
			interrupt-names = "dma";
			clocks = <0x6a 0x0 0x6a 0x1 0x6a 0x2 0x6b 0x0 0x6c 0x0 0x6d 0x0 0x6e 0x0>;
			clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", "pcie_phy", "phy_per", "pcie_per", "misc_per";
			power-domains = <0x14 0xa9 0x14 0xab 0x14 0xac>;
			power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
			fsl,max-link-speed = <0x3>;
			hsio-cfg = <0x3>;
			local-addr = <0x80000000>;
			num-ib-windows = <0x6>;
			num-ob-windows = <0x6>;
			status = "disabled";
		};

		clock-controller@5f090000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5f090000 0x10000>;
			#clock-cells = <0x1>;
			clocks = <0x6f 0x69 0x69 0x69>;
			bit-offset = <0x0 0x4 0x8 0x10>;
			clock-output-names = "hsio_phyx1_pclk", "hsio_phyx1_epcs_tx_clk", "hsio_phyx1_epcs_rx_clk", "hsio_phyx1_apb_clk";
			power-domains = <0x14 0xab>;
			phandle = <0x6b>;
		};
	};

	bus@5a180000 {
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x5a180000 0x0 0x5a180000 0x500000>;

		clock-ipg {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <0x7270e00>;
			clock-output-names = "ipg_dma_clk";
			phandle = <0x70>;
		};

		clock-controller@5a580000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5a580000 0x4>;
			#clock-cells = <0x1>;
			clocks = <0x3 0xbb 0x2 0x70>;
			bit-offset = <0x0 0x10>;
			clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk";
			power-domains = <0x14 0xbb>;
			phandle = <0x71>;
		};

		lcdif@5a180000 {
			compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
			reg = <0x5a180000 0x10000>;
			clocks = <0x71 0x0 0x71 0x1 0x3 0xbb 0x0>;
			clock-names = "pix", "axi", "disp_axi";
			assigned-clocks = <0x3 0xbb 0x2 0x3 0xbb 0x0 0x3 0x143 0x4>;
			assigned-clock-parents = <0x3 0x143 0x4 0x3 0xbb 0x4>;
			assigned-clock-rates = <0x0 0x16e3600 0x2fec1100>;
			interrupts = <0x0 0x3e 0x4>;
			power-domains = <0x14 0xbb>;
			status = "disabled";
		};
	};

	chosen {
		stdout-path = "/bus@5a000000/serial@5a060000";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
	};

	regulator-can0-stby {
		compatible = "regulator-fixed";
		regulator-name = "can0-stby";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		gpio = <0x72 0x13 0x0>;
		enable-active-high;
		phandle = <0x45>;
	};

	regulator-can1-stby {
		compatible = "regulator-fixed";
		regulator-name = "can1-stby";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		gpio = <0x72 0x14 0x0>;
		enable-active-high;
		phandle = <0x47>;
	};

	regulator-adc-vref {
		compatible = "regulator-fixed";
		regulator-name = "vref_1v8";
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x1b7740>;
		phandle = <0x3d>;
	};

	scu-gpio0 {
		compatible = "fsl,imx-scu-gpio";
		gpio-controller;
		#gpio-cells = <0x2>;
		#interrupt-cells = <0x2>;
	};
};