diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index 72319688d7..a464aeef84 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -35,28 +35,6 @@
 		      <0x1 0x00000000 0 0x80000000>;
 	};
 
-	reg_can1_stby: regulator-can1-stby {
-		compatible = "regulator-fixed";
-		regulator-name = "can1-stby";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_flexcan1_reg>;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reg_can2_stby: regulator-can2-stby {
-		compatible = "regulator-fixed";
-		regulator-name = "can2-stby";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_flexcan2_reg>;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -70,115 +48,74 @@
 		off-on-delay-us = <12000>;
 	};
 
-	dsi_host: dsi-host {
-		compatible = "samsung,sec-mipi-dsi";
-		status = "okay";
-	};
+    reg_lvds_panel: regulator-lvds-panel {
+        compatible = "regulator-fixed";
+        regulator-name = "lvds-panel";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        enable-active-high;
+    };
 
-	rm67199_panel {
-		compatible = "raydium,rm67199";
+	backlight: backlight {
+		compatible = "pwm-backlight";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_mipi_dsi_en>;
-		reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
-		dsi-lanes = <4>;
-		video-mode = <2>;	/* 0: burst mode
-					 * 1: non-burst mode with sync event
-					 * 2: non-burst mode with sync pulse
-					 */
-		panel-width-mm = <68>;
-		panel-height-mm = <121>;
+		pinctrl-0 = <&pinctrl_backlight>;
+		pwms = <&pwm2 0 100000>;
+		enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
 		status = "okay";
 
-		port {
-			rm67191_from_dsim: endpoint {
-				remote-endpoint = <&dsim_to_rm67191>;
-			};
-		};
-	};
-
-	cbtl04gp {
-		compatible = "nxp,cbtl04gp";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_typec_mux>;
-		switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
-		orientation-switch;
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <80>;
+	};
+
+	lvds0_panel {
+		compatible = "simple-panel";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lvds_panel>;
+        enable-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;		
+		backlight = <&backlight>;
+		power-supply = <&reg_lvds_panel>;
+		status = "okay";
 
+        display-timings {
+            native-mode = <&timing0>;
+
+            timing0: timing0 {
+                clock-frequency = <74250000>;
+                hactive = <1280>;
+                vactive = <800>;
+                hfront-porch = <64>;
+                hback-porch = <48>;
+                hsync-len = <48>;
+                vback-porch = <11>;
+                vfront-porch = <8>;
+                vsync-len = <5>;
+				de-active = <0>;
+            };
+        };
+		
 		port {
-			usb3_data_ss: endpoint {
-				remote-endpoint = <&typec_con_ss>;
+			panel_lvds_in: endpoint {
+				remote-endpoint = <&lvds_out>;
 			};
 		};
-	};
-};
-
-&eqos {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_eqos>;
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy0>;
-	status = "okay";
-
-	mdio {
-		compatible = "snps,dwmac-mdio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-			eee-broken-1000t;
-		};
-	};
+	};	
 };
 
-&flexcan1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	xceiver-supply = <&reg_can1_stby>;
-	status = "okay";
-};
-
-&flexcan2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan2>;
-	xceiver-supply = <&reg_can2_stby>;
-	status = "disabled";/* can2 pin conflict with pdm */
-};
-
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec>;
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy1>;
-	fsl,magic-packet;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy1: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-			eee-broken-1000t;
-		};
-	};
-};
-
-&flexspi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexspi0>;
-	status = "okay";
-
-	flash0: mt25qu256aba@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <80000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-	};
+&pwm2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm2>;
+    status = "okay";
 };
 
 &i2c1 {
@@ -298,105 +235,33 @@
 	};
 };
 
-&i2c2 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default", "gpio";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	pinctrl-1 = <&pinctrl_i2c2_gpio>;
-	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-
-	adv_bridge: adv7535@3d {
-		compatible = "adi,adv7533";
-		reg = <0x3d>;
-		adi,addr-cec = <0x3c>;
-		adi,dsi-lanes = <4>;
-		status = "okay";
-
-		port {
-			adv7535_from_dsim: endpoint {
-				remote-endpoint = <&dsim_to_adv7535>;
-			};
-		};
-	};
-
-	ptn5110: tcpc@50 {
-		compatible = "nxp,ptn5110";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_typec>;
-		reg = <0x50>;
-		interrupt-parent = <&gpio4>;
-		interrupts = <19 8>;
-
-		port {
-			typec_dr_sw: endpoint {
-				remote-endpoint = <&usb3_drd_sw>;
-			};
-		};
-
-		usb_con: connector {
-			compatible = "usb-c-connector";
-			label = "USB-C";
-			power-role = "dual";
-			data-role = "dual";
-			try-power-role = "sink";
-			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
-				     PDO_VAR(5000, 20000, 3000)>;
-			op-sink-microwatt = <15000000>;
-			self-powered;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					typec_con_ss: endpoint {
-						remote-endpoint = <&usb3_data_ss>;
-					};
-				};
-			};
-		};
-	};
+&lcdif2 {
+    status = "okay";
 };
 
-&i2c3 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default", "gpio";
-	pinctrl-0 = <&pinctrl_i2c3>;
-	pinctrl-1 = <&pinctrl_i2c3_gpio>;
-	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+&ldb_phy {
 	status = "okay";
-
-	pca6416: gpio@20 {
-		compatible = "ti,tca6416";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
 };
 
-&lcdif1 {
-	status = "okay";
-};
+&ldb {
+ 	status = "okay";
 
-&mipi_dsi {
-	status = "okay";
+	lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+		status = "okay";
 
-	port@1 {
-		dsim_to_adv7535: endpoint {
-			remote-endpoint = <&adv7535_from_dsim>;
-		};
+		port@1 {
+			reg = <1>;
+			lvds_out: endpoint {
+				remote-endpoint = <&panel_lvds_in>;
+			};
+ 		};		
 	};
+};
 
-	port@2 {
-		dsim_to_rm67191: endpoint {
-			remote-endpoint = <&rm67191_from_dsim>;
-		};
-	};
+&mipi_dsi {
+	status = "disabled";
 };
 
 &snvs_pwrkey {
@@ -411,13 +276,6 @@
 };
 
 &usb3_phy0 {
-	vbus-power-supply = <&ptn5110>;
-	fsl,phy-tx-vref-tune = <0xe>;
-	fsl,phy-tx-preemp-amp-tune = <3>;
-	fsl,phy-tx-vboost-level = <5>;
-	fsl,phy-comp-dis-tune = <7>;
-	fsl,pcs-tx-deemph-3p5db = <0x21>;
-	fsl,phy-pcs-tx-swing-full = <0x7f>;
 	status = "okay";
 };
 
@@ -433,12 +291,6 @@
 	usb-role-switch;
 	role-switch-default-mode = "none";
 	status = "okay";
-
-	port {
-		usb3_drd_sw: endpoint {
-			remote-endpoint = <&typec_dr_sw>;
-		};
-	};
 };
 
 &usb3_phy1 {
@@ -489,80 +341,6 @@
 &iomuxc {
 	pinctrl-names = "default";
 
-	pinctrl_eqos: eqosgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC	0x3
-			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO	0x3
-			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
-			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
-			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
-			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
-			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
-			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
-			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f
-			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f
-			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f
-			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f
-			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
-			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
-			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x19
-		>;
-	};
-
-	pinctrl_fec: fecgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
-			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
-			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
-			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
-			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
-			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
-			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
-			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
-			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
-			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
-			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
-			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
-		>;
-	};
-
-	pinctrl_flexcan1: flexcan1grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
-			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
-			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
-		>;
-	};
-
-	pinctrl_flexcan1_reg: flexcan1reggrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
-		>;
-	};
-
-	pinctrl_flexcan2_reg: flexcan2reggrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
-		>;
-	};
-
-	pinctrl_flexspi0: flexspi0grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
-			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
-			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
-			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
-			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
-			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
-		>;
-	};
-
     pinctrl_gpio_led: gpioledgrp {
         fsl,pins = <
             MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10  0x19
@@ -576,20 +354,6 @@
 		>;
 	};
 
-	pinctrl_i2c2: i2c2grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
-			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
-		>;
-	};
-
-	pinctrl_i2c3: i2c3grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
-			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
-		>;
-	};
-
 	pinctrl_i2c1_gpio: i2c1grp-gpio {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14        	0x1c3
@@ -597,38 +361,12 @@
 		>;
 	};
 
-	pinctrl_i2c2_gpio: i2c2grp-gpio {
-		fsl,pins = <
-			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16        	0x1c3
-			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17        	0x1c3
-		>;
-	};
-
-	pinctrl_i2c3_gpio: i2c3grp-gpio {
-		fsl,pins = <
-			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18        	0x1c3
-			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19        	0x1c3
-		>;
-	};
-
-	pinctrl_mipi_dsi_en: mipi_dsi_en {
-		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08	0x16
-		>;
-	};
-
 	pinctrl_pmic: pmicirq {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41
 		>;
 	};
 
-	pinctrl_typec: typec1grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x1c4
-		>;
-	};
-
 	pinctrl_typec_mux: typec1muxgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x16
@@ -749,4 +487,22 @@
 			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
 		>;
 	};
-};
+
+	pinctrl_pwm2: pwm2grp {
+        fsl,pins = <
+            MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT   0x116
+        >;
+	};
+
+	pinctrl_backlight: backlight {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08	0x16
+		>;
+	};
+
+	pinctrl_lvds_panel: lvds-panel {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11	0x16
+		>;
+	};
+};	
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 9a58bb376e..9016ce27bc 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -41,7 +41,7 @@
 		usb0 = &usb_dwc3_0;
 		usb1 = &usb_dwc3_1;
 		spi0 = &flexspi;
-		video0 = &lcdif1;
+		video0 = &lcdif2;
 	};
 
 	cpus {
@@ -351,6 +351,14 @@
 			domain-name = "hdmi_phy";
 			parent-domains = <&hdmimix_pd>;
 		};
+
+		lvds_phy_pd: lvdsphy-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <19>;
+			domain-name = "lvds_phy";
+			parent-domains = <&mediamix_pd>;
+		};					 
 	};
 
 	pmu {
@@ -1143,6 +1151,114 @@
 				};
 			};
 
+			lcdif2: lcd-controller@32e90000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mp-lcdif2";
+				reg = <0x32e90000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+				clock-names = "pix", "disp-axi", "disp-apb";
+				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+						  <&clk IMX8MP_CLK_MEDIA_AXI>,
+						  <&clk IMX8MP_CLK_MEDIA_APB>;
+				assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MP_SYS_PLL2_1000M>,
+							 <&clk IMX8MP_SYS_PLL1_800M>;
+				assigned-clock-rates = <0>, <500000000>, <200000000>;
+				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				blk-ctl = <&mediamix_blk_ctl>;
+				power-domains = <&mediamix_pd>;
+				status = "disabled";
+
+				lcdif2_disp: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					lcdif2_disp_ldb_ch0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&ldb_ch0>;
+					};
+
+					lcdif2_disp_ldb_ch1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&ldb_ch1>;
+					};
+
+				};
+			};
+
+			ldb: ldb@32ec005c {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mp-ldb";
+				clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>;
+				clock-names = "ldb";
+				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
+				assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+				gpr = <&mediamix_blk_ctl>;
+				power-domains = <&mediamix_pd>;
+				status = "disabled";
+
+				lvds-channel@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					phys = <&ldb_phy1>;
+					phy-names = "ldb_phy";
+					status = "disabled";
+
+					port@0 {
+						reg = <0>;
+
+						ldb_ch0: endpoint {
+							remote-endpoint = <&lcdif2_disp_ldb_ch0>;
+						};
+					};
+				};
+
+				lvds-channel@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					phys = <&ldb_phy2>;
+					phy-names = "ldb_phy";
+					status = "disabled";
+
+					port@0 {
+						reg = <0>;
+
+						ldb_ch1: endpoint {
+							remote-endpoint = <&lcdif2_disp_ldb_ch1>;
+						};
+					};
+				};
+
+			};
+
+			ldb_phy: phy@32ec0128 {
+				compatible = "fsl,imx8mp-lvds-phy";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				gpr = <&mediamix_blk_ctl>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+				clock-names = "apb";
+				power-domains = <&mediamix_pd>;
+				status = "disabled";
+
+				ldb_phy1: port@0 {
+					reg = <0>;
+					#phy-cells = <0>;
+				};
+
+				ldb_phy2: port@1 {
+					reg = <1>;
+					#phy-cells = <0>;
+				};
+			};
+
 			mediamix_blk_ctl: blk-ctl@32ec0000 {
 				compatible = "fsl,imx8mp-mediamix-blk-ctl",
 					     "syscon";
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index a97498c162..e96ab5abad 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -48,7 +48,9 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 
 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
+    PLL_1443X_RATE(1039500000U, 693, 4, 2, 0),	
 	PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
+	PLL_1443X_RATE(995400000U, 207, 5, 0, 24576),
 	PLL_1443X_RATE(800000000U, 200, 3, 1, 0),
 	PLL_1443X_RATE(750000000U, 250, 2, 2, 0),
 	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
@@ -279,7 +281,7 @@ int intpll_configure(enum pll_clocks pll, ulong freq)
 	return 0;
 }
 
-#define VIDEO_PLL_RATE 594000000U
+#define VIDEO_PLL_RATE 995400000U
 
 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
 {
@@ -303,11 +305,9 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
 	return;
 
 find:
-	/* Select to video PLL */
-	debug("mxs_set_lcdclk, pre = %d, post = %d\n", pre, post);
-
+	/* Select to video PLL, pre should be 14 when use 74.25MHz */
 #ifdef CONFIG_IMX8MP
-	clock_set_target_val(MEDIA_DISP1_PIX_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1));
+	clock_set_target_val(MEDIA_DISP2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1));
 #elif defined(CONFIG_IMX8MN)
 	clock_set_target_val(DISPLAY_PIXEL_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1));
 #else
@@ -322,17 +322,18 @@ void enable_display_clk(unsigned char enable)
 	if (enable) {
 		clock_enable(CCGR_DISPMIX, false);
 
-		/* Set Video PLL to 594Mhz, p = 1, m = 99,  k = 0, s = 2 */
+		/* Set Video PLL to 995.4Mhz for LVDS, p = 5, m = 207,  k = 24576, s = 0 */
 		fracpll_configure(ANATOP_VIDEO_PLL, VIDEO_PLL_RATE);
 
-		/* 400Mhz */
-		clock_set_target_val(MEDIA_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2));
+		/* 500Mhz */
+		clock_set_target_val(MEDIA_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2));		
 
 		/* 200Mhz */
 		clock_set_target_val(MEDIA_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
 
-		/* 27Mhz MIPI DPHY PLL ref from video PLL */
-		clock_set_target_val(MEDIA_MIPI_PHY1_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22));
+		/* 497.7Mhz LVDS PLL ref from video PLL */
+		clock_set_target_val(MEDIA_LDB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+
 		clock_enable(CCGR_DISPMIX, true);
 	} else {
 		clock_enable(CCGR_DISPMIX, false);
@@ -368,6 +369,17 @@ void enable_display_clk(unsigned char enable)
 }
 #endif
 
+u32 get_dsi_phy_ref_clk(void)
+{
+#ifdef CONFIG_IMX8MP
+	return get_root_clk(MEDIA_LDB_CLK_ROOT);
+#elif defined(CONFIG_IMX8MN)
+	return get_root_clk(DISPLAY_DSI_PHY_REF_CLK_ROOT);
+#else
+	return get_root_clk(MIPI_DSI_PHY_REF_CLK_ROOT);
+#endif
+}
+
 void init_uart_clk(u32 index)
 {
 	/*
diff --git a/configs/imx8mp_evk_android_defconfig b/configs/imx8mp_evk_android_defconfig
index ecbcbac4ff..f04c34ba46 100644
--- a/configs/imx8mp_evk_android_defconfig
+++ b/configs/imx8mp_evk_android_defconfig
@@ -132,6 +132,8 @@ CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
@@ -159,10 +161,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_VIDEO_IMX_LCDIFV3=y
-CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX8MP_LVDS=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
-CONFIG_VIDEO_ADV7535=y
+CONFIG_BACKLIGHT=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/configs/imx8mp_evk_android_dual_defconfig b/configs/imx8mp_evk_android_dual_defconfig
index 2f9d5f4558..c4faf03690 100644
--- a/configs/imx8mp_evk_android_dual_defconfig
+++ b/configs/imx8mp_evk_android_dual_defconfig
@@ -132,6 +132,8 @@ CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
@@ -158,10 +160,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_VIDEO_IMX_LCDIFV3=y
-CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX8MP_LVDS=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
-CONFIG_VIDEO_ADV7535=y
+CONFIG_BACKLIGHT=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/configs/imx8mp_evk_android_powersave_defconfig b/configs/imx8mp_evk_android_powersave_defconfig
index a492ee410b..96072774c2 100644
--- a/configs/imx8mp_evk_android_powersave_defconfig
+++ b/configs/imx8mp_evk_android_powersave_defconfig
@@ -132,6 +132,8 @@ CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
@@ -159,10 +161,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_VIDEO_IMX_LCDIFV3=y
-CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX8MP_LVDS=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
-CONFIG_VIDEO_ADV7535=y
+CONFIG_BACKLIGHT=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/configs/imx8mp_evk_android_trusty_defconfig b/configs/imx8mp_evk_android_trusty_defconfig
index 945037cb67..b734353d67 100644
--- a/configs/imx8mp_evk_android_trusty_defconfig
+++ b/configs/imx8mp_evk_android_trusty_defconfig
@@ -132,6 +132,8 @@ CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
@@ -159,10 +161,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_VIDEO_IMX_LCDIFV3=y
-CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX8MP_LVDS=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
-CONFIG_VIDEO_ADV7535=y
+CONFIG_BACKLIGHT=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/configs/imx8mp_evk_android_trusty_dual_defconfig b/configs/imx8mp_evk_android_trusty_dual_defconfig
index 03fcfcf6f6..46532ab302 100644
--- a/configs/imx8mp_evk_android_trusty_dual_defconfig
+++ b/configs/imx8mp_evk_android_trusty_dual_defconfig
@@ -132,6 +132,8 @@ CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
@@ -159,10 +161,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_VIDEO_IMX_LCDIFV3=y
-CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX8MP_LVDS=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
-CONFIG_VIDEO_ADV7535=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/configs/imx8mp_evk_android_trusty_powersave_defconfig b/configs/imx8mp_evk_android_trusty_powersave_defconfig
index 24932c2ac6..31caf88d2b 100644
--- a/configs/imx8mp_evk_android_trusty_powersave_defconfig
+++ b/configs/imx8mp_evk_android_trusty_powersave_defconfig
@@ -132,6 +132,8 @@ CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
@@ -159,10 +161,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_VIDEO_IMX_LCDIFV3=y
-CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX8MP_LVDS=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
-CONFIG_VIDEO_ADV7535=y
+CONFIG_BACKLIGHT=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig
index 2a201a2749..96cbe75934 100644
--- a/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig
+++ b/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig
@@ -132,6 +132,8 @@ CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
@@ -159,10 +161,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_VIDEO_IMX_LCDIFV3=y
-CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX8MP_LVDS=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
-CONFIG_VIDEO_ADV7535=y
+CONFIG_BACKLIGHT=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/configs/imx8mp_evk_android_uuu_defconfig b/configs/imx8mp_evk_android_uuu_defconfig
index 8795b6c422..e940352e06 100644
--- a/configs/imx8mp_evk_android_uuu_defconfig
+++ b/configs/imx8mp_evk_android_uuu_defconfig
@@ -133,6 +133,8 @@ CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
@@ -160,10 +162,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_VIDEO_IMX_LCDIFV3=y
-CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX8MP_LVDS=y
 CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
-CONFIG_VIDEO_ADV7535=y
+CONFIG_BACKLIGHT=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index bce439a443..7f4de2a79d 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -43,10 +43,25 @@ static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = {
 	PLL_1416X_RATE(600000000U,  300, 3, 2),
 };
 
+static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
+    PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
+    PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
+    PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
+    PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
+    PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+    PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
 static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = {
 	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
 };
 
+struct imx_pll14xx_clk imx_1443x_pll = {
+		.type = PLL_1443X,
+		.rate_table = imx_pll1443x_tbl,
+		.rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
+};
+
 static struct imx_pll14xx_clk imx8mp_dram_pll __initdata = {
 		.type = PLL_1443X,
 		.rate_table = imx8mp_drampll_tbl,
@@ -65,6 +80,7 @@ static struct imx_pll14xx_clk imx8mp_sys_pll __initdata = {
 		.rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
 };
 
+static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
@@ -198,6 +214,23 @@ static const char *imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m"
 
 static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
 
+static const char * const imx8mp_media_axi_sels[] = {"clock-osc-24m", "sys_pll2_1000m", "sys_pll1_800m",
+                             "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
+                             "clk_ext1", "sys_pll2_500m", };
+
+static const char * const imx8mp_media_apb_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll1_800m",
+                             "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
+                             "clk_ext1", "sys_pll1_133m", };
+
+static const char * const imx8mp_media_disp2_pix_sels[] = {"clock-osc-24m", "video_pll1_out", "audio_pll2_out",
+                               "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
+                               "sys_pll3_out", "clk_ext4", };
+
+static const char * const imx8mp_media_ldb_sels[] = {"clokc-osc-24m", "sys_pll2_333m", "sys_pll2_100m",
+                             "sys_pll1_800m", "sys_pll2_1000m",
+                             "clk_ext2", "audio_pll2_out",
+                             "video_pll1_out", };
+
 
 static ulong imx8mp_clk_get_rate(struct clk *clk)
 {
@@ -292,24 +325,28 @@ static int imx8mp_clk_probe(struct udevice *dev)
 
 	base = (void *)ANATOP_BASE_ADDR;
 
+	clk_dm(IMX8MP_VIDEO_PLL1_REF_SEL, imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
+	clk_dm(IMX8MP_VIDEO_PLL1, imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll));
 	clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll));
 	clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll));
 	clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll));
 	clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll));
 	clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll));
 
+    clk_dm(IMX8MP_VIDEO_PLL1_BYPASS, imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
 
+	clk_dm(IMX8MP_VIDEO_PLL1_OUT, imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13));
 	clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
 	clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
 	clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
@@ -344,6 +381,11 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 	clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
 
+    clk_dm(IMX8MP_CLK_MEDIA_LDB, imx8m_clk_composite("media_ldb", imx8mp_media_ldb_sels, base + 0xbf00));
+    clk_dm(IMX8MP_CLK_MEDIA_AXI, imx8m_clk_composite("media_axi", imx8mp_media_axi_sels, base + 0x8a00));
+    clk_dm(IMX8MP_CLK_MEDIA_APB, imx8m_clk_composite("media_apb", imx8mp_media_apb_sels, base + 0x8a80));
+    clk_dm(IMX8MP_CLK_MEDIA_DISP2_PIX, imx8m_clk_composite("media_disp2_pix", imx8mp_media_disp2_pix_sels, base + 0x9300));
+
 	clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
 
 	clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c
index 823a9d2d6b..b52cb6a32a 100644
--- a/drivers/pwm/pwm-imx-util.c
+++ b/drivers/pwm/pwm-imx-util.c
@@ -14,6 +14,8 @@
 #include <div64.h>
 #include <asm/arch/imx-regs.h>
 
+#define CONFIG_IMX6_PWM_PER_CLK	66000000
+
 /* pwm_id from 0..7 */
 struct pwm_regs *pwm_id_to_reg(int pwm_id)
 {
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2008c1520e..f3201dd966 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -15,6 +15,23 @@
 #include <asm/io.h>
 #include "pwm-imx-util.h"
 
+#define PWMCR_PRESCALER(x)  (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN        (1 << 24)
+#define PWMCR_WAITEN        (1 << 23)
+#define PWMCR_DBGEN     (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH   (2 << 16)
+#define PWMCR_CLKSRC_IPG    (1 << 16)
+#define PWMCR_EN        (1 << 0)
+
+struct pwm_regs {
+    u32 cr;
+    u32 sr;
+    u32 ir;
+    u32 sar;
+    u32 pr;
+    u32 cnr;
+};
+
 int pwm_init(int pwm_id, int div, int invert)
 {
 	struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
diff --git a/drivers/video/nxp/imx/Kconfig b/drivers/video/nxp/imx/Kconfig
index f201c4a87c..ae75bdd331 100644
--- a/drivers/video/nxp/imx/Kconfig
+++ b/drivers/video/nxp/imx/Kconfig
@@ -23,6 +23,15 @@ config VIDEO_IMX8_LVDS
 	help
 	  Support for i.MX8 LDVS bridge controller for i.MX8 processors.
 
+config VIDEO_IMX8MP_LVDS
+	bool "i.MX8MP LDVS bridge support"
+	default n
+	depends on IMX8MP && DM_VIDEO
+	select DISPLAY
+	select VIDEO_LINK
+	help
+	  Support for i.MX8MP LDVS bridge controller for i.MX8 processors.
+
 config VIDEO_IMX_HDP_LOAD
 	bool "i.MX8 HDMI/DP firmware loading"
 	default n
diff --git a/drivers/video/nxp/imx/Makefile b/drivers/video/nxp/imx/Makefile
index ae2a847a89..12f0fcf896 100644
--- a/drivers/video/nxp/imx/Makefile
+++ b/drivers/video/nxp/imx/Makefile
@@ -6,6 +6,7 @@
 obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
 obj-$(CONFIG_VIDEO_IMXDPUV1) += imxdpuv1.o imx8_dc.o
 obj-$(CONFIG_VIDEO_IMX8_LVDS) += imx8_lvds.o
+obj-$(CONFIG_VIDEO_IMX8MP_LVDS) += imx8mp_lvds.o
 obj-$(CONFIG_VIDEO_IMX8M_DCSS) += imx8m_dcss.o
 obj-$(CONFIG_VIDEO_SEC_MIPI_DSI) += sec_mipi_dsim.o
 obj-$(CONFIG_VIDEO_IMX_SEC_DSI) += sec_dsim_imx.o
diff --git a/drivers/video/nxp/imx/imx_lcdifv3.c b/drivers/video/nxp/imx/imx_lcdifv3.c
index 1eb9938777..2f8c1fe37c 100644
--- a/drivers/video/nxp/imx/imx_lcdifv3.c
+++ b/drivers/video/nxp/imx/imx_lcdifv3.c
@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <malloc.h>
+#include <display.h>
 #include <video.h>
 #include <video_fb.h>
 #include <video_bridge.h>
@@ -101,11 +102,6 @@ static void lcdifv3_set_mode(struct lcdifv3_priv *priv,
 	/* Polarities */
 	writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
 	writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
-
-	/* SEC MIPI DSI specific */
-	writel(CTRL_INV_PXCK, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
-	writel(CTRL_INV_DE, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
-
 }
 
 static void lcdifv3_set_bus_fmt(struct lcdifv3_priv *priv)
@@ -113,15 +109,18 @@ static void lcdifv3_set_bus_fmt(struct lcdifv3_priv *priv)
 	uint32_t disp_para = 0;
 
 	disp_para = readl((ulong)(priv->reg_base + LCDIFV3_DISP_PARA));
-	disp_para &= DISP_PARA_LINE_PATTERN(0xf);
 
+    /* clear line pattern bits */
+    disp_para &= ~DISP_PARA_LINE_PATTERN(0xf);
+	
 	/* Fixed to 24 bits output */
 	disp_para |= DISP_PARA_LINE_PATTERN(LP_RGB888_OR_YUV444);
 
 	/* config display mode: default is normal mode */
-	disp_para &= DISP_PARA_DISP_MODE(3);
+	disp_para &= ~DISP_PARA_DISP_MODE(3);
 	disp_para |= DISP_PARA_DISP_MODE(0);
 	writel(disp_para, (ulong)(priv->reg_base + LCDIFV3_DISP_PARA));
+
 }
 
 static void lcdifv3_enable_plane_panic(struct lcdifv3_priv *priv)
@@ -174,6 +173,7 @@ static void lcdifv3_enable_controller(struct lcdifv3_priv *priv)
 	/* enable layer dma */
 	ctrldescl0_5 |= CTRLDESCL0_5_EN;
 	writel(ctrldescl0_5, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5));
+
 }
 
 static void lcdifv3_disable_controller(struct lcdifv3_priv *priv)
@@ -224,6 +224,7 @@ static void lcdifv3_init(struct udevice *dev,
 		(ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_3));
 
 	lcdifv3_enable_controller(priv);
+
 }
 
 void lcdifv3_power_down(struct lcdifv3_priv *priv)
@@ -254,7 +255,6 @@ static int lcdifv3_of_get_timings(struct udevice *dev,
 		(device_get_uclass_id(priv->disp_dev) != UCLASS_VIDEO_BRIDGE
 		&& device_get_uclass_id(priv->disp_dev) != UCLASS_DISPLAY)) {
 
-		printf("fail to find output device\n");
 		return -ENODEV;
 	}
 
@@ -262,7 +262,6 @@ static int lcdifv3_of_get_timings(struct udevice *dev,
 
 	ret = video_link_get_display_timings(timings);
 	if (ret) {
-		printf("fail to get display timings\n");
 		return ret;
 	}
 
@@ -316,7 +315,6 @@ static void lcdifv3_of_parse_thres(struct udevice *dev)
 	}
 }
 
-
 static int lcdifv3_video_probe(struct udevice *dev)
 {
 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
@@ -345,21 +343,11 @@ static int lcdifv3_video_probe(struct udevice *dev)
 	lcdifv3_of_parse_thres(dev);
 
 	if (priv->disp_dev) {
-#if IS_ENABLED(CONFIG_VIDEO_BRIDGE)
-		if (device_get_uclass_id(priv->disp_dev) == UCLASS_VIDEO_BRIDGE) {
-			ret = video_bridge_attach(priv->disp_dev);
-			if (ret) {
-				dev_err(dev, "fail to attach bridge\n");
-				return ret;
-			}
-
-			ret = video_bridge_set_backlight(priv->disp_dev, 80);
-			if (ret) {
-				dev_err(dev, "fail to set backlight\n");
-				return ret;
-			}
+		ret = display_enable(priv->disp_dev, 0, NULL);
+		if (ret) {
+			debug("%s: Display enable error %d\n", __func__, ret);
+			return ret;		
 		}
-#endif
 	}
 
 	mode.xres = timings.hactive.typ;
@@ -385,6 +373,8 @@ static int lcdifv3_video_probe(struct udevice *dev)
 	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 					DCACHE_WRITEBACK);
 	video_set_flush_dcache(dev, true);
+
+	//set framebuffer address in uboot
 	gd->fb_base = plat->base;
 
 	return ret;
@@ -416,6 +406,7 @@ static int lcdifv3_video_remove(struct udevice *dev)
 
 static const struct udevice_id lcdifv3_video_ids[] = {
 	{ .compatible = "fsl,imx8mp-lcdif1" },
+	{ .compatible = "fsl,imx8mp-lcdif2" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index 9e32bc47cf..1bc91179e7 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -177,6 +177,10 @@ static int pwm_backlight_set_brightness(struct udevice *dev, int percent)
 				return log_ret(ret);
 		}
 		priv->enabled = false;
+	} else {
+		ret = pwm_set_enable(priv->pwm, priv->channel, true);
+		if (ret)
+			return log_ret(ret);
 	}
 
 	return 0;
