&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
   fsl,dte-mode;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	assigned-clocks = <&clk IMX8MP_CLK_UART4>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	status = "okay";
};

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
	status = "okay";

   can@0 {
      compatible = "microchip,mcp2518fd";
		clocks = <&clk20m>;
      reg = <0>;
      spi-max-frequency = <12000000>;            // 12 MHz
      interrupt-parent = <&gpio1>;//interrupt on port 1
      interrupts = <0 IRQ_TYPE_EDGE_FALLING>;//port 1-0
   };

};

   clk20m: oscillator {
      compatible = "fixed-clock";
      #clock-cells = <0>;
      clock-frequency = <20000000>;
   };

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
	status = "okay";

   can@0 {
      compatible = "microchip,mcp2518fd";
		clocks = <&clk20m>;
      reg = <0>;
      spi-max-frequency = <12000000>;            // 12 MHz
      interrupt-parent = <&gpio1>;//interrupt on port 1
      interrupts = <1 IRQ_TYPE_EDGE_FALLING>;//port 1-1
   };
};

&ecspi3 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
	cs-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>,
              <&gpio5 25 GPIO_ACTIVE_LOW>;
	status = "okay";

   ism330dlc@0 {
      compatible = "st,ism330dlc";
      reg = <0>;
      spi-max-frequency = <10000000>;            // Max 10 MHz
      interrupt-parent = <&gpio1>;//interrupt on port 1
      interrupts = <4 IRQ_TYPE_EDGE_FALLING>;//port 1-4
   };
	slb9670@1 {
      compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
      reg = <1>;
      spi-max-frequency = <12000000>;            // 12 MHz
	};

};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
         MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX        0x00000144
         MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS      0x00000104
         MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX       0x00000144
         MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS      0x00000104
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
         MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS       0x00000144
         MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS       0x00000104
         MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX        0x00000144
         MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX       0x00000144
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
         MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX       0x00000144
         MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX       0x00000144
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
         MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX       0x00000144
         MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX       0x00000144
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO      0x00000146
			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI      0x00000146
			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK      0x00000146
		>;
	};

	pinctrl_ecspi1_cs: ecspi1cs {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0        0x00000106
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO      0x00000146
			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI      0x00000146
			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK      0x00000146
		>;
	};

	pinctrl_ecspi2_cs: ecspi2cs {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0        0x00000106
		>;
	};

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO      0x00000146
			MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI      0x00000146
			MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK      0x00000146
		>;
	};

	pinctrl_ecspi3_cs: ecspi3cs {
		fsl,pins = <
         MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01         0x00000144
         MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25        0x00000152
		>;
	};