# Version 6 # Note, though the extension of this file implies use with the DS5 debugger, # the file is meant specifically for the DDR Stress Test GUI tool. # It contains data commands which are not compatible with the DS5 debugger, # trying to use this file with DS5 will result in errors. # There are currently no plans to create a DS5 JTAG DRAM initialization script. # # DCD command: # CMD_WRITE_DATA: memory set ADDR BITWIDTH VALUE : *ADDR = VALUE # CMD_SET_BIT: memory setbit ADDR BITWIDTH VALUE : *ADDR = *ADDR | VALUE # CMD_CLR_BIT: memory clrbit ADDR BITWIDTH VALUE : *ADDR = *ADDR &~ VALUE # CMD_CHECK_BIT_SET: memory chkbit1 ADDR BITWIDTH VALUE : while((*ADDR & VALUE) != VALUE){} # CMD_CHECK_BIT_CLR: memory chkbit0 ADDR BITWIDTH VALUE : while((*ADDR & VALUE) != 0){} ########################################################################################################### ################step 0: configure debug uart port. Assumes use of UART IO Pads. ##### ##### If using non-UART pads (i.e. using other pads to mux out the UART signals), ##### ##### then it is up to the user to overwrite the following IO register settings ##### memory set 0x3033023C 32 0x00000000 #IOMUXC_SW_MUX_UART2_RXD memory set 0x30330240 32 0x00000000 #IOMUXC_SW_MUX_UART2_TXD memory set 0x303304A4 32 0x0000000E #IOMUXC_SW_PAD_UART2_RXD memory set 0x303304A8 32 0x0000000E #IOMUXC_SW_PAD_UART2_TXD memory set 0x303304FC 32 0x00000000 #IOMUXC_SW_MUX_UART2_SEL_RXD sysparam set debug_uart 1 #UART index from 0 ('0' = UART1, '1' = UART2, '2' = UART3, '3' = UART4) sysparam set fw_version 1 #Firmware Selection: '0' for FW201709, '1' for FW201810 ################step 1: DDR clock configuration################ memory set 0x30391000 32 0x8F00003F #SRC_DDRC_RCR_ADDR: assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! memory set 0x30391000 32 0x8F00000F #SRC_DDRC_RCR_ADDR: deassert [4]src_system_rst_b! memory set 0x3038A088 32 0x07070000 #DRAM_APB_CLK_ROOT_CLR memory set 0x3038A084 32 0x04030000 #DRAM_APB_CLK_ROOT_SET, dram_apb_clk_root set to source 4 --800MHz/4 #disable the clock gating memory set 0x303A00EC 32 0x0000FFFF #PGC_CPU_MAPPING memory setbit 0x303A00F8 32 0x20 #GPC_PU_PGC_SW_PUP_REQ: DDR1_SW_PUP_REQ=1 memory set 0x30391004 32 0x8F000000 #SRC_DDRC_RCR_ADDR #DRAM_PLL_CONFIG # The RPA provides the DRAM_PLL_FDIV_CTL0 register (0x30360054) setting for 1200Mhz (0x12C032). # For frequencies other than 1200Mhz, it is up to the user to create the appropriate register setting for the desired frequency. # Formula is DDR_freq = [(24MHz x pll_main_div)/(pll_pre_div x 2^pll_post_div)] x 2 memory set 0x30360054 32 0xC8022 #DRAM_PLL_FDIV_CTL0: For 1200MHz, pll_main_div = 300, pll_pre_div = 3, pll_post_div = 2 memory set 0x30360058 32 0x00000000 #DRAM_PLL_FDIV_CTL1: pll_dsm=0 memory setbit 0x30360050 32 0x200 #DRAM_PLL_GNRL_CTL: pll_rst = 1 memory clrbit 0x30360050 32 0x10 #DRAM_PLL_GNRL_CTL: pll_bypass = 0 memory chkbit1 0x30360050 32 0x80000000 #DRAM_PLL_GNRL_CTL: check pll_lock=1? memory set 0x30391000 32 0x8F000006 ################step2: DDRC configuration ################ memory set 0x3D400000 32 0x81040010 #DDRC_MSTR memory set 0x3D400030 32 0x00000020 #DDRC_PWRCTL memory set 0x3D400034 32 0x00221306 #DDRC_PWRTMG memory set 0x3D400050 32 0x00210070 #DDRC_RFSHCTL0 memory set 0x3D400054 32 0x00010008 #DDRC_RFSHCTL1 memory set 0x3D400060 32 0x00000000 #DDRC_RFSHCTL3 memory set 0x3D400064 32 0x0092014A #DDRC_RFSHTMG memory set 0x3D4000C0 32 0x00000000 #DDRC_CRCPARCTL0 memory set 0x3D4000C4 32 0x00001000 #DDRC_CRCPARCTL1 memory set 0x3D4000D0 32 0xC0030126 #DDRC_INIT0 memory set 0x3D4000D4 32 0x00770000 #DDRC_INIT1 memory set 0x3D4000DC 32 0x08640105 #DDRC_INIT3 memory set 0x3D4000E0 32 0x00180200 #DDRC_INIT4 memory set 0x3D4000E4 32 0x00110000 #DDRC_INIT5 memory set 0x3D4000E8 32 0x02000600 #DDRC_INIT6 memory set 0x3D4000EC 32 0x00000810 #DDRC_INIT7 memory set 0x3D4000F0 32 0x00000020 #DDRC_DIMMCTL memory set 0x3D4000F4 32 0x00000EC7 #DDRC_RANKCTL memory set 0x3D400100 32 0x11122914 #DDRC_DRAMTMG0 memory set 0x3D400104 32 0x0004051C #DDRC_DRAMTMG1 memory set 0x3D400108 32 0x0609050D #DDRC_DRAMTMG2 memory set 0x3D40010C 32 0x0000400C #DDRC_DRAMTMG3 memory set 0x3D400110 32 0x09030409 #DDRC_DRAMTMG4 memory set 0x3D400114 32 0x06060403 #DDRC_DRAMTMG5 memory set 0x3D40011C 32 0x00000606 #DDRC_DRAMTMG7 memory set 0x3D400120 32 0x07070D0C #DDRC_DRAMTMG8 memory set 0x3D400124 32 0x0002040A #DDRC_DRAMTMG9 memory set 0x3D40012C 32 0x1809010E #DDRC_DRAMTMG11 memory set 0x3D400130 32 0x00000008 #DDRC_DRAMTMG12 memory set 0x3D40013c 32 0x00000000 #DDRC_DRAMTMG15 memory set 0x3D400180 32 0x01000040 #DDRC_ZQCTL0 memory set 0x3D400184 32 0x0000493E #DDRC_ZQCTL1 memory set 0x3D400190 32 0x038C8207 #DDRC_DFITMG0 memory set 0x3D400194 32 0x02020303 #DDRC_DFITMG1 memory set 0x3D400198 32 0x07F04011 #DDRC_DFILPCFG0 memory set 0x3D40019c 32 0x000000B0 #DDRC_DFILPCFG1 memory set 0x3D4001A0 32 0xE0400018 #DDRC_DFIUPD0 memory set 0x3D4001A4 32 0x0048005A #DDRC_DFIUPD1 memory set 0x3D4001A8 32 0x80000000 #DDRC_DFIUPD2 memory set 0x3D4001B0 32 0x00000001 #DDRC_DFIMISC memory set 0x3D4001B4 32 0x00000C07 #DDRC_DFITMG2 memory set 0x3D4001B8 32 0x00000004 #DDRC_DFITMG3 memory set 0x3D4001C0 32 0x00000001 #DDRC_DBICTL memory set 0x3D4001C4 32 0x00000000 #DDRC_DFIPHYMSTR memory set 0x3D400200 32 0x00003F1F #DDRC_ADDRMAP0 memory set 0x3D400204 32 0x003F0909 #DDRC_ADDRMAP1 memory set 0x3D400208 32 0x00000700 #DDRC_ADDRMAP2 memory set 0x3D40020C 32 0x00000000 #DDRC_ADDRMAP3 memory set 0x3D400210 32 0x00001F1F #DDRC_ADDRMAP4 memory set 0x3D400214 32 0x07070707 #DDRC_ADDRMAP5 memory set 0x3D400218 32 0x07070707 #DDRC_ADDRMAP6 memory set 0x3D40021c 32 0x00000F07 #DDRC_ADDRMAP7 memory set 0x3D400220 32 0x00003F01 #DDRC_ADDRMAP8 memory set 0x3D400240 32 0x06000614 #DDRC_ODTCFG memory set 0x3D400244 32 0x00001323 #DDRC_ODTMAP #performance optimization memory set 0x3D400400 32 0x00000100 #DDRC_PCCFG memory set 0x3D400250 32 0x317D1A07 #DDRC_SCHED memory set 0x3D400254 32 0x0000000F #DDRC_SCHED1 memory set 0x3D40025C 32 0x2A001B76 #DDRC_PERFHPR1 memory set 0x3D400264 32 0x7300B473 #DDRC_PERFLPR1 memory set 0x3D40026C 32 0x30000E06 #DDRC_PERFWR1 memory set 0x3D400300 32 0x00000014 #DDRC_DBG0 memory set 0x3D40036C 32 0x00000010 #DDRC_POISONCFG memory set 0x3D400404 32 0x00013193 #DDRC_PCFGR_0 memory set 0x3D400408 32 0x00006096 #DDRC_PCFGW_0 memory set 0x3D400490 32 0x00000001 #DDRC_PCTRL_0 memory set 0x3D400494 32 0x02000C00 #DDRC_PCFGQOS0_0 memory set 0x3D400498 32 0x003C00DB #DDRC_PCFGQOS1_0 memory set 0x3D40049C 32 0x00100009 #DDRC_PCFGWQOS0_0 memory set 0x3D4004A0 32 0x00000002 #DDRC_PCFGWQOS1_0 # DDR-533MHz clock configuration memory set 0x3D402050 32 0x00210070 #DDRC_FREQ1_RFSHCTL0 memory set 0x3D402064 32 0x00400093 #DDRC_FREQ1_RFSHTMG memory set 0x3D4020DC 32 0x00040105 #DDRC_FREQ1_INIT3 memory set 0x3D4020E0 32 0x00000000 #DDRC_FREQ1_INIT4 memory set 0x3D4020E8 32 0x02000600 #DDRC_FREQ1_INIT6 memory set 0x3D4020EC 32 0x00000010 #DDRC_FREQ1_INIT7 memory set 0x3D402100 32 0x0B081209 #DDRC_FREQ1_DRAMTMG0 memory set 0x3D402104 32 0x0002020D #DDRC_FREQ1_DRAMTMG1 memory set 0x3D402108 32 0x05050309 #DDRC_FREQ1_DRAMTMG2 memory set 0x3D40210C 32 0x0000400C #DDRC_FREQ1_DRAMTMG3 memory set 0x3D402110 32 0x05030206 #DDRC_FREQ1_DRAMTMG4 memory set 0x3D402114 32 0x03030202 #DDRC_FREQ1_DRAMTMG5 memory set 0x3D40211C 32 0x00000303 #DDRC_FREQ1_DRAMTMG7 memory set 0x3D402120 32 0x04040D06 #DDRC_FREQ1_DRAMTMG8 memory set 0x3D402124 32 0x00020208 #DDRC_FREQ1_DRAMTMG9 memory set 0x3D40212C 32 0x1205010E #DDRC_FREQ1_DRAMTMG11 memory set 0x3D402130 32 0x00000008 #DDRC_FREQ1_DRAMTMG12 memory set 0x3D40213c 32 0x00000000 #DDRC_FREQ1_DRAMTMG15 memory set 0x3D402180 32 0x01000040 #DDRC_FREQ1_ZQCTL0 memory set 0x3D402190 32 0x03858204 #DDRC_FREQ1_DFITMG0 memory set 0x3D402194 32 0x02020303 #DDRC_FREQ1_DFITMG1 memory set 0x3D4021B4 32 0x00000504 #DDRC_FREQ1_DFITMG2 memory set 0x3D4021B8 32 0x00000004 #DDRC_FREQ1_DFITMG3 memory set 0x3D402240 32 0x06000604 #DDRC_FREQ1_ODTCFG memory set 0x3D4020F4 32 0x00000EC7 #DDRC_FREQ1_RANKCTL #RESET DDRC memory set 0x30391000 32 0x8F000004 #SRC_DDRC_RCR_ADDR memory set 0x30391000 32 0x8F000000 #SRC_DDRC_RCR_ADDR memory set 0x3d400304 32 0x00000000 #DDRC_DBG1 memory set 0x3d400030 32 0x00000020 #DDRC_PWRCTL memory set 0x3d400320 32 0x00000000 #DDRC_SWCTL memory set 0x3d4001b0 32 0x00000000 #DDRC_DDR_DFIMISC:12:8]dfi_freq, [5]dfi_init_start, [4]ctl_idle_en ######################### # DDR parameter settings ######################### ddrparam set dram_type 0 #DDR4=0,DDR3=1,LPDDR4=2,LPDDR3=3,DDR5=4 ddrparam set num_pstat 2 #up to support 4 frequencies (Hardware Fast Frequency Change) ddrparam set train_2d 1 #0=1D training only, 1=1D&2D training ddrparam set data_width 16 #16bit or 32bit only ddrparam set PhyVref 0x5E #### DDR frequency point0 ##### ddrparam set frequency0 1200 ddrparam set pllbypass0 0 freq0 set 0x3038A088 32 0x07070000 #CCM_TARGET_ROOT_CLR(DRAM_APB_CLK_ROOT) freq0 set 0x3038A084 32 0x04030000 #CCM_TARGET_ROOT_SET(DRAM_APB_CLK_ROOT):MUX=4(system_pll1_800M_clk), PRE_PODF=3 //DRAM_APB_CLK=800/4=200MHz freq0 set 0x303A00EC 32 0x0000FFFF #PGC_CPU_MAPPING,disable the clock gating freq0 setbit 0x303A00F8 32 0x20 #GPC_PU_PGC_SW_PUP_REQ: DDR1_SW_PUP_REQ=1 freq0 clrbit 0x30360050 32 0x200 #DRAM_PLL_GNRL_CTL: pll_rst = 0 freq0 set 0x30360054 32 0xC8022 #DRAM_PLL_FDIV_CTL0:pll_main_div = 300, pll_pre_div = 3, pll_post_div = 2 freq0 set 0x30360058 32 0x00000000 #DRAM_PLL_FDIV_CTL1: pll_dsm=0 freq0 setbit 0x30360050 32 0x200 #DRAM_PLL_GNRL_CTL: pll_rst = 1 freq0 clrbit 0x30360050 32 0x10 #DRAM_PLL_GNRL_CTL: pll_bypass = 0 freq0 chkbit1 0x30360050 32 0x80000000 #DRAM_PLL_GNRL_CTL: check pll_lock=1? freq0 set 0x30389808 32 0x01000000 #CCM_TARGET_ROOT_CLR(DRAM_SEL): clear DRAM PLL bypass bit24 #### DDR frequency point1 ##### ddrparam set frequency1 533 ddrparam set pllbypass1 0 freq1 set 0x3038A088 32 0x07070000 #CCM_TARGET_ROOT_CLR(DRAM_APB_CLK_ROOT) freq1 set 0x3038A084 32 0x04030000 #CCM_TARGET_ROOT_SET(DRAM_APB_CLK_ROOT):MUX=4(system_pll1_800M_clk), PRE_PODF=3 //DRAM_APB_CLK=800/4=200MHz freq1 set 0x303A00EC 32 0x0000FFFF #PGC_CPU_MAPPING,disable the clock gating freq1 setbit 0x303A00F8 32 0x20 #GPC_PU_PGC_SW_PUP_REQ: DDR1_SW_PUP_REQ=1 freq1 clrbit 0x30360050 32 0x200 #DRAM_PLL_GNRL_CTL: pll_rst = 0 freq1 set 0x30360054 32 0x10A033 #DRAM_PLL_FDIV_CTL0:pll_main_div = 266, pll_pre_div = 3, pll_post_div = 3 freq1 set 0x30360058 32 0x00000000 #DRAM_PLL_FDIV_CTL1: pll_dsm=0 freq1 setbit 0x30360050 32 0x200 #DRAM_PLL_GNRL_CTL: pll_rst = 1 freq1 clrbit 0x30360050 32 0x10 #DRAM_PLL_GNRL_CTL: pll_bypass = 0 freq1 chkbit1 0x30360050 32 0x80000000 #DRAM_PLL_GNRL_CTL: check pll_lock=1? freq1 set 0x30389808 32 0x01000000 #CCM_TARGET_ROOT_CLR(DRAM_SEL): clear DRAM PLL bypass bit24 ddrparam set csPresent 0x1 #Indicates presence of DRAM at each chip select for PHY. #If the bit is set to 1, the CS is connected to DRAM. #If the bit is set to 0, the CS is not connected to DRAM. #Set CsPresent[0] = 1 (if CS0 is populated with DRAM) #Set CsPresent[1] = 1 (if CS1 is populated with DRAM) #Set CsPresent[2] = 1 (if CS2 is populated with DRAM) #Set CsPresent[3] = 1 (if CS3 is populated with DRAM) #Set CsPresent[7:4] = 0 (Reserved; must be programmed to 0) ddrparam set rdODT0 2 ddrparam set rdODT1 1 ddrparam set rdODT2 0 ddrparam set rdODT3 0 ddrparam set wrODT0 1 ddrparam set wrODT1 2 ddrparam set wrODT2 0 ddrparam set wrODT3 0 ddrparam set addrMirror 0x00 # Corresponds to CS[3:0] # 1 = Address Mirror. # 0 = No Address Mirror. # The following is to configure the recommended training, it is strongly recommended not to change this ddrparam set TrainCtrl0 0x031f #TrainCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. #TrainCtrl[1] = Run WrLvl - Write leveling #TrainCtrl[2] = Run RxEn - Read gate training #TrainCtrl[3] = Run RdDQS1D - 1d read dqs training #TrainCtrl[4] = Run WrDQ1D - 1d write dq training #TrainCtrl[5] = RFU, must be zero #TrainCtrl[6] = RFU, must be zero #TrainCtrl[7] = RFU, must be zero #TrainCtrl[8] = Run RdDeskew - Per lane read dq deskew training #TrainCtrl[9] = Run MxRdLat - Max read latency training #TrainCtrl[11-10] = RFU, must be zero #TrainCtrl[12] = Run LPCA - CA Training #TrainCtrl[15-13] = RFU, must be zero # The following is for internal factory use, it is strongly recommended not to change this ddrparam set TrainInfo 0xC8 #0x05 = Detailed debug (e.g. eys delays) #0x0A = Coarse debug info (e.g. rank information) #0xC8 = Stage completion #0xC9 = Assertion messages #0xFF = Firmware complete #others = reserved ddrparam set MR0 0x0864 ddrparam set MR1 0x0105 ddrparam set MR2 0x0018 ddrparam set MR3 0x0200 ddrparam set MR4 0x0200 ddrparam set MR5 0x0600 ddrparam set MR6 0x0810 ddrparam set MR0-1 0x0004 ddrparam set MR1-1 0x0105 ddrparam set MR2-1 0x0000 ddrparam set MR3-1 0x0000 ddrparam set MR4-1 0x0200 ddrparam set MR5-1 0x0600 ddrparam set MR6-1 0x0010 ddrparam set rdPreAmbLen 0x0 ddrparam set wrPreAmbLen 0x0 ddrparam set ATxImpedance 40 ddrparam set ODTImpedance 48 ddrparam set TxImpedance 40 ddrparam set extCalRes 0x00 ddrparam set WDQSExt 0x00 ddrparam set SlewRiseDQ 0x0d ddrparam set SlewFallDQ 0x0f ddrparam set SlewFallAC 0x05 ddrparam set SlewRiseAC 0x05 ddrparam set CaliInterval 0x09 ddrparam set CaliOnce 0x00 ddrparam set RX2D_trainOpt 0x00 ddrparam set TX2D_trainOpt 0x00 ddrparam set Share_2dVref 0x01 ddrparam set Delay_weight2d 0x7f ddrparam set Volt_weight2d 0x1f