/*
 * i.MX drm driver - Raydium MIPI-DSI panel driver
 *
 * Copyright (C) 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_panel.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
#include <video/of_videomode.h>
#include <video/videomode.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include "panel-dsi85.h"

#define CMD_TABLE_LEN 2
static int lcd_type = 4; //0 defaul, 1, 7inc mipi , 2 9inc , 3 10inch , 4 21inch , 5 15inch, 6 amp 7inch
typedef u8 cmd_set_table[CMD_TABLE_LEN];
static int enable_gpio;
/* Write Manufacture Command Set Control */
#define WRMAUCCTR 0xFE
//extern void sn65dsi8x_config(void);
//extern void sn65dsi85_enable(void);

struct reg_v {
    unsigned char reg;
    unsigned char val;
};
#define MAX_REG_LEN 43 
static struct reg_v init_reg[MAX_REG_LEN] = {
    { 0x09, 0x00},
    { 0x0A, 0x05},
    { 0x0B, 0x18},
    { 0x0D, 0x00},
    { 0x10, 0x26},
    { 0x11, 0x00},
    { 0x12, 0x63},
    { 0x13, 0x00},
    { 0x18, 0x6c},
    { 0x19, 0x00},
    { 0x1A, 0x03},
    { 0x1B, 0x00},
    { 0x20, 0x80},
    { 0x21, 0x07},
    { 0x22, 0x00},
    { 0x23, 0x00},
    { 0x24, 0x00},
    { 0x25, 0x00},
    { 0x26, 0x00},
    { 0x27, 0x00},
    { 0x28, 0xe1},
    { 0x29, 0x03},
    { 0x2A, 0x00},
    { 0x2B, 0x00},
    { 0x2C, 0x20},
    { 0x2D, 0x00},
    { 0x2E, 0x00},
    { 0x2F, 0x00},
    { 0x30, 0x04},
    { 0x31, 0x00},
    { 0x32, 0x00},
    { 0x33, 0x00},
    { 0x34, 0x30},
    { 0x35, 0x00},
    { 0x36, 0x00},
    { 0x37, 0x00},
    { 0x38, 0x00},
    { 0x39, 0x00},
    { 0x3A, 0x00},
    { 0x3B, 0x00},
    { 0x3C, 0x00},
    { 0x3D, 0x00},
    { 0x3E, 0x00},
};


/*
 * The clock might range from 66MHz (30Hz refresh rate)
 * to 132MHz (60Hz refresh rate)
 */
static const struct display_timing sn65_default_timing = {
#if 0
	.pixelclock =  { 50000000, 51000000, 80000000 },
	//.pixelclock =  { 50000000, 65000000, 80000000 },
    //   .pixelclock = { 66000000, 120000000, 132000000 },
       .hactive = { 1080, 1080, 1080 },
	.hfront_porch = { 48, 48, 48 },
	.hback_porch = { 160, 160,160 },
	.hsync_len = { 32, 32, 32 },
       .vactive = { 1920, 1920, 1920 },
	.vfront_porch = { 3, 3, 3 },
	.vback_porch = { 23, 23, 23 },
	.vsync_len = { 12, 12, 12 },
	.flags = DISPLAY_FLAGS_DE_HIGH|DRM_MODE_FLAG_NHSYNC|DRM_MODE_FLAG_NVSYNC,
#else
       //.pixelclock = { 66000000, 120000000, 132000000 },
       .pixelclock = { 66000000, 120000000, 132000000 },
       .hactive = { 1080, 1080, 1080 },
       .hfront_porch = { 20, 20, 20 },
       .hsync_len = { 2, 2, 2 },
       .hback_porch = { 34, 34, 34 },
       .vactive = { 1920, 1920, 1920 },
       .vfront_porch = { 10, 10, 10 },
       .vsync_len = { 2, 2, 2 },
       .vback_porch = { 4, 4, 4 },

	.flags = DISPLAY_FLAGS_HSYNC_LOW |
		 DISPLAY_FLAGS_VSYNC_LOW |
		 DISPLAY_FLAGS_DE_LOW |
		 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
#endif
};
static const struct display_timing sn65_7inchmip_timing = {
       //.pixelclock = { 66000000, 120000000, 132000000 },
       //.pixelclock = { 66000000, 120000000, 132000000 },
       //.pixelclock = { 80000000, 51000000, 132000000 },
#if 1 //7inch
       .pixelclock = { 80000000, 100000000, 132000000 },
       .hactive = { 1200, 1200, 1200 },
       .hfront_porch = { 100, 100, 100 },
       .hsync_len = { 8, 8, 8 },
       .hback_porch = { 45, 45, 45 },
       .vactive = { 1448, 1920, 1928 },
       .vfront_porch = { 4, 4, 4 },
       .vsync_len = { 1, 1, 1 },
       .vback_porch = { 4, 4, 4 },
#endif

	.flags = DISPLAY_FLAGS_HSYNC_LOW |
		 DISPLAY_FLAGS_VSYNC_LOW |
		 DISPLAY_FLAGS_DE_LOW |
		 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
};

static const struct display_timing sn65_9inch_timing = {
       //.pixelclock = { 66000000, 120000000, 132000000 },
       .pixelclock = { 66000000, 120000000, 132000000 },
       .hactive = { 1080, 1080, 1080 },
       .hfront_porch = { 20, 20, 20 },
       .hsync_len = { 2, 2, 2 },
       .hback_porch = { 34, 34, 34 },
       .vactive = { 1920, 1920, 1920 },
       .vfront_porch = { 10, 10, 10 },
       .vsync_len = { 2, 2, 2 },
       .vback_porch = { 4, 4, 4 },

	.flags = DISPLAY_FLAGS_HSYNC_LOW |
		 DISPLAY_FLAGS_VSYNC_LOW |
		 DISPLAY_FLAGS_DE_LOW |
		 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
};


static const struct display_timing sn65_10inch_timing = {
       //.pixelclock = { 66000000, 120000000, 132000000 },
       //.pixelclock = { 66000000, 160000000, 182000000 },
       .pixelclock = { 80000000, 100000000, 132000000 },
       .hactive = { 1200, 1200, 1200 },
       .hfront_porch = { 100, 100, 100 },
       .hsync_len = { 8, 8, 8 },
       .hback_porch = { 45, 45, 45 },
       .vactive = { 1448, 1920, 1928 },
       .vfront_porch = { 4, 4, 4 },
       .vsync_len = { 1, 1, 1 },
       .vback_porch = { 4, 4, 4 },

	.flags = DISPLAY_FLAGS_HSYNC_LOW |
		 DISPLAY_FLAGS_VSYNC_LOW |
		 DISPLAY_FLAGS_DE_LOW |
		 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
};
static const struct display_timing sn65_15inch_timing = {
       //.pixelclock = { 66000000, 120000000, 132000000 },
       //.pixelclock = { 66000000, 120000000, 132000000 },
       //.pixelclock = { 80000000, 51000000, 132000000 },
   //.pixelclock = { 80000000, 130000000, 132000000 }, //ok for 15inch
#if 0
    .pixelclock = { 80000000, 130000000, 132000000 }, //ok for 15inch
	.hactive = { 1024, 1024,1024 },
	.hfront_porch = { 48, 48, 48 },
	.hback_porch = { 240, 240,240 },
	.hsync_len = { 32, 32, 32 },
	.vactive =  { 768, 768, 768},
	.vfront_porch = { 3, 3, 3 },
	.vback_porch = { 23, 23, 23 },
	.vsync_len = { 12, 12, 12 },
#else
     .pixelclock = { 60000000, 72000000, 132000000 },
	.hactive = { 1024, 1024,1024 },
	.hfront_porch = { 48, 48, 48 },
	.hback_porch = { 240, 240,240 },
	.hsync_len = { 32, 32, 32 },
	.vactive =  { 768, 768, 768},
	.vfront_porch = { 3, 3, 3 },
	.vback_porch = { 23, 23, 23 },
	.vsync_len = { 12, 12, 12 },
#endif

	.flags = DISPLAY_FLAGS_HSYNC_LOW |
		 DISPLAY_FLAGS_VSYNC_LOW |
		 DISPLAY_FLAGS_DE_LOW |
		 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
};
static const struct display_timing sn65_21inch_timing = {
       //.pixelclock = { 60000000, 72000000, 132000000 },
#if 0
       .pixelclock = { 80000000, 100000000, 132000000 },
       .hactive = { 1920, 1920, 1920 },
       .hfront_porch = { 48, 48, 48 },
       .hsync_len = { 32, 32, 32 },
       .hback_porch = { 48, 48, 48},
       .vactive = { 1080, 1080, 1080 },
       .vfront_porch = { 8, 8, 8 },
       .vsync_len = { 4, 4, 4 },
       .vback_porch = { 8, 8, 8 },
#else
       .pixelclock = { 80000000, 148500000, 158500000 },
       .hactive = { 1920, 1920, 1920 },
       .hfront_porch = { 48, 48, 48 },
       .hsync_len = { 32, 32, 32 },
       .hback_porch = { 48, 48, 48},
       .vactive = { 1080, 1080, 1080 },
       .vfront_porch = { 8, 8, 8 },
       .vsync_len = { 4, 4, 4 },
       .vback_porch = { 8, 8, 8 },

#endif

	.flags = DISPLAY_FLAGS_HSYNC_LOW |
		 DISPLAY_FLAGS_VSYNC_LOW |
		 DISPLAY_FLAGS_DE_LOW |
		 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
};

static const struct display_timing sn65_7inch_amp_timing = {
       //.pixelclock = { 66000000, 120000000, 132000000 },
       //.pixelclock = { 66000000, 120000000, 132000000 },
       //.pixelclock = { 80000000, 51000000, 132000000 },

       .pixelclock = { 30000000, 56000000, 158500000 },
       .hactive = { 1024, 1024, 1024 },
       .hfront_porch = { 160, 160, 160 },
       .hsync_len = { 4, 50, 100 },
       .hback_porch = { 160, 160, 160  },
       .vactive = { 600, 600, 600 },
       .vfront_porch = { 17, 17, 17 },
       .vsync_len = { 12, 12, 12 },
       .vback_porch = {18,18, 18},


	.flags = DISPLAY_FLAGS_HSYNC_LOW |
		 DISPLAY_FLAGS_VSYNC_LOW |
		 DISPLAY_FLAGS_DE_LOW |
		 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
};


static void write_dsi85(struct i2c_client *i2c, u8 reg, u8 value)
{
	int res;
	res = i2c_smbus_write_byte_data(i2c, reg, value);
	DRM_DEV_DEBUG(&i2c->dev, "write reg 0x%X <- 0x%X (res=%d)", reg, value, res);
	if(res < 0) {
		DRM_DEV_ERROR(&i2c->dev, "could not write DSI85 register 0x%x, i2c error %d", reg, res);
	}
}


/**
 * dsi85_config - Configure dsi85
 *
 * Initial configuration for dsi85 configuration registers
 */
void sn65dsi8x_config(struct i2c_client *i2c)
{
	printk(KERN_INFO ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Now Configuring\n");
	
	//struct dsi85_data *dsi85_d = dev_get_drvdata(&dssdev->dev);

    if(i2c == NULL)return;
    int i = 0;
    for( i = 0; i< MAX_REG_LEN; i++){

	    write_dsi85(i2c,init_reg[i].reg ,init_reg[i].val);
    }
	printk(KERN_INFO "Config END\n");
	return;
}

void sn65dsi85_reconfig(struct i2c_client *i2c,int lcdtype){

    struct display_timing *timing = NULL;
    u8 val = 0x01;
    unsigned int  pixel_clock = 137500;
    switch(lcdtype){
        case 4://21inch
            break;
        case 6://7inch amp
            timing = &sn65_7inch_amp_timing;
            pixel_clock = timing->pixelclock.typ;

            /* user external clock reference with no muliplier */
            if (pixel_clock <= 37500)
            {
                // Do nothing.
            }
            else if (pixel_clock <= 62500)
            {
                val |= (0x01 << 1);
            }
            else if (pixel_clock <= 87500)
            {
                val |= (0x02 << 1);
            }
            else if (pixel_clock <= 112500)
            {
                val |= (0x03 << 1);
            }
            //else if (dssdev->panel.timings.pixel_clock <= 137500)
            else if (pixel_clock <= 137500)
            {
                val |= (0x04 << 1);
            }
            else
            {
                val |= (0x05 << 1);
            }
            write_dsi85(i2c,DSI85_CORE_PLL,val);
            write_dsi85(i2c,DSI85_PLL_DIV,0x10);
            write_dsi85(i2c,DSI85_CHA_DSI_CLK_RNG,(pixel_clock * 3 / 5000));
            write_dsi85(i2c,DSI85_CHB_DSI_CLK_RNG,(pixel_clock * 3 / 5000));
            write_dsi85(i2c,DSI85_LVDS_MODE,0x78);
            break;
    };
    if( timing != NULL ){
     
#if 1
        write_dsi85(i2c,DSI85_CHA_LINE_LEN_LO,timing->hactive.typ & 0x00FF);
        write_dsi85(i2c,DSI85_CHA_LINE_LEN_HI,(timing->hactive.typ & 0xFF00) >> 8);
        write_dsi85(i2c,DSI85_CHB_LINE_LEN_LO,timing->hactive.typ & 0x00FF);
        write_dsi85(i2c,DSI85_CHB_LINE_LEN_HI,(timing->hactive.typ & 0xFF00) >> 8);

        write_dsi85(i2c,DSI85_CHA_VERT_LINES_LO,timing->vactive.typ & 0x00FF);
        write_dsi85(i2c,DSI85_CHA_VERT_LINES_HI,(timing->vactive.typ & 0xFF00) >> 8);
        write_dsi85(i2c,DSI85_CHB_VERT_LINES_LO,timing->vactive.typ & 0x00FF);
        write_dsi85(i2c,DSI85_CHB_VERT_LINES_HI,(timing->vactive.typ & 0xFF00) >> 8);
#endif

        write_dsi85(i2c,DSI85_CHA_HSYNC_WIDTH_LO,timing->hsync_len.typ & 0x00FF);
        write_dsi85(i2c,DSI85_CHA_HSYNC_WIDTH_HI,(timing->hsync_len.typ & 0xFF00) >> 8);
        write_dsi85(i2c,DSI85_CHB_HSYNC_WIDTH_LO,timing->hsync_len.typ & 0x00FF);
        write_dsi85(i2c,DSI85_CHB_HSYNC_WIDTH_HI,(timing->hsync_len.typ & 0xFF00) >> 8);

        write_dsi85(i2c,DSI85_CHA_VSYNC_WIDTH_LO,timing->vsync_len.typ & 0x00FF);
        write_dsi85(i2c,DSI85_CHA_VSYNC_WIDTH_HI,(timing->vsync_len.typ & 0xFF00) >> 8);
        write_dsi85(i2c,DSI85_CHB_VSYNC_WIDTH_LO,timing->vsync_len.typ & 0x00FF);
        write_dsi85(i2c,DSI85_CHB_VSYNC_WIDTH_HI,(timing->vsync_len.typ & 0xFF00) >> 8);


        write_dsi85(i2c,DSI85_CHA_HORZ_BACKPORCH,timing->hback_porch.typ );
        write_dsi85(i2c,DSI85_CHB_HORZ_BACKPORCH,timing->hback_porch.typ );

        write_dsi85(i2c,DSI85_CHA_VERT_BACKPORCH,timing->vback_porch.typ );
        write_dsi85(i2c,DSI85_CHB_VERT_BACKPORCH,timing->vback_porch.typ );

        write_dsi85(i2c,DSI85_CHA_HORZ_FRONTPORCH,timing->hfront_porch.typ );
        write_dsi85(i2c,DSI85_CHB_HORZ_FRONTPORCH,timing->hfront_porch.typ );

        write_dsi85(i2c,DSI85_CHA_VERT_FRONTPORCH,timing->vfront_porch.typ );
        write_dsi85(i2c,DSI85_CHB_VERT_FRONTPORCH,timing->vfront_porch.typ );

    }
}



void sn65dsi85_enable(struct i2c_client * client)
{
    if(client == NULL)return;
    printk("function:%s line:%d - \n",__FUNCTION__,__LINE__);
	i2c_smbus_write_byte_data(client, 0x0D, 0x01);
    udelay(3100);
	i2c_smbus_write_byte_data(client, 0x09, 0x01);			

}


static const cmd_set_table inc10_manufacturer_cmd_set[] = {
//Page0
    {0xE0,0x00},
//--- PASSWORD  ----//
    {0xE1,0x93},
    {0xE2,0x65},
    {0xE3,0xF8},
    {0x80,0x03},//0X03：4-LANE;0X02：3-LANE;0X01:2-LANE


//--- Page1  ----//
    {0xE0,0x01},
//Set VCOM
    {0x00,0x00},
    {0x01,0x6F},
//Set VCOM_Reverse
//    {0x03,0x00},
//    {0x04,0xA0},
//Set Gamma Power, VGMP,VGMN,VGSP,VGSN
    {0x17,0x00},
    {0x18,0xAF},//4.3V
    {0x19,0x01},//0.3V
    {0x1A,0x00},//
    {0x1B,0xAF},//4.3V
    {0x1C,0x01},//0.3V
               
//Set Gate Power
    {0x1F,0x3E},     //VGH_R  = 15V                       
    {0x20,0x28},     //VGL_R  = -12V                      
    {0x21,0x28},     //VGL_R2 = -12V                      
    {0x22,0x7E},     //PA[6]=1, PA[5]=1, PA[4]=1, PA[0]=0 
//SETPANEL
    {0x35,0x26},  //ASP=0110

//SETPANEL
    {0x37,0x09},  //SS=1,BGR=1
//SET RGBCYC
    {0x38,0x04},  //JDT=100 column inversion
    {0x39,0x00},  //RGB_N_EQ1, 0x12
    {0x3A,0x01},  //RGB_N_EQ2, 0x18
    {0x3C,0x7C},  //SET EQ3 for TE_H
    {0x3D,0xFF},  //SET CHGEN_ON, 
    {0x3E,0xFF},  //SET CHGEN_OFF, 
    {0x3F,0x7F},  //SET CHGEN_OFF2,

//Set TCON
    {0x40,0x06},  //RSO=800 RGB
    {0x41,0xA0},  //LN=640->1280 line
    {0x42,0x81},  //SLT
    {0x43,0x08},  //VFP=8
    {0x44,0x0B},  //VBP=12
    {0x45,0x28},  //HBP=40
//--- power voltage  ----//
    {0x55,0x0F},  //DCDCM=0001, JD PWR_IC
    {0x57,0x69},
    {0x59,0x0A},  //VCL = -2.9V
    {0x5A,0x28},  //VGH = 15V
    {0x5B,0x14},  //VGL = -11V

//--- Gamma  ----//
    {0x5D,0x7C},              
    {0x5E,0x65},      
    {0x5F,0x55},    
    {0x60,0x47},    
    {0x61,0x43},    
    {0x62,0x32},    
    {0x63,0x34},    
    {0x64,0x1C},    
    {0x65,0x33},    
    {0x66,0x31},    
    {0x67,0x30},    
    {0x68,0x4E},    
    {0x69,0x3C},    
    {0x6A,0x44},    
    {0x6B,0x35},    
    {0x6C,0x31},    
    {0x6D,0x23},    
    {0x6E,0x11},    
    {0x6F,0x00},    
    {0x70,0x7C},    
    {0x71,0x65},    
    {0x72,0x55},    
    {0x73,0x47},    
    {0x74,0x43},    
    {0x75,0x32},    
    {0x76,0x34},    
    {0x77,0x1C},    
    {0x78,0x33},    
    {0x79,0x31},    
    {0x7A,0x30},    
    {0x7B,0x4E},    
    {0x7C,0x3C},    
    {0x7D,0x44},    
    {0x7E,0x35},    
    {0x7F,0x31},    
    {0x80,0x23},    
    {0x81,0x11},    
    {0x82,0x00},    

                                 
//Page2, for GIP                                      
    {0xE0,0x02},                                
//GIP_L Pin mapping                                   
    {0x00,0x1E},//1  VDS                        
    {0x01,0x1E},//2  VDS                        
    {0x02,0x41},//3  STV2                       
    {0x03,0x41},//4  STV2                       
    {0x04,0x43},//5  STV4                       
    {0x05,0x43},//6  STV4                       
    {0x06,0x1F},//7  VSD                        
    {0x07,0x1F},//8  VSD                        
    {0x08,0x35},//9  GCL                        
    {0x09,0x1F},//10                            
    {0x0A,0x15},//11 GCH                        
    {0x0B,0x15},//12 GCH                        
    {0x0C,0x1F},//13                            
    {0x0D,0x47},//14 CLK8                       
    {0x0E,0x47},//15 CLK8                       
    {0x0F,0x45},//16 CLK6                       
    {0x10,0x45},//17 CLK6                       
    {0x11,0x4B},//18 CLK4                       
    {0x12,0x4B},//19 CLK4                       
    {0x13,0x49},//20 CLK2                       
    {0x14,0x49},//21 CLK2                       
    {0x15,0x1F},//22 VGL                        
                                                      
                                                      
//GIP_R Pin mapping                                   
    {0x16,0x1E},//1  VDS                 
    {0x17,0x1E},//2  VDS                
    {0x18,0x40},//3  STV1               
    {0x19,0x40},//4  STV1               
    {0x1A,0x42},//5  STV3               
    {0x1B,0x42},//6  STV3               
    {0x1C,0x1F},//7  VSD                
    {0x1D,0x1F},//8  VSD                
    {0x1E,0x35},//9  GCL                
    {0x1F,0x1F},//10                    
    {0x20,0x15},//11 GCH                
    {0x21,0x15},//12 GCH                
    {0x22,0x1f},//13                    
    {0x23,0x46},//14 CLK7               
    {0x24,0x46},//15 CLK7               
    {0x25,0x44},//16 CLK5               
    {0x26,0x44},//17 CLK5               
    {0x27,0x4A},//18 CLK3               
    {0x28,0x4A},//19 CLK3               
    {0x29,0x48},//20 CLK1               
    {0x2A,0x48},//21 CLK1               
    {0x2B,0x1F},//22 VGL                                 



//GIP Timing  
    {0x58,0x40}, 
    {0x5B,0x30}, //STV_NUM,STV_S0
    {0x5C,0x03}, //STV_S0
    {0x5D,0x30}, //STV_W / S1
    {0x5E,0x01}, //STV_S2
    {0x5F,0x02}, //STV_S3
    {0x63,0x14}, //SETV_ON  
    {0x64,0x6A}, //SETV_OFF 
    {0x67,0x73}, 
    {0x68,0x05}, 
    {0x69,0x14}, 
    {0x6A,0x6A}, 
    {0x6B,0x08}, //Dummy clk

    {0x6C,0x00}, 
    {0x6D,0x00}, 
    {0x6E,0x00}, 
    {0x6F,0x88}, 

    {0x77,0xDD}, 
    {0x79,0x0E},//0x0C 
    {0x7A,0x03},//0x04
    {0x7D,0x14}, 
    {0x7E,0x6A}, 


//Page4
    {0xE0,0x04},
    {0x09,0x11},
    {0x0E,0x48},
    {0x2B,0x2B},
    {0x2D,0x03},//defult 0x01
    {0x2E,0x44},

//Page0
    {0xE0,0x00},

    {0xE6,0x02},
    {0xE7,0x0C},
};
/* Manufacturer Command Set pages (CMD2) */
static const cmd_set_table manufacturer_cmd_set[] = {
	{0xFE, 0x0B},
	{0x28, 0x40},
	{0x29, 0x4F},
	{0xFE, 0x0E},
	{0x4B, 0x00},
	{0x4C, 0x0F},
	{0x4D, 0x20},
	{0x4E, 0x40},
	{0x4F, 0x60},
	{0x50, 0xA0},
	{0x51, 0xC0},
	{0x52, 0xE0},
	{0x53, 0xFF},
	{0xFE, 0x0D},
	{0x18, 0x08},
	{0x42, 0x00},
	{0x08, 0x41},
	{0x46, 0x02},
	{0x72, 0x09},
	{0xFE, 0x0A},
	{0x24, 0x17},
	{0x04, 0x07},
	{0x1A, 0x0C},
	{0x0F, 0x44},
	{0xFE, 0x04},
	{0x00, 0x0C},
	{0x05, 0x08},
	{0x06, 0x08},
	{0x08, 0x08},
	{0x09, 0x08},
	{0x0A, 0xE6},
	{0x0B, 0x8C},
	{0x1A, 0x12},
	{0x1E, 0xE0},
	{0x29, 0x93},
	{0x2A, 0x93},
	{0x2F, 0x02},
	{0x31, 0x02},
	{0x33, 0x05},
	{0x37, 0x2D},
	{0x38, 0x2D},
	{0x3A, 0x1E},
	{0x3B, 0x1E},
	{0x3D, 0x27},
	{0x3F, 0x80},
	{0x40, 0x40},
	{0x41, 0xE0},
	{0x4F, 0x2F},
	{0x50, 0x1E},
	{0xFE, 0x06},
	{0x00, 0xCC},
	{0x05, 0x05},
	{0x07, 0xA2},
	{0x08, 0xCC},
	{0x0D, 0x03},
	{0x0F, 0xA2},
	{0x32, 0xCC},
	{0x37, 0x05},
	{0x39, 0x83},
	{0x3A, 0xCC},
	{0x41, 0x04},
	{0x43, 0x83},
	{0x44, 0xCC},
	{0x49, 0x05},
	{0x4B, 0xA2},
	{0x4C, 0xCC},
	{0x51, 0x03},
	{0x53, 0xA2},
	{0x75, 0xCC},
	{0x7A, 0x03},
	{0x7C, 0x83},
	{0x7D, 0xCC},
	{0x82, 0x02},
	{0x84, 0x83},
	{0x85, 0xEC},
	{0x86, 0x0F},
	{0x87, 0xFF},
	{0x88, 0x00},
	{0x8A, 0x02},
	{0x8C, 0xA2},
	{0x8D, 0xEA},
	{0x8E, 0x01},
	{0x8F, 0xE8},
	{0xFE, 0x06},
	{0x90, 0x0A},
	{0x92, 0x06},
	{0x93, 0xA0},
	{0x94, 0xA8},
	{0x95, 0xEC},
	{0x96, 0x0F},
	{0x97, 0xFF},
	{0x98, 0x00},
	{0x9A, 0x02},
	{0x9C, 0xA2},
	{0xAC, 0x04},
	{0xFE, 0x06},
	{0xB1, 0x12},
	{0xB2, 0x17},
	{0xB3, 0x17},
	{0xB4, 0x17},
	{0xB5, 0x17},
	{0xB6, 0x11},
	{0xB7, 0x08},
	{0xB8, 0x09},
	{0xB9, 0x06},
	{0xBA, 0x07},
	{0xBB, 0x17},
	{0xBC, 0x17},
	{0xBD, 0x17},
	{0xBE, 0x17},
	{0xBF, 0x17},
	{0xC0, 0x17},
	{0xC1, 0x17},
	{0xC2, 0x17},
	{0xC3, 0x17},
	{0xC4, 0x0F},
	{0xC5, 0x0E},
	{0xC6, 0x00},
	{0xC7, 0x01},
	{0xC8, 0x10},
	{0xFE, 0x06},
	{0x95, 0xEC},
	{0x8D, 0xEE},
	{0x44, 0xEC},
	{0x4C, 0xEC},
	{0x32, 0xEC},
	{0x3A, 0xEC},
	{0x7D, 0xEC},
	{0x75, 0xEC},
	{0x00, 0xEC},
	{0x08, 0xEC},
	{0x85, 0xEC},
	{0xA6, 0x21},
	{0xA7, 0x05},
	{0xA9, 0x06},
	{0x82, 0x06},
	{0x41, 0x06},
	{0x7A, 0x07},
	{0x37, 0x07},
	{0x05, 0x06},
	{0x49, 0x06},
	{0x0D, 0x04},
	{0x51, 0x04},
};

struct sn65_panel {
	struct drm_panel base;
	struct mipi_dsi_device *dsi;

	struct gpio_desc *reset;
	struct backlight_device *backlight;

	bool prepared;
	bool enabled;

	struct videomode vm;
	struct i2c_adapter *ddc;
	u32 width_mm;
	u32 height_mm;
	struct i2c_client *client;
};

static inline struct sn65_panel *to_sn65_panel(struct drm_panel *panel)
{
	return container_of(panel, struct sn65_panel, base);
}

static int sn65_panel_push_cmd_list(struct mipi_dsi_device *dsi)
{
	size_t i;
	const u8 *cmd;
	size_t count = sizeof(manufacturer_cmd_set) / CMD_TABLE_LEN;
	int ret = 0;

    if(lcd_type == 0){
		cmd = manufacturer_cmd_set[i];
	    count = sizeof(manufacturer_cmd_set) / CMD_TABLE_LEN;
    }else if(lcd_type == 3){
		cmd = inc10_manufacturer_cmd_set[i];
	    count = sizeof(inc10_manufacturer_cmd_set) / CMD_TABLE_LEN;
    }
	for (i = 0; i < count ; i++) {
		ret = mipi_dsi_generic_write(dsi, cmd, CMD_TABLE_LEN);
		if (ret < 0)
			return ret;
	}

	return ret;
};
static int sn65_panel_prepare(struct drm_panel *panel)
{
	struct sn65_panel *sn65 = to_sn65_panel(panel);
	struct mipi_dsi_device *dsi = sn65->dsi;
	struct device *dev = &dsi->dev;
	int ret;

	if (sn65->prepared)
		return 0;
    if (gpio_is_valid(enable_gpio)) {  
		udelay(100);
	    gpio_set_value(enable_gpio, 1);
		udelay(1500);
        sn65dsi8x_config(sn65->client);
        sn65dsi85_reconfig(sn65->client,lcd_type);
        sn65dsi85_enable(sn65->client);
    }
	DRM_DEV_DEBUG_DRIVER(dev, "\n");

	if (sn65->reset != NULL) {
		gpiod_set_value(sn65->reset, 1);
		msleep(100);
		gpiod_set_value(sn65->reset, 0);
		msleep(100);
		gpiod_set_value(sn65->reset, 1);
		msleep(100);
	}

	dsi->mode_flags |= MIPI_DSI_MODE_LPM;

    if(lcd_type == 0){ //default
        ret = sn65_panel_push_cmd_list(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to send MCS (%d)\n", ret);
            goto fail;
        }
        /* Select User Command Set table (CMD1) */
        ret = mipi_dsi_generic_write(dsi, (u8[]){ WRMAUCCTR, 0x00 }, 2);
        if (ret < 0)
            goto fail;

        /* Software reset */
        ret = mipi_dsi_dcs_soft_reset(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to do Software Reset (%d)\n", ret);
            goto fail;
        }

        msleep(100);

        /* Set DSI mode */
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xC2, 0x0B }, 2);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
        /* Set tear ON */
        ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set tear ON (%d)\n", ret);
            goto fail;
        }
        /* Set tear scanline */
        ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x380);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set tear scanline (%d)\n", ret);
            goto fail;
        }
        /* Set pixel format to RGB888 */
        ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x77);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set pixel format (%d)\n", ret);
            goto fail;
        }
        /* Set display brightness */
        ret = mipi_dsi_dcs_set_display_brightness(dsi, 0x20);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set display brightness (%d)\n",
                      ret);
            goto fail;
        }
        /* Exit sleep mode */
        ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to exit sleep mode (%d)\n", ret);
            goto fail;
        }

        ret = mipi_dsi_dcs_set_display_on(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set display ON (%d)\n", ret);
            goto fail;
        }
    }else if(lcd_type == 1 ){ //7 inch
#if 0
        msleep(20);
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0x11,0x00 }, 2);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
        msleep(150);
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xb0,0x00}, 2);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
#if 0
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xd6,0x14,0x08,0x00,0x22,0x00 }, 6);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
#endif
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xb4,0x0c }, 2);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
        //ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xb6,0x3a,0xd3 }, 3);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0x51,0x36 }, 2);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0x53,0x2c }, 2);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0x3a,0x77 }, 2);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
        ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to exit sleep mode (%d)\n", ret);
            goto fail;
        }
        msleep(120);
        //ret = mipi_dsi_generic_write(dsi, (u8[]){ 0x29,0x00 }, 2);
        ret = mipi_dsi_dcs_set_display_on(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
        msleep(10);
        /* reset */
        ret = mipi_dsi_dcs_soft_reset(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
            goto fail;
        }
#endif
       ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to exit sleep mode (%d)\n", ret);
            goto fail;
        }
        msleep(120);
        ret = mipi_dsi_dcs_set_display_on(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to exit sleep mode (%d)\n", ret);
            goto fail;
        }
        msleep(5);
        //ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set tear ON (%d)\n", ret);
            goto fail;
        }

   }else if(lcd_type == 2 ){// 9 inch
        ret = mipi_dsi_generic_write(dsi, (u8[]){ 0x32 }, 0);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set display ON (%d)\n", ret);
            goto fail;
        }
    }else if(lcd_type == 3 ){ //10 inch
        //ret = sn65_panel_push_cmd_list(dsi);
        //ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xb6,0x3a}, 2);
        ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to exit sleep mode (%d)\n", ret);
            goto fail;
        }
        msleep(120);
        ret = mipi_dsi_dcs_set_display_on(dsi);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to exit sleep mode (%d)\n", ret);
            goto fail;
        }
        msleep(5);
        //ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
        if (ret < 0) {
            DRM_DEV_ERROR(dev, "Failed to set tear ON (%d)\n", ret);
            goto fail;
        }
    }
	sn65->prepared = true;

	return 0;

fail:
	if (sn65->reset != NULL)
		gpiod_set_value(sn65->reset, 0);

	return ret;
}

static int sn65_panel_unprepare(struct drm_panel *panel)
{
	struct sn65_panel *sn65 = to_sn65_panel(panel);
	struct mipi_dsi_device *dsi = sn65->dsi;
	struct device *dev = &dsi->dev;

	if (!sn65->prepared)
		return 0;

	DRM_DEV_DEBUG_DRIVER(dev, "\n");

	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
#if 0
	ret = mipi_dsi_dcs_set_display_off(dsi);
	if (ret < 0)
		DRM_DEV_ERROR(dev, "Failed to set display OFF (%d)\n", ret);

	usleep_range(5000, 10000);

	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
	if (ret < 0)
		DRM_DEV_ERROR(dev, "Failed to enter sleep mode (%d)\n", ret);

	usleep_range(10000, 15000);

	if (sn65->reset != NULL) {
		gpiod_set_value(sn65->reset, 0);
		usleep_range(10000, 15000);
	}
#endif
	sn65->prepared = false;

	return 0;
}

static int sn65_panel_enable(struct drm_panel *panel)
{
	struct sn65_panel *sn65 = to_sn65_panel(panel);
	struct device *dev = &sn65->dsi->dev;

    printk("function:%s line:%d ----------- \n",__FUNCTION__,__LINE__);
	if (sn65->enabled)
		return 0;

	DRM_DEV_DEBUG_DRIVER(dev, "\n");

	sn65->backlight->props.power = FB_BLANK_UNBLANK;
	backlight_update_status(sn65->backlight);
	sn65->enabled = true;

	return 0;
}

static int sn65_panel_disable(struct drm_panel *panel)
{
	struct sn65_panel *sn65 = to_sn65_panel(panel);
	struct device *dev = &sn65->dsi->dev;

	if (!sn65->enabled)
		return 0;

	DRM_DEV_DEBUG_DRIVER(dev, "\n");

	sn65->backlight->props.power = FB_BLANK_POWERDOWN;
	backlight_update_status(sn65->backlight);

	sn65->enabled = false;

	return 0;
}

static int sn65_panel_get_modes(struct drm_panel *panel)
{
	struct sn65_panel *sn65 = to_sn65_panel(panel);
	struct device *dev = &sn65->dsi->dev;
	struct drm_connector *connector = panel->connector;
	struct drm_display_mode *mode;
	u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
	u32 *bus_flags = &connector->display_info.bus_flags;
	int ret;

	mode = drm_mode_create(connector->dev);
	if (!mode) {
		DRM_DEV_ERROR(dev, "Failed to create display mode!\n");
		return 0;
	}

	drm_display_mode_from_videomode(&sn65->vm, mode);
	mode->width_mm = sn65->width_mm;
	mode->height_mm = sn65->height_mm;
	connector->display_info.width_mm = sn65->width_mm;
	connector->display_info.height_mm = sn65->height_mm;
	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;

	if (sn65->vm.flags & DISPLAY_FLAGS_DE_HIGH)
		*bus_flags |= DRM_BUS_FLAG_DE_HIGH;
	if (sn65->vm.flags & DISPLAY_FLAGS_DE_LOW)
		*bus_flags |= DRM_BUS_FLAG_DE_LOW;
	if (sn65->vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
		*bus_flags |= DRM_BUS_FLAG_PIXDATA_NEGEDGE;
	if (sn65->vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
		*bus_flags |= DRM_BUS_FLAG_PIXDATA_POSEDGE;

	ret = drm_display_info_set_bus_formats(&connector->display_info,
					       &bus_format, 1);
	if (ret)
		return ret;

	drm_mode_probed_add(panel->connector, mode);

	return 1;
}

static int sn65_bl_get_brightness(struct backlight_device *bl)
{
	struct mipi_dsi_device *dsi = bl_get_data(bl);
	struct sn65_panel *sn65 = mipi_dsi_get_drvdata(dsi);
	struct device *dev = &dsi->dev;
	u16 brightness;

	if (!sn65->prepared)
		return 0;

	DRM_DEV_DEBUG_DRIVER(dev, "\n");

#if 0
	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
	if (ret < 0)
		return ret;

	bl->props.brightness = brightness;
#endif
	return brightness & 0xff;
}

static int sn65_bl_update_status(struct backlight_device *bl)
{
	struct mipi_dsi_device *dsi = bl_get_data(bl);
	struct sn65_panel *sn65 = mipi_dsi_get_drvdata(dsi);
	struct device *dev = &dsi->dev;

	if (!sn65->prepared)
		return 0;

	dev_info(dev, "New brightness: %d\n", bl->props.brightness);

#if 0
	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	ret = mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness);
	if (ret < 0)
		return ret;
#endif
	return 0;
}

static const struct backlight_ops sn65_bl_ops = {
	.update_status = sn65_bl_update_status,
	.get_brightness = sn65_bl_get_brightness,
};

static const struct drm_panel_funcs sn65_panel_funcs = {
	.prepare = sn65_panel_prepare,
	.unprepare = sn65_panel_unprepare,
	.enable = sn65_panel_enable,
	.disable = sn65_panel_disable,
	.get_modes = sn65_panel_get_modes,
};




static int sn65_panel_probe(struct mipi_dsi_device *dsi)
{
	struct device *dev = &dsi->dev;
	struct device_node *np = dev->of_node;
    struct device_node *client_node = NULL;
	struct i2c_client *client_dev;
	struct sn65_panel *panel;
	struct backlight_properties bl_props;
	int ret;

	panel = devm_kzalloc(&dsi->dev, sizeof(*panel), GFP_KERNEL);
	if (!panel)
		return -ENOMEM;

	mipi_dsi_set_drvdata(dsi, panel);

	panel->dsi = dsi;

	dsi->format = MIPI_DSI_FMT_RGB888;
	//dsi->format = MIPI_DSI_FMT_RGB666_PACKED;
	dsi->mode_flags = MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;

	ret = of_property_read_u32(np, "dsi-lanes", &dsi->lanes);
	if (ret < 0) {
		dev_err(dev, "Failed to get dsi-lanes property (%d)\n", ret);
		return ret;
	}
	//ret = of_get_videomode(np, &panel->vm, 0);
	//if (ret < 0)
    if(lcd_type == 0 ){ //7 inch
		videomode_from_timing(&sn65_default_timing, &panel->vm);
    }else if(lcd_type == 1){
		videomode_from_timing(&sn65_7inchmip_timing, &panel->vm);
    }else if(lcd_type == 2){
		videomode_from_timing(&sn65_9inch_timing, &panel->vm);
    }else if(lcd_type == 3){
		videomode_from_timing(&sn65_10inch_timing, &panel->vm);
    }else if(lcd_type == 4){
		videomode_from_timing(&sn65_21inch_timing, &panel->vm);
    }else if(lcd_type == 5){
		videomode_from_timing(&sn65_15inch_timing, &panel->vm);
    }else if(lcd_type == 6){
		videomode_from_timing(&sn65_7inch_amp_timing, &panel->vm);
    }


	of_property_read_u32(np, "panel-width-mm", &panel->width_mm);
	of_property_read_u32(np, "panel-height-mm", &panel->height_mm);

	panel->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);

	if (IS_ERR(panel->reset))
		panel->reset = NULL;
	else
		gpiod_set_value(panel->reset, 0);

    client_node = of_parse_phandle(dev->of_node, "client-device", 0);
	if (!client_node) {
		dev_err(dev, "phandle missing or invalid\n");
	}else{
        client_dev = of_find_i2c_device_by_node(client_node);
        if (!client_dev || !client_dev->dev.driver) {
            dev_err(dev, "failed to find client platform device\n");
        }
        else{
            panel->client = client_dev;
        }
    }

    enable_gpio = of_get_named_gpio(dev->of_node, "device_en", 0);  
    if (gpio_is_valid(enable_gpio)) {  
        devm_gpio_request_one(dev,enable_gpio, GPIOF_OUT_INIT_LOW, "dsi_enable_gpio"); 
	    gpio_set_value(enable_gpio, 0);
    }
    

	memset(&bl_props, 0, sizeof(bl_props));
	bl_props.type = BACKLIGHT_RAW;
	bl_props.brightness = 255;
	bl_props.max_brightness = 255;
#if 1
	struct device_node *backlight;
	backlight = of_parse_phandle(dev->of_node, "backlight", 0);
    if (backlight) {
		panel->backlight = of_find_backlight_by_node(backlight);
		of_node_put(backlight);
	}
#else
	panel->backlight = devm_backlight_device_register(
				dev, dev_name(dev),
				dev, dsi,
				&sn65_bl_ops, &bl_props);
	if (IS_ERR(panel->backlight)) {
		ret = PTR_ERR(panel->backlight);
		dev_err(dev, "Failed to register backlight (%d)\n", ret);
		return ret;
	}
	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
	if (ddc) {
		panel->ddc = of_find_i2c_adapter_by_node(ddc);
		of_node_put(ddc);

		if (!panel->ddc) {
			ret = -EPROBE_DEFER;
		}
	}
#endif


	drm_panel_init(&panel->base);
	panel->base.funcs = &sn65_panel_funcs;
	panel->base.dev = dev;

	ret = drm_panel_add(&panel->base);

	if (ret < 0)
		return ret;

	ret = mipi_dsi_attach(dsi);
	if (ret < 0)
		drm_panel_remove(&panel->base);

	return ret;
}

static int sn65_panel_remove(struct mipi_dsi_device *dsi)
{
	struct sn65_panel *sn65 = mipi_dsi_get_drvdata(dsi);
	struct device *dev = &dsi->dev;
	int ret;

	ret = sn65_panel_disable(&sn65->base);
	if (ret < 0)
		DRM_DEV_ERROR(dev, "Failed to disable panel (%d)\n", ret);

	ret = mipi_dsi_detach(dsi);
	if (ret < 0)
		DRM_DEV_ERROR(dev, "Failed to detach from host (%d)\n",
			ret);

	drm_panel_detach(&sn65->base);

	if (sn65->base.dev)
		drm_panel_remove(&sn65->base);

	return 0;
}

static void sn65_panel_shutdown(struct mipi_dsi_device *dsi)
{
	struct sn65_panel *sn65 = mipi_dsi_get_drvdata(dsi);

	sn65_panel_disable(&sn65->base);
}

static const struct of_device_id sn65_of_match[] = {
	{ .compatible = "ti,panel-sn65dsi8x", },
	{ }
};
MODULE_DEVICE_TABLE(of, sn65_of_match);

static struct mipi_dsi_driver sn65_panel_driver = {
	.driver = {
		.name = "panel-ti-sn65dsi8x",
		.of_match_table = sn65_of_match,
	},
	.probe = sn65_panel_probe,
	.remove = sn65_panel_remove,
	.shutdown = sn65_panel_shutdown,
};
module_mipi_dsi_driver(sn65_panel_driver);

MODULE_AUTHOR("SHENZHEN HMS");
MODULE_DESCRIPTION("TI SN65DSI8X PANEL");
MODULE_LICENSE("GPL v2");