diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
old mode 100644
new mode 100755
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
old mode 100644
new mode 100755
index 3f1b18f..71d429e
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -58,6 +58,7 @@ enum clk_root_index {
 	MXC_IPG_CLK			= 33,
 	AUDIO_AHB_CLK_ROOT		= 34,
 	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
+	MIPI_DSI_ESC_TX_CLK_ROOT =37,
 	DRAM_SEL_CFG			= 48,
 	CORE_SEL_CFG			= 49,
 	DRAM_ALT_CLK_ROOT		= 64,
@@ -671,6 +672,8 @@ int clock_init(void);
 void init_clk_usdhc(u32 index);
 void init_nand_clk(void);
 void init_uart_clk(u32 index);
+void init_mipi_clk(void);
+void show_mipi_clk(void);
 void init_usb_clk(void);
 void init_wdog_clk(void);
 unsigned int mxc_get_clock(enum clk_root_index clk);
diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
old mode 100644
new mode 100755
index d620dc0..656e5eb
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -198,13 +198,12 @@ int main(void)
 	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
 	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
 #endif
-
-#ifdef CONFIG_ARM_SMCCC
-	DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
+#ifdef CONFIG_ARM_SMCCC 
+ 	DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
 	DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
 	DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
 	DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
-#endif
+#endif   
 
 	return 0;
 }
diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S
old mode 100644
new mode 100755
index 0480452..aa63282
--- a/arch/arm/lib/relocate_64.S
+++ b/arch/arm/lib/relocate_64.S
@@ -27,7 +27,8 @@ ENTRY(relocate_code)
 	/*
 	 * Copy u-boot from flash to RAM
 	 */
-	adr	x1, __image_copy_start	/* x1 <- Run &__image_copy_start */
+	adrp	x1, __image_copy_start	/* x1 <- Run &__image_copy_start */
+	add	x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
 	subs	x9, x0, x1		/* x8 <- Run to copy offset */
 	b.eq	relocate_done		/* skip relocation */
 	/*
@@ -43,8 +44,10 @@ ENTRY(relocate_code)
 	ldr	x1, _TEXT_BASE		/* x1 <- Linked &__image_copy_start */
 	subs	x9, x0, x1		/* x9 <- Link to copy offset */
 
-	adr	x1, __image_copy_start	/* x1 <- Run &__image_copy_start */
-	adr	x2, __image_copy_end	/* x2 <- Run &__image_copy_end */
+	adrp	x1, __image_copy_start	/* x1 <- Run &__image_copy_start */
+	add	x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
+	adrp	x2, __image_copy_end	/* x2 <- Run &__image_copy_end */
+	add	x2, x2, :lo12:__image_copy_end	/* x2 <- address bits [11:00] */
 copy_loop:
 	ldp	x10, x11, [x1], #16	/* copy from source address [x1] */
 	stp	x10, x11, [x0], #16	/* copy to   target address [x0] */
@@ -55,8 +58,10 @@ copy_loop:
 	/*
 	 * Fix .rela.dyn relocations
 	 */
-	adr	x2, __rel_dyn_start	/* x2 <- Run &__rel_dyn_start */
-	adr	x3, __rel_dyn_end	/* x3 <- Run &__rel_dyn_end */
+	adrp	x2, __rel_dyn_start	/* x2 <- Run &__rel_dyn_start */
+	add	x2, x2, :lo12:__rel_dyn_start	/* x2 <- address bits [11:00] */
+	adrp	x3, __rel_dyn_end	/* x3 <- Run &__rel_dyn_end */
+	add	x3, x3, :lo12:__rel_dyn_end	/* x3 <- address bits [11:00] */
 fixloop:
 	ldp	x0, x1, [x2], #16	/* (x0,x1) <- (SRC location, fixup) */
 	ldr	x4, [x2], #8		/* x4 <- addend */
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
old mode 100644
new mode 100755
index 33a4d51..d4ff0c6
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/clock_imx8mq.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
@@ -32,6 +33,12 @@ static u32 decode_frac_pll(enum clk_root_src frac_pll)
 		pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
 		pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
 		break;
+	case VIDEO_PLL_CLK:
+		pll_cfg0 = readl(&ana_pll->video_pll_cfg0);
+		pll_cfg1 = readl(&ana_pll->video_pll_cfg1);
+		pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
+		pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
+		break;
 	default:
 		printf("Frac PLL %d not supporte\n", frac_pll);
 		return 0;
@@ -257,6 +264,7 @@ static u32 get_root_src_clk(enum clk_root_src root_src)
 	case OSC_32K_CLK:
 		return 32000;
 	case ARM_PLL_CLK:
+	case VIDEO_PLL_CLK:
 		return decode_frac_pll(root_src);
 	case SYSTEM_PLL1_800M_CLK:
 	case SYSTEM_PLL1_400M_CLK:
@@ -303,7 +311,6 @@ static u32 get_root_clk(enum clk_root_index clock_id)
 		return 0;
 
 	root_src_clk = get_root_src_clk(root_src);
-
 	return root_src_clk / (post_podf + 1) / (pre_podf + 1);
 }
 
@@ -347,7 +354,29 @@ unsigned int mxc_get_clock(enum clk_root_index clk)
 		val = val & 0x3;
 		return get_root_clk(AHB_CLK_ROOT) / (val + 1);
 	}
-
+	if (clk == MIPI_DSI_PHY_REF_CLK_ROOT)
+		return get_root_clk(MIPI_DSI_PHY_REF_CLK_ROOT);
+	if (clk == MIPI_DSI_ESC_RX_CLK_ROOT)
+	{
+		return get_root_clk(MIPI_DSI_ESC_RX_CLK_ROOT);
+	}
+	if (clk == OLD_MIPI_DSI_ESC_RX_ROOT)
+	{
+		return get_root_clk(OLD_MIPI_DSI_ESC_RX_ROOT);
+	}
+	if (clk == MIPI_DSI_ESC_TX_CLK_ROOT)
+	{
+		return get_root_clk(MIPI_DSI_ESC_TX_CLK_ROOT);
+	}
+	if (clk == MIPI_DSI_CORE_CLK_ROOT)
+	{
+		return get_root_clk(MIPI_DSI_CORE_CLK_ROOT);
+	}
+	if (clk == LCDIF_PIXEL_CLK_ROOT)
+	{
+		return get_root_clk(LCDIF_PIXEL_CLK_ROOT);
+	}
+	
 	return get_root_clk(clk);
 }
 
@@ -356,15 +385,61 @@ u32 imx_get_uartclk(void)
 	return mxc_get_clock(UART1_CLK_ROOT);
 }
 
+// add video_pll to imx8mq
+int set_video_pll(void)
+ {
+ 	void __iomem *pll_cfg0, __iomem *pll_cfg1;
+ 	u32 val_cfg0, val_cfg1;
+ 	int ret;
+	int freq;
+ 
+ 	pll_cfg0 = &ana_pll->video_pll_cfg0;
+ 	pll_cfg1 = &ana_pll->video_pll_cfg1;
+ 
+ 	val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(54);
+ 	val_cfg0 = FRAC_PLL_LOCK_MASK |FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_27M |
+ 		FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_REFCLK_DIV_VAL(4) |
+ 		FRAC_PLL_OUTPUT_DIV_VAL(0);
+ 
+ 	/* bypass the clock */
+ 	setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
+ 	/* Set the value */
+	writel(val_cfg1, pll_cfg1);
+ 	writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
+ 	val_cfg0 = readl(pll_cfg0);
+ 	/* unbypass the clock */
+ 	clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
+	/*set from kernel video_pll1*/
+ 	ret = readl_poll_timeout(pll_cfg0, val_cfg0,
+ 				 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
+ 	if (ret)
+ 	printf("%s timeout\n", __func__);
+	return 0;
+ }
+ // add dsi clocks
+ void imx8mq_dsi_set_clocks(void)
+ {
+ 	/* Set Clocks */
+	/* Video PLL Out parent clock for LCDIF clock & DSI PHY reference clock */
+ 	set_video_pll();
+	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV10));	       
+ 	clock_set_target_val(MIPI_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV44));	//PARENT: VIDEO_PLL1/CLK_ROOT_POST_DIV42
+ 	clock_set_target_val(MIPI_DSI_CORE_CLK_ROOT,CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));											//PARENT: SYS_PLL1
+ 	clock_set_target_val(MIPI_DSI_ESC_TX_CLK_ROOT,CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));											//PARENT: SYS_PLL1
+ }
+ 
+//set LCDIF_clk
 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 {
 	/*
-	 * LCDIF_PIXEL_CLK: select 800MHz root clock,
+	 * LCDIF_PIXEL_CLK: select video_pll1_clk root clock,
 	 * select pre divider 8, output is 100 MHz
+	 * 
 	 */
-	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
-			     CLK_ROOT_SOURCE_SEL(4) |
-			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
+	/* Video PLL Out parent clock for LCDIF clock & DSI PHY reference clock */
+ 	set_video_pll();
+	//PARENT: VIDEO_PLL1
+ 	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV10));	       
 }
 
 void init_wdog_clk(void)
@@ -575,7 +650,7 @@ void dram_enable_bypass(enum dram_bypassclk_val clk_val)
 	int i;
 	struct dram_bypass_clk_setting *config;
 
-	for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
+	for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i ++) {
 		if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
 			break;
 	}
@@ -893,6 +968,19 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 	printf("USDHC1         %8d MHz\n", freq / 1000000);
 	freq = mxc_get_clock(QSPI_CLK_ROOT);
 	printf("QSPI           %8d MHz\n", freq / 1000000);
+	//add mipi
+	freq = decode_frac_pll(VIDEO_PLL_CLK);
+	printf("VIDEO_PLL_CLK    %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MIPI_DSI_PHY_REF_CLK_ROOT);
+	printf("MIPI_DSI_PHY_REF_CLK_ROOT      %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MIPI_DSI_ESC_RX_CLK_ROOT);
+	printf("MIPI_DSI_ESC_RX_CLK_ROOT       %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MIPI_DSI_ESC_TX_CLK_ROOT);
+	printf("MIPI_DSI_ESC_TX_CLK_ROOT       %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MIPI_DSI_CORE_CLK_ROOT);
+	printf("MIPI_DSI_CORE_CLK_ROOT         %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(LCDIF_PIXEL_CLK_ROOT);
+	printf("LCDIF_PIXEL_CLK_ROOT        %8d MHz\n", freq / 1000000);
 	return 0;
 }
 
diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
old mode 100644
new mode 100755
diff --git a/arch/arm/mach-imx/imx8m/video_common.c b/arch/arm/mach-imx/imx8m/video_common.c
old mode 100644
new mode 100755
index e2c7c01..186657d
--- a/arch/arm/mach-imx/imx8m/video_common.c
+++ b/arch/arm/mach-imx/imx8m/video_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019 NXP 
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -62,7 +62,7 @@ GraphicDevice *imx8m_get_gd(void)
 
 #define REG_BASE_ADDR 0x32e00000UL
 
-/*#define DEBUGREG*/
+#define DEBUGREG
 #ifdef DEBUGREG
 #define reg32_write(addr, val) \
 do { \
@@ -676,16 +676,15 @@ void *video_hw_init(void)
 	}
 
 	imx8m_create_color_bar((void *)((uint64_t) fb), &gmode);
-
-	ret = imx8_hdmi_enable(encoding, &gmode); /* may change gmode */
+	
+	ret = imx8_hdmi_enable(encoding, &gmode); //may change gmode 
 	if (ret) {
 		printf("HDMI enable failed!\n");
 		return NULL;
 	}
-
+	
 	/* start dccs */
 	imx8m_display_init((uint64_t) fb, encoding, &gmode);
-
 	panel.frameAdrs = (ulong) fb;
 	debug("IMXDCSS display started ...\n");
 
diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c
old mode 100644
new mode 100755
index 0f94641..f9c1386
--- a/arch/arm/mach-imx/video.c
+++ b/arch/arm/mach-imx/video.c
@@ -43,10 +43,10 @@ int board_video_skip(void)
 #elif defined(CONFIG_VIDEO_IMXDPUV1)
 		ret = imxdpuv1_fb_init(&displays[i].mode, displays[i].bus,
 					displays[i].pixfmt);
-#elif defined(CONFIG_VIDEO_IMXDCSS)
+#elif defined(CONFIG_VIDEO_IMXDCSS)   //Dcss
 		ret = imx8m_fb_init(&displays[i].mode, displays[i].bus,
 					displays[i].pixfmt);
-#elif defined(CONFIG_VIDEO_MXS)
+#elif defined(CONFIG_VIDEO_MXS)  //Lcdif 
 		ret = mxs_lcd_panel_setup(displays[i].mode,
 					displays[i].pixfmt,
 				    displays[i].bus);
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
old mode 100644
new mode 100755
index 1d2b912..a092393
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -30,6 +30,11 @@
 #include "../common/pfuze.h"
 #include <usb.h>
 #include <dwc3-uboot.h>
+#include <mipi_dsi_panel.h>
+#include <imx8mq_mipi_dsi_bridge.h>
+#include <imx8mq_mipi_dsi.h>
+#include <mipi_dsi_northwest.h>
+#include <imx_mipi_dsi_bridge.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -383,7 +388,57 @@ struct display_info_t const displays[] = {{
 } };
 size_t display_count = ARRAY_SIZE(displays);
 
-#endif /* CONFIG_VIDEO_IMXDCSS */
+#endif // CONFIG_VIDEO_IMXDCSS 
+
+struct mipi_dsi_client_dev rm67191_dev = {
+	.channel = 0,
+	.lanes	= 4,   //4 lanes for mipi
+	.format	= MIPI_DSI_FMT_RGB888,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+		MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
+};
+#define MIPI_RESET_GPIO IMX_GPIO_NR(5, 6)
+int board_mipi_panel_en(void)
+{
+	gpio_request(MIPI_RESET_GPIO, "DSI EN");
+    gpio_direction_output(MIPI_RESET_GPIO, 0);
+    mdelay(100);
+    gpio_direction_output(MIPI_RESET_GPIO, 1);
+}
+void do_enable_rm67191(struct display_info_t const *dev)
+{
+	// DSI_EN setup
+	mipi_dsi_northwest_setup(MIPI_PHY_BASE_ADDR,SRC_IPS_BASE_ADDR);  // called in mipi_dsi_northwest.c
+	rm67191_init();
+	rm67191_dev.name = displays[0].mode.name;
+	imx_mipi_dsi_bridge_attach(&rm67191_dev);   /*attach rm67191 device */
+}
+
+#if defined (CONFIG_VIDEO_MXS)
+struct display_info_t const displays[] = {{
+	.bus	= LCDIF_BASE_ADDR, /* Unused */
+	.addr	= 0, /* Unused */
+	.pixfmt	= 24,
+	.detect	= NULL,
+	.enable	= do_enable_rm67191,
+	.mode	= {
+		.name           = "RM67191_OLED", 
+		.refresh        = 60,
+		.xres           = 1080,
+		.yres           = 1920,
+		.pixclock       = 7575, /* 132000  kHz */
+		.left_margin    = 34,
+		.right_margin   = 20,
+		.upper_margin   = 4,
+		.lower_margin   = 10,
+		.hsync_len      = 2,
+		.vsync_len      = 2,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+	}
+}};
+size_t display_count = ARRAY_SIZE(displays);
+#endif
 
 /* return hard code board id for imx8m_ref */
 #if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
diff --git a/common/lcd.c b/common/lcd.c
index 07417ea..a851286 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -160,7 +160,6 @@ int drv_lcd_init(void)
 	lcddev.puts  = lcd_stub_puts;		/* 'puts' function */
 
 	rc = stdio_register(&lcddev);
-
 	return (rc == 0) ? 1 : rc;
 }
 
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
old mode 100644
new mode 100755
index 372ab57..5bbad08
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -36,6 +36,9 @@ CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_MIXEL_MIPI_DSI=y
+CONFIG_VIDEO_MXS=y
+CONFIG_RM67191=y
 CONFIG_CMD_PMIC=y
 CONFIG_NXP_TMU=y
 CONFIG_DM_THERMAL=y
@@ -46,7 +49,6 @@ CONFIG_USB_TCPC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
-CONFIG_VIDEO_IMX8_HDMI=y
 CONFIG_USB_GADGET=y
 CONFIG_FASTBOOT=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 57d21d6..9cb80b5 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -555,6 +555,18 @@ config IMX_NORTHWEST_MIPI_DSI
 	depends on VIDEO && MX7ULP
 	help
 	  Support for i.MX7ULP MIPI DSI controller.
+config RM67191
+	bool "RM67191 mipi to panel IC"
+	default y
+config DRM_NWL_DSI
+	bool "MIPI DSI bridge driver for i.MX8 processors"
+
+config DRM_IMX_NWL_DSI
+	bool "Support for Northwest Logic MIPI DSI displays"
+	select DRM_NWL_DSI
+	help
+	  Choose this to enable the internal NWL MIPI DSI controller
+	  found on i.MX8 processors.
 
 config IMX_SEC_MIPI_DSI
 	bool "i.MX Samsung's MIPI DSI"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
old mode 100644
new mode 100755
index d0d484c..d939d58
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -69,7 +69,8 @@ obj-$(CONFIG_IMX_MIPI_DSI_BRIDGE) += imx_mipi_dsi_bridge.o
 obj-$(CONFIG_HX8363) += hx8363_wvga.o
 obj-$(CONFIG_RM67191) += rm67191.o
 obj-$(CONFIG_RM68200) += rm68200.o
-
+obj-$(CONFIG_DRM_IMX_NWL_DSI) += nwl_dsi-imx.o
+obj-$(CONFIG_DRM_NWL_DSI) += nwl-dsi.o
 obj-y += bridge/
 obj-y += sunxi/
 obj-y += imx/
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
old mode 100644
new mode 100755
index 917a5a9..99b678a
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -64,13 +64,13 @@
  *				Uses the macros CURSOR_SET and
  *				CURSOR_OFF.
  */
-
 #include <common.h>
 #include <fdtdec.h>
 #include <version.h>
 #include <malloc.h>
 #include <video.h>
 #include <linux/compiler.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_VIDEO_MXS)
 #define VIDEO_FB_16BPP_WORD_SWAP
@@ -1383,7 +1383,6 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
 
 	debug("Display-bmp: %ld x %ld  with %d colors\n",
 	      width, height, colors);
-
 	if (compression != BMP_BI_RGB
 #ifdef CONFIG_VIDEO_BMP_RLE8
 	    && compression != BMP_BI_RLE8
@@ -1691,6 +1690,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
 static int video_logo_xpos;
 static int video_logo_ypos;
 
+
 static void plot_logo_or_black(void *screen, int x, int y, int black);
 
 static void logo_plot(void *screen, int x, int y)
@@ -1721,14 +1721,14 @@ U_BOOT_CMD(
 
 static void plot_logo_or_black(void *screen, int x, int y, int black)
 {
-
 	int xcount, i;
 	int skip = VIDEO_LINE_LEN - VIDEO_LOGO_WIDTH * VIDEO_PIXEL_SIZE;
 	int ycount = video_logo_height;
 	unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
 	unsigned char *source;
 	unsigned char *dest;
-
+	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(ulong)(LCDIF_BASE_ADDR);
+	unsigned int ret = 0;
 #ifdef CONFIG_SPLASH_SCREEN_ALIGN
 	if (x == BMP_ALIGN_CENTER)
 		x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2);
@@ -1745,7 +1745,6 @@ static void plot_logo_or_black(void *screen, int x, int y, int black)
 
 #ifdef CONFIG_VIDEO_BMP_LOGO
 	source = bmp_logo_bitmap;
-
 	/* Allocate temporary space for computing colormap */
 	logo_red = malloc(BMP_LOGO_COLORS);
 	logo_green = malloc(BMP_LOGO_COLORS);
@@ -1833,6 +1832,10 @@ static void plot_logo_or_black(void *screen, int x, int y, int black)
 #endif
 				break;
 			}
+			ret = readl(&regs->hw_lcdif_ctrl1);
+			if(ret & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ) {
+				writel(LCDIF_CTRL1_CUR_FRAME_DONE_IRQ, &regs->hw_lcdif_ctrl1_clr);
+			}
 			source++;
 			dest += VIDEO_PIXEL_SIZE;
 		}
@@ -1871,9 +1874,7 @@ static void *video_logo(void)
 		}
 	}
 #endif /* CONFIG_SPLASH_SCREEN */
-
 	logo_plot(video_fb_address, video_logo_xpos, video_logo_ypos);
-
 #ifdef CONFIG_SPLASH_SCREEN_ALIGN
 	/*
 	 * when using splashpos for video_logo, skip any info
@@ -2015,7 +2016,6 @@ void video_clear(void)
 static int cfg_video_init(void)
 {
 	unsigned char color8;
-
 	pGD = video_hw_init();
 	if (pGD == NULL)
 		return -1;
@@ -2133,9 +2133,8 @@ int drv_video_init(void)
 	struct stdio_dev console_dev;
 	bool have_keyboard;
 	bool __maybe_unused keyboard_ok = false;
-
 	/* Check if video initialization should be skipped */
-	if (board_video_skip())
+	if(board_video_skip())
 		return 0;
 
 	/* Init video chip - returns with framebuffer cleared */
diff --git a/drivers/video/imx_mipi_dsi_bridge.c b/drivers/video/imx_mipi_dsi_bridge.c
old mode 100644
new mode 100755
diff --git a/drivers/video/mipi_dsi_northwest.c b/drivers/video/mipi_dsi_northwest.c
old mode 100644
new mode 100755
index 7817aa4..c054f48
--- a/drivers/video/mipi_dsi_northwest.c
+++ b/drivers/video/mipi_dsi_northwest.c
@@ -180,7 +180,10 @@ int __weak board_mipi_panel_reset(void)
 {
 	return 0;
 }
-
+int __weak board_mipi_panel_en(void)
+{
+	return 0;
+}
 /**
  * board_mipi_panel_shutdown - Shut down the mipi dsi panel
  *
@@ -220,6 +223,7 @@ static void mipi_dsi_set_mode(struct mipi_dsi_northwest_info *mipi_dsi,
 static int mipi_dsi_dphy_init(struct mipi_dsi_northwest_info *mipi_dsi)
 {
 	uint32_t time_out = 100;
+	uint32_t CN, CM, CO;
 	uint32_t lock;
 	uint32_t req_bit_clk;
 	uint32_t bpp;
@@ -240,7 +244,7 @@ static int mipi_dsi_dphy_init(struct mipi_dsi_northwest_info *mipi_dsi)
 	*  We need meet clk_byte_freq >= dpi_pclk_freq * DPI_pixel_size / ( 8 * (cfg_num_lanes + 1))
 	*/
 
-	req_bit_clk = PS2KHZ(mipi_dsi->mode.pixclock) * 1000U;
+	req_bit_clk = (mipi_dsi->mode.pixclock) * 1000U;
 	req_bit_clk = req_bit_clk * bpp;
 
 	switch (mipi_dsi->dsi_panel_dev->lanes) {
@@ -431,17 +435,36 @@ static int mipi_dsi_dphy_init(struct mipi_dsi_northwest_info *mipi_dsi)
 		div.cn = cn_map_table[denominator - 1];
 	}
 
-	debug("cn 0x%x, cm 0x%x, co 0x%x\n", div.cn, div.cm, div.co);
-
-	writel(div.cn, mipi_dsi->mmio_base + DPHY_CN);
-	writel(div.cm, mipi_dsi->mmio_base + DPHY_CM);
-	writel(div.co, mipi_dsi->mmio_base + DPHY_CO);
+	
 
-	writel(0x25, mipi_dsi->mmio_base + DPHY_TST);
+	//writel(div.cn, mipi_dsi->mmio_base + DPHY_CN);
+	//writel(div.cm, mipi_dsi->mmio_base + DPHY_CM);
+	//writel(div.co, mipi_dsi->mmio_base + DPHY_CO);
+	writel(0x1, mipi_dsi->mmio_base + DPHY_PD_PLL);
+	udelay(1000);
+	writel(0x0, mipi_dsi->mmio_base + DPHY_M_PRG_HS_PREPARE);
+	writel(0x0, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_PREPARE);
+	writel(0x6, mipi_dsi->mmio_base + DPHY_M_PRG_HS_ZERO);
+	writel(0x18, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_ZERO);
+	writel(0x9, mipi_dsi->mmio_base + DPHY_M_PRG_HS_TRAIL);
+	writel(0x9, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_TRAIL);
+	writel(0x25, mipi_dsi->mmio_base + DPHY_TST); //
+	writel(0x7, mipi_dsi->mmio_base + DPHY_RXHS_SETTLE); // 0x30a00348 add, not in RM
+
+	writel(0x10, mipi_dsi->mmio_base + DPHY_CN); //CN=10,3
+	writel(0x98, mipi_dsi->mmio_base + DPHY_CM); //CM=98,88
+	writel(0x0, mipi_dsi->mmio_base + DPHY_CO); //CO=0,1
+	writel(0x0, mipi_dsi->mmio_base + DPHY_LOCK_BYP);
+	writel(0x1, mipi_dsi->mmio_base + DPHY_RTERM_SEL); //
+	writel(0x0, mipi_dsi->mmio_base + DPHY_AUTO_PD_EN);
+	writel(0x2, mipi_dsi->mmio_base + DPHY_RXLPRP);
+	writel(0x2, mipi_dsi->mmio_base + DPHY_RXCDRP);
+	writel(0x0,  mipi_dsi->mmio_base + DPHY_BYPASS_PLL); // 0x30a0034c add, not in RM
+	
 	writel(0x0, mipi_dsi->mmio_base + DPHY_PD_PLL);
 
 	while (!(lock = readl(mipi_dsi->mmio_base + DPHY_LOCK))) {
-		udelay(10);
+		udelay(1000);
 		time_out--;
 		if (time_out == 0) {
 			printf("cannot get the dphy lock = 0x%x\n", lock);
@@ -449,22 +472,11 @@ static int mipi_dsi_dphy_init(struct mipi_dsi_northwest_info *mipi_dsi)
 		}
 	}
 	debug("%s: dphy lock = 0x%x\n", __func__, lock);
-
-	writel(0x0, mipi_dsi->mmio_base + DPHY_LOCK_BYP);
-	writel(0x1, mipi_dsi->mmio_base + DPHY_RTERM_SEL);
-	writel(0x0, mipi_dsi->mmio_base + DPHY_AUTO_PD_EN);
-	writel(0x1, mipi_dsi->mmio_base + DPHY_RXLPRP);
-	writel(0x1, mipi_dsi->mmio_base + DPHY_RXCDRP);
-	writel(0x0, mipi_dsi->mmio_base + DPHY_M_PRG_HS_PREPARE);
-	writel(0x0, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_PREPARE);
-	writel(0x9, mipi_dsi->mmio_base + DPHY_M_PRG_HS_ZERO);
-	writel(0x20, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_ZERO);
-	writel(0x5, mipi_dsi->mmio_base + DPHY_M_PRG_HS_TRAIL);
-	writel(0x5, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_TRAIL);
 	writel(0x0, mipi_dsi->mmio_base + DPHY_PD_DPHY);
-
 	setbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_PLL_EN);
 	return 0;
+	
+
 }
 
 static int mipi_dsi_host_init(struct mipi_dsi_northwest_info *mipi_dsi)
@@ -478,22 +490,27 @@ static int mipi_dsi_host_init(struct mipi_dsi_northwest_info *mipi_dsi)
 	case 2:
 		lane_num = 0x1;
 		break;
+	case 3:
+		lane_num = 0x2;
+	break;
+	case 4:
+		lane_num = 0x3;
+	break;
 	default:
 		/* Invalid lane num */
 		return -EINVAL;
 	}
-
 	writel(lane_num, mipi_dsi->mmio_base + HOST_CFG_NUM_LANES);
-	writel(0x1, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK);
+	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK);
 	writel(0x1, mipi_dsi->mmio_base + HOST_CFG_T_PRE);
-	writel(52, mipi_dsi->mmio_base + HOST_CFG_T_POST);
-	writel(13, mipi_dsi->mmio_base + HOST_CFG_TX_GAP);
-	writel(0x1, mipi_dsi->mmio_base + HOST_CFG_AUTOINSERT_EOTP);
-	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_EXTRA_CMDS_AFTER_EOTP);
+	writel(0x25, mipi_dsi->mmio_base + HOST_CFG_T_POST);
+	writel(0xa, mipi_dsi->mmio_base + HOST_CFG_TX_GAP);
+	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_AUTOINSERT_EOTP);
+	writel(0x1, mipi_dsi->mmio_base + HOST_CFG_EXTRA_CMDS_AFTER_EOTP);
 	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_HTX_TO_COUNT);
 	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_LRX_H_TO_COUNT);
 	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_BTA_H_TO_COUNT);
-	writel(0x3A98, mipi_dsi->mmio_base + HOST_CFG_TWAKEUP);
+	writel(0x4e20, mipi_dsi->mmio_base + HOST_CFG_TWAKEUP);
 
 	return 0;
 }
@@ -524,12 +541,11 @@ static int mipi_dsi_dpi_init(struct mipi_dsi_northwest_info *mipi_dsi)
 	writel(color_coding, mipi_dsi->mmio_base + DPI_INTERFACE_COLOR_CODING);
 	writel(pixel_fmt, mipi_dsi->mmio_base + DPI_PIXEL_FORMAT);
 	writel(0x0, mipi_dsi->mmio_base + DPI_VSYNC_POLARITY);
-	writel(0x0, mipi_dsi->mmio_base + DPI_HSYNC_POLARITY);
-	writel(0x2, mipi_dsi->mmio_base + DPI_VIDEO_MODE);
-
-	writel(mode->right_margin * (bpp >> 3), mipi_dsi->mmio_base + DPI_HFP);
-	writel(mode->left_margin * (bpp >> 3), mipi_dsi->mmio_base + DPI_HBP);
-	writel(mode->hsync_len * (bpp >> 3), mipi_dsi->mmio_base + DPI_HSA);
+	writel(0x0, mipi_dsi->mmio_base + DPI_HSYNC_POLARITY); 
+	writel(0x0, mipi_dsi->mmio_base + DPI_VIDEO_MODE);  //ref kernel
+	writel(mode->right_margin /** (bpp >> 3)*/, mipi_dsi->mmio_base + DPI_HFP);
+	writel(mode->left_margin /** (bpp >> 3)*/, mipi_dsi->mmio_base + DPI_HBP);
+	writel(mode->hsync_len /** (bpp >> 3)*/, mipi_dsi->mmio_base + DPI_HSA);
 	writel(0x0, mipi_dsi->mmio_base + DPI_ENABLE_MULT_PKTS);
 
 	writel(mode->upper_margin, mipi_dsi->mmio_base + DPI_VBP);
@@ -537,7 +553,7 @@ static int mipi_dsi_dpi_init(struct mipi_dsi_northwest_info *mipi_dsi)
 	writel(0x1, mipi_dsi->mmio_base + DPI_BLLP_MODE);
 	writel(0x0, mipi_dsi->mmio_base + DPI_USE_NULL_PKT_BLLP);
 
-	writel(mode->yres - 1, mipi_dsi->mmio_base + DPI_VACTIVE);
+	writel(mode->yres, mipi_dsi->mmio_base + DPI_VACTIVE);
 
 	writel(0x0, mipi_dsi->mmio_base + DPI_VC);
 
@@ -547,7 +563,7 @@ static int mipi_dsi_dpi_init(struct mipi_dsi_northwest_info *mipi_dsi)
 static void mipi_dsi_init_interrupt(struct mipi_dsi_northwest_info *mipi_dsi)
 {
 	/* disable all the irqs */
-	writel(0xffffffff, mipi_dsi->mmio_base + HOST_IRQ_MASK);
+	writel(0x7FFFFF75, mipi_dsi->mmio_base + HOST_IRQ_MASK);
 	writel(0x7, mipi_dsi->mmio_base + HOST_IRQ_MASK2);
 }
 
@@ -573,21 +589,17 @@ static int mipi_display_enter_sleep(struct mipi_dsi_northwest_info *mipi_dsi)
 
 static int mipi_dsi_enable(struct mipi_dsi_northwest_info *mipi_dsi)
 {
-	int ret;
+	int ret;	
+	/* Enable MIPI PGC power domain */
+	writel(0x0000ffff, 0x303a00ec);
+	writel(1, 0x303a00f8);
 
 	/* Assert resets */
-	/* escape domain */
-	clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_ESC_N);
-
-	/* byte domain */
-	clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_BYTE_N);
-
-	/* dpi domain */
-	clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_DPI_N);
-
+	setbits_le32((mipi_dsi->sim_base + SRC_MIPIPHY_RCR),
+		     BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) );
+	mdelay(20);
 	/* Enable mipi relevant clocks */
-	enable_mipi_dsi_clk(1);
-
+	imx8mq_dsi_set_clocks();
 	ret = mipi_dsi_dphy_init(mipi_dsi);
 	if (ret < 0)
 		return ret;
@@ -599,28 +611,8 @@ static int mipi_dsi_enable(struct mipi_dsi_northwest_info *mipi_dsi)
 	ret = mipi_dsi_dpi_init(mipi_dsi);
 	if (ret < 0)
 		return ret;
-
-	/* Deassert resets */
-	/* escape domain */
-	setbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_ESC_N);
-
-	/* byte domain */
-	setbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_BYTE_N);
-
-	/* dpi domain */
-	setbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_DPI_N);
-
-	/* display_en */
-	clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_SD);
-
-	/* normal cm */
-	clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_CM);
-	mdelay(20);
-
 	/* Reset mipi panel */
-	board_mipi_panel_reset();
-	mdelay(60);
-
+	board_mipi_panel_en();
 	/* Disable all interrupts, since we use polling */
 	mipi_dsi_init_interrupt(mipi_dsi);
 
@@ -635,7 +627,7 @@ static int mipi_dsi_enable(struct mipi_dsi_northwest_info *mipi_dsi)
 
 	/* Enter the HS mode for video stream */
 	mipi_dsi_set_mode(mipi_dsi, DSI_HS_MODE);
-
+	mdelay(100);
 	return 0;
 }
 
@@ -731,7 +723,6 @@ static int mipi_dsi_pkt_write(struct mipi_dsi_northwest_info *mipi_dsi,
 	const uint8_t *data = (const uint8_t *)buf;
 
 	debug("mipi_dsi_pkt_write data_type 0x%x, buf 0x%x, len %u\n", data_type, (u32)buf, len);
-
 	if (len == 0)
 		/* handle generic long write command */
 		mipi_dsi_wr_tx_header(mipi_dsi, data_type, data[0], data[1], DSI_LP_MODE, 0);
@@ -786,20 +777,7 @@ static void mipi_dsi_shutdown(struct mipi_dsi_northwest_info *mipi_dsi)
 
 	writel(0x1, mipi_dsi->mmio_base + DPHY_PD_PLL);
 	writel(0x1, mipi_dsi->mmio_base + DPHY_PD_DPHY);
-
-	enable_mipi_dsi_clk(0);
-
-	/* Assert resets */
-	/* escape domain */
-	clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_ESC_N);
-
-	/* byte domain */
-	clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_BYTE_N);
-
-	/* dpi domain */
-	clrbits_le32(mipi_dsi->sim_base + SIM_SOPT1CFG, DSI_RST_DPI_N);
 }
-
 /* Attach a LCD panel device */
 int mipi_dsi_northwest_bridge_attach(struct mipi_dsi_bridge_driver *bridge_driver, struct mipi_dsi_client_dev *panel_dev)
 {
@@ -869,7 +847,6 @@ static int mipi_dsi_northwest_bridge_enable(struct mipi_dsi_bridge_driver *bridg
 	mipi_dsi_enable(dsi_info);
 
 	dsi_info->enabled = 1;
-
 	return 0;
 }
 
diff --git a/drivers/video/mipi_dsi_northwest_regs.h b/drivers/video/mipi_dsi_northwest_regs.h
old mode 100644
new mode 100755
index 6493403..20c8813
--- a/drivers/video/mipi_dsi_northwest_regs.h
+++ b/drivers/video/mipi_dsi_northwest_regs.h
@@ -22,6 +22,8 @@
 #define DSI_SD			0x200
 #define DSI_CM			0x100
 #define DSI_PLL_EN		0x80
+#define SRC_MIPIPHY_RCR			0x28
+#define SRC_DISP_RCR			0x34
 
 /* dphy */
 #define DPHY_PD_DPHY			0x300
@@ -42,7 +44,10 @@
 #define DPHY_AUTO_PD_EN			0x33c
 #define DPHY_RXLPRP			0x340
 #define DPHY_RXCDRP			0x344
-
+#define DPHY_RXHS_SETTLE		0x348
+#define DPHY_BYPASS_PLL			0x34c
+#define DPHY_RXHS_SETTLE		0x348
+#define DPHY_BYPASS_PLL			0x34c
 /* host */
 #define HOST_CFG_NUM_LANES		0x0
 #define HOST_CFG_NONCONTINUOUS_CLK	0x4
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
old mode 100644
new mode 100755
index 838c037..b07eb21
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -12,7 +12,7 @@
 #include <malloc.h>
 #include <video_fb.h>
 
-#include <asm/arch/imx-regs.h>
+#include <asm/arch-imx8m/imx-regs-imx8mq.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <linux/errno.h>
@@ -34,6 +34,11 @@
 #include <imx_mipi_dsi_bridge.h>
 #endif
 
+#ifdef CONFIG_DRM_NWL_DSI
+#include <imx8mq_mipi_dsi_bridge.h>
+#include <imx8mq_mipi_dsi.h>
+#endif
+
 #define	PS2KHZ(ps)	(1000000000UL / (ps))
 
 static GraphicDevice panel;
@@ -94,8 +99,10 @@ static void mxs_lcd_init(GraphicDevice *panel,
 	uint32_t word_len = 0, bus_width = 0;
 	uint8_t valid_data = 0;
 
-	/* Kick in the LCDIF clock */
-	mxs_set_lcdclk(panel->isaBase, PS2KHZ(mode->pixclock));
+	/* Kick in the LCDIF clock 
+	mxs_set_lcdclk() is defined in clock_imx8mq.c
+	*/
+	// mxs_set_lcdclk(panel->isaBase, PS2KHZ(mode->pixclock));
 
 	/* Restart the LCDIF block */
 	mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
@@ -127,9 +134,9 @@ static void mxs_lcd_init(GraphicDevice *panel,
 		LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
 		&regs->hw_lcdif_ctrl);
 
-	writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
+	 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
 		&regs->hw_lcdif_ctrl1);
-
+	writel(0x00070300,&regs->hw_lcdif_ctrl1);
 #ifdef CONFIG_IMX_MIPI_DSI_BRIDGE
 	writel(LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16, &regs->hw_lcdif_ctrl2);
 #endif
@@ -138,32 +145,33 @@ static void mxs_lcd_init(GraphicDevice *panel,
 
 	writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
 		&regs->hw_lcdif_transfer_count);
-
-#ifdef CONFIG_IMX_SEC_MIPI_DSI
+#ifdef CONFIG_IMX_SEC_MIPI_DSI  //samsang mipi for imx8mm
 	writel(LCDIF_VDCTRL0_ENABLE_PRESENT |
 		LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 		LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 		mode->vsync_len, &regs->hw_lcdif_vdctrl0);
 #else
-	writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
+	writel(LCDIF_VDCTRL0_ENABLE_PRESENT  | LCDIF_VDCTRL0_ENABLE_POL |
 		LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 		LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 		mode->vsync_len, &regs->hw_lcdif_vdctrl0);
+	writel(0x1c300002,&regs->hw_lcdif_vdctrl0); 
+
 #endif
 	writel(mode->upper_margin + mode->lower_margin +
 		mode->vsync_len + mode->yres,
 		&regs->hw_lcdif_vdctrl1);
 	writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 		(mode->left_margin + mode->right_margin +
-		mode->hsync_len + mode->xres),
+		mode->hsync_len + mode->xres ),
 		&regs->hw_lcdif_vdctrl2);
+
 	writel(((mode->left_margin + mode->hsync_len) <<
 		LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 		(mode->upper_margin + mode->vsync_len),
 		&regs->hw_lcdif_vdctrl3);
 	writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
 		&regs->hw_lcdif_vdctrl4);
-
 	writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
 	writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
 
@@ -174,7 +182,6 @@ static void mxs_lcd_init(GraphicDevice *panel,
 	/* Sync signals ON */
 	setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 #endif
-
 	/* FIFO cleared */
 	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 
@@ -197,7 +204,9 @@ void lcdif_power_down(void)
 #ifdef CONFIG_IMX_MIPI_DSI_BRIDGE
 	imx_mipi_dsi_bridge_disable();
 #endif
-
+#ifdef CONFIG_DRM_NWL_DSI
+	imx8mq_mipi_dsi_bridge_disable();
+#endif
 	writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
 	writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
 	writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
@@ -216,9 +225,6 @@ void *video_hw_init(void)
 	char *penv;
 	void *fb;
 	struct ctfb_res_modes mode;
-
-	puts("Video: ");
-
 	if (!setup) {
 
 		/* Suck display configuration from "videomode" variable */
@@ -295,14 +301,14 @@ void *video_hw_init(void)
 	memset(fb, 0, panel.memSize);
 
 	panel.frameAdrs = (ulong)fb;
-
-	printf("%s\n", panel.modeIdent);
+	puts("Video: ");
+	printf("%s\n", panel.modeIdent);  //Video: 1080x1920x24
 
 #ifdef CONFIG_IMX_MIPI_DSI_BRIDGE
-	imx_mipi_dsi_bridge_mode_set(&fbmode);
+	//for imx6ull, 8mq ,call mipi_dsi_enable in mipi_dsi_northwest.c
+	imx_mipi_dsi_bridge_mode_set(&fbmode);  
 	imx_mipi_dsi_bridge_enable();
 #endif
-
 	/* Start framebuffer */
 	mxs_lcd_init(&panel, &mode, bpp);
 
@@ -333,6 +339,5 @@ void *video_hw_init(void)
 	/* Entry for GIS */
 	mxc_enable_gis();
 #endif
-
 	return (void *)&panel;
 }
diff --git a/drivers/video/rm67191.c b/drivers/video/rm67191.c
old mode 100644
new mode 100755
index 4ef907f..9c049ed
--- a/drivers/video/rm67191.c
+++ b/drivers/video/rm67191.c
@@ -1,4 +1,4 @@
-/*
+/* 
  * Copyright 2018 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -170,7 +170,7 @@ static u8 color_format_from_dsi_format(enum mipi_dsi_pixel_format format)
 	case MIPI_DSI_FMT_RGB666:
 	case MIPI_DSI_FMT_RGB666_PACKED:
 		return 0x66;
-	case MIPI_DSI_FMT_RGB888:
+	case MIPI_DSI_FMT_RGB888:  
 		return 0x77;
 	default:
 		return 0x77; /* for backward compatibility */
@@ -302,7 +302,7 @@ int rm67191_lcd_setup(struct mipi_dsi_client_dev *panel_dev)
 		return -EIO;
 	}
 
-	/* Set tear ON */
+	/* Set tear ON  */
 	ret = mipi_dsi_dcs_write(MIPI_DCS_SET_TEAR_ON, (u8[]){ 0x0 }, 1);
 	if (ret < 0) {
 		printf("Failed to set tear ON (%d)\n", ret);
@@ -347,7 +347,6 @@ int rm67191_lcd_setup(struct mipi_dsi_client_dev *panel_dev)
 		printf("Failed to set display ON (%d)\n", ret);
 		return -EIO;
 	}
-
 	return 0;
 }
 
@@ -359,4 +358,6 @@ static struct mipi_dsi_client_driver rm67191_drv = {
 void rm67191_init(void)
 {
 	imx_mipi_dsi_bridge_add_client_driver(&rm67191_drv);
+	
 }
+ 
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index 68d0643..02aafa3 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -389,7 +389,7 @@
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_RM67191
+#define CONFIG_RM67191 
 #endif
 
 #define CONFIG_OF_SYSTEM_SETUP
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
old mode 100644
new mode 100755
index 6cff7fe..22b8314
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -294,14 +294,17 @@
 
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IMXDCSS
+#define CONFIG_VIDEO_MXS
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_IMX_NORTHWEST_MIPI_DSI
+#define CONFIG_IMX_MIPI_DSI_BRIDGE
 #endif
 
 #if defined(CONFIG_ANDROID_SUPPORT)
diff --git a/tools/logos/freescale.bmp b/tools/logos/freescale.bmp
old mode 100644
new mode 100755
