/*
 * Copyright 2019 EMBEST
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/ {
	backlight: backlight {
			compatible = "pwm-backlight";
			pwms = <&pwm1 0 40000 0>;
			brightness-levels = <0 8 32 64 96 128 160 192 224 255>;
			default-brightness-level = <8>;
			power-supply = <&reg_mipi_en>;
			status = "disabled";
	};

	regulators {
		reg_mipi_en: regulator-mipi-vcc {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_baklight_en>;
			regulator-name = "mipi_vcc_en";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			enable-active-high;
			startup-delay-us = <160000>;
			gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>;
		};
	};
};

&iomuxc {
	imx8mq-evk {
		pinctrl_mipi_dsi_en: mipi_dsi_en {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x16  	/* DSI_EN */
				//MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16  	/* DSI_EN */
			    MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13		0x19	/* DSI_TS_nINT */
				>;
		};	
	
		pinctrl_baklight_en: lcdbaklight_en {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16  	/* DSI_EN */
				>;
		};	

		pinctrl_ts_ft5426: ft5426_pinsgrp {
			fsl,pins = <
				//MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13		0x19  /* DSI_TS_nINT */
				MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x19  /* DSI_TS_RST  */
			>;
		};

		pinctrl_pwm1: pwm1_grp {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT		0x06
			>;
		};
	};
};

&irqsteer {
	status = "okay";
};

&lcdif {
	status = "disabled";
	max-memory-bandwidth = <221257728>; /* 720x1280-32@60.02 */

	assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
			  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
			  <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
			  <&clk IMX8MQ_VIDEO_PLL1>;
	assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
				 <&clk IMX8MQ_VIDEO_PLL1>,
				 <&clk IMX8MQ_CLK_27M>;
	assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>;
};

&dcss {
	status = "disabled";

	clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
		 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
		 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
		 <&clk IMX8MQ_CLK_DC_PIXEL>,
		 <&clk IMX8MQ_CLK_DISP_DTRC>;
	clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
	assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
					  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
					  <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
					  <&clk IMX8MQ_CLK_DISP_AXI>,
					  <&clk IMX8MQ_CLK_DISP_RTRM>;
	assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
							 <&clk IMX8MQ_VIDEO_PLL1>,
							 <&clk IMX8MQ_CLK_27M>,
							 <&clk IMX8MQ_SYS1_PLL_800M>,
							 <&clk IMX8MQ_SYS1_PLL_800M>;
	assigned-clock-rates = <600000000>, <0>, <0>,
						   <800000000>,
						   <400000000>;
};

&mipi_dsi {
	status = "disabled";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			mipi_dsi_in: endpoint {
				remote-endpoint = <&dcss_lcdif_dsi>;
			};
		};
	};
};

&dphy {
	status = "okay";
};

&pwm1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm1>;
        status = "disabled";
};

&i2c4 {
	status = "okay";

	ft5426: ft5426_ts@38 {
		compatible = "focaltech,fts";
		reg = <0x38>;
		pinctrl-0 = <&pinctrl_ts_ft5426>;

		interrupt-parent = <&gpio3>;
		interrupts = <13 2>;
		focaltech,reset-gpio = <&gpio1 4 0x01>;
		focaltech,irq-gpio = <&gpio3 13 0x02>;
		focaltech,max-touch-number = <10>;
		focaltech,panel-type = <0x54260002>; /* _FT5426 */
		focaltech,display-coords =  <0 0 720 1280>;
		focaltech,have-key;
		focaltech,key-number = <3>;
		focaltech,keys = <139 102 158>;
		focaltech,key-y-coord = <2000>;
		focaltech,key-x-coords = <200 600 800>;
		status = "disabled";
	};
};