#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <asm/uaccess.h>

#include <linux/platform_device.h>
#include <linux/errno.h>
#include <linux/power_supply.h>
#include <linux/mutex.h>
#include <linux/delay.h>

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <asm/io.h>
//#include "common.h"
//#include "hardware.h"



#define IRQN_EPIT1  56
#define IRQN_EPIT2  57

#define EPIT1_BASE_ADDR  (0x020D0000UL)
#define EPIT2_BASE_ADDR  (0x020D4000UL)

#define EPIT1_IOMEM_LEN  (0x1024UL)


#define EPITCR		0x00 /* Control register */
#define EPITSR		0x04  /* Status register  */
#define EPITLR		0x08 /* Load register */
#define EPITCMPR	0x0c /* Compare register */
#define EPITCNR		0x10   /* Counter register */


#define EPIT_CR_EN                (1 << 0)
#define EPIT_CR_ENMOD             (1 << 1)
#define EPIT_CR_OCIEN             (1 << 2)
#define EPIT_CR_RLD               (1 << 3)
#define EPIT_CR_PRESCALAR_MASK    (0x00000FFF << 4)
#define EPIT_CR_PRESCALAR_DIV(v)  (((v - 1) & 0x00000FFF) << 4)
#define EPIT_CR_SWR               (1 << 16)
#define EPIT_CR_IOVW              (1 << 17)
#define EPIT_CR_DBGEN             (1 << 18)
#define EPIT_CR_WAITEN            (1 << 19)
#define EPIT_CR_STOPEN            (1 << 21)
#define EPIT_CR_OM_MASK           (3 << 22)
#define EPIT_CR_OM_DIS            (0 << 22)
#define EPIT_CR_OM_TOGGLE         (1 << 22)
#define EPIT_CR_OM_CLEAR          (2 << 22)
#define EPIT_CR_OM_SET            (3 << 22)
#define EPIT_CR_CLKSRC_MASK       (3 << 24)
#define EPIT_CR_CLKSRC_OFF        (0 << 24)
#define EPIT_CR_CLKSRC_PERIPH     (1 << 24)
#define EPIT_CR_CLKSRC_HI_REF     (2 << 24)
#define EPIT_CR_CLKSRC_LO_REF     (3 << 24)

#define EPIT_SR_OCIF  (1 << 0)


//void hwtimer_start_epit1(void);	

static void __iomem * epit1base_addr;



static irqreturn_t epit1_intr_handler(int irq, void* dev_id)
{
	printk(KERN_NOTICE "EPIT1 Interrupt (irq %d) !\n", irq);
	//disable_epit_irq1();
	printk("[HWTIMER][%s] #### Restart hwtimer- 1 ####\n", __func__);
	//hwtimer_start_epit1(); // restart timer
	return IRQ_HANDLED;
}


static int __init epit_init(void)
{
	int res;
	unsigned long tcmp;
	epit1base_addr = ioremap(EPIT1_BASE_ADDR, EPIT1_IOMEM_LEN);
	if (epit1base_addr == NULL) {
		printk(KERN_ERR "EPIT1 : ioremap() failure!\n");
		return -EIO;
	}
	printk(KERN_DEBUG "EPIT1 base address: %lx \n",
	                  (unsigned long)epit1base_addr);

		/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */
	//__raw_writel(0x0, epit1base_addr + EPITCR);	// p.1215
	//__raw_writel(0xffffffff, epit1base_addr + EPITLR);
	//__raw_writel(EPIT_CR_EN | EPIT_CR_CLKSRC_LO_REF | EPIT_CR_WAITEN | EPIT_CR_STOPEN /*| EPITCR_IOVW*/,epit1base_addr + EPITCR);
//
	//tcmp = __raw_readl(epit1base_addr + EPITCNR);
	//__raw_writel(-320000, epit1base_addr + EPITCMPR); //10 sec
	
	res = request_irq(IRQN_EPIT1,&epit1_intr_handler,0, "EPIT_1_Interrupt", NULL);

	printk(KERN_ERR "EPIT1 request_irq return %d\n",res);

	if (res != 0) {
		printk(KERN_ERR "EPIT1 : request_irq() failure!\n");
		return -EIO;
	}
	
	printk(KERN_NOTICE "EPIT module initialised.\n");
	return 0;
}


static void __exit epit_exit(void)
{
	
	free_irq(IRQN_EPIT1,(void *)(epit1_intr_handler));
	printk(KERN_NOTICE "EPIT module exited.\n");
}

module_init(epit_init);
module_exit(epit_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("-");
MODULE_DESCRIPTION("EPIT i.MX6 solo x");