gpc: gpc@20dc000 {
	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
	reg = <0x020dc000 0x4000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
			 <0 90 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&intc>;
	clocks = <&clks IMX6QDL_CLK_IPG>;
	clock-names = "ipg";
	fsl,cpu_pupscr_sw2iso = <0xf>;
	fsl,cpu_pupscr_sw = <0xf>;
	fsl,cpu_pdnscr_iso2sw = <0x1>;
	fsl,cpu_pdnscr_iso = <0x1>;
	fsl,ldo-bypass = <0>; /* No ldo-bypass */
	fsl,wdog-reset = <1>; /* watchdog select of reset source */
	pu-supply = <&reg_pu>;

	pgc {
		#address-cells = <1>;
		#size-cells = <0>;

		power-domain@0 {
			reg = <0>;
			#power-domain-cells = <0>;
		};
		pd_pu: power-domain@1 {
			reg = <1>;
			#power-domain-cells = <0>;
			power-supply = <&reg_pu>;
			clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
					 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
					 <&clks IMX6QDL_CLK_GPU2D_CORE>,
					 <&clks IMX6QDL_CLK_GPU2D_AXI>,
					 <&clks IMX6QDL_CLK_OPENVG_AXI>,
					 <&clks IMX6QDL_CLK_VPU_AXI>;
		};
	};
};


gpu_3d: gpu@130000 {
	compatible = "vivante,gc";
	reg = <0x00130000 0x4000>;
	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
		 <&clks IMX6QDL_CLK_GPU3D_CORE>,
		 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
	clock-names = "bus", "core", "shader";
	power-domains = <&pd_pu>;
	#cooling-cells = <2>;
	status = "disabled";
};

gpu_2d: gpu@134000 {
	compatible = "vivante,gc";
	reg = <0x00134000 0x4000>;
	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
		 <&clks IMX6QDL_CLK_GPU2D_CORE>;
	clock-names = "bus", "core";
	power-domains = <&pd_pu>;
	#cooling-cells = <2>;
	status = "disabled";
};

gpu_vg: gpu@2204000 {
	compatible = "vivante,gc";
	reg = <0x02204000 0x4000>;
	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
		 <&clks IMX6QDL_CLK_GPU2D_CORE>;
	clock-names = "bus", "core";
	power-domains = <&pd_pu>;
	#cooling-cells = <2>;
	status = "disabled";
};

gpu: gpu@00130000 {
	compatible = "fsl,imx6q-gpu";
	reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
		<0x02204000 0x4000>, <0x10000000 0x0>,
		<0x0 0x8000000>;
	reg-names = "iobase_3d", "iobase_2d",
		"iobase_vg", "phys_baseaddr",
		"contiguous_mem";
	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
		<0 10 IRQ_TYPE_LEVEL_HIGH>,
		<0 11 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "irq_3d", "irq_2d", "irq_vg";
	clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>,
		<&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>,
		<&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>;
	clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
		"gpu3d_axi_clk", "gpu2d_clk",
		"gpu3d_clk", "gpu3d_shader_clk";
	resets = <&src 0>, <&src 3>, <&src 3>;
	reset-names = "gpu3d", "gpu2d", "gpuvg";
	power-domains = <&pd_pu>;
	contiguous-size-percentage = <12>;
};