diff -Naur -x '.*' u-boot-2009.08.orig/board/karo/tx53-1331/config.mk u-boot-2009.08/board/karo/tx53-1331/config.mk
--- u-boot-2009.08.orig/board/karo/tx53-1331/config.mk	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-2009.08/board/karo/tx53-1331/config.mk	2012-05-14 19:10:10.000000000 +0200
@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x77800000
diff -Naur -x '.*' u-boot-2009.08.orig/board/karo/tx53-1331/flash_header.S u-boot-2009.08/board/karo/tx53-1331/flash_header.S
--- u-boot-2009.08.orig/board/karo/tx53-1331/flash_header.S	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-2009.08/board/karo/tx53-1331/flash_header.S	2012-08-09 15:03:46.000000000 +0200
@@ -0,0 +1,428 @@
+/*
+* This code is mainly based on the hal_platform_setup.h provided by Ka-Ro with RedBoot.
+* It has been adopted to fit the needs for U-Boot and supporting the TX53-1331 module 
+* from Ka-Ro electronics GmbH.
+* (C) Copyright 2012 Thomas Poms <hwsw.development@gmail.com>
+*/   
+
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+#include <asm/sizes.h>
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "FLASH_HEADER_OFFSET not defined."
+#endif
+
+#if !defined(PHYS_SDRAM_1_SIZE) || !defined(PHYS_SDRAM_1)
+#error "PHYS_SDRAM_1_SIZE or PHYS_SDRAM_1 not defined."
+#endif
+
+#if defined(PHYS_SDRAM_2) && !defined(PHYS_SDRAM_2_SIZE)
+#error "PHYS_SDRAM_2_SIZE not defined."
+#endif
+
+
+#define SDRAM_SIZE     (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+
+#define SDRAM_CLK CONFIG_SYS_PLL2_FREQ
+
+
+#define CPU_2_BE_32(l)			\
+	((((l) << 24) & 0xFF000000) |	\
+	(((l) << 8) & 0x00FF0000) |	\
+	(((l) >> 8) & 0x0000FF00) |	\
+	(((l) >> 24) & 0x000000FF))
+
+#define MXC_DCD_ITEM(addr, val)		\
+	.word CPU_2_BE_32(addr)	;	\
+	.word CPU_2_BE_32(val)
+
+#define MXC_DCD_CMD_SZ_BYTE		1
+#define MXC_DCD_CMD_SZ_SHORT		2
+#define MXC_DCD_CMD_SZ_WORD		4
+#define MXC_DCD_CMD_FLAG_WRITE		0x0
+#define MXC_DCD_CMD_FLAG_CLR		0x2
+#define MXC_DCD_CMD_FLAG_SET		0x3
+#define MXC_DCD_CMD(type, flags, next)	\
+	.word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define NS_TO_CK(ns)	(((ns) * SDRAM_CLK + 999) / 1000)
+
+	.macro		CK_VAL,	name, clks, offs, max
+	.iflt		\clks - \offs
+	.set		\name, 0
+	.else
+	.ifle		\clks - \offs - \max
+	.set		\name, \clks - \offs
+	.endif
+	.endif
+	.endm
+
+	.macro		NS_VAL,	name, ns, offs, max
+	.iflt		\ns - \offs
+	.set		\name, 0
+	.else
+	CK_VAL		\name, NS_TO_CK(\ns), \offs, \max
+	.endif
+	.endm
+
+	.macro		CK_MAX, name, ck1, ck2, offs, max
+	.ifgt		\ck1 - \ck2
+	CK_VAL		\name, \ck1, \offs, \max
+	.else
+	CK_VAL		\name, \ck2, \offs, \max
+	.endif
+	.endm
+
+#define SDRAM_TYPE_DDR2 2
+#define SDRAM_TYPE_DDR3 3
+
+#define ESDMISC_DDR_TYPE_DDR3		0
+#define ESDMISC_DDR_TYPE_LPDDR2		1
+#define ESDMISC_DDR_TYPE_DDR2		2
+
+#define ESDOR_CLK_PERIOD		15625	/* base clock for ESDOR values 15.625uS */
+
+#if CONFIG_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2
+# error "SDRAM_TYPE_DDR2 not supported"
+#elif CONFIG_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR3
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > SZ_512M
+#define BANK_ADDR_BITS			2
+#else
+#define BANK_ADDR_BITS			1
+#endif
+#define SDRAM_BURST_LENGTH		8
+#define RALAT				5
+#define WALAT				1
+#define ADDR_MIRROR			0
+#define DDR_TYPE			ESDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* ESDCFG0 0x0c */
+NS_VAL	tRFC,	160, 1, 255		/* clks - 1 (0..255) */
+CK_MAX	tXS,	tRFC + 1 + NS_TO_CK(10), 5, 1, 255	/* clks - 1 (0..255) tRFC + 10 */
+CK_MAX	tXP,	3, NS_TO_CK(6), 1, 7	/* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX	tXPDLL, NS_TO_CK(24), 2, 1, 15		/* clks - 1 (0..15) */
+NS_VAL	tFAW,	45, 1, 31		/* clks - 1 (0..31) */
+CK_VAL	tCL,	9, 3, 8			/* clks - 3 (0..8) CAS Latency */
+
+/* ESDCFG1 0x10 */
+NS_VAL	tRCD,	14, 1, 7		/* clks - 1 (0..7) */
+NS_VAL	tRP,	14, 1, 7		/* clks - 1 (0..7) */
+NS_VAL	tRC,	50, 1, 31		/* clks - 1 (0..31) */
+NS_VAL	tRAS,	36, 1, 31		/* clks - 1 (0..31) */
+CK_VAL	tRPA,	0, 0, 1			/* clks     (0..1) */
+NS_VAL	tWR,	15, 1, 15		/* clks - 1 (0..15) */
+CK_VAL	tMRD,	4, 1, 15		/* clks - 1 (0..15) */
+CK_VAL	tCWL,	7, 2, 6			/* clks - 2 (0..6) */
+
+/* ESDCFG2 0x14 */
+CK_VAL	tDLLK,	512, 1, 511		/* clks - 1 (0..511) */
+CK_MAX	tRTP,	4, NS_TO_CK(8), 1, 7	/* clks - 1 (0..7) */
+CK_MAX	tWTR,	4, NS_TO_CK(8), 1, 7	/* clks - 1 (0..7) */
+CK_MAX	tRRD,	4, NS_TO_CK(8), 1, 7	/* clks - 1 (0..7) */
+
+/* ESDOR 0x30 */
+CK_MAX	tXPR,	NS_TO_CK(160 + 10), 5, 1, 255 /* max(tRFC + 10, 5CK) */
+
+#define tSDE_RST			((200000 + (ESDOR_CLK_PERIOD - 1)) / ESDOR_CLK_PERIOD)
+#define tRST_CKE			((500000 + (ESDOR_CLK_PERIOD - 1)) / ESDOR_CLK_PERIOD)
+
+#define ROW_ADDR_BITS			14
+#define COL_ADDR_BITS			10
+
+	.iflt	tWR - 7
+	.set	ESDSCR_MRS_VAL, (0x8000 | (3 << 4) | \
+				(((tWR - 3) << 9) | \
+				(((tCL + 3) - 4) << 4)) << 16)
+	.else
+	.set	ESDSCR_MRS_VAL, (0x8000 | (3 << 4) | \
+				((((tWR + 1) / 2) << 9) | \
+				(((tCL + 3) - 4) << 4)) << 16)
+	.endif
+
+#else
+#error Unsupported SDRAM type selected
+#endif
+
+#define ESDCFG0_VAL	(			\
+	((tRFC) << 24) |			\
+	((tXS) << 16) |				\
+	((tXP) << 13) |				\
+	((tXPDLL) << 9) |			\
+	((tFAW) << 4) |				\
+	((tCL) << 0))				\
+
+#define ESDCFG1_VAL	(			\
+	((tRCD) << 29) |			\
+	((tRP) << 26) |				\
+	((tRC) << 21) |				\
+	((tRAS) << 16) |			\
+	((tRPA) << 15) |			\
+	((tWR) << 9) |				\
+	((tMRD) << 5) |				\
+	((tCWL) << 0))				\
+
+#define ESDCFG2_VAL	(			\
+	((tDLLK) << 16) |			\
+	((tRTP) << 6) |				\
+	((tWTR) << 3) |				\
+	((tRRD) << 0))
+
+#define BL				(SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+#define ESDCTL_VAL			(((ROW_ADDR_BITS - 11) << 24) | \
+					((COL_ADDR_BITS - 9) << 20) | \
+					(BL << 19) | \
+					(1 << 16) | /* SDRAM bus width */ \
+					((-1) << (32 - BANK_ADDR_BITS)))
+
+#define ESDMISC_VAL			((1 << 12) | \
+					(0x3 << 9) | \
+					(RALAT << 6) | \
+					(WALAT << 16) | \
+					(ADDR_MIRROR << 19) | \
+					(DDR_TYPE << 3))
+
+#define ESDOR_VAL		((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+
+.section ".text.flasheader", "x"
+	b	_start
+/* Informationen to the FCB can be found on p. 495 @ i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2, 12/2011 */
+/* on device power the boot ROM will start searching for the firmware configuration block (FCB) */
+	.word	0x20424346	/* "FCB " marker */
+	.word	0x01	/* FCB version number */
+	.org	0x68
+	.word	0x0	/* primary image starting page number */
+	.word	0x0	/* secondary image starting page number */
+	.word	0x6b
+	.word	0x6b
+	.word	0x0	/* DBBT start page (0 == NO DBBT) */
+	.word	0	/* Bad block marker offset in main area (unused) */
+	.org	0xac
+	.word	0	/* BI Swap disabled */
+	.word	0	/* Bad Block marker offset in spare area */
+#if 1
+	.word	0
+tRFC_VAL:
+	.byte	tRFC
+tXS_VAL:
+	.byte	tXS
+tXP_VAL:
+	.byte	tXP
+tXPDLL_VAL:
+	.byte	tXPDLL
+tFAW_VAL:
+	.byte	tFAW
+tCL_VAL:
+	.byte	tCL
+tRCD_VAL:
+	.byte	tRCD
+tRP_VAL:
+	.byte	tRP
+tRC_VAL:
+	.byte	tRC
+tRAS_VAL:
+	.byte	tRAS
+tRPA_VAL:
+	.byte	tRPA
+tWR_VAL:
+	.byte	tWR
+tMRD_VAL:
+	.byte	tMRD
+tCWL_VAL:
+	.byte	tCWL
+tDLLK_VAL:
+	.byte	tDLLK
+tRTP_VAL:
+	.byte	tRTP
+tWTR_VAL:
+	.byte	tWTR
+tRRD_VAL:
+	.byte	tRRD
+tXPR_VAL:
+	.byte	tXPR
+tSDE_RST_VAL:
+	.byte	tSDE_RST
+tRST_CKE_VAL:
+	.byte	tRST_CKE
+	.align	2
+W_ESDCTL_VAL:
+	.word	ESDCTL_VAL
+W_ESDMISC_VAL:
+	.word	ESDMISC_VAL
+W_ESDCFG0_VAL:
+	.word	ESDCFG0_VAL
+W_ESDCFG1_VAL:
+	.word	ESDCFG1_VAL
+W_ESDCFG2_VAL:
+	.word	ESDCFG2_VAL
+W_ESDOR_VAL:
+	.word	ESDOR_VAL
+W_ESDSCR_MRS_VAL:
+	.word	ESDSCR_MRS_VAL
+#endif
+#if 0
+#undef ESDCFG0_VAL
+#undef ESDCFG1_VAL
+#undef ESDMISC_VAL
+
+#define ESDCFG0_VAL 0x9f5152e3
+#define ESDCFG1_VAL 0xb68e8a63
+#define ESDMISC_VAL 0x00011740
+W_ESDMISC_VAL_FSL:
+	.word	ESDMISC_VAL
+W_ESDCFG0_VAL_FSL:
+	.word	ESDCFG0_VAL
+W_ESDCFG1_VAL_FSL:
+	.word	ESDCFG1_VAL
+#endif
+	.org	0x400
+ivt_header:
+	.word	CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+	.long	_start
+	.long	0x0
+dcd_ptr:
+	.long	dcd_hdr
+boot_data_ptr:
+	.word	boot_data
+self_ptr:
+	.word	ivt_header
+app_code_csf:
+	.word	0x0
+	.word	0x0
+boot_data:
+	.long	TEXT_BASE
+image_len:
+	.long	_end - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin:
+	.word	0
+ivt_end:
+
+#define DCD_VERSION	0x40
+
+dcd_hdr:
+	.word CPU_2_BE_32((0xd2 << 24) |
+	((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+	MXC_DCD_CMD(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
+	/* disable all irrelevant clocks */
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcc0fff)
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR1, 0x000fffc3)
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR2, 0x033c0000)
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR3, 0x00000000)
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR4, 0x00000000)
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR5, 0x00fff033)
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR6, 0x0f00030f)
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR7, 0xfff00000)
+	MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CMEOR, 0x00000000)
+
+    MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x174, 0x00000011)	/* EIM_D18 => GPIO2[20] STK5-LED */
+
+	MXC_DCD_ITEM(0x63fd800c, 0x00000000)	/* M4IF: MUX NFC signals on WEIM */
+
+   
+    MXC_DCD_ITEM(0x53fa8554, 0x00300000)
+    MXC_DCD_ITEM(0x53fa8558, 0x00f00000)
+    MXC_DCD_ITEM(0x53fa8560, 0x00300000)
+    MXC_DCD_ITEM(0x53fa8564, 0x003000c0)
+    MXC_DCD_ITEM(0x53fa8568, 0x00f00000)
+    MXC_DCD_ITEM(0x53fa8570, 0x00300000)
+    MXC_DCD_ITEM(0x53fa8574, 0x00300000)
+    MXC_DCD_ITEM(0x53fa8578, 0x00300000)
+    MXC_DCD_ITEM(0x53fa857c, 0x00f000c0)
+    MXC_DCD_ITEM(0x53fa8580, 0x003000c0)
+    MXC_DCD_ITEM(0x53fa8584, 0x00300000)
+    MXC_DCD_ITEM(0x53fa8588, 0x00300000)
+    MXC_DCD_ITEM(0x53fa8590, 0x00f00000)
+    MXC_DCD_ITEM(0x53fa8594, 0x00300000)
+    MXC_DCD_ITEM(0x53fa86f0, 0x00300000)
+    MXC_DCD_ITEM(0x53fa86f4, 0x00000000)
+    MXC_DCD_ITEM(0x53fa86fc, 0x00000000)
+    MXC_DCD_ITEM(0x53fa8714, 0x00000000)
+    MXC_DCD_ITEM(0x53fa8718, 0x00300000)
+    MXC_DCD_ITEM(0x53fa871c, 0x00300000)
+    MXC_DCD_ITEM(0x53fa8720, 0x00300000)
+    MXC_DCD_ITEM(0x53fa8724, 0x00000000)
+    MXC_DCD_ITEM(0x53fa8728, 0x00300000)
+    MXC_DCD_ITEM(0x53fa872c, 0x00300000)
+    
+    MXC_DCD_ITEM(0x63fd9088, 0x35343535)
+    MXC_DCD_ITEM(0x63fd9090, 0x4d444c44)
+    MXC_DCD_ITEM(0x63fd907c, 0x01370138)
+    MXC_DCD_ITEM(0x63fd9080, 0x013b013c)
+    
+    MXC_DCD_ITEM(0x63fd9018, 0x00011740)
+    MXC_DCD_ITEM(0x63fd9000, 0xc3190000)
+    MXC_DCD_ITEM(0x63fd900c, 0x9f5152e3)
+    MXC_DCD_ITEM(0x63fd9010, 0xb68e8a63)
+    MXC_DCD_ITEM(0x63fd9014, 0x01ff00db)
+    
+    MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
+    MXC_DCD_ITEM(0x63fd9030, 0x009f0e21)
+    MXC_DCD_ITEM(0x63fd9008, 0x12273030)
+    MXC_DCD_ITEM(0x63fd9004, 0x0002002d)
+    # MR0 - CS0
+    MXC_DCD_ITEM(0x63fd901c, 0x00008032)
+    MXC_DCD_ITEM(0x63fd901c, 0x00008033)
+    MXC_DCD_ITEM(0x63fd901c, 0x00028031)
+    MXC_DCD_ITEM(0x63fd901c, 0x092080b0)
+    MXC_DCD_ITEM(0x63fd901c, 0x04008040)
+#if CONFIG_NR_DRAM_BANKS > 1   
+    # MR0 - CS1
+    MXC_DCD_ITEM(0x63fd901c, 0x0000803a)
+    MXC_DCD_ITEM(0x63fd901c, 0x0000803b)
+    MXC_DCD_ITEM(0x63fd901c, 0x00028039)
+    MXC_DCD_ITEM(0x63fd901c, 0x09208138)
+#endif
+    
+    MXC_DCD_ITEM(0x63fd901c, 0x04008048)
+    
+    MXC_DCD_ITEM(0x63fd9020, 0x00005800)
+    MXC_DCD_ITEM(0x63fd9040, 0x04b80003)
+    MXC_DCD_ITEM(0x63fd9058, 0x00011117)
+    MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+   
+
+	MXC_DCD_ITEM(0x53fa8004, 0x00194005)	@ set LDO to 1.3V
+
+	/* setup NFC pads */
+	/* MUX_SEL */
+	MXC_DCD_ITEM(0x53fa819c, 0x00000000)	@ EIM_DA0
+	MXC_DCD_ITEM(0x53fa81a0, 0x00000000)	@ EIM_DA1
+	MXC_DCD_ITEM(0x53fa81a4, 0x00000000)	@ EIM_DA2
+	MXC_DCD_ITEM(0x53fa81a8, 0x00000000)	@ EIM_DA3
+	MXC_DCD_ITEM(0x53fa81ac, 0x00000000)	@ EIM_DA4
+	MXC_DCD_ITEM(0x53fa81b0, 0x00000000)	@ EIM_DA5
+	MXC_DCD_ITEM(0x53fa81b4, 0x00000000)	@ EIM_DA6
+	MXC_DCD_ITEM(0x53fa81b8, 0x00000000)	@ EIM_DA7
+	MXC_DCD_ITEM(0x53fa81dc, 0x00000000)	@ WE_B
+	MXC_DCD_ITEM(0x53fa81e0, 0x00000000)	@ RE_B
+	MXC_DCD_ITEM(0x53fa8228, 0x00000000)	@ CLE
+	MXC_DCD_ITEM(0x53fa822c, 0x00000000)	@ ALE
+	MXC_DCD_ITEM(0x53fa8230, 0x00000000)	@ WP_B
+	MXC_DCD_ITEM(0x53fa8234, 0x00000000)	@ RB0
+	MXC_DCD_ITEM(0x53fa8238, 0x00000000)	@ CS0
+	/* PAD_CTL */
+	MXC_DCD_ITEM(0x53fa84ec, 0x000000e4)	@ EIM_DA0
+	MXC_DCD_ITEM(0x53fa84f0, 0x000000e4)	@ EIM_DA1
+	MXC_DCD_ITEM(0x53fa84f4, 0x000000e4)	@ EIM_DA2
+	MXC_DCD_ITEM(0x53fa84f8, 0x000000e4)	@ EIM_DA3
+	MXC_DCD_ITEM(0x53fa84fc, 0x000000e4)	@ EIM_DA4
+	MXC_DCD_ITEM(0x53fa8500, 0x000000e4)	@ EIM_DA5
+	MXC_DCD_ITEM(0x53fa8504, 0x000000e4)	@ EIM_DA6
+	MXC_DCD_ITEM(0x53fa8508, 0x000000e4)	@ EIM_DA7
+	MXC_DCD_ITEM(0x53fa852c, 0x00000004)	@ NANDF_WE_B
+	MXC_DCD_ITEM(0x53fa8530, 0x00000004)	@ NANDF_RE_B
+	MXC_DCD_ITEM(0x53fa85a0, 0x00000004)	@ NANDF_CLE_B
+	MXC_DCD_ITEM(0x53fa85a4, 0x00000004)	@ NANDF_ALE_B
+	MXC_DCD_ITEM(0x53fa85a8, 0x000000e4)	@ NANDF_WE_B
+	MXC_DCD_ITEM(0x53fa85ac, 0x000000e4)	@ NANDF_RB0
+	MXC_DCD_ITEM(0x53fa85b0, 0x00000004)	@ NANDF_CS0
+dcd_end:
+
+#endif
diff -Naur -x '.*' u-boot-2009.08.orig/board/karo/tx53-1331/lowlevel_init.S u-boot-2009.08/board/karo/tx53-1331/lowlevel_init.S
--- u-boot-2009.08.orig/board/karo/tx53-1331/lowlevel_init.S	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-2009.08/board/karo/tx53-1331/lowlevel_init.S	2012-08-09 15:01:07.000000000 +0200
@@ -0,0 +1,458 @@
+/*
+* This code is mainly based on the hal_platform_setup.h provided by Ka-Ro with RedBoot.
+* It has been adopted to fit the needs for U-Boot and supporting the TX53-1331 module 
+* from Ka-Ro electronics GmbH.
+* (C) Copyright 2012 Thomas Poms <hwsw.development@gmail.com>
+*/   
+
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+/* FIXME: is CPU_CLK defined anywhere else??? */
+#define CPU_CLK		CONFIG_SYS_HZ
+#define SDRAM_CLK	CONFIG_SYS_PLL2_FREQ
+
+//use GPIO2_20 for LED debugging --> FIXME: use the appropriate LED on the AIS Display platform
+#define DEBUG_LED_BIT			20
+#define LED_GPIO_BASE			GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET			0x174
+#define LED_MUX_MODE			0x11
+
+#ifdef DEBUG
+#define LED_ON				bl	led_on
+#define LED_OFF				bl	led_off
+
+	.macro	LED_BLINK,val
+	ldr	r8, =\val
+	bl	led_blink
+	.endm
+	.macro	DELAY,ms
+	ldr	r10, =\ms
+	bl	delay
+	.endm
+
+#else
+#define LED_ON
+#define LED_OFF
+
+	.macro	LED_BLINK,val
+	.endm
+	.macro  DELAY,ms
+	.endm
+#endif
+
+#define AIPS1_CTRL_BASE_ADDR		AIPS1_BASE_ADDR
+#define AIPS2_CTRL_BASE_ADDR		AIPS2_BASE_ADDR
+#define PLATFORM_BASE_ADDR			ARM_BASE_ADDR
+
+#define MMU_CP               p15      // Co-processor ID
+#define MMU_Control          c1       // Control register
+#define MMU_Base             c2       // Page tables base
+#define MMU_DomainAccess     c3       // Domain access control
+#define MMU_FaultStatus      c5       // Fault status register
+#define MMU_FaultAddress     c6       // Fault Address
+#define MMU_InvalidateCache  c7       // Invalidate cache data
+#define MMU_TLB              c8       // Translation Lookaside Buffer
+
+
+// This macro represents the initial startup code for the platform
+	.macro	_platform_setup1
+KARO_TX53_SETUP_START:
+	mrs	r0, CPSR
+	bic	r0, r0, #0x1f
+	orr	r0, r0, #0xd3
+	msr	CPSR_fc, r0
+
+	/*
+	 * Invalidate L1 I/D
+	 */
+	mov	r0, #0			@ set up for MCR
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
+	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
+	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
+	orr	r0, r0, #0x00000800	@ set bit 12 (Z---) BTB
+	mcr	p15, 0, r0, c1, c0, 0
+
+	setup_sdram
+
+	/* ARM errata ID #468414 */
+	mrc	15, 0, r1, c1, c0, 1
+	orr	r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr	15, 0, r1, c1, c0, 1
+
+	// Explicitly disable L2 cache
+	mrc	15, 0, r0, c1, c0, 1
+	bic	r0, r0, #0x2
+	mcr	15, 0, r0, c1, c0, 1
+
+	// reconfigure L2 cache aux control reg
+	mov	r0, #0xC0		// tag RAM
+	add	r0, r0, #0x4		// data RAM
+	orr	r0, r0, #(1 << 24)	// disable write allocate delay
+	orr	r0, r0, #(1 << 23)	// disable write allocate combine
+	orr	r0, r0, #(1 << 22)	// disable write allocate
+
+	mcr	15, 1, r0, c9, c0, 2
+
+init_aips_start:
+	init_aips
+
+    /* add code here that should configure critical pins */
+    /* ... */
+
+	/* switch off LCD backlight */
+	ldr	r10, =GPIO1_BASE_ADDR
+    // set the data register
+	ldr	r9, [r10, #GPIO_DR]
+	orr	r9, r9, #(1 << 1)
+	str	r9, [r10, #GPIO_DR]
+    // set the direction register to output
+	ldr	r9, [r10, #GPIO_GDIR]
+	orr	r9, r9, #(1 << 1)
+	str	r9, [r10, #GPIO_GDIR]
+
+	LED_INIT
+	LED_BLINK 1
+
+init_clock_start:
+	init_clock
+	LED_BLINK 2
+
+Normal_Boot_Continue:
+/*
+ * Note:
+ *	IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+10:
+	LED_BLINK 4
+	.endm	@ _platform_setup1
+
+	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+	.macro	init_aips
+	/*
+	* Set all MPROTx to be non-bufferable, trusted for R/W,
+	* not forced to user-mode.
+	*/
+	ldr	r0, =AIPS1_CTRL_BASE_ADDR
+	ldr	r1, AIPS1_PARAM
+	str	r1, [r0, #0x00]
+	str	r1, [r0, #0x04]
+	ldr	r0, =AIPS2_CTRL_BASE_ADDR
+	str	r1, [r0, #0x00]
+	str	r1, [r0, #0x04]
+	.endm	/* init_aips */
+
+	.macro	init_clock
+	ldr	r0, =CCM_BASE_ADDR
+	ldr	r1, [r0, #CLKCTL_CCR]
+	tst	r1, #(1 << 12)
+	bne	osc_ok
+
+	orr	r1, r1, #(1 << 12)
+	str	r1, [r0, #CLKCTL_CCR]
+osc_ok:
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR7]
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+	
+	
+	/* Switch ARM to step clock */
+	mov	r1, #0x4
+	str	r1, [r0, #CLKCTL_CCSR]
+
+/* FIXME: add support for 1200 CPU_CLK */
+#if CPU_CLK == 1000
+	setup_pll PLL1_BASE_ADDR, 1000
+#elif CPU_CLK == 800
+	setup_pll PLL1_BASE_ADDR, 800
+#else
+#error Bad CPU clock
+#endif
+	setup_pll PLL3_BASE_ADDR, 400
+
+    /* Switch peripheral to PLL3 */
+    ldr r0, =CCM_BASE_ADDR
+    ldr r1, CCM_CBCMR_VAL1
+    str r1, [r0, #CLKCTL_CBCMR]
+    ldr r1, CCM_CBCDR_VAL1
+    orr r1, r1, #(1 << 16)
+    str r1, [r0, #CLKCTL_CBCDR]
+    /* make sure change is effective */
+1:  ldr r1, [r0, #CLKCTL_CDHIPR]
+    LED_BLINK 1
+    cmp r1, #0x0
+    bne 1b
+
+#if SDRAM_CLK == 400
+	setup_pll PLL2_BASE_ADDR, 400
+#elif SDRAM_CLK == 333
+	setup_pll PLL2_BASE_ADDR, 333
+#elif SDRAM_CLK == 266
+	setup_pll PLL2_BASE_ADDR, 266
+#elif SDRAM_CLK == 216
+	setup_pll PLL2_BASE_ADDR, 216
+#elif SDRAM_CLK == 666
+	setup_pll PLL2_BASE_ADDR, 666
+#else
+#error Bad SDRAM_CLK
+#endif
+    /* Switch peripheral to PLL2 */
+	//ldr r0, =CCM_BASE_ADDR
+	ldr r1, CCM_CBCDR_VAL2
+	orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+	orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+	orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, CCM_CBCMR_VAL2
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	/*change uart clk parent to pll2*/
+	ldr r1, [r0, #CLKCTL_CSCMR1]
+	and r1, r1, #0xfcffffff
+	orr r1, r1, #0x01000000
+	str r1, [r0, #CLKCTL_CSCMR1]
+
+	/* make sure change is effective */
+1:  ldr r1, [r0, #CLKCTL_CDHIPR]
+    LED_BLINK 1
+	cmp r1, #0x0
+	bne 1b
+
+	setup_pll PLL3_BASE_ADDR, 216
+	setup_pll PLL4_BASE_ADDR, 455
+    
+	/* Set the platform clock dividers */
+	ldr r0, =PLATFORM_BASE_ADDR
+	ldr r1, PLATFORM_CLOCK_DIV
+	str r1, [r0, #PLATFORM_ICGC]
+
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1. */
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* make uart div=6*/
+	ldr r1, [r0, #CLKCTL_CSCDR1]
+	and r1, r1, #0xffffffc0
+	orr r1, r1, #0x0a
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+    mov r1, #0x00000
+    str r1, [r0, #CLKCTL_CCDR]
+
+    /* for cko - for ARM div by 8 */
+    mov r1, #0x000A0000
+    add r1, r1, #0x00000F0
+    str r1, [r0, #CLKCTL_CCOSR]
+end_clk_init:
+	.endm	@ init_clock
+
+	.macro	setup_pll pll, mhz
+	ldr	r2, =\pll
+	ldr	r1, =0x1232
+	str	r1, [r2, #PLL_DP_CTL]		@ Set DPLL ON (set UPEN bit); BRMO=1
+	mov	r1, #0x2
+	str	r1, [r2, #PLL_DP_CONFIG]	@ Enable auto-restart AREN bit
+
+	ldr	r1, W_DP_OP_\mhz
+	str	r1, [r2, #PLL_DP_OP]
+	str	r1, [r2, #PLL_DP_HFS_OP]
+
+	ldr	r1, W_DP_MFD_\mhz
+	str	r1, [r2, #PLL_DP_MFD]
+	str	r1, [r2, #PLL_DP_HFS_MFD]
+
+	ldr	r1, W_DP_MFN_\mhz
+	str	r1, [r2, #PLL_DP_MFN]
+	str	r1, [r2, #PLL_DP_HFS_MFN]
+
+	/* Now restart PLL */
+	ldr	r1, =0x1232
+	str	r1, [r2, #PLL_DP_CTL]
+101:
+	ldr	r1, [r2, #PLL_DP_CTL]
+	ands	r1, r1, #0x1
+	beq	101b
+	.endm
+
+	.macro	setup_sdram
+#if 0
+	/* Decrease the DRAM SDCLK pads to HIGH Drive strength */
+	ldr	r0, =IOMUXC_BASE_ADDR
+	ldr	r1, =0x000000e5
+	str	r1, [r0, #0x4b8]
+	/* Change the delay line configuration */
+	ldr	r0, =ESDCTL_BASE_ADDR
+	ldr	r1, =0x00f49400
+	str	r1, [r0, #ESDCTL_ESDCDLY1]
+	ldr	r1, =0x00f49a00
+	str	r1, [r0, #ESDCTL_ESDCDLY2]
+	ldr	r1, =0x00f49100
+	str	r1, [r0, #ESDCTL_ESDCDLY3]
+	ldr	r1, =0x00f48900
+	str	r1, [r0, #ESDCTL_ESDCDLY4]
+	ldr	r1, =0x00f49400
+	str	r1, [r0, #ESDCTL_ESDCDLY5]
+#endif
+	.endm
+
+
+/* FIXME: configure LED for AIS Display here */
+/* FIXME: This function is obviously essential. If not enabled U-Boot do not start, why??? */
+
+	.macro	LED_INIT
+	// initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
+	ldr	r10, =LED_GPIO_BASE
+	// GPIO_DR
+	ldr	r9, [r10, #GPIO_DR]
+	bic	r9, #(1 << DEBUG_LED_BIT)	@ LED OFF
+	str	r9, [r10, #GPIO_DR]
+	// GPIO_GDIR
+	ldr	r9, [r10, #GPIO_GDIR]
+	orr	r9, r9, #(1 << DEBUG_LED_BIT)
+	str	r9, [r10, #GPIO_GDIR]
+	// iomux
+	ldr	r10, =IOMUXC_BASE_ADDR
+	mov	r9, #LED_MUX_MODE
+	str	r9, [r10, #LED_MUX_OFFSET]
+	.endm
+
+#ifdef  DEBUG
+led_on:
+	ldr	r10, =LED_GPIO_BASE
+	// GPIO_DR
+	ldr	r9, [r10, #GPIO_DR]
+	orr	r9, #(1 << DEBUG_LED_BIT)	@ LED ON
+	str	r9, [r10, #GPIO_DR]
+	mov	pc, lr
+
+led_off:
+	ldr	r10, =LED_GPIO_BASE
+	// GPIO_DR
+	ldr	r9, [r10, #GPIO_DR]
+	bic	r9, #(1 << DEBUG_LED_BIT)	@ LED OFF
+	str	r9, [r10, #GPIO_DR]
+	mov	pc, lr
+
+delay:
+	subs	r10, r10, #1
+	movmi	pc, lr
+
+	ldr	r9, =(36000 / 10 / 10)
+2:
+	subs	r9, r9, #1
+	bne	2b
+	b	delay
+
+led_blink:
+	mov	r7, lr
+1:
+	subs	r8, r8, #1
+	bmi	2f
+
+	LED_ON
+	DELAY	200
+	LED_OFF
+	DELAY	300
+	b	1b
+2:
+	DELAY	700
+	mov	pc, r7
+#endif //DEBUG
+
+.globl lowlevel_init
+lowlevel_init:
+	_platform_setup1
+
+	mov pc, lr
+
+AIPS1_PARAM:		.word	0x77777777
+
+#if SDRAM_CLK > 333
+CCM_CBCDR_VAL1:		.word	0x02888945
+CCM_CBCMR_VAL1:		.word	0x00015154
+CCM_CBCDR_VAL2:		.word	0x00808145
+CCM_CBCMR_VAL2:		.word	0x00016154
+#else
+CCM_CBCDR_VAL1:		.word	0x02888945
+CCM_CBCMR_VAL1:		.word	0x00015154
+CCM_CBCDR_VAL2:		.word	0x00808145
+CCM_CBCMR_VAL2:		.word	0x00016154
+#endif
+
+W_CSCMR1_VAL:		.word	0xa6a2a020
+W_CSCDR1_VAL:		.word	0x00080b18
+W_DP_OP_1000:		.word	DP_OP_1000
+W_DP_MFD_1000:		.word	DP_MFD_1000
+W_DP_MFN_1000:		.word	DP_MFN_1000
+W_DP_OP_800:		.word	DP_OP_800
+W_DP_MFD_800:		.word	DP_MFD_800
+W_DP_MFN_800:		.word	DP_MFN_800
+W_DP_OP_700:		.word	DP_OP_700
+W_DP_MFD_700:		.word	DP_MFD_700
+W_DP_MFN_700:		.word	DP_MFN_700
+W_DP_OP_400:		.word	DP_OP_400
+W_DP_MFD_400:		.word	DP_MFD_400
+W_DP_MFN_400:		.word	DP_MFN_400
+W_DP_OP_532:		.word	DP_OP_532
+W_DP_MFD_532:		.word	DP_MFD_532
+W_DP_MFN_532:		.word	DP_MFN_532
+W_DP_OP_666:		.word	DP_OP_666
+W_DP_MFD_666:		.word	DP_MFD_666
+W_DP_MFN_666:		.word	DP_MFN_666
+W_DP_OP_665:		.word	DP_OP_665
+W_DP_MFD_665:		.word	DP_MFD_665
+W_DP_MFN_665:		.word	DP_MFN_665
+W_DP_OP_216:		.word	DP_OP_216
+W_DP_MFD_216:		.word	DP_MFD_216
+W_DP_MFN_216:		.word	DP_MFN_216
+W_DP_OP_333:		.word	DP_OP_333
+W_DP_MFD_333:		.word	DP_MFD_333
+W_DP_MFN_333:		.word	DP_MFN_333
+W_DP_OP_266:		.word	DP_OP_266
+W_DP_MFD_266:		.word	DP_MFD_266
+W_DP_MFN_266:		.word	DP_MFN_266
+W_DP_OP_455:            .word DP_OP_455
+W_DP_MFD_455:           .word DP_MFD_455
+W_DP_MFN_455:           .word DP_MFN_455
+PLATFORM_CLOCK_DIV:	.word	0x00000124
+
diff -Naur -x '.*' u-boot-2009.08.orig/board/karo/tx53-1331/Makefile u-boot-2009.08/board/karo/tx53-1331/Makefile
--- u-boot-2009.08.orig/board/karo/tx53-1331/Makefile	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-2009.08/board/karo/tx53-1331/Makefile	2012-08-09 15:04:33.000000000 +0200
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# 
+# (C) Copyright 2012 hwsw.development@gmail.com
+#           Changed to support TX53-1331 module from Ka-Ro electronics GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= tx53-1331.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -Naur -x '.*' u-boot-2009.08.orig/board/karo/tx53-1331/tx53-1331.c u-boot-2009.08/board/karo/tx53-1331/tx53-1331.c
--- u-boot-2009.08.orig/board/karo/tx53-1331/tx53-1331.c	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-2009.08/board/karo/tx53-1331/tx53-1331.c	2012-08-09 15:03:17.000000000 +0200
@@ -0,0 +1,794 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * 
+ *
+ *
+ * 
+ * (C) Copyright 2012 Thomas Poms <hwsw.development@gmail.com>
+ *          Changed to support TX53-1331 module from Ka-Ro electronics GmbH
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx53.h>
+#include <asm/arch/mx53_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <imx_spi.h>
+#include <netdev.h>
+
+#if CONFIG_I2C_MXC
+#include <i2c.h>
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMU
+#include <asm/mmu.h>
+#include <asm/arch/mmu.h>
+#endif
+
+#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#include <asm/imx_iim.h>
+#endif
+
+#ifdef CONFIG_CMD_CLOCK
+#include <asm/clock.h>
+#endif
+
+#ifdef CONFIG_MXC_NAND
+#include <asm-arm/arch/mxc_nand.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+static enum boot_device boot_dev;
+
+static inline void setup_boot_device(void)
+{
+	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+	uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
+	uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
+
+	switch (bt_mem_ctl) {
+	case 0x0:
+		if (bt_mem_type)
+			boot_dev = ONE_NAND_BOOT;
+		else
+			boot_dev = WEIM_NOR_BOOT;
+		break;
+	case 0x2:
+		if (bt_mem_type)
+			boot_dev = SATA_BOOT;
+		else
+			boot_dev = PATA_BOOT;
+		break;
+	case 0x3:
+		if (bt_mem_type)
+			boot_dev = SPI_NOR_BOOT;
+		else
+			boot_dev = I2C_BOOT;
+		break;
+	case 0x4:
+	case 0x5:
+		boot_dev = SD_BOOT;
+		break;
+	case 0x6:
+	case 0x7:
+		boot_dev = MMC_BOOT;
+		break;
+	case 0x8 ... 0xf:
+		boot_dev = NAND_BOOT;
+		break;
+	default:
+		boot_dev = UNKNOWN_BOOT;
+		break;
+	}
+}
+
+enum boot_device get_boot_device(void)
+{
+	return boot_dev;
+}
+
+u32 get_board_rev(void)
+{
+	return system_rev;
+}
+
+static inline void setup_soc_rev(void)
+{
+	int reg;
+
+	/* Si rev is obtained from ROM */
+	reg = __REG(ROM_SI_REV);
+
+	switch (reg) {
+	case 0x10:
+		system_rev = 0x53000 | CHIP_REV_1_0;
+		break;
+	case 0x20:
+		system_rev = 0x53000 | CHIP_REV_2_0;
+		break;
+	case 0x21:
+		system_rev = 0x53000 | CHIP_REV_2_1;
+		break;
+	default:
+		system_rev = 0x53000 | CHIP_REV_UNKNOWN;
+	}
+}
+
+static inline void setup_board_rev(int rev)
+{
+	system_rev |= (rev & 0xF) << 8;
+}
+
+inline int is_soc_rev(int rev)
+{
+	return (system_rev & 0xFF) - rev;
+}
+
+#ifdef CONFIG_ARCH_MMU
+void board_mmu_init(void)
+{
+	unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
+	unsigned long i;
+
+	/*
+	* Set the TTB register
+	*/
+	asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+	/*
+	* Set the Domain Access Control Register
+	*/
+	i = ARM_ACCESS_DACR_DEFAULT;
+	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+	/*
+	* First clear all TT entries - ie Set them to Faulting
+	*/
+	memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+	/* Actual   Virtual  Size   Attributes          Function */
+	/* Base     Base     MB     cached? buffered?  access permissions */
+	/* xxx00000 xxx00000 */
+	X_ARM_MMU_SECTION(0x000, 0x000, 0x010,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */
+	X_ARM_MMU_SECTION(0x010, 0x010, 0x060,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* Reserved, 96M */
+	X_ARM_MMU_SECTION(0x070, 0x070, 0x010,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* IRAM, 16M */
+	X_ARM_MMU_SECTION(0x080, 0x080, 0x080,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* Reserved region + TZIC. 1M */
+	X_ARM_MMU_SECTION(0x100, 0x100, 0x040,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* SATA */
+	X_ARM_MMU_SECTION(0x140, 0x140, 0x040,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* Reserved, 64M */
+	X_ARM_MMU_SECTION(0x180, 0x180, 0x080,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* IPUv3M */
+	X_ARM_MMU_SECTION(0x200, 0x200, 0x200,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* GPU */
+	X_ARM_MMU_SECTION(0x400, 0x400, 0x300,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* periperals */
+	X_ARM_MMU_SECTION(0x700, 0x700, (PHYS_SDRAM_1_SIZE >> 20),
+			ARM_CACHEABLE, ARM_BUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */
+	X_ARM_MMU_SECTION(0x700, 0x900, (PHYS_SDRAM_1_SIZE >> 20),
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */
+#if defined(CONFIG_NR_DRAM_BANKS)				
+	X_ARM_MMU_SECTION(0xB00, 0xB00, (PHYS_SDRAM_2_SIZE >> 20),
+			ARM_CACHEABLE, ARM_BUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* CSD1 512M */
+	X_ARM_MMU_SECTION(0xB00, 0xD00, (PHYS_SDRAM_2_SIZE >> 20),
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* CSD1 512M */
+#endif	 //CONFIG_NR_DRAM_BANKS		
+	X_ARM_MMU_SECTION(0xF00, 0xF00, 0x07F,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
+	X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x001,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */
+	X_ARM_MMU_SECTION(0xF80, 0xF80, 0x080,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* iRam + GPU3D + Reserved */
+
+	/* Workaround for arm errata #709718 */
+	/* Setup PRRR so device is always mapped to non-shared */
+	asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
+	i &= (~(3 << 0x10));
+	asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
+
+	/* Enable MMU */
+	MMU_ON();
+}
+#endif
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#if defined(CONFIG_NR_DRAM_BANKS) 
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif	
+	return 0;
+}
+
+static void setup_uart(void)
+{
+	/* UART1 TXD */
+	mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, 0x1E4);
+
+	/* UART1 RXD */
+	mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
+	mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, 0x1E4);
+}
+
+#ifdef CONFIG_I2C_MXC
+static void setup_i2c(unsigned int module_base)
+{
+	switch (module_base) {
+	case I2C1_BASE_ADDR:
+		/* i2c1 SDA */
+		mxc_request_iomux(MX53_PIN_CSI0_D8,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+				PAD_CTL_HYS_ENABLE);
+		/* i2c1 SCL */
+		mxc_request_iomux(MX53_PIN_CSI0_D9,
+				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+				PAD_CTL_HYS_ENABLE);
+		break;
+	case I2C2_BASE_ADDR:
+		/* i2c2 SDA */
+		mxc_request_iomux(MX53_PIN_KEY_ROW3,
+				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
+				PAD_CTL_SRE_FAST |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+				PAD_CTL_HYS_ENABLE);
+
+		/* i2c2 SCL */
+		mxc_request_iomux(MX53_PIN_KEY_COL3,
+				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+				INPUT_CTL_PATH0);
+		mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
+				PAD_CTL_SRE_FAST |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+				PAD_CTL_HYS_ENABLE);
+
+		break;
+	case I2C3_BASE_ADDR:
+		/* No device is connected via I2C3 in EVK and ARM2 */
+		break;
+	default:
+		printf("Invalid I2C base: 0x%x\n", module_base);
+		break;
+	}
+}
+
+void setup_core_voltages(void)
+{
+
+	unsigned char buf[4] = { 0 };
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	if (is_soc_rev(CHIP_REV_1_0) == 0) {
+		/* Set core voltage VDDGP to 1.05V for 800MHZ */
+		buf[0] = 0x45;
+		buf[1] = 0x4a;
+		buf[2] = 0x52;
+		if (i2c_write(0x8, 24, 1, buf, 3))
+			return;
+
+		/* Set DDR voltage VDDA to 1.25V */
+		buf[0] = 0;
+		buf[1] = 0;
+		buf[2] = 0x1a;
+		if (i2c_write(0x8, 26, 1, buf, 3))
+			return;
+	}
+
+	if (is_soc_rev(CHIP_REV_2_0) >= 0) {
+		/* set VDDGP as 1.25V for 1.0 GHZ */
+		buf[0] = 0x45;
+		buf[1] = 0x4a;
+		buf[2] = 0x5a;
+		if (i2c_write(0x8, 24, 1, buf, 3))
+			return;
+		/* Set VCC to 1.3V for TO2 */
+		buf[0] = 0;
+		buf[1] = 0;
+		buf[2] = 0x1C;
+		if (i2c_write(0x8, 25, 1, buf, 3))
+			return;
+
+		/* Set VDDA to 1.3V for TO2 */
+		buf[0] = 0;
+		buf[1] = 0;
+		buf[2] = 0x1C;
+		if (i2c_write(0x8, 26, 1, buf, 3))
+			return;
+	}
+
+	/* need to delay 100 ms to allow power supplies to ramp-up */
+	udelay(100000);
+
+	/* Raise the core frequency to 800MHz */
+	writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+	if (is_soc_rev(CHIP_REV_2_0) >= 0)
+		/* Raise the core frequency as 1G for TO2.0 */
+		clk_config(CONFIG_REF_CLK_FREQ, 1000, CPU_CLK);
+}
+#endif
+
+#ifdef CONFIG_IMX_ECSPI
+s32 spi_get_cfg(struct imx_spi_dev_t *dev)
+{
+	switch (dev->slave.cs) {
+	case 0:
+		/* pmic */
+		dev->base = CSPI1_BASE_ADDR;
+		dev->freq = 2500000;
+		dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
+		dev->ss = 0;
+		dev->fifo_sz = 64 * 4;
+		dev->us_delay = 0;
+		break;
+	case 1:
+		/* spi_nor */
+		dev->base = CSPI1_BASE_ADDR;
+		dev->freq = 2500000;
+		dev->ss_pol = IMX_SPI_ACTIVE_LOW;
+		dev->ss = 1;
+		dev->fifo_sz = 64 * 4;
+		dev->us_delay = 0;
+		break;
+	default:
+		printf("Invalid Bus ID!\n");
+		break;
+	}
+
+	return 0;
+}
+
+void spi_io_init(struct imx_spi_dev_t *dev)
+{
+	switch (dev->base) {
+	case CSPI1_BASE_ADDR:
+		/* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */
+		mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0x104);
+		mxc_iomux_set_input(
+				MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, 0x3);
+
+		/* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */
+		mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0x104);
+		mxc_iomux_set_input(
+				MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, 0x3);
+
+		if (dev->ss == 0) {
+			/* de-select SS1 of instance: ecspi1. */
+			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
+			mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x1E4);
+
+			/* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
+			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
+			mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x104);
+			mxc_iomux_set_input(
+				MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, 0x3);
+		} else if (dev->ss == 1) {
+			/* de-select SS0 of instance: ecspi1. */
+			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
+			mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x1E4);
+
+			/* mux mode: ALT0 mux port: SS1 of instance: ecspi1. */
+			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
+			mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x104);
+			mxc_iomux_set_input(
+				MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, 0x2);
+		}
+
+		/* Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+		mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104);
+		mxc_iomux_set_input(
+			MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3);
+		break;
+
+	case CSPI2_BASE_ADDR:
+	default:
+
+		break;
+	}
+}
+#endif
+
+#ifdef CONFIG_MXC_FEC
+
+#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+
+int fec_get_mac_addr(unsigned char *mac)
+{
+	u32 *iim1_mac_base =
+		(u32 *)(IIM_BASE_ADDR + IIM_BANK_AREA_1_OFFSET +
+			CONFIG_IIM_MAC_ADDR_OFFSET);
+	int i;
+
+	for (i = 0; i < 6; ++i, ++iim1_mac_base)
+		mac[i] = (u8)readl(iim1_mac_base);
+
+	return 0;
+}
+#endif
+
+static void setup_fec(void)
+{
+	volatile unsigned int reg;
+
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 0x1FC);
+	mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, 0x004);
+
+	/* FEC RXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 0x180);
+
+	/* FEC RXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 0x180);
+
+	 /* FEC TXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, 0x004);
+
+	/* FEC TXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, 0x004);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, 0x004);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 0x180);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 0x180);
+
+	/* FEC CRS */
+	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 0x180);
+
+	/* phy reset: gpio7-6 */
+	mxc_request_iomux(MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1);
+
+	reg = readl(GPIO7_BASE_ADDR + 0x0);
+	reg &= ~0x40;
+	writel(reg, GPIO7_BASE_ADDR + 0x0);
+
+	reg = readl(GPIO7_BASE_ADDR + 0x4);
+	reg |= 0x40;
+	writel(reg, GPIO7_BASE_ADDR + 0x4);
+
+	udelay(500);
+
+	reg = readl(GPIO7_BASE_ADDR + 0x0);
+	reg |= 0x40;
+	writel(reg, GPIO7_BASE_ADDR + 0x0);
+
+}
+#endif
+
+#ifdef CONFIG_NET_MULTI
+int board_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+
+	return rc;
+}
+#endif
+
+#ifdef CONFIG_CMD_MMC
+
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1, 1},
+	{MMC_SDHC3_BASE_ADDR, 1, 1},
+};
+
+#ifdef CONFIG_DYNAMIC_MMC_DEVNO
+int get_mmc_env_devno(void)
+{
+	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+	return (soc_sbmr & 0x00300000) ? 1 : 0;
+}
+#endif
+
+#ifdef CONFIG_EMMC_DDR_PORT_DETECT
+int detect_mmc_emmc_ddr_port(struct fsl_esdhc_cfg *cfg)
+{
+	return (MMC_SDHC3_BASE_ADDR == cfg->esdhc_base) ? 1 : 0;
+}
+#endif
+
+int esdhc_gpio_init(bd_t *bis)
+{
+	s32 status = 0;
+	u32 index = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
+		++index) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA0,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA1,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA2,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA3,
+						IOMUX_CONFIG_ALT0);
+
+			mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
+			mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
+			break;
+		case 1:
+			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_IORDY,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_DATA8,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA9,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA10,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA11,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA0,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA1,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA2,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA3,
+						IOMUX_CONFIG_ALT4);
+
+			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4);
+
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+			break;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+
+	return status;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	if (!esdhc_gpio_init(bis))
+		return 0;
+	else
+		return -1;
+}
+
+#endif
+
+#ifdef CONFIG_MXC_NAND
+void setup_nfc(void)
+{
+	//setup is already done in flash_header.S
+}
+#endif
+
+#if defined(CONFIG_DWC_AHSATA)
+static void setup_sata_device(void)
+{
+	u32 *tmp_base =
+		(u32 *)(IIM_BASE_ADDR + 0x180c);
+	u32 reg;
+#if 0	
+	mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT1);
+
+
+	/* GPIO_3_3 */
+	reg = readl(GPIO3_BASE_ADDR);
+	reg |= (0x1 << 3);
+	writel(reg, GPIO3_BASE_ADDR);
+
+	reg = readl(GPIO3_BASE_ADDR + 0x4);
+	reg |= (0x1 << 3);
+	writel(reg, GPIO3_BASE_ADDR + 0x4);
+#endif
+	udelay(1000);
+
+	/* Set USB_PHY1 clk, fuse bank4 row3 bit2 */
+	set_usb_phy1_clk();
+	writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_MFG
+/* MFG firmware need reset usb to avoid host crash firstly */
+#define USBCMD 0x140
+	int val = readl(OTG_BASE_ADDR + USBCMD);
+	val &= ~0x1; /*RS bit*/
+	writel(val, OTG_BASE_ADDR + USBCMD);
+#endif
+	setup_boot_device();
+	setup_soc_rev();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX53_LOCO;	/* board id for linux */ /* FIXME: an MACH type should be specified for the TX53-1331 --> see ../include/asm-arm/mach-types.h*/
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	setup_uart();
+
+#ifdef CONFIG_MXC_NAND
+	setup_nfc();
+#endif
+
+#ifdef CONFIG_MXC_FEC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_I2C_MXC
+	setup_i2c(CONFIG_SYS_I2C_PORT);
+	setup_core_voltages();
+#endif
+
+#if defined(CONFIG_DWC_AHSATA)
+	setup_sata_device();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Boot Reason: [");
+
+	switch (__REG(SRC_BASE_ADDR + 0x8)) {
+	case 0x0001:
+		printf("POR");
+		break;
+	case 0x0009:
+		printf("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		printf("WDOG");
+		break;
+	default:
+		printf("unknown");
+	}
+	printf("]\n");
+
+	printf("Boot Device: ");
+	switch (get_boot_device()) {
+	case WEIM_NOR_BOOT:
+		printf("NOR\n");
+		break;
+	case ONE_NAND_BOOT:
+		printf("ONE NAND\n");
+		break;
+	case PATA_BOOT:
+		printf("PATA\n");
+		break;
+	case SATA_BOOT:
+		printf("SATA\n");
+		break;
+	case I2C_BOOT:
+		printf("I2C\n");
+		break;
+	case SPI_NOR_BOOT:
+		printf("SPI NOR\n");
+		break;
+	case SD_BOOT:
+		printf("SD\n");
+		break;
+	case MMC_BOOT:
+		printf("MMC\n");
+		break;
+	case NAND_BOOT:
+		printf("NAND\n");
+		break;
+	case UNKNOWN_BOOT:
+	default:
+		printf("UNKNOWN\n");
+		break;
+	}
+	return 0;
+}
+
diff -Naur -x '.*' u-boot-2009.08.orig/board/karo/tx53-1331/u-boot.lds u-boot-2009.08/board/karo/tx53-1331/u-boot.lds
--- u-boot-2009.08.orig/board/karo/tx53-1331/u-boot.lds	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-2009.08/board/karo/tx53-1331/u-boot.lds	2012-08-09 15:04:12.000000000 +0200
@@ -0,0 +1,81 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ * 
+ *
+ *
+ * 
+ * (C) Copyright 2012 Thomas Poms <hwsw.development@gmail.com>
+ *          Changed to support TX53-1331 module from Ka-Ro electronics GmbH
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/karo/tx53-1331/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/karo/tx53-1331/libtx53-1331.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_end_of_copy = .; /* end_of ROM copy code here */
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff -Naur -x '.*' u-boot-2009.08.orig/include/asm-arm/arch-mx53/mx53.h u-boot-2009.08/include/asm-arm/arch-mx53/mx53.h
--- u-boot-2009.08.orig/include/asm-arm/arch-mx53/mx53.h	2012-05-16 15:19:41.000000000 +0200
+++ u-boot-2009.08/include/asm-arm/arch-mx53/mx53.h	2012-05-15 10:29:09.000000000 +0200
@@ -384,6 +384,10 @@
 #define DP_MFD_665      (96 - 1)
 #define DP_MFN_665      89
 
+#define DP_OP_666       ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_666      (16 - 1)
+#define DP_MFN_666      15
+
 #define DP_OP_532       ((5 << 4) + ((1 - 1)  << 0))
 #define DP_MFD_532      (24 - 1)
 #define DP_MFN_532      13
@@ -403,6 +407,14 @@
 #define DP_MFD_216      (1 - 1)
 #define DP_MFN_216      1
 
+#define DP_OP_333       ((6 << 4) + ((2 - 1) << 0))
+#define DP_MFD_333      (16 - 1)
+#define DP_MFN_333      15
+
+#define DP_OP_266       ((5 << 4) + ((2 - 1) << 0))
+#define DP_MFD_266      (24 - 1)
+#define DP_MFN_266      13
+
 #define PLL_DP_CTL      0x00
 #define PLL_DP_CONFIG   0x04
 #define PLL_DP_OP       0x08
diff -Naur -x '.*' u-boot-2009.08.orig/include/configs/tx53-1331.h u-boot-2009.08/include/configs/tx53-1331.h
--- u-boot-2009.08.orig/include/configs/tx53-1331.h	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-2009.08/include/configs/tx53-1331.h	2012-08-09 15:06:35.000000000 +0200
@@ -0,0 +1,304 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2012 Thomas Poms <hwsw.development@gmail.com>
+ *          Configuration settings for the TX53-1331 module from Ka-Ro electronics GmbH.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NO_FLASH     //must be defined here otherwise ../include/config_cmd_default.h will define CONFIGs that will cause a fail during compilation
+
+#include <asm/arch/mx53.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7		/* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_MXC
+#define CONFIG_MX53
+#define CONFIG_MX53_LOCO        //the TX53-1331 uses the same DDR3 configuration as the MX53 Loco 
+                                //dual SDRAM bank support is required --> see mmu.h
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_MX53_CLK32	32768
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_MX53_HCLK_FREQ	24000000
+#define CONFIG_SYS_PLL2_FREQ    400
+#define CONFIG_SYS_AHB_PODF     2
+#define CONFIG_SYS_AXIA_PODF    0
+#define CONFIG_SYS_AXIB_PODF    1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(3 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART 1
+#define CONFIG_UART_BASE_ADDR   UART1_BASE_ADDR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+//#define CONFIG_CMD_DHCP
+//#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT  100
+#define CONFIG_NET_MULTI 1
+//#define CONFIG_BOOTP_SUBNETMASK
+//#define CONFIG_BOOTP_GATEWAY
+//#define CONFIG_BOOTP_DNS
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_FPGA
+
+#define CONFIG_CMD_MMC
+
+/* Enable below configure when supporting nand */
+#define CONFIG_CMD_NAND
+#define CONFIG_MXC_NAND
+/* NAND FLASH driver setup */
+#define CONFIG_SYS_NAND_MAX_CHIPS     1
+#define CONFIG_SYS_MAX_NAND_DEVICE    1
+#define CONFIG_SYS_NAND_BASE          0x40000000
+#define CONFIG_NAND_FW_16BIT    0 /* 1: 16bit 0: 8bit */
+
+#define CONFIG_ENV_IS_IN_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT			"nand0=mxc_nand"
+#define MTDPARTS_DEFAULT		"mtdparts=mxc_nand:1m@0x0(u-boot),512k@0x80000(u-bootenv),96m(rootfs),-(flashnv)\0"
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_NAND
+
+#define CONFIG_CMD_IIM
+#define CONFIG_CMD_ENV
+
+#define CONFIG_CMD_CLOCK
+#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ
+
+#define CONFIG_CMD_SATA
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	1
+
+#define CONFIG_PRIME	"FEC0"
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+#define CONFIG_RD_LOADADDR	(CONFIG_LOADADDR + 0x300000)
+
+#define	CONFIG_EXTRA_ENV_SETTINGS			\
+        "kernel=uImage\0"												\
+        "test_kernel=uImage_mx53_ft\0"												\
+		"serverip=10.0.0.22\0"												\
+		"ipaddr=10.0.0.200\0"												\
+		"nfsroot=/tftpboot/rootfs\0"											\
+		"baudrate=115200\0"											\
+		"serialInterface=ttymxc0\0"											\
+		"lvds=video=mxcdi0fb:RGB666,WXGA di0_primary ldb=di0\0"          \
+		"tve=video=mxcdi1fb: YUV444,TV-1080P30 di1_primary tve\0"       \
+		"display=video=mxcdi0fb:RGB666,WXGA di0_primary ldb=di0\0"     \
+		"misc=debug\0"          \
+		"fileSystemType=ext3\0"              \
+		"rootDeviceMMC=/dev/mmcblk0p2\0"              \
+		"rootDeviceSATA=/dev/sda1\0"              \
+		"bootargs_base=setenv bootargs console=${serialInterface},${baudrate}n8 ${init} ${display} ${misc}\0"						\
+		"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
+		"bootargs_nand=setenv bootargs ${bootargs} ${mtdparts} root=mtd:rootfs rootfstype=jffs2 ro\0"	\
+		"bootargs_sata=setenv bootargs ${bootargs} ip=dhcp root=${rootDeviceSATA} rootfstype=${fileSystemType} rw rootwait\0"   \
+		"bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp root=${rootDeviceMMC} rootfstype=${fileSystemType} rw rootwait\0"       \
+		"bootcmd_tftp_sata=run bootargs_base bootargs_sata;sata init;tftpboot ${loadaddr} ${kernel};bootm\0"    \
+		"bootcmd_tftp_nfs=run bootargs_base bootargs_nfs;sata init;tftpboot ${loadaddr} ${kernel}; bootm\0"			\
+ 		"bootcmd_tftp_mmc=run bootargs_base bootargs_mmc;sata init;tftpboot ${loadaddr} ${kernel};bootm\0"			\
+        "bootcmd_nfs=run bootargs_base bootargs_nfs;sata init;nfs ${loadaddr} ${serverip}/boot/${kernel};bootm\0"			\
+		"bootcmd_nand=run bootargs_nand;sata init; chpart rootfs; fsload ${loadaddr} /boot/uImage; bootm\0"	\
+		"bootcmd_mmc=run bootargs_base bootargs_mmc;sata init; mmc rescan; mmcinfo; fatinfo mmc 0:1; fatls mmc 0:1; fatload mmc 0:1 ${loadaddr} ${kernel}; bootm\0"  \
+		"bootcmd_test=run bootargs_base bootargs_nfs;sata init;tftpboot ${loadaddr} ${test_kernel}; bootm\0"			\
+		"mtdids=" MTDIDS_DEFAULT "\0"							\
+		"mtdparts=" MTDPARTS_DEFAULT "\0"	
+
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"TX53-1331 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	64	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ				1000
+
+#define CONFIG_CMDLINE_EDITING	1
+
+#define CONFIG_FEC0_IOBASE	FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX	-1
+#define CONFIG_FEC0_PHY_ADDR	-1
+#define CONFIG_FEC0_MIIBASE 	-1
+
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_IIM_MAC_ADDR_OFFSET      0x24
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+/*
+ * FUSE Configs
+ * */
+#ifdef CONFIG_CMD_IIM
+	#define CONFIG_IMX_IIM
+	#define IMX_IIM_BASE    IIM_BASE_ADDR
+	#define CONFIG_IIM_MAC_BANK     1
+	#define CONFIG_IIM_MAC_ROW      9
+#endif
+
+#ifdef CONFIG_CMD_MMC
+	#define CONFIG_MMC				1
+	#define CONFIG_GENERIC_MMC
+	#define CONFIG_IMX_MMC
+	#define CONFIG_SYS_FSL_ESDHC_NUM        2
+	#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+	#define CONFIG_SYS_MMC_ENV_DEV  0
+	#define CONFIG_DOS_PARTITION	1
+	#define CONFIG_CMD_FAT		1
+	#define CONFIG_CMD_EXT2		1
+
+	/* detect whether ESDHC1 or ESDHC3 is boot device */
+	#define CONFIG_DYNAMIC_MMC_DEVNO
+
+	#define CONFIG_EMMC_DDR_PORT_DETECT
+	#define CONFIG_EMMC_DDR_MODE
+	/* port 1 (ESDHC3) is 8 bit */
+	#define CONFIG_MMC_8BIT_PORTS	0x2
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+  #define CONFIG_DWC_AHSATA
+  #define CONFIG_SYS_SATA_MAX_DEVICE      1
+  #define CONFIG_DWC_AHSATA_PORT_ID       0
+  #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+  #define CONFIG_LBA48
+  #define CONFIG_LIBATA
+  #define DWC_AHSATA_DEBUG
+#endif
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MX53_EVK)
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(1024 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+	(addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+#endif
+
+
+#if defined (CONFIG_MX53_LOCO)
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_2		CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE	(512 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+	((addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) \
+	|| (addr >= PHYS_SDRAM_2 && addr <= (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
+#endif	
+
+
+#define CONFIG_TX53_SDRAM_TYPE  SDRAM_TYPE_DDR3
+#define CONFIG_TX53_SDRAM_CLK	333
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET			 0x80000
+#define CONFIG_ENV_SIZE				 0x20000	/* 1 Erase block */
+#else
+#define CONFIG_ENV_SIZE				 0x20000
+#define CONFIG_ENV_IS_NOWHERE	1
+#endif
+#endif				/* __CONFIG_H */
diff -Naur -x '.*' u-boot-2009.08.orig/Makefile u-boot-2009.08/Makefile
--- u-boot-2009.08.orig/Makefile	2012-05-16 15:19:39.000000000 +0200
+++ u-boot-2009.08/Makefile	2012-05-15 10:01:12.000000000 +0200
@@ -2021,7 +2021,7 @@
 	if [ "$${FLASH}" = "SPANSION" ] ; then \
 		echo "#define CONFIG_SYS_SPANSION_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
-		cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
+		Tcp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
 		$(XECHO) "... with SPANSION boot..." ; \
 	fi; \
 	if [ "$${FLASH}" = "STMICRO" ] ; then \
@@ -3283,6 +3283,9 @@
 mx53_pcba_android_mfg_config	\
 mx53_pcba_android_config	:unconfig
 	$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_pcba freescale mx53
+	
+tx53-1331_config :unconfig
+	$(MKCONFIG) $(@:_config=) arm arm_cortexa8 tx53-1331 karo mx53 	
 
 mx53_smd_mfg_config             \
 mx53_smd_android_config		\
