//------------------------------------------------------------------------------
//
//  Function:  OEMInterruptHandler
//
ULONG OEMInterruptHandler(ULONG ra)
{
    UINT32 sysIntr = SYSINTR_NOP;
    UINT32 irq;
    UINT32 dwLevel;
    UINT32 line;
 	
 	UINT32 temp_irq;

    // Read the vector address and compute the vector number. This also signals
    // inservice to the icoll hardware because the ARM read side effect (RSE)
    // is enabled. We are using the default one word vector pitch.
    temp_irq = HW_ICOLL_VECTOR_RD();
    irq = (temp_irq / 4) & 0x7F;


    // Make sure interrupt is pending
    if (irq >= ICOLL_IRQ_SOURCES_MAX)
    {
        OALMSGS(OAL_ERROR,(TEXT("OEMInterrupHandler:  No pending interrupt!\r\n")));
    }

    // If system timer interrupt
    else if (irq == IRQ_TIMER0)
    {
        // Call timer interrupt handler
        sysIntr = OALTimerIntrHandler();
    }

    // If profile timer interrupt
    else if (g_pProfilerISR && (irq == IRQ_TIMER1))
    {
        //OALMSGS(1,(TEXT("ProfilerISR!\r\n")));

        // Call profiling interupt handler
        sysIntr = g_pProfilerISR(ra);
    }
    else if (irq == IRQ_RTC_ALARM)
    {
        sysIntr = OALRTCAlarmIntrHandler(ra);
    }
    // Else not system timer interrupt
    else
    {
#ifdef OAL_ILTIMING
        if (g_oalILT.active) 
        {
            g_oalILT.isrTime1 = OALTimerCountsSinceSysTick();
            g_oalILT.savedPC = 0;
            g_oalILT.interrupts++;
        }
#endif

        // GPIO0 special case
        if(irq == IRQ_GPIO0)
        {
            // Detect GPIO line that is asserting interrupt
            line = _CountLeadingZeros(HW_PINCTRL_IRQSTAT0_RD() & HW_PINCTRL_IRQEN0_RD());

            // If at least one GPIO interrupt line is asserted
            if (line < 32)
            {
                // Translate it to the secondary IRQ
                irq = IRQ_GPIO0_PIN0 + (31 - line);
            }
            else
            {
                irq = (UINT32) OAL_INTR_IRQ_UNDEFINED;
            }

            	OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  irq == IRQ_GPIO0 line = (%x)\r\n"),line));
            	OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  irq =(%x)\r\n"),irq));
		OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_PINCTRL_IRQEN0_RD =(%x)\r\n"),HW_PINCTRL_IRQEN0_RD()));
		OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_PINCTRL_IRQSTAT0_RD =(%x)\r\n"),HW_PINCTRL_IRQSTAT0_RD()));
		OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_PINCTRL_PIN2IRQ0_RD =(%x)\r\n"),HW_PINCTRL_PIN2IRQ0_RD()));
        }

        // GPIO1 special case
        else if(irq == IRQ_GPIO1)
        {
            // Detect GPIO line that is asserting interrupt
            line = _CountLeadingZeros(HW_PINCTRL_IRQSTAT1_RD() & HW_PINCTRL_IRQEN1_RD());

            // If at least one GPIO interrupt line is asserted
            if (line < 32)
            {
                // Translate it to the secondary IRQ
                irq = IRQ_GPIO1_PIN0 + (31 - line);
            }
            else
            {
                irq = (UINT32) OAL_INTR_IRQ_UNDEFINED;
            }
        }

        // GPIO2 special case
        else if(irq == IRQ_GPIO2)
        { 
            // Detect GPIO line that is asserting interrupt
            line = _CountLeadingZeros(HW_PINCTRL_IRQSTAT2_RD() & HW_PINCTRL_IRQEN2_RD());

            // If at least one GPIO interrupt line is asserted
            if (line < 32)
            {
                // Translate it to the secondary IRQ
                irq = IRQ_GPIO2_PIN0 + (31 - line);
            }
            else
            {
                irq = (UINT32) OAL_INTR_IRQ_UNDEFINED;
            }
        }

        // GPIO3 special case
        else if(irq == IRQ_GPIO3)
        { 
            // Detect GPIO line that is asserting interrupt
            line = _CountLeadingZeros(HW_PINCTRL_IRQSTAT3_RD() & HW_PINCTRL_IRQEN3_RD());
        
            // If at least one GPIO interrupt line is asserted
            if (line < 32)
            {
                // Translate it to the secondary IRQ
                irq = IRQ_GPIO3_PIN0 + (31 - line);
            }
            else
            {
                irq = (UINT32) OAL_INTR_IRQ_UNDEFINED;
            }
        }

        // GPIO4 special case
        else if(irq == IRQ_GPIO4)
        { 
            // Detect GPIO line that is asserting interrupt
            line = _CountLeadingZeros(HW_PINCTRL_IRQSTAT4_RD() & HW_PINCTRL_IRQEN4_RD());
        
            // If at least one GPIO interrupt line is asserted
            if (line < 32)
            {
                // Translate it to the secondary IRQ
                irq = IRQ_GPIO4_PIN0 + (31 - line);
            }
            else
            {
                irq = (UINT32) OAL_INTR_IRQ_UNDEFINED;
            }
        }

#ifdef OAL_BSP_CALLBACKS
        // Give BSP chance to translate IRQ -- if there is subordinate
        // interrupt controller in the BSP give it a chance to decode
        // its status and change the IRQ
        irq = BSPIntrActiveIrq(irq);
#endif

        // If IRQ is defined
        if (irq != OAL_INTR_IRQ_UNDEFINED)
        {
            // First find if IRQ is claimed by chain
            sysIntr = NKCallIntChain((UCHAR)irq);
            if (sysIntr == SYSINTR_CHAIN || !NKIsSysIntrValid(sysIntr))
            {
                // IRQ wasn't claimed, use static mapping
                sysIntr = OALIntrTranslateIrq(irq);
            }

            // Mask all IRQs associated with the sysintr
            OEMInterruptMask(sysIntr, TRUE);
        }
        else
        {
//EAI====================================
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  temp_irq (%x)!\r\n"),temp_irq));
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  irq (%x)!\r\n"),irq));
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  undefined IRQ (%x)!\r\n"),HW_ICOLL_VECTOR_RD()));

            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_STAT_RD() = %x \r\n"),HW_ICOLL_STAT_RD()));        
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_VBASE_RD() = %x \r\n"),HW_ICOLL_VBASE_RD()));        
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_CTRL_RD() = %x \r\n"),HW_ICOLL_CTRL_RD()));        
            
            
            
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_RAWn_RD0 = %x \r\n"),HW_ICOLL_RAWn_RD(0)));        
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_RAWn_RD1 = %x \r\n"),HW_ICOLL_RAWn_RD(1)));        
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_RAWn_RD2 = %x \r\n"),HW_ICOLL_RAWn_RD(2)));        
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_RAWn_RD3 = %x \r\n"),HW_ICOLL_RAWn_RD(3)));        

            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_DBGREAD0_RD = %x \r\n"),HW_ICOLL_DBGREAD0_RD()));        
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_DBGREAD1_RD = %x \r\n"),HW_ICOLL_DBGREAD1_RD()));        


            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_DBGREQUESTn_RD(0) = %x \r\n"),HW_ICOLL_DBGREQUESTn_RD(0)));                    
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_DBGREQUESTn_RD(1) = %x \r\n"),HW_ICOLL_DBGREQUESTn_RD(1)));        
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_DBGREQUESTn_RD(2) = %x \r\n"),HW_ICOLL_DBGREQUESTn_RD(2)));                    
            OALMSGS(OAL_ERROR,(TEXT("OEMInterruptHandler:  HW_ICOLL_DBGREQUESTn_RD(3) = %x \r\n"),HW_ICOLL_DBGREQUESTn_RD(3)));        

			
			

	{
 	int ii=0;
    
    	for (ii=0;ii<128;ii++)
    		OALMSG(1, (L"HW_ICOLL_INTERRUPTn_RD(%d)=%x\r\n",ii,HW_ICOLL_INTERRUPTn_RD(ii)));
	}

//EAI====================================        
        }
    } // Else not system timer interrupt

    dwLevel = HW_ICOLL_INTERRUPTn_RD(irq) & BM_ICOLL_INTERRUPTn_PRIORITY;

    // Clear Interrupt
    HW_ICOLL_LEVELACK_SET(1 << dwLevel);

    return sysIntr;
}