Setup Overview:
IFC Bus Configuration:

The IFC bus is connected to the FPGA.
Upon negation of PORESET, the Reset Configuration Word (RCW) value {IFC_AD[8:15], IFC_CLE} = 9'b010011101 is assigned.
Reset Signals from JTAG:

The JTAG interface provides the following reset signals to the FPGA:
jtag_hrst (Hardware Reset)
jtag_srst (Software Reset)
jtag_trst (Target Reset)
These signals are routed through FPGA logic and assigned to the processor.
Reset Control Logic:

The processor’s reset signals are governed by the following equations:

PORESET (Power-On Reset):

PORESET = jtag_hrst & jtag_srst & req_rst_r
Explanation: PORESET is negated (inactive) if either the JTAG hardware reset (jtag_hrst) or software reset (jtag_srst) is negated, or if the reset request signal (req_rst_r) is active low.

HRESET_N (Hardware Reset):

HRESET_N = ((PORESET) ? req_rst_r : 1'b1) ? 1'b1 : 1'b0
Explanation: HRESET_N is asserted low (active) when both PORESET is asserted and req_rst_r is active. Otherwise, HRESET_N remains high (inactive).

TRST (Test Reset):

trst_out = req_rst_r & jtag_trstin
Explanation: TRST is negated (inactive) if either req_rst_r or the JTAG TRST input (jtag_trstin) is inactive.

Reset Request Signal (req_rst_r):

This signal is active low and is generated following the assertion of RESET_REQUEST.
It is crucial in determining whether PORESET, HRESET_N, and TRST are asserted or negated.