From f552dfd32c8b0380e6a3444bff45664ce8aee252 Mon Sep 17 00:00:00 2001
From: Shaojun Wang <shaojun.wang@nxp.com>
Date: Mon, 15 Aug 2022 14:56:12 +0800
Subject: [PATCH 2/4] resolve download error and upgrade toolchain to 2022.04

---
 .../micro/tools/make/download_and_extract.sh  |  25 +-
 .../make/targets/xtensa_hifi_makefile.inc     |   2 +-
 .../memmap/imx8/ldscripts/elf32xtensa.x       | 681 ++++++++++++++++++
 .../memmap/imx8/ldscripts/elf32xtensa.xbn     | 681 ++++++++++++++++++
 .../memmap/imx8/ldscripts/elf32xtensa.xn      | 681 ++++++++++++++++++
 .../memmap/imx8/ldscripts/elf32xtensa.xr      |  61 ++
 .../memmap/imx8/ldscripts/elf32xtensa.xu      |  61 ++
 .../micro/xtensa_hifi/memmap/imx8/memmap.xmm  |  93 +++
 .../micro/xtensa_hifi/memmap/imx8/sim.parm    |  23 +
 .../lite/micro/xtensa_hifi/memmap/imx8/specs  |  36 +
 .../memmap/imx8m/ldscripts/elf32xtensa.x      | 681 ++++++++++++++++++
 .../memmap/imx8m/ldscripts/elf32xtensa.xbn    | 681 ++++++++++++++++++
 .../memmap/imx8m/ldscripts/elf32xtensa.xn     | 681 ++++++++++++++++++
 .../memmap/imx8m/ldscripts/elf32xtensa.xr     |  61 ++
 .../memmap/imx8m/ldscripts/elf32xtensa.xu     |  61 ++
 .../micro/xtensa_hifi/memmap/imx8m/memmap.xmm |  93 +++
 .../micro/xtensa_hifi/memmap/imx8m/sim.parm   |  23 +
 .../lite/micro/xtensa_hifi/memmap/imx8m/specs |  36 +
 .../memmap/imx8ulp/ldscripts/elf32xtensa.x    | 630 ++++++++++++++++
 .../memmap/imx8ulp/ldscripts/elf32xtensa.xbn  | 630 ++++++++++++++++
 .../memmap/imx8ulp/ldscripts/elf32xtensa.xn   | 630 ++++++++++++++++
 .../memmap/imx8ulp/ldscripts/elf32xtensa.xr   |  61 ++
 .../memmap/imx8ulp/ldscripts/elf32xtensa.xu   |  61 ++
 .../xtensa_hifi/memmap/imx8ulp/memmap.xmm     |  93 +++
 .../micro/xtensa_hifi/memmap/imx8ulp/specs    |  36 +
 25 files changed, 6777 insertions(+), 25 deletions(-)
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.x
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xbn
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xn
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xr
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xu
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8/memmap.xmm
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8/sim.parm
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8/specs
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.x
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xbn
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xn
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xr
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xu
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/memmap.xmm
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/sim.parm
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/specs
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.x
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xbn
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xn
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xr
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xu
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/memmap.xmm
 create mode 100644 tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/specs

diff --git a/tensorflow/lite/micro/tools/make/download_and_extract.sh b/tensorflow/lite/micro/tools/make/download_and_extract.sh
index 6eff18690f0..c0dae01bc62 100755
--- a/tensorflow/lite/micro/tools/make/download_and_extract.sh
+++ b/tensorflow/lite/micro/tools/make/download_and_extract.sh
@@ -129,31 +129,8 @@ download_and_extract() {
 
   echo "downloading ${url}" >&2
   mkdir -p "${dir}"
-  # We've been seeing occasional 56 errors from valid URLs, so set up a retry
-  # loop to attempt to recover from them.
-  for (( i=1; i<=$curl_retries; ++i ))
-  do
-    # We have to use this approach because we normally halt the script when
-    # there's an error, and instead we want to catch errors so we can retry.
-    set +e
-    curl -Ls --fail --retry 5 "${url}" > ${tempfile}
-    CURL_RESULT=$?
-    set -e
-
-    # Was the command successful? If so, continue.
-    if [[ $CURL_RESULT -eq 0 ]]
-    then
-      break
-    fi
 
-    # Keep trying if we see the '56' error code.
-    if [[ ( $CURL_RESULT -ne 56 ) || ( $i -eq $curl_retries ) ]]
-    then
-      echo "Error $CURL_RESULT downloading '${url}'"
-      exit 1
-    fi
-    sleep 2
-  done
+  wget ${url} -O ${tempfile}
 
   # Check that the file was downloaded correctly using a checksum.
   DOWNLOADED_MD5=$(openssl dgst -md5 ${tempfile} | sed 's/.* //g')
diff --git a/tensorflow/lite/micro/tools/make/targets/xtensa_hifi_makefile.inc b/tensorflow/lite/micro/tools/make/targets/xtensa_hifi_makefile.inc
index 67ee65b8a4d..6b0259e7833 100644
--- a/tensorflow/lite/micro/tools/make/targets/xtensa_hifi_makefile.inc
+++ b/tensorflow/lite/micro/tools/make/targets/xtensa_hifi_makefile.inc
@@ -68,7 +68,7 @@ $(eval $(call add_third_party_download,$(XTENSA_HIFI5_URL),$(XTENSA_HIFI5_MD5),x
 
   # Enable sim-local for local RAM based setups 
   #LDFLAGS += -mlsp=sim-local
-  LINK_DIR = $(XTENSA_BASE)builds/$(XTENSA_TOOLS_VERSION)/$(XTENSA_CORE)/xtensa-elf/lib/mainsim
+  LINK_DIR = tensorflow/lite/micro/xtensa_hifi/memmap/$(PLATF)
   LDFLAGS += -mlsp=$(LINK_DIR)
 
   TEST_SCRIPT := tensorflow/lite/micro/testing/test_xtensa_hifi_binary.sh
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.x b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.x
new file mode 100644
index 00000000000..b4ad6809faf
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.x
@@ -0,0 +1,681 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for default link */
+MEMORY
+{
+  dram0_0_seg :                       	org = 0x596E8000, len = 0x8000
+  dram1_0_seg :                       	org = 0x596F0000, len = 0x8000
+  iram0_0_seg :                       	org = 0x596F8000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x596F8400, len = 0x178
+  iram0_3_seg :                       	org = 0x596F8578, len = 0x4
+  iram0_4_seg :                       	org = 0x596F857C, len = 0x1C
+  iram0_5_seg :                       	org = 0x596F8598, len = 0x4
+  iram0_6_seg :                       	org = 0x596F859C, len = 0x1C
+  iram0_7_seg :                       	org = 0x596F85B8, len = 0x4
+  iram0_8_seg :                       	org = 0x596F85BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x596F85D8, len = 0x4
+  iram0_10_seg :                      	org = 0x596F85DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x596F85F8, len = 0x4
+  iram0_12_seg :                      	org = 0x596F85FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x596F8618, len = 0x4
+  iram0_14_seg :                      	org = 0x596F861C, len = 0x1C
+  iram0_15_seg :                      	org = 0x596F8638, len = 0x4
+  iram0_16_seg :                      	org = 0x596F863C, len = 0x1C
+  iram0_17_seg :                      	org = 0x596F8658, len = 0x1A8
+  sram0_seg :                         	org = 0x92400000, len = 0x800000
+  srom0_seg :                         	org = 0x92C00000, len = 0x700000
+}
+
+PHDRS
+{
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+  dram1_0_phdr PT_LOAD;
+  dram1_0_bss_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_dram0_start = 0x596e8000;
+_memmap_mem_dram0_end   = 0x596f0000;
+_memmap_mem_dram1_start = 0x596f0000;
+_memmap_mem_dram1_end   = 0x596f8000;
+_memmap_mem_iram0_start = 0x596f8000;
+_memmap_mem_iram0_end   = 0x596f8800;
+_memmap_mem_sram_start = 0x92400000;
+_memmap_mem_sram_end   = 0x92c00000;
+_memmap_mem_srom_start = 0x92c00000;
+_memmap_mem_srom_end   = 0x93300000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_dram0_0_start = 0x596e8000;
+_memmap_seg_dram0_0_max   = 0x596f0000;
+_memmap_seg_dram1_0_start = 0x596f0000;
+_memmap_seg_dram1_0_max   = 0x596f8000;
+_memmap_seg_iram0_0_start = 0x596f8000;
+_memmap_seg_iram0_0_max   = 0x596f82e0;
+_memmap_seg_iram0_2_start = 0x596f8400;
+_memmap_seg_iram0_2_max   = 0x596f8578;
+_memmap_seg_iram0_3_start = 0x596f8578;
+_memmap_seg_iram0_3_max   = 0x596f857c;
+_memmap_seg_iram0_4_start = 0x596f857c;
+_memmap_seg_iram0_4_max   = 0x596f8598;
+_memmap_seg_iram0_5_start = 0x596f8598;
+_memmap_seg_iram0_5_max   = 0x596f859c;
+_memmap_seg_iram0_6_start = 0x596f859c;
+_memmap_seg_iram0_6_max   = 0x596f85b8;
+_memmap_seg_iram0_7_start = 0x596f85b8;
+_memmap_seg_iram0_7_max   = 0x596f85bc;
+_memmap_seg_iram0_8_start = 0x596f85bc;
+_memmap_seg_iram0_8_max   = 0x596f85d8;
+_memmap_seg_iram0_9_start = 0x596f85d8;
+_memmap_seg_iram0_9_max   = 0x596f85dc;
+_memmap_seg_iram0_10_start = 0x596f85dc;
+_memmap_seg_iram0_10_max   = 0x596f85f8;
+_memmap_seg_iram0_11_start = 0x596f85f8;
+_memmap_seg_iram0_11_max   = 0x596f85fc;
+_memmap_seg_iram0_12_start = 0x596f85fc;
+_memmap_seg_iram0_12_max   = 0x596f8618;
+_memmap_seg_iram0_13_start = 0x596f8618;
+_memmap_seg_iram0_13_max   = 0x596f861c;
+_memmap_seg_iram0_14_start = 0x596f861c;
+_memmap_seg_iram0_14_max   = 0x596f8638;
+_memmap_seg_iram0_15_start = 0x596f8638;
+_memmap_seg_iram0_15_max   = 0x596f863c;
+_memmap_seg_iram0_16_start = 0x596f863c;
+_memmap_seg_iram0_16_max   = 0x596f8658;
+_memmap_seg_iram0_17_start = 0x596f8658;
+_memmap_seg_iram0_17_max   = 0x596f8800;
+_memmap_seg_sram0_start = 0x92400000;
+_memmap_seg_sram0_max   = 0x92c00000;
+_memmap_seg_srom0_start = 0x92c00000;
+_memmap_seg_srom0_max   = 0x93300000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x596f8000);
+PROVIDE(_memmap_vecbase_reset = 0x596f8400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00040200;
+_memmap_cacheattr_wt_base = 0x00010200;
+_memmap_cacheattr_bp_base = 0x00020200;
+_memmap_cacheattr_unused_mask = 0xFFF0F0FF;
+_memmap_cacheattr_wb_trapnull = 0x2224222F;
+_memmap_cacheattr_wba_trapnull = 0x2224222F;
+_memmap_cacheattr_wbna_trapnull = 0x2225222F;
+_memmap_cacheattr_wt_trapnull = 0x2221222F;
+_memmap_cacheattr_bp_trapnull = 0x2222222F;
+_memmap_cacheattr_wb_strict = 0xFFF4F2FF;
+_memmap_cacheattr_wt_strict = 0xFFF1F2FF;
+_memmap_cacheattr_bp_strict = 0xFFF2F2FF;
+_memmap_cacheattr_wb_allvalid = 0x22242222;
+_memmap_cacheattr_wt_allvalid = 0x22212222;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000014;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.literal : ALIGN(4)
+  {
+    _dram0_literal_start = ABSOLUTE(.);
+    *(.dram0.literal)
+    . = ALIGN (4);
+    _dram0_literal_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .dram1.rodata : ALIGN(4)
+  {
+    _dram1_rodata_start = ABSOLUTE(.);
+    *(.dram1.rodata)
+    . = ALIGN (4);
+    _dram1_rodata_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.literal : ALIGN(4)
+  {
+    _dram1_literal_start = ABSOLUTE(.);
+    *(.dram1.literal)
+    . = ALIGN (4);
+    _dram1_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .ResetVector.literal : ALIGN(4)
+  {
+    _ResetVector_literal_start = ABSOLUTE(.);
+    *(.ResetVector.literal)
+    . = ALIGN (4);
+    _ResetVector_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.data : ALIGN(4)
+  {
+    _dram1_data_start = ABSOLUTE(.);
+    *(.dram1.data)
+    . = ALIGN (4);
+    _dram1_data_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram1_bss_start = ABSOLUTE(.);
+    *(.dram1.bss)
+    . = ALIGN (8);
+    _dram1_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram1_0_end = ALIGN(0x8);
+  } >dram1_0_seg :dram1_0_bss_phdr
+
+  _memmap_mem_dram1_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    LONG(_dram1_bss_start)
+    LONG(_dram1_bss_end)
+    LONG(_bss_start)
+    LONG(_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x92c00000);
+  _heap_sentry = 0x92c00000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xbn b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xbn
new file mode 100644
index 00000000000..8cbd944ca21
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xbn
@@ -0,0 +1,681 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -N */
+MEMORY
+{
+  dram0_0_seg :                       	org = 0x596E8000, len = 0x8000
+  dram1_0_seg :                       	org = 0x596F0000, len = 0x8000
+  iram0_0_seg :                       	org = 0x596F8000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x596F8400, len = 0x178
+  iram0_3_seg :                       	org = 0x596F8578, len = 0x4
+  iram0_4_seg :                       	org = 0x596F857C, len = 0x1C
+  iram0_5_seg :                       	org = 0x596F8598, len = 0x4
+  iram0_6_seg :                       	org = 0x596F859C, len = 0x1C
+  iram0_7_seg :                       	org = 0x596F85B8, len = 0x4
+  iram0_8_seg :                       	org = 0x596F85BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x596F85D8, len = 0x4
+  iram0_10_seg :                      	org = 0x596F85DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x596F85F8, len = 0x4
+  iram0_12_seg :                      	org = 0x596F85FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x596F8618, len = 0x4
+  iram0_14_seg :                      	org = 0x596F861C, len = 0x1C
+  iram0_15_seg :                      	org = 0x596F8638, len = 0x4
+  iram0_16_seg :                      	org = 0x596F863C, len = 0x1C
+  iram0_17_seg :                      	org = 0x596F8658, len = 0x1A8
+  sram0_seg :                         	org = 0x92400000, len = 0x800000
+  srom0_seg :                         	org = 0x92C00000, len = 0x700000
+}
+
+PHDRS
+{
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+  dram1_0_phdr PT_LOAD;
+  dram1_0_bss_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_dram0_start = 0x596e8000;
+_memmap_mem_dram0_end   = 0x596f0000;
+_memmap_mem_dram1_start = 0x596f0000;
+_memmap_mem_dram1_end   = 0x596f8000;
+_memmap_mem_iram0_start = 0x596f8000;
+_memmap_mem_iram0_end   = 0x596f8800;
+_memmap_mem_sram_start = 0x92400000;
+_memmap_mem_sram_end   = 0x92c00000;
+_memmap_mem_srom_start = 0x92c00000;
+_memmap_mem_srom_end   = 0x93300000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_dram0_0_start = 0x596e8000;
+_memmap_seg_dram0_0_max   = 0x596f0000;
+_memmap_seg_dram1_0_start = 0x596f0000;
+_memmap_seg_dram1_0_max   = 0x596f8000;
+_memmap_seg_iram0_0_start = 0x596f8000;
+_memmap_seg_iram0_0_max   = 0x596f82e0;
+_memmap_seg_iram0_2_start = 0x596f8400;
+_memmap_seg_iram0_2_max   = 0x596f8578;
+_memmap_seg_iram0_3_start = 0x596f8578;
+_memmap_seg_iram0_3_max   = 0x596f857c;
+_memmap_seg_iram0_4_start = 0x596f857c;
+_memmap_seg_iram0_4_max   = 0x596f8598;
+_memmap_seg_iram0_5_start = 0x596f8598;
+_memmap_seg_iram0_5_max   = 0x596f859c;
+_memmap_seg_iram0_6_start = 0x596f859c;
+_memmap_seg_iram0_6_max   = 0x596f85b8;
+_memmap_seg_iram0_7_start = 0x596f85b8;
+_memmap_seg_iram0_7_max   = 0x596f85bc;
+_memmap_seg_iram0_8_start = 0x596f85bc;
+_memmap_seg_iram0_8_max   = 0x596f85d8;
+_memmap_seg_iram0_9_start = 0x596f85d8;
+_memmap_seg_iram0_9_max   = 0x596f85dc;
+_memmap_seg_iram0_10_start = 0x596f85dc;
+_memmap_seg_iram0_10_max   = 0x596f85f8;
+_memmap_seg_iram0_11_start = 0x596f85f8;
+_memmap_seg_iram0_11_max   = 0x596f85fc;
+_memmap_seg_iram0_12_start = 0x596f85fc;
+_memmap_seg_iram0_12_max   = 0x596f8618;
+_memmap_seg_iram0_13_start = 0x596f8618;
+_memmap_seg_iram0_13_max   = 0x596f861c;
+_memmap_seg_iram0_14_start = 0x596f861c;
+_memmap_seg_iram0_14_max   = 0x596f8638;
+_memmap_seg_iram0_15_start = 0x596f8638;
+_memmap_seg_iram0_15_max   = 0x596f863c;
+_memmap_seg_iram0_16_start = 0x596f863c;
+_memmap_seg_iram0_16_max   = 0x596f8658;
+_memmap_seg_iram0_17_start = 0x596f8658;
+_memmap_seg_iram0_17_max   = 0x596f8800;
+_memmap_seg_sram0_start = 0x92400000;
+_memmap_seg_sram0_max   = 0x92c00000;
+_memmap_seg_srom0_start = 0x92c00000;
+_memmap_seg_srom0_max   = 0x93300000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x596f8000);
+PROVIDE(_memmap_vecbase_reset = 0x596f8400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00040200;
+_memmap_cacheattr_wt_base = 0x00010200;
+_memmap_cacheattr_bp_base = 0x00020200;
+_memmap_cacheattr_unused_mask = 0xFFF0F0FF;
+_memmap_cacheattr_wb_trapnull = 0x2224222F;
+_memmap_cacheattr_wba_trapnull = 0x2224222F;
+_memmap_cacheattr_wbna_trapnull = 0x2225222F;
+_memmap_cacheattr_wt_trapnull = 0x2221222F;
+_memmap_cacheattr_bp_trapnull = 0x2222222F;
+_memmap_cacheattr_wb_strict = 0xFFF4F2FF;
+_memmap_cacheattr_wt_strict = 0xFFF1F2FF;
+_memmap_cacheattr_bp_strict = 0xFFF2F2FF;
+_memmap_cacheattr_wb_allvalid = 0x22242222;
+_memmap_cacheattr_wt_allvalid = 0x22212222;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000014;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.literal : ALIGN(4)
+  {
+    _dram0_literal_start = ABSOLUTE(.);
+    *(.dram0.literal)
+    . = ALIGN (4);
+    _dram0_literal_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .dram1.rodata : ALIGN(4)
+  {
+    _dram1_rodata_start = ABSOLUTE(.);
+    *(.dram1.rodata)
+    . = ALIGN (4);
+    _dram1_rodata_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.literal : ALIGN(4)
+  {
+    _dram1_literal_start = ABSOLUTE(.);
+    *(.dram1.literal)
+    . = ALIGN (4);
+    _dram1_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .ResetVector.literal : ALIGN(4)
+  {
+    _ResetVector_literal_start = ABSOLUTE(.);
+    *(.ResetVector.literal)
+    . = ALIGN (4);
+    _ResetVector_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.data : ALIGN(4)
+  {
+    _dram1_data_start = ABSOLUTE(.);
+    *(.dram1.data)
+    . = ALIGN (4);
+    _dram1_data_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram1_bss_start = ABSOLUTE(.);
+    *(.dram1.bss)
+    . = ALIGN (8);
+    _dram1_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram1_0_end = ALIGN(0x8);
+  } >dram1_0_seg :dram1_0_bss_phdr
+
+  _memmap_mem_dram1_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    LONG(_dram1_bss_start)
+    LONG(_dram1_bss_end)
+    LONG(_bss_start)
+    LONG(_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x92c00000);
+  _heap_sentry = 0x92c00000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xn b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xn
new file mode 100644
index 00000000000..c8f6b6d3c33
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xn
@@ -0,0 +1,681 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -n */
+MEMORY
+{
+  dram0_0_seg :                       	org = 0x596E8000, len = 0x8000
+  dram1_0_seg :                       	org = 0x596F0000, len = 0x8000
+  iram0_0_seg :                       	org = 0x596F8000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x596F8400, len = 0x178
+  iram0_3_seg :                       	org = 0x596F8578, len = 0x4
+  iram0_4_seg :                       	org = 0x596F857C, len = 0x1C
+  iram0_5_seg :                       	org = 0x596F8598, len = 0x4
+  iram0_6_seg :                       	org = 0x596F859C, len = 0x1C
+  iram0_7_seg :                       	org = 0x596F85B8, len = 0x4
+  iram0_8_seg :                       	org = 0x596F85BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x596F85D8, len = 0x4
+  iram0_10_seg :                      	org = 0x596F85DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x596F85F8, len = 0x4
+  iram0_12_seg :                      	org = 0x596F85FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x596F8618, len = 0x4
+  iram0_14_seg :                      	org = 0x596F861C, len = 0x1C
+  iram0_15_seg :                      	org = 0x596F8638, len = 0x4
+  iram0_16_seg :                      	org = 0x596F863C, len = 0x1C
+  iram0_17_seg :                      	org = 0x596F8658, len = 0x1A8
+  sram0_seg :                         	org = 0x92400000, len = 0x800000
+  srom0_seg :                         	org = 0x92C00000, len = 0x700000
+}
+
+PHDRS
+{
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+  dram1_0_phdr PT_LOAD;
+  dram1_0_bss_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_dram0_start = 0x596e8000;
+_memmap_mem_dram0_end   = 0x596f0000;
+_memmap_mem_dram1_start = 0x596f0000;
+_memmap_mem_dram1_end   = 0x596f8000;
+_memmap_mem_iram0_start = 0x596f8000;
+_memmap_mem_iram0_end   = 0x596f8800;
+_memmap_mem_sram_start = 0x92400000;
+_memmap_mem_sram_end   = 0x92c00000;
+_memmap_mem_srom_start = 0x92c00000;
+_memmap_mem_srom_end   = 0x93300000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_dram0_0_start = 0x596e8000;
+_memmap_seg_dram0_0_max   = 0x596f0000;
+_memmap_seg_dram1_0_start = 0x596f0000;
+_memmap_seg_dram1_0_max   = 0x596f8000;
+_memmap_seg_iram0_0_start = 0x596f8000;
+_memmap_seg_iram0_0_max   = 0x596f82e0;
+_memmap_seg_iram0_2_start = 0x596f8400;
+_memmap_seg_iram0_2_max   = 0x596f8578;
+_memmap_seg_iram0_3_start = 0x596f8578;
+_memmap_seg_iram0_3_max   = 0x596f857c;
+_memmap_seg_iram0_4_start = 0x596f857c;
+_memmap_seg_iram0_4_max   = 0x596f8598;
+_memmap_seg_iram0_5_start = 0x596f8598;
+_memmap_seg_iram0_5_max   = 0x596f859c;
+_memmap_seg_iram0_6_start = 0x596f859c;
+_memmap_seg_iram0_6_max   = 0x596f85b8;
+_memmap_seg_iram0_7_start = 0x596f85b8;
+_memmap_seg_iram0_7_max   = 0x596f85bc;
+_memmap_seg_iram0_8_start = 0x596f85bc;
+_memmap_seg_iram0_8_max   = 0x596f85d8;
+_memmap_seg_iram0_9_start = 0x596f85d8;
+_memmap_seg_iram0_9_max   = 0x596f85dc;
+_memmap_seg_iram0_10_start = 0x596f85dc;
+_memmap_seg_iram0_10_max   = 0x596f85f8;
+_memmap_seg_iram0_11_start = 0x596f85f8;
+_memmap_seg_iram0_11_max   = 0x596f85fc;
+_memmap_seg_iram0_12_start = 0x596f85fc;
+_memmap_seg_iram0_12_max   = 0x596f8618;
+_memmap_seg_iram0_13_start = 0x596f8618;
+_memmap_seg_iram0_13_max   = 0x596f861c;
+_memmap_seg_iram0_14_start = 0x596f861c;
+_memmap_seg_iram0_14_max   = 0x596f8638;
+_memmap_seg_iram0_15_start = 0x596f8638;
+_memmap_seg_iram0_15_max   = 0x596f863c;
+_memmap_seg_iram0_16_start = 0x596f863c;
+_memmap_seg_iram0_16_max   = 0x596f8658;
+_memmap_seg_iram0_17_start = 0x596f8658;
+_memmap_seg_iram0_17_max   = 0x596f8800;
+_memmap_seg_sram0_start = 0x92400000;
+_memmap_seg_sram0_max   = 0x92c00000;
+_memmap_seg_srom0_start = 0x92c00000;
+_memmap_seg_srom0_max   = 0x93300000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x596f8000);
+PROVIDE(_memmap_vecbase_reset = 0x596f8400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00040200;
+_memmap_cacheattr_wt_base = 0x00010200;
+_memmap_cacheattr_bp_base = 0x00020200;
+_memmap_cacheattr_unused_mask = 0xFFF0F0FF;
+_memmap_cacheattr_wb_trapnull = 0x2224222F;
+_memmap_cacheattr_wba_trapnull = 0x2224222F;
+_memmap_cacheattr_wbna_trapnull = 0x2225222F;
+_memmap_cacheattr_wt_trapnull = 0x2221222F;
+_memmap_cacheattr_bp_trapnull = 0x2222222F;
+_memmap_cacheattr_wb_strict = 0xFFF4F2FF;
+_memmap_cacheattr_wt_strict = 0xFFF1F2FF;
+_memmap_cacheattr_bp_strict = 0xFFF2F2FF;
+_memmap_cacheattr_wb_allvalid = 0x22242222;
+_memmap_cacheattr_wt_allvalid = 0x22212222;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000014;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.literal : ALIGN(4)
+  {
+    _dram0_literal_start = ABSOLUTE(.);
+    *(.dram0.literal)
+    . = ALIGN (4);
+    _dram0_literal_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .dram1.rodata : ALIGN(4)
+  {
+    _dram1_rodata_start = ABSOLUTE(.);
+    *(.dram1.rodata)
+    . = ALIGN (4);
+    _dram1_rodata_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.literal : ALIGN(4)
+  {
+    _dram1_literal_start = ABSOLUTE(.);
+    *(.dram1.literal)
+    . = ALIGN (4);
+    _dram1_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .ResetVector.literal : ALIGN(4)
+  {
+    _ResetVector_literal_start = ABSOLUTE(.);
+    *(.ResetVector.literal)
+    . = ALIGN (4);
+    _ResetVector_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.data : ALIGN(4)
+  {
+    _dram1_data_start = ABSOLUTE(.);
+    *(.dram1.data)
+    . = ALIGN (4);
+    _dram1_data_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram1_bss_start = ABSOLUTE(.);
+    *(.dram1.bss)
+    . = ALIGN (8);
+    _dram1_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram1_0_end = ALIGN(0x8);
+  } >dram1_0_seg :dram1_0_bss_phdr
+
+  _memmap_mem_dram1_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    LONG(_dram1_bss_start)
+    LONG(_dram1_bss_end)
+    LONG(_bss_start)
+    LONG(_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x92c00000);
+  _heap_sentry = 0x92c00000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xr b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xr
new file mode 100644
index 00000000000..4a59d9768a3
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xr
@@ -0,0 +1,61 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -r or ld -i */
+
+
+SECTIONS
+{
+
+  .text 0 :
+  {
+    *(.literal .text)
+  }
+
+  .bss 0 :
+  {
+    *(.dynsbss)
+    *(.sbss)
+    *(.scommon)
+    *(.dynbss)
+    *(.bss)
+    *(COMMON)
+  }
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xu b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xu
new file mode 100644
index 00000000000..62a3382fb53
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/ldscripts/elf32xtensa.xu
@@ -0,0 +1,61 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -Ur */
+
+
+SECTIONS
+{
+
+  .text 0 :
+  {
+    *(.literal .text)
+  }
+
+  .bss 0 :
+  {
+    *(.dynsbss)
+    *(.sbss)
+    *(.scommon)
+    *(.dynbss)
+    *(.bss)
+    *(COMMON)
+  }
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/memmap.xmm b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/memmap.xmm
new file mode 100644
index 00000000000..ba8b49b026e
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/memmap.xmm
@@ -0,0 +1,93 @@
+//  Memory map file to generate linker scripts for programs run on the ISS.
+
+// Customer ID=12445; Build=0x6ded3; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+// A memory map is a sequence of memory descriptions and
+// optional parameter assignments.
+//
+// Each memory description has the following format:
+//   BEGIN <name>
+//     <addr> [,<paddr>] : <mem-type> : <mem-name> : <size> [,<psize>]
+//                       : [writable] [,executable] [,device] ;
+//     <segment>*
+//   END <name>
+//
+// where each <segment> description has the following format:
+//     <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
+//                : <section-name>* ;
+//
+// Each parameter assignment is a keyword/value pair in the following format:
+//   <keyword> = <value>                (no spaces in <value>)
+// or
+//   <keyword> = "<value>"              (spaces allowed in <value>)
+//
+// The following primitives are also defined:
+//   PLACE SECTIONS( <section-name>* ) { WITH_SECTION(<section-name>)
+//                                       | IN_SEGMENT(<seg-name>) }
+//
+//   NOLOAD <section-name1> [ <section-name2> ... ]
+//
+// Please refer to the Xtensa LSP Reference Manual for more details.
+//
+BEGIN dram0
+0x596e8000: dataRam : dram0 : 0x8000 : writable ;
+ dram0_0 : C : 0x596e8000 - 0x596effff : .dram0.rodata .dram0.literal .dram0.data .dram0.bss;
+END dram0
+
+BEGIN dram1
+0x596f0000: dataRam : dram1 : 0x8000 : writable ;
+ dram1_0 : C : 0x596f0000 - 0x596f7fff : .dram1.rodata .dram1.literal .ResetVector.literal .dram1.data .dram1.bss;
+END dram1
+
+BEGIN iram0
+0x596f8000: instRam : iram0 : 0x800 : executable, writable ;
+ iram0_0 : F : 0x596f8000 - 0x596f82df : .ResetVector.text;
+ iram0_1 : C : 0x596f82e0 - 0x596f83ff : ;
+ iram0_2 : F : 0x596f8400 - 0x596f8577 : .WindowVectors.text;
+ iram0_3 : C : 0x596f8578 - 0x596f857b : .Level2InterruptVector.literal;
+ iram0_4 : F : 0x596f857c - 0x596f8597 : .Level2InterruptVector.text;
+ iram0_5 : C : 0x596f8598 - 0x596f859b : .Level3InterruptVector.literal;
+ iram0_6 : F : 0x596f859c - 0x596f85b7 : .Level3InterruptVector.text;
+ iram0_7 : C : 0x596f85b8 - 0x596f85bb : .DebugExceptionVector.literal;
+ iram0_8 : F : 0x596f85bc - 0x596f85d7 : .DebugExceptionVector.text;
+ iram0_9 : C : 0x596f85d8 - 0x596f85db : .NMIExceptionVector.literal;
+ iram0_10 : F : 0x596f85dc - 0x596f85f7 : .NMIExceptionVector.text;
+ iram0_11 : C : 0x596f85f8 - 0x596f85fb : .KernelExceptionVector.literal;
+ iram0_12 : F : 0x596f85fc - 0x596f8617 : .KernelExceptionVector.text;
+ iram0_13 : C : 0x596f8618 - 0x596f861b : .UserExceptionVector.literal;
+ iram0_14 : F : 0x596f861c - 0x596f8637 : .UserExceptionVector.text;
+ iram0_15 : C : 0x596f8638 - 0x596f863b : .DoubleExceptionVector.literal;
+ iram0_16 : F : 0x596f863c - 0x596f8657 : .DoubleExceptionVector.text;
+ iram0_17 : C : 0x596f8658 - 0x596f87ff : .iram0.literal .iram0.text;
+END iram0
+
+BEGIN sram
+0x92400000: sysram : sram : 0x800000 : executable, writable ;
+ sram0 : C : 0x92400000 - 0x92bfffff :  STACK :  HEAP : .sram.rodata .clib.rodata .rtos.rodata .rodata .sram.literal .literal .rtos.literal .clib.literal .sram.text .text .clib.text .rtos.text .clib.data .clib.percpu.data .rtos.percpu.data .rtos.data .sram.data .data __llvm_prf_names .resource_table .clib.bss .clib.percpu.bss .rtos.percpu.bss .rtos.bss .sram.bss .bss;
+END sram
+
+BEGIN srom
+0x92c00000: sysrom : srom : 0x700000 : executable ;
+ srom0 : C : 0x92c00000 - 0x932fffff : .srom.rodata .srom.literal .srom.text .rom.store;
+END srom
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/sim.parm b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/sim.parm
new file mode 100644
index 00000000000..d6cefe0c31e
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/sim.parm
@@ -0,0 +1,23 @@
+//  Memory map file to generate linker scripts for programs run on the ISS.
+
+// Customer ID=12445; Build=0x6ded3; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/specs b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/specs
new file mode 100644
index 00000000000..870f4a07234
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8/specs
@@ -0,0 +1,36 @@
+# Customer ID=12445; Build=0x6ded3; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+# The %O suffix on the start and end files indicates that the system's
+# standard suffix for object files (e.g., ".o") should be appended.
+# The %s suffix tells the compiler driver to search for the file in the
+# list of known locations for startfiles.
+
+*startfile:
+crt1-sim%O%s crti%O%s crtbegin%O%s _sharedvectors%O%s _vectors%O%s
+
+*endfile:
+crtend%O%s crtn%O%s
+
+*lib:
+-lc -lsim -lc -lhandler-reset -lhandlers-sim -lhal -lc
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.x b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.x
new file mode 100644
index 00000000000..4ffb24272b0
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.x
@@ -0,0 +1,681 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for default link */
+MEMORY
+{
+  dram0_0_seg :                       	org = 0x3B6E8000, len = 0x8000
+  dram1_0_seg :                       	org = 0x3B6F0000, len = 0x8000
+  iram0_0_seg :                       	org = 0x3B6F8000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x3B6F8400, len = 0x178
+  iram0_3_seg :                       	org = 0x3B6F8578, len = 0x4
+  iram0_4_seg :                       	org = 0x3B6F857C, len = 0x1C
+  iram0_5_seg :                       	org = 0x3B6F8598, len = 0x4
+  iram0_6_seg :                       	org = 0x3B6F859C, len = 0x1C
+  iram0_7_seg :                       	org = 0x3B6F85B8, len = 0x4
+  iram0_8_seg :                       	org = 0x3B6F85BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x3B6F85D8, len = 0x4
+  iram0_10_seg :                      	org = 0x3B6F85DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x3B6F85F8, len = 0x4
+  iram0_12_seg :                      	org = 0x3B6F85FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x3B6F8618, len = 0x4
+  iram0_14_seg :                      	org = 0x3B6F861C, len = 0x1C
+  iram0_15_seg :                      	org = 0x3B6F8638, len = 0x4
+  iram0_16_seg :                      	org = 0x3B6F863C, len = 0x1C
+  iram0_17_seg :                      	org = 0x3B6F8658, len = 0x1A8
+  sram0_seg :                         	org = 0x92400000, len = 0x800000
+  srom0_seg :                         	org = 0x92C00000, len = 0x700000
+}
+
+PHDRS
+{
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+  dram1_0_phdr PT_LOAD;
+  dram1_0_bss_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_dram0_start = 0x3b6e8000;
+_memmap_mem_dram0_end   = 0x3b6f0000;
+_memmap_mem_dram1_start = 0x3b6f0000;
+_memmap_mem_dram1_end   = 0x3b6f8000;
+_memmap_mem_iram0_start = 0x3b6f8000;
+_memmap_mem_iram0_end   = 0x3b6f8800;
+_memmap_mem_sram_start = 0x92400000;
+_memmap_mem_sram_end   = 0x92c00000;
+_memmap_mem_srom_start = 0x92c00000;
+_memmap_mem_srom_end   = 0x93300000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_dram0_0_start = 0x3b6e8000;
+_memmap_seg_dram0_0_max   = 0x3b6f0000;
+_memmap_seg_dram1_0_start = 0x3b6f0000;
+_memmap_seg_dram1_0_max   = 0x3b6f8000;
+_memmap_seg_iram0_0_start = 0x3b6f8000;
+_memmap_seg_iram0_0_max   = 0x3b6f82e0;
+_memmap_seg_iram0_2_start = 0x3b6f8400;
+_memmap_seg_iram0_2_max   = 0x3b6f8578;
+_memmap_seg_iram0_3_start = 0x3b6f8578;
+_memmap_seg_iram0_3_max   = 0x3b6f857c;
+_memmap_seg_iram0_4_start = 0x3b6f857c;
+_memmap_seg_iram0_4_max   = 0x3b6f8598;
+_memmap_seg_iram0_5_start = 0x3b6f8598;
+_memmap_seg_iram0_5_max   = 0x3b6f859c;
+_memmap_seg_iram0_6_start = 0x3b6f859c;
+_memmap_seg_iram0_6_max   = 0x3b6f85b8;
+_memmap_seg_iram0_7_start = 0x3b6f85b8;
+_memmap_seg_iram0_7_max   = 0x3b6f85bc;
+_memmap_seg_iram0_8_start = 0x3b6f85bc;
+_memmap_seg_iram0_8_max   = 0x3b6f85d8;
+_memmap_seg_iram0_9_start = 0x3b6f85d8;
+_memmap_seg_iram0_9_max   = 0x3b6f85dc;
+_memmap_seg_iram0_10_start = 0x3b6f85dc;
+_memmap_seg_iram0_10_max   = 0x3b6f85f8;
+_memmap_seg_iram0_11_start = 0x3b6f85f8;
+_memmap_seg_iram0_11_max   = 0x3b6f85fc;
+_memmap_seg_iram0_12_start = 0x3b6f85fc;
+_memmap_seg_iram0_12_max   = 0x3b6f8618;
+_memmap_seg_iram0_13_start = 0x3b6f8618;
+_memmap_seg_iram0_13_max   = 0x3b6f861c;
+_memmap_seg_iram0_14_start = 0x3b6f861c;
+_memmap_seg_iram0_14_max   = 0x3b6f8638;
+_memmap_seg_iram0_15_start = 0x3b6f8638;
+_memmap_seg_iram0_15_max   = 0x3b6f863c;
+_memmap_seg_iram0_16_start = 0x3b6f863c;
+_memmap_seg_iram0_16_max   = 0x3b6f8658;
+_memmap_seg_iram0_17_start = 0x3b6f8658;
+_memmap_seg_iram0_17_max   = 0x3b6f8800;
+_memmap_seg_sram0_start = 0x92400000;
+_memmap_seg_sram0_max   = 0x92c00000;
+_memmap_seg_srom0_start = 0x92c00000;
+_memmap_seg_srom0_max   = 0x93300000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x3b6f8000);
+PROVIDE(_memmap_vecbase_reset = 0x3b6f8400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00040020;
+_memmap_cacheattr_wt_base = 0x00010020;
+_memmap_cacheattr_bp_base = 0x00020020;
+_memmap_cacheattr_unused_mask = 0xFFF0FF0F;
+_memmap_cacheattr_wb_trapnull = 0x2224222F;
+_memmap_cacheattr_wba_trapnull = 0x2224222F;
+_memmap_cacheattr_wbna_trapnull = 0x2225222F;
+_memmap_cacheattr_wt_trapnull = 0x2221222F;
+_memmap_cacheattr_bp_trapnull = 0x2222222F;
+_memmap_cacheattr_wb_strict = 0xFFF4FF2F;
+_memmap_cacheattr_wt_strict = 0xFFF1FF2F;
+_memmap_cacheattr_bp_strict = 0xFFF2FF2F;
+_memmap_cacheattr_wb_allvalid = 0x22242222;
+_memmap_cacheattr_wt_allvalid = 0x22212222;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000012;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.literal : ALIGN(4)
+  {
+    _dram0_literal_start = ABSOLUTE(.);
+    *(.dram0.literal)
+    . = ALIGN (4);
+    _dram0_literal_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .dram1.rodata : ALIGN(4)
+  {
+    _dram1_rodata_start = ABSOLUTE(.);
+    *(.dram1.rodata)
+    . = ALIGN (4);
+    _dram1_rodata_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.literal : ALIGN(4)
+  {
+    _dram1_literal_start = ABSOLUTE(.);
+    *(.dram1.literal)
+    . = ALIGN (4);
+    _dram1_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .ResetVector.literal : ALIGN(4)
+  {
+    _ResetVector_literal_start = ABSOLUTE(.);
+    *(.ResetVector.literal)
+    . = ALIGN (4);
+    _ResetVector_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.data : ALIGN(4)
+  {
+    _dram1_data_start = ABSOLUTE(.);
+    *(.dram1.data)
+    . = ALIGN (4);
+    _dram1_data_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram1_bss_start = ABSOLUTE(.);
+    *(.dram1.bss)
+    . = ALIGN (8);
+    _dram1_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram1_0_end = ALIGN(0x8);
+  } >dram1_0_seg :dram1_0_bss_phdr
+
+  _memmap_mem_dram1_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    LONG(_dram1_bss_start)
+    LONG(_dram1_bss_end)
+    LONG(_bss_start)
+    LONG(_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x92c00000);
+  _heap_sentry = 0x92c00000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xbn b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xbn
new file mode 100644
index 00000000000..5b085bc70e1
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xbn
@@ -0,0 +1,681 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -N */
+MEMORY
+{
+  dram0_0_seg :                       	org = 0x3B6E8000, len = 0x8000
+  dram1_0_seg :                       	org = 0x3B6F0000, len = 0x8000
+  iram0_0_seg :                       	org = 0x3B6F8000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x3B6F8400, len = 0x178
+  iram0_3_seg :                       	org = 0x3B6F8578, len = 0x4
+  iram0_4_seg :                       	org = 0x3B6F857C, len = 0x1C
+  iram0_5_seg :                       	org = 0x3B6F8598, len = 0x4
+  iram0_6_seg :                       	org = 0x3B6F859C, len = 0x1C
+  iram0_7_seg :                       	org = 0x3B6F85B8, len = 0x4
+  iram0_8_seg :                       	org = 0x3B6F85BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x3B6F85D8, len = 0x4
+  iram0_10_seg :                      	org = 0x3B6F85DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x3B6F85F8, len = 0x4
+  iram0_12_seg :                      	org = 0x3B6F85FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x3B6F8618, len = 0x4
+  iram0_14_seg :                      	org = 0x3B6F861C, len = 0x1C
+  iram0_15_seg :                      	org = 0x3B6F8638, len = 0x4
+  iram0_16_seg :                      	org = 0x3B6F863C, len = 0x1C
+  iram0_17_seg :                      	org = 0x3B6F8658, len = 0x1A8
+  sram0_seg :                         	org = 0x92400000, len = 0x800000
+  srom0_seg :                         	org = 0x92C00000, len = 0x700000
+}
+
+PHDRS
+{
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+  dram1_0_phdr PT_LOAD;
+  dram1_0_bss_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_dram0_start = 0x3b6e8000;
+_memmap_mem_dram0_end   = 0x3b6f0000;
+_memmap_mem_dram1_start = 0x3b6f0000;
+_memmap_mem_dram1_end   = 0x3b6f8000;
+_memmap_mem_iram0_start = 0x3b6f8000;
+_memmap_mem_iram0_end   = 0x3b6f8800;
+_memmap_mem_sram_start = 0x92400000;
+_memmap_mem_sram_end   = 0x92c00000;
+_memmap_mem_srom_start = 0x92c00000;
+_memmap_mem_srom_end   = 0x93300000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_dram0_0_start = 0x3b6e8000;
+_memmap_seg_dram0_0_max   = 0x3b6f0000;
+_memmap_seg_dram1_0_start = 0x3b6f0000;
+_memmap_seg_dram1_0_max   = 0x3b6f8000;
+_memmap_seg_iram0_0_start = 0x3b6f8000;
+_memmap_seg_iram0_0_max   = 0x3b6f82e0;
+_memmap_seg_iram0_2_start = 0x3b6f8400;
+_memmap_seg_iram0_2_max   = 0x3b6f8578;
+_memmap_seg_iram0_3_start = 0x3b6f8578;
+_memmap_seg_iram0_3_max   = 0x3b6f857c;
+_memmap_seg_iram0_4_start = 0x3b6f857c;
+_memmap_seg_iram0_4_max   = 0x3b6f8598;
+_memmap_seg_iram0_5_start = 0x3b6f8598;
+_memmap_seg_iram0_5_max   = 0x3b6f859c;
+_memmap_seg_iram0_6_start = 0x3b6f859c;
+_memmap_seg_iram0_6_max   = 0x3b6f85b8;
+_memmap_seg_iram0_7_start = 0x3b6f85b8;
+_memmap_seg_iram0_7_max   = 0x3b6f85bc;
+_memmap_seg_iram0_8_start = 0x3b6f85bc;
+_memmap_seg_iram0_8_max   = 0x3b6f85d8;
+_memmap_seg_iram0_9_start = 0x3b6f85d8;
+_memmap_seg_iram0_9_max   = 0x3b6f85dc;
+_memmap_seg_iram0_10_start = 0x3b6f85dc;
+_memmap_seg_iram0_10_max   = 0x3b6f85f8;
+_memmap_seg_iram0_11_start = 0x3b6f85f8;
+_memmap_seg_iram0_11_max   = 0x3b6f85fc;
+_memmap_seg_iram0_12_start = 0x3b6f85fc;
+_memmap_seg_iram0_12_max   = 0x3b6f8618;
+_memmap_seg_iram0_13_start = 0x3b6f8618;
+_memmap_seg_iram0_13_max   = 0x3b6f861c;
+_memmap_seg_iram0_14_start = 0x3b6f861c;
+_memmap_seg_iram0_14_max   = 0x3b6f8638;
+_memmap_seg_iram0_15_start = 0x3b6f8638;
+_memmap_seg_iram0_15_max   = 0x3b6f863c;
+_memmap_seg_iram0_16_start = 0x3b6f863c;
+_memmap_seg_iram0_16_max   = 0x3b6f8658;
+_memmap_seg_iram0_17_start = 0x3b6f8658;
+_memmap_seg_iram0_17_max   = 0x3b6f8800;
+_memmap_seg_sram0_start = 0x92400000;
+_memmap_seg_sram0_max   = 0x92c00000;
+_memmap_seg_srom0_start = 0x92c00000;
+_memmap_seg_srom0_max   = 0x93300000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x3b6f8000);
+PROVIDE(_memmap_vecbase_reset = 0x3b6f8400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00040020;
+_memmap_cacheattr_wt_base = 0x00010020;
+_memmap_cacheattr_bp_base = 0x00020020;
+_memmap_cacheattr_unused_mask = 0xFFF0FF0F;
+_memmap_cacheattr_wb_trapnull = 0x2224222F;
+_memmap_cacheattr_wba_trapnull = 0x2224222F;
+_memmap_cacheattr_wbna_trapnull = 0x2225222F;
+_memmap_cacheattr_wt_trapnull = 0x2221222F;
+_memmap_cacheattr_bp_trapnull = 0x2222222F;
+_memmap_cacheattr_wb_strict = 0xFFF4FF2F;
+_memmap_cacheattr_wt_strict = 0xFFF1FF2F;
+_memmap_cacheattr_bp_strict = 0xFFF2FF2F;
+_memmap_cacheattr_wb_allvalid = 0x22242222;
+_memmap_cacheattr_wt_allvalid = 0x22212222;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000012;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.literal : ALIGN(4)
+  {
+    _dram0_literal_start = ABSOLUTE(.);
+    *(.dram0.literal)
+    . = ALIGN (4);
+    _dram0_literal_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .dram1.rodata : ALIGN(4)
+  {
+    _dram1_rodata_start = ABSOLUTE(.);
+    *(.dram1.rodata)
+    . = ALIGN (4);
+    _dram1_rodata_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.literal : ALIGN(4)
+  {
+    _dram1_literal_start = ABSOLUTE(.);
+    *(.dram1.literal)
+    . = ALIGN (4);
+    _dram1_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .ResetVector.literal : ALIGN(4)
+  {
+    _ResetVector_literal_start = ABSOLUTE(.);
+    *(.ResetVector.literal)
+    . = ALIGN (4);
+    _ResetVector_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.data : ALIGN(4)
+  {
+    _dram1_data_start = ABSOLUTE(.);
+    *(.dram1.data)
+    . = ALIGN (4);
+    _dram1_data_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram1_bss_start = ABSOLUTE(.);
+    *(.dram1.bss)
+    . = ALIGN (8);
+    _dram1_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram1_0_end = ALIGN(0x8);
+  } >dram1_0_seg :dram1_0_bss_phdr
+
+  _memmap_mem_dram1_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    LONG(_dram1_bss_start)
+    LONG(_dram1_bss_end)
+    LONG(_bss_start)
+    LONG(_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x92c00000);
+  _heap_sentry = 0x92c00000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xn b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xn
new file mode 100644
index 00000000000..55ce2c2a04b
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xn
@@ -0,0 +1,681 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -n */
+MEMORY
+{
+  dram0_0_seg :                       	org = 0x3B6E8000, len = 0x8000
+  dram1_0_seg :                       	org = 0x3B6F0000, len = 0x8000
+  iram0_0_seg :                       	org = 0x3B6F8000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x3B6F8400, len = 0x178
+  iram0_3_seg :                       	org = 0x3B6F8578, len = 0x4
+  iram0_4_seg :                       	org = 0x3B6F857C, len = 0x1C
+  iram0_5_seg :                       	org = 0x3B6F8598, len = 0x4
+  iram0_6_seg :                       	org = 0x3B6F859C, len = 0x1C
+  iram0_7_seg :                       	org = 0x3B6F85B8, len = 0x4
+  iram0_8_seg :                       	org = 0x3B6F85BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x3B6F85D8, len = 0x4
+  iram0_10_seg :                      	org = 0x3B6F85DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x3B6F85F8, len = 0x4
+  iram0_12_seg :                      	org = 0x3B6F85FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x3B6F8618, len = 0x4
+  iram0_14_seg :                      	org = 0x3B6F861C, len = 0x1C
+  iram0_15_seg :                      	org = 0x3B6F8638, len = 0x4
+  iram0_16_seg :                      	org = 0x3B6F863C, len = 0x1C
+  iram0_17_seg :                      	org = 0x3B6F8658, len = 0x1A8
+  sram0_seg :                         	org = 0x92400000, len = 0x800000
+  srom0_seg :                         	org = 0x92C00000, len = 0x700000
+}
+
+PHDRS
+{
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+  dram1_0_phdr PT_LOAD;
+  dram1_0_bss_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_dram0_start = 0x3b6e8000;
+_memmap_mem_dram0_end   = 0x3b6f0000;
+_memmap_mem_dram1_start = 0x3b6f0000;
+_memmap_mem_dram1_end   = 0x3b6f8000;
+_memmap_mem_iram0_start = 0x3b6f8000;
+_memmap_mem_iram0_end   = 0x3b6f8800;
+_memmap_mem_sram_start = 0x92400000;
+_memmap_mem_sram_end   = 0x92c00000;
+_memmap_mem_srom_start = 0x92c00000;
+_memmap_mem_srom_end   = 0x93300000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_dram0_0_start = 0x3b6e8000;
+_memmap_seg_dram0_0_max   = 0x3b6f0000;
+_memmap_seg_dram1_0_start = 0x3b6f0000;
+_memmap_seg_dram1_0_max   = 0x3b6f8000;
+_memmap_seg_iram0_0_start = 0x3b6f8000;
+_memmap_seg_iram0_0_max   = 0x3b6f82e0;
+_memmap_seg_iram0_2_start = 0x3b6f8400;
+_memmap_seg_iram0_2_max   = 0x3b6f8578;
+_memmap_seg_iram0_3_start = 0x3b6f8578;
+_memmap_seg_iram0_3_max   = 0x3b6f857c;
+_memmap_seg_iram0_4_start = 0x3b6f857c;
+_memmap_seg_iram0_4_max   = 0x3b6f8598;
+_memmap_seg_iram0_5_start = 0x3b6f8598;
+_memmap_seg_iram0_5_max   = 0x3b6f859c;
+_memmap_seg_iram0_6_start = 0x3b6f859c;
+_memmap_seg_iram0_6_max   = 0x3b6f85b8;
+_memmap_seg_iram0_7_start = 0x3b6f85b8;
+_memmap_seg_iram0_7_max   = 0x3b6f85bc;
+_memmap_seg_iram0_8_start = 0x3b6f85bc;
+_memmap_seg_iram0_8_max   = 0x3b6f85d8;
+_memmap_seg_iram0_9_start = 0x3b6f85d8;
+_memmap_seg_iram0_9_max   = 0x3b6f85dc;
+_memmap_seg_iram0_10_start = 0x3b6f85dc;
+_memmap_seg_iram0_10_max   = 0x3b6f85f8;
+_memmap_seg_iram0_11_start = 0x3b6f85f8;
+_memmap_seg_iram0_11_max   = 0x3b6f85fc;
+_memmap_seg_iram0_12_start = 0x3b6f85fc;
+_memmap_seg_iram0_12_max   = 0x3b6f8618;
+_memmap_seg_iram0_13_start = 0x3b6f8618;
+_memmap_seg_iram0_13_max   = 0x3b6f861c;
+_memmap_seg_iram0_14_start = 0x3b6f861c;
+_memmap_seg_iram0_14_max   = 0x3b6f8638;
+_memmap_seg_iram0_15_start = 0x3b6f8638;
+_memmap_seg_iram0_15_max   = 0x3b6f863c;
+_memmap_seg_iram0_16_start = 0x3b6f863c;
+_memmap_seg_iram0_16_max   = 0x3b6f8658;
+_memmap_seg_iram0_17_start = 0x3b6f8658;
+_memmap_seg_iram0_17_max   = 0x3b6f8800;
+_memmap_seg_sram0_start = 0x92400000;
+_memmap_seg_sram0_max   = 0x92c00000;
+_memmap_seg_srom0_start = 0x92c00000;
+_memmap_seg_srom0_max   = 0x93300000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x3b6f8000);
+PROVIDE(_memmap_vecbase_reset = 0x3b6f8400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00040020;
+_memmap_cacheattr_wt_base = 0x00010020;
+_memmap_cacheattr_bp_base = 0x00020020;
+_memmap_cacheattr_unused_mask = 0xFFF0FF0F;
+_memmap_cacheattr_wb_trapnull = 0x2224222F;
+_memmap_cacheattr_wba_trapnull = 0x2224222F;
+_memmap_cacheattr_wbna_trapnull = 0x2225222F;
+_memmap_cacheattr_wt_trapnull = 0x2221222F;
+_memmap_cacheattr_bp_trapnull = 0x2222222F;
+_memmap_cacheattr_wb_strict = 0xFFF4FF2F;
+_memmap_cacheattr_wt_strict = 0xFFF1FF2F;
+_memmap_cacheattr_bp_strict = 0xFFF2FF2F;
+_memmap_cacheattr_wb_allvalid = 0x22242222;
+_memmap_cacheattr_wt_allvalid = 0x22212222;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000012;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.literal : ALIGN(4)
+  {
+    _dram0_literal_start = ABSOLUTE(.);
+    *(.dram0.literal)
+    . = ALIGN (4);
+    _dram0_literal_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .dram1.rodata : ALIGN(4)
+  {
+    _dram1_rodata_start = ABSOLUTE(.);
+    *(.dram1.rodata)
+    . = ALIGN (4);
+    _dram1_rodata_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.literal : ALIGN(4)
+  {
+    _dram1_literal_start = ABSOLUTE(.);
+    *(.dram1.literal)
+    . = ALIGN (4);
+    _dram1_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .ResetVector.literal : ALIGN(4)
+  {
+    _ResetVector_literal_start = ABSOLUTE(.);
+    *(.ResetVector.literal)
+    . = ALIGN (4);
+    _ResetVector_literal_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.data : ALIGN(4)
+  {
+    _dram1_data_start = ABSOLUTE(.);
+    *(.dram1.data)
+    . = ALIGN (4);
+    _dram1_data_end = ABSOLUTE(.);
+  } >dram1_0_seg :dram1_0_phdr
+
+  .dram1.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram1_bss_start = ABSOLUTE(.);
+    *(.dram1.bss)
+    . = ALIGN (8);
+    _dram1_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram1_0_end = ALIGN(0x8);
+  } >dram1_0_seg :dram1_0_bss_phdr
+
+  _memmap_mem_dram1_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    LONG(_dram1_bss_start)
+    LONG(_dram1_bss_end)
+    LONG(_bss_start)
+    LONG(_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x92c00000);
+  _heap_sentry = 0x92c00000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xr b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xr
new file mode 100644
index 00000000000..4a59d9768a3
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xr
@@ -0,0 +1,61 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -r or ld -i */
+
+
+SECTIONS
+{
+
+  .text 0 :
+  {
+    *(.literal .text)
+  }
+
+  .bss 0 :
+  {
+    *(.dynsbss)
+    *(.sbss)
+    *(.scommon)
+    *(.dynbss)
+    *(.bss)
+    *(COMMON)
+  }
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xu b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xu
new file mode 100644
index 00000000000..62a3382fb53
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/ldscripts/elf32xtensa.xu
@@ -0,0 +1,61 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -Ur */
+
+
+SECTIONS
+{
+
+  .text 0 :
+  {
+    *(.literal .text)
+  }
+
+  .bss 0 :
+  {
+    *(.dynsbss)
+    *(.sbss)
+    *(.scommon)
+    *(.dynbss)
+    *(.bss)
+    *(COMMON)
+  }
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/memmap.xmm b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/memmap.xmm
new file mode 100644
index 00000000000..3a1fe7a5165
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/memmap.xmm
@@ -0,0 +1,93 @@
+//  Memory map file to generate linker scripts for programs run on the ISS.
+
+// Customer ID=14556; Build=0x7ef28; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+// A memory map is a sequence of memory descriptions and
+// optional parameter assignments.
+//
+// Each memory description has the following format:
+//   BEGIN <name>
+//     <addr> [,<paddr>] : <mem-type> : <mem-name> : <size> [,<psize>]
+//                       : [writable] [,executable] [,device] ;
+//     <segment>*
+//   END <name>
+//
+// where each <segment> description has the following format:
+//     <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
+//                : <section-name>* ;
+//
+// Each parameter assignment is a keyword/value pair in the following format:
+//   <keyword> = <value>                (no spaces in <value>)
+// or
+//   <keyword> = "<value>"              (spaces allowed in <value>)
+//
+// The following primitives are also defined:
+//   PLACE SECTIONS( <section-name>* ) { WITH_SECTION(<section-name>)
+//                                       | IN_SEGMENT(<seg-name>) }
+//
+//   NOLOAD <section-name1> [ <section-name2> ... ]
+//
+// Please refer to the Xtensa LSP Reference Manual for more details.
+//
+BEGIN dram0
+0x3b6e8000: dataRam : dram0 : 0x8000 : writable ;
+ dram0_0 : C : 0x3b6e8000 - 0x3b6effff : .dram0.rodata .dram0.literal .dram0.data .dram0.bss;
+END dram0
+
+BEGIN dram1
+0x3b6f0000: dataRam : dram1 : 0x8000 : writable ;
+ dram1_0 : C : 0x3b6f0000 - 0x3b6f7fff : .dram1.rodata .dram1.literal .ResetVector.literal .dram1.data .dram1.bss;
+END dram1
+
+BEGIN iram0
+0x3b6f8000: instRam : iram0 : 0x800 : executable, writable ;
+ iram0_0 : F : 0x3b6f8000 - 0x3b6f82df : .ResetVector.text;
+ iram0_1 : C : 0x3b6f82e0 - 0x3b6f83ff : ;
+ iram0_2 : F : 0x3b6f8400 - 0x3b6f8577 : .WindowVectors.text;
+ iram0_3 : C : 0x3b6f8578 - 0x3b6f857b : .Level2InterruptVector.literal;
+ iram0_4 : F : 0x3b6f857c - 0x3b6f8597 : .Level2InterruptVector.text;
+ iram0_5 : C : 0x3b6f8598 - 0x3b6f859b : .Level3InterruptVector.literal;
+ iram0_6 : F : 0x3b6f859c - 0x3b6f85b7 : .Level3InterruptVector.text;
+ iram0_7 : C : 0x3b6f85b8 - 0x3b6f85bb : .DebugExceptionVector.literal;
+ iram0_8 : F : 0x3b6f85bc - 0x3b6f85d7 : .DebugExceptionVector.text;
+ iram0_9 : C : 0x3b6f85d8 - 0x3b6f85db : .NMIExceptionVector.literal;
+ iram0_10 : F : 0x3b6f85dc - 0x3b6f85f7 : .NMIExceptionVector.text;
+ iram0_11 : C : 0x3b6f85f8 - 0x3b6f85fb : .KernelExceptionVector.literal;
+ iram0_12 : F : 0x3b6f85fc - 0x3b6f8617 : .KernelExceptionVector.text;
+ iram0_13 : C : 0x3b6f8618 - 0x3b6f861b : .UserExceptionVector.literal;
+ iram0_14 : F : 0x3b6f861c - 0x3b6f8637 : .UserExceptionVector.text;
+ iram0_15 : C : 0x3b6f8638 - 0x3b6f863b : .DoubleExceptionVector.literal;
+ iram0_16 : F : 0x3b6f863c - 0x3b6f8657 : .DoubleExceptionVector.text;
+ iram0_17 : C : 0x3b6f8658 - 0x3b6f87ff : .iram0.literal .iram0.text;
+END iram0
+
+BEGIN sram
+0x92400000: sysram : sram : 0x800000 : executable, writable ;
+ sram0 : C : 0x92400000 - 0x92bfffff :  STACK :  HEAP : .sram.rodata .clib.rodata .rtos.rodata .rodata .sram.literal .literal .rtos.literal .clib.literal .sram.text .text .clib.text .rtos.text .clib.data .clib.percpu.data .rtos.percpu.data .rtos.data .sram.data .data __llvm_prf_names .resource_table .clib.bss .clib.percpu.bss .rtos.percpu.bss .rtos.bss .sram.bss .bss;
+END sram
+
+BEGIN srom
+0x92c00000: sysrom : srom : 0x700000 : executable ;
+ srom0 : C : 0x92c00000 - 0x932fffff : .srom.rodata .srom.literal .srom.text .rom.store;
+END srom
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/sim.parm b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/sim.parm
new file mode 100644
index 00000000000..1788de09228
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/sim.parm
@@ -0,0 +1,23 @@
+//  Memory map file to generate linker scripts for programs run on the ISS.
+
+// Customer ID=14556; Build=0x7ef28; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/specs b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/specs
new file mode 100644
index 00000000000..80f3f81ce81
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8m/specs
@@ -0,0 +1,36 @@
+# Customer ID=14556; Build=0x7ef28; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+# The %O suffix on the start and end files indicates that the system's
+# standard suffix for object files (e.g., ".o") should be appended.
+# The %s suffix tells the compiler driver to search for the file in the
+# list of known locations for startfiles.
+
+*startfile:
+crt1-sim%O%s crti%O%s crtbegin%O%s _sharedvectors%O%s _vectors%O%s
+
+*endfile:
+crtend%O%s crtn%O%s
+
+*lib:
+-lc -lsim -lc -lhandler-reset -lhandlers-sim -lhal -lc
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.x b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.x
new file mode 100644
index 00000000000..c6bd93b0a53
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.x
@@ -0,0 +1,630 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for default link */
+MEMORY
+{
+  sram0_seg :                         	org = 0x1A000000, len = 0x800000
+  srom0_seg :                         	org = 0x1A800000, len = 0x700000
+  iram0_0_seg :                       	org = 0x21170000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x21170400, len = 0x178
+  iram0_3_seg :                       	org = 0x21170578, len = 0x4
+  iram0_4_seg :                       	org = 0x2117057C, len = 0x1C
+  iram0_5_seg :                       	org = 0x21170598, len = 0x4
+  iram0_6_seg :                       	org = 0x2117059C, len = 0x1C
+  iram0_7_seg :                       	org = 0x211705B8, len = 0x4
+  iram0_8_seg :                       	org = 0x211705BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x211705D8, len = 0x4
+  iram0_10_seg :                      	org = 0x211705DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x211705F8, len = 0x4
+  iram0_12_seg :                      	org = 0x211705FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x21170618, len = 0x4
+  iram0_14_seg :                      	org = 0x2117061C, len = 0x1C
+  iram0_15_seg :                      	org = 0x21170638, len = 0x4
+  iram0_16_seg :                      	org = 0x2117063C, len = 0x1C
+  iram0_17_seg :                      	org = 0x21170658, len = 0xF9A8
+  dram0_0_seg :                       	org = 0x21180000, len = 0x10000
+}
+
+PHDRS
+{
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_iram0_start = 0x21170000;
+_memmap_mem_iram0_end   = 0x21180000;
+_memmap_mem_dram0_start = 0x21180000;
+_memmap_mem_dram0_end   = 0x21190000;
+_memmap_mem_sram_start = 0x1a000000;
+_memmap_mem_sram_end   = 0x1a800000;
+_memmap_mem_srom_start = 0x1a800000;
+_memmap_mem_srom_end   = 0x1af00000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_sram0_start = 0x1a000000;
+_memmap_seg_sram0_max   = 0x1a800000;
+_memmap_seg_srom0_start = 0x1a800000;
+_memmap_seg_srom0_max   = 0x1af00000;
+_memmap_seg_iram0_0_start = 0x21170000;
+_memmap_seg_iram0_0_max   = 0x211702e0;
+_memmap_seg_iram0_2_start = 0x21170400;
+_memmap_seg_iram0_2_max   = 0x21170578;
+_memmap_seg_iram0_3_start = 0x21170578;
+_memmap_seg_iram0_3_max   = 0x2117057c;
+_memmap_seg_iram0_4_start = 0x2117057c;
+_memmap_seg_iram0_4_max   = 0x21170598;
+_memmap_seg_iram0_5_start = 0x21170598;
+_memmap_seg_iram0_5_max   = 0x2117059c;
+_memmap_seg_iram0_6_start = 0x2117059c;
+_memmap_seg_iram0_6_max   = 0x211705b8;
+_memmap_seg_iram0_7_start = 0x211705b8;
+_memmap_seg_iram0_7_max   = 0x211705bc;
+_memmap_seg_iram0_8_start = 0x211705bc;
+_memmap_seg_iram0_8_max   = 0x211705d8;
+_memmap_seg_iram0_9_start = 0x211705d8;
+_memmap_seg_iram0_9_max   = 0x211705dc;
+_memmap_seg_iram0_10_start = 0x211705dc;
+_memmap_seg_iram0_10_max   = 0x211705f8;
+_memmap_seg_iram0_11_start = 0x211705f8;
+_memmap_seg_iram0_11_max   = 0x211705fc;
+_memmap_seg_iram0_12_start = 0x211705fc;
+_memmap_seg_iram0_12_max   = 0x21170618;
+_memmap_seg_iram0_13_start = 0x21170618;
+_memmap_seg_iram0_13_max   = 0x2117061c;
+_memmap_seg_iram0_14_start = 0x2117061c;
+_memmap_seg_iram0_14_max   = 0x21170638;
+_memmap_seg_iram0_15_start = 0x21170638;
+_memmap_seg_iram0_15_max   = 0x2117063c;
+_memmap_seg_iram0_16_start = 0x2117063c;
+_memmap_seg_iram0_16_max   = 0x21170658;
+_memmap_seg_iram0_17_start = 0x21170658;
+_memmap_seg_iram0_17_max   = 0x21180000;
+_memmap_seg_dram0_0_start = 0x21180000;
+_memmap_seg_dram0_0_max   = 0x21190000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x21170000);
+PROVIDE(_memmap_vecbase_reset = 0x21170400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00000024;
+_memmap_cacheattr_wt_base = 0x00000021;
+_memmap_cacheattr_bp_base = 0x00000022;
+_memmap_cacheattr_unused_mask = 0xFFFFFF00;
+_memmap_cacheattr_wb_trapnull = 0x22222224;
+_memmap_cacheattr_wba_trapnull = 0x22222224;
+_memmap_cacheattr_wbna_trapnull = 0x22222225;
+_memmap_cacheattr_wt_trapnull = 0x22222221;
+_memmap_cacheattr_bp_trapnull = 0x22222222;
+_memmap_cacheattr_wb_strict = 0xFFFFFF24;
+_memmap_cacheattr_wt_strict = 0xFFFFFF21;
+_memmap_cacheattr_bp_strict = 0xFFFFFF22;
+_memmap_cacheattr_wb_allvalid = 0x22222224;
+_memmap_cacheattr_wt_allvalid = 0x22222221;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000003;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+  } >iram0_0_seg :iram0_0_phdr
+
+  .ResetHandler.text : ALIGN(4)
+  {
+    _ResetHandler_text_start = ABSOLUTE(.);
+    *(.ResetHandler.literal .ResetHandler.text)
+    . = ALIGN (4);
+    _ResetHandler_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_bss_start)
+    LONG(_bss_end)
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x1a800000);
+  _heap_sentry = 0x1a800000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    *(.dram.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    *(.dram.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xbn b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xbn
new file mode 100644
index 00000000000..7719e270ba4
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xbn
@@ -0,0 +1,630 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -N */
+MEMORY
+{
+  sram0_seg :                         	org = 0x1A000000, len = 0x800000
+  srom0_seg :                         	org = 0x1A800000, len = 0x700000
+  iram0_0_seg :                       	org = 0x21170000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x21170400, len = 0x178
+  iram0_3_seg :                       	org = 0x21170578, len = 0x4
+  iram0_4_seg :                       	org = 0x2117057C, len = 0x1C
+  iram0_5_seg :                       	org = 0x21170598, len = 0x4
+  iram0_6_seg :                       	org = 0x2117059C, len = 0x1C
+  iram0_7_seg :                       	org = 0x211705B8, len = 0x4
+  iram0_8_seg :                       	org = 0x211705BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x211705D8, len = 0x4
+  iram0_10_seg :                      	org = 0x211705DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x211705F8, len = 0x4
+  iram0_12_seg :                      	org = 0x211705FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x21170618, len = 0x4
+  iram0_14_seg :                      	org = 0x2117061C, len = 0x1C
+  iram0_15_seg :                      	org = 0x21170638, len = 0x4
+  iram0_16_seg :                      	org = 0x2117063C, len = 0x1C
+  iram0_17_seg :                      	org = 0x21170658, len = 0xF9A8
+  dram0_0_seg :                       	org = 0x21180000, len = 0x10000
+}
+
+PHDRS
+{
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_iram0_start = 0x21170000;
+_memmap_mem_iram0_end   = 0x21180000;
+_memmap_mem_dram0_start = 0x21180000;
+_memmap_mem_dram0_end   = 0x21190000;
+_memmap_mem_sram_start = 0x1a000000;
+_memmap_mem_sram_end   = 0x1a800000;
+_memmap_mem_srom_start = 0x1a800000;
+_memmap_mem_srom_end   = 0x1af00000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_sram0_start = 0x1a000000;
+_memmap_seg_sram0_max   = 0x1a800000;
+_memmap_seg_srom0_start = 0x1a800000;
+_memmap_seg_srom0_max   = 0x1af00000;
+_memmap_seg_iram0_0_start = 0x21170000;
+_memmap_seg_iram0_0_max   = 0x211702e0;
+_memmap_seg_iram0_2_start = 0x21170400;
+_memmap_seg_iram0_2_max   = 0x21170578;
+_memmap_seg_iram0_3_start = 0x21170578;
+_memmap_seg_iram0_3_max   = 0x2117057c;
+_memmap_seg_iram0_4_start = 0x2117057c;
+_memmap_seg_iram0_4_max   = 0x21170598;
+_memmap_seg_iram0_5_start = 0x21170598;
+_memmap_seg_iram0_5_max   = 0x2117059c;
+_memmap_seg_iram0_6_start = 0x2117059c;
+_memmap_seg_iram0_6_max   = 0x211705b8;
+_memmap_seg_iram0_7_start = 0x211705b8;
+_memmap_seg_iram0_7_max   = 0x211705bc;
+_memmap_seg_iram0_8_start = 0x211705bc;
+_memmap_seg_iram0_8_max   = 0x211705d8;
+_memmap_seg_iram0_9_start = 0x211705d8;
+_memmap_seg_iram0_9_max   = 0x211705dc;
+_memmap_seg_iram0_10_start = 0x211705dc;
+_memmap_seg_iram0_10_max   = 0x211705f8;
+_memmap_seg_iram0_11_start = 0x211705f8;
+_memmap_seg_iram0_11_max   = 0x211705fc;
+_memmap_seg_iram0_12_start = 0x211705fc;
+_memmap_seg_iram0_12_max   = 0x21170618;
+_memmap_seg_iram0_13_start = 0x21170618;
+_memmap_seg_iram0_13_max   = 0x2117061c;
+_memmap_seg_iram0_14_start = 0x2117061c;
+_memmap_seg_iram0_14_max   = 0x21170638;
+_memmap_seg_iram0_15_start = 0x21170638;
+_memmap_seg_iram0_15_max   = 0x2117063c;
+_memmap_seg_iram0_16_start = 0x2117063c;
+_memmap_seg_iram0_16_max   = 0x21170658;
+_memmap_seg_iram0_17_start = 0x21170658;
+_memmap_seg_iram0_17_max   = 0x21180000;
+_memmap_seg_dram0_0_start = 0x21180000;
+_memmap_seg_dram0_0_max   = 0x21190000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x21170000);
+PROVIDE(_memmap_vecbase_reset = 0x21170400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00000024;
+_memmap_cacheattr_wt_base = 0x00000021;
+_memmap_cacheattr_bp_base = 0x00000022;
+_memmap_cacheattr_unused_mask = 0xFFFFFF00;
+_memmap_cacheattr_wb_trapnull = 0x22222224;
+_memmap_cacheattr_wba_trapnull = 0x22222224;
+_memmap_cacheattr_wbna_trapnull = 0x22222225;
+_memmap_cacheattr_wt_trapnull = 0x22222221;
+_memmap_cacheattr_bp_trapnull = 0x22222222;
+_memmap_cacheattr_wb_strict = 0xFFFFFF24;
+_memmap_cacheattr_wt_strict = 0xFFFFFF21;
+_memmap_cacheattr_bp_strict = 0xFFFFFF22;
+_memmap_cacheattr_wb_allvalid = 0x22222224;
+_memmap_cacheattr_wt_allvalid = 0x22222221;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000003;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+  } >iram0_0_seg :iram0_0_phdr
+
+  .ResetHandler.text : ALIGN(4)
+  {
+    _ResetHandler_text_start = ABSOLUTE(.);
+    *(.ResetHandler.literal .ResetHandler.text)
+    . = ALIGN (4);
+    _ResetHandler_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_bss_start)
+    LONG(_bss_end)
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x1a800000);
+  _heap_sentry = 0x1a800000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    *(.dram.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    *(.dram.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xn b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xn
new file mode 100644
index 00000000000..35e911db556
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xn
@@ -0,0 +1,630 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -n */
+MEMORY
+{
+  sram0_seg :                         	org = 0x1A000000, len = 0x800000
+  srom0_seg :                         	org = 0x1A800000, len = 0x700000
+  iram0_0_seg :                       	org = 0x21170000, len = 0x2E0
+  iram0_2_seg :                       	org = 0x21170400, len = 0x178
+  iram0_3_seg :                       	org = 0x21170578, len = 0x4
+  iram0_4_seg :                       	org = 0x2117057C, len = 0x1C
+  iram0_5_seg :                       	org = 0x21170598, len = 0x4
+  iram0_6_seg :                       	org = 0x2117059C, len = 0x1C
+  iram0_7_seg :                       	org = 0x211705B8, len = 0x4
+  iram0_8_seg :                       	org = 0x211705BC, len = 0x1C
+  iram0_9_seg :                       	org = 0x211705D8, len = 0x4
+  iram0_10_seg :                      	org = 0x211705DC, len = 0x1C
+  iram0_11_seg :                      	org = 0x211705F8, len = 0x4
+  iram0_12_seg :                      	org = 0x211705FC, len = 0x1C
+  iram0_13_seg :                      	org = 0x21170618, len = 0x4
+  iram0_14_seg :                      	org = 0x2117061C, len = 0x1C
+  iram0_15_seg :                      	org = 0x21170638, len = 0x4
+  iram0_16_seg :                      	org = 0x2117063C, len = 0x1C
+  iram0_17_seg :                      	org = 0x21170658, len = 0xF9A8
+  dram0_0_seg :                       	org = 0x21180000, len = 0x10000
+}
+
+PHDRS
+{
+  sram0_phdr PT_LOAD;
+  sram0_bss_phdr PT_LOAD;
+  srom0_phdr PT_LOAD;
+  iram0_0_phdr PT_LOAD;
+  iram0_1_phdr PT_LOAD;
+  iram0_2_phdr PT_LOAD;
+  iram0_3_phdr PT_LOAD;
+  iram0_4_phdr PT_LOAD;
+  iram0_5_phdr PT_LOAD;
+  iram0_6_phdr PT_LOAD;
+  iram0_7_phdr PT_LOAD;
+  iram0_8_phdr PT_LOAD;
+  iram0_9_phdr PT_LOAD;
+  iram0_10_phdr PT_LOAD;
+  iram0_11_phdr PT_LOAD;
+  iram0_12_phdr PT_LOAD;
+  iram0_13_phdr PT_LOAD;
+  iram0_14_phdr PT_LOAD;
+  iram0_15_phdr PT_LOAD;
+  iram0_16_phdr PT_LOAD;
+  iram0_17_phdr PT_LOAD;
+  dram0_0_phdr PT_LOAD;
+  dram0_0_bss_phdr PT_LOAD;
+}
+
+
+/*  Default entry point:  */
+ENTRY(_ResetVector)
+
+
+/*  Memory boundary addresses:  */
+_memmap_mem_iram0_start = 0x21170000;
+_memmap_mem_iram0_end   = 0x21180000;
+_memmap_mem_dram0_start = 0x21180000;
+_memmap_mem_dram0_end   = 0x21190000;
+_memmap_mem_sram_start = 0x1a000000;
+_memmap_mem_sram_end   = 0x1a800000;
+_memmap_mem_srom_start = 0x1a800000;
+_memmap_mem_srom_end   = 0x1af00000;
+
+/*  Memory segment boundary addresses:  */
+_memmap_seg_sram0_start = 0x1a000000;
+_memmap_seg_sram0_max   = 0x1a800000;
+_memmap_seg_srom0_start = 0x1a800000;
+_memmap_seg_srom0_max   = 0x1af00000;
+_memmap_seg_iram0_0_start = 0x21170000;
+_memmap_seg_iram0_0_max   = 0x211702e0;
+_memmap_seg_iram0_2_start = 0x21170400;
+_memmap_seg_iram0_2_max   = 0x21170578;
+_memmap_seg_iram0_3_start = 0x21170578;
+_memmap_seg_iram0_3_max   = 0x2117057c;
+_memmap_seg_iram0_4_start = 0x2117057c;
+_memmap_seg_iram0_4_max   = 0x21170598;
+_memmap_seg_iram0_5_start = 0x21170598;
+_memmap_seg_iram0_5_max   = 0x2117059c;
+_memmap_seg_iram0_6_start = 0x2117059c;
+_memmap_seg_iram0_6_max   = 0x211705b8;
+_memmap_seg_iram0_7_start = 0x211705b8;
+_memmap_seg_iram0_7_max   = 0x211705bc;
+_memmap_seg_iram0_8_start = 0x211705bc;
+_memmap_seg_iram0_8_max   = 0x211705d8;
+_memmap_seg_iram0_9_start = 0x211705d8;
+_memmap_seg_iram0_9_max   = 0x211705dc;
+_memmap_seg_iram0_10_start = 0x211705dc;
+_memmap_seg_iram0_10_max   = 0x211705f8;
+_memmap_seg_iram0_11_start = 0x211705f8;
+_memmap_seg_iram0_11_max   = 0x211705fc;
+_memmap_seg_iram0_12_start = 0x211705fc;
+_memmap_seg_iram0_12_max   = 0x21170618;
+_memmap_seg_iram0_13_start = 0x21170618;
+_memmap_seg_iram0_13_max   = 0x2117061c;
+_memmap_seg_iram0_14_start = 0x2117061c;
+_memmap_seg_iram0_14_max   = 0x21170638;
+_memmap_seg_iram0_15_start = 0x21170638;
+_memmap_seg_iram0_15_max   = 0x2117063c;
+_memmap_seg_iram0_16_start = 0x2117063c;
+_memmap_seg_iram0_16_max   = 0x21170658;
+_memmap_seg_iram0_17_start = 0x21170658;
+_memmap_seg_iram0_17_max   = 0x21180000;
+_memmap_seg_dram0_0_start = 0x21180000;
+_memmap_seg_dram0_0_max   = 0x21190000;
+
+_rom_store_table = 0;
+PROVIDE(_memmap_reset_vector = 0x21170000);
+PROVIDE(_memmap_vecbase_reset = 0x21170400);
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00000024;
+_memmap_cacheattr_wt_base = 0x00000021;
+_memmap_cacheattr_bp_base = 0x00000022;
+_memmap_cacheattr_unused_mask = 0xFFFFFF00;
+_memmap_cacheattr_wb_trapnull = 0x22222224;
+_memmap_cacheattr_wba_trapnull = 0x22222224;
+_memmap_cacheattr_wbna_trapnull = 0x22222225;
+_memmap_cacheattr_wt_trapnull = 0x22222221;
+_memmap_cacheattr_bp_trapnull = 0x22222222;
+_memmap_cacheattr_wb_strict = 0xFFFFFF24;
+_memmap_cacheattr_wt_strict = 0xFFFFFF21;
+_memmap_cacheattr_bp_strict = 0xFFFFFF22;
+_memmap_cacheattr_wb_allvalid = 0x22222224;
+_memmap_cacheattr_wt_allvalid = 0x22222221;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000003;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+  .srom.rodata : ALIGN(4)
+  {
+    _srom_rodata_start = ABSOLUTE(.);
+    *(.srom.rodata)
+    . = ALIGN (4);
+    _srom_rodata_end = ABSOLUTE(.);
+  } >srom0_seg :srom0_phdr
+
+  .srom.text : ALIGN(4)
+  {
+    _srom_text_start = ABSOLUTE(.);
+    *(.srom.literal .srom.text)
+    . = ALIGN (4);
+    _srom_text_end = ABSOLUTE(.);
+    _memmap_seg_srom0_end = ALIGN(0x8);
+  } >srom0_seg :srom0_phdr
+
+  _memmap_mem_srom_max = ABSOLUTE(.);
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    . = ALIGN (4);
+    _ResetVector_text_end = ABSOLUTE(.);
+  } >iram0_0_seg :iram0_0_phdr
+
+  .ResetHandler.text : ALIGN(4)
+  {
+    _ResetHandler_text_start = ABSOLUTE(.);
+    *(.ResetHandler.literal .ResetHandler.text)
+    . = ALIGN (4);
+    _ResetHandler_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_0_end = ALIGN(0x8);
+  } >iram0_0_seg :iram0_0_phdr
+
+
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    . = ALIGN (4);
+    _WindowVectors_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_2_end = ALIGN(0x8);
+  } >iram0_2_seg :iram0_2_phdr
+
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    . = ALIGN (4);
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_3_end = ALIGN(0x8);
+  } >iram0_3_seg :iram0_3_phdr
+
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    . = ALIGN (4);
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_4_end = ALIGN(0x8);
+  } >iram0_4_seg :iram0_4_phdr
+
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    . = ALIGN (4);
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_5_end = ALIGN(0x8);
+  } >iram0_5_seg :iram0_5_phdr
+
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    . = ALIGN (4);
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_6_end = ALIGN(0x8);
+  } >iram0_6_seg :iram0_6_phdr
+
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    . = ALIGN (4);
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_7_end = ALIGN(0x8);
+  } >iram0_7_seg :iram0_7_phdr
+
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    . = ALIGN (4);
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_8_end = ALIGN(0x8);
+  } >iram0_8_seg :iram0_8_phdr
+
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    . = ALIGN (4);
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_9_end = ALIGN(0x8);
+  } >iram0_9_seg :iram0_9_phdr
+
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    . = ALIGN (4);
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_10_end = ALIGN(0x8);
+  } >iram0_10_seg :iram0_10_phdr
+
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    . = ALIGN (4);
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_11_end = ALIGN(0x8);
+  } >iram0_11_seg :iram0_11_phdr
+
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    . = ALIGN (4);
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_12_end = ALIGN(0x8);
+  } >iram0_12_seg :iram0_12_phdr
+
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    . = ALIGN (4);
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_13_end = ALIGN(0x8);
+  } >iram0_13_seg :iram0_13_phdr
+
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    . = ALIGN (4);
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_14_end = ALIGN(0x8);
+  } >iram0_14_seg :iram0_14_phdr
+
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    . = ALIGN (4);
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+    _memmap_seg_iram0_15_end = ALIGN(0x8);
+  } >iram0_15_seg :iram0_15_phdr
+
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    . = ALIGN (4);
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_16_end = ALIGN(0x8);
+  } >iram0_16_seg :iram0_16_phdr
+
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+    _memmap_seg_iram0_17_end = ALIGN(0x8);
+  } >iram0_17_seg :iram0_17_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .sram.rodata : ALIGN(4)
+  {
+    _sram_rodata_start = ABSOLUTE(.);
+    *(.sram.rodata)
+    . = ALIGN (4);
+    _sram_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.rodata : ALIGN(4)
+  {
+    _clib_rodata_start = ABSOLUTE(.);
+    *(.clib.rodata)
+    . = ALIGN (4);
+    _clib_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.rodata : ALIGN(4)
+  {
+    _rtos_rodata_start = ABSOLUTE(.);
+    *(.rtos.rodata)
+    . = ALIGN (4);
+    _rtos_rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rodata : ALIGN(4)
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    KEEP (*(.eh_frame))
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_bss_start)
+    LONG(_bss_end)
+    LONG(_dram0_bss_start)
+    LONG(_dram0_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    _rodata_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.text : ALIGN(4)
+  {
+    _sram_text_start = ABSOLUTE(.);
+    *(.sram.literal .sram.text)
+    . = ALIGN (4);
+    _sram_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >sram0_seg :sram0_phdr
+
+  .clib.text : ALIGN(4)
+  {
+    _clib_text_start = ABSOLUTE(.);
+    *(.clib.literal .clib.text)
+    . = ALIGN (4);
+    _clib_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.text : ALIGN(4)
+  {
+    _rtos_text_start = ABSOLUTE(.);
+    *(.rtos.literal .rtos.text)
+    . = ALIGN (4);
+    _rtos_text_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.data : ALIGN(4)
+  {
+    _clib_data_start = ABSOLUTE(.);
+    *(.clib.data)
+    . = ALIGN (4);
+    _clib_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .clib.percpu.data : ALIGN(4)
+  {
+    _clib_percpu_data_start = ABSOLUTE(.);
+    *(.clib.percpu.data)
+    . = ALIGN (4);
+    _clib_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.percpu.data : ALIGN(4)
+  {
+    _rtos_percpu_data_start = ABSOLUTE(.);
+    *(.rtos.percpu.data)
+    . = ALIGN (4);
+    _rtos_percpu_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .rtos.data : ALIGN(4)
+  {
+    _rtos_data_start = ABSOLUTE(.);
+    *(.rtos.data)
+    . = ALIGN (4);
+    _rtos_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .sram.data : ALIGN(4)
+  {
+    _sram_data_start = ABSOLUTE(.);
+    *(.sram.data)
+    . = ALIGN (4);
+    _sram_data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .resource_table : ALIGN(4)
+  {
+    _resource_table_start = ABSOLUTE(.);
+    *(.resource_table)
+    . = ALIGN (4);
+    _resource_table_end = ABSOLUTE(.);
+  } >sram0_seg :sram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    *(.sram.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_sram0_end = ALIGN(0x8);
+  } >sram0_seg :sram0_bss_phdr
+
+  PROVIDE(__stack = 0x1a800000);
+  _heap_sentry = 0x1a800000;
+  _memmap_mem_sram_max = ABSOLUTE(.);
+
+  .dram0.rodata : ALIGN(4)
+  {
+    _dram0_rodata_start = ABSOLUTE(.);
+    *(.dram0.rodata)
+    *(.dram.rodata)
+    . = ALIGN (4);
+    _dram0_rodata_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.data : ALIGN(4)
+  {
+    _dram0_data_start = ABSOLUTE(.);
+    *(.dram0.data)
+    *(.dram.data)
+    . = ALIGN (4);
+    _dram0_data_end = ABSOLUTE(.);
+  } >dram0_0_seg :dram0_0_phdr
+
+  .dram0.bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _dram0_bss_start = ABSOLUTE(.);
+    *(.dram0.bss)
+    . = ALIGN (8);
+    _dram0_bss_end = ABSOLUTE(.);
+    _memmap_seg_dram0_0_end = ALIGN(0x8);
+  } >dram0_0_seg :dram0_0_bss_phdr
+
+
+  _memmap_mem_dram0_max = ABSOLUTE(.);
+
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xr b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xr
new file mode 100644
index 00000000000..4a59d9768a3
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xr
@@ -0,0 +1,61 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -r or ld -i */
+
+
+SECTIONS
+{
+
+  .text 0 :
+  {
+    *(.literal .text)
+  }
+
+  .bss 0 :
+  {
+    *(.dynsbss)
+    *(.sbss)
+    *(.scommon)
+    *(.dynbss)
+    *(.bss)
+    *(COMMON)
+  }
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xu b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xu
new file mode 100644
index 00000000000..62a3382fb53
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/ldscripts/elf32xtensa.xu
@@ -0,0 +1,61 @@
+/* This linker script generated from xt-genldscripts.tpp for LSP . */
+/* Linker Script for ld -Ur */
+
+
+SECTIONS
+{
+
+  .text 0 :
+  {
+    *(.literal .text)
+  }
+
+  .bss 0 :
+  {
+    *(.dynsbss)
+    *(.sbss)
+    *(.scommon)
+    *(.dynbss)
+    *(.bss)
+    *(COMMON)
+  }
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    KEEP (*(.xt.prop))
+    KEEP (*(.xt.prop.*))
+    KEEP (*(.gnu.linkonce.prop.*))
+  }
+  .xt.lit 0 :
+  {
+    KEEP (*(.xt.lit))
+    KEEP (*(.xt.lit.*))
+    KEEP (*(.gnu.linkonce.p.*))
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+}
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/memmap.xmm b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/memmap.xmm
new file mode 100644
index 00000000000..85b938f379b
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/memmap.xmm
@@ -0,0 +1,93 @@
+//  Memory map file to generate linker scripts for programs run on the ISS.
+
+// Customer ID=15782; Build=0x8a8c2; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+// A memory map is a sequence of memory descriptions and
+// optional parameter assignments.
+//
+// Each memory description has the following format:
+//   BEGIN <name>
+//     <addr> [,<paddr>] : <mem-type> : <mem-name> : <size> [,<psize>]
+//                       : [writable] [,executable] [,device] ;
+//     <segment>*
+//   END <name>
+//
+// where each <segment> description has the following format:
+//     <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
+//                : <section-name>* ;
+//
+// Each parameter assignment is a keyword/value pair in the following format:
+//   <keyword> = <value>                (no spaces in <value>)
+// or
+//   <keyword> = "<value>"              (spaces allowed in <value>)
+//
+// The following primitives are also defined:
+//   PLACE SECTIONS( <section-name>* ) { WITH_SECTION(<section-name>)
+//                                       | IN_SEGMENT(<seg-name>) }
+//
+//   NOLOAD <section-name1> [ <section-name2> ... ]
+//
+// Please refer to the Xtensa LSP Reference Manual for more details.
+//
+
+
+// Additions for -mvecselect option:
+VECSELECT = 0x0
+
+BEGIN iram0
+0x21170000: instRam : iram0 : 0x10000 : executable, writable ;
+ iram0_0 : F : 0x21170000 - 0x211702df : .ResetVector.text .ResetHandler.literal .ResetHandler.text;
+ iram0_1 : C : 0x211702e0 - 0x211703ff : ;
+ iram0_2 : F : 0x21170400 - 0x21170577 : .WindowVectors.text;
+ iram0_3 : C : 0x21170578 - 0x2117057b : .Level2InterruptVector.literal;
+ iram0_4 : F : 0x2117057c - 0x21170597 : .Level2InterruptVector.text;
+ iram0_5 : C : 0x21170598 - 0x2117059b : .Level3InterruptVector.literal;
+ iram0_6 : F : 0x2117059c - 0x211705b7 : .Level3InterruptVector.text;
+ iram0_7 : C : 0x211705b8 - 0x211705bb : .DebugExceptionVector.literal;
+ iram0_8 : F : 0x211705bc - 0x211705d7 : .DebugExceptionVector.text;
+ iram0_9 : C : 0x211705d8 - 0x211705db : .NMIExceptionVector.literal;
+ iram0_10 : F : 0x211705dc - 0x211705f7 : .NMIExceptionVector.text;
+ iram0_11 : C : 0x211705f8 - 0x211705fb : .KernelExceptionVector.literal;
+ iram0_12 : F : 0x211705fc - 0x21170617 : .KernelExceptionVector.text;
+ iram0_13 : C : 0x21170618 - 0x2117061b : .UserExceptionVector.literal;
+ iram0_14 : F : 0x2117061c - 0x21170637 : .UserExceptionVector.text;
+ iram0_15 : C : 0x21170638 - 0x2117063b : .DoubleExceptionVector.literal;
+ iram0_16 : F : 0x2117063c - 0x21170657 : .DoubleExceptionVector.text;
+ iram0_17 : C : 0x21170658 - 0x2117ffff : .iram0.literal .iram0.text;
+END iram0
+
+BEGIN dram0
+0x21180000: dataRam : dram0 : 0x10000 : writable ;
+ dram0_0 : C : 0x21180000 - 0x2118ffff : .dram0.rodata .dram0.data .dram0.bss;
+END dram0
+
+BEGIN sram
+0x1a000000: sysram : sram : 0x800000 : executable, writable ;
+ sram0 : C : 0x1a000000 - 0x1a7fffff :  STACK :  HEAP : .sram.rodata .clib.rodata .rtos.rodata .rodata .sram.literal .literal .rtos.literal .clib.literal .sram.text .text .clib.text .rtos.text .clib.data .clib.percpu.data .rtos.percpu.data .rtos.data .sram.data .data __llvm_prf_names .resource_table .clib.bss .clib.percpu.bss .rtos.percpu.bss .rtos.bss .sram.bss .bss;
+END sram
+
+BEGIN srom
+0x1a800000: sysrom : srom : 0x700000 : executable ;
+ srom0 : C : 0x1a800000 - 0x1aefffff : .srom.rodata .srom.literal .srom.text .rom.store;
+END srom
+
diff --git a/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/specs b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/specs
new file mode 100644
index 00000000000..4face522a97
--- /dev/null
+++ b/tensorflow/lite/micro/xtensa_hifi/memmap/imx8ulp/specs
@@ -0,0 +1,36 @@
+# Customer ID=15782; Build=0x8a8c2; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+# The %O suffix on the start and end files indicates that the system's
+# standard suffix for object files (e.g., ".o") should be appended.
+# The %s suffix tells the compiler driver to search for the file in the
+# list of known locations for startfiles.
+
+*startfile:
+crt1-sim%O%s crti%O%s crtbegin%O%s _sharedvectors%O%s _vectors%O%s
+
+*endfile:
+crtend%O%s crtn%O%s
+
+*lib:
+-lc -lsim -lc -lhandler-reset -lhandlers-sim -lhal -lc
+
-- 
2.34.1

