/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: ClockConfig0
called_from_default_init: true
outputs:
- {id: ADC0_CLK.outFreq, value: 16 MHz}
- {id: ADC1_CLK.outFreq, value: 16 MHz}
- {id: BUS_CLK.outFreq, value: 40 MHz}
- {id: CLKOUT0_CLK.outFreq, value: 16 MHz}
- {id: CMP0_CLK.outFreq, value: 40 MHz}
- {id: CORE_CLK.outFreq, value: 80 MHz}
- {id: CRC0_CLK.outFreq, value: 40 MHz}
- {id: DMA0_CLK.outFreq, value: 80 MHz}
- {id: DMAMUX0_CLK.outFreq, value: 40 MHz}
- {id: EIM0_CLK.outFreq, value: 80 MHz}
- {id: ERM0_CLK.outFreq, value: 80 MHz}
- {id: EWM0_CLK.outFreq, value: 40 MHz}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
- {id: FIRCOUT.outFreq, value: 48 MHz}
- {id: FLASH_CLK.outFreq, value: 20 MHz}
- {id: FLEXCAN0_CLK.outFreq, value: 80 MHz}
- {id: FLEXCAN1_CLK.outFreq, value: 80 MHz}
- {id: FTFM0_CLK.outFreq, value: 20 MHz}
- {id: FTM0_CLK.outFreq, value: 16 MHz}
- {id: FTM0_EXT_CLK.outFreq, value: 32 kHz}
- {id: FTM1_CLK.outFreq, value: 16 MHz}
- {id: FTM1_EXT_CLK.outFreq, value: 32 kHz}
- {id: FTM2_CLK.outFreq, value: 16 MHz}
- {id: FTM2_EXT_CLK.outFreq, value: 32 kHz}
- {id: FTM3_CLK.outFreq, value: 16 MHz}
- {id: FTM3_EXT_CLK.outFreq, value: 32 kHz}
- {id: FlexIO0_CLK.outFreq, value: 8 MHz}
- {id: FlexIO_CLK.outFreq, value: 8 MHz}
- {id: LPI2C0_CLK.outFreq, value: 16 MHz}
- {id: LPIT0_CLK.outFreq, value: 16 MHz}
- {id: LPO_128K_CLK.outFreq, value: 128 kHz}
- {id: LPO_1K_CLK.outFreq, value: 1 kHz}
- {id: LPO_32K_CLK.outFreq, value: 32 kHz}
- {id: LPO_CLK.outFreq, value: 128 kHz}
- {id: LPSPI0_CLK.outFreq, value: 16 MHz}
- {id: LPSPI1_CLK.outFreq, value: 16 MHz}
- {id: LPSPI2_CLK.outFreq, value: 16 MHz}
- {id: LPTMR0_CLK.outFreq, value: 16 MHz}
- {id: LPUART0_CLK.outFreq, value: 16 MHz}
- {id: LPUART1_CLK.outFreq, value: 16 MHz}
- {id: MPU0_CLK.outFreq, value: 80 MHz}
- {id: MSCM0_CLK.outFreq, value: 80 MHz}
- {id: PDB0_CLK.outFreq, value: 80 MHz}
- {id: PDB1_CLK.outFreq, value: 80 MHz}
- {id: PORTA_CLK.outFreq, value: 40 MHz}
- {id: PORTB_CLK.outFreq, value: 40 MHz}
- {id: PORTC_CLK.outFreq, value: 40 MHz}
- {id: PORTD_CLK.outFreq, value: 40 MHz}
- {id: PORTE_CLK.outFreq, value: 40 MHz}
- {id: RTC0_CLK.outFreq, value: 16 MHz}
- {id: RTC_CLK.outFreq, value: 16 MHz}
- {id: RTC_CLKIN.outFreq, value: 32.768 kHz}
- {id: SCGCLKOUT_CLK.outFreq, value: 48 MHz}
- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
- {id: SIRCOUT.outFreq, value: 8 MHz}
- {id: SOSCDIV1_CLK.outFreq, value: 16 MHz}
- {id: SOSCDIV2_CLK.outFreq, value: 16 MHz}
- {id: SOSCOUT.outFreq, value: 16 MHz}
- {id: SPLLDIV1_CLK.outFreq, value: 80 MHz}
- {id: SPLLDIV2_CLK.outFreq, value: 40 MHz}
- {id: SYS_CLK.outFreq, value: 80 MHz}
- {id: TCLK0_REF.outFreq, value: 32 kHz}
- {id: TCLK1_REF.outFreq, value: 32 kHz}
- {id: TCLK2_REF.outFreq, value: 32 kHz}
- {id: TRACE_CLK.outFreq, value: 80 MHz}
settings:
- {id: DIVBUS.scale, value: '2', locked: true}
- {id: DIVCORE.scale, value: '2', locked: true}
- {id: DIVSLOW.scale, value: '4', locked: true}
- {id: FIRCDIV1.scale, value: '1', locked: true}
- {id: FIRCDIV2.scale, value: '1', locked: true}
- {id: MODULE_CLOCKS.PCC_ADC0_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_ADC1_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_FTM0_MUX.sel, value: SOSCDIV1}
- {id: MODULE_CLOCKS.PCC_FTM1_MUX.sel, value: SOSCDIV1}
- {id: MODULE_CLOCKS.PCC_FTM2_MUX.sel, value: SOSCDIV1}
- {id: MODULE_CLOCKS.PCC_FTM3_MUX.sel, value: SOSCDIV1}
- {id: MODULE_CLOCKS.PCC_FlexIO_MUX.sel, value: SIRCDIV2}
- {id: MODULE_CLOCKS.PCC_LPI2C0_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_LPIT_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_LPSPI0_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_LPSPI1_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_LPSPI2_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_LPTMR0_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_LPUART0_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.PCC_LPUART1_MUX.sel, value: SOSCDIV2}
- {id: MODULE_CLOCKS.SIM_CLKOUT_DIV.scale, value: '3', locked: true}
- {id: PREDIV.scale, value: '1', locked: true}
- {id: 'RUN:DIVBUS.scale', value: '2', locked: true}
- {id: 'RUN:DIVCORE.scale', value: '2', locked: true}
- {id: 'RUN:DIVSLOW.scale', value: '4', locked: true}
- {id: 'RUN:SCSSEL.sel', value: SPLL_CLK}
- {id: SCG_SIRCCSR_SIRCSTEN_CFG, value: Enabled}
- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscHighGain}
- {id: SCG_SOSCCFG_RANGE_CFG, value: High}
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
- {id: SCSSEL.sel, value: SPLL_CLK}
- {id: SIRCDIV1.scale, value: '1', locked: true}
- {id: SIRCDIV2.scale, value: '1', locked: true}
- {id: SOSCDIV1.scale, value: '1', locked: true}
- {id: SOSCDIV2.scale, value: '1', locked: true}
- {id: SPLLDIV1.scale, value: '2', locked: true}
- {id: SPLLDIV2.scale, value: '4', locked: true}
- {id: SPLL_mul.scale, value: '20', locked: true}
- {id: 'VLPR:DIVBUS.scale', value: '1', locked: true}
- {id: 'VLPR:DIVCORE.scale', value: '8', locked: true}
- {id: 'VLPR:DIVSLOW.scale', value: '4', locked: true}
- {id: 'VLPR:SCSSEL.sel', value: SIRC}
sources:
- {id: RTC.RTC_CLK_EXT_IN.outFreq, value: 32.768 kHz, enabled: true}
- {id: SOSC.SOSC.outFreq, value: 16 MHz, enabled: true}
- {id: tclk_clocks.tclk0_ref.outFreq, value: 32 kHz, enabled: true}
- {id: tclk_clocks.tclk1_ref.outFreq, value: 32 kHz, enabled: true}
- {id: tclk_clocks.tclk2_ref.outFreq, value: 32 kHz, enabled: true}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
   
