/*
 * CAN_Transciever_drv.h
 *
 *  Created on: Oct 13, 2020
 *      Author: yang_p1
 */

#ifndef DRIVER_INC_CAN_TRANSCIEVER_DRV_H_
#define DRIVER_INC_CAN_TRANSCIEVER_DRV_H_

/*************************************************
 *   macro
 *************************************************/

/*
 * switch define
 */
#define TJA1145




/*
 * TJA1145 register address
 */
#if defined(TJA1145)

//Mode control register(address 01h)
#define MODE_CONTROL_REG_ADDRESS                               (0x01u)
#define MODE_CONTROL_MC_WIDTH                                  (3u)
#define MODE_CONTROL_MC_SHIFT                                  (0u)
#define MODE_CONTROL_MC_MASK                                   (0x07u)
// 0x01 : sleep mode ; 0x04 : stanby mode ; 0x07 : Normal mode
#define MODE_CONTROL_MC(x)                                     (((uint8_t)(((uint8_t)(x)) << MODE_CONTROL_MC_SHIFT)) &  MODE_CONTROL_MC_MASK)
#define SLEEP_MODE                                             (1u)
#define STANDBY_MODE                                           (4u)
#define NORMAL_MODE                                            (7u)

#define MAIN_STATUS_REG_ADDRESS                                (0x03u)

#define SYS_EVENT_ENABLE_REG_ADDRESS                           (0x04u)
#define SYS_EVENT_ENABLE_OTWE_WIDTH                            (1u)
#define SYS_EVENT_ENABLE_OTWE_SHIFT                            (2u)
#define SYS_EVENT_ENABLE_OTWE_MASK                             (0x04u)
// 0 : overtemperature warning disabled  1: overtemperature warning enabled
#define SYS_EVENT_ENABLE_OTWE(x)                               (((uint8_t)(((uint8_t)(x)) << SYS_EVENT_ENABLE_OTWE_SHIFT)) &  SYS_EVENT_ENABLE_OTWE_MASK)
#define SYS_EVENT_ENABLE_SPIFE_WIDTH                           (1u)
#define SYS_EVENT_ENABLE_SPIFE_SHIFT                           (1u)
#define SYS_EVENT_ENABLE_SPIFE_MASK                            (0x02u)
// 0 : SPI failure detection disabled  1: SPI failure detection enabled
#define SYS_EVENT_ENABLE_SPIFE(x)                              (((uint8_t)(((uint8_t)(x)) << SYS_EVENT_ENABLE_SPIFE_SHIFT)) &  SYS_EVENT_ENABLE_SPIFE_MASK)

#define GENERAL_MEMORY_0_REG_ADDRESS                           (0x06u)
#define GENERAL_MEMORY_1_REG_ADDRESS                           (0x07u)
#define GENERAL_MEMORY_2_REG_ADDRESS                           (0x08u)
#define GENERAL_MEMORY_3_REG_ADDRESS                           (0x09u)

#define LOCL_CONTROL_REG_ADDRESS                               (0x0Au)
#define TRANS_SPI_WRITE_LOCK             					   (0u)
#define TRANS_SPI_WRITE_UNLOCK          					   (1u)
#define LOCL_CONTROL_LK6C_WIDTH                                (1u)
#define LOCL_CONTROL_LK6C_SHIFT                                (6u)
#define LOCL_CONTROL_LK6C_MASK                                 (0x40u)
#define LOCL_CONTROL_LK6C(x)                                   (((uint8_t)(((uint8_t)(x)) << LOCL_CONTROL_LK6C_SHIFT)) &  LOCL_CONTROL_LK6C_MASK)
#define LOCL_CONTROL_LK5C_WIDTH                                (1u)
#define LOCL_CONTROL_LK5C_SHIFT                                (5u)
#define LOCL_CONTROL_LK5C_MASK                                 (0x20u)
#define LOCL_CONTROL_LK5C(x)                                   (((uint8_t)(((uint8_t)(x)) << LOCL_CONTROL_LK5C_SHIFT)) &  LOCL_CONTROL_LK5C_MASK)
#define LOCL_CONTROL_LK4C_WIDTH                                (1u)
#define LOCL_CONTROL_LK4C_SHIFT                                (4u)
#define LOCL_CONTROL_LK4C_MASK                                 (0x10u)
#define LOCL_CONTROL_LK4C(x)                                   (((uint8_t)(((uint8_t)(x)) << LOCL_CONTROL_LK4C_SHIFT)) &  LOCL_CONTROL_LK4C_MASK)
#define LOCL_CONTROL_LK3C_WIDTH                                (1u)
#define LOCL_CONTROL_LK3C_SHIFT                                (3u)
#define LOCL_CONTROL_LK3C_MASK                                 (0x08u)
#define LOCL_CONTROL_LK3C(x)                                   (((uint8_t)(((uint8_t)(x)) << LOCL_CONTROL_LK3C_SHIFT)) &  LOCL_CONTROL_LK3C_MASK)
#define LOCL_CONTROL_LK2C_WIDTH                                (1u)
#define LOCL_CONTROL_LK2C_SHIFT                                (2u)
#define LOCL_CONTROL_LK2C_MASK                                 (0x04u)
#define LOCL_CONTROL_LK2C(x)                                   (((uint8_t)(((uint8_t)(x)) << LOCL_CONTROL_LK2C_SHIFT)) &  LOCL_CONTROL_LK2C_MASK)
#define LOCL_CONTROL_LK1C_WIDTH                                (1u)
#define LOCL_CONTROL_LK1C_SHIFT                                (1u)
#define LOCL_CONTROL_LK1C_MASK                                 (0x02u)
#define LOCL_CONTROL_LK1C(x)                                   (((uint8_t)(((uint8_t)(x)) << LOCL_CONTROL_LK1C_SHIFT)) &  LOCL_CONTROL_LK1C_MASK)
#define LOCL_CONTROL_LK0C_WIDTH                                (1u)
#define LOCL_CONTROL_LK0C_SHIFT                                (0u)
#define LOCL_CONTROL_LK0C_MASK                                 (0x01u)
#define LOCL_CONTROL_LK0C(x)                                   (((uint8_t)(((uint8_t)(x)) << LOCL_CONTROL_LK0C_SHIFT)) &  LOCL_CONTROL_LK0C_MASK)

#define CAN_CONTROL_REG_ADDRESS                                (0x20u)
#define CAN_CONTROL_CFDC_WIDTH                                 (1u)
#define CAN_CONTROL_CFDC_SHIFT                                 (6u)
#define CAN_CONTROL_CFDC_MASK                                  (0x40u)
#define CAN_FD_TYPE                                            (1u)
#define CAN_TYPE                                               (0u)
// 0 : CAN FD tolerance disabled  1: CAN FD tolerance enabled
#define MSG_TYPE_CAN            		 					   (0u)
#define MSG_TYPE_CANFD                  					   (1u)
#define CAN_CONTROL_CFDC(x)                                    (((uint8_t)(((uint8_t)(x)) << CAN_CONTROL_CFDC_SHIFT)) &  CAN_CONTROL_CFDC_MASK)
#define CAN_CONTROL_PNCOK_WIDTH                                (1u)
#define CAN_CONTROL_PNCOK_SHIFT                                (5u)
#define CAN_CONTROL_PNCOK_MASK                                 (0x20u)
// 0 : partial networking invalid 1: partial networking valid
#define CAN_CONTROL_PNCOK(x)                                   (((uint8_t)(((uint8_t)(x)) << CAN_CONTROL_PNCOK_SHIFT)) &  CAN_CONTROL_PNCOK_MASK)
#define CAN_CONTROL_CPNC_WIDTH                                 (1u)
#define CAN_CONTROL_CPNC_SHIFT                                 (4u)
#define CAN_CONTROL_CPNC_MASK                                  (0x10u)
// 0 : disable CAN selective wake-up 1: enable CAN selective wake-up
#define CAN_CONTROL_CPNC(x)                                    (((uint8_t)(((uint8_t)(x)) << CAN_CONTROL_CPNC_SHIFT)) &  CAN_CONTROL_CPNC_MASK)
#define CAN_CONTROL_CMC_WIDTH                                  (2u)
#define CAN_CONTROL_CMC_SHIFT                                  (0u)
#define CAN_CONTROL_CMC_MASK                                   (0x03u)
#define CAN_OFFLINE                                            (0u)
#define CAN_ACTIVE_UVD                                         (1u)
#define CAN_ACTIVE                                             (2u)
#define CAN_LISTEN                                             (3u)
// 0: offline mode ; 1: active mode(undervoltage detection active) 2:active mode(undervoltage detection inactive) 3:Listen-only mode
#define CAN_CONTROL_CMC(x)                                     (((uint8_t)(((uint8_t)(x)) << CAN_CONTROL_CMC_SHIFT)) &  CAN_CONTROL_CMC_MASK)
#define OFFLINE_MODE                                           (0u)
#define ACTIVE_UV_DETEC_MODE                                   (1u)
#define ACTIVE__MODE                                           (2u)
#define LISTEN_ONLY_MODE                                       (3u)

#define TRANS_STATUS_REG_ADDRESS                               (0x22u)

#define TRANS_EVENT_ENABLE_REG_ADDRESS                         (0x23u)
#define TRANS_EVENT_ENABLE_CBSE_WIDTH                          (1u)
#define TRANS_EVENT_ENABLE_CBSE_SHIFT                          (4u)
#define TRANS_EVENT_ENABLE_CBSE_MASK                           (0x10u)
// 0 : CAN-bus silence detection disabled ; 1 : CAN-bus silence detection enabled
#define TRANS_EVENT_ENABLE_CBSE(x)                             (((uint8_t)(((uint8_t)(x)) << TRANS_EVENT_ENABLE_CBSE_SHIFT)) &  TRANS_EVENT_ENABLE_CBSE_MASK)
#define TRANS_EVENT_ENABLE_CFE_WIDTH                           (1u)
#define TRANS_EVENT_ENABLE_CFE_SHIFT                           (1u)
#define TRANS_EVENT_ENABLE_CFE_MASK                            (0x02u)
// 0 : CAN failure detection disabled ; 1 : CAN failure detection enabled
#define TRANS_EVENT_ENABLE_CFE(x)                              (((uint8_t)(((uint8_t)(x)) << TRANS_EVENT_ENABLE_CFE_SHIFT)) &  TRANS_EVENT_ENABLE_CFE_MASK)
#define TRANS_EVENT_ENABLE_CWE_WIDTH                           (1u)
#define TRANS_EVENT_ENABLE_CWE_SHIFT                           (0u)
#define TRANS_EVENT_ENABLE_CWE_MASK                            (0x01u)
// 0 : CAN failure detection disabled ; 1 : CAN failure detection enabled
#define TRANS_EVENT_ENABLE_CWE(x)                              (((uint8_t)(((uint8_t)(x)) << TRANS_EVENT_ENABLE_CWE_SHIFT)) &  TRANS_EVENT_ENABLE_CWE_MASK)

#define DATA_RATE_REG_ADDRESS                         		   (0x26u)
#define DATA_RATE_CDR_WIDTH                                    (3u)
#define DATA_RATE_CDR_SHIFT                                    (0u)
#define DATA_RATE_CDR_MASK                                     (0x07u)
#define DATA_RATE_50                                           (0x00u)
#define DATA_RATE_100                                          (0x01u)
#define DATA_RATE_125                                          (0x02u)
#define DATA_RATE_250                                          (0x03u)
#define DATA_RATE_500                                          (0x05u)
#define DATA_RATE_1000                                         (0x07u)
#define DATA_RATE_CDR(x)                                       (((uint8_t)(((uint8_t)(x)) << DATA_RATE_CDR_SHIFT)) &  DATA_RATE_CDR_MASK)

#define ID_0_REG_ADDRESS                                       (0x27u)
#define EXTEND_ID_7_0_WIDTH                                    (8u)
#define EXTEND_ID_7_0_SHIFT                                    (0u)
#define EXTEND_ID_7_0_MASK                                     (0xFFu)
#define EXTEND_ID_7_0(x)									   (((uint8_t)(((uint8_t)(x)) << EXTEND_ID_7_0_SHIFT)) &  EXTEND_ID_7_0_MASK)

#define ID_1_REG_ADDRESS                                       (0x28u)
#define EXTEND_ID_15_8_WIDTH                                   (8u)
#define EXTEND_ID_15_8_SHIFT                                   (0u)
#define EXTEND_ID_15_8_MASK                                    (0xFFu)
#define EXTEND_ID_15_8(x)									   (((uint8_t)(((uint8_t)(x)) << EXTEND_ID_15_8_SHIFT)) &  EXTEND_ID_15_8_MASK)

#define ID_2_REG_ADDRESS                                       (0x29u)
#define EXTEND_ID_23_16_WIDTH                                  (8u)
#define EXTEND_ID_23_16_SHIFT                                  (0u)
#define EXTEND_ID_23_16_MASK                                   (0xFFu)
#define EXTEND_ID_23_16(x)									   (((uint8_t)(((uint8_t)(x)) << EXTEND_ID_23_16_SHIFT)) &  EXTEND_ID_23_16_MASK)
#define STANDARD_ID_5_0_WIDTH                                  (6u)
#define STANDARD_ID_5_0_SHIFT                                  (2u)
#define STANDARD_ID_5_0_MASK                                   (0xFCu)
#define STANDARD_ID_5_0(x)									   (((uint8_t)(((uint8_t)(x)) << STANDARD_ID_5_0_SHIFT)) &  STANDARD_ID_5_0_MASK)

#define ID_3_REG_ADDRESS                                       (0x2Au)
#define EXTEND_ID_28_24_WIDTH                                  (5u)
#define EXTEND_ID_28_24_SHIFT                                  (0u)
#define EXTEND_ID_28_24_MASK                                   (0x1Fu)
#define EXTEND_ID_28_24(x)									   (((uint8_t)(((uint8_t)(x)) << EXTEND_ID_28_24_SHIFT)) &  EXTEND_ID_28_24_MASK)
#define STANDARD_ID_10_6_WIDTH                                 (5u)
#define STANDARD_ID_10_6_SHIFT                                 (0u)
#define STANDARD_ID_10_6_MASK                                  (0x1Fu)
#define STANDARD_ID_10_6(x)									   (((uint8_t)(((uint8_t)(x)) << STANDARD_ID_10_6_SHIFT)) &  STANDARD_ID_10_6_MASK)

#define ID_MASK_0_REG_ADDRESS                                  (0x2Bu)
#define EXTEND_ID_MASK_7_0_WIDTH                               (8u)
#define EXTEND_ID_MASK_7_0_SHIFT                               (0u)
#define EXTEND_ID_MASK_7_0_MASK                                (0xFFu)
#define EXTEND_ID_MASK_7_0(x)								   (((uint8_t)(((uint8_t)(x)) << EXTEND_ID_MASK_7_0_SHIFT)) &  EXTEND_ID_MASK_7_0_MASK)

#define ID_MASK_1_REG_ADDRESS                                  (0x2Cu)
#define EXTEND_ID_MASK_15_8_WIDTH                              (8u)
#define EXTEND_ID_MASK_15_8_SHIFT                              (0u)
#define EXTEND_ID_MASK_15_8_MASK                               (0xFFu)
#define EXTEND_ID_MASK_15_8(x)								   (((uint8_t)(((uint8_t)(x)) << EXTEND_ID_MASK_15_8_SHIFT)) &  EXTEND_ID_MASK_15_8_MASK)

#define ID_MASK_2_REG_ADDRESS                                  (0x2Du)
#define EXTEND_ID_MASK_23_16_WIDTH                             (8u)
#define EXTEND_ID_MASK_23_16_SHIFT                             (0u)
#define EXTEND_ID_MASK_23_16_MASK                              (0xFFu)
#define EXTEND_ID_MASK_23_16(x)								   (((uint8_t)(((uint8_t)(x)) << EXTEND_ID_MASK_23_16_SHIFT)) &  EXTEND_ID_MASK_23_16_MASK)
#define STANDARD_ID_MASK_5_0_WIDTH                             (6u)
#define STANDARD_ID_MASK_5_0_SHIFT                             (2u)
#define STANDARD_ID_MASK_5_0_MASK                              (0xFCu)
#define STANDARD_ID_MASK_5_0(x)								   (((uint8_t)(((uint8_t)(x)) << STANDARD_ID_MASK_5_0_SHIFT)) &  STANDARD_ID_MASK_5_0_MASK)

#define ID_MASK_3_REG_ADDRESS                                  (0x2Eu)
#define EXTEND_ID_MASK_28_24_WIDTH                             (5u)
#define EXTEND_ID_MASK_28_24_SHIFT                             (0u)
#define EXTEND_ID_MASK_28_24_MASK                              (0x1Fu)
#define EXTEND_ID_MASK_28_24(x)								   (((uint8_t)(((uint8_t)(x)) << EXTEND_ID_MASK_28_24_SHIFT)) &  EXTEND_ID_MASK_28_24_MASK)
#define STANDARD_ID_MASK_10_6_WIDTH                            (5u)
#define STANDARD_ID_MASK_10_6_SHIFT                            (0u)
#define STANDARD_ID_MASK_10_6_MASK                             (0x1Fu)
#define STANDARD_ID_MASK_10_6(x)							   (((uint8_t)(((uint8_t)(x)) << STANDARD_ID_MASK_10_6_SHIFT)) &  STANDARD_ID_MASK_10_6_MASK)

#define FRAME_CONTROL_REG_ADDRESS                              (0x2Fu)
#define FRAME_CONTROL_IDE_WIDTH                                (1u)
#define FRAME_CONTROL_IDE_SHIFT                                (7u)
#define FRAME_CONTROL_IDE_MASK                                 (0x80u)
// 0 : standard frame format (11-bit)  1: extended frame format (29-bit)
#define MSG_ID_EXTEND                    					   (1u)
#define MSG_ID_STANDARD                 					   (0u)
#define FRAME_CONTROL_IDE(x)                                   (((uint8_t)(((uint8_t)(x)) << FRAME_CONTROL_IDE_SHIFT)) &  FRAME_CONTROL_IDE_MASK)
#define FRAME_CONTROL_PNDM_WIDTH                               (1u)
#define FRAME_CONTROL_PNDM_SHIFT                               (6u)
#define FRAME_CONTROL_PNDM_MASK                                (0x40u)
// 0: data length code and data field are ‘don’t care’ for wake-up
// 1: data length code and data field are evaluated at wake-up
#define FRAME_DATA_VALID                  					   (1u)
#define FRAME_DATA_INVALID                  				   (0u)
#define FRAME_CONTROL_PNDM(x)                                  (((uint8_t)(((uint8_t)(x)) << FRAME_CONTROL_PNDM_SHIFT)) &  FRAME_CONTROL_PNDM_MASK)
#define FRAME_CONTROL_DLC_WIDTH                                (4u)
#define FRAME_CONTROL_DLC_SHIFT                                (0u)
#define FRAME_CONTROL_DLC_MASK                                 (0x0Fu)
// 0000-1000: DLC = 0-8
// 1001-1111: DLC = 8 ; DM0 ignored
#define FRAME_CONTROL_DLC(x)                                   (((uint8_t)(((uint8_t)(x)) << FRAME_CONTROL_DLC_SHIFT)) &  FRAME_CONTROL_DLC_MASK)

#define DATA_MASK_0_REG_ADDRESS                                (0x68u)
#define DATA_MASK_0_WIDTH                                      (8u)
#define DATA_MASK_0_SHIFT                                      (0u)
#define DATA_MASK_0_MASK                                       (0xFFu)
#define DATA_MASK_0(x)									       (((uint8_t)(((uint8_t)(x)) << DATA_MASK_0_SHIFT)) &  DATA_MASK_0_MASK)

#define DATA_MASK_1_REG_ADDRESS                                (0x69u)
#define DATA_MASK_1_WIDTH                                      (8u)
#define DATA_MASK_1_SHIFT                                      (0u)
#define DATA_MASK_1_MASK                                       (0xFFu)
#define DATA_MASK_1(x)									       (((uint8_t)(((uint8_t)(x)) << DATA_MASK_1_SHIFT)) &  DATA_MASK_1_MASK)

#define DATA_MASK_2_REG_ADDRESS                                (0x6Au)
#define DATA_MASK_2_WIDTH                                      (8u)
#define DATA_MASK_2_SHIFT                                      (0u)
#define DATA_MASK_2_MASK                                       (0xFFu)
#define DATA_MASK_2(x)									       (((uint8_t)(((uint8_t)(x)) << DATA_MASK_2_SHIFT)) &  DATA_MASK_2_MASK)

#define DATA_MASK_3_REG_ADDRESS                                (0x6Bu)
#define DATA_MASK_3_WIDTH                                      (8u)
#define DATA_MASK_3_SHIFT                                      (0u)
#define DATA_MASK_3_MASK                                       (0xFFu)
#define DATA_MASK_3(x)									       (((uint8_t)(((uint8_t)(x)) << DATA_MASK_3_SHIFT)) &  DATA_MASK_3_MASK)

#define DATA_MASK_4_REG_ADDRESS                                (0x6Cu)
#define DATA_MASK_4_WIDTH                                      (8u)
#define DATA_MASK_4_SHIFT                                      (0u)
#define DATA_MASK_4_MASK                                       (0xFFu)
#define DATA_MASK_4(x)									       (((uint8_t)(((uint8_t)(x)) << DATA_MASK_4_SHIFT)) &  DATA_MASK_4_MASK)

#define DATA_MASK_5_REG_ADDRESS                                (0x6Du)
#define DATA_MASK_5_WIDTH                                      (8u)
#define DATA_MASK_5_SHIFT                                      (0u)
#define DATA_MASK_5_MASK                                       (0xFFu)
#define DATA_MASK_5(x)									       (((uint8_t)(((uint8_t)(x)) << DATA_MASK_5_SHIFT)) &  DATA_MASK_5_MASK)

#define DATA_MASK_6_REG_ADDRESS                                (0x6Eu)
#define DATA_MASK_6_WIDTH                                      (8u)
#define DATA_MASK_6_SHIFT                                      (0u)
#define DATA_MASK_6_MASK                                       (0xFFu)
#define DATA_MASK_6(x)									       (((uint8_t)(((uint8_t)(x)) << DATA_MASK_6_SHIFT)) &  DATA_MASK_6_MASK)

#define DATA_MASK_7_REG_ADDRESS                                (0x6Fu)
#define DATA_MASK_7_WIDTH                                      (8u)
#define DATA_MASK_7_SHIFT                                      (0u)
#define DATA_MASK_7_MASK                                       (0xFFu)
#define DATA_MASK_7(x)									       (((uint8_t)(((uint8_t)(x)) << DATA_MASK_7_SHIFT)) &  DATA_MASK_7_MASK)

#define WAKE_PIN_STATUS_REG_ADDRESS                            (0x4Bu)

#define WAKE_PIN_ENABLE_REG_ADDRESS                            (0x4Cu)
#define WAKE_PIN_ENABLE_WPRE_WIDTH                             (1u)
#define WAKE_PIN_ENABLE_WPRE_SHIFT                             (1u)
#define WAKE_PIN_ENABLE_WPRE_MASK                              (0x02u)
// 0 : rising-edge detection on WAKE pin disabled ; 1 : rising-edge detection on WAKE pin enabled
#define WAKE_PIN_ENABLE_WPRE(x)                                (((uint8_t)(((uint8_t)(x)) << WAKE_PIN_ENABLE_WPRE_SHIFT)) &  WAKE_PIN_ENABLE_WPRE_MASK)
#define WAKE_PIN_ENABLE_WPFE_WIDTH                             (1u)
#define WAKE_PIN_ENABLE_WPFE_SHIFT                             (0u)
#define WAKE_PIN_ENABLE_WPFE_MASK                              (0x01u)
// 0 : falling-edge detection on WAKE pin disabled ; 1 : falling-edge detection on WAKE pin enabled
#define WAKE_PIN_ENABLE_WPFE(x)                              (((uint8_t)(((uint8_t)(x)) << WAKE_PIN_ENABLE_WPFE_SHIFT)) &  WAKE_PIN_ENABLE_WPFE_MASK)

#define EVENT_CAPTURE_STATUS_REG_ADDRESS                       (0x60u)
#define EVENT_CAPTURE_STATUS_CLEAR                             (0xFFu)
#define SYSTEM_EVENT_STATUS_REG_ADDRESS                        (0x61u)
#define SYSTEM_EVEN_STATUS_CLEAR                               (0xFFu)
#define TRANS_EVENT_STATUS_REG_ADDRESS                         (0x63u)
#define TRANS_EVENT_STATUS_CLEAR                               (0xFFu)
#define WAKE_PIN_EVENT_STATUS_REG_ADDRESS                      (0x64u)
#define WAKE_PIN_EVENT_STATUS_CLEAR                            (0xFFu)
#define DEVICE_ID_REG_ADDRESS                                  (0x7Eu)

typedef    unsigned char            trans_ret;
typedef    unsigned char            reg_data_type;

#endif


#define    TRANS_RET_OK                  						(0u)
#define    TRANS_RET_NG                  						(1u)
#define    TRANS_DISABLE                  						(0u)
#define    TRANS_ENABLE                   						(1u)




/*************************************************
 *   variable
 *************************************************/
typedef struct
{
	/*CAN control register*/
	uint8_t CAN_Type;/*CAN FD ?*/
	uint8_t CAN_Partial_Cfg;/*CAN partial networking configuration*/
	uint8_t CAN_Select_WK;/*CAN selective wake-up*/
	uint8_t CAN_Mode_Select;/*transceiver operating mode selection*/
}CanTransControlCfg;

typedef struct
{
	/*Data rate register*/
	uint8_t DataRate;/*CAN data rate selection*/
	/*ID register*/
	uint32_t MsgID; /*partial network wakeup message id*/
	/*ID Mast register*/
	uint32_t MsgID_mask;/*partial network wakeup message id mask*/
	/*Frame control register*/
	uint8_t Id_format;/*starndard id? externd id?*/
	uint8_t Data_mask_en;/*wakeup frame data length and data enable?*/
	uint8_t Data_len;/*number of data bytes expected in a wakeup CAN frame*/
	uint8_t* Data_mask;/*Data mask*/
}CanTransPartialNetwork;


typedef struct
{
	/*System event capture enable register*/
	uint8_t OTWE; /*overtemperature warning enabled?*/
	uint8_t SPIFE;/*SPI failture detection enabled?*/
	/*Transceiver event capture enable register*/
	uint8_t CBSE;/*CAN-bus silence detection enabled?*/
	uint8_t CFE;/*CAN failure detection enabled?*/
	uint8_t CWE;/*CAN wake-up detection enabled?*/
	/*WAKE pin event capture enable register*/
	uint8_t WPRE;/*WAKE pin rising-edge enable?*/
	uint8_t WPFE;/*WAKE pin falling-edge enable?*/

}CanTransCaptureCfg;



/*************************************************
 *   external function
 *************************************************/
extern void transceiver_sleep_mode(void);
extern void transceiver_wakeup_mode(void);
extern void transceiver_standby_mode(void);
extern void transceiver_event_capture_cfg(CanTransCaptureCfg cfg);
extern void transceiver_partial_network_cfg(CanTransPartialNetwork cfg);
extern void transceiver_control_cfg(CanTransControlCfg cfg);







#endif /* DRIVER_INC_CAN_TRANSCIEVER_DRV_H_ */
