/*
 * LPSPI_SpiDrv.c
 *
 *  Created on: 2020Äê10ÔÂ14ÈÕ
 *      Author: zhou_l4
 */

#include "S32K148.h"
#include "S32K148_features.h"
#include "LPSPI_SpiDrv.h"
#include "interrupt_manager.h"
uint16_t tx_16bits = 0xFD00;
uint16_t LPSPI1_16bits_read;
uint8_t txbuff0[512] = {0};
uint8_t rxbuff0[512] = {0};


SPI_CallbackType SPI_Callback[5] = { 0 };
void SOSC_init_8MHz(void)
{
	/*!
	 * SOSC Initialization (8 MHz):
	 * ===================================================
	 */
	SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1)|
				   SCG_SOSCDIV_SOSCDIV2(1);  	/* SOSCDIV1 & SOSCDIV2 =1: divide by 1 		*/
	SCG->SOSCCFG  =	SCG_SOSCCFG_RANGE(2)|		/* Range=2: Medium freq (SOSC betw 1MHz-8MHz) 	*/
					SCG_SOSCCFG_EREFS_MASK;		/* HGO=0:   Config xtal osc for low power 		*/
  	  	  	  	  	  	  	  	  	  	  	  	/* EREFS=1: Input is external XTAL 			*/

  while(SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK); 	/* Ensure SOSCCSR unlocked 							*/
  SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK; 		/* LK=0:          SOSCCSR can be written 				*/
												/* SOSCCMRE=0:    OSC CLK monitor IRQ if enabled 		*/
												/* SOSCCM=0:      OSC CLK monitor disabled 			*/
												/* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled */
												/* SOSCLPEN=0:    Sys OSC disabled in VLP modes 		*/
												/* SOSCSTEN=0:    Sys OSC disabled in Stop modes 		*/
												/* SOSCEN=1:      Enable oscillator 					*/

while(!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK));	/* Wait for sys OSC clk valid */
}

void SPLL_init_160MHz(void)
{
	/*!
	 * SPLL Initialization (160 MHz):
	 * ===================================================
	 */
  while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); 	/* Ensure SPLLCSR unlocked 				*/
  SCG->SPLLCSR &= ~SCG_SPLLCSR_SPLLEN_MASK;  	/* SPLLEN=0: SPLL is disabled (default) 	*/

  SCG->SPLLDIV |= 	SCG_SPLLDIV_SPLLDIV1(2)|	/* SPLLDIV1 divide by 2 */
					SCG_SPLLDIV_SPLLDIV2(3);  	/* SPLLDIV2 divide by 4 */

  SCG->SPLLCFG = SCG_SPLLCFG_MULT(24);			/* PREDIV=0: Divide SOSC_CLK by 0+1=1 		*/
  	  	  	  	  	  	  	  	  	  	  		/* MULT=24:  Multiply sys pll by 4+24=40 	*/
										  		/* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz 	*/

  while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); 	/* Ensure SPLLCSR unlocked 						*/
  SCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK; 		/* LK=0:        SPLLCSR can be written 			*/
                             	 	 	 		/* SPLLCMRE=0:  SPLL CLK monitor IRQ if enabled 	*/
                             	 	 	 	 	/* SPLLCM=0:    SPLL CLK monitor disabled 			*/
                             	 	 	 	 	/* SPLLSTEN=0:  SPLL disabled in Stop modes 		*/
                             	 	 	 	 	/* SPLLEN=1:    Enable SPLL 						*/

  while(!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */
}

void NormalRUNmode_80MHz (void)
{
/*! Slow IRC is enabled with high range (8 MHz) in reset.
 *	Enable SIRCDIV2_CLK and SIRCDIV1_CLK, divide by 1 = 8MHz
 *  asynchronous clock source.
 * ==========================================
*/
	SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1)
				 | SCG_SIRCDIV_SIRCDIV2(1);

/*!
 *  Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL:
 *  ====================================================
 */
  SCG->RCCR=SCG_RCCR_SCS(6)      /* Select PLL as clock source 								*/
    |SCG_RCCR_DIVCORE(01)      /* DIVCORE=1, div. by 2: Core clock = 160/2 MHz = 80 MHz 		*/
    |SCG_RCCR_DIVBUS(01)       /* DIVBUS=1, div. by 2: bus clock = 40 MHz 					*/
    |SCG_RCCR_DIVSLOW(02);     /* DIVSLOW=2, div. by 2: SCG slow, flash clock= 26 2/3 MHz	*/

  while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6) {}	/* Wait for sys clk src = SPLL */
}

void WDOG_disable (void)
{
	WDOG->CNT=0xD928C520;     /* Unlock watchdog 		*/
    WDOG->TOVAL=0x0000FFFF;   /* Maximum timeout value */
    WDOG->CS = 0x00002100;    /* Disable watchdog 		*/
}
void DMA0_IRQHandler(void)
{

}
void DMA1_IRQHandler(void)
{
	DMA->CINT = DMA_CINT_CINT(1);
	SPI2_Information_Registrant_Func( rxbuff0 , 0 );
//	DMA1_TCD_init(rxbuff0,512);
}
void DMA2_IRQHandler(void)
{

}
void DMA3_IRQHandler(void)
{
	DMA->CINT = DMA_CINT_CINT(3);
}
void DMA_init(void)
{
 /* This is an initialization place holder for:   											*/
 /* 1. Enabling DMA MUX clock PCC_PCCn[PCC_DMAMUX_INDEX] (not needed when START bit used) 	*/
 /* 2. Enabling desired channels by setting ERQ bit (not needed when START bit used) 		*/
	PCC->PCCn[PCC_DMAMUX_INDEX]|=PCC_PCCn_CGC_MASK;
	DMAMUX->CHCFG[0] |= DMAMUX_CHCFG_ENBL(1);
	DMAMUX->CHCFG[0] |= DMAMUX_CHCFG_SOURCE(15);
	DMAMUX->CHCFG[1] |= DMAMUX_CHCFG_ENBL(1);
	DMAMUX->CHCFG[1] |= DMAMUX_CHCFG_SOURCE(14);
#if 0
	DMA->DCHPRI[0] = 0x0;
	DMA->DCHPRI[1] = 0x1;
	DMA->DCHPRI[2] = 0x2;
	DMA->DCHPRI[3] = 0x3;
	DMA->DCHPRI[4] = 0x4;
	DMA->DCHPRI[5] = 0x5;
	DMA->DCHPRI[6] = 0x6;
	DMA->DCHPRI[7] = 0x7;
	DMA->DCHPRI[8] = 0x8;
	DMA->DCHPRI[9] = 0x9;
	DMA->DCHPRI[10] = 0xA;
	DMA->DCHPRI[11] = 0xB;
	DMA->DCHPRI[12] = 0xC;
	DMA->DCHPRI[13] = 0xD;
	DMA->DCHPRI[14] = 0xE;
	DMA->DCHPRI[15] = 0xF;
#endif
	//DMAMUX->CHCFG[0] = DMAMUX_CHCFG_TRIG(0);
}
void DMA_SPI2_init(void)
{
 /* This is an initialization place holder for:   											*/
 /* 1. Enabling DMA MUX clock PCC_PCCn[PCC_DMAMUX_INDEX] (not needed when START bit used) 	*/
 /* 2. Enabling desired channels by setting ERQ bit (not needed when START bit used) 		*/
	PCC->PCCn[PCC_DMAMUX_INDEX]|=PCC_PCCn_CGC_MASK;
	DMAMUX->CHCFG[2] |= DMAMUX_CHCFG_ENBL(1);
	DMAMUX->CHCFG[2] |= DMAMUX_CHCFG_SOURCE(19);
	DMAMUX->CHCFG[3] |= DMAMUX_CHCFG_ENBL(1);
	DMAMUX->CHCFG[3] |= DMAMUX_CHCFG_SOURCE(18);
	//DMAMUX->CHCFG[0] = DMAMUX_CHCFG_TRIG(0);
}

void DMA0_TCD_init(uint8_t *src_addr,uint16_t len)
{
	/*!
	 * TCD0: Transfers string to a single memory location
	 * ===================================================
	 */
	//DMA->ERQ = DMA_ERQ_ERQ0(0);

	(LPSPI0->TCR) = ((LPSPI0->TCR) | (LPSPI_TCR_CONTC_MASK));
	DMA->CR = 0x80;
	DMA->TCD[0].SADDR        = DMA_TCD_SADDR_SADDR((uint32_t volatile) src_addr);
	DMA->TCD[0].DADDR        = DMA_TCD_DADDR_DADDR((uint32_t volatile) &(LPSPI0->TDR));
	DMA->TCD[0].ATTR = 0;
	DMA->TCD[0].SOFF = (uint16_t)1;
	DMA->TCD[0].DOFF = (uint16_t)0;
	DMA->TCD[0].NBYTES.MLOFFNO = 1;
	DMA->TCD[0].BITER.ELINKNO = 1;
	DMA->TCD[0].CITER.ELINKNO = 1;
	DMA->TCD[0].BITER.ELINKNO = len;
	DMA->TCD[0].CITER.ELINKNO = len;
	DMA->TCD[0].CSR = 8;
	LPSPI0->CR |= ((uint32_t)1 << LPSPI_CR_RTF_SHIFT)|((uint32_t)1 << LPSPI_CR_RRF_SHIFT);
	DMA->SERQ = 0;
	LPSPI0->DER = (LPSPI0->DER & (~LPSPI_DER_TDDE_MASK)) | ((uint32_t)1 << LPSPI_DER_TDDE_SHIFT);
#if 0
	DMA->CR = DMA_CR_EMLM(1);
  DMA->TCD[0].SADDR        = DMA_TCD_SADDR_SADDR((uint32_t volatile) &txbuff); /* Source Address. */
  DMA->TCD[0].SOFF         = DMA_TCD_SOFF_SOFF(1);   /* Src. addr add 1 byte after Transfers   */
  DMA->TCD[0].ATTR         = DMA_TCD_ATTR_SMOD(0)  | /* Src. modulo feature not used */
                             DMA_TCD_ATTR_SSIZE(0) | /* Src. read 2**0 =1 byte per transfer */
                             DMA_TCD_ATTR_DMOD(0)  | /* Dest. modulo feature not used */
                             DMA_TCD_ATTR_DSIZE(0);  /* Dest. write 2**0 =1 byte per trans. */

  DMA->TCD[0].NBYTES.MLNO  = DMA_TCD_NBYTES_MLNO_NBYTES(1); /* Transfer 1 byte /minor loop */
  DMA->TCD[0].SLAST        = DMA_TCD_SLAST_SLAST(0); 		/* Src addr change after major loop */

  DMA->TCD[0].DADDR        = DMA_TCD_DADDR_DADDR((uint32_t volatile) &(LPSPI0->TDR));	/* Destination Address. */
  DMA->TCD[0].DOFF         = DMA_TCD_DOFF_DOFF(0);     			/* No dest adr offset after transfer */
  DMA->TCD[0].CITER.ELINKNO= DMA_TCD_CITER_ELINKNO_CITER(128) | 	/* 11 minor loop iterations */
                             DMA_TCD_CITER_ELINKNO_ELINK(0);   	/* No minor loop chan link */

  DMA->TCD[0].DLASTSGA     = DMA_TCD_DLASTSGA_DLASTSGA(0); /* No dest chg after major loop */
  DMA->TCD[0].CSR          = DMA_TCD_CSR_START(0)       |  /* Clear START status flag */
                             DMA_TCD_CSR_INTMAJOR(1)    |  /* No IRQ after major loop */
                             DMA_TCD_CSR_INTHALF(0)     |  /* No IRQ after 1/2 major loop */
                             DMA_TCD_CSR_DREQ(1)        |  /* Disable chan after major loop */
                             DMA_TCD_CSR_ESG(0)         |  /* Disable Scatter Gather */
                             DMA_TCD_CSR_MAJORELINK(0)  |  /* No major loop chan link */
                             DMA_TCD_CSR_ACTIVE(0)      |  /* Clear ACTIVE status flag */
                             DMA_TCD_CSR_DONE(0)        |  /* Clear DONE status flag */
                             DMA_TCD_CSR_MAJORLINKCH(0) |  /* Chan # if major loop ch link */
                             DMA_TCD_CSR_BWC(0);           /* No eDMA stalls after R/W */
  DMA->TCD[0].BITER.ELINKNO= DMA_TCD_BITER_ELINKNO_BITER(128) |  /* Initial iteration count */
                             DMA_TCD_BITER_ELINKNO_ELINK(0);    /* No minor loop chan link */
  //DMA->TCD[0].CSR = DMA_TCD_CSR_START(0);
  //DMA->TCD[0].CSR = DMA_TCD_CSR_ACTIVE(0);
  //DMA->TCD[0].CSR = DMA_TCD_CSR_DONE(0);
#endif
}
void DMA1_TCD_init(uint8_t *dest_addr,uint16_t len)
{
	/*!
	 * TCD0: Transfers string to a single memory location
	 * ===================================================
	 */
	//DMA->ERQ = DMA_ERQ_ERQ0(0);
	LPSPI0->CR |= ((uint32_t)1 << LPSPI_CR_RTF_SHIFT)|((uint32_t)1 << LPSPI_CR_RRF_SHIFT);
	//	(LPSPI0->TCR) = ((LPSPI0->TCR) | (LPSPI_TCR_CONTC_MASK));
		DMA->INT = DMA_INT_INT1(1);
		DMA->CR = 0x80;
		DMA->TCD[1].SADDR        = DMA_TCD_SADDR_SADDR((uint32_t volatile) &(LPSPI0->RDR));
		DMA->TCD[1].DADDR        = DMA_TCD_DADDR_DADDR((uint32_t volatile) dest_addr);
		DMA->TCD[1].ATTR = 0;
		DMA->TCD[1].SOFF = (uint16_t)0;
		DMA->TCD[1].DOFF = (uint16_t)1;
		DMA->TCD[1].NBYTES.MLOFFNO = 1;
		DMA->TCD[1].BITER.ELINKNO = 1;
		DMA->TCD[1].CITER.ELINKNO = 1;
		DMA->TCD[1].BITER.ELINKNO = len;
		DMA->TCD[1].CITER.ELINKNO = len;
		DMA->TCD[1].CSR = 10;
		DMA->SERQ = 1;
		LPSPI0->DER = (LPSPI0->DER & (~LPSPI_DER_RDDE_MASK)) | ((uint32_t)1 << LPSPI_DER_RDDE_SHIFT);
}

void DMA2_TCD_init(uint8_t *src_addr,uint16_t len)
{
	/*!
	 * TCD0: Transfers string to a single memory location
	 * ===================================================
	 */
	//DMA->ERQ = DMA_ERQ_ERQ0(0);
	int i=0;


	LPSPI2->CR |= ((uint32_t)1 << LPSPI_CR_RTF_SHIFT)|((uint32_t)1 << LPSPI_CR_RRF_SHIFT);
	(LPSPI2->TCR) = ((LPSPI2->TCR) | (LPSPI_TCR_CONTC_MASK));
	DMA->CR = 0x80;
	DMA->TCD[2].SADDR        = DMA_TCD_SADDR_SADDR((uint32_t volatile) src_addr);
	DMA->TCD[2].DADDR        = DMA_TCD_DADDR_DADDR((uint32_t volatile) &(LPSPI2->TDR));
	DMA->TCD[2].ATTR = 0;
	DMA->TCD[2].SOFF = (uint16_t)1;
	DMA->TCD[2].DOFF = (uint16_t)0;
	DMA->TCD[2].NBYTES.MLOFFNO = 1;
	DMA->TCD[2].BITER.ELINKNO = 1;
	DMA->TCD[2].CITER.ELINKNO = 1;
	DMA->TCD[2].BITER.ELINKNO = len;
	DMA->TCD[2].CITER.ELINKNO = len;
	DMA->TCD[2].CSR = 8;
	DMA->SERQ = 2;
	while((DMA->TCD[2].CSR&DMA_TCD_CSR_DONE_MASK) == 0)
	{

	}
	LPSPI2->TCR &= (~(LPSPI_TCR_CONTC_MASK));

	for(i=0;i<50000;i++)
	{

	}
	//LPSPI2->SR |= ((uint32_t)1U << (uint32_t)10);
	//LPSPI2->DER = (LPSPI2->DER & (~LPSPI_DER_TDDE_MASK)) | ((uint32_t)1 << LPSPI_DER_TDDE_SHIFT);
}

void DMA3_TCD_init(uint8_t *dest_addr,uint16_t len)
{
	/*!
	 * TCD0: Transfers string to a single memory location
	 * ===================================================
	 */
	//DMA->ERQ = DMA_ERQ_ERQ0(0);
	LPSPI2->CR |= ((uint32_t)1 << LPSPI_CR_RTF_SHIFT)|((uint32_t)1 << LPSPI_CR_RRF_SHIFT);
	//	(LPSPI0->TCR) = ((LPSPI0->TCR) | (LPSPI_TCR_CONTC_MASK));
		DMA->INT = DMA_INT_INT3(1);
		DMA->CR = 0x80;
		DMA->TCD[3].SADDR        = DMA_TCD_SADDR_SADDR((uint32_t volatile) &(LPSPI2->RDR));
		DMA->TCD[3].DADDR        = DMA_TCD_DADDR_DADDR((uint32_t volatile) dest_addr);
		DMA->TCD[3].ATTR = 0;
		DMA->TCD[3].SOFF = (uint16_t)0;
		DMA->TCD[3].DOFF = (uint16_t)1;
		DMA->TCD[3].NBYTES.MLOFFNO = 1;
		DMA->TCD[3].BITER.ELINKNO = 1;
		DMA->TCD[3].CITER.ELINKNO = 1;
		DMA->TCD[3].BITER.ELINKNO = 512;
		DMA->TCD[3].CITER.ELINKNO = 512;
		DMA->TCD[3].CSR = 10;
		DMA->SERQ = 3;
		LPSPI2->DER = (LPSPI2->DER & (~LPSPI_DER_RDDE_MASK)) | ((uint32_t)1 << LPSPI_DER_RDDE_SHIFT);
}


void SPI_PORT_init (void)
{
	/*!
	 * Pins definitions
	 * ===================================================
	 *
	 * Pin number        | Function
	 * ----------------- |------------------
	 * PTA26  PTA21           | LPSPI1_PCS0
	 * PTA27             | LPSPI1_SOUT
	 * PTA28			 | LPSPI1_SCK
	 * PTA29			 | LPSPI1_SIN
	 */
	uint16_t add_counter = 0;
	  PCC->PCCn[PCC_PORTA_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
	  PORTA->PCR[30]|=PORT_PCR_MUX(4);//SO
	  PORTA->PCR[31]|=PORT_PCR_MUX(4);//PCS1
	  PCC->PCCn[PCC_PORTD_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
	  PORTD->PCR[15]|=PORT_PCR_MUX(4);//SCK
	  PORTD->PCR[16]|=PORT_PCR_MUX(4);//SI
	  PORTD->PCR[6]|=PORT_PCR_MUX(1);//GPIO

	  //PORTA->PCR[18]|=PORT_PCR_MUX(1);//PTA18 GPIO
	  //PORTA->PCR[26]|=PORT_PCR_MUX(3); /* Port B14: MUX = ALT3, LPSPI1_PCS0 */
	  //PORTA->PCR[21]|=PORT_PCR_MUX(4);
	  //PORTA->PCR[27]|=PORT_PCR_MUX(3); /* Port B15: MUX = ALT3, LPSPI1_SOUT */
	  //PORTA->PCR[28]|=PORT_PCR_MUX(3); /* Port B16: MUX = ALT3, LPSPI1_SCK */
	  //PORTA->PCR[29]|=PORT_PCR_MUX(5); /* Port B17: MUX = ALT3, LPSPI1_SIN */
	  //PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
	  //PORTB->PCR[0]|=PORT_PCR_MUX(3);
	  //PORTB->PCR[2]|=PORT_PCR_MUX(3);
	  //PCC->PCCn[PCC_PORTE_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
	  //PORTE->PCR[1]|=PORT_PCR_MUX(2);
	  //PORTE->PCR[2]|=PORT_PCR_MUX(2);
	  while(add_counter<512)
	{
	  txbuff0[add_counter] = add_counter+1;
	  add_counter++;
	}

}
void SPI2_Port_Init()
{
	PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
	PORTB->PCR[27]|=PORT_PCR_MUX(5);//SO
	PORTB->PCR[28]|=PORT_PCR_MUX(5);//SI
	PORTB->PCR[29]|=PORT_PCR_MUX(5);//SCK

	PCC->PCCn[PCC_PORTC_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
	PORTC->PCR[19]|=PORT_PCR_MUX(5);//PCS1
}
void irq_init(void)
{
	S32_NVIC->ICPR[0] = 1 << (1 % 32);  /* DMA1_IRQn (1): clr any pending IRQ*/
	S32_NVIC->ISER[0] = 1 << (1 % 32);  /* DMA1_RxTx_IRQn(1): enable IRQ */
	//S32_NVIC->IP[1] = 0x1;              /* DMA1_RxTx_IRQn(1): priority 3 of 0-15*/
	INT_SYS_SetPriority(1,1);
}
void irq_Spi2_init(void)
{
	S32_NVIC->ICPR[0] = 1 << (3 % 32);  /* DMA3_IRQn (1): clr any pending IRQ*/
	S32_NVIC->ISER[0] = 1 << (3 % 32);  /* DMA3_RxTx_IRQn(1): enable IRQ */
	S32_NVIC->IP[3] = 0x3;
}
void LPSPI0_init_master(void)
{
	/*!
	 * LPSPI1 Clocking:
	 * ===================================================
	 */
	PCC->PCCn[PCC_LPSPI0_INDEX] = 0;          		/* Disable clocks to modify PCS ( default) 	*/
	PCC->PCCn[PCC_LPSPI0_INDEX] = PCC_PCCn_PR_MASK	/* (default) Peripheral is present.			*/
								 |PCC_PCCn_CGC_MASK	/* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) 	*/
								 |PCC_PCCn_PCS(6);
	/*!
	 * LPSPI1 Initialization:
	 * ===================================================
	 */
  LPSPI0->CR    = 0x00000000;   			/* Disable module for configuration 			*/
  LPSPI0->IER   = 0x00000000;   			/* Interrupts not used 						*/
  LPSPI0->DER   = 0x00000000;    			/* DMA not used 	tx use dma							*/
  LPSPI0->CFGR0 = 0x00000000;   			/* Defaults: 									*/
                                			/* RDM0=0: rec'd data to FIFO as normal 		*/
                                			/* CIRFIFO=0; Circular FIFO is disabled 		*/
                                			/* HRSEL, HRPOL, HREN=0: Host request disabled */

  LPSPI0->CFGR1 = LPSPI_CFGR1_MASTER_MASK  /* Configurations: master mode									*/
		  	  	  |LPSPI_CFGR1_OUTCFG(1)
				  |LPSPI_CFGR1_SAMPLE(1);	/* PCSCFG=0: PCS[3:2] are enabled 								*/
											/* OUTCFG=0: Output data retains last value when CS negated	*/
											/* PINCFG=0: SIN is input, SOUT is output 						*/
											/* MATCFG=0: Match disabled 									*/
											/* PCSPOL=0: PCS is active low 								*/
											/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full 			*/
											/* AUTOPCS=0: does not apply for master mode 					*/
											/* SAMPLE=0: input data sampled on SCK edge 					*/
											/* MASTER=1: Master mode 										*/

  LPSPI0->TCR   = //LPSPI_TCR_CPHA_MASK
				  LPSPI_TCR_PRESCALE(2)
				  |LPSPI_TCR_PCS(1)
				  //|LPSPI_TCR_RXMSK(1)
				  |LPSPI_TCR_FRAMESZ(7);   /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc	*/
											/* CPOL=0: SCK inactive state is low 							*/
											/* CPHA=1: Change data on SCK lead'g, capture on trail'g edge	*/
											/* PRESCALE=2: Functional clock divided by 2**2 = 4 			*/
											/* PCS=3: Transfer using PCS3 									*/
											/* LSBF=0: Data is transfered MSB first 						*/
											/* BYSW=0: Byte swap disabled 									*/
											/* CONT, CONTC=0: Continuous transfer disabled 				*/
											/* RXMSK=0: Normal transfer: rx data stored in rx FIFO 		*/
											/* TXMSK=0: Normal transfer: data loaded from tx FIFO 			*/
											/* WIDTH=0: Single bit transfer 								*/
											/* FRAMESZ=15: # bits in frame = 15+1=16 						*/

  LPSPI0->CCR   = LPSPI_CCR_SCKPCS(4)
				  |LPSPI_CCR_PCSSCK(4)
				  |LPSPI_CCR_DBT(8)
				  |LPSPI_CCR_SCKDIV(8);   	/* Clock dividers based on prescaled func'l clk of 100 nsec 	*/
											/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) 			*/
											/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) 				*/
											/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) 			*/
											/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) 	*/

  LPSPI0->FCR   = LPSPI_FCR_TXWATER(0);   	/* RXWATER=0: Rx flags set when Rx FIFO >0 	*/
                                			/* TXWATER=3: Tx flags set when Tx FIFO <= 3 	*/
  LPSPI0->DER   |= LPSPI_DER_TDDE(1);
  LPSPI0->CR    = LPSPI_CR_MEN_MASK;
		  	  	  ///|LPSPI_CR_DBGEN_MASK;   	/* Enable module for operation 			*/
											/* DBGEN=1: module enabled in debug mode 	*/
											/* DOZEN=0: module enabled in Doze mode 	*/
											/* RST=0: Master logic not reset 			*/
											/* MEN=1: Module is enabled 				*/
  //LPSPI0->CR = LPSPI_CR_MEN(1);
}
void LPSPI2_Deinit_master(void)
{
	  LPSPI2->CR    = 0x00000000;   			/* Disable module for configuration 			*/
	  LPSPI2->IER   = 0x00000000;   			/* Interrupts not used 						*/
	  LPSPI2->DER   = 0x00000000;    			/* DMA not used 	tx use dma							*/
	  LPSPI2->CFGR0 = 0x00000000;
	  DMA->CERQ = 2;
	  DMAMUX->CHCFG[2] |= DMAMUX_CHCFG_ENBL(0);
}
void LPSPI2_init_master(void)
{
	/*!
	 * LPSPI1 Clocking:
	 * ===================================================
	 */
	PCC->PCCn[PCC_LPSPI2_INDEX] = 0;          		/* Disable clocks to modify PCS ( default) 	*/
	PCC->PCCn[PCC_LPSPI2_INDEX] = PCC_PCCn_PR_MASK	/* (default) Peripheral is present.			*/
								 |PCC_PCCn_CGC_MASK	/* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) 	*/
								 |PCC_PCCn_PCS(6);
	/*!
	 * LPSPI1 Initialization:
	 * ===================================================
	 */
  LPSPI2->CR    = 0x00000000;   			/* Disable module for configuration 			*/
  LPSPI2->IER   = 0x00000000;   			/* Interrupts not used 						*/
  LPSPI2->DER   = 0x00000000;    			/* DMA not used 	tx use dma							*/
  LPSPI2->CFGR0 = 0x00000000;   			/* Defaults: 									*/
                                			/* RDM0=0: rec'd data to FIFO as normal 		*/
                                			/* CIRFIFO=0; Circular FIFO is disabled 		*/
                                			/* HRSEL, HRPOL, HREN=0: Host request disabled */

  LPSPI2->CFGR1 = LPSPI_CFGR1_MASTER_MASK  /* Configurations: master mode									*/
				  |LPSPI_CFGR1_PCSCFG(1)
				  |LPSPI_CFGR1_OUTCFG(1)
		  	  	  |LPSPI_CFGR1_AUTOPCS(1)
		  	  	  |LPSPI_CFGR1_SAMPLE(1);	/* PCSCFG=0: PCS[3:2] are enabled 								*/
											/* OUTCFG=0: Output data retains last value when CS negated	*/
											/* PINCFG=0: SIN is input, SOUT is output 						*/
											/* MATCFG=0: Match disabled 									*/
											/* PCSPOL=0: PCS is active low 								*/
											/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full 			*/
											/* AUTOPCS=0: does not apply for master mode 					*/
											/* SAMPLE=0: input data sampled on SCK edge 					*/
											/* MASTER=1: Master mode 										*/

  LPSPI2->TCR   = LPSPI_TCR_CPHA_MASK
				  |LPSPI_TCR_PRESCALE(4)
				  |LPSPI_TCR_PCS(1)
				  |LPSPI_TCR_CONT(1)
				  //|LPSPI_TCR_CONTC(1)
				  |LPSPI_TCR_RXMSK(1)
				  |LPSPI_TCR_FRAMESZ(7);   /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc	*/
											/* CPOL=0: SCK inactive state is low 							*/
											/* CPHA=1: Change data on SCK lead'g, capture on trail'g edge	*/
											/* PRESCALE=2: Functional clock divided by 2**2 = 4 			*/
											/* PCS=3: Transfer using PCS3 									*/
											/* LSBF=0: Data is transfered MSB first 						*/
											/* BYSW=0: Byte swap disabled 									*/
											/* CONT, CONTC=0: Continuous transfer disabled 				*/
											/* RXMSK=0: Normal transfer: rx data stored in rx FIFO 		*/
											/* TXMSK=0: Normal transfer: data loaded from tx FIFO 			*/
											/* WIDTH=0: Single bit transfer 								*/
											/* FRAMESZ=15: # bits in frame = 15+1=16 						*/

  LPSPI2->CCR   = LPSPI_CCR_SCKPCS(9)
				  |LPSPI_CCR_PCSSCK(9)
				  |LPSPI_CCR_DBT(18)
				  |LPSPI_CCR_SCKDIV(18);   	/* Clock dividers based on prescaled func'l clk of 100 nsec 	*/
											/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) 			*/
											/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) 				*/
											/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) 			*/
											/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) 	*/

  LPSPI2->FCR   = LPSPI_FCR_TXWATER(3);   	/* RXWATER=0: Rx flags set when Rx FIFO >0 	*/
                                			/* TXWATER=3: Tx flags set when Tx FIFO <= 3 	*/
  LPSPI2->DER   |= LPSPI_DER_TDDE(1);
  LPSPI2->CR    = LPSPI_CR_MEN_MASK;
		  	  	  ///|LPSPI_CR_DBGEN_MASK;   	/* Enable module for operation 			*/
											/* DBGEN=1: module enabled in debug mode 	*/
											/* DOZEN=0: module enabled in Doze mode 	*/
											/* RST=0: Master logic not reset 			*/
											/* MEN=1: Module is enabled 				*/
  //LPSPI0->CR = LPSPI_CR_MEN(1);
}
void SPI0_init(void)
{
	LPSPI0_init_slave();
//LPSPI0_init_master();
	SPI_PORT_init();             /* Configure ports */
	irq_init();
	DMA_init();
//	DMA1_TCD_init(rxbuff0,512);
}
void SPI2_init(void)
{
	LPSPI2_init_master();
	irq_Spi2_init();
	SPI2_Port_Init();
	DMA_SPI2_init();

}
void LPSPI0_init_slave(void)
{
	/*!
	 * LPSPI1 Clocking:
	 * ===================================================
	 */
	PCC->PCCn[PCC_LPSPI0_INDEX] = 0;          		/* Disable clocks to modify PCS ( default) 	*/
	PCC->PCCn[PCC_LPSPI0_INDEX] = PCC_PCCn_PR_MASK	/* (default) Peripheral is present.			*/
								 |PCC_PCCn_CGC_MASK	/* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) 	*/
								 |PCC_PCCn_PCS(6);
	/*!
	 * LPSPI1 Initialization:
	 * ===================================================
	 */
  LPSPI0->CR    = 0x00000000;   			/* Disable module for configuration 			*/
  LPSPI0->IER   = 0x00000000;   			/* Interrupts not used 						*/
  LPSPI0->DER   = 0x00000000;    			/* DMA not used 	tx use dma							*/
  LPSPI0->CFGR0 = 0x00000000;   			/* Defaults: 									*/
                                			/* RDM0=0: rec'd data to FIFO as normal 		*/
                                			/* CIRFIFO=0; Circular FIFO is disabled 		*/
                                			/* HRSEL, HRPOL, HREN=0: Host request disabled */

  LPSPI0->CFGR1 = //LPSPI_CFGR1_MASTER_MASK  /* Configurations: master mode									*/
				  //|
				  LPSPI_CFGR1_SAMPLE(1)
				 |LPSPI_CFGR1_OUTCFG(1);	/* PCSCFG=0: PCS[3:2] are enabled 								*/
											/* OUTCFG=0: Output data retains last value when CS negated	*/
											/* PINCFG=0: SIN is input, SOUT is output 						*/
											/* MATCFG=0: Match disabled 									*/
											/* PCSPOL=0: PCS is active low 								*/
											/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full 			*/
											/* AUTOPCS=0: does not apply for master mode 					*/
											/* SAMPLE=0: input data sampled on SCK edge 					*/
											/* MASTER=1: Master mode 										*/

  LPSPI0->TCR   = //LPSPI_TCR_CPHA_MASK
				  //|

				  LPSPI_TCR_PRESCALE(2)
				  |LPSPI_TCR_PCS(1)
				  //|LPSPI_TCR_RXMSK(1)
				  |LPSPI_TCR_FRAMESZ(7);   /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc	*/
											/* CPOL=0: SCK inactive state is low 							*/
											/* CPHA=1: Change data on SCK lead'g, capture on trail'g edge	*/
											/* PRESCALE=2: Functional clock divided by 2**2 = 4 			*/
											/* PCS=3: Transfer using PCS3 									*/
											/* LSBF=0: Data is transfered MSB first 						*/
											/* BYSW=0: Byte swap disabled 									*/
											/* CONT, CONTC=0: Continuous transfer disabled 				*/
											/* RXMSK=0: Normal transfer: rx data stored in rx FIFO 		*/
											/* TXMSK=0: Normal transfer: data loaded from tx FIFO 			*/
											/* WIDTH=0: Single bit transfer 								*/
											/* FRAMESZ=15: # bits in frame = 15+1=16 						*/
#if 0
  LPSPI0->CCR   = LPSPI_CCR_SCKPCS(4)
				  |LPSPI_CCR_PCSSCK(4)
				  |LPSPI_CCR_DBT(8)
				  |LPSPI_CCR_SCKDIV(8);   	/* Clock dividers based on prescaled func'l clk of 100 nsec 	*/
											/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) 			*/
											/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) 				*/
											/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) 			*/
											/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) 	*/
#endif
  LPSPI0->FCR   = LPSPI_FCR_TXWATER(3);   	/* RXWATER=0: Rx flags set when Rx FIFO >0 	*/
                                			/* TXWATER=3: Tx flags set when Tx FIFO <= 3 	*/
  LPSPI0->DER   |= LPSPI_DER_TDDE(1);
  LPSPI0->CR    = LPSPI_CR_MEN_MASK;
		  	  	  ///|LPSPI_CR_DBGEN_MASK;   	/* Enable module for operation 			*/
											/* DBGEN=1: module enabled in debug mode 	*/
											/* DOZEN=0: module enabled in Doze mode 	*/
											/* RST=0: Master logic not reset 			*/
											/* MEN=1: Module is enabled 				*/
  //LPSPI0->CR = LPSPI_CR_MEN(1);
}
void LPSPI1_init_master(void)
{
	/*!
	 * LPSPI1 Clocking:
	 * ===================================================
	 */
	//PCC->PCCn[PCC_LPSPI1_INDEX] = 0;          		/* Disable clocks to modify PCS ( default) 	*/
	//PCC->PCCn[PCC_LPSPI1_INDEX] = PCC_PCCn_PR_MASK	/* (default) Peripheral is present.			*/
								 //|PCC_PCCn_CGC_MASK	/* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) 	*/
								// |PCC_PCCn_PCS(6);
	/*!
	 * LPSPI1 Initialization:
	 * ===================================================
	 */
  LPSPI0->CR    = 0x00000000;   			/* Disable module for configuration 			*/
  LPSPI0->IER   = 0x00000000;   			/* Interrupts not used 						*/
  LPSPI0->DER   = 0x00000000;   			/* DMA not used 								*/
  LPSPI0->CFGR0 = 0x00000000;   			/* Defaults: 									*/
                                			/* RDM0=0: rec'd data to FIFO as normal 		*/
                                			/* CIRFIFO=0; Circular FIFO is disabled 		*/
                                			/* HRSEL, HRPOL, HREN=0: Host request disabled */

  LPSPI0->CFGR1 = 0;  						/* Configurations: SLAVE mode									*/
											/* PCSCFG=0: PCS[3:2] are enabled 								*/
											/* OUTCFG=0: Output data retains last value when CS negated	*/
											/* PINCFG=0: SIN is input, SOUT is output 						*/
											/* MATCFG=0: Match disabled 									*/
											/* PCSPOL=0: PCS is active low 								*/
											/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full 			*/
											/* AUTOPCS=0: does not apply for master mode 					*/
											/* SAMPLE=0: input data sampled on SCK edge 					*/
											/* MASTER=1: Master mode 										*/

  LPSPI0->TCR   = LPSPI_TCR_CPHA_MASK
				  |LPSPI_TCR_PRESCALE(2)
				  |LPSPI_TCR_PCS(0)
				  |LPSPI_TCR_FRAMESZ(7);   /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc	*/
											/* CPOL=0: SCK inactive state is low 							*/
											/* CPHA=1: Change data on SCK lead'g, capture on trail'g edge	*/
											/* PRESCALE=2: Functional clock divided by 2**2 = 4 			*/
											/* PCS=3: Transfer using PCS3 									*/
											/* LSBF=0: Data is transfered MSB first 						*/
											/* BYSW=0: Byte swap disabled 									*/
											/* CONT, CONTC=0: Continuous transfer disabled 				*/
											/* RXMSK=0: Normal transfer: rx data stored in rx FIFO 		*/
											/* TXMSK=0: Normal transfer: data loaded from tx FIFO 			*/
											/* WIDTH=0: Single bit transfer 								*/
											/* FRAMESZ=15: # bits in frame = 15+1=16 						*/

 // LPSPI1->CCR   = LPSPI_CCR_SCKPCS(4)
			//	  |LPSPI_CCR_PCSSCK(4)
			//	  |LPSPI_CCR_DBT(8)
			//	  |LPSPI_CCR_SCKDIV(8);   	/* Clock dividers based on prescaled func'l clk of 100 nsec 	*/
											/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) 			*/
											/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) 				*/
											/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) 			*/
											/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) 	*/

  LPSPI0->FCR   = LPSPI_FCR_TXWATER(3);   	/* RXWATER=0: Rx flags set when Rx FIFO >0 	*/
                                			/* TXWATER=3: Tx flags set when Tx FIFO <= 3 	*/

  LPSPI0->CR    = LPSPI_CR_MEN_MASK
		  	  	  |LPSPI_CR_DBGEN_MASK;   	/* Enable module for operation 			*/
											/* DBGEN=1: module enabled in debug mode 	*/
											/* DOZEN=0: module enabled in Doze mode 	*/
											/* RST=0: Master logic not reset 			*/
											/* MEN=1: Module is enabled 				*/
}

void LPSPI1_transmit_16bits (uint16_t send)
{
  while((LPSPI1->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
                                   /* Wait for Tx FIFO available 	*/
  LPSPI1->TDR = send;              /* Transmit data 				*/
  LPSPI1->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag 				*/
}
void LPSPI2_transmit_8bits (uint8_t *send,uint16_t len)
{
  while(len > 0)
  {
	  while((LPSPI2->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
	  /* Wait for Tx FIFO available 	*/
	   LPSPI2->TDR = *send;              /* Transmit data 				*/
	   LPSPI2->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag 				*/
	   send++;
	   len--;
  }

}
uint16_t LPSPI1_receive_16bits (void)
{
  uint16_t recieve = 0;

  while((LPSPI1->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
                                   /* Wait at least one RxFIFO entry 	*/
  recieve= LPSPI1->RDR;            /* Read received data 				*/
  LPSPI1->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag 					*/
  return recieve;                  /* Return received data 			*/
}

void LPSPI0_transmit_16bits (uint16_t send)
{
  while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
                                   /* Wait for Tx FIFO available 	*/
  LPSPI0->TDR = send;              /* Transmit data 				*/
  LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag 				*/
}

uint16_t LPSPI0_receive_16bits (void)
{
  uint16_t recieve = 0;

  while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
                                   /* Wait at least one RxFIFO entry 	*/
  recieve= LPSPI0->RDR;            /* Read received data 				*/
  LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag 					*/
  return recieve;                  /* Return received data 			*/
}
void SPI_Set_Call_Back_Func( SPI_CallbackType pSPI_CallBack , uint8_t aucCallBackID )
{
	SPI_Callback[aucCallBackID] = pSPI_CallBack;
}
void SPI2_Information_Registrant_Func( uint8_t *aucpMessageBuff , uint8_t aucCallBackID )
{
	if( SPI_Callback[aucCallBackID] )
	{
		SPI_Callback[aucCallBackID]( &aucpMessageBuff[0] );
	}
}
