/*==================================================================================================
*   Project              : RTD AUTOSAR 4.7 
*   Platform             : CORTEXM
*   Peripheral           : SIUL2
*   Dependencies         : none
*
*   Autosar Version      : 4.7.0
*   Autosar Revision     : ASR_REL_4_7_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 6.0.0
*   Build Version        : S32K3_S32M27x_Real-Time_Drivers_AUTOSAR_R21-11_Version_6_0_0_D2506_ASR_REL_4_7_REV_0000_20250610
*
*   Copyright 2020 - 2025 NXP
*
*   NXP Confidential. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

#ifndef SIUL2_PORT_IP_CFG_H
#define SIUL2_PORT_IP_CFG_H

/**
*   @file      Siul2_Port_Ip_Cfg.h
*
*   @addtogroup Port_CFG
*   @{
*/

#ifdef __cplusplus
extern "C"{
#endif


/*==================================================================================================
                                         INCLUDE FILES
 1) system and project includes
 2) needed interfaces from external units
 3) internal and external interfaces from this unit
==================================================================================================*/
#include "S32K344_SIUL2.h"
#include "Siul2_Port_Ip_Types.h"

/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define SIUL2_PORT_IP_VENDOR_ID_CFG_H                       43
#define SIUL2_PORT_IP_AR_RELEASE_MAJOR_VERSION_CFG_H        4
#define SIUL2_PORT_IP_AR_RELEASE_MINOR_VERSION_CFG_H        7
#define SIUL2_PORT_IP_AR_RELEASE_REVISION_VERSION_CFG_H     0
#define SIUL2_PORT_IP_SW_MAJOR_VERSION_CFG_H                6
#define SIUL2_PORT_IP_SW_MINOR_VERSION_CFG_H                0
#define SIUL2_PORT_IP_SW_PATCH_VERSION_CFG_H                0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/
/* Check if the files Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are of the same version */
#if (SIUL2_PORT_IP_VENDOR_ID_CFG_H != SIUL2_PORT_IP_TYPES_VENDOR_ID_H)
    #error "Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h have different vendor ids"
#endif
/* Check if Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are of the same Autosar version */
#if ((SIUL2_PORT_IP_AR_RELEASE_MAJOR_VERSION_CFG_H    != SIUL2_PORT_IP_TYPES_AR_RELEASE_MAJOR_VERSION_H) || \
     (SIUL2_PORT_IP_AR_RELEASE_MINOR_VERSION_CFG_H    != SIUL2_PORT_IP_TYPES_AR_RELEASE_MINOR_VERSION_H) || \
     (SIUL2_PORT_IP_AR_RELEASE_REVISION_VERSION_CFG_H != SIUL2_PORT_IP_TYPES_AR_RELEASE_REVISION_VERSION_H) \
    )
    #error "AutoSar Version Numbers of Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are different"
#endif
/* Check if Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are of the same Software version */
#if ((SIUL2_PORT_IP_SW_MAJOR_VERSION_CFG_H != SIUL2_PORT_IP_TYPES_SW_MAJOR_VERSION_H) || \
     (SIUL2_PORT_IP_SW_MINOR_VERSION_CFG_H != SIUL2_PORT_IP_TYPES_SW_MINOR_VERSION_H) || \
     (SIUL2_PORT_IP_SW_PATCH_VERSION_CFG_H != SIUL2_PORT_IP_TYPES_SW_PATCH_VERSION_H)    \
    )
    #error "Software Version Numbers of Siul2_Port_Ip_Cfg.h and Siul2_Port_Ip_Types.h are different"
#endif
/*==================================================================================================
                                           CONSTANTS
==================================================================================================*/

/*==================================================================================================
                                      DEFINES AND MACROS
==================================================================================================*/
#define SIUL2_MSCR_SSS_MASK                      (0xFU)
#define SIUL2_MSCR_SSS_SHIFT                     (0U)
#define SIUL2_MSCR_SSS_WIDTH                     (4U)
#define SIUL2_MSCR_SSS(x)                        (((uint32)(((uint32)(x)) << SIUL2_MSCR_SSS_SHIFT)) & SIUL2_MSCR_SSS_MASK)

#define SIUL2_MSCR_SRE_MASK                      (0x4000U)
#define SIUL2_MSCR_SRE_SHIFT                     (14U)
#define SIUL2_MSCR_SRE_WIDTH                     (1U)
#define SIUL2_MSCR_SRE(x)                        (((uint32)(((uint32)(x)) << SIUL2_MSCR_SRE_SHIFT)) & SIUL2_MSCR_SRE_MASK)


/*! @brief Definitions for BOARD_InitPins Functional Group */

/*! @brief User number of configured pins */
#define NUM_OF_CONFIGURED_PINS_BOARD_InitPins 43

#define PORT_START_SEC_CONFIG_DATA_UNSPECIFIED
#include "Port_MemMap.h"

/*! @brief User configuration structure */
extern const Siul2_Port_Ip_PinSettingsConfig g_pin_mux_InitConfigArr_BOARD_InitPins[NUM_OF_CONFIGURED_PINS_BOARD_InitPins];

#define PORT_STOP_SEC_CONFIG_DATA_UNSPECIFIED
#include "Port_MemMap.h"

/*! @brief Defines for user pin and port configurations */
#define LED1_PIN                8u
#define LED1_PORT               PTF_L_HALF
#define LED2_PIN                9u
#define LED2_PORT               PTF_L_HALF
#define LED3_PIN                10u
#define LED3_PORT               PTF_L_HALF
#define TJA1102_INT_PIN         14u
#define TJA1102_INT_PORT        PTA_H_HALF
#define TJA1101_EN_PIN          2u
#define TJA1101_EN_PORT         PTB_H_HALF
#define TJA1101_RST_PIN         4u
#define TJA1101_RST_PORT        PTB_H_HALF
#define TJA1101_INT_PIN         5u
#define TJA1101_INT_PORT        PTB_H_HALF
#define SJA1105_RST_PIN         10u
#define SJA1105_RST_PORT        PTB_H_HALF
#define NJJ_INT_PIN             7u
#define NJJ_INT_PORT            PTC_L_HALF
#define FRAM_WP_PIN             2u
#define FRAM_WP_PORT            PTC_H_HALF
#define DP838_RST_PIN           3u
#define DP838_RST_PORT          PTC_H_HALF
#define USR_BTN1_PIN            4u
#define USR_BTN1_PORT           PTC_H_HALF
#define USR_BTN2_PIN            5u
#define USR_BTN2_PORT           PTC_H_HALF
#define D_IN_1_PIN              10u
#define D_IN_1_PORT             PTC_H_HALF
#define MSDI_INT_PIN            4u
#define MSDI_INT_PORT           PTD_H_HALF
#define NCK_CS_PIN              4u
#define NCK_CS_PORT             PTE_L_HALF
#define MSDI_WAKE_PIN           5u
#define MSDI_WAKE_PORT          PTE_L_HALF
#define D_IN_2_PIN              13u
#define D_IN_2_PORT             PTE_L_HALF
#define XS65_LIMP_PIN           3u
#define XS65_LIMP_PORT          PTE_H_HALF
#define SJA1124_TMF_PIN         1u
#define SJA1124_TMF_PORT        PTF_L_HALF
#define TJA1124_SLP_PIN         6u
#define TJA1124_SLP_PORT        PTF_L_HALF
#define NCK_RDY_PIN             5u
#define NCK_RDY_PORT            PTF_H_HALF
#define NJJ_BUSY_PIN            11u
#define NJJ_BUSY_PORT           PTF_H_HALF
#define NJJ_GPIO_PIN            12u
#define NJJ_GPIO_PORT           PTF_H_HALF
#define NJJ_RST_PIN             14u
#define NJJ_RST_PORT            PTF_H_HALF
#define LED5_PIN                0u
#define LED5_PORT               PTG_L_HALF
#define LED6_PIN                1u
#define LED6_PORT               PTG_L_HALF
#define LED7_PIN                2u
#define LED7_PORT               PTG_L_HALF
#define FS26_INT_PIN            3u
#define FS26_INT_PORT           PTG_L_HALF
#define TJA1044_1_STB_PIN       5u
#define TJA1044_1_STB_PORT      PTG_L_HALF
#define TJA1044_2_STB_PIN       10u
#define TJA1044_2_STB_PORT      PTG_L_HALF
#define SJA1124_INT_PIN         11u
#define SJA1124_INT_PORT        PTG_L_HALF
#define SJA1124_STAT_PIN        12u
#define SJA1124_STAT_PORT       PTG_L_HALF
#define NCK_RST_PIN             13u
#define NCK_RST_PORT            PTG_L_HALF
#define HB20_DIS_PIN            8u
#define HB20_DIS_PORT           PTG_H_HALF
#define HB20_EN_PIN             9u
#define HB20_EN_PORT            PTG_H_HALF
#define MC33879_EN_PIN          10u
#define MC33879_EN_PORT         PTG_H_HALF
#define XS65_RST_PIN            11u
#define XS65_RST_PORT           PTG_H_HALF
#define XS65_CLK_PIN            6u
#define XS65_CLK_PORT           PTC_H_HALF
#define SPI1_SIN_PIN            15u
#define SPI1_SIN_PORT           PTB_L_HALF
#define FS26_CS_PIN             5u
#define FS26_CS_PORT            PTA_H_HALF
#define SPI1_SOUT_PIN           0u
#define SPI1_SOUT_PORT          PTB_H_HALF
#define SPI1_SCK_PIN            3u
#define SPI1_SCK_PORT           PTA_H_HALF

/*==================================================================================================
                                           ENUMS
==================================================================================================*/

/*==================================================================================================
                               STRUCTURES AND OTHER TYPEDEFS
==================================================================================================*/

/*==================================================================================================
                               GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/

/*==================================================================================================
                               FUNCTION PROTOTYPES
==================================================================================================*/

#ifdef __cplusplus
}
#endif

#endif /* SIUL2_PORT_IP_CFG_H */

