/*==================================================================================================
*   Project              : RTD AUTOSAR 4.7
*   Platform             : CORTEXM
*   Peripheral           : IPV_QSPI
*   Dependencies         : None
*
*   Autosar Version      : 4.7.0
*   Autosar Revision     : ASR_REL_4_7_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 6.0.0
*   Build Version        : S32K3_RTD_6_0_0_D2506_ASR_REL_4_7_REV_0000_20250610
*
*   Copyright 2020 - 2025 NXP
*
*   NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

#ifndef QSPI_IP_HYPERFLASHREGS_H
#define QSPI_IP_HYPERFLASHREGS_H

#ifdef __cplusplus
extern "C"{
#endif


/*==================================================================================================
 *                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define QSPI_IP_HYPERFLASHREGS_VENDOR_ID_H                    43
#define QSPI_IP_HYPERFLASHREGS_AR_RELEASE_MAJOR_VERSION_H     4
#define QSPI_IP_HYPERFLASHREGS_AR_RELEASE_MINOR_VERSION_H     7
#define QSPI_IP_HYPERFLASHREGS_AR_RELEASE_REVISION_VERSION_H  0
#define QSPI_IP_HYPERFLASHREGS_SW_MAJOR_VERSION_H             6
#define QSPI_IP_HYPERFLASHREGS_SW_MINOR_VERSION_H             0
#define QSPI_IP_HYPERFLASHREGS_SW_PATCH_VERSION_H             0


/*******************************************************************************
 *                                       DEFINITIONS
 ******************************************************************************/

#if (QSPI_IP_HYPERFLASH_ENABLED == STD_ON)

/* Macros for Status Register bits manipulation */

#define QSPI_IP_HF_SR_ESTAT_MASK           0x100u

#define QSPI_IP_HF_SR_PSSB_MASK            0x400u

#define QSPI_IP_HF_SR_WBASB_MASK           0x800u

#define QSPI_IP_HF_SR_PSB_MASK             0x1000u

#define QSPI_IP_HF_SR_ESB_MASK             0x2000u

#define QSPI_IP_HF_SR_ESSB_MASK            0x4000u

#define QSPI_IP_HF_SR_DRB_MASK             0x8000u

#define QSPI_IP_HF_SR_CRCSSB_MASK          0x1u

 /* Macros for x-Volatile Configuration Register */

#define QSPI_IP_HF_xVCR_BL_MASK             0x300u
#define QSPI_IP_HF_xVCR_BL_SHIFT            8u
#define QSPI_IP_HF_xVCR_BL(x)               (((uint16)(((uint16)(x)) << QSPI_IP_HF_xVCR_BL_SHIFT))&QSPI_IP_HF_xVCR_BL_MASK)

#define QSPI_IP_HF_xVCR_RWDS_MASK           0x400u
#define QSPI_IP_HF_xVCR_RWDS_SHIFT          10u
#define QSPI_IP_HF_xVCR_RWDS(x)             (((uint16)(((uint16)(x)) << QSPI_IP_HF_xVCR_RWDS_SHIFT))&QSPI_IP_HF_xVCR_RWDS_MASK)

#define QSPI_IP_HF_xVCR_RL_MASK             0xF000u
#define QSPI_IP_HF_xVCR_RL_SHIFT            12u
#define QSPI_IP_HF_xVCR_RL(x)               (((uint16)(((uint16)(x)) << QSPI_IP_HF_xVCR_RL_SHIFT))&QSPI_IP_HF_xVCR_RL_MASK)

#define QSPI_IP_HF_xVCR_PSM_MASK            0x3u
#define QSPI_IP_HF_xVCR_PSM_SHIFT           0u
#define QSPI_IP_HF_xVCR_PSM(x)              (((uint16)(((uint16)(x)) << QSPI_IP_HF_xVCR_PSM_SHIFT))&QSPI_IP_HF_xVCR_PSM_MASK)

#define QSPI_IP_HF_xVCR_SSR_MASK            0x4u
#define QSPI_IP_HF_xVCR_SSR_SHIFT           2u
#define QSPI_IP_HF_xVCR_SSR(x)              (((uint16)(((uint16)(x)) << QSPI_IP_HF_xVCR_SSR_SHIFT))&QSPI_IP_HF_xVCR_SSR_MASK)

#define QSPI_IP_HF_xVCR_FRZ_MASK            0x8u
#define QSPI_IP_HF_xVCR_FRZ_SHIFT           3u
#define QSPI_IP_HF_xVCR_FRZ(x)              (((uint16)(((uint16)(x)) << QSPI_IP_HF_xVCR_FRZ_SHIFT))&QSPI_IP_HF_xVCR_FRZ_MASK)

#define QSPI_IP_HF_xVCR_DS_MASK             0x70u
#define QSPI_IP_HF_xVCR_DS_SHIFT            4u
#define QSPI_IP_HF_xVCR_DS(x)               (((uint16)(((uint16)(x)) << QSPI_IP_HF_xVCR_DS_SHIFT))&QSPI_IP_HF_xVCR_DS_MASK)

/* Reserved bits of the Volatile/Non-Volatile Configuration register */

#define QSPI_IP_HF_xVCR_RESERVED_BIT_3      0x800u
#define QSPI_IP_HF_xVCR_RESERVED_BIT_16     0x80

#endif /* QSPI_IP_HYPERFLASH_ENABLED == STD_ON */

#ifdef __cplusplus
}
#endif


#endif /* QSPI_IP_HYPERFLASHREGS_H */
