/*==================================================================================================
* Project : RTD AUTOSAR 4.7
* Platform : CORTEXM
* Peripheral : S32K3XX
* Dependencies : none
*
* Autosar Version : 4.7.0
* Autosar Revision : ASR_REL_4_7_REV_0000
* Autosar Conf.Variant :
* SW Version : 5.0.0
* Build Version : S32K3_RTD_5_0_0_D2408_ASR_REL_4_7_REV_0000_20241002
*
* Copyright 2020 - 2024 NXP
*
* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be 
*   used strictly in accordance with the applicable license terms.  By expressly 
*   accepting such terms or by downloading, installing, activating and/or otherwise 
*   using the software, you are agreeing that you have read, and that you agree to 
*   comply with and are bound by, such license terms.  If you do not agree to be 
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

/**
*   @file main.c
*
*   @addtogroup main_module main module documentation
*   @{
*/

/* Including necessary configuration files. */
//#include "Mcal.h"
#include "Platform.h"
#include "Pwm.h"
#include "Mcu.h"
#include "Port.h"
#include "Mcl.h"
#include "CDD_Mcl.h"
#include "CDD_Rm.h"
#include "Dma_Ip_Hw_Access.h"
#include "Emios_Pwm_Ip.h"


__attribute__(( aligned(32) )) const sint16 g_kas16DmaPwmDC[2][128] =
{
    {
          32,   64,   96,  128,  160,  192,  224,  256,  288,  320,  352,  384,  416,  448,  480,  512,
         544,  576,  608,  640,  672,  704,  736,  768,  800,  832,  864,  896,  928,  960,  992, 1024,
        1056, 1088, 1120, 1152, 1184, 1216, 1248, 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, 1536,
        1568, 1600, 1632, 1664, 1696, 1728, 1760, 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, 2048,
        2080, 2112, 2144, 2176, 2208, 2240, 2272, 2304, 2336, 2368, 2400, 2432, 2464, 2496, 2528, 2560,
        2592, 2624, 2656, 2688, 2720, 2752, 2784, 2816, 2848, 2880, 2912, 2944, 2976, 3008, 3040, 3072,
        3104, 3136, 3168, 3200, 3232, 3264, 3296, 3328, 3360, 3392, 3424, 3456, 3488, 3520, 3552, 3584,
        3616, 3648, 3680, 3712, 3744, 3776, 3808, 3840, 3872, 3904, 3936, 3968, 4000, 4032, 4064, 4096
    },
    {
        4096, 4064, 4032, 4000, 3968, 3936, 3904, 3872, 3840, 3808, 3776, 3744, 3712, 3680, 3648, 3616,
        3584, 3552, 3520, 3488, 3456, 3424, 3392, 3360, 3328, 3296, 3264, 3232, 3200, 3168, 3136, 3104,
        3072, 3040, 3008, 2976, 2944, 2912, 2880, 2848, 2816, 2784, 2752, 2720, 2688, 2656, 2624, 2592,
        2560, 2528, 2496, 2464, 2432, 2400, 2368, 2336, 2304, 2272, 2240, 2208, 2176, 2144, 2112, 2080,
        2048, 2016, 1984, 1952, 1920, 1888, 1856, 1824, 1792, 1760, 1728, 1696, 1664, 1632, 1600, 1568,
        1536, 1504, 1472, 1440, 1408, 1376, 1344, 1312, 1280, 1248, 1216, 1184, 1152, 1120, 1088, 1056,
        1024,  992,  960,  928,  896,  864,  832,  800,  768,  736,  704,  672,  640,  608,  576,  544,
         512,  480,  448,  416,  384,  352,  320,  288,  256,  224,  192,  160,  128,   96,   64,   32
    }
};


volatile int exit_code = 0;
volatile uint32 g_u32DmaCh0CallbackCounter = 0U;
volatile uint32 g_u32DmaCh0ErrorCallbackCounter = 0U;

void DMA_Ch0IsrCallback(void)
{
    g_u32DmaCh0CallbackCounter++;
}

void DMA_Ch0ErrorCallback(void)
{
    g_u32DmaCh0ErrorCallbackCounter++;
}


/*!
  \brief The main function for the project.
  \details The startup initialization sequence is the following:
 * - startup asm routine
 * - main()
*/
int main(void)
{
//    Mcl_DmaChannelStatusType stch0Status;

    /* DMA Logic Channel 0 element 0 address configuration */
    Mcl_DmaChannelScatterGatherListType stDmaCh0Elem0[2] =
    {
        {MCL_DMA_CH_SET_SOURCE_ADDRESS,      (Dma_Ip_uintPtrType)&(g_kas16DmaPwmDC[0U][0U])},
        {MCL_DMA_CH_SET_DESTINATION_ADDRESS, (Dma_Ip_uintPtrType)&(IP_EMIOS_0->CH.UC[1].B)}
    };

    /* DMA Logic Channel 0 element 1 address configuration */
    Mcl_DmaChannelScatterGatherListType stDmaCh0Elem1[2] =
    {
        {MCL_DMA_CH_SET_SOURCE_ADDRESS,      (Dma_Ip_uintPtrType)&(g_kas16DmaPwmDC[1U][0U])},
        {MCL_DMA_CH_SET_DESTINATION_ADDRESS, (Dma_Ip_uintPtrType)&(IP_EMIOS_0->CH.UC[1].B)}
    };

    /* Initialize Platform */
    Platform_Init(NULL_PTR);
    Platform_InstallIrqHandler(DMATCD0_IRQn, Dma0_Ch0_IRQHandler, NULL_PTR);

    /* Initialize the Mcu driver */
    Mcu_Init(&Mcu_Config_VS_0);

    /* Initialize the clock tree */
    Mcu_InitClock(McuClockSettingConfig_0);
    while (MCU_PLL_LOCKED != Mcu_GetPllStatus())
    {
        /* Busy wait until the System PLL is locked */
    }
    Mcu_DistributePllClock();

    /* Apply a mode configuration */
    Mcu_SetMode(McuModeSettingConf_0);

    /* Initialize all pins using the Port driver */
    Port_Init(&Port_Config_VS_0);

    /* Initialize DMAMUX */
    Rm_DmaMuxInit(&Rm_Config_VS_0);

    /* Initialize Mcl driver */
    Mcl_Init(&Mcl_Config_VS_0);

    /* Set Logic Channel 0 -> Source and Destination Address for each Scatter/Gather Element */
    Mcl_SetDmaChannelScatterGatherList(DMA_LOGIC_CH_0, DMA_LOGIC_CH_0_SGA_ELEMENT_0, stDmaCh0Elem0, 2U);
    Mcl_SetDmaChannelScatterGatherList(DMA_LOGIC_CH_0, DMA_LOGIC_CH_0_SGA_ELEMENT_1, stDmaCh0Elem1, 2U);
    Mcl_SetDmaChannelScatterGatherConfig(DMA_LOGIC_CH_0, DMA_LOGIC_CH_0_SGA_ELEMENT_0);

    /* Start transfer for logic Channel 0 */
//    Mcl_SetDmaChannelCommand(DMA_LOGIC_CH_0, MCL_DMA_CH_START_SERVICE);
//    Mcl_GetDmaChannelStatus(DMA_LOGIC_CH_0, &stch0Status);
//    while(stch0Status.Done != TRUE)
//    {
//        Mcl_GetDmaChannelStatus(DMA_LOGIC_CH_0, &stch0Status);
//    }

    /* Initialize Pwm driver, frequency of 29296.875 KHz, DC of 0% */
   // Pwm_Init(&Pwm_Config_VS_0);

    for(;;)
    {
        if(exit_code != 0)
        {
            break;
        }
    }

    return exit_code;
}

/** @} */
