/*==================================================================================================
* Project : RTD AUTOSAR 4.7
* Platform : CORTEXM
* Peripheral : S32K3XX
* Dependencies : none
*
* Autosar Version : 4.7.0
* Autosar Revision : ASR_REL_4_7_REV_0000
* Autosar Conf.Variant :
* SW Version : 5.0.0
* Build Version : S32K3_RTD_5_0_0_D2408_ASR_REL_4_7_REV_0000_20241002
*
* Copyright 2020 - 2024 NXP
*
* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms.  By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms.  If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

/**
*   @file main.c
*
*   @addtogroup main_module main module documentation
*   @{
*/

/* Including necessary configuration files. */
#include "Mcal.h"

/*Adc Lib .h*/
#include "Adc_Sar_Ip.h"

/*Clock Lib .h*/
#include "Clock_Ip.h"

/*GPIO Lib .h*/
#include "Siul2_Port_Ip.h"
#include "Siul2_Dio_Ip.h"

/*Int Cfg .h*/
#include "IntCtrl_Ip.h"

/*Emios Cfg .h*/
#include "Emios_Mcl_Ip.h"

/*Emios PWM Cfg.h*/
#include "Emios_Pwm_Ip.h"

/*Bctu Cfg .h*/
#include "Bctu_Ip.h"

/*DMA Cfg .h*/
#include "Dma_Ip.h"
#include "CDD_Rm.h"
#include "Stm_Ip.h"
#include "Stddef.h"
#include "OsIf.h"
#include "string.h"


volatile int exit_code = 0;
/* User includes */
#define ADC_Samlpe_Full			68.0f
#define ADC_Samlpe_R1			56.0f
#define ADC_Samlpe_R2			12.0f

#define NUM_OF_CONF_PINS0 4U
#define ADC_SAR_INST0	0U
//#define SarAdc_VREF		((5.0f * ADC_Samlpe_R2) / ADC_Samlpe_Full)

#define SarAdc_VREF		((5.0f * ADC_Samlpe_Full) / ADC_Samlpe_R2)

#define ADC0_PVDD_OFFSET		10U
#define ADC0_VBAT_OFFSET		70U

uint16 EmiosPwm_Test_Data = 0;

uint16 g_Result_Adc0[100];

float g_ResultInMv_Adc0[10];

volatile boolean notif_triggered = FALSE;

#define STM0_INST 0
#define STM0_CH0 0
#define STM0_CH1 1

#define STM0_CH0_CMP_INTERVAL 1000000 /* 1000mS interval */
/*!
  \brief The main function for the project.
  \details The startup initialization sequence is the following:
 * - startup asm routine
 * - main()
*/
volatile int stm_ch0_cnt = 0;
int test_cnt =0;
void stm_ch0_callback(uint8 channel)
{
	(void)channel;
	stm_ch0_cnt++;

//	/*adc soft test start*/
//	if(FALSE == notif_triggered){
//		Adc_Sar_Ip_StartConversion(0, ADC_SAR_IP_CONV_CHAIN_NORMAL);
//		notif_triggered = TRUE;
//	/*adc soft test finish*/
//	}
}

ISR(STM_0_ISR);

void Dma_IRQn(void)
{
	if(FALSE == notif_triggered){
		notif_triggered = TRUE;
	}
}

void ADC0_ECH_ISR_Callback(void)
{
	Adc_Sar_Ip_GetConvDataToArray(ADC_SAR_INST0, ADC_SAR_IP_CONV_CHAIN_NORMAL, 2U, g_Result_Adc0);

	for(uint32 i = 0; i < 2;i++)
	{
		g_ResultInMv_Adc0[i] = (uint16)( (SarAdc_VREF * g_Result_Adc0[i]) / (0x1FFF) );
	}
}
#define ADC_TOLERANCE(x,y) (((x > y) ? (x - y) : (y - x)) > 200U) /* Check that the data is within tolerated range */
uint16 Adc0_2_data = 0;
uint16 Adc0_7_data = 0;
void AdcEndOfChainNotif(void)
{
	if(TRUE == notif_triggered){
		Adc0_2_data = Adc_Sar_Ip_GetConvData(ADC_SAR_INST0, 2U);
		Adc0_7_data = Adc_Sar_Ip_GetConvData(ADC_SAR_INST0, 7U);
		//while(ADC_TOLERANCE(data,3932U));
		notif_triggered = FALSE;
	}
}

void BctuWatermarkNotif(void)
{
//	uint16 data;
	g_Result_Adc0[0] = (uint16_t) (BctuDmaFifo1[0]&0xFFFF)>>3;
	g_Result_Adc0[1] = (uint16_t) (BctuDmaFifo1[1]&0xFFFF)>>3;
	g_Result_Adc0[2] = (uint16_t) (BctuDmaFifo1[2]&0xFFFF)>>3;
	g_Result_Adc0[3] = (uint16_t) (BctuDmaFifo1[3]&0xFFFF)>>3;

	g_ResultInMv_Adc0[0] = ((float) g_Result_Adc0[0]/ (1<<12)) * (5);
	g_ResultInMv_Adc0[1] = ((float) g_Result_Adc0[1]/ (1<<12)) * (5);
	g_ResultInMv_Adc0[2] = ((float) g_Result_Adc0[2]/ (1<<12)) * (5);
	g_ResultInMv_Adc0[3] = ((float) g_Result_Adc0[3]/ (1<<12)) * (5);
 	//g_ResultInMv_Adc0[0] = (uint16)( (SarAdc_VREF * g_Result_Adc0[0] * 100) / (4096.0f) + ADC0_PVDD_OFFSET);
}

/*!
  \brief The main function for the project.
  \details The startup initialization sequence is the following:
 * - startup asm routine
 * - main()
*/
int main(void)
{
	StatusType status;
	/* Write your code here */
	//memset(g_Result_Adc0,0x88,sizeof(g_Result_Adc0));
	/*Clock init*/
	Clock_Ip_StatusType Clock_Init_Flag = CLOCK_IP_ERROR;

	Clock_Init_Flag = Clock_Ip_Init(Clock_Ip_aClockConfig);

	while(Clock_Init_Flag != CLOCK_IP_SUCCESS)
	{
		Clock_Init_Flag = Clock_Ip_Init(Clock_Ip_aClockConfig);
	}

	OsIf_Init(NULL);
	/*Int Ctrl Init*/
	IntCtrl_Ip_Init(&IntCtrlConfig_0);
	IntCtrl_Ip_InstallHandler(DMATCD0_IRQn, Dma0_Ch0_IRQHandler, NULL_PTR);
	IntCtrl_Ip_EnableIrq(DMATCD0_IRQn);

	/*Pin Init*/
	Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals,
						g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals);

	Siul2_Dio_Ip_WritePin(Vol_FBK_EN_PORT, Vol_FBK_EN_PIN, 1);


	/*Adc Init*/
	status = (StatusType) Adc_Sar_Ip_Init(0, &AdcHwUnit_0);
	while(status != E_OK)
	{
		status = (StatusType) Adc_Sar_Ip_Init(0, &AdcHwUnit_0);
	}


//	/*Dma Init*/
	Rm_Init(&Rm_Config);

	Dma_Ip_ReturnType DmaStatus = DMA_IP_STATUS_ERROR;
	DmaStatus = Dma_Ip_Init(&Dma_Ip_xDmaInitPB);
	while (DmaStatus != DMA_IP_STATUS_SUCCESS)
	{
		DmaStatus = Dma_Ip_Init(&Dma_Ip_xDmaInitPB);
	}

	/*Bctu Init*/
	Bctu_Ip_Init(0,&BctuHwUnit_0);

	/* enable HW triggers to be accepted */
	Bctu_Ip_SetGlobalTriggerEn(BCTUHWUNIT_0_INSTANCE, TRUE);

		/*adc soft test start*/

	Stm_Ip_Init(STM0_INST, &STM_0_InitConfig_PB);
	/* initialize STM0 compare channel 0 */
	Stm_Ip_InitChannel(STM0_INST, &STM_0_ChannelConfig_PB[0]);
	/* start STM0 channel 0 - set compare value, enable this channel */
	Stm_Ip_StartCounting(STM0_INST, STM0_CH0, STM0_CH0_CMP_INTERVAL);

	/* Install IRQ handler for STM0 */
	IntCtrl_Ip_InstallHandler(STM0_IRQn, STM_0_ISR, NULL_PTR);
	/* Enable STM0 interrupt in NVIC */
	IntCtrl_Ip_EnableIrq(STM0_IRQn);

	/*Emios MCL/PWM Init*/
	Emios_Pwm_Ip_InitChannel(0,&Emios_Pwm_Ip_I0_Ch6);
	Emios_Mcl_Ip_Init(0, &Emios_Mcl_Ip_0_Config);
//	IntCtrl_Ip_InstallHandler(ADC0_IRQn, AdcEndOfChainNotif, NULL_PTR);
//	IntCtrl_Ip_EnableIrq(ADC0_IRQn);
//	Adc_Sar_Ip_EnableNotifications(0, ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN | ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN);

	/*adc soft test finish*/


	//int i = 0;
    for(;;){
//    	if(TRUE == notif_triggered){
//    		Adc0_2_data = Adc_Sar_Ip_GetConvData(ADC_SAR_INST0, 2U);
//    		//while(ADC_TOLERANCE(data,3932U));
//    		notif_triggered = FALSE;
//    	}

//    	g_ResultInMv_Adc0[0] 12291
//		g_ResultInMv_Adc0[1] 11766
//		g_Result_Adc0[0]	 14196
//		g_Result_Adc0[1]	 13527
//    	if(notif_triggered == TRUE){  //for dma
//        	g_ResultInMv_Adc0[0] = (uint16)( (SarAdc_VREF * g_Result_Adc0[0] * 1000) / (32768.0f) + ADC0_PVDD_OFFSET);
 //       	g_ResultInMv_Adc0[1] = (uint16)( (SarAdc_VREF * g_Result_Adc0[1] * 1000) / (32768.0f) + ADC0_VBAT_OFFSET);
//    		notif_triggered = FALSE;
//   	}

//    	if(exit_code != 0)
//        {
//            break;
//        }
    }
    return exit_code;
}