generate/src/Platform_Cfg.o: ../generate/src/Platform_Cfg.c \
 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Platform_Cfg.h \
 ../RTD/include/Platform_TypesDef.h \
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 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Compiler.h \
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 ../RTD/include/Platform_Ipw_TypesDef.h \
 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Platform_CfgDefines.h \
 ../RTD/include/Det.h \
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 ../RTD/include/IntCtrl_Ip_TypesDef.h \
 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/IntCtrl_Ip_CfgDefines.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_NVIC.h \
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 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/System_Ip_CfgDefines.h \
 ../RTD/include/System_Ip_DeviceRegisters.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344.h \
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 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_FLEXCAN.h \
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 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_LPI2C.h \
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 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MC_RGM.h \
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 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MSCM.h \
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 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Intm_Ip_CfgDefines.h \
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 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Platform_CfgDefines.h \
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 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Platform_Ipw_Cfg.h \
 ../RTD/include/Platform_Ipw_TypesDef.h
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Platform_Cfg.h:
../RTD/include/Platform_TypesDef.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/StandardTypes.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Platform_Types.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/PlatformTypes.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Compiler.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Compiler_Cfg.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/CompilerDefinition.h:
../RTD/include/Platform_Ipw_TypesDef.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Platform_CfgDefines.h:
../RTD/include/Det.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Std_Types.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/StandardTypes.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Det_MemMap.h:
../RTD/include/IntCtrl_Ip_TypesDef.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/IntCtrl_Ip_CfgDefines.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_NVIC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_COMMON.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/BasicTypes.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MSCM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SCB.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/System_Ip_CfgDefines.h:
../RTD/include/System_Ip_DeviceRegisters.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_ADC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_AXBS_LITE.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_BCTU.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_CMU_FC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_CMU_FM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_CONFIGURATION_GPR.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_CRC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_DCM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_DCM_GPR.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_DMAMUX.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_DMA_TCD.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_EDMA.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_EIM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_EMAC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_EMIOS.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_ERM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_FCCU.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_FIRC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_FLASH.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_FLEXCAN.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_FLEXIO.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_FXOSC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_INTM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_JDC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_LCU.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_LPCMP.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_LPI2C.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_LPSPI.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_LPUART.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MCM_CM7.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MC_CGM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MC_ME.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MC_RGM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MDM_AP.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MSCM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MU.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_PFLASH.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_PIT.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_PLL.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_PMC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_PRAMC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_QUADSPI.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_QUADSPI_ARDB.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_RTC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SAI.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SDA_AP.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SELFTEST_GPR.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SEMA42.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SIRC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SIUL2.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_STCU.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_STM.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SWT.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SXOSC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_TEMPSENSE.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_TRGMUX.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_TSPC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_VIRT_WRAPPER.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_WKPU.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_XBIC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_XRDC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_NVIC.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SCB.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SYSTICK.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MPU.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_MCM_CM7.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Intm_Ip_CfgDefines.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_INTM.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Platform_CfgDefines.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Platform_MemMap.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Platform_Ipw_Cfg.h:
../RTD/include/Platform_Ipw_TypesDef.h:
