RTD/src/Siul2_Port_Ip.o: ../RTD/src/Siul2_Port_Ip.c \
 ../RTD/include/Siul2_Port_Ip.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/StandardTypes.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Platform_Types.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/PlatformTypes.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Compiler.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Compiler_Cfg.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/CompilerDefinition.h \
 B\:/projects/s32-v3.4/Uart_Example_S32K344/board/Siul2_Port_Ip_Cfg.h \
 ../RTD/include/Siul2_Port_Ip_Types.h \
 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Siul2_Port_Ip_Defines.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SIUL2.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_COMMON.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/BasicTypes.h \
 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Siul2_Port_Ip_VS_0_PBcfg.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Port_MemMap.h \
 ../RTD/include/Siul2_Port_Ip_Types.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Devassert.h \
 ../RTD/include/SchM_Port.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Rte_MemMap.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/RegLockMacros.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Soc_Ips.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/IpVersionMacros.h \
 ../RTD/include/OsIf_Internal.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Soc_Ips.h \
 B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/OsIf_Cfg.h \
 C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SYSTICK.h
../RTD/include/Siul2_Port_Ip.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/StandardTypes.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Platform_Types.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/PlatformTypes.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Compiler.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Compiler_Cfg.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/CompilerDefinition.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/board/Siul2_Port_Ip_Cfg.h:
../RTD/include/Siul2_Port_Ip_Types.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Siul2_Port_Ip_Defines.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SIUL2.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_COMMON.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/BasicTypes.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/Siul2_Port_Ip_VS_0_PBcfg.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Port_MemMap.h:
../RTD/include/Siul2_Port_Ip_Types.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Devassert.h:
../RTD/include/SchM_Port.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Rte_MemMap.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/RegLockMacros.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Soc_Ips.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/IpVersionMacros.h:
../RTD/include/OsIf_Internal.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/include/Soc_Ips.h:
B\:/projects/s32-v3.4/Uart_Example_S32K344/generate/include/OsIf_Cfg.h:
C\:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_10/SW32K3_RTD_4_4_1_0_0_D2110/Base_TS_T40D34M10I0R0/header/S32K344_SYSTICK.h:
