/* * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016 - 2018, NXP. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. Neither the name of the copyright holder nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ /*! * Description: * ===================================================================== * This short project is a starting point to learn GPIO. * An input is polled to detect a high or low level. An output is set * depending on input state. If running code on the S32K14x evaluation * board, pressing button 0 lights up the blue LED. */ #include "device_registers.h" #include "freemaster.h" /*! Port PTD0, bit 0: FRDM EVB output to blue LED */ #define PTD0 0 int globvar=1; /*! Port PTC12, bit 12: FRDM EVB input from BTN0 [SW2] */ #define PTC12 12 void WDOG_disable (void) { WDOG->CNT=0xD928C520; /* Unlock watchdog */ WDOG->TOVAL=0x0000FFFF; /* Maximum timeout value */ WDOG->CS = 0x00002100; /* Disable watchdog */ } void LPUART1_init(void) /* Init. summary: 9600 baud, 1 stop bit, 8 bit format, no parity */ { PCC->PCCn[PCC_LPUART1_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Ensure clk disabled for config */ PCC->PCCn[PCC_LPUART1_INDEX] |= PCC_PCCn_PCS(3) /* Clock Src = 3 (FIRCDIV2_CLK) */ | PCC_PCCn_CGC_MASK; /* Enable clock for LPUART1 regs */ LPUART1->BAUD = LPUART_BAUD_SBR(0x138) /* Initialize for 9600 baud, 1 stop: */ |LPUART_BAUD_OSR(15)|(1<<14)|(1<<15); /* SBR=312 (0x138): baud divisor = 48M/9600/16 = 312 */ /* OSR=15: Over sampling ratio = 15+1=16 */ /* SBNS=0: One stop bit */ /* BOTHEDGE=0: receiver samples only on rising edge */ /* M10=0: Rx and Tx use 7 to 9 bit data characters */ /* RESYNCDIS=0: Resync during rec'd data word supported */ /* LBKDIE, RXEDGIE=0: interrupts disable */ /* TDMAE, RDMAE, TDMAE=0: DMA requests disabled */ /* MAEN1, MAEN2, MATCFG=0: Match disabled */ LPUART1->CTRL = LPUART_CTRL_RE_MASK |LPUART_CTRL_TE_MASK; /* Enable transmitter & receiver, no parity, 8 bit char: */ /* RE=1: Receiver enabled */ /* TE=1: Transmitter enabled */ /* PE,PT=0: No hw parity generation or checking */ /* M7,M,R8T9,R9T8=0: 8-bit data characters*/ /* DOZEEN=0: LPUART enabled in Doze mode */ /* ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ*/ /* TxDIR=0: TxD pin is input if in single-wire mode */ /* TXINV=0: TRansmit data not inverted */ /* RWU,WAKE=0: normal operation; rcvr not in statndby */ /* IDLCFG=0: one idle character */ /* ILT=0: Idle char bit count starts after start bit */ /* SBK=0: Normal transmitter operation - no break char */ /* LOOPS,RSRC=0: no loop back */ } void LPUART1_RxTx_IRQHandler(void) { FMSTR_Isr(); } int main(void) { int counter = 0; /*! * Pins definitions * =================================================== * * Pin number | Function * ----------------- |------------------ * PTD0 | GPIO [BLUE LED] * PTC12 | GPIO [SW2] * */ /*! * Initialization * =================================================== */ SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV2(1); WDOG_disable();/* Disable Watchdog in case it is not done in startup code */ PCC-> PCCn[PCC_PORTC_INDEX] = PCC_PCCn_CGC_MASK;/* Enable clocks to peripherals (PORT modules) */ PCC-> PCCn[PCC_PORTD_INDEX] = PCC_PCCn_CGC_MASK;/* Enable clock to PORT C*/ /* Enable clock to PORT D*/ /* Configure port C12 as GPIO input (BTN 0 [SW2] on EVB) */ PTC->PDDR &= ~(1<PCR[12] = PORT_PCR_MUX(1) |PORT_PCR_PFE_MASK; /* Port C12: MUX = GPIO, input filter enabled */ /* Configure port D0 as GPIO output (LED on EVB) */ PTD->PDDR |= 1<PCR[0] = PORT_PCR_MUX(1); /* Port D0: MUX = GPIO */ PORTC->PCR[6]|=PORT_PCR_MUX(2); /* Port C6: MUX = ALT2, UART1 TX */ PORTC->PCR[7]|=PORT_PCR_MUX(2); /* Port C7: MUX = ALT2, UART1 RX */ PTC->PSOR |= 0x00000080; PTC->PDDR |= 0x00000080; LPUART1_init(); S32_NVIC->ICPR[1] = 1 << (33 % 32); S32_NVIC->ISER[1] = 1 << (33 % 32); S32_NVIC->IP[33] = 5; asm(" cpsie i"); FMSTR_Init(); /*! * Infinite for: * ======================== */ for(;;) { int i; FMSTR_Poll(); /*! -If Pad Data Input = 1 (BTN0 [SW2] pushed) * * Clear Output on port D0 (LED on) * */ if(globvar==1) { PTD-> PCOR |= 1< PSOR |= 1<PDIR & (1< PCOR |= 1< PSOR |= 1<