/*
** ###################################################################
**     Processor:           S32K36_M7
**     Compiler:            Keil ARM C/C++ Compiler
**     Reference manual:    S32K36
**     Version:             rev. 1.0, 2024-11-27
**     Build:               b241127
**
**     Abstract:
**         Peripheral Access Layer for S32K36_M7
**
**     Copyright 1997-2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2024 NXP
**
**     NXP Confidential and Proprietary. This software is owned or controlled
**     by NXP and may only be used strictly in accordance with the applicable
**     license terms. By expressly accepting such terms or by downloading,
**     installing, activating and/or otherwise using the software, you are
**     agreeing that you have read, and that you agree to comply with and are
**     bound by, such license terms. If you do not agree to be bound by the
**     applicable license terms, then you may not retain, install, activate
**     or otherwise use the software.
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
** ###################################################################
*/

/*!
 * @file S32K36_CONFIGURATION_GPR.h
 * @version 1.0
 * @date 2024-11-27
 * @brief Peripheral Access Layer for S32K36_CONFIGURATION_GPR
 *
 * This file contains register definitions and macros for easy access to their
 * bit fields.
 *
 * This file assumes LITTLE endian system.
 */

/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
* The SoC header defines typedef for all modules.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
* The SoC header defines macros for all modules and registers.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
* These are generated macros used for accessing the bit-fields from registers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.1, identifier clash
* The supported compilers use more than 31 significant characters for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.2, identifier clash
* The supported compilers use more than 31 significant characters for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.4, identifier clash
* The supported compilers use more than 31 significant characters for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.5, identifier clash
* The supported compilers use more than 31 significant characters for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
* This type qualifier is needed to ensure correct I/O access and addressing.
*/

/* Prevention from multiple including the same memory map */
#if !defined(S32K36_CONFIGURATION_GPR_H_)  /* Check if memory map has not been already included */
#define S32K36_CONFIGURATION_GPR_H_

#include "S32K36_COMMON.h"

/* ----------------------------------------------------------------------------
   -- CONFIGURATION_GPR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONFIGURATION_GPR_Peripheral_Access_Layer CONFIGURATION_GPR Peripheral Access Layer
 * @{
 */

/** CONFIGURATION_GPR - Register Layout Typedef */
typedef struct {
  uint8_t RESERVED_0[28];
  __I  uint32_t CONFIG_REG0;                       /**< General Purpose Configuration 0, offset: 0x1C */
  __IO uint32_t CONFIG_GPR1;                       /**< SBAF Version Information Low Word, offset: 0x20 */
  __IO uint32_t CONFIG_GPR2;                       /**< SBAF Version Information High Word, offset: 0x24 */
  __IO uint32_t CONFIG_GPR3;                       /**< SBAF Status Information, offset: 0x28 */
  uint8_t RESERVED_1[8];
  __I  uint32_t CONFIG_REG6;                       /**< General Purpose Configuration 6, offset: 0x34 */
  uint8_t RESERVED_2[44];
  __IO uint32_t CONFIG_REG_GPR;                    /**< Configuration REG_GPR, offset: 0x64 */
} CONFIGURATION_GPR_Type, *CONFIGURATION_GPR_MemMapPtr;

/** Number of instances of the CONFIGURATION_GPR module. */
#define CONFIGURATION_GPR_INSTANCE_COUNT         (1u)

/* CONFIGURATION_GPR - Peripheral instance base addresses */
/** Peripheral CONFIGURATION_GPR base address */
#define IP_CONFIGURATION_GPR_BASE                (0x4039C000u)
/** Peripheral CONFIGURATION_GPR base pointer */
#define IP_CONFIGURATION_GPR                     ((CONFIGURATION_GPR_Type *)IP_CONFIGURATION_GPR_BASE)
/** Array initializer of CONFIGURATION_GPR peripheral base addresses */
#define IP_CONFIGURATION_GPR_BASE_ADDRS          { IP_CONFIGURATION_GPR_BASE }
/** Array initializer of CONFIGURATION_GPR peripheral base pointers */
#define IP_CONFIGURATION_GPR_BASE_PTRS           { IP_CONFIGURATION_GPR }

/* ----------------------------------------------------------------------------
   -- CONFIGURATION_GPR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONFIGURATION_GPR_Register_Masks CONFIGURATION_GPR Register Masks
 * @{
 */

/*! @name CONFIG_REG0 - General Purpose Configuration 0 */
/*! @{ */

#define CONFIGURATION_GPR_CONFIG_REG0_EDB_MASK   (0x40U)
#define CONFIGURATION_GPR_CONFIG_REG0_EDB_SHIFT  (6U)
#define CONFIGURATION_GPR_CONFIG_REG0_EDB_WIDTH  (1U)
#define CONFIGURATION_GPR_CONFIG_REG0_EDB(x)     (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG0_EDB_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG0_EDB_MASK)
/*! @} */

/*! @name CONFIG_GPR1 - SBAF Version Information Low Word */
/*! @{ */

#define CONFIGURATION_GPR_CONFIG_GPR1_SOC_TYPE_MASK (0xFF00U)
#define CONFIGURATION_GPR_CONFIG_GPR1_SOC_TYPE_SHIFT (8U)
#define CONFIGURATION_GPR_CONFIG_GPR1_SOC_TYPE_WIDTH (8U)
#define CONFIGURATION_GPR_CONFIG_GPR1_SOC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR1_SOC_TYPE_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR1_SOC_TYPE_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR1_FW_TYPE_MASK (0xFFFF0000U)
#define CONFIGURATION_GPR_CONFIG_GPR1_FW_TYPE_SHIFT (16U)
#define CONFIGURATION_GPR_CONFIG_GPR1_FW_TYPE_WIDTH (16U)
#define CONFIGURATION_GPR_CONFIG_GPR1_FW_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR1_FW_TYPE_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR1_FW_TYPE_MASK)
/*! @} */

/*! @name CONFIG_GPR2 - SBAF Version Information High Word */
/*! @{ */

#define CONFIGURATION_GPR_CONFIG_GPR2_BASELINE_NUMBER_MASK (0xFF00U)
#define CONFIGURATION_GPR_CONFIG_GPR2_BASELINE_NUMBER_SHIFT (8U)
#define CONFIGURATION_GPR_CONFIG_GPR2_BASELINE_NUMBER_WIDTH (8U)
#define CONFIGURATION_GPR_CONFIG_GPR2_BASELINE_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR2_BASELINE_NUMBER_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR2_BASELINE_NUMBER_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR2_INCREMENTAL_NUMBER_MASK (0xFF0000U)
#define CONFIGURATION_GPR_CONFIG_GPR2_INCREMENTAL_NUMBER_SHIFT (16U)
#define CONFIGURATION_GPR_CONFIG_GPR2_INCREMENTAL_NUMBER_WIDTH (8U)
#define CONFIGURATION_GPR_CONFIG_GPR2_INCREMENTAL_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR2_INCREMENTAL_NUMBER_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR2_INCREMENTAL_NUMBER_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR2_RC_NUMBER_MASK (0xFF000000U)
#define CONFIGURATION_GPR_CONFIG_GPR2_RC_NUMBER_SHIFT (24U)
#define CONFIGURATION_GPR_CONFIG_GPR2_RC_NUMBER_WIDTH (8U)
#define CONFIGURATION_GPR_CONFIG_GPR2_RC_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR2_RC_NUMBER_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR2_RC_NUMBER_MASK)
/*! @} */

/*! @name CONFIG_GPR3 - SBAF Status Information */
/*! @{ */

#define CONFIGURATION_GPR_CONFIG_GPR3_HSE_FW_MASK (0x1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HSE_FW_SHIFT (0U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HSE_FW_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HSE_FW(x)  (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_HSE_FW_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_HSE_FW_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_MU_E_MASK  (0x2U)
#define CONFIGURATION_GPR_CONFIG_GPR3_MU_E_SHIFT (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_MU_E_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_MU_E(x)    (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_MU_E_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_MU_E_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_CFE_MASK (0x4U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_CFE_SHIFT (2U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_CFE_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_CFE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_HFW_CFE_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_HFW_CFE_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_DFE_MASK (0x8U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_DFE_SHIFT (3U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_DFE_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_DFE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_HFW_DFE_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_HFW_DFE_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_P_MASK (0x10U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_P_SHIFT (4U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_P_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_HFW_P(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_HFW_P_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_HFW_P_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_ACB_MASK   (0x20U)
#define CONFIGURATION_GPR_CONFIG_GPR3_ACB_SHIFT  (5U)
#define CONFIGURATION_GPR_CONFIG_GPR3_ACB_WIDTH  (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_ACB(x)     (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_ACB_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_ACB_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_IVTVS_MASK (0x80U)
#define CONFIGURATION_GPR_CONFIG_GPR3_IVTVS_SHIFT (7U)
#define CONFIGURATION_GPR_CONFIG_GPR3_IVTVS_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_IVTVS(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_IVTVS_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_IVTVS_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_UTAWA_MASK (0x10000U)
#define CONFIGURATION_GPR_CONFIG_GPR3_UTAWA_SHIFT (16U)
#define CONFIGURATION_GPR_CONFIG_GPR3_UTAWA_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_UTAWA(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_UTAWA_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_UTAWA_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_B0AWA_MASK (0x20000U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B0AWA_SHIFT (17U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B0AWA_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B0AWA(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_B0AWA_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_B0AWA_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_B1AWA_MASK (0x40000U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B1AWA_SHIFT (18U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B1AWA_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B1AWA(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_B1AWA_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_B1AWA_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_B2AWA_MASK (0x80000U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B2AWA_SHIFT (19U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B2AWA_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B2AWA(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_B2AWA_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_B2AWA_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_UTARA_MASK (0x1000000U)
#define CONFIGURATION_GPR_CONFIG_GPR3_UTARA_SHIFT (24U)
#define CONFIGURATION_GPR_CONFIG_GPR3_UTARA_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_UTARA(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_UTARA_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_UTARA_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_B0ARA_MASK (0x2000000U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B0ARA_SHIFT (25U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B0ARA_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B0ARA(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_B0ARA_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_B0ARA_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_B1ARA_MASK (0x4000000U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B1ARA_SHIFT (26U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B1ARA_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B1ARA(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_B1ARA_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_B1ARA_MASK)

#define CONFIGURATION_GPR_CONFIG_GPR3_B2ARA_MASK (0x8000000U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B2ARA_SHIFT (27U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B2ARA_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_GPR3_B2ARA(x)   (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_GPR3_B2ARA_SHIFT)) & CONFIGURATION_GPR_CONFIG_GPR3_B2ARA_MASK)
/*! @} */

/*! @name CONFIG_REG6 - General Purpose Configuration 6 */
/*! @{ */

#define CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_MASK (0x1U)
#define CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_SHIFT (0U)
#define CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_QUADSPI_SDID_PCTL_MASK)

#define CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_MASK (0x4U)
#define CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_SHIFT (2U)
#define CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_EMAC_CLOCK_GATE_MASK)

#define CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_MASK (0x10U)
#define CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_SHIFT (4U)
#define CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_FLEXIO_CLOCK_GATE_MASK)

#define CONFIGURATION_GPR_CONFIG_REG6_HARD_LOCK_MASK (0x80000000U)
#define CONFIGURATION_GPR_CONFIG_REG6_HARD_LOCK_SHIFT (31U)
#define CONFIGURATION_GPR_CONFIG_REG6_HARD_LOCK_WIDTH (1U)
#define CONFIGURATION_GPR_CONFIG_REG6_HARD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG6_HARD_LOCK_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG6_HARD_LOCK_MASK)
/*! @} */

/*! @name CONFIG_REG_GPR - Configuration REG_GPR */
/*! @{ */

#define CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK (0x3U)
#define CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT (0U)
#define CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_WIDTH (2U)
#define CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK)

#define CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_MASK (0xE0000000U)
#define CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_SHIFT (29U)
#define CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_WIDTH (3U)
#define CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC(x) (((uint32_t)(((uint32_t)(x)) << CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_SHIFT)) & CONFIGURATION_GPR_CONFIG_REG_GPR_APP_CORE_ACC_MASK)
/*! @} */

/*!
 * @}
 */ /* end of group CONFIGURATION_GPR_Register_Masks */

/*!
 * @}
 */ /* end of group CONFIGURATION_GPR_Peripheral_Access_Layer */

#endif  /* #if !defined(S32K36_CONFIGURATION_GPR_H_) */
