/*
 * RTIC.c
 *
 */
 
 #define uswap_32(x) \
    ((((x) & 0xFF000000) >> 24) | \
     (((x) & 0x00FF0000) >>  8) | \
     (((x) & 0x0000FF00) <<  8) | \
     (((x) & 0x000000FF) << 24))
 # define cpu_to_le32(x)     uswap_32(x)
#define __arch_putl(v,a)        (*(volatile u32 *)(a) = (v))
#define __raw_writel(v,a)   __arch_putl(v,a)
#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
#define out_le32(a, v)	out_arch(l, le32, a, v)
#define sec_out32(a, v)   out_le32((ulong *)(ulong)a, v)


void RTIC()
{      
       
          sec_out32(0x176001c, 0x000000ff);  //<- # set RTIC Throttle (RTHR)
          
          sec_out32(0x176002c, 0x0000ffff);  //<- # set RTIC Watchdog Timer (RWDOG)
         
          sec_out32(0x1760014, 0x00001110);  //<- Enable and unlock run time memory (RCTL)
         
          sec_out32(0x176000c, 0x00000004);  //<- Enable Run Time Check (RMAL)
          
          sec_out32(0x1760104, 0x80000000);  //<- # set RTIC monitor address (RMAA)
                    
          sec_out32(0x176010c, 0x00000100);  //<- # set RTIC monitor length (RMAL)
		  
          sec_out32(0x176000c, 0x00000002);  //<- Hash block A once (RMAL)
                  
}