U-Boot 2018.03 (Jan 04 2021 - 16:22:27 +0800)

SoC:  LS1043A Rev1.1 (0x87920111)
Clock Configuration:
       CPU0(A53):1300 MHz  CPU1(A53):1300 MHz  CPU2(A53):1300 MHz  
       CPU3(A53):1300 MHz  
       Bus:      400  MHz  DDR:      1300 MT/s  FMAN:     500  MHz
Reset Configuration Word (RCW):
       00000000: 080d000d 0a000000 00000000 00000000
       00000010: 24550002 80004002 40044000 c1002000
       00000020: 00000000 00000000 00000000 00028800
       00000030: 20044500 00001002 00000096 00000001
Model: LS1043A RDB Board
Board: LS1043ARDB, boot from Invalid setting of SW4
CPLD:  V0.0
PCBA:  V0.0
SERDES Reference Clocks:
SD1_CLK1 = 100.00MHZ, SD1_CLK2 = 100.00MHZ
I2C:   ready
DRAM:  Initialzing DDR using fixed setting
Configuring DDR for 1300 MT/s data rate
1.9 GiB (DDR4, 32-bit, CL=11, ECC off)
Using SERDES1 Protocol: 9301 (0x2455)
PPA Firmware: Version LSDK-18.06
SEC Firmware: 'loadables' present in config
loadables: 'trustedOS@1'
ERROR:   [0x0] TEE-CORE:tee_otp_get_hw_unique_key:195: 
H/W Unique key is not fetched from the platform.
MMC:   FSL_SDHC: 0
Loading Environment from SPI Flash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
OK
EEPROM: Read failed.
In:    serial
Out:   serial
Err:   serial
#####scfg value is [1111]
#####scfg value 2  is [0]
SCSI:  PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 Root Complex: no link
PCIe2: pcie@3600000 Root Complex: no link
Error: SCSI Controller(s) 1B4B:9170 not found
Net:   Invalid SerDes protocol 0x2455 for LS1043ARDB
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
Fman1: Uploading microcode version 106.4.18
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
FM1@DTSEC1 [PRIME], FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, FM1@DTSEC6, FM1@DTSEC9
Hit any key to stop autoboot:  0 
=> mdio list
FSL_MDIO0:
1 - AR8031/AR8033 <--> FM1@DTSEC3
2 - AR8031/AR8033 <--> FM1@DTSEC4
8 - Generic PHY <--> FM1@DTSEC1
9 - Generic PHY <--> FM1@DTSEC2
a - Generic PHY <--> FM1@DTSEC5
b - Generic PHY <--> FM1@DTSEC6
FM_TGEC_MDIO:
=>