/*
* LS1046AFRWY RCW for SerDes Protocol 0x3040_0x0506
*
* 4G configuration -- 4G QSGMII +  2 PCIe
*
* Frequencies:
*
* Sys Clock: 100 MHz
* DDR_Refclock: 100 MHz
*
* Core		-- 1600 MHz (Mul 16)
* Platform	-- 600 MHz (Mul 6)
* DDR		-- 2100 MT/s (Mul 21)
* FMan		-- 700 MHz (CGA2 /2)
* QSGMII	-- 100 MHz (5G)
* PCIE		-- 100 MHz (5G)
* eSDHC	-- 1400 MHz (CGA2 /1)
*
* Hardware Accelerator Block Cluster Group A Mux Clock:
*   FMan        - HWA_CGA_M1_CLK_SEL = 6 - Async mode, CGA PLL 2 /2 is clock
*   eSDHC, QSPI - HWA_CGA_M2_CLK_SEL = 1 - Async mode, CGA PLL 2 /1 is clock
*
* Serdes Lanes vs Slot information
*  Serdes1 Lane 0 (D) - Unused
*  Serdes1 Lane 1 (C) - Unused
*  Serdes1 Lane 2 (B) - QSGMII6,QSGMII5,QSGMII10,QSGMII1 port
*  Serdes1 Lane 3 (A) - Unused
*
*  Serdes2 Lane 0 (A) - Unused
*  Serdes2 Lane 1 (B) - PCIe2 Gen3 x1
*  Serdes2 Lane 2 (C) - Unused
*  Serdes2 Lane 3 (D) - PCIe3 Gen3 x1
*
* PLL mapping: 2222_2222
*
* Serdes 1:
*  PLL mapping: 2222
*
*  SRDS_PLL_REF_CLK_SEL_S1 : 0b'01
*    SerDes 1, PLL1[160] : 0 - 100MHz for QSGMII
*    SerDes 1, PLL2[161] : 1 - 100MHz for QSGMII
*  SRDS_PLL_PD_S1 : 0b'0
*    SerDes 1, PLL1 : 0 - not power down
*    SerDes 1, PLL2 : 0 - not poewr down
*  HWA_CGA_M1_CLK_SEL[224-226] : 6 - Cluster Group A PLL 2 /2 to FMan
*
* Serdes 2:
*  PLL mapping: 2222
*  SRDS_PLL_REF_CLK_SEL_S2 : 0b'00
*    SerDes 2, PLL1[162] : 0 - 100MHz for PCIe
*    SerDes 2, PLL2[163] : 0 - 100MHz for PCIe
*  SRDS_PLL_PD_S2 : 0b'00
*    SerDes 2, PLL1 : 0 - not power down
*    SerDes 2, PLL2 : 0 - not poewr down
*  SRDS_DIV_PEX_S2 : 0b'01
*    00 - train up to max rate of 8G
*    01 - train up to max rate of 5G
*    10 - train up to max rate of 2.5G
*
* DDR clock:
* DDR_REFCLK_SEL : 1 - DDRCLK pin provides the reference clock to the DDR PLL
*
*/
 
#include <../ls1046ardb/ls1046a.rcwi>
 
SYS_PLL_RAT=6
MEM_PLL_RAT=21
CGA_PLL1_RAT=16
CGA_PLL2_RAT=14
SRDS_PRTCL_S1=0
SRDS_PRTCL_S2=0
SRDS_PLL_PD_S1=0
DDR_REFCLK_SEL=0
DDR_FDBK_MULT=2
PBI_SRC=4
IFC_MODE=0
HWA_CGA_M1_CLK_SEL=6
DRAM_LAT=1
UART_BASE=0
IRQ_OUT=1
IFC_GRP_A_EXT=0
IFC_GRP_E1_EXT=0
IFC_GRP_F_EXT=0
IFC_GRP_D_BASE=0
EC1=0
EC2=0
TVDD_VSEL=0
DVDD_VSEL=0
EVDD_VSEL=0
IIC2_EXT=0
SYSCLK_FREQ=600
HWA_CGA_M2_CLK_SEL=1
 
.pbi
// set CLK_SEL for QSPI CONFIG Register
write 0x57015c, 0x20100000
// set SCFG_SCRATCHRW1 ansd SCFG_SCRATCHRW2 for boot location ptr
write 0x570600, 0x00000000
write 0x570604, 0x40100000
.end
 
// Errta A-008850 for ddr controller for barrier transaction
#include <../ls1046ardb/cci_barrier_disable.rcw>
// Set USB PHY PLL for 100MHz
#include <../ls1046ardb/usb_phy_freq.rcw>
// Clear SerDes RxBoost on SD2 lane D
#include <../ls1046ardb/serdes_sata.rcw>
// Errata A-010477 and  A-008851 for PCI Express Gen3 link training
#include <../ls1046ardb/pex_gen3_link.rcw>
 
.pbi
// QSPI END_CFG 64 bit LE
write 0x550000, 0x000f400c
.end