/* * LS1046ARDB RCW for SerDes Protocol 0x1133_5559 * * 24G configuration -- 2 RGMII + two XFI + 2 SGMII + 3 PCIe + SATA * * Frequencies: * * Sys Clock: 100 MHz * DDR_Refclock: 100 MHz * * Core -- 1600 MHz (Mul 16) * Platform -- 600 MHz (Mul 6) * DDR -- 2100 MT/s (Mul 21) * FMan -- 700 MHz (CGA2 /2) * XFI -- 156.25 MHz (10.3125G) * SGMII -- 100 MHz (5G) * PCIE -- 100 MHz (5G) * eSDHC -- 1400 MHz (CGA2 /1) * * Hardware Accelerator Block Cluster Group A Mux Clock: * FMan - HWA_CGA_M1_CLK_SEL = 6 - Async mode, CGA PLL 2 /2 is clock * eSDHC, QSPI - HWA_CGA_M2_CLK_SEL = 1 - Async mode, CGA PLL 2 /1 is clock * * Serdes Lanes vs Slot information * Serdes1 Lane 0 (D) - XFI9, AQR107 PHY * Serdes1 Lane 1 (C) - XFI10, SFP cage * Serdes1 Lane 2 (B) - SGMII5, SGMII1 port * Serdes1 Lane 3 (A) - SGMII6, SGMII2 port * * Serdes2 Lane 0 (A) - PCIe1 Gen3 x1, Slot 1, mPCIe * Serdes2 Lane 1 (B) - PCIe2 Gen3 x1, Slot 2 * Serdes2 Lane 2 (C) - PCIe3 Gen3 x1, Slot 3 * Serdes2 Lane 3 (D) - SATA * * PLL mapping: 2211_2221 * * Serdes 1: * PLL mapping: 2211 * * SRDS_PLL_REF_CLK_SEL_S1 : 0b'01 * SerDes 1, PLL1[160] : 0 - 100MHz for SGMII and PCIe * SerDes 1, PLL2[161] : 1 - 156.25MHz for XFI * SRDS_PLL_PD_S1 : 0b'0 * SerDes 1, PLL1 : 0 - not power down * SerDes 1, PLL2 : 0 - not poewr down * HWA_CGA_M1_CLK_SEL[224-226] : 6 - Cluster Group A PLL 2 /2 to FMan * * Serdes 2: * PLL mapping: 2221 * SRDS_PLL_REF_CLK_SEL_S2 : 0b'00 * SerDes 2, PLL1[162] : 0 - 100MHz for SATA * SerDes 2, PLL2[163] : 0 - 100MHz for PCIe * SRDS_PLL_PD_S2 : 0b'00 * SerDes 2, PLL1 : 0 - not power down * SerDes 2, PLL2 : 0 - not poewr down * SRDS_DIV_PEX_S2 : 0b'01 * 00 - train up to max rate of 8G * 01 - train up to max rate of 5G * 10 - train up to max rate of 2.5G * * DDR clock: * DDR_REFCLK_SEL : 1 - DDRCLK pin provides the reference clock to the DDR PLL * */ #include %littleendian64b=1 %dont64bswapcrc=1 /* NXP CPU Part number: LS1046A SE8T1A S - 0-105C E - With Encryption 8 - LSFC 780 Balls T - CPU max Speed: 1800 MHz 1 - DDR max Speed: 2100 MHz A - Silicon Revision 1.0 Min Max Core cluster group PLL frequency 1000 1800 MHz Platform clock frequency 400 700 MHz Memory Bus Clock Frequency (DDR4) 650 1050 MHz IFC clock frequency - 100 MHz FMan 400 800 MHz */ /* Frequencies: Sys Clock: 100 MHz DDR_Refclock: 100 MHz Core 1200 MHz (Mul 12) CGA_PLL1_RAT=12 Platform 600 MHz (Mul 6) SYS_PLL_RAT=6 DDR 800 MHz (Mul 16) MEM_PLL_RAT=16 FMan 500 MHz (CGA2/2) CGA_PLL2_RAT=10, HWA_CGA_M1_CLK_SEL=6 CGA_PLL1 1200 MHz CGA_PLL2 1000 MHz QSPI CGA_PLL2 / SCFG_QSPI_CFG[CLK_SEL] = 1000 / 64 = 15.625 MHz PCIE 100 MHz (5G) ???? eSDHC 1000 MHz (CGA_PLL2/1) CGA_PLL2_RAT=10, HWA_CGA_M2_CLK_SEL=1 SCFG_QSPI_CFG[CLK_SEL] Address: 157_0000h base + 15Ch offset = 157_015Ch 0000 Divide by 256 0001 Divide by 64 (default) 0010 Divide by 32 0011 Divide by 24 0100 Divide by 20 0101 Divide by 16 0110 Divide by 12 0111 Divide by 8 */ /****************************************/ /*** System PLLs ***/ /****************************************/ SYS_PLL_RAT=6 SYSCLK_FREQ=600 // Both RCW 9F & 9E use '13' for CGA_PLL1_RAT // CGA_PLL1_RAT=16 Chris //CGA_PLL1_RAT=12 CGA_PLL1_RAT=18 // RU Jan 12, 2023 C1_PLL_SEL=0 // Chris Jan 12, 2023: You may also need to increase CGA_PLL1_RAT to 18 (0x12), // and CGA_PLL2_RAT to 14 (0x0e). SYSCLK_FREQ should stay at 600 // RCW 9F uses '10' 9E uses '12' // CGA_PLL2_RAT=14 Chris //CGA_PLL2_RAT=10 CGA_PLL2_RAT=14 // RU Jan 12, 2023 HWA_CGA_M1_CLK_SEL=6 // PLL2 div by 2 (RM, page 243) HWA_CGA_M2_CLK_SEL=1 // PLL2 clock, goes to eSDHC & QSPI flash (RM, page 243) /****************************************/ /*** SERDES ***/ /****************************************/ /* Serdes 1: * PLL mapping: 2211 * * SRDS_REFCLK_SEL_S1 SerDes1 PLL2 reference clock select * 0 SD1_REF_CLK2/SD1_REF_CLK2_B. Separate reference clocks to both PLLs of SerDes1 * 1 SD1_REF_CLK1/SD1_REF_CLK1_B. Single reference clock to both PLLs of SerDes1 * SRDS_PLL_REF_CLK_SEL_S1 : 0b'01 * SerDes 1, PLL1[160] : 0 - 100MHz for SGMII and PCIe * SerDes 1, PLL2[161] : 1 - 156.25MHz for XFI * SRDS_PLL_PD_S1 : 0b'0 * SerDes 1, PLL1 : 0 - not power down * SerDes 1, PLL2 : 0 - not poewr down * * * Serdes 2: * PLL mapping: 2221 * * SRDS_REFCLK_SEL_S2 SerDes2 PLL2 reference clock select * 0 SD2_REF_CLK2/SD2_REF_CLK2_B. Separate reference clocks to both PLLs of SerDes2 * 1 SD2_REF_CLK1/SD2_REF_CLK1_B. Single reference clock to both PLLs of SerDes2 * SRDS_PLL_REF_CLK_SEL_S2 : 0b'00 * SerDes 2, PLL1[162] : 0 - 100MHz for SATA * SerDes 2, PLL2[163] : 0 - 100MHz for PCIe * SRDS_PLL_PD_S2 : 0b'00 * SerDes 2, PLL1 : 0 - not power down * SerDes 2, PLL2 : 0 - not poewr down * SRDS_DIV_PEX_S2 : 0b'01 * 00 - train up to max rate of 8G * 01 - train up to max rate of 5G * 10 - train up to max rate of 2.5G */ // SERDES 1, not used, clocks are not connected SRDS_REFCLK_SEL_S1=1 SRDS_PLL_PD_S1=3 SRDS_PRTCL_S1=0 SRDS_PLL_REF_CLK_SEL_S1=0 SRDS_DIV_PEX_S1=0 // SERDES 2 Turned Off: // SRDS_REFCLK_SEL_S2=1 // SRDS_PLL_PD_S2=3 // SRDS_PRTCL_S2=0 // SRDS_PLL_REF_CLK_SEL_S2=0 // SRDS_DIV_PEX_S2=0 // Serdes 2 Conf for PCIe SRDS_REFCLK_SEL_S2=1 SRDS_PLL_PD_S2=0 SRDS_PRTCL_S2=34952 SRDS_PLL_REF_CLK_SEL_S2=0 SRDS_DIV_PEX_S2=0 /****************************************/ /*** DDR ***/ /****************************************/ // Both RCW 9F & 9E use '16' for MEM_PLL_RAT // MEM_PLL_RAT=21 Chris //MEM_PLL_RAT=13 // DDR PLL Clock: 1300 MHz //MEM_PLL_RAT=16 // DDR PLL Clock: 1600 MHz //MEM_PLL_RAT=16 // DDR PLL Clock: 1600 MHz MEM_PLL_RAT=21 // DDR PLL Clock: 2100 MHz RU Jan 12, 2023 //MEM_PLL_RAT=18 // DDR PLL Clock: 2100 MHz RU Jan 12, 2023 DDR_REFCLK_SEL=1 // Reference Clock: 0 - use dedicated input; 1 - use SYS_DIFF_CLK (We should use SYS_DIFF_CLK, to reduce failure nodes) DDR_FDBK_MULT=2 // Fixed at 2 DDR_RATE=0 // reserved, must be 0 (implies Divide by 2) DRAM_LAT=1 // '1' as a conservative (slow) choice if DDR timing is unknown /****************************************/ /*** USB ***/ /****************************************/ // USB_DRVVBUS // 0: USB_DRVVBUS // 1: GPIO4[29] // USB_PWRFAULT // 0: USB_PWRFAULT // 1: GPIO4[30] // SCFG_USB_REF_CLK_SELCR ??? USB_DRVVBUS=0 USB_PWRFAULT=0 /****************************************/ /*** MISC ***/ /****************************************/ // Boot Source PBI_SRC=4 BOOT_HO=0 // if set to '1' it will not boot, all cores will be in hold off // Select QSPI A QSPI B not used) //IFC_MODE=37 IFC_MODE=00 // RU Jan-18-2023, set to zero as PLB validation complains IFC_GRP_A_EXT=1 // Select QSPI_A_DATA[3] IFC_GRP_E1_EXT=0 // Needed for GPIO2[10-12] IFC_GRP_E1_BASE=1 // Needed for GPIO2[10-12] IFC_GRP_F_EXT=1 // Select QSPI_A_CS0, QSPI_A_CS1, QSPI_A_SCK, QSPI_A_DATA[0], QSPI_A_DATA[1], QSPI_A_DATA[2], (QSPI_B_CS0, QSPI_B_CS1, QSPI_B_SCK)\ // Modified CZ Nov. 15 IFC_GRP_D_EXT=2 // Select FTM6 // Need for LED1 & LED2 // Routes pin mux to GPIO2[13:15] // Added CZ Jan. 20 IFC_GRP_D_BASE=1 // HW RCW set it to zero ... // Uncommented CZ Jan. 20 IRQ_OUT=1 // Setting IRQ_BASE = 1 to identify GPIO1[23:31] as GPIO IRQ_BASE=1 IRQ_EXT=0 // I2C2/SDHC/GPIO4/FTM Pin Mux // 0 1 2 3 IIC2_EXT=0 // SPI/SDHC/GPIO Pin Mux SPI_EXT=0 SPI_BASE=0 // UART Pin Mux UART_EXT=0 // UART_BASE=5 UART_BASE=3 // CZ - Temporarily disable UART2 SDHC_BASE=0 // Changed to 0 to enable the SDHC pins SDHC_EXT=0 EM1=1 // Changed to send GPIO3[0:1] to pin mux EM2=1 EC2=1 EC1=1 /****************************************/ /*** I/O Voltages ***/ /****************************************/ TVDD_VSEL=1 // 0: 1.2 or 1.8V, 1: 2.5V 2.5V EMI2, GPIO2 DVDD_VSEL=2 // 0: 1.8V, 2: 3.3V 3.3V DUART, I2C, USB2/3, SDHC(CD/WP), FTM, EVT EVDD_VSEL=2 // 0: 1.8V, 2: 3.3V 3.3V SDHC(CLK,DAT,CMD), LPUART, FTM LVDD_VSEL=1 // 0: 1.8V, 1: 2.5V 1.8V EMI1, IRQ11, FTM, 1588 // ERROR: I2C runs on 3.3V, DDR I2C on 2.5V /****************************************/ /*** PBI ***/ /****************************************/ // everything here is big-endien ... .pbi write 0x570600, 0x00000000 write 0x570604, 0x40100000 write 0x57015C, 0x10100000 // Div 64, 1000Mhz/64=15.625Mhz (*) CZ /256 = 3.90625MHz // ^ // That bit tells it to increment the address, fucking shit // It is set after reset, if cleared here, it will keep on reading from address 0x00005000 .end /* Set up I2C3 */ .pbi write 0x57040C, 0x00000000 .end // WE DID THIS ALREADY .... #include #include // -- #include // This is what usb_phy_freq.rcw does: // It has been suggested that it is needed to make DDR work .pbi write 0x570418, 0x0000009e write 0x57041c, 0x0000009e write 0x570420, 0x0000009e .end // WTF FOR ??? #include #include /* Chris's GPIO fun ... */ /* Setup the debug port: GPIO3[17:22] (base = 0x00_0000) Offset Action -------------------- 0x0 Direction (0 = in, 1 = out) 0x4 Opendrain (0 = driven high, 1 = opendrain) 0x8 Value (0 = low, 1 = high) */ .pbi write 0x570158, 0x00000200 // Bank switch to 0x0232_0000 flush awrite 0x320000, 0x000003f0 // GPIO3[17:22] = Out awrite 0x320004, 0x00000000 // No open drain signals awrite 0x320008, 0x000003f0 // GPIO3[17:22] = 1 (DBG_Port_Value = 0x63) /* Setup the docker lines: GPIO1[23:30] (base = 0x0230_0000) */ awrite 0x300000, 0x00000154 // GPIO1[23],GPIO1[25],GPIO1[27],GPIO1[29] = Out awrite 0x300004, 0x00000000 // No open drain signals awrite 0x300008, 0x00000044 // GPIO1[23],GPIO1[27] = 0; GPIO1[25],GPIO1[29] = 1 .end /* */ /* This needs to be the last statement */ #include