volatile uint8 ADC0InitCommandList[2][4] = 
   {
      {0x00,DCMOT_ADC0_CH_INT4          ,0x00u,0x00u},   /* normal conv.[0x00]      ,Vsup sense [0xCC] , 4 clock cycles sample time [40], reserved [00]          INT4*/
      {0xC0,DCMOT_ADC0_CH_INT1          ,0x00u,0x00u},   /* end of list [0xC0]      ,bandgap  , 4 clock cycles sample time [00], reserved                        NA*/ 
   };


volatile uint16 ADC0InitResult[2] = {0u, 0u}; 


void DcMot_LldInitADC(void)
{
   ADC0TIM = 2u;         /* fbus [50 MHz]   / (2x(2 + 1)) => 8.33 MHz */
   ADC0FMT_DJM = 1u;    /* 1 - Right justified data in the conversion result list.*/
   ADC0FMT_SRES = 4u;   /* 12-bit result */
   
   ADC0CONIE_1_EOL_IE = 0u;     /* No End of list interrupt enable */

   /*InitBooster*/
   
   GDUCLK1_GBOCD = 0x17u;    /* GDU Boost Option Clock Divider    */
   GDUCLK1_GBODC = 0u;       /* GDU Boost Option Clock Duty Cycle */
   GDUBCL_GBCL = 0xF;        /* Boost Current Limit Register      */
   GDUE_GBOE = 1u;           /* enable Boost Converter            */
   
   /*Init Vsup Measure*/
   
   ADC0CTL_0_ADC_EN = 0;     /* ADC disabled*/
   ADC0CTL_1_SMOD_ACC = 1;   /* 1 -> Special access - Register write restrictions are lifted.*/
   ADC0CTL_0_ACC_CFG = 2;    /* access mode from Data Bus  */
   ADC0CTL_0_STR_SEQA = 0;   /* Store result at abort/restart */
   ADC0CTL_0_MOD_CFG = 1;    /* Trigger Mode  */

   {
      uint32 ui32Help;

      /* Justification 0303: MISRA-C:  Cast between a pointer to object and an integral type necessary */
      ui32Help = (uint32)&ADC0InitCommandList[0][0];

      ADC0CBP_0 = (uint8)((ui32Help >> 16u) & 0x0000FFu);
      ADC0CBP_1 = (uint8)((ui32Help >> 8u)  & 0x0000FFu);
      ADC0CBP_2 = (uint8)( ui32Help        & 0x0000FFu);


      ui32Help = (uint32)&ADC0InitResult[0];

      ADC0RBP_0 = (uint8)((ui32Help >> 16u) & 0x0000FFu); 
      ADC0RBP_1 = (uint8)((ui32Help >> 8u)  & 0x0000FFu);
      ADC0RBP_2 = (uint8)( ui32Help        & 0x0000FFu);
   }

   ADC0CROFF1 = 0u;  /* ADC0 Command/Result Offset registers */

   ADC0CTL_0_ADC_EN = 1u; /*ADC enabled.*/
   
   /*Prepare GDU Cyclic*/
   while (DcMot_LldOutputData.RawVsup < 409u) /*4500mV*/
   {
      /* wait until Vsup reaches the min value */

      /* clear conversion interrupt flags*/
      ADC0CONIF_0 = 0xFFu; 
      ADC0CONIF_1 = 0xFFu; 

      ADC0FLWCTL_RSTA = 1u;   /* 1 -> Restart from top of active Sequence Command List.*/

      while (ADC0CONIF_1_EOL_IF == 0u) /*PRQA S 2461*/
      {
         /*result index must match with sampling order in command sequence list (InitCSL) */
         DcMot_LldOutputData.RawVsup                           = ADC0InitResult[0];     /*Intern4 */
         DcMot_LldOutputData.RawBandgap                        = ADC0InitResult[1];     /*Bandgap */
      }
   }
   
}