;***************************************************************** ;* This stationery serves as the framework for a * ;* user application (single file, absolute assembly application) * ;* For a more comprehensive program that * ;* demonstrates the more advanced functionality of this * ;* processor, please see the demonstration applications * ;* located in the examples subdirectory of the * ;* Freescale CodeWarrior for the HC12 Program directory * ;***************************************************************** ; export symbols XDEF Entry, _Startup ; export 'Entry' symbol ABSENTRY Entry ; for absolute assembly: mark this as application entry point ; Include derivative-specific definitions INCLUDE 'derivative.inc' ROMStart EQU $4000 ; absolute address to place my code/constant data ; variable/data section ORG RAMStart ; Insert here your data definition. ; No variables for this program ; code section ORG ROMStart Entry: ; Entry point after reset _Startup: LDS #RAMEnd+1 ; initialize the stack pointer ;***************************************************************************************** ; - Initialize Port B. General purpose I/Os. all pins outputs, LEDs on all pins ;***************************************************************************************** movb #$FF,DDRB ; Load %11111111 into Port B Data ; Direction Register (all pins outputs) movb #$00,PORTB ; Load %00000000 into Port B Data ; Register (initialize all pin states low) ;***************************************************************************************** ; - Initialize Port S. General purpose I/Os. SCI0 RS232 RXD input Pin 0, TXD output pin 1, ; all others not used, set as inputs - Page 126, 128 ; Note! When SCI0 is enabled Pins 0 and 1 are under SCI control ;***************************************************************************************** clr DDRS ; Load %00000000 into Port S Data Direction ; Register(all pins inputs) movw #$FF00,PERS ; Load Port S Pull Device Enable ; Register and Port S Polarity Select ; Register with %1111111100000000 ; (pull-ups on all pins) ;***************************************************************************************** ; - Initialize the the clock generator and Phase Lock Loop for 50 Mhz ; Bus Clock frequency.(See pages 473, 474 and 486,487) ; ; SYSCLK (bus clock) is half of selected source clock, either OSCCLK ; or PLLCLK.The PLLCLK frequency is: ; PLLCLCK = 2 * OSCCLK * (SYDIV + 1) / REFDIV + 1) ; We are using a 16 Mhz crystal oscilator for OSCCLK, So if SYNDIV ; = 24 and REFDIV = 7 then PLLCLCK will be (2 * 16000000 *25) / 8 = ; 100 Mhz. PLLCLK / 2 = 50 Mhz. Bus Clock. ; From table 11-2 for 100MHz VCO clock VCOFRQ[1:0] = 11 so ; so SYNR = %11011000 = $D8 ; From table 11-3 for 2MHz REFLCK frequency REFFRQ[1:0] = 00 so ; so REFDV = %00000111 = $07 ;***************************************************************************************** movb #$FF,CRGFLG ; Clear all flags movb #$D8,SYNR ; Load "SYNR" with %11011000 movb #$07,REFDV ; Load "REFDV" with %00000111 bset PORTB,mPORTB_PB4 ; LED on brclr CRGFLG,mCRGFLG_LOCK,*+0 ; Loop until LOCK flag is cleared bset PORTB,mPORTB_PB5 ; LED on bset CLKSEL,mCLKSEL_PLLSEL ; Set "PLL Select bit" to derive system clocks from "PLLCLK" ;***************************************************************************************** ; - Initialize Real Time Interrupt for 125uS period - ; OSCLOCK / 2 = Frequency divide rate ; 16,000,000/2=8,000,000 ; 1/8,000,000=0.000125 Sec period ;***************************************************************************************** movb #$81,RTICTL ; Load "RTICTL with %10000001 (Decimal ; based divider,125uS period) bset CRGFLG,mCRGFLG_RTIF ; Clear Real Time Interrupt Flag bset CRGINT,mCRGINT_RTIE ; Enable RTI ;***************************************************************************************** ; - Initialize the SCI0 interface for 115,200 Baud Rate ; When IREN = 0, SCI Baud Rate = SCI bus clock / 16 x SBR[12-0] ; or SCI0BDH:SCI0BDL = (Bus Freq/16)/115200 = 21.70 ; 27.1 rounded = 27 = $1B ;***************************************************************************************** movb #$00,SCI0BDH ; Load SCI0BDH with %01010100, (IR disabled, 1/16 narrow pulse ; width, no prescale Hi Byte) movb #$1B,SCI0BDL ; Load SCI0BDL with decimal 27, prescale Lo byte ;(115,200 Baud Rate) clr SCI0CR1 ; Load SCI0CR1 with %00000000(Normal operation, SCI enabled ; in wait mode. Internal receiver source. One start bit,8 data ; bits, one stop bit. Idle line wakeup. No parity.) movb #$24,SCI0CR2 ; Load SCI0CR2 with %00100100(TDRE interrupts disabled. TCIE ; interrpts disabled. RIE interrupts enabled.IDLE interrupts ; disabled. Transmitter disabled, Receiver enabled, Normal ; operation, No break characters) ; (Transmitter and interrupt get enabled in SCI0_ISR) ;***************************************************************************************** ; - Initialize RTI -> UI ISR vectors - movb #$F0,INT_CFADDR ; Load "CFADDR" with %11110000 (Place RTI -> UI ; into window) movb #$01,INT_CFDATA0 ; Load "CFDATA0" with %00000001 (Set RTI CPU ; RTI ENABLED, CPU, level 1 movb #$00,INT_CFDATA1 ; Load "CFDATA1" with %00000000 (Set IRQ disabled) movb #$00,INT_CFDATA2 ; Load "CFDATA2" with %00000000 (Set XIRQ disabled) movb #$00,INT_CFDATA3 ; Load "CFDATA3" with %00000000 (Set SWI disabled) ; - Initialize ATD1 -> Enhanced Capture Timer Overflow Interrupt Vectors - movb #$D0,INT_CFADDR ; Load "CFADDR" with %11010000 (Place ATD1 -> Enhanced ; Capture Timer Overflow into window) movb #$00,INT_CFDATA0 ; Load "CFDATA0" with %00000000 (Set ATD1 disabled) movb #$00,INT_CFDATA1 ; Load "CFDATA1" with %00000000 (Set ATD0 disabled) movb #$00,INT_CFDATA2 ; Load "CFDATA2" with %00000000 (Set SCI1 disabled) movb #$01,INT_CFDATA3 ; Load "CFDATA3" with %00000001 (Set SCI0 CPU to ; SCI0 ENABLED, CPU, level 1 movb #$00,INT_CFDATA4 ; Load "CFDATA4" with %00000000 (Set SPI0 disabled) movb #$00,INT_CFDATA5 ; Load "CFDATA5" with %00000000 (Set Pulse accumulator input ; edge disabled) movb #$00,INT_CFDATA6 ; Load "CFDATA0" with %00000000 (Set Pulse accumulator A ; overflow disabled) movb #$00,INT_CFDATA7 ; Load "CFDATA0" with %00000000 (Set ECT overflow disabled) CLI ; enable interrupts mainLoop: ; LDAA #$01 ; A bit 0 = 1 ; EORA PORTB ; invert the port B state ; STAA PORTB ; put result back to port B BRA mainLoop ;************************************************************** ;* Interrupt Service Routines * ;************************************************************** XDEF SCI0_ISR SCI0_ISR: ldaa SCI0SR1 ; Load accu A with value in SCI0SR1(Read SCI0SR1 to clear "RDRF" flag) bset PORTB,mPORTB_PB2 ; LED on RTI XDEF RTI_ISR RTI_ISR: bset PORTB,mPORTB_PB1 ; LED on RTI ;************************************************************** ;* Interrupt Vectors * ;************************************************************** ORG $FFD6 DC.W SCI0_ISR ; SCI0 ISR Vector ORG $FFF0 DC.W RTI_ISR ; RTI ISR Vector ORG $FFFE DC.W Entry ; Reset Vector