Junior Contributor I
Freescale: Experienced System, SoC, and software architecture manager and individual contributor. Co-architect of MPC83xx/P1/P2 product families, OCN (On-Chip Network used in all P1-P4 products), pipelined Magenta SRS standard (used in P1-P4 memory controllers and StarCore CLASS interconnect), and XLB protocol and no-starve arbitration algorithm (used in 83xx and 52xx family). Quantitative system performance modeling using C++ and SystemC. Led development of first hardware/software PowerPC co-simulation environment (ISS with Verilog). Architected alternative instruction set and pre-silicon source-level debug solution for synthesizeable CPM. Developed bootloaders and BSPs. PuC/Hamlet synthesizable PowerPC architect. IP licensing. Led M&A technical teams. Specified PowerPC performance monitor, XLB bus protocol definition, standards development (GPON, FSAN, ATM Forum, DAVIC, PCI-SIG, MAP/TOP), Bare board, vxWorks, and MQX BSPs. Developed optimized embedded PowerPC EABI startup code. 5 patents.
Motorola Computer Group, AZ: Embedded real-time and Unix networking protocols, including Ethernet, TCP/IP, OSI transport, network management, ASN.1, and ISDN. Bare board software development: 68K, 88K, and PowerPC. StarT (*T) massively parallel processing/ supercomputing. , Common Environment, SVR3, SVR4, and AIX operating system development.
Perkin-Elmer Data Systems / Concurrent Computer Corp, NJ: Hardware design, optical disk file manager, Nexrad radar system, multi-channel demodulation. OS/32 and Unix on Interdata 8/32 and 3280 multi-processor super mini-computers.
| Solutions | 0 |
| Kudos given | 0 |
| Kudos received | 0 |
| Member Since | 09-10-2012 |