Hi Sugiyama
>1. There are status bits of DI0_CNTR_FIFO_FULL and DI0_READ_CNTR_EMPTY.
> What FIFO status does it indicate?
This FIFO is part of the DI0 synchronizer, depicted on Figure 37-39 DI's block diagram
i.MX6DQ Reference Manual
http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf
>Does this FIFO use data transfer from DMFC/Memory to DI0?
No. DMFC has not direct connection to DI0, as shown on p.33 "IPUv3H – Internal Structure"
presentation on
https://community.nxp.com/docs/DOC-100482
>2. There are status bits of DI0_READ_FIFO_FULL and DI0_READ_FIFO_EMPTY.
> What FIFO status does it indicate?
This FIFO is part of the DI0 synchronizer, depicted on Figure 37-39 DI's block diagram.
>Does this FIFO use data transfer from smart Display or DMFC/Frame buffer?
It i used for smart display, not supported in i.MX6 IPU.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
