AnsweredAssumed Answered

Explenation for HS-SETTLE  parameter in MIPI CSI D-PHY registers

Question asked by Robrecht Bisschop on Nov 9, 2017
Latest reply on Nov 13, 2017 by Qiang Li - Mpu Se

Hello,

 

I am currently working on modifying the OV5640 mipi driver so it can work for our custom camera sensor on the SABRE board. In the device tree of the sabre board there is the following configuration:

 

 

&mipi_csi {
     clock-frequency = <240000000>;
     status = "okay";
     port {
     
          mipi_sensor_ep: endpoint1 {
               remote-endpoint = <&ov5640_mipi_ep>;
               data-lanes = <2>;
               csis-hs-settle = <13>;
               csis-clk-settle = <2>;
               csis-wclk;
          };

          csi_mipi_ep: endpoint2 {
               remote-endpoint = <&csi_ep>;
          };
     };
};

 

 

I can see in the driver that the csis-hs-settle and csis-clk-settle parameter set the corresponding parameters in the  MIPI_CSI2_DPHY_CMN_CTRL  register. In the datasheet however, there is no mention what these values actually mean. Since the Ths-settle time of the receiver on the PHY is a very critical parameter to get the MIPI working i would like to know what the meaning of this value 13 is. Anybody any idea?

 

Also it is not clear to me what clock-frequency parameter exactly does. If i look into the driver, i see that this sets the mipi_clk. When i measure the clock on the mipi clk lane for the OV5640, i measure a frequency of 112MHz. So i don't understand why you would need to set the D-PHY mipi clk to 240Mhz. Does this have to be in a certain range so that the PHY can lock on the mipi clk?

 

Thanks for your help.

Outcomes