Hi, I am having a problem using the IS45S32400F-6BLA2 SDRAM 128 mb (1meg x 32 bit x 4 banks)
After setup, I run a simple RAM test writing the lease significant 24 bits into each word of the 8 mB SDRAM space.
When I read back data starting at the first SDRAM addr (0x28000000) I get:
1004 1008 100c 1010 1014 1018 101c 1000 1024 1028 102c 1030 1034 1038 103c 1020
1044 1048 104c 1050 1054 1058 105c 1040 1064 1068 106c 1070 1074 1078 107c 1060
1084 1088 108c 1090 1094 1098 109c 1080 10a4 10a8 10ac 10b0 10b4 10b8 10bc 10a0
10c4 10c8 10cc 10d0 10d4 10d8 10dc 10c0 10e4 10e8 10ec 10f0 10f4 10f8 10fc 10e0
1100 1104 1108 110c 1110 1114 1118 111c 1120 1124 1128 112c 1130 1134 1138 113c
1140 1144 1148 114c 1150 1154 1158 115c 1160 1164 1168 116c 1170 1174 1178 117c
1180 1184 1188 118c 1190 1194 1198 119c 11a0 11a4 11a8 11ac 11b0 11b4 11b8 11bc
11c0 11c4 11c8 11cc 11d0 11d4 11d8 11dc 11e0 11e4 11e8 11ec 11f0 11f4 11f8 11fc
1204 1208 120c 1210 1214 1218 121c 1200 1224 1228 122c 1230 1234 1238 123c 1220
1244 1248 124c 1250 1254 1258 125c 1240 1264 1268 126c 1270 1274 1278 127c 1260
1284 1288 128c 1290 1294 1298 129c 1280 12a4 12a8 12ac 12b0 12b4 12b8 12bc 12a0
12c4 12c8 12cc 12d0 12d4 12d8 12dc 12c0 12e4 12e8 12ec 12f0 12f4 12f8 12fc 12e0
1300 1304 1308 130c 1310 1314 1318 131c 1320 1324 1328 132c 1330 1334 1338 133c
1340 1344 1348 134c 1350 1354 1358 135c 1360 1364 1368 136c 1370 1374 1378 137c
1380 1384 1388 138c 1390 1394 1398 139c 13a0 13a4 13a8 13ac 13b0 13b4 13b8 13bc
13c0 13c4 13c8 13cc 13d0 13d4 13d8 13dc 13e0 13e4 13e8 13ec 13f0 13f4 13f8 a99595a9
Instead of 0000 0004 0008 000C 0010 etc
Looks like bit 12 is stuck on, the last word is in error, and every other 64 word block has 8 word blocks
shifted left with the first value showing in the 8th word position?
This repeats almost everywhere in SDRAM. However this pattern did not show in at least two places
0x40000 and at 0x200000 although the last byte was still in error.
I have used a similar setup on a different board layout with an MT48LC4M32B2 successfully.
Also tried reducing the EMC clock to 50 mHz - no help.
Is this a setup issue (Setup info attached) or possibly a PCB connection issue? SDRAM is a BGA package.
Thanks for any help -
Original Attachment has been moved to: Source1.cpp.zip
