eDMA problem in S32R274?

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eDMA problem in S32R274?

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taokang
Contributor III

Dear NXP engineer:
   I want to use the eDMA module of S32R274,I refrence the exmaple Example MPC5775K-DMA_Transfer S32DS ,For this sentence,as follows:
pastedImage_1.png


Why disable it ,if do as this,Will it still transfer successfuly?
Aand additionally question:Whether FlexCAN in S32R274 could use a eDMA request?
   Sincerely hope to get your help,thanks!

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martin_kovar
NXP Employee
NXP Employee

Hello,

PBRIDGE_0_CLK is derived from System Clock which is 264MHz (PLL0).

pastedImage_1.png

PBRIDGE_0_CLK is set by MC_CGM_SC_DC_3 register. DIV bits in this register are set to 3 by default, so divider is 4. This tells you that PBRIDGE clock is 66MHz (PLL0/4 ....264/4=66)

Please ignore SC_CGM_AC13 register settings. This is not related to PBRIDGE clock settings.

2) In general, this bridge allows masters to access (write and read) the slaves. So, if DMA (master) wants to access to UART (slave), this must be enabled in AIPS bridge. Please read chapter 22 in MPC5775K reference manual.

3) It could be little bit complicated. At first, check if you have correctly configured pins and if the the pins you configured are routed to UART transceiver. Second, try to send characters without DMA and check, if it works. If yes, check DMA settings. If no, there will be most probably some issue with pad settings.

Regards,

Martin

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davidtosenovjan
NXP TechSupport
NXP TechSupport

In this case apparently transfer is initiated software way thus DMA hardware request does not need to be enabled.

The eDMA requests for FlexCAN are not supported on this device.

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taokang
Contributor III

hello David:

    I need to use uart in edma way in S32R274,I refrence the exmapleExample MPC5775K UART_with_DMA S32DS ,I have some question about this example.

1:Why baud clock is 66MHz (PBRIDGE_CLK)?It seems that PBRIDGE_0_CLK is not configured,it is only configured PLL0

pastedImage_2.png

2:Why must be configured APIS_0,APIS_1?What function do they have?

pastedImage_3.png

3:I transplanted it to SR274, but did not succeed, the data did not send out from uart, do you have any good debugging advice?

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martin_kovar
NXP Employee
NXP Employee

Hello,

PBRIDGE_0_CLK is derived from System Clock which is 264MHz (PLL0).

pastedImage_1.png

PBRIDGE_0_CLK is set by MC_CGM_SC_DC_3 register. DIV bits in this register are set to 3 by default, so divider is 4. This tells you that PBRIDGE clock is 66MHz (PLL0/4 ....264/4=66)

Please ignore SC_CGM_AC13 register settings. This is not related to PBRIDGE clock settings.

2) In general, this bridge allows masters to access (write and read) the slaves. So, if DMA (master) wants to access to UART (slave), this must be enabled in AIPS bridge. Please read chapter 22 in MPC5775K reference manual.

3) It could be little bit complicated. At first, check if you have correctly configured pins and if the the pins you configured are routed to UART transceiver. Second, try to send characters without DMA and check, if it works. If yes, check DMA settings. If no, there will be most probably some issue with pad settings.

Regards,

Martin

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taokang
Contributor III

Hello Martin,

Follow your suggestion,I have used uart with edma ways to send a data .But I still have a question, Excepting EDMA that use AIPS, where there will be used AIPS?

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martin_kovar
NXP Employee
NXP Employee

Hello,

Every master must be enabled on AIPS bridge to access slave (read, write). Some of them are enabled by default, another ones must be enabled by application. Please check AIPS_MPRA and AIPS_MPRB registers.

For Master logical numbers, please check Figure3-3 and table 3-8.

pastedImage_1.png

Regards,

Martin