When testing the RAM data bus, a popular solution is the "walking-1's" test. There are several patterns read from ROM, written then in a RAM address, and then read-back. However, there is no mention of the interference of the data cache. Since when we first read the pattern from the ROM, that pattern has to be stored in the data cache. When doing the read-back operation, the processor can optimize this operation by sending the pattern from the data cache, rather then the one from the RAM address, because no modification has been done to the pattern.
For the MPC5605B is there any way to "bypass" the data cache ? Like a data cache flush or inhibition ?
Also, if instead of a predefined pattern, we calculate the value by performing shift operations, will the data cache still interfere ?