Hi, Guys
I want to use the input caputure and output compare function in MPC5634m, but the code cannot realize the functions. Can you find the fault in my code? Thank you
//input capture
#include "MPC5634M_MLQC80.h"
unsigned int i=0;
unsigned int time1;
unsigned int time2;
unsigned int shuju[8];
void pll_init_80M(void)
{
FMPLL.SYNCR.R = 0x03080030; /* Initial setting: 40 MHz for 8 MHz crystal */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for LOCK = 1 */
FMPLL.SYNCR.R = 0x03080430; /* Enable FM */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK again */
FMPLL.SYNCR.R = 0x03000430; /* Final setting: 80 MHz for 8 MHz crystal */
}
void pll_init_64M(void)
{
FMPLL.SYNCR.R = 0x03080030; /* Initial setting: 40 MHz for 8 MHz crystal */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for LOCK = 1 */
FMPLL.SYNCR.R = 0x03080430; /* Enable FM */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK again */
FMPLL.SYNCR.R = 0x16000000; /* Final value for 64 MHz: RFD=0 */
}
void initEMIOS(void)
{
EMIOS.MCR.B.GPRE= 63; /* Divide 64 MHz sysclk by 63+1 = 64 for 1MHz eMIOS clk*/
EMIOS.MCR.B.ETB = 0; /* External time base is disabled; Ch 23 drives ctr bus A */
EMIOS.MCR.B.GPREN = 1; /* Enable eMIOS clock */
EMIOS.MCR.B.GTBE = 1; /* Enable global time base */
EMIOS.MCR.B.FRZ = 0;
}
void initEMIOSch2(void)
{ /* EMIOS CH 9: Output Pulse Width Modulation */
EMIOS.CH[2].CCR.B.BSL = 0x3; /* Use internal counter */
EMIOS.CH[2].CCR.B.FEN = 1;
EMIOS.CH[2].CCR.B.EDSEL = 0; /*Single edge triggering defined by the EDPOL bit*/
EMIOS.CH[2].CCR.B.EDPOL = 0; /*Trigger on a falling edge*/
EMIOS.CH[2].CCR.B.MODE = 0x02; /* MPC551x, MPC563x: Mode is SAIC*/
SIU.PCR[181].R = 0x0500; /* Initialize pad for eMIOS chan. 2 output */
}
void EMIOS_RX_ISR(void)
{
while(EMIOS.GFR.B.F2==0){ };
time1=time2;
time2=EMIOS.CH[2].CADR.R;
shuju[i] = time2-time1;
i++;
if(i>7)
i=0;
}
void main(void)
{
pll_init_64M();
initEMIOS();
initEMIOSch2();
INTC_InstallINTCInterruptHandler(EMIOS_RX_ISR,53,10);
/* Loop forever */
for (;;)
{
}
}
//output compare
#include "MPC5634M_MLQC80.h"
void pll_init_80M(void)
{
FMPLL.SYNCR.R = 0x03080030; /* Initial setting: 40 MHz for 8 MHz crystal */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for LOCK = 1 */
FMPLL.SYNCR.R = 0x03080430; /* Enable FM */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK again */
FMPLL.SYNCR.R = 0x03000430; /* Final setting: 80 MHz for 8 MHz crystal */
}
void pll_init_64M(void)
{
FMPLL.SYNCR.R = 0x03080030; /* Initial setting: 40 MHz for 8 MHz crystal */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for LOCK = 1 */
FMPLL.SYNCR.R = 0x03080430; /* Enable FM */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK again */
FMPLL.SYNCR.R = 0x16000000; /* Final value for 64 MHz: RFD=0 */
}
void initEMIOS(void)
{
EMIOS.MCR.B.GPRE= 63; /* Divide 64 MHz sysclk by 63+1 = 64 for 1MHz eMIOS clk*/
EMIOS.MCR.B.ETB = 0; /* External time base is disabled; Ch 23 drives ctr bus A */
EMIOS.MCR.B.GPREN = 1; /* Enable eMIOS clock */
EMIOS.MCR.B.GTBE = 1; /* Enable global time base */
EMIOS.MCR.B.FRZ = 0;
}
void initEMIOSch2(void)
{ /* EMIOS CH 2: Output Pulse Width Modulation */
EMIOS.CH[2].CADR.R = 100; /*match value*/
EMIOS.CH[2].CCR.B.BSL = 0x3; /* Use internal counter */
EMIOS.CH[2].CCR.B.EDSEL = 1; /* the output flip-flop is toggled at each match*/
EMIOS.CH[2].CCR.B.EDPOL = 1; /* Polarity-leading edge sets output/trailing clears*/
EMIOS.CH[2].CCR.B.MODE = 0x03; /* MPC551x, MPC563x: Mode is SAOC */
SIU.PCR[181].R = 0x0600; /* Initialize pad for eMIOS chan. 2 output */
}
void initSIU(void)
{
SIU.PCR[187].R = 0x0203;
}
int main(void) {
volatile int i = 0;
pll_init_64M();
initEMIOS();
initEMIOSch2();
initSIU();
/* Loop forever */
for (;;)
{
SIU.GPDO[187].R = 0;
if(EMIOS.CH[2].CADR.R == EMIOS.CH[2].CCNTR.R)
{
EMIOS.CH[0].CSR.B.FLAG =1;
SIU.GPDO[187].R = 1;
}
if(EMIOS.CH[2].CADR.R == EMIOS.CH[2].CCNTR.R)
EMIOS.CH[0].CSR.B.FLAG =1;
}
}
