MQX serial driver on K70

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MQX serial driver on K70

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louiemoye
Contributor III

Hello,

I'm using MQX 4.1, CW10.6, K70 processor.  I'm trying to get the MQX Serial-device driver working on UART3.  I've enabled BSPCFG_ENABLE_TTYD, and everything seems to be initializing correctly as _io_fopen() get a valid file pointer; However, I am never seeing any activity on the serial transmit pin when I do an _io_fwrite().  I suspect a pin configuration problem.  I'm not sure how select the required pins and cannot find any clues in the MQX driver docs.  I'm using PTE4/5 for the tx/rx lines to my RS-232 transceiver.  Any help would be much appreciated.

Regards,

Louie

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5 Replies

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louiemoye
Contributor III

Daniel - BTW, your first reply helped very much.  The MUX , and PORTE_PCR16 you provided was very helpful.  

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louiemoye
Contributor III

Daniel - thanks again for the reply and info!  I stumbled upon come clues just before I left work for the day, and was able to get my serial driver working (https://community.nxp.com/thread/324752 ).  Thanks so much for sharing!  The changes I made are identical to yours, so now I know I did it right :smileyhappy:.  

Regards,

Louie

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louiemoye
Contributor III

Daniel - Thanks for the reply and the info.  I was mainly interested in a way to possibly select the configuration via the driver.  I've used Processor Expert to setup UART3 on these pins, but was hoping to be able to do it with the driver now.  If not, is there a component I can use in PE, or shall I plan to do it grammatically?

Yes, we are using a custom platform, however, our BSP was originally cloned from the K70 Tower Platform. 

Here's a dump of  PORTE_PCR16, which I understand the mux value is incorrect:

PORTE_PCR16 = 400

Pin Control Register n

Bit Field Values:
bits[ 31:25 ] = 0
ISF bits[ 24:24 ] = 0 Configured interrupt has not been detected.
bits[ 23:20 ] = 0
IRQC bits[ 19:16 ] = 0 Interrupt/DMA Request disabled.
LK bits[ 15:15 ] = 0 Pin Control Register bits [15:0] are not locked.
bits[ 14:11 ] = 0
MUX bits[ 10:8 ] = 4 Alternative 4 (chip specific).
bits[ 7:7 ] = 0
DSE bits[ 6:6 ] = 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
ODE bits[ 5:5 ] = 0 Open Drain output is disabled on the corresponding pin.
PFE bits[ 4:4 ] = 0 Passive Input Filter is disabled on the corresponding pin.
bits[ 3:3 ] = 0
SRE bits[ 2:2 ] = 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
PE bits[ 1:1 ] = 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
PS bits[ 0:0 ] = 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.

Regards,

Louie

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danielchen
NXP TechSupport
NXP TechSupport

Hi Louie:

Please check my modifications based on BSP_twrk70, I use PTE4/5 as the rx/tx pin according to your requirement

I enabled ttyd in user_config.h

and modify the  _bsp_serial_io_init function in init_gpio.c

        case 3:
            pctl = (PORT_MemMapPtr)PORTE_BASE_PTR;
            if (flags & IO_PERIPHERAL_PIN_MUX_ENABLE)
            {
                /* PTE5 as RX function (Alt.3) + drive strength */
                pctl->PCR[5] = 0 | PORT_PCR_MUX(3) | PORT_PCR_DSE_MASK;
                /* PTE4 as TX function (Alt.3) + drive strength */
                pctl->PCR[4] = 0 | PORT_PCR_MUX(3) | PORT_PCR_DSE_MASK;
            }
            if (flags & IO_PERIPHERAL_PIN_MUX_DISABLE)
            {
                /* PTE5 default */
                pctl->PCR[5] = 0;
                /* PTE4 default */
                pctl->PCR[4] = 0;
                // /*  default */
            }
            if (flags & IO_PERIPHERAL_CLOCK_ENABLE)
            {
                /* start SGI clock */
                sim->SCGC4 |= SIM_SCGC4_UART3_MASK;
            }
            if (flags & IO_PERIPHERAL_CLOCK_DISABLE)
            {
                /* stop SGI clock */
                sim->SCGC4 &= (~ SIM_SCGC4_UART3_MASK);
            }
            break;

then rebuild bsp and psp, debug, I can see the PTE4/5 setting is as below, please check whether it can work on your side or not.

pastedImage_1.png

Regards

Daniel

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535 Views
danielchen
NXP TechSupport
NXP TechSupport

Hi Louie:

Which board you are using, TWR-K70 board or your custom board?  Could you please dump your  Port E 4/5 configuration (register )value?  The below picture is for Port E 16 (debug console)

pastedImage_2.png

According to K70 reference manual, MUX value for PTE4 should be 0x3

pastedImage_1.png

Regards

Daniel

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