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iMX.6 NAND: can BCH be disabled?

Question asked by Tim Meese on May 22, 2017
Latest reply on May 24, 2017 by Yuri Muhin


We are using a custom designed SoC with a iMX6D and a NAND device with built-in 4-bit ECC. Since we are not using the NAND as a filesystem, and don't expect to incur many bit errors due to wear, we would like to use the built-in 4-bit ECC mechanism in the NAND device, and disable the BCH in the iMX6. It is thought that this would increase the read/write speed, which are currently not good. I have modified the appropriate fields in the FCB that gets written to the NAND device, and also the Layout registers. I have also modified the read and write methods so that they do not set the ECC control fields in the descriptor chains. The SoC does not boot. Is there anything that I am missing here? Does Block 0 need to be set to ECC level 1 or some edge case that I am forgetting. I've reviewed the documentation, and haven't found the case described to turn off the BCH. 


Assistance is much appreciated. Thank you. 

Best Regards,

Tim Meese