When no SPL during booting , DDR init happens in SRAM or Flash(NOR)

[adityanagal]

Hi ,

I am working on the IMX6 solo based design. In which there is no SPL used in booting process. My u-boot is in the NOR Flash. Now when the booting starts , instruction for DDR initialization get executes in SRAM  or it get executed on the NOR flash directly . I had discussion over this in two separate threads  but found different views on it . One has suggested that starting instructions get executed on the flash itself . Another suggested that , starting instructions get copied to SRAM  and then relocation happens . Please suggest.

https://community.nxp.com/thread/451730

https://community.nxp.com/thread/448636

[igorpadykov]

Hi Aditya

your question is unclear as does not describe what nor flash used: parallel or

spi. For parallel nor and qspi-nor, XIP is supported (instructions executed on the flash itself),

for usual spi - not. This depends on address of ivt instructions to execute from the image

described in Figure 8-21. Image Vector Table i.MX6DQ Reference Manual
http://cache.nxp.com/files/soft_dev_tools/doc/support_info/iMX6DQPRM.pdf

Best regards
igor
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