CPMUCOP register Flash load location on Reset S12ZVMB

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

CPMUCOP register Flash load location on Reset S12ZVMB

707 Views
rajivbandodkar
Contributor II

Hi,

Where can I find the information of location of Flash location from where some of the register bits are loaded on reset. There are other registers also available in CPMU module that have bite loaded from Flash. Are these locations accessible?  Attached photo has some of the highlighted bits.

0 Kudos
2 Replies

494 Views
lama
NXP TechSupport
NXP TechSupport

Hi,

Chapter:

1.12.1 CPMU COP and GDU GSUF configuration

 

The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the flash

configuration field byte at global address 0xFF_FE0E during the reset sequence. The GSUF bit in the GDUF register is also loaded from the Flash configuration field byte at global address 0xFF_FE0E during

the reset sequence. See Table 1-15, Table 1-16 and Table 1-17 for coding.

 

Table 1-15. Initial COP rate configuration

 

NV[2:0] in                              CR[2:0] in

FOPT Register                    CPMUCOP Register

000                                         111

001                                         110

010                                         101

011                                         100

100                                         011

101                                         010

110                                         001

111                                         000

 

Table 1-16. Initial WCOP configuration

NV[3] in                                 WCOP in

FOPT Register                    CPMUCOP Register

1                                              0

0                                              1

 

Table 1-17. Initial GSUF configuration

 

NV[7] in                                 GSUF in

FOPT Register                    GDUF Register

1                                              0

0                                              1

Best regards,

Ladislav

0 Kudos

495 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

The information is in chapter 1.12.1 CPMU COP and GDU GSUF configuration. The flash address is 0xFF_FE0E.  Please be aware that the bits loaded from Flash to CPMUCOP are inverted as you can see in table 1-15,16,17.

 

Regards,

Daniel

0 Kudos