i.MX6 IPU Interlaced Output

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i.MX6 IPU Interlaced Output

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robertspriggs
Contributor I

Hi,

I'm using a custom i/MX6DL board based on the sabre. I've had no problem setting the display port output format to 720P59.94 and 1080P59.94, but for our product we have to support interlaced formats as well.

I'm trying to set my display port output format to interlaced by adding the 'interlaced' flag to the LDB section of my device tree file:

display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <148351500>;
hactive = <1920>;
vactive = <1080>;
hback-porch = <148>;
hfront-porch = <88>;
vback-porch = <36>;
vfront-porch = <4>;
hsync-len = <44>;
vsync-len = <5>;
interlaced = <1>;

};

Firstly I get two images per screen (stacked vertically). There don't seem to be any interlace artifacts though. People's faces are purple, but other than that colours look normal.

I also get this warning what looks like about once per frame:

imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_10 = 0x00080000  

(0x00080000 == DI0_SYNC_DISP_ERR)

Any ideas whats going on?

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igorpadykov
NXP Employee
NXP Employee

Hi Robert

there may be confusion regarding supported formats:

for IPU please check 4.11.10.4 IPU Display Interface Signal Mapping i.MX6SDL Datasheet

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf

for LDB sect.40.5.1 Mapping of Input Data Busses i.MX6SDL Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

LDB uses split mode sending even pixel on one channel and odd on another,

this is used for high resolution lcds. There is no "interlaced format".

Best regards
igor
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robertspriggs
Contributor I

Hi Igor,

We are using the LDB driver, but we are not using it to drive an LVDS monitor. The display port output of the IPU connects directly to the input of an FPGA. I'm probably going to have to find a hack to make interlaced output work with the LDB driver. Can you point me to any examples of setting up the IPU for interlaced output?

EDIT: I found a patch for HDMI and LCD here Patch for iMX6 BSP to support interlaced display on HDMI and LCD interface  

I was reading through the patch and it looks like the IPUv3 and IDMAC patches should work with the version of code I have. As for hacking the LDB driver, there are a couple of things I need clarification on though. Firstly, what is the difference between IPUv3EX and IPU_V3DEX?

Also, looking at the patches specifically for HDMI and LCD, there are arrays of fb_videomode structures describing supported modes, but the LDB driver doesn't seem to have any. Why is this?

My assumption is that if I patch the IPUv3 and IDMAC drivers, I should be able to use fbset from the command line to set interlaced modes and they should work with no changes to the LDB driver...

Final EDIT: This is working now. I was right, the LDB driver worked without modification, all I needed to do was apply the patches to the IPUv3 and IDMAC driver files. I did however have to make a couple of small edits to the patch. I had to change queries of 'ipu->devtype' to 'g_ipu_hw_rev', and instances of 'IPUv3H' to 'IPU_V3H.'

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robertspriggs
Contributor I

Now that I have this working, I'm wondering why I can't change to/from interlaced using 'fbset -laced true/false.' The only way I can change to or from interlaced modes is by recompiling the device tree with the new settings.

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tengri
Contributor IV

Dear Robert,

I am also working to get the interlace output mode working on IMX6Q but through LCD interface. I have to stick with kernel 4.1.15 for this and by comparing the same patch for 3.14.52 (IDMAC and IPU changes) I made modifications to the relevant files. However the display output does not look good as expected. The mode I need is LCD 1440x480i@60. Could you please tell me to which kernel you applied these changes and exactly point out what those changes are ?

Thanks in Advance

Anuradha

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