About core 0 and core 1 for MPC5675K

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About core 0 and core 1 for MPC5675K

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Contributor III

Hi,everybody :

        I have a question about cores for MPC5675K . After I config both  cores , I want to make full use of the both cores ,but I don't know how to use semaphore.  I cann't understand what's the role of  16 hardware-enforced gates in a dual-processor configuration. What's the difference of the 16 hardware-enforced gates?

      In practice , I write data to  the buffer in core 0,and I want to clear the buffer in core 1,but I don't know how to operate it . Can you help me and give me a example about how to operate core 0 and core 1 about  commom data  ?

 

 

                                                                                                                                                            Thanks

                                                                                                                                                            Yao,Xiao

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martin_kovar
NXP Employee
NXP Employee

Hello,

please check this application note:

http://cache.nxp.com/assets/documents/data/en/application-notes/AN4805.pdf?fsrch=1&sr=2&pageNum=1 

I have also created simple example for MPC5775K, it should be helpful for you:

https://community.nxp.com/docs/DOC-329941 

If you have any other question, please feel free to write me back.

Regards,

Martin

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