IMX6SX eMMC DDR with 8 bits bus problem

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IMX6SX eMMC DDR with 8 bits bus problem

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LPs
Contributor III

Hi all,

  i'm struggling with my IMX6SX based platform.

I'm using Yocto with kernel 3.14.28+g91cf351.

On my device I monted a eMMC 4.41 compliance and I'm able to make it working with DDR and 4 bits data bus.

I'm trying to enable 8bit data bus but I found out that the kernel fails to request that type of bus and switch back automatically to 4 bits.

Into dts bus-width is correctly set to 8.

I found out that the kernel drvier receive error -84 into data.err when try top read CSD data using function mmc_send_cxd_data (code in mmc_ops.c) called by mmc_init_card (in mmc.c) where the DDR wide bus activiation is performed (around line  1642).

Are there known bugs on this matter?

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LPs
Contributor III

I finally got it: it was a problem on the mounting of my custom board that can mount SD card and eMMC. Data6 and data7 was thightened to VSS.

View solution in original post

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LPs
Contributor III

I finally got it: it was a problem on the mounting of my custom board that can mount SD card and eMMC. Data6 and data7 was thightened to VSS.

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igorpadykov
NXP Employee
NXP Employee

Hi LP

is it working in 8 bit non-ddr mode, are you able to boot in this

mode and successfully work in uboot ? One can check waveforms of data lines

with oscilloscope and try this part on i.MX6SX Sabre SD board using U4 eMMC Footprint.

Note for ddr mode may be necessary to tweak MMC_DLL_DLY values please check 

eMMC DDR mode 

Best regards
igor
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LPs
Contributor III

What I'm seeing is that:

  1. mmc_send_cxd_data is colled by driver to check 8bit mode
  2. CMD 8 (MMC_SEND_EXT_CSD) is sent
  3. After mmc_wait_for_req returns: cmd.error = 0 (OK) and data.error=-84 which is my problem
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igorpadykov
NXP Employee
NXP Employee

what bsp used in the case, could you try to reproduce issue with

nxp official L3.14.28 bsp on i.MX6SX Sabre SD board

linux-2.6-imx.git - Freescale i.MX Linux Tree 

Best regards
igor

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LPs
Contributor III

Hi Igor,

    I set fuses to start at 1 bit. So U-Boot uses 8 bit mode, but I reall don't know if it uses DDR mode, I think it is.

All is loaded correctly and kernel is loaded and launched, but It continuously fails to set up DDR 8 bit mode, wit the error I reported.

I cannot check different BOOT configuration, I'm on my final board design and only fuses are available.

It smell like A9 communication with eMMC is failing for something like timeout, but, as you probabl knows, it is hard to debug the kernel....

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igorpadykov
NXP Employee
NXP Employee

Hi LP

could you try latest L4.1.15 kernel

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/?h=imx_4.1.15_1.0.0_ga

Best regards
igor

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