i.MX6soloX issue of accessing TCM

[moritoyujiro]

I'm using MX6SX SABRE SDB(i.MX6soloX) and L3.14.52
I can read/write SRC_SCR register by memtool

root@imx6sxsabresd:~# memtool -32 0x020d8000 1
Reading 0x1 count starting at address 0x020D8000

0x020D8000: A0480538

But try to access TCML address, system to hung

root@imx6sxsabresd:~# memtool -32 0x007f8000 1
Reading 0x1 count starting at add

Though set to enable all clocks(CCM_CCGR0-6), I got the same result
How can I access to TCM from Linux?

[moritoyujiro]

I appreciate for your replies

Of course I followed "Steps for reloading code on i.MX 6SoloX", but I couldn't access TCM
I found the way to access TCM

1. Replace uboot environment variable
Replace fdt_file from imx6sx-sdb.dtb to imx6sx-sdb-m4.dtb

=> setenv fdt_file imx6sx-sdb-m4.dtb
=> saveenv
Saving Environment to MMC...
Writing to MMC(2)... done
=> reset
resetting ...

2. Boot M4 by bootaux command

=> bootaux 0x7F8000
## Starting auxiliary core at 0x007F8000 ...

Without any code loading
Probably the M4 core is running incorrectly

3. Boot Linux

=> run bootcmd

Now, I can access TCML/U

root@imx6sxsabresd:~# memtool -32 0x007f8000 1
Reading 0x1 count starting at address 0x007F8000

0x007F8000: xxxxxxxx

root@imx6sxsabresd:~# memtool -32 0x00800000 1
Reading 0x1 count starting at address 0x00800000

0x00800000: xxxxxxxx

Isn't there any lack documentation of to activate the M4 core like fdt_file replacement?

Regards

[Yuri]

Hello,

  please check supported by memtool registers. 

Accessing raw memory addresses on i.MX6 SoloX while running Linus on A9-core 

Regards,

Yuri.

[RossMcLuckie]

The TCM is part of the M4 platform, so the M4 platform itself needs to be enabled before the TCM memory can be accessed, you might want to start here -

http://www.nxp.com/assets/documents/data/en/application-notes/AN5317.pdf 

Regards

Ross

[gary_bisson]

Hi,

Is a firmware running on the M4 side when you try to access the TCM?

Have you tried accessing the TCM from U-Boot before starting the M4?

It is most likely due to the Resource Domain Controller (RDC) which might only allow the M4 to access this memory.

Regards,

Gary