Re: PCIe BAR length limit
Based on the imx_3.0.35.4.0 FSL Linux BSP release, the layout of the 16MB address space of PCIe RC is listed below:
* i.MX6 defines 16MB in the AXI address map for PCIe.
*
* That address space excepted the pcie registers is
* split and defined into different regions by iATU,
* with sizes and offsets as follows:
*
* RC:
* 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
* 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
* 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + MSI + Registers
*
0x0110_0000 ~ 0x01EF_FFFF 14MB would be used for MEM allocation.
But the "IORESOURCE_SIZEALIGN" would be used during the Linux PCI/PCIe subsystem probe/scan the bus and allocate the resources.
If the 8MB MEM is required, the start address 0x0180_0000 would be used by Linux PCI/PCIe subsystem, trying to
allocate the 8MB MEM space (0x0180_0000 ~ 0x01FF_FFFF), this operation would be failed.
Because that the limitation of the MEM space of iMX6 PCIe RC is
* 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
So, One method to allocate the 8MB(the biggest size of IO/MEM space) MEM space on iMX6 PCIe RC.
Adjust the layout of the 16MB address space of iMX6 PCIe RC, like this:
* RC:
* 0x0100_0000 --- 0x01DF_FFFF 14MB IORESOURCE_MEM
* 0x01E0_0000 --- 0x01EF_FFFF 1MB IORESOURCE_IO
* 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + MSI + Registers
The 8MB space would be allocated from 0x0100_0000 ~ 0x017F_FFFF.
Based two imx6 platforms, one is used as RC, the other is used as RC.
Here is the test log at RC side:
iMX6 PCIe PCIe RC mode imx_pcie_pltfm_probe entering.
PCIE: imx_pcie_pltfm_probe start link up.
IMX PCIe port: link up.
PCI: bus0: Fast back to back transfers disabled
PCI: bus1: Fast back to back transfers disabled
pci 0000:00:00.0: BAR 8: assigned [mem 0x01000000-0x017fffff]
pci 0000:00:00.0: BAR 0: assigned [mem 0x01800000-0x018fffff 64bit pref]
pci 0000:00:00.0: BAR 0: set to [mem 0x01800000-0x018fffff 64bit pref] (PCI address [0x1800000-0x18fffff])
pci 0000:00:00.0: BAR 9: assigned [mem 0x01900000-0x019fffff pref]
pci 0000:00:00.0: BAR 6: assigned [mem 0x01a00000-0x01a0ffff pref]
pci 0000:00:00.0: BAR 7: assigned [io 0x1e00000-0x1e00fff]
pci 0000:01:00.0: BAR 0: assigned [mem 0x01000000-0x017fffff]
pci 0000:01:00.0: BAR 0: set to [mem 0x01000000-0x017fffff] (PCI address [0x1000000-0x17fffff])
pci 0000:01:00.0: BAR 6: assigned [mem 0x01900000-0x0190ffff pref]
pci 0000:01:00.0: BAR 2: assigned [io 0x1e00000-0x1e00fff]
pci 0000:01:00.0: BAR 2: set to [io 0x1e00000-0x1e00fff] (PCI address [0x1e00000-0x1e00fff])
pci 0000:01:00.0: BAR 3: assigned [mem 0x01910000-0x019100ff pref]
pci 0000:01:00.0: BAR 3: set to [mem 0x01910000-0x019100ff pref] (PCI address [0x1910000-0x19100ff])
pci 0000:00:00.0: PCI bridge to [bus 01-01]
pci 0000:00:00.0: bridge window [io 0x1e00000-0x1e00fff]
pci 0000:00:00.0: bridge window [mem 0x01000000-0x017fffff]
pci 0000:00:00.0: bridge window [mem 0x01900000-0x019fffff pref]
Based on the imx_3.0.35.4.0 release, attach the patch
