i.MX6UL EIM access when EIM memory region is set to uncacheable.

[satoshishimoda]

Hi community,

Our customer have a question about i.MX6UL EIM access.

[Q1]

According to i.MX6 maximum EIM burst length and performance , EIM burst length is affected by the ARM instruction.

So they think that EIM execute single access (not burst access) even though it is synchronous mode if EIM memory region is set to uncacheable (L1/L2 cache) and if ARM issue single LOAD/STORE instruction to EIM memory region.

Is their understanding correct?

[Q2]

Do you know how memory attribute of EIM memory region set to uncacheable?

Best Regards,

Satoshi Shimoda

[art]

First of all, I'm sorry for so delayed reply, I needed some time to collect all information available.

Q1. Is their understanding correct?

A1. Yes, the understanding is correct.

Q2. Do you know how memory attribute of EIM memory region set to uncacheable?

A2. This can be done by the corresponding setup of MMU at very eraly stage of system boot.

Have a great day,
Artur

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[satoshishimoda]

Hi community,

Would you let me know the status to this post?

Our customer have to provide a working sample to a end customer by Sep 1st, so please give us your reply ASAP.

Best Regards,

Satoshi Shimoda

[satoshishimoda]

Hi community,

Would you let me know your status?

Confirming to expert team?

Our customer have to provide their working sample today in JST (UTC +9), so please give us your status or reply ASAP.

Best Regards,

Satoshi Shimoda

[satoshishimoda]

Hi Community,

Our customer found the following post.

Synchronous Burst Mode 

According to the above post, sequential read with address increment was happen even though the original poster wants to do burst access.

Our customer understand sequential read is one of the single access (single access * number of times = sequential access).

So they think single access is possible with ARM instruction or other method.

Best Regards,

Satoshi Shimoda