IMX6Q change to 32bit 1GB DDR3

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

IMX6Q change to 32bit 1GB DDR3

874 Views
jiejia
Contributor III

为了降低布线的难度,我们想只使用2片DDR3。想请问下,IMX6Q支持32bit的DDR3吗?如果支持的话,DRAM_CS0和DRAM_CS1要如何接线呢?

Labels (2)
0 Kudos
6 Replies

639 Views
igorpadykov
NXP Employee
NXP Employee

Q: IMX6Q support 32bit of DDR3 do? If supported, DRAM_CS0 and DRAM_CS1 to how to wire it?

A: yes, please check sect.3.3 DDR connection information

i.MX6 System Development User’s Guide

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

For 64bit bus connect DRAM_CS0 and DRAM_CS1 together

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos

639 Views
jiejia
Contributor III

Hi,igor

  In mx6q sabresd borad, there are 4 ddr3. In my imx6q borad, I want to use 2 DDR3(32bit bus). Would it be ok?

For 32bit bus, should I connect the 2 ddr3 to DRAM_CS0  or      connect the 2 ddr3 to DRAM_CS0 and DRAM_CS1?

How to change u-boot to make it work?

0 Kudos

639 Views
igorpadykov
NXP Employee
NXP Employee

2 DDR3(32bit bus) would it be ok, for 32bit bus connect the 2 ddr3 to DRAM_CS0 and DRAM_CS1

~igor

0 Kudos

639 Views
jiejia
Contributor III

I saw this article: Calibration of i.mx6 32bit bus DDR3 with 2 CS 

At the end:We do not have such tool if memories populated on CSD1 are NOT “mirrored” with the memories populated on CSD0.  What does "mirrored" means?  

0 Kudos

639 Views
igorpadykov
NXP Employee
NXP Employee

“mirrored” means the identical topology and trace length for CSD1 memory side.

0 Kudos

639 Views
jiejia
Contributor III

If the DDR memory devices are populated on CSD0, Would it be ok? It seems very strict while the 2 DDR memory devices are populated on CSD0 and CSD2.

0 Kudos