We have custom board with a Vybrid controller and LPDDR2 Memory (IS43LD16640A).
We recently managed to get it working with the DRAM clock running at 400 MHz (WL=3, RL=6), but due to power concerns, we need to clock it down to 200 MHz (WL=2, RL=4). Both the MCU and DRAM are running from the same clock (PLL1pfd3), the resulting MCU frequency will be 198MHz. Both setups use burst length (BL) 4.
Assuming this would be an easy task, we simply updated the DRAM controller timings and hoped for the best. Not surprisingly, this did not work.
Using a JLINK-debugger, we loaded the DRAM using a functional setup (running at 400 MHz), and then immediately reset the MCU and initialized the DRAM controller with the experimental setup (200 MHz). From this we were able to read back the pattern written, indicating that nothing is wrong with the read-operation.
Next we wrote an ant-pattern to the same region we just read. When reading it back, we observed that the first two bytes of every other burst were wrong.
We have previously observed that a 32bit write produces the following result:
write -> readback 0x8000_0000 -> 0x0000_aaaa 0x4000_0000 -> 0x0000_aaaa 0x2000_0000 -> 0x0000_aaaa 0x1000_0000 -> 0x0000_aaaa [...] 0x0008_0000 -> 0x0000_aaaa 0x0004_0000 -> 0x0000_aaaa 0x0002_0000 -> 0x0000_aaaa 0x0001_0000 -> 0x0000_aaaa 0x0000_8000 -> 0x8000_aaaa 0x0000_4000 -> 0x4000_aaaa 0x0000_2000 -> 0x2000_aaaa 0x0000_1000 -> 0x1000_aaaa [...] 0x0000_0008 -> 0x0008_aaaa 0x0000_0004 -> 0x0004_aaaa 0x0000_0002 -> 0x0002_aaaa 0x0000_0001 -> 0x0001_aaaa
It seems that the missing two bytes "flow over" to the next 32-bit word:
(gdb) x/16b addr 0x80000000: 0x00 0x00 0x55 0x55 0x55 0x55 0x00 0x80 0x80000008: 0xaa 0xaa 0xaa 0xaa 0xaa 0xaa 0x00 0x55 (gdb) p/x *addr $59 = 0x55550000 (gdb) set *addr = 0xaabbccdd (gdb) p/x *addr $60 = 0xccdd0000 (gdb) x/16b addr 0x80000000: 0x00 0x00 0xdd 0xcc 0xbb 0xaa 0x00 0x80 0x80000008: 0xaa 0xaa 0xaa 0xaa 0xaa 0xaa 0x00 0x55
We are therefore wondering: What parameters do we specifically need to change when changing the DRAM clock from 400MHz to 200 MHz?
Following is a diff between the functional 400MHz setup, and the experimental 200 MHz setup: